ARMInstrFormats.td revision 205218
1//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<5> val> { 19 bits<5> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def LdStExFrm : Format<28>; 37 38def ArithMiscFrm : Format<11>; 39def ExtFrm : Format<12>; 40 41def VFPUnaryFrm : Format<13>; 42def VFPBinaryFrm : Format<14>; 43def VFPConv1Frm : Format<15>; 44def VFPConv2Frm : Format<16>; 45def VFPConv3Frm : Format<17>; 46def VFPConv4Frm : Format<18>; 47def VFPConv5Frm : Format<19>; 48def VFPLdStFrm : Format<20>; 49def VFPLdStMulFrm : Format<21>; 50def VFPMiscFrm : Format<22>; 51 52def ThumbFrm : Format<23>; 53 54def NEONFrm : Format<24>; 55def NEONGetLnFrm : Format<25>; 56def NEONSetLnFrm : Format<26>; 57def NEONDupFrm : Format<27>; 58 59def MiscFrm : Format<29>; 60def ThumbMiscFrm : Format<30>; 61 62// Misc flags. 63 64// the instruction has a Rn register operand. 65// UnaryDP - Indicates this is a unary data processing instruction, i.e. 66// it doesn't have a Rn operand. 67class UnaryDP { bit isUnaryDataProc = 1; } 68 69// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 70// a 16-bit Thumb instruction if certain conditions are met. 71class Xform16Bit { bit canXformTo16Bit = 1; } 72 73//===----------------------------------------------------------------------===// 74// ARM Instruction flags. These need to match ARMInstrInfo.h. 75// 76 77// Addressing mode. 78class AddrMode<bits<4> val> { 79 bits<4> Value = val; 80} 81def AddrModeNone : AddrMode<0>; 82def AddrMode1 : AddrMode<1>; 83def AddrMode2 : AddrMode<2>; 84def AddrMode3 : AddrMode<3>; 85def AddrMode4 : AddrMode<4>; 86def AddrMode5 : AddrMode<5>; 87def AddrMode6 : AddrMode<6>; 88def AddrModeT1_1 : AddrMode<7>; 89def AddrModeT1_2 : AddrMode<8>; 90def AddrModeT1_4 : AddrMode<9>; 91def AddrModeT1_s : AddrMode<10>; 92def AddrModeT2_i12: AddrMode<11>; 93def AddrModeT2_i8 : AddrMode<12>; 94def AddrModeT2_so : AddrMode<13>; 95def AddrModeT2_pc : AddrMode<14>; 96def AddrModeT2_i8s4 : AddrMode<15>; 97 98// Instruction size. 99class SizeFlagVal<bits<3> val> { 100 bits<3> Value = val; 101} 102def SizeInvalid : SizeFlagVal<0>; // Unset. 103def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 104def Size8Bytes : SizeFlagVal<2>; 105def Size4Bytes : SizeFlagVal<3>; 106def Size2Bytes : SizeFlagVal<4>; 107 108// Load / store index mode. 109class IndexMode<bits<2> val> { 110 bits<2> Value = val; 111} 112def IndexModeNone : IndexMode<0>; 113def IndexModePre : IndexMode<1>; 114def IndexModePost : IndexMode<2>; 115def IndexModeUpd : IndexMode<3>; 116 117// Instruction execution domain. 118class Domain<bits<2> val> { 119 bits<2> Value = val; 120} 121def GenericDomain : Domain<0>; 122def VFPDomain : Domain<1>; // Instructions in VFP domain only 123def NeonDomain : Domain<2>; // Instructions in Neon domain only 124def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 125 126//===----------------------------------------------------------------------===// 127 128// ARM special operands. 129// 130 131// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 132// register whose default is 0 (no register). 133def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 134 (ops (i32 14), (i32 zero_reg))> { 135 let PrintMethod = "printPredicateOperand"; 136} 137 138// Conditional code result for instructions whose 's' bit is set, e.g. subs. 139def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 140 let PrintMethod = "printSBitModifierOperand"; 141} 142 143// Same as cc_out except it defaults to setting CPSR. 144def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 145 let PrintMethod = "printSBitModifierOperand"; 146} 147 148// ARM special operands for disassembly only. 149// 150 151def cps_opt : Operand<i32> { 152 let PrintMethod = "printCPSOptionOperand"; 153} 154 155def msr_mask : Operand<i32> { 156 let PrintMethod = "printMSRMaskOperand"; 157} 158 159// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. 160// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. 161def neg_zero : Operand<i32> { 162 let PrintMethod = "printNegZeroOperand"; 163} 164 165//===----------------------------------------------------------------------===// 166 167// ARM Instruction templates. 168// 169 170class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 171 Format f, Domain d, string cstr, InstrItinClass itin> 172 : Instruction { 173 let Namespace = "ARM"; 174 175 // TSFlagsFields 176 AddrMode AM = am; 177 bits<4> AddrModeBits = AM.Value; 178 179 SizeFlagVal SZ = sz; 180 bits<3> SizeFlag = SZ.Value; 181 182 IndexMode IM = im; 183 bits<2> IndexModeBits = IM.Value; 184 185 Format F = f; 186 bits<5> Form = F.Value; 187 188 Domain D = d; 189 bits<2> Dom = D.Value; 190 191 // 192 // Attributes specific to ARM instructions... 193 // 194 bit isUnaryDataProc = 0; 195 bit canXformTo16Bit = 0; 196 197 let Constraints = cstr; 198 let Itinerary = itin; 199} 200 201class Encoding { 202 field bits<32> Inst; 203} 204 205class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 206 Format f, Domain d, string cstr, InstrItinClass itin> 207 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 208 209// This Encoding-less class is used by Thumb1 to specify the encoding bits later 210// on by adding flavors to specific instructions. 211class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 212 Format f, Domain d, string cstr, InstrItinClass itin> 213 : InstTemplate<am, sz, im, f, d, cstr, itin>; 214 215class PseudoInst<dag oops, dag iops, InstrItinClass itin, 216 string asm, list<dag> pattern> 217 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 218 "", itin> { 219 let OutOperandList = oops; 220 let InOperandList = iops; 221 let AsmString = asm; 222 let Pattern = pattern; 223} 224 225// Almost all ARM instructions are predicable. 226class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 227 IndexMode im, Format f, InstrItinClass itin, 228 string opc, string asm, string cstr, 229 list<dag> pattern> 230 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 231 let OutOperandList = oops; 232 let InOperandList = !con(iops, (ops pred:$p)); 233 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 234 let Pattern = pattern; 235 list<Predicate> Predicates = [IsARM]; 236} 237// A few are not predicable 238class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 239 IndexMode im, Format f, InstrItinClass itin, 240 string opc, string asm, string cstr, 241 list<dag> pattern> 242 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 243 let OutOperandList = oops; 244 let InOperandList = iops; 245 let AsmString = !strconcat(opc, asm); 246 let Pattern = pattern; 247 let isPredicable = 0; 248 list<Predicate> Predicates = [IsARM]; 249} 250 251// Same as I except it can optionally modify CPSR. Note it's modeled as 252// an input operand since by default it's a zero register. It will 253// become an implicit def once it's "flipped". 254class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 255 IndexMode im, Format f, InstrItinClass itin, 256 string opc, string asm, string cstr, 257 list<dag> pattern> 258 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 259 let OutOperandList = oops; 260 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 261 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); 262 let Pattern = pattern; 263 list<Predicate> Predicates = [IsARM]; 264} 265 266// Special cases 267class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 268 IndexMode im, Format f, InstrItinClass itin, 269 string asm, string cstr, list<dag> pattern> 270 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 271 let OutOperandList = oops; 272 let InOperandList = iops; 273 let AsmString = asm; 274 let Pattern = pattern; 275 list<Predicate> Predicates = [IsARM]; 276} 277 278class AI<dag oops, dag iops, Format f, InstrItinClass itin, 279 string opc, string asm, list<dag> pattern> 280 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 281 opc, asm, "", pattern>; 282class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 283 string opc, string asm, list<dag> pattern> 284 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 285 opc, asm, "", pattern>; 286class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 287 string asm, list<dag> pattern> 288 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 289 asm, "", pattern>; 290class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 291 string opc, string asm, list<dag> pattern> 292 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 293 opc, asm, "", pattern>; 294 295// Ctrl flow instructions 296class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 297 string opc, string asm, list<dag> pattern> 298 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 299 opc, asm, "", pattern> { 300 let Inst{27-24} = opcod; 301} 302class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 303 string asm, list<dag> pattern> 304 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 305 asm, "", pattern> { 306 let Inst{27-24} = opcod; 307} 308class ABXIx2<dag oops, dag iops, InstrItinClass itin, 309 string asm, list<dag> pattern> 310 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin, 311 asm, "", pattern>; 312 313// BR_JT instructions 314class JTI<dag oops, dag iops, InstrItinClass itin, 315 string asm, list<dag> pattern> 316 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 317 asm, "", pattern>; 318 319 320// Atomic load/store instructions 321 322class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 323 string opc, string asm, list<dag> pattern> 324 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 325 opc, asm, "", pattern> { 326 let Inst{27-23} = 0b00011; 327 let Inst{22-21} = opcod; 328 let Inst{20} = 1; 329 let Inst{11-0} = 0b111110011111; 330} 331class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 332 string opc, string asm, list<dag> pattern> 333 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 334 opc, asm, "", pattern> { 335 let Inst{27-23} = 0b00011; 336 let Inst{22-21} = opcod; 337 let Inst{20} = 0; 338 let Inst{11-4} = 0b11111001; 339} 340 341// addrmode1 instructions 342class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 343 string opc, string asm, list<dag> pattern> 344 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 345 opc, asm, "", pattern> { 346 let Inst{24-21} = opcod; 347 let Inst{27-26} = {0,0}; 348} 349class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 350 string opc, string asm, list<dag> pattern> 351 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 352 opc, asm, "", pattern> { 353 let Inst{24-21} = opcod; 354 let Inst{27-26} = {0,0}; 355} 356class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 357 string asm, list<dag> pattern> 358 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 359 asm, "", pattern> { 360 let Inst{24-21} = opcod; 361 let Inst{27-26} = {0,0}; 362} 363class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin, 364 string opc, string asm, list<dag> pattern> 365 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin, 366 opc, asm, "", pattern>; 367 368 369// addrmode2 loads and stores 370class AI2<dag oops, dag iops, Format f, InstrItinClass itin, 371 string opc, string asm, list<dag> pattern> 372 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 373 opc, asm, "", pattern> { 374 let Inst{27-26} = {0,1}; 375} 376 377// loads 378class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 379 string opc, string asm, list<dag> pattern> 380 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 381 opc, asm, "", pattern> { 382 let Inst{20} = 1; // L bit 383 let Inst{21} = 0; // W bit 384 let Inst{22} = 0; // B bit 385 let Inst{24} = 1; // P bit 386 let Inst{27-26} = {0,1}; 387} 388class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 389 string asm, list<dag> pattern> 390 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 391 asm, "", pattern> { 392 let Inst{20} = 1; // L bit 393 let Inst{21} = 0; // W bit 394 let Inst{22} = 0; // B bit 395 let Inst{24} = 1; // P bit 396 let Inst{27-26} = {0,1}; 397} 398class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 399 string opc, string asm, list<dag> pattern> 400 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 401 opc, asm, "", pattern> { 402 let Inst{20} = 1; // L bit 403 let Inst{21} = 0; // W bit 404 let Inst{22} = 1; // B bit 405 let Inst{24} = 1; // P bit 406 let Inst{27-26} = {0,1}; 407} 408class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 409 string asm, list<dag> pattern> 410 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 411 asm, "", pattern> { 412 let Inst{20} = 1; // L bit 413 let Inst{21} = 0; // W bit 414 let Inst{22} = 1; // B bit 415 let Inst{24} = 1; // P bit 416 let Inst{27-26} = {0,1}; 417} 418 419// stores 420class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 421 string opc, string asm, list<dag> pattern> 422 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 423 opc, asm, "", pattern> { 424 let Inst{20} = 0; // L bit 425 let Inst{21} = 0; // W bit 426 let Inst{22} = 0; // B bit 427 let Inst{24} = 1; // P bit 428 let Inst{27-26} = {0,1}; 429} 430class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 431 string asm, list<dag> pattern> 432 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 433 asm, "", pattern> { 434 let Inst{20} = 0; // L bit 435 let Inst{21} = 0; // W bit 436 let Inst{22} = 0; // B bit 437 let Inst{24} = 1; // P bit 438 let Inst{27-26} = {0,1}; 439} 440class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 441 string opc, string asm, list<dag> pattern> 442 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 443 opc, asm, "", pattern> { 444 let Inst{20} = 0; // L bit 445 let Inst{21} = 0; // W bit 446 let Inst{22} = 1; // B bit 447 let Inst{24} = 1; // P bit 448 let Inst{27-26} = {0,1}; 449} 450class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 451 string asm, list<dag> pattern> 452 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 453 asm, "", pattern> { 454 let Inst{20} = 0; // L bit 455 let Inst{21} = 0; // W bit 456 let Inst{22} = 1; // B bit 457 let Inst{24} = 1; // P bit 458 let Inst{27-26} = {0,1}; 459} 460 461// Pre-indexed loads 462class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin, 463 string opc, string asm, string cstr, list<dag> pattern> 464 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 465 opc, asm, cstr, pattern> { 466 let Inst{20} = 1; // L bit 467 let Inst{21} = 1; // W bit 468 let Inst{22} = 0; // B bit 469 let Inst{24} = 1; // P bit 470 let Inst{27-26} = {0,1}; 471} 472class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin, 473 string opc, string asm, string cstr, list<dag> pattern> 474 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 475 opc, asm, cstr, pattern> { 476 let Inst{20} = 1; // L bit 477 let Inst{21} = 1; // W bit 478 let Inst{22} = 1; // B bit 479 let Inst{24} = 1; // P bit 480 let Inst{27-26} = {0,1}; 481} 482 483// Pre-indexed stores 484class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin, 485 string opc, string asm, string cstr, list<dag> pattern> 486 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 487 opc, asm, cstr, pattern> { 488 let Inst{20} = 0; // L bit 489 let Inst{21} = 1; // W bit 490 let Inst{22} = 0; // B bit 491 let Inst{24} = 1; // P bit 492 let Inst{27-26} = {0,1}; 493} 494class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin, 495 string opc, string asm, string cstr, list<dag> pattern> 496 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 497 opc, asm, cstr, pattern> { 498 let Inst{20} = 0; // L bit 499 let Inst{21} = 1; // W bit 500 let Inst{22} = 1; // B bit 501 let Inst{24} = 1; // P bit 502 let Inst{27-26} = {0,1}; 503} 504 505// Post-indexed loads 506class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin, 507 string opc, string asm, string cstr, list<dag> pattern> 508 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 509 opc, asm, cstr,pattern> { 510 let Inst{20} = 1; // L bit 511 let Inst{21} = 0; // W bit 512 let Inst{22} = 0; // B bit 513 let Inst{24} = 0; // P bit 514 let Inst{27-26} = {0,1}; 515} 516class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin, 517 string opc, string asm, string cstr, list<dag> pattern> 518 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 519 opc, asm, cstr,pattern> { 520 let Inst{20} = 1; // L bit 521 let Inst{21} = 0; // W bit 522 let Inst{22} = 1; // B bit 523 let Inst{24} = 0; // P bit 524 let Inst{27-26} = {0,1}; 525} 526 527// Post-indexed stores 528class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin, 529 string opc, string asm, string cstr, list<dag> pattern> 530 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 531 opc, asm, cstr,pattern> { 532 let Inst{20} = 0; // L bit 533 let Inst{21} = 0; // W bit 534 let Inst{22} = 0; // B bit 535 let Inst{24} = 0; // P bit 536 let Inst{27-26} = {0,1}; 537} 538class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin, 539 string opc, string asm, string cstr, list<dag> pattern> 540 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 541 opc, asm, cstr,pattern> { 542 let Inst{20} = 0; // L bit 543 let Inst{21} = 0; // W bit 544 let Inst{22} = 1; // B bit 545 let Inst{24} = 0; // P bit 546 let Inst{27-26} = {0,1}; 547} 548 549// addrmode3 instructions 550class AI3<dag oops, dag iops, Format f, InstrItinClass itin, 551 string opc, string asm, list<dag> pattern> 552 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 553 opc, asm, "", pattern>; 554class AXI3<dag oops, dag iops, Format f, InstrItinClass itin, 555 string asm, list<dag> pattern> 556 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 557 asm, "", pattern>; 558 559// loads 560class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 561 string opc, string asm, list<dag> pattern> 562 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 563 opc, asm, "", pattern> { 564 let Inst{4} = 1; 565 let Inst{5} = 1; // H bit 566 let Inst{6} = 0; // S bit 567 let Inst{7} = 1; 568 let Inst{20} = 1; // L bit 569 let Inst{21} = 0; // W bit 570 let Inst{24} = 1; // P bit 571 let Inst{27-25} = 0b000; 572} 573class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 574 string asm, list<dag> pattern> 575 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 576 asm, "", pattern> { 577 let Inst{4} = 1; 578 let Inst{5} = 1; // H bit 579 let Inst{6} = 0; // S bit 580 let Inst{7} = 1; 581 let Inst{20} = 1; // L bit 582 let Inst{21} = 0; // W bit 583 let Inst{24} = 1; // P bit 584} 585class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 586 string opc, string asm, list<dag> pattern> 587 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 588 opc, asm, "", pattern> { 589 let Inst{4} = 1; 590 let Inst{5} = 1; // H bit 591 let Inst{6} = 1; // S bit 592 let Inst{7} = 1; 593 let Inst{20} = 1; // L bit 594 let Inst{21} = 0; // W bit 595 let Inst{24} = 1; // P bit 596 let Inst{27-25} = 0b000; 597} 598class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 599 string asm, list<dag> pattern> 600 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 601 asm, "", pattern> { 602 let Inst{4} = 1; 603 let Inst{5} = 1; // H bit 604 let Inst{6} = 1; // S bit 605 let Inst{7} = 1; 606 let Inst{20} = 1; // L bit 607 let Inst{21} = 0; // W bit 608 let Inst{24} = 1; // P bit 609} 610class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 611 string opc, string asm, list<dag> pattern> 612 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 613 opc, asm, "", pattern> { 614 let Inst{4} = 1; 615 let Inst{5} = 0; // H bit 616 let Inst{6} = 1; // S bit 617 let Inst{7} = 1; 618 let Inst{20} = 1; // L bit 619 let Inst{21} = 0; // W bit 620 let Inst{24} = 1; // P bit 621 let Inst{27-25} = 0b000; 622} 623class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 624 string asm, list<dag> pattern> 625 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 626 asm, "", pattern> { 627 let Inst{4} = 1; 628 let Inst{5} = 0; // H bit 629 let Inst{6} = 1; // S bit 630 let Inst{7} = 1; 631 let Inst{20} = 1; // L bit 632 let Inst{21} = 0; // W bit 633 let Inst{24} = 1; // P bit 634} 635class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin, 636 string opc, string asm, list<dag> pattern> 637 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 638 opc, asm, "", pattern> { 639 let Inst{4} = 1; 640 let Inst{5} = 0; // H bit 641 let Inst{6} = 1; // S bit 642 let Inst{7} = 1; 643 let Inst{20} = 0; // L bit 644 let Inst{21} = 0; // W bit 645 let Inst{24} = 1; // P bit 646 let Inst{27-25} = 0b000; 647} 648 649// stores 650class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 651 string opc, string asm, list<dag> pattern> 652 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 653 opc, asm, "", pattern> { 654 let Inst{4} = 1; 655 let Inst{5} = 1; // H bit 656 let Inst{6} = 0; // S bit 657 let Inst{7} = 1; 658 let Inst{20} = 0; // L bit 659 let Inst{21} = 0; // W bit 660 let Inst{24} = 1; // P bit 661 let Inst{27-25} = 0b000; 662} 663class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 664 string asm, list<dag> pattern> 665 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 666 asm, "", pattern> { 667 let Inst{4} = 1; 668 let Inst{5} = 1; // H bit 669 let Inst{6} = 0; // S bit 670 let Inst{7} = 1; 671 let Inst{20} = 0; // L bit 672 let Inst{21} = 0; // W bit 673 let Inst{24} = 1; // P bit 674} 675class AI3std<dag oops, dag iops, Format f, InstrItinClass itin, 676 string opc, string asm, list<dag> pattern> 677 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 678 opc, asm, "", pattern> { 679 let Inst{4} = 1; 680 let Inst{5} = 1; // H bit 681 let Inst{6} = 1; // S bit 682 let Inst{7} = 1; 683 let Inst{20} = 0; // L bit 684 let Inst{21} = 0; // W bit 685 let Inst{24} = 1; // P bit 686 let Inst{27-25} = 0b000; 687} 688 689// Pre-indexed loads 690class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin, 691 string opc, string asm, string cstr, list<dag> pattern> 692 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 693 opc, asm, cstr, pattern> { 694 let Inst{4} = 1; 695 let Inst{5} = 1; // H bit 696 let Inst{6} = 0; // S bit 697 let Inst{7} = 1; 698 let Inst{20} = 1; // L bit 699 let Inst{21} = 1; // W bit 700 let Inst{24} = 1; // P bit 701 let Inst{27-25} = 0b000; 702} 703class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin, 704 string opc, string asm, string cstr, list<dag> pattern> 705 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 706 opc, asm, cstr, pattern> { 707 let Inst{4} = 1; 708 let Inst{5} = 1; // H bit 709 let Inst{6} = 1; // S bit 710 let Inst{7} = 1; 711 let Inst{20} = 1; // L bit 712 let Inst{21} = 1; // W bit 713 let Inst{24} = 1; // P bit 714 let Inst{27-25} = 0b000; 715} 716class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin, 717 string opc, string asm, string cstr, list<dag> pattern> 718 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 719 opc, asm, cstr, pattern> { 720 let Inst{4} = 1; 721 let Inst{5} = 0; // H bit 722 let Inst{6} = 1; // S bit 723 let Inst{7} = 1; 724 let Inst{20} = 1; // L bit 725 let Inst{21} = 1; // W bit 726 let Inst{24} = 1; // P bit 727 let Inst{27-25} = 0b000; 728} 729class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin, 730 string opc, string asm, string cstr, list<dag> pattern> 731 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 732 opc, asm, cstr, pattern> { 733 let Inst{4} = 1; 734 let Inst{5} = 0; // H bit 735 let Inst{6} = 1; // S bit 736 let Inst{7} = 1; 737 let Inst{20} = 0; // L bit 738 let Inst{21} = 1; // W bit 739 let Inst{24} = 1; // P bit 740 let Inst{27-25} = 0b000; 741} 742 743 744// Pre-indexed stores 745class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 746 string opc, string asm, string cstr, list<dag> pattern> 747 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 748 opc, asm, cstr, pattern> { 749 let Inst{4} = 1; 750 let Inst{5} = 1; // H bit 751 let Inst{6} = 0; // S bit 752 let Inst{7} = 1; 753 let Inst{20} = 0; // L bit 754 let Inst{21} = 1; // W bit 755 let Inst{24} = 1; // P bit 756 let Inst{27-25} = 0b000; 757} 758class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin, 759 string opc, string asm, string cstr, list<dag> pattern> 760 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 761 opc, asm, cstr, pattern> { 762 let Inst{4} = 1; 763 let Inst{5} = 1; // H bit 764 let Inst{6} = 1; // S bit 765 let Inst{7} = 1; 766 let Inst{20} = 0; // L bit 767 let Inst{21} = 1; // W bit 768 let Inst{24} = 1; // P bit 769 let Inst{27-25} = 0b000; 770} 771 772// Post-indexed loads 773class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin, 774 string opc, string asm, string cstr, list<dag> pattern> 775 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 776 opc, asm, cstr,pattern> { 777 let Inst{4} = 1; 778 let Inst{5} = 1; // H bit 779 let Inst{6} = 0; // S bit 780 let Inst{7} = 1; 781 let Inst{20} = 1; // L bit 782 let Inst{21} = 0; // W bit 783 let Inst{24} = 0; // P bit 784 let Inst{27-25} = 0b000; 785} 786class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin, 787 string opc, string asm, string cstr, list<dag> pattern> 788 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 789 opc, asm, cstr,pattern> { 790 let Inst{4} = 1; 791 let Inst{5} = 1; // H bit 792 let Inst{6} = 1; // S bit 793 let Inst{7} = 1; 794 let Inst{20} = 1; // L bit 795 let Inst{21} = 0; // W bit 796 let Inst{24} = 0; // P bit 797 let Inst{27-25} = 0b000; 798} 799class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin, 800 string opc, string asm, string cstr, list<dag> pattern> 801 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 802 opc, asm, cstr,pattern> { 803 let Inst{4} = 1; 804 let Inst{5} = 0; // H bit 805 let Inst{6} = 1; // S bit 806 let Inst{7} = 1; 807 let Inst{20} = 1; // L bit 808 let Inst{21} = 0; // W bit 809 let Inst{24} = 0; // P bit 810 let Inst{27-25} = 0b000; 811} 812class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin, 813 string opc, string asm, string cstr, list<dag> pattern> 814 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 815 opc, asm, cstr, pattern> { 816 let Inst{4} = 1; 817 let Inst{5} = 0; // H bit 818 let Inst{6} = 1; // S bit 819 let Inst{7} = 1; 820 let Inst{20} = 0; // L bit 821 let Inst{21} = 0; // W bit 822 let Inst{24} = 0; // P bit 823 let Inst{27-25} = 0b000; 824} 825 826// Post-indexed stores 827class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 828 string opc, string asm, string cstr, list<dag> pattern> 829 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 830 opc, asm, cstr,pattern> { 831 let Inst{4} = 1; 832 let Inst{5} = 1; // H bit 833 let Inst{6} = 0; // S bit 834 let Inst{7} = 1; 835 let Inst{20} = 0; // L bit 836 let Inst{21} = 0; // W bit 837 let Inst{24} = 0; // P bit 838 let Inst{27-25} = 0b000; 839} 840class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin, 841 string opc, string asm, string cstr, list<dag> pattern> 842 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 843 opc, asm, cstr, pattern> { 844 let Inst{4} = 1; 845 let Inst{5} = 1; // H bit 846 let Inst{6} = 1; // S bit 847 let Inst{7} = 1; 848 let Inst{20} = 0; // L bit 849 let Inst{21} = 0; // W bit 850 let Inst{24} = 0; // P bit 851 let Inst{27-25} = 0b000; 852} 853 854 855// addrmode4 instructions 856class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 857 string asm, string cstr, list<dag> pattern> 858 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, 859 asm, cstr, pattern> { 860 let Inst{20} = 1; // L bit 861 let Inst{22} = 0; // S bit 862 let Inst{27-25} = 0b100; 863} 864class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 865 string asm, string cstr, list<dag> pattern> 866 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, 867 asm, cstr, pattern> { 868 let Inst{20} = 0; // L bit 869 let Inst{22} = 0; // S bit 870 let Inst{27-25} = 0b100; 871} 872 873// Unsigned multiply, multiply-accumulate instructions. 874class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 875 string opc, string asm, list<dag> pattern> 876 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 877 opc, asm, "", pattern> { 878 let Inst{7-4} = 0b1001; 879 let Inst{20} = 0; // S bit 880 let Inst{27-21} = opcod; 881} 882class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 883 string opc, string asm, list<dag> pattern> 884 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 885 opc, asm, "", pattern> { 886 let Inst{7-4} = 0b1001; 887 let Inst{27-21} = opcod; 888} 889 890// Most significant word multiply 891class AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 892 string opc, string asm, list<dag> pattern> 893 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 894 opc, asm, "", pattern> { 895 let Inst{7-4} = 0b1001; 896 let Inst{20} = 1; 897 let Inst{27-21} = opcod; 898} 899 900// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 901class AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 902 string opc, string asm, list<dag> pattern> 903 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 904 opc, asm, "", pattern> { 905 let Inst{4} = 0; 906 let Inst{7} = 1; 907 let Inst{20} = 0; 908 let Inst{27-21} = opcod; 909} 910 911// Extend instructions. 912class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 913 string opc, string asm, list<dag> pattern> 914 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 915 opc, asm, "", pattern> { 916 let Inst{7-4} = 0b0111; 917 let Inst{27-20} = opcod; 918} 919 920// Misc Arithmetic instructions. 921class AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 922 string opc, string asm, list<dag> pattern> 923 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 924 opc, asm, "", pattern> { 925 let Inst{27-20} = opcod; 926} 927 928//===----------------------------------------------------------------------===// 929 930// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 931class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 932 list<Predicate> Predicates = [IsARM]; 933} 934class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 935 list<Predicate> Predicates = [IsARM, HasV5TE]; 936} 937class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 938 list<Predicate> Predicates = [IsARM, HasV6]; 939} 940 941//===----------------------------------------------------------------------===// 942// 943// Thumb Instruction Format Definitions. 944// 945 946// TI - Thumb instruction. 947 948class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 949 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 950 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 951 let OutOperandList = oops; 952 let InOperandList = iops; 953 let AsmString = asm; 954 let Pattern = pattern; 955 list<Predicate> Predicates = [IsThumb]; 956} 957 958class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 959 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 960 961// Two-address instructions 962class TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 963 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>; 964 965// tBL, tBX 32-bit instructions 966class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 967 dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 968 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding { 969 let Inst{31-27} = opcod1; 970 let Inst{15-14} = opcod2; 971 let Inst{12} = opcod3; 972} 973 974// BR_JT instructions 975class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 976 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 977 978// Thumb1 only 979class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 980 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 981 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 982 let OutOperandList = oops; 983 let InOperandList = iops; 984 let AsmString = asm; 985 let Pattern = pattern; 986 list<Predicate> Predicates = [IsThumb1Only]; 987} 988 989class T1I<dag oops, dag iops, InstrItinClass itin, 990 string asm, list<dag> pattern> 991 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 992class T1Ix2<dag oops, dag iops, InstrItinClass itin, 993 string asm, list<dag> pattern> 994 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 995class T1JTI<dag oops, dag iops, InstrItinClass itin, 996 string asm, list<dag> pattern> 997 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 998 999// Two-address instructions 1000class T1It<dag oops, dag iops, InstrItinClass itin, 1001 string asm, string cstr, list<dag> pattern> 1002 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 1003 asm, cstr, pattern>; 1004 1005// Thumb1 instruction that can either be predicated or set CPSR. 1006class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1007 InstrItinClass itin, 1008 string opc, string asm, string cstr, list<dag> pattern> 1009 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1010 let OutOperandList = !con(oops, (ops s_cc_out:$s)); 1011 let InOperandList = !con(iops, (ops pred:$p)); 1012 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 1013 let Pattern = pattern; 1014 list<Predicate> Predicates = [IsThumb1Only]; 1015} 1016 1017class T1sI<dag oops, dag iops, InstrItinClass itin, 1018 string opc, string asm, list<dag> pattern> 1019 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 1020 1021// Two-address instructions 1022class T1sIt<dag oops, dag iops, InstrItinClass itin, 1023 string opc, string asm, list<dag> pattern> 1024 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 1025 "$lhs = $dst", pattern>; 1026 1027// Thumb1 instruction that can be predicated. 1028class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1029 InstrItinClass itin, 1030 string opc, string asm, string cstr, list<dag> pattern> 1031 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1032 let OutOperandList = oops; 1033 let InOperandList = !con(iops, (ops pred:$p)); 1034 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1035 let Pattern = pattern; 1036 list<Predicate> Predicates = [IsThumb1Only]; 1037} 1038 1039class T1pI<dag oops, dag iops, InstrItinClass itin, 1040 string opc, string asm, list<dag> pattern> 1041 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 1042 1043// Two-address instructions 1044class T1pIt<dag oops, dag iops, InstrItinClass itin, 1045 string opc, string asm, list<dag> pattern> 1046 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 1047 "$lhs = $dst", pattern>; 1048 1049class T1pI1<dag oops, dag iops, InstrItinClass itin, 1050 string opc, string asm, list<dag> pattern> 1051 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>; 1052class T1pI2<dag oops, dag iops, InstrItinClass itin, 1053 string opc, string asm, list<dag> pattern> 1054 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>; 1055class T1pI4<dag oops, dag iops, InstrItinClass itin, 1056 string opc, string asm, list<dag> pattern> 1057 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>; 1058class T1pIs<dag oops, dag iops, 1059 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1060 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 1061 1062class Encoding16 : Encoding { 1063 let Inst{31-16} = 0x0000; 1064} 1065 1066// A6.2 16-bit Thumb instruction encoding 1067class T1Encoding<bits<6> opcode> : Encoding16 { 1068 let Inst{15-10} = opcode; 1069} 1070 1071// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1072class T1General<bits<5> opcode> : Encoding16 { 1073 let Inst{15-14} = 0b00; 1074 let Inst{13-9} = opcode; 1075} 1076 1077// A6.2.2 Data-processing encoding. 1078class T1DataProcessing<bits<4> opcode> : Encoding16 { 1079 let Inst{15-10} = 0b010000; 1080 let Inst{9-6} = opcode; 1081} 1082 1083// A6.2.3 Special data instructions and branch and exchange encoding. 1084class T1Special<bits<4> opcode> : Encoding16 { 1085 let Inst{15-10} = 0b010001; 1086 let Inst{9-6} = opcode; 1087} 1088 1089// A6.2.4 Load/store single data item encoding. 1090class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1091 let Inst{15-12} = opA; 1092 let Inst{11-9} = opB; 1093} 1094class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>; 1095class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes 1096class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte 1097class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes 1098class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1099 1100// A6.2.5 Miscellaneous 16-bit instructions encoding. 1101class T1Misc<bits<7> opcode> : Encoding16 { 1102 let Inst{15-12} = 0b1011; 1103 let Inst{11-5} = opcode; 1104} 1105 1106// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1107class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1108 InstrItinClass itin, 1109 string opc, string asm, string cstr, list<dag> pattern> 1110 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1111 let OutOperandList = oops; 1112 let InOperandList = !con(iops, (ops pred:$p)); 1113 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1114 let Pattern = pattern; 1115 list<Predicate> Predicates = [IsThumb2]; 1116} 1117 1118// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as 1119// an input operand since by default it's a zero register. It will 1120// become an implicit def once it's "flipped". 1121// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1122// more consistent. 1123class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1124 InstrItinClass itin, 1125 string opc, string asm, string cstr, list<dag> pattern> 1126 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1127 let OutOperandList = oops; 1128 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 1129 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 1130 let Pattern = pattern; 1131 list<Predicate> Predicates = [IsThumb2]; 1132} 1133 1134// Special cases 1135class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1136 InstrItinClass itin, 1137 string asm, string cstr, list<dag> pattern> 1138 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1139 let OutOperandList = oops; 1140 let InOperandList = iops; 1141 let AsmString = asm; 1142 let Pattern = pattern; 1143 list<Predicate> Predicates = [IsThumb2]; 1144} 1145 1146class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1147 InstrItinClass itin, 1148 string asm, string cstr, list<dag> pattern> 1149 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1150 let OutOperandList = oops; 1151 let InOperandList = iops; 1152 let AsmString = asm; 1153 let Pattern = pattern; 1154 list<Predicate> Predicates = [IsThumb1Only]; 1155} 1156 1157class T2I<dag oops, dag iops, InstrItinClass itin, 1158 string opc, string asm, list<dag> pattern> 1159 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1160class T2Ii12<dag oops, dag iops, InstrItinClass itin, 1161 string opc, string asm, list<dag> pattern> 1162 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "", pattern>; 1163class T2Ii8<dag oops, dag iops, InstrItinClass itin, 1164 string opc, string asm, list<dag> pattern> 1165 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 1166class T2Iso<dag oops, dag iops, InstrItinClass itin, 1167 string opc, string asm, list<dag> pattern> 1168 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 1169class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1170 string opc, string asm, list<dag> pattern> 1171 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1172class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin, 1173 string opc, string asm, list<dag> pattern> 1174 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1175 pattern> { 1176 let Inst{31-27} = 0b11101; 1177 let Inst{26-25} = 0b00; 1178 let Inst{24} = P; 1179 let Inst{23} = ?; // The U bit. 1180 let Inst{22} = 1; 1181 let Inst{21} = W; 1182 let Inst{20} = load; 1183} 1184 1185class T2sI<dag oops, dag iops, InstrItinClass itin, 1186 string opc, string asm, list<dag> pattern> 1187 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1188 1189class T2XI<dag oops, dag iops, InstrItinClass itin, 1190 string asm, list<dag> pattern> 1191 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1192class T2JTI<dag oops, dag iops, InstrItinClass itin, 1193 string asm, list<dag> pattern> 1194 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1195 1196class T2Ix2<dag oops, dag iops, InstrItinClass itin, 1197 string opc, string asm, list<dag> pattern> 1198 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>; 1199 1200// Two-address instructions 1201class T2XIt<dag oops, dag iops, InstrItinClass itin, 1202 string asm, string cstr, list<dag> pattern> 1203 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>; 1204 1205// T2Iidxldst - Thumb2 indexed load / store instructions. 1206class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1207 dag oops, dag iops, 1208 AddrMode am, IndexMode im, InstrItinClass itin, 1209 string opc, string asm, string cstr, list<dag> pattern> 1210 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1211 let OutOperandList = oops; 1212 let InOperandList = !con(iops, (ops pred:$p)); 1213 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1214 let Pattern = pattern; 1215 list<Predicate> Predicates = [IsThumb2]; 1216 let Inst{31-27} = 0b11111; 1217 let Inst{26-25} = 0b00; 1218 let Inst{24} = signed; 1219 let Inst{23} = 0; 1220 let Inst{22-21} = opcod; 1221 let Inst{20} = load; 1222 let Inst{11} = 1; 1223 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1224 let Inst{10} = pre; // The P bit. 1225 let Inst{8} = 1; // The W bit. 1226} 1227 1228// Helper class for disassembly only 1229// A6.3.16 & A6.3.17 1230// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions. 1231class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops, 1232 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1233 : T2I<oops, iops, itin, opc, asm, pattern> { 1234 let Inst{31-27} = 0b11111; 1235 let Inst{26-24} = 0b011; 1236 let Inst{23} = long; 1237 let Inst{22-20} = op22_20; 1238 let Inst{7-4} = op7_4; 1239} 1240 1241// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1242class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1243 list<Predicate> Predicates = [IsThumb1Only, HasV5T]; 1244} 1245 1246// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1247class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1248 list<Predicate> Predicates = [IsThumb1Only]; 1249} 1250 1251// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1252class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1253 list<Predicate> Predicates = [IsThumb2]; 1254} 1255 1256//===----------------------------------------------------------------------===// 1257 1258//===----------------------------------------------------------------------===// 1259// ARM VFP Instruction templates. 1260// 1261 1262// Almost all VFP instructions are predicable. 1263class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1264 IndexMode im, Format f, InstrItinClass itin, 1265 string opc, string asm, string cstr, list<dag> pattern> 1266 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1267 let OutOperandList = oops; 1268 let InOperandList = !con(iops, (ops pred:$p)); 1269 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1270 let Pattern = pattern; 1271 list<Predicate> Predicates = [HasVFP2]; 1272} 1273 1274// Special cases 1275class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1276 IndexMode im, Format f, InstrItinClass itin, 1277 string asm, string cstr, list<dag> pattern> 1278 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1279 let OutOperandList = oops; 1280 let InOperandList = iops; 1281 let AsmString = asm; 1282 let Pattern = pattern; 1283 list<Predicate> Predicates = [HasVFP2]; 1284} 1285 1286class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1287 string opc, string asm, list<dag> pattern> 1288 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1289 opc, asm, "", pattern>; 1290 1291// ARM VFP addrmode5 loads and stores 1292class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1293 InstrItinClass itin, 1294 string opc, string asm, list<dag> pattern> 1295 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1296 VFPLdStFrm, itin, opc, asm, "", pattern> { 1297 // TODO: Mark the instructions with the appropriate subtarget info. 1298 let Inst{27-24} = opcod1; 1299 let Inst{21-20} = opcod2; 1300 let Inst{11-8} = 0b1011; 1301 1302 // 64-bit loads & stores operate on both NEON and VFP pipelines. 1303 let Dom = VFPNeonDomain.Value; 1304} 1305 1306class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1307 InstrItinClass itin, 1308 string opc, string asm, list<dag> pattern> 1309 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1310 VFPLdStFrm, itin, opc, asm, "", pattern> { 1311 // TODO: Mark the instructions with the appropriate subtarget info. 1312 let Inst{27-24} = opcod1; 1313 let Inst{21-20} = opcod2; 1314 let Inst{11-8} = 0b1010; 1315} 1316 1317// Load / store multiple 1318class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1319 string asm, string cstr, list<dag> pattern> 1320 : VFPXI<oops, iops, AddrMode5, Size4Bytes, im, 1321 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1322 // TODO: Mark the instructions with the appropriate subtarget info. 1323 let Inst{27-25} = 0b110; 1324 let Inst{11-8} = 0b1011; 1325 1326 // 64-bit loads & stores operate on both NEON and VFP pipelines. 1327 let Dom = VFPNeonDomain.Value; 1328} 1329 1330class AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1331 string asm, string cstr, list<dag> pattern> 1332 : VFPXI<oops, iops, AddrMode5, Size4Bytes, im, 1333 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1334 // TODO: Mark the instructions with the appropriate subtarget info. 1335 let Inst{27-25} = 0b110; 1336 let Inst{11-8} = 0b1010; 1337} 1338 1339// Double precision, unary 1340class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1341 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1342 string asm, list<dag> pattern> 1343 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1344 let Inst{27-23} = opcod1; 1345 let Inst{21-20} = opcod2; 1346 let Inst{19-16} = opcod3; 1347 let Inst{11-8} = 0b1011; 1348 let Inst{7-6} = opcod4; 1349 let Inst{4} = opcod5; 1350} 1351 1352// Double precision, binary 1353class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1354 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 1355 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1356 let Inst{27-23} = opcod1; 1357 let Inst{21-20} = opcod2; 1358 let Inst{11-8} = 0b1011; 1359 let Inst{6} = op6; 1360 let Inst{4} = op4; 1361} 1362 1363// Single precision, unary 1364class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1365 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1366 string asm, list<dag> pattern> 1367 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1368 let Inst{27-23} = opcod1; 1369 let Inst{21-20} = opcod2; 1370 let Inst{19-16} = opcod3; 1371 let Inst{11-8} = 0b1010; 1372 let Inst{7-6} = opcod4; 1373 let Inst{4} = opcod5; 1374} 1375 1376// Single precision unary, if no NEON 1377// Same as ASuI except not available if NEON is enabled 1378class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1379 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1380 string asm, list<dag> pattern> 1381 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1382 pattern> { 1383 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1384} 1385 1386// Single precision, binary 1387class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1388 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1389 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1390 let Inst{27-23} = opcod1; 1391 let Inst{21-20} = opcod2; 1392 let Inst{11-8} = 0b1010; 1393 let Inst{6} = op6; 1394 let Inst{4} = op4; 1395} 1396 1397// Single precision binary, if no NEON 1398// Same as ASbI except not available if NEON is enabled 1399class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1400 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 1401 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1402 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1403} 1404 1405// VFP conversion instructions 1406class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1407 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1408 list<dag> pattern> 1409 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1410 let Inst{27-23} = opcod1; 1411 let Inst{21-20} = opcod2; 1412 let Inst{19-16} = opcod3; 1413 let Inst{11-8} = opcod4; 1414 let Inst{6} = 1; 1415 let Inst{4} = 0; 1416} 1417 1418// VFP conversion between floating-point and fixed-point 1419class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1420 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1421 list<dag> pattern> 1422 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1423 // size (fixed-point number): sx == 0 ? 16 : 32 1424 let Inst{7} = op5; // sx 1425} 1426 1427// VFP conversion instructions, if no NEON 1428class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1429 dag oops, dag iops, InstrItinClass itin, 1430 string opc, string asm, list<dag> pattern> 1431 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1432 pattern> { 1433 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1434} 1435 1436class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1437 InstrItinClass itin, 1438 string opc, string asm, list<dag> pattern> 1439 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1440 let Inst{27-20} = opcod1; 1441 let Inst{11-8} = opcod2; 1442 let Inst{4} = 1; 1443} 1444 1445class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1446 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1447 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1448 1449class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1450 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1451 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1452 1453class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1454 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1455 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1456 1457class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1458 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1459 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1460 1461//===----------------------------------------------------------------------===// 1462 1463//===----------------------------------------------------------------------===// 1464// ARM NEON Instruction templates. 1465// 1466 1467class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, 1468 string opc, string dt, string asm, string cstr, list<dag> pattern> 1469 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> { 1470 let OutOperandList = oops; 1471 let InOperandList = !con(iops, (ops pred:$p)); 1472 let AsmString = !strconcat( 1473 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), 1474 !strconcat("\t", asm)); 1475 let Pattern = pattern; 1476 list<Predicate> Predicates = [HasNEON]; 1477} 1478 1479// Same as NeonI except it does not have a "data type" specifier. 1480class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, 1481 string opc, string asm, string cstr, list<dag> pattern> 1482 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> { 1483 let OutOperandList = oops; 1484 let InOperandList = !con(iops, (ops pred:$p)); 1485 let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm)); 1486 let Pattern = pattern; 1487 list<Predicate> Predicates = [HasNEON]; 1488} 1489 1490class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1491 list<dag> pattern> 1492 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "", 1493 pattern> { 1494} 1495 1496class NI4<dag oops, dag iops, InstrItinClass itin, string opc, 1497 string asm, list<dag> pattern> 1498 : NeonXI<oops, iops, AddrMode4, IndexModeNone, itin, opc, asm, "", 1499 pattern> { 1500} 1501 1502class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1503 dag oops, dag iops, InstrItinClass itin, 1504 string opc, string dt, string asm, string cstr, list<dag> pattern> 1505 : NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, dt, asm, cstr, 1506 pattern> { 1507 let Inst{31-24} = 0b11110100; 1508 let Inst{23} = op23; 1509 let Inst{21-20} = op21_20; 1510 let Inst{11-8} = op11_8; 1511 let Inst{7-4} = op7_4; 1512} 1513 1514class NDataI<dag oops, dag iops, InstrItinClass itin, 1515 string opc, string dt, string asm, string cstr, list<dag> pattern> 1516 : NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, dt, asm, 1517 cstr, pattern> { 1518 let Inst{31-25} = 0b1111001; 1519} 1520 1521class NDataXI<dag oops, dag iops, InstrItinClass itin, 1522 string opc, string asm, string cstr, list<dag> pattern> 1523 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, 1524 cstr, pattern> { 1525 let Inst{31-25} = 0b1111001; 1526} 1527 1528// NEON "one register and a modified immediate" format. 1529class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1530 bit op5, bit op4, 1531 dag oops, dag iops, InstrItinClass itin, 1532 string opc, string dt, string asm, string cstr, list<dag> pattern> 1533 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1534 let Inst{23} = op23; 1535 let Inst{21-19} = op21_19; 1536 let Inst{11-8} = op11_8; 1537 let Inst{7} = op7; 1538 let Inst{6} = op6; 1539 let Inst{5} = op5; 1540 let Inst{4} = op4; 1541} 1542 1543// NEON 2 vector register format. 1544class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1545 bits<5> op11_7, bit op6, bit op4, 1546 dag oops, dag iops, InstrItinClass itin, 1547 string opc, string dt, string asm, string cstr, list<dag> pattern> 1548 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1549 let Inst{24-23} = op24_23; 1550 let Inst{21-20} = op21_20; 1551 let Inst{19-18} = op19_18; 1552 let Inst{17-16} = op17_16; 1553 let Inst{11-7} = op11_7; 1554 let Inst{6} = op6; 1555 let Inst{4} = op4; 1556} 1557 1558// Same as N2V except it doesn't have a datatype suffix. 1559class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1560 bits<5> op11_7, bit op6, bit op4, 1561 dag oops, dag iops, InstrItinClass itin, 1562 string opc, string asm, string cstr, list<dag> pattern> 1563 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> { 1564 let Inst{24-23} = op24_23; 1565 let Inst{21-20} = op21_20; 1566 let Inst{19-18} = op19_18; 1567 let Inst{17-16} = op17_16; 1568 let Inst{11-7} = op11_7; 1569 let Inst{6} = op6; 1570 let Inst{4} = op4; 1571} 1572 1573// NEON 2 vector register with immediate. 1574class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1575 dag oops, dag iops, InstrItinClass itin, 1576 string opc, string dt, string asm, string cstr, list<dag> pattern> 1577 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1578 let Inst{24} = op24; 1579 let Inst{23} = op23; 1580 let Inst{11-8} = op11_8; 1581 let Inst{7} = op7; 1582 let Inst{6} = op6; 1583 let Inst{4} = op4; 1584} 1585 1586// NEON 3 vector register format. 1587class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1588 dag oops, dag iops, InstrItinClass itin, 1589 string opc, string dt, string asm, string cstr, list<dag> pattern> 1590 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1591 let Inst{24} = op24; 1592 let Inst{23} = op23; 1593 let Inst{21-20} = op21_20; 1594 let Inst{11-8} = op11_8; 1595 let Inst{6} = op6; 1596 let Inst{4} = op4; 1597} 1598 1599// Same as N3VX except it doesn't have a data type suffix. 1600class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1601 dag oops, dag iops, InstrItinClass itin, 1602 string opc, string asm, string cstr, list<dag> pattern> 1603 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> { 1604 let Inst{24} = op24; 1605 let Inst{23} = op23; 1606 let Inst{21-20} = op21_20; 1607 let Inst{11-8} = op11_8; 1608 let Inst{6} = op6; 1609 let Inst{4} = op4; 1610} 1611 1612// NEON VMOVs between scalar and core registers. 1613class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1614 dag oops, dag iops, Format f, InstrItinClass itin, 1615 string opc, string dt, string asm, list<dag> pattern> 1616 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain, 1617 "", itin> { 1618 let Inst{27-20} = opcod1; 1619 let Inst{11-8} = opcod2; 1620 let Inst{6-5} = opcod3; 1621 let Inst{4} = 1; 1622 1623 let OutOperandList = oops; 1624 let InOperandList = !con(iops, (ops pred:$p)); 1625 let AsmString = !strconcat( 1626 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), 1627 !strconcat("\t", asm)); 1628 let Pattern = pattern; 1629 list<Predicate> Predicates = [HasNEON]; 1630} 1631class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1632 dag oops, dag iops, InstrItinClass itin, 1633 string opc, string dt, string asm, list<dag> pattern> 1634 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin, 1635 opc, dt, asm, pattern>; 1636class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1637 dag oops, dag iops, InstrItinClass itin, 1638 string opc, string dt, string asm, list<dag> pattern> 1639 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin, 1640 opc, dt, asm, pattern>; 1641class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1642 dag oops, dag iops, InstrItinClass itin, 1643 string opc, string dt, string asm, list<dag> pattern> 1644 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin, 1645 opc, dt, asm, pattern>; 1646 1647// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1648// for single-precision FP. 1649class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1650 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1651} 1652