ARMInstrFormats.td revision 204642
1//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<5> val> { 19 bits<5> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def LdStExFrm : Format<28>; 37 38def ArithMiscFrm : Format<11>; 39def ExtFrm : Format<12>; 40 41def VFPUnaryFrm : Format<13>; 42def VFPBinaryFrm : Format<14>; 43def VFPConv1Frm : Format<15>; 44def VFPConv2Frm : Format<16>; 45def VFPConv3Frm : Format<17>; 46def VFPConv4Frm : Format<18>; 47def VFPConv5Frm : Format<19>; 48def VFPLdStFrm : Format<20>; 49def VFPLdStMulFrm : Format<21>; 50def VFPMiscFrm : Format<22>; 51 52def ThumbFrm : Format<23>; 53 54def NEONFrm : Format<24>; 55def NEONGetLnFrm : Format<25>; 56def NEONSetLnFrm : Format<26>; 57def NEONDupFrm : Format<27>; 58 59def MiscFrm : Format<29>; 60def ThumbMiscFrm : Format<30>; 61 62// Misc flags. 63 64// the instruction has a Rn register operand. 65// UnaryDP - Indicates this is a unary data processing instruction, i.e. 66// it doesn't have a Rn operand. 67class UnaryDP { bit isUnaryDataProc = 1; } 68 69// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 70// a 16-bit Thumb instruction if certain conditions are met. 71class Xform16Bit { bit canXformTo16Bit = 1; } 72 73//===----------------------------------------------------------------------===// 74// ARM Instruction flags. These need to match ARMInstrInfo.h. 75// 76 77// Addressing mode. 78class AddrMode<bits<4> val> { 79 bits<4> Value = val; 80} 81def AddrModeNone : AddrMode<0>; 82def AddrMode1 : AddrMode<1>; 83def AddrMode2 : AddrMode<2>; 84def AddrMode3 : AddrMode<3>; 85def AddrMode4 : AddrMode<4>; 86def AddrMode5 : AddrMode<5>; 87def AddrMode6 : AddrMode<6>; 88def AddrModeT1_1 : AddrMode<7>; 89def AddrModeT1_2 : AddrMode<8>; 90def AddrModeT1_4 : AddrMode<9>; 91def AddrModeT1_s : AddrMode<10>; 92def AddrModeT2_i12: AddrMode<11>; 93def AddrModeT2_i8 : AddrMode<12>; 94def AddrModeT2_so : AddrMode<13>; 95def AddrModeT2_pc : AddrMode<14>; 96def AddrModeT2_i8s4 : AddrMode<15>; 97 98// Instruction size. 99class SizeFlagVal<bits<3> val> { 100 bits<3> Value = val; 101} 102def SizeInvalid : SizeFlagVal<0>; // Unset. 103def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 104def Size8Bytes : SizeFlagVal<2>; 105def Size4Bytes : SizeFlagVal<3>; 106def Size2Bytes : SizeFlagVal<4>; 107 108// Load / store index mode. 109class IndexMode<bits<2> val> { 110 bits<2> Value = val; 111} 112def IndexModeNone : IndexMode<0>; 113def IndexModePre : IndexMode<1>; 114def IndexModePost : IndexMode<2>; 115 116// Instruction execution domain. 117class Domain<bits<2> val> { 118 bits<2> Value = val; 119} 120def GenericDomain : Domain<0>; 121def VFPDomain : Domain<1>; // Instructions in VFP domain only 122def NeonDomain : Domain<2>; // Instructions in Neon domain only 123def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 124 125//===----------------------------------------------------------------------===// 126 127// ARM special operands. 128// 129 130// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 131// register whose default is 0 (no register). 132def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 133 (ops (i32 14), (i32 zero_reg))> { 134 let PrintMethod = "printPredicateOperand"; 135} 136 137// Conditional code result for instructions whose 's' bit is set, e.g. subs. 138def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 139 let PrintMethod = "printSBitModifierOperand"; 140} 141 142// Same as cc_out except it defaults to setting CPSR. 143def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 144 let PrintMethod = "printSBitModifierOperand"; 145} 146 147//===----------------------------------------------------------------------===// 148 149// ARM Instruction templates. 150// 151 152class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 153 Format f, Domain d, string cstr, InstrItinClass itin> 154 : Instruction { 155 let Namespace = "ARM"; 156 157 // TSFlagsFields 158 AddrMode AM = am; 159 bits<4> AddrModeBits = AM.Value; 160 161 SizeFlagVal SZ = sz; 162 bits<3> SizeFlag = SZ.Value; 163 164 IndexMode IM = im; 165 bits<2> IndexModeBits = IM.Value; 166 167 Format F = f; 168 bits<5> Form = F.Value; 169 170 Domain D = d; 171 bits<2> Dom = D.Value; 172 173 // 174 // Attributes specific to ARM instructions... 175 // 176 bit isUnaryDataProc = 0; 177 bit canXformTo16Bit = 0; 178 179 let Constraints = cstr; 180 let Itinerary = itin; 181} 182 183class Encoding { 184 field bits<32> Inst; 185} 186 187class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 188 Format f, Domain d, string cstr, InstrItinClass itin> 189 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 190 191// This Encoding-less class is used by Thumb1 to specify the encoding bits later 192// on by adding flavors to specific instructions. 193class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 194 Format f, Domain d, string cstr, InstrItinClass itin> 195 : InstTemplate<am, sz, im, f, d, cstr, itin>; 196 197class PseudoInst<dag oops, dag iops, InstrItinClass itin, 198 string asm, list<dag> pattern> 199 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 200 "", itin> { 201 let OutOperandList = oops; 202 let InOperandList = iops; 203 let AsmString = asm; 204 let Pattern = pattern; 205} 206 207// Almost all ARM instructions are predicable. 208class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 209 IndexMode im, Format f, InstrItinClass itin, 210 string opc, string asm, string cstr, 211 list<dag> pattern> 212 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 213 let OutOperandList = oops; 214 let InOperandList = !con(iops, (ops pred:$p)); 215 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 216 let Pattern = pattern; 217 list<Predicate> Predicates = [IsARM]; 218} 219// A few are not predicable 220class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 221 IndexMode im, Format f, InstrItinClass itin, 222 string opc, string asm, string cstr, 223 list<dag> pattern> 224 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 225 let OutOperandList = oops; 226 let InOperandList = iops; 227 let AsmString = !strconcat(opc, asm); 228 let Pattern = pattern; 229 let isPredicable = 0; 230 list<Predicate> Predicates = [IsARM]; 231} 232 233// Same as I except it can optionally modify CPSR. Note it's modeled as 234// an input operand since by default it's a zero register. It will 235// become an implicit def once it's "flipped". 236class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 237 IndexMode im, Format f, InstrItinClass itin, 238 string opc, string asm, string cstr, 239 list<dag> pattern> 240 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 241 let OutOperandList = oops; 242 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 243 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); 244 let Pattern = pattern; 245 list<Predicate> Predicates = [IsARM]; 246} 247 248// Special cases 249class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 250 IndexMode im, Format f, InstrItinClass itin, 251 string asm, string cstr, list<dag> pattern> 252 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 253 let OutOperandList = oops; 254 let InOperandList = iops; 255 let AsmString = asm; 256 let Pattern = pattern; 257 list<Predicate> Predicates = [IsARM]; 258} 259 260class AI<dag oops, dag iops, Format f, InstrItinClass itin, 261 string opc, string asm, list<dag> pattern> 262 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 263 opc, asm, "", pattern>; 264class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 265 string opc, string asm, list<dag> pattern> 266 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 267 opc, asm, "", pattern>; 268class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 269 string asm, list<dag> pattern> 270 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 271 asm, "", pattern>; 272class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 273 string opc, string asm, list<dag> pattern> 274 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 275 opc, asm, "", pattern>; 276 277// Ctrl flow instructions 278class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 279 string opc, string asm, list<dag> pattern> 280 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 281 opc, asm, "", pattern> { 282 let Inst{27-24} = opcod; 283} 284class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 285 string asm, list<dag> pattern> 286 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 287 asm, "", pattern> { 288 let Inst{27-24} = opcod; 289} 290class ABXIx2<dag oops, dag iops, InstrItinClass itin, 291 string asm, list<dag> pattern> 292 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin, 293 asm, "", pattern>; 294 295// BR_JT instructions 296class JTI<dag oops, dag iops, InstrItinClass itin, 297 string asm, list<dag> pattern> 298 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 299 asm, "", pattern>; 300 301 302// Atomic load/store instructions 303 304class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 305 string opc, string asm, list<dag> pattern> 306 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 307 opc, asm, "", pattern> { 308 let Inst{27-23} = 0b00011; 309 let Inst{22-21} = opcod; 310 let Inst{20} = 1; 311 let Inst{11-0} = 0b111110011111; 312} 313class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 314 string opc, string asm, list<dag> pattern> 315 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 316 opc, asm, "", pattern> { 317 let Inst{27-23} = 0b00011; 318 let Inst{22-21} = opcod; 319 let Inst{20} = 0; 320 let Inst{11-4} = 0b11111001; 321} 322 323// addrmode1 instructions 324class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 325 string opc, string asm, list<dag> pattern> 326 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 327 opc, asm, "", pattern> { 328 let Inst{24-21} = opcod; 329 let Inst{27-26} = {0,0}; 330} 331class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 332 string opc, string asm, list<dag> pattern> 333 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 334 opc, asm, "", pattern> { 335 let Inst{24-21} = opcod; 336 let Inst{27-26} = {0,0}; 337} 338class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 339 string asm, list<dag> pattern> 340 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 341 asm, "", pattern> { 342 let Inst{24-21} = opcod; 343 let Inst{27-26} = {0,0}; 344} 345class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin, 346 string opc, string asm, list<dag> pattern> 347 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin, 348 opc, asm, "", pattern>; 349 350 351// addrmode2 loads and stores 352class AI2<dag oops, dag iops, Format f, InstrItinClass itin, 353 string opc, string asm, list<dag> pattern> 354 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 355 opc, asm, "", pattern> { 356 let Inst{27-26} = {0,1}; 357} 358 359// loads 360class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 361 string opc, string asm, list<dag> pattern> 362 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 363 opc, asm, "", pattern> { 364 let Inst{20} = 1; // L bit 365 let Inst{21} = 0; // W bit 366 let Inst{22} = 0; // B bit 367 let Inst{24} = 1; // P bit 368 let Inst{27-26} = {0,1}; 369} 370class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 371 string asm, list<dag> pattern> 372 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 373 asm, "", pattern> { 374 let Inst{20} = 1; // L bit 375 let Inst{21} = 0; // W bit 376 let Inst{22} = 0; // B bit 377 let Inst{24} = 1; // P bit 378 let Inst{27-26} = {0,1}; 379} 380class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 381 string opc, string asm, list<dag> pattern> 382 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 383 opc, asm, "", pattern> { 384 let Inst{20} = 1; // L bit 385 let Inst{21} = 0; // W bit 386 let Inst{22} = 1; // B bit 387 let Inst{24} = 1; // P bit 388 let Inst{27-26} = {0,1}; 389} 390class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 391 string asm, list<dag> pattern> 392 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 393 asm, "", pattern> { 394 let Inst{20} = 1; // L bit 395 let Inst{21} = 0; // W bit 396 let Inst{22} = 1; // B bit 397 let Inst{24} = 1; // P bit 398 let Inst{27-26} = {0,1}; 399} 400 401// stores 402class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 403 string opc, string asm, list<dag> pattern> 404 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 405 opc, asm, "", pattern> { 406 let Inst{20} = 0; // L bit 407 let Inst{21} = 0; // W bit 408 let Inst{22} = 0; // B bit 409 let Inst{24} = 1; // P bit 410 let Inst{27-26} = {0,1}; 411} 412class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 413 string asm, list<dag> pattern> 414 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 415 asm, "", pattern> { 416 let Inst{20} = 0; // L bit 417 let Inst{21} = 0; // W bit 418 let Inst{22} = 0; // B bit 419 let Inst{24} = 1; // P bit 420 let Inst{27-26} = {0,1}; 421} 422class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 423 string opc, string asm, list<dag> pattern> 424 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 425 opc, asm, "", pattern> { 426 let Inst{20} = 0; // L bit 427 let Inst{21} = 0; // W bit 428 let Inst{22} = 1; // B bit 429 let Inst{24} = 1; // P bit 430 let Inst{27-26} = {0,1}; 431} 432class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 433 string asm, list<dag> pattern> 434 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 435 asm, "", pattern> { 436 let Inst{20} = 0; // L bit 437 let Inst{21} = 0; // W bit 438 let Inst{22} = 1; // B bit 439 let Inst{24} = 1; // P bit 440 let Inst{27-26} = {0,1}; 441} 442 443// Pre-indexed loads 444class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin, 445 string opc, string asm, string cstr, list<dag> pattern> 446 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 447 opc, asm, cstr, pattern> { 448 let Inst{20} = 1; // L bit 449 let Inst{21} = 1; // W bit 450 let Inst{22} = 0; // B bit 451 let Inst{24} = 1; // P bit 452 let Inst{27-26} = {0,1}; 453} 454class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin, 455 string opc, string asm, string cstr, list<dag> pattern> 456 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 457 opc, asm, cstr, pattern> { 458 let Inst{20} = 1; // L bit 459 let Inst{21} = 1; // W bit 460 let Inst{22} = 1; // B bit 461 let Inst{24} = 1; // P bit 462 let Inst{27-26} = {0,1}; 463} 464 465// Pre-indexed stores 466class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin, 467 string opc, string asm, string cstr, list<dag> pattern> 468 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 469 opc, asm, cstr, pattern> { 470 let Inst{20} = 0; // L bit 471 let Inst{21} = 1; // W bit 472 let Inst{22} = 0; // B bit 473 let Inst{24} = 1; // P bit 474 let Inst{27-26} = {0,1}; 475} 476class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin, 477 string opc, string asm, string cstr, list<dag> pattern> 478 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 479 opc, asm, cstr, pattern> { 480 let Inst{20} = 0; // L bit 481 let Inst{21} = 1; // W bit 482 let Inst{22} = 1; // B bit 483 let Inst{24} = 1; // P bit 484 let Inst{27-26} = {0,1}; 485} 486 487// Post-indexed loads 488class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin, 489 string opc, string asm, string cstr, list<dag> pattern> 490 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 491 opc, asm, cstr,pattern> { 492 let Inst{20} = 1; // L bit 493 let Inst{21} = 0; // W bit 494 let Inst{22} = 0; // B bit 495 let Inst{24} = 0; // P bit 496 let Inst{27-26} = {0,1}; 497} 498class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin, 499 string opc, string asm, string cstr, list<dag> pattern> 500 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 501 opc, asm, cstr,pattern> { 502 let Inst{20} = 1; // L bit 503 let Inst{21} = 0; // W bit 504 let Inst{22} = 1; // B bit 505 let Inst{24} = 0; // P bit 506 let Inst{27-26} = {0,1}; 507} 508 509// Post-indexed stores 510class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin, 511 string opc, string asm, string cstr, list<dag> pattern> 512 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 513 opc, asm, cstr,pattern> { 514 let Inst{20} = 0; // L bit 515 let Inst{21} = 0; // W bit 516 let Inst{22} = 0; // B bit 517 let Inst{24} = 0; // P bit 518 let Inst{27-26} = {0,1}; 519} 520class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin, 521 string opc, string asm, string cstr, list<dag> pattern> 522 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 523 opc, asm, cstr,pattern> { 524 let Inst{20} = 0; // L bit 525 let Inst{21} = 0; // W bit 526 let Inst{22} = 1; // B bit 527 let Inst{24} = 0; // P bit 528 let Inst{27-26} = {0,1}; 529} 530 531// addrmode3 instructions 532class AI3<dag oops, dag iops, Format f, InstrItinClass itin, 533 string opc, string asm, list<dag> pattern> 534 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 535 opc, asm, "", pattern>; 536class AXI3<dag oops, dag iops, Format f, InstrItinClass itin, 537 string asm, list<dag> pattern> 538 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 539 asm, "", pattern>; 540 541// loads 542class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 543 string opc, string asm, list<dag> pattern> 544 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 545 opc, asm, "", pattern> { 546 let Inst{4} = 1; 547 let Inst{5} = 1; // H bit 548 let Inst{6} = 0; // S bit 549 let Inst{7} = 1; 550 let Inst{20} = 1; // L bit 551 let Inst{21} = 0; // W bit 552 let Inst{24} = 1; // P bit 553 let Inst{27-25} = 0b000; 554} 555class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 556 string asm, list<dag> pattern> 557 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 558 asm, "", pattern> { 559 let Inst{4} = 1; 560 let Inst{5} = 1; // H bit 561 let Inst{6} = 0; // S bit 562 let Inst{7} = 1; 563 let Inst{20} = 1; // L bit 564 let Inst{21} = 0; // W bit 565 let Inst{24} = 1; // P bit 566} 567class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 568 string opc, string asm, list<dag> pattern> 569 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 570 opc, asm, "", pattern> { 571 let Inst{4} = 1; 572 let Inst{5} = 1; // H bit 573 let Inst{6} = 1; // S bit 574 let Inst{7} = 1; 575 let Inst{20} = 1; // L bit 576 let Inst{21} = 0; // W bit 577 let Inst{24} = 1; // P bit 578 let Inst{27-25} = 0b000; 579} 580class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 581 string asm, list<dag> pattern> 582 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 583 asm, "", pattern> { 584 let Inst{4} = 1; 585 let Inst{5} = 1; // H bit 586 let Inst{6} = 1; // S bit 587 let Inst{7} = 1; 588 let Inst{20} = 1; // L bit 589 let Inst{21} = 0; // W bit 590 let Inst{24} = 1; // P bit 591} 592class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 593 string opc, string asm, list<dag> pattern> 594 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 595 opc, asm, "", pattern> { 596 let Inst{4} = 1; 597 let Inst{5} = 0; // H bit 598 let Inst{6} = 1; // S bit 599 let Inst{7} = 1; 600 let Inst{20} = 1; // L bit 601 let Inst{21} = 0; // W bit 602 let Inst{24} = 1; // P bit 603 let Inst{27-25} = 0b000; 604} 605class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 606 string asm, list<dag> pattern> 607 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 608 asm, "", pattern> { 609 let Inst{4} = 1; 610 let Inst{5} = 0; // H bit 611 let Inst{6} = 1; // S bit 612 let Inst{7} = 1; 613 let Inst{20} = 1; // L bit 614 let Inst{21} = 0; // W bit 615 let Inst{24} = 1; // P bit 616} 617class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin, 618 string opc, string asm, list<dag> pattern> 619 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 620 opc, asm, "", pattern> { 621 let Inst{4} = 1; 622 let Inst{5} = 0; // H bit 623 let Inst{6} = 1; // S bit 624 let Inst{7} = 1; 625 let Inst{20} = 0; // L bit 626 let Inst{21} = 0; // W bit 627 let Inst{24} = 1; // P bit 628 let Inst{27-25} = 0b000; 629} 630 631// stores 632class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 633 string opc, string asm, list<dag> pattern> 634 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 635 opc, asm, "", pattern> { 636 let Inst{4} = 1; 637 let Inst{5} = 1; // H bit 638 let Inst{6} = 0; // S bit 639 let Inst{7} = 1; 640 let Inst{20} = 0; // L bit 641 let Inst{21} = 0; // W bit 642 let Inst{24} = 1; // P bit 643 let Inst{27-25} = 0b000; 644} 645class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 646 string asm, list<dag> pattern> 647 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 648 asm, "", pattern> { 649 let Inst{4} = 1; 650 let Inst{5} = 1; // H bit 651 let Inst{6} = 0; // S bit 652 let Inst{7} = 1; 653 let Inst{20} = 0; // L bit 654 let Inst{21} = 0; // W bit 655 let Inst{24} = 1; // P bit 656} 657class AI3std<dag oops, dag iops, Format f, InstrItinClass itin, 658 string opc, string asm, list<dag> pattern> 659 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 660 opc, asm, "", pattern> { 661 let Inst{4} = 1; 662 let Inst{5} = 1; // H bit 663 let Inst{6} = 1; // S bit 664 let Inst{7} = 1; 665 let Inst{20} = 0; // L bit 666 let Inst{21} = 0; // W bit 667 let Inst{24} = 1; // P bit 668 let Inst{27-25} = 0b000; 669} 670 671// Pre-indexed loads 672class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin, 673 string opc, string asm, string cstr, list<dag> pattern> 674 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 675 opc, asm, cstr, pattern> { 676 let Inst{4} = 1; 677 let Inst{5} = 1; // H bit 678 let Inst{6} = 0; // S bit 679 let Inst{7} = 1; 680 let Inst{20} = 1; // L bit 681 let Inst{21} = 1; // W bit 682 let Inst{24} = 1; // P bit 683 let Inst{27-25} = 0b000; 684} 685class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin, 686 string opc, string asm, string cstr, list<dag> pattern> 687 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 688 opc, asm, cstr, pattern> { 689 let Inst{4} = 1; 690 let Inst{5} = 1; // H bit 691 let Inst{6} = 1; // S bit 692 let Inst{7} = 1; 693 let Inst{20} = 1; // L bit 694 let Inst{21} = 1; // W bit 695 let Inst{24} = 1; // P bit 696 let Inst{27-25} = 0b000; 697} 698class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin, 699 string opc, string asm, string cstr, list<dag> pattern> 700 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 701 opc, asm, cstr, pattern> { 702 let Inst{4} = 1; 703 let Inst{5} = 0; // H bit 704 let Inst{6} = 1; // S bit 705 let Inst{7} = 1; 706 let Inst{20} = 1; // L bit 707 let Inst{21} = 1; // W bit 708 let Inst{24} = 1; // P bit 709 let Inst{27-25} = 0b000; 710} 711class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin, 712 string opc, string asm, string cstr, list<dag> pattern> 713 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 714 opc, asm, cstr, pattern> { 715 let Inst{4} = 1; 716 let Inst{5} = 0; // H bit 717 let Inst{6} = 1; // S bit 718 let Inst{7} = 1; 719 let Inst{20} = 0; // L bit 720 let Inst{21} = 1; // W bit 721 let Inst{24} = 1; // P bit 722 let Inst{27-25} = 0b000; 723} 724 725 726// Pre-indexed stores 727class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 728 string opc, string asm, string cstr, list<dag> pattern> 729 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 730 opc, asm, cstr, pattern> { 731 let Inst{4} = 1; 732 let Inst{5} = 1; // H bit 733 let Inst{6} = 0; // S bit 734 let Inst{7} = 1; 735 let Inst{20} = 0; // L bit 736 let Inst{21} = 1; // W bit 737 let Inst{24} = 1; // P bit 738 let Inst{27-25} = 0b000; 739} 740class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin, 741 string opc, string asm, string cstr, list<dag> pattern> 742 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 743 opc, asm, cstr, pattern> { 744 let Inst{4} = 1; 745 let Inst{5} = 1; // H bit 746 let Inst{6} = 1; // S bit 747 let Inst{7} = 1; 748 let Inst{20} = 0; // L bit 749 let Inst{21} = 1; // W bit 750 let Inst{24} = 1; // P bit 751 let Inst{27-25} = 0b000; 752} 753 754// Post-indexed loads 755class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin, 756 string opc, string asm, string cstr, list<dag> pattern> 757 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 758 opc, asm, cstr,pattern> { 759 let Inst{4} = 1; 760 let Inst{5} = 1; // H bit 761 let Inst{6} = 0; // S bit 762 let Inst{7} = 1; 763 let Inst{20} = 1; // L bit 764 let Inst{21} = 0; // W bit 765 let Inst{24} = 0; // P bit 766 let Inst{27-25} = 0b000; 767} 768class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin, 769 string opc, string asm, string cstr, list<dag> pattern> 770 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 771 opc, asm, cstr,pattern> { 772 let Inst{4} = 1; 773 let Inst{5} = 1; // H bit 774 let Inst{6} = 1; // S bit 775 let Inst{7} = 1; 776 let Inst{20} = 1; // L bit 777 let Inst{21} = 0; // W bit 778 let Inst{24} = 0; // P bit 779 let Inst{27-25} = 0b000; 780} 781class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin, 782 string opc, string asm, string cstr, list<dag> pattern> 783 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 784 opc, asm, cstr,pattern> { 785 let Inst{4} = 1; 786 let Inst{5} = 0; // H bit 787 let Inst{6} = 1; // S bit 788 let Inst{7} = 1; 789 let Inst{20} = 1; // L bit 790 let Inst{21} = 0; // W bit 791 let Inst{24} = 0; // P bit 792 let Inst{27-25} = 0b000; 793} 794class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin, 795 string opc, string asm, string cstr, list<dag> pattern> 796 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 797 opc, asm, cstr, pattern> { 798 let Inst{4} = 1; 799 let Inst{5} = 0; // H bit 800 let Inst{6} = 1; // S bit 801 let Inst{7} = 1; 802 let Inst{20} = 0; // L bit 803 let Inst{21} = 0; // W bit 804 let Inst{24} = 0; // P bit 805 let Inst{27-25} = 0b000; 806} 807 808// Post-indexed stores 809class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 810 string opc, string asm, string cstr, list<dag> pattern> 811 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 812 opc, asm, cstr,pattern> { 813 let Inst{4} = 1; 814 let Inst{5} = 1; // H bit 815 let Inst{6} = 0; // S bit 816 let Inst{7} = 1; 817 let Inst{20} = 0; // L bit 818 let Inst{21} = 0; // W bit 819 let Inst{24} = 0; // P bit 820 let Inst{27-25} = 0b000; 821} 822class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin, 823 string opc, string asm, string cstr, list<dag> pattern> 824 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 825 opc, asm, cstr, pattern> { 826 let Inst{4} = 1; 827 let Inst{5} = 1; // H bit 828 let Inst{6} = 1; // S bit 829 let Inst{7} = 1; 830 let Inst{20} = 0; // L bit 831 let Inst{21} = 0; // W bit 832 let Inst{24} = 0; // P bit 833 let Inst{27-25} = 0b000; 834} 835 836 837// addrmode4 instructions 838class AXI4ld<dag oops, dag iops, Format f, InstrItinClass itin, 839 string asm, list<dag> pattern> 840 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin, 841 asm, "", pattern> { 842 let Inst{20} = 1; // L bit 843 let Inst{22} = 0; // S bit 844 let Inst{27-25} = 0b100; 845} 846class AXI4st<dag oops, dag iops, Format f, InstrItinClass itin, 847 string asm, list<dag> pattern> 848 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin, 849 asm, "", pattern> { 850 let Inst{20} = 0; // L bit 851 let Inst{22} = 0; // S bit 852 let Inst{27-25} = 0b100; 853} 854 855// Unsigned multiply, multiply-accumulate instructions. 856class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 857 string opc, string asm, list<dag> pattern> 858 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 859 opc, asm, "", pattern> { 860 let Inst{7-4} = 0b1001; 861 let Inst{20} = 0; // S bit 862 let Inst{27-21} = opcod; 863} 864class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 865 string opc, string asm, list<dag> pattern> 866 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 867 opc, asm, "", pattern> { 868 let Inst{7-4} = 0b1001; 869 let Inst{27-21} = opcod; 870} 871 872// Most significant word multiply 873class AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 874 string opc, string asm, list<dag> pattern> 875 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 876 opc, asm, "", pattern> { 877 let Inst{7-4} = 0b1001; 878 let Inst{20} = 1; 879 let Inst{27-21} = opcod; 880} 881 882// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 883class AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 884 string opc, string asm, list<dag> pattern> 885 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 886 opc, asm, "", pattern> { 887 let Inst{4} = 0; 888 let Inst{7} = 1; 889 let Inst{20} = 0; 890 let Inst{27-21} = opcod; 891} 892 893// Extend instructions. 894class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 895 string opc, string asm, list<dag> pattern> 896 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 897 opc, asm, "", pattern> { 898 let Inst{7-4} = 0b0111; 899 let Inst{27-20} = opcod; 900} 901 902// Misc Arithmetic instructions. 903class AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 904 string opc, string asm, list<dag> pattern> 905 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 906 opc, asm, "", pattern> { 907 let Inst{27-20} = opcod; 908} 909 910//===----------------------------------------------------------------------===// 911 912// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 913class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 914 list<Predicate> Predicates = [IsARM]; 915} 916class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 917 list<Predicate> Predicates = [IsARM, HasV5TE]; 918} 919class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 920 list<Predicate> Predicates = [IsARM, HasV6]; 921} 922 923//===----------------------------------------------------------------------===// 924// 925// Thumb Instruction Format Definitions. 926// 927 928// TI - Thumb instruction. 929 930class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 931 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 932 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 933 let OutOperandList = oops; 934 let InOperandList = iops; 935 let AsmString = asm; 936 let Pattern = pattern; 937 list<Predicate> Predicates = [IsThumb]; 938} 939 940class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 941 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 942 943// Two-address instructions 944class TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 945 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>; 946 947// tBL, tBX 32-bit instructions 948class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 949 dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 950 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding { 951 let Inst{31-27} = opcod1; 952 let Inst{15-14} = opcod2; 953 let Inst{12} = opcod3; 954} 955 956// BR_JT instructions 957class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 958 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 959 960// Thumb1 only 961class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 962 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 963 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 964 let OutOperandList = oops; 965 let InOperandList = iops; 966 let AsmString = asm; 967 let Pattern = pattern; 968 list<Predicate> Predicates = [IsThumb1Only]; 969} 970 971class T1I<dag oops, dag iops, InstrItinClass itin, 972 string asm, list<dag> pattern> 973 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 974class T1Ix2<dag oops, dag iops, InstrItinClass itin, 975 string asm, list<dag> pattern> 976 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 977class T1JTI<dag oops, dag iops, InstrItinClass itin, 978 string asm, list<dag> pattern> 979 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 980 981// Two-address instructions 982class T1It<dag oops, dag iops, InstrItinClass itin, 983 string asm, list<dag> pattern> 984 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 985 asm, "$lhs = $dst", pattern>; 986 987// Thumb1 instruction that can either be predicated or set CPSR. 988class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 989 InstrItinClass itin, 990 string opc, string asm, string cstr, list<dag> pattern> 991 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 992 let OutOperandList = !con(oops, (ops s_cc_out:$s)); 993 let InOperandList = !con(iops, (ops pred:$p)); 994 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 995 let Pattern = pattern; 996 list<Predicate> Predicates = [IsThumb1Only]; 997} 998 999class T1sI<dag oops, dag iops, InstrItinClass itin, 1000 string opc, string asm, list<dag> pattern> 1001 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 1002 1003// Two-address instructions 1004class T1sIt<dag oops, dag iops, InstrItinClass itin, 1005 string opc, string asm, list<dag> pattern> 1006 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 1007 "$lhs = $dst", pattern>; 1008 1009// Thumb1 instruction that can be predicated. 1010class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1011 InstrItinClass itin, 1012 string opc, string asm, string cstr, list<dag> pattern> 1013 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1014 let OutOperandList = oops; 1015 let InOperandList = !con(iops, (ops pred:$p)); 1016 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1017 let Pattern = pattern; 1018 list<Predicate> Predicates = [IsThumb1Only]; 1019} 1020 1021class T1pI<dag oops, dag iops, InstrItinClass itin, 1022 string opc, string asm, list<dag> pattern> 1023 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 1024 1025// Two-address instructions 1026class T1pIt<dag oops, dag iops, InstrItinClass itin, 1027 string opc, string asm, list<dag> pattern> 1028 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 1029 "$lhs = $dst", pattern>; 1030 1031class T1pI1<dag oops, dag iops, InstrItinClass itin, 1032 string opc, string asm, list<dag> pattern> 1033 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>; 1034class T1pI2<dag oops, dag iops, InstrItinClass itin, 1035 string opc, string asm, list<dag> pattern> 1036 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>; 1037class T1pI4<dag oops, dag iops, InstrItinClass itin, 1038 string opc, string asm, list<dag> pattern> 1039 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>; 1040class T1pIs<dag oops, dag iops, 1041 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1042 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 1043 1044class Encoding16 : Encoding { 1045 let Inst{31-16} = 0x0000; 1046} 1047 1048// A6.2 16-bit Thumb instruction encoding 1049class T1Encoding<bits<6> opcode> : Encoding16 { 1050 let Inst{15-10} = opcode; 1051} 1052 1053// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1054class T1General<bits<5> opcode> : Encoding16 { 1055 let Inst{15-14} = 0b00; 1056 let Inst{13-9} = opcode; 1057} 1058 1059// A6.2.2 Data-processing encoding. 1060class T1DataProcessing<bits<4> opcode> : Encoding16 { 1061 let Inst{15-10} = 0b010000; 1062 let Inst{9-6} = opcode; 1063} 1064 1065// A6.2.3 Special data instructions and branch and exchange encoding. 1066class T1Special<bits<4> opcode> : Encoding16 { 1067 let Inst{15-10} = 0b010001; 1068 let Inst{9-6} = opcode; 1069} 1070 1071// A6.2.4 Load/store single data item encoding. 1072class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1073 let Inst{15-12} = opA; 1074 let Inst{11-9} = opB; 1075} 1076class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>; 1077class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes 1078class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte 1079class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes 1080class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1081 1082// A6.2.5 Miscellaneous 16-bit instructions encoding. 1083class T1Misc<bits<7> opcode> : Encoding16 { 1084 let Inst{15-12} = 0b1011; 1085 let Inst{11-5} = opcode; 1086} 1087 1088// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1089class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1090 InstrItinClass itin, 1091 string opc, string asm, string cstr, list<dag> pattern> 1092 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1093 let OutOperandList = oops; 1094 let InOperandList = !con(iops, (ops pred:$p)); 1095 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1096 let Pattern = pattern; 1097 list<Predicate> Predicates = [IsThumb2]; 1098} 1099 1100// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as 1101// an input operand since by default it's a zero register. It will 1102// become an implicit def once it's "flipped". 1103// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1104// more consistent. 1105class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1106 InstrItinClass itin, 1107 string opc, string asm, string cstr, list<dag> pattern> 1108 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1109 let OutOperandList = oops; 1110 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 1111 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 1112 let Pattern = pattern; 1113 list<Predicate> Predicates = [IsThumb2]; 1114} 1115 1116// Special cases 1117class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1118 InstrItinClass itin, 1119 string asm, string cstr, list<dag> pattern> 1120 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1121 let OutOperandList = oops; 1122 let InOperandList = iops; 1123 let AsmString = asm; 1124 let Pattern = pattern; 1125 list<Predicate> Predicates = [IsThumb2]; 1126} 1127 1128class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1129 InstrItinClass itin, 1130 string asm, string cstr, list<dag> pattern> 1131 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1132 let OutOperandList = oops; 1133 let InOperandList = iops; 1134 let AsmString = asm; 1135 let Pattern = pattern; 1136 list<Predicate> Predicates = [IsThumb1Only]; 1137} 1138 1139class T2I<dag oops, dag iops, InstrItinClass itin, 1140 string opc, string asm, list<dag> pattern> 1141 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1142class T2Ii12<dag oops, dag iops, InstrItinClass itin, 1143 string opc, string asm, list<dag> pattern> 1144 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "", pattern>; 1145class T2Ii8<dag oops, dag iops, InstrItinClass itin, 1146 string opc, string asm, list<dag> pattern> 1147 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 1148class T2Iso<dag oops, dag iops, InstrItinClass itin, 1149 string opc, string asm, list<dag> pattern> 1150 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 1151class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1152 string opc, string asm, list<dag> pattern> 1153 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1154class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin, 1155 string opc, string asm, list<dag> pattern> 1156 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1157 pattern> { 1158 let Inst{31-27} = 0b11101; 1159 let Inst{26-25} = 0b00; 1160 let Inst{24} = P; 1161 let Inst{23} = ?; // The U bit. 1162 let Inst{22} = 1; 1163 let Inst{21} = W; 1164 let Inst{20} = load; 1165} 1166 1167class T2sI<dag oops, dag iops, InstrItinClass itin, 1168 string opc, string asm, list<dag> pattern> 1169 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1170 1171class T2XI<dag oops, dag iops, InstrItinClass itin, 1172 string asm, list<dag> pattern> 1173 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1174class T2JTI<dag oops, dag iops, InstrItinClass itin, 1175 string asm, list<dag> pattern> 1176 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1177 1178class T2Ix2<dag oops, dag iops, InstrItinClass itin, 1179 string opc, string asm, list<dag> pattern> 1180 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>; 1181 1182 1183// T2Iidxldst - Thumb2 indexed load / store instructions. 1184class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1185 dag oops, dag iops, 1186 AddrMode am, IndexMode im, InstrItinClass itin, 1187 string opc, string asm, string cstr, list<dag> pattern> 1188 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1189 let OutOperandList = oops; 1190 let InOperandList = !con(iops, (ops pred:$p)); 1191 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1192 let Pattern = pattern; 1193 list<Predicate> Predicates = [IsThumb2]; 1194 let Inst{31-27} = 0b11111; 1195 let Inst{26-25} = 0b00; 1196 let Inst{24} = signed; 1197 let Inst{23} = 0; 1198 let Inst{22-21} = opcod; 1199 let Inst{20} = load; 1200 let Inst{11} = 1; 1201 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1202 let Inst{10} = pre; // The P bit. 1203 let Inst{8} = 1; // The W bit. 1204} 1205 1206// Helper class for disassembly only 1207// A6.3.16 & A6.3.17 1208// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions. 1209class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops, 1210 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1211 : T2I<oops, iops, itin, opc, asm, pattern> { 1212 let Inst{31-27} = 0b11111; 1213 let Inst{26-24} = 0b011; 1214 let Inst{23} = long; 1215 let Inst{22-20} = op22_20; 1216 let Inst{7-4} = op7_4; 1217} 1218 1219// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1220class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1221 list<Predicate> Predicates = [IsThumb1Only, HasV5T]; 1222} 1223 1224// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1225class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1226 list<Predicate> Predicates = [IsThumb1Only]; 1227} 1228 1229// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1230class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1231 list<Predicate> Predicates = [IsThumb2]; 1232} 1233 1234//===----------------------------------------------------------------------===// 1235 1236//===----------------------------------------------------------------------===// 1237// ARM VFP Instruction templates. 1238// 1239 1240// Almost all VFP instructions are predicable. 1241class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1242 IndexMode im, Format f, InstrItinClass itin, 1243 string opc, string asm, string cstr, list<dag> pattern> 1244 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1245 let OutOperandList = oops; 1246 let InOperandList = !con(iops, (ops pred:$p)); 1247 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1248 let Pattern = pattern; 1249 list<Predicate> Predicates = [HasVFP2]; 1250} 1251 1252// Special cases 1253class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1254 IndexMode im, Format f, InstrItinClass itin, 1255 string asm, string cstr, list<dag> pattern> 1256 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1257 let OutOperandList = oops; 1258 let InOperandList = iops; 1259 let AsmString = asm; 1260 let Pattern = pattern; 1261 list<Predicate> Predicates = [HasVFP2]; 1262} 1263 1264class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1265 string opc, string asm, list<dag> pattern> 1266 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1267 opc, asm, "", pattern>; 1268 1269// ARM VFP addrmode5 loads and stores 1270class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1271 InstrItinClass itin, 1272 string opc, string asm, list<dag> pattern> 1273 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1274 VFPLdStFrm, itin, opc, asm, "", pattern> { 1275 // TODO: Mark the instructions with the appropriate subtarget info. 1276 let Inst{27-24} = opcod1; 1277 let Inst{21-20} = opcod2; 1278 let Inst{11-8} = 0b1011; 1279 1280 // 64-bit loads & stores operate on both NEON and VFP pipelines. 1281 let Dom = VFPNeonDomain.Value; 1282} 1283 1284class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1285 InstrItinClass itin, 1286 string opc, string asm, list<dag> pattern> 1287 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1288 VFPLdStFrm, itin, opc, asm, "", pattern> { 1289 // TODO: Mark the instructions with the appropriate subtarget info. 1290 let Inst{27-24} = opcod1; 1291 let Inst{21-20} = opcod2; 1292 let Inst{11-8} = 0b1010; 1293} 1294 1295// Load / store multiple 1296class AXDI5<dag oops, dag iops, InstrItinClass itin, 1297 string asm, list<dag> pattern> 1298 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1299 VFPLdStMulFrm, itin, asm, "", pattern> { 1300 // TODO: Mark the instructions with the appropriate subtarget info. 1301 let Inst{27-25} = 0b110; 1302 let Inst{11-8} = 0b1011; 1303 1304 // 64-bit loads & stores operate on both NEON and VFP pipelines. 1305 let Dom = VFPNeonDomain.Value; 1306} 1307 1308class AXSI5<dag oops, dag iops, InstrItinClass itin, 1309 string asm, list<dag> pattern> 1310 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1311 VFPLdStMulFrm, itin, asm, "", pattern> { 1312 // TODO: Mark the instructions with the appropriate subtarget info. 1313 let Inst{27-25} = 0b110; 1314 let Inst{11-8} = 0b1010; 1315} 1316 1317// Double precision, unary 1318class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1319 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1320 string asm, list<dag> pattern> 1321 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1322 let Inst{27-23} = opcod1; 1323 let Inst{21-20} = opcod2; 1324 let Inst{19-16} = opcod3; 1325 let Inst{11-8} = 0b1011; 1326 let Inst{7-6} = opcod4; 1327 let Inst{4} = opcod5; 1328} 1329 1330// Double precision, binary 1331class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1332 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 1333 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1334 let Inst{27-23} = opcod1; 1335 let Inst{21-20} = opcod2; 1336 let Inst{11-8} = 0b1011; 1337 let Inst{6} = op6; 1338 let Inst{4} = op4; 1339} 1340 1341// Single precision, unary 1342class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1343 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1344 string asm, list<dag> pattern> 1345 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1346 let Inst{27-23} = opcod1; 1347 let Inst{21-20} = opcod2; 1348 let Inst{19-16} = opcod3; 1349 let Inst{11-8} = 0b1010; 1350 let Inst{7-6} = opcod4; 1351 let Inst{4} = opcod5; 1352} 1353 1354// Single precision unary, if no NEON 1355// Same as ASuI except not available if NEON is enabled 1356class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1357 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1358 string asm, list<dag> pattern> 1359 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1360 pattern> { 1361 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1362} 1363 1364// Single precision, binary 1365class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1366 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1367 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1368 let Inst{27-23} = opcod1; 1369 let Inst{21-20} = opcod2; 1370 let Inst{11-8} = 0b1010; 1371 let Inst{6} = op6; 1372 let Inst{4} = op4; 1373} 1374 1375// Single precision binary, if no NEON 1376// Same as ASbI except not available if NEON is enabled 1377class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1378 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 1379 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1380 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1381} 1382 1383// VFP conversion instructions 1384class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1385 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1386 list<dag> pattern> 1387 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1388 let Inst{27-23} = opcod1; 1389 let Inst{21-20} = opcod2; 1390 let Inst{19-16} = opcod3; 1391 let Inst{11-8} = opcod4; 1392 let Inst{6} = 1; 1393 let Inst{4} = 0; 1394} 1395 1396// VFP conversion between floating-point and fixed-point 1397class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1398 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1399 list<dag> pattern> 1400 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1401 // size (fixed-point number): sx == 0 ? 16 : 32 1402 let Inst{7} = op5; // sx 1403} 1404 1405// VFP conversion instructions, if no NEON 1406class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1407 dag oops, dag iops, InstrItinClass itin, 1408 string opc, string asm, list<dag> pattern> 1409 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1410 pattern> { 1411 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1412} 1413 1414class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1415 InstrItinClass itin, 1416 string opc, string asm, list<dag> pattern> 1417 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1418 let Inst{27-20} = opcod1; 1419 let Inst{11-8} = opcod2; 1420 let Inst{4} = 1; 1421} 1422 1423class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1424 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1425 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1426 1427class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1428 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1429 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1430 1431class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1432 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1433 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1434 1435class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1436 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1437 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1438 1439//===----------------------------------------------------------------------===// 1440 1441//===----------------------------------------------------------------------===// 1442// ARM NEON Instruction templates. 1443// 1444 1445class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, 1446 string opc, string dt, string asm, string cstr, list<dag> pattern> 1447 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> { 1448 let OutOperandList = oops; 1449 let InOperandList = !con(iops, (ops pred:$p)); 1450 let AsmString = !strconcat( 1451 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), 1452 !strconcat("\t", asm)); 1453 let Pattern = pattern; 1454 list<Predicate> Predicates = [HasNEON]; 1455} 1456 1457// Same as NeonI except it does not have a "data type" specifier. 1458class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, 1459 string opc, string asm, string cstr, list<dag> pattern> 1460 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> { 1461 let OutOperandList = oops; 1462 let InOperandList = !con(iops, (ops pred:$p)); 1463 let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm)); 1464 let Pattern = pattern; 1465 list<Predicate> Predicates = [HasNEON]; 1466} 1467 1468class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1469 list<dag> pattern> 1470 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "", 1471 pattern> { 1472} 1473 1474class NI4<dag oops, dag iops, InstrItinClass itin, string opc, 1475 string asm, list<dag> pattern> 1476 : NeonXI<oops, iops, AddrMode4, IndexModeNone, itin, opc, asm, "", 1477 pattern> { 1478} 1479 1480class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1481 dag oops, dag iops, InstrItinClass itin, 1482 string opc, string dt, string asm, string cstr, list<dag> pattern> 1483 : NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, dt, asm, cstr, 1484 pattern> { 1485 let Inst{31-24} = 0b11110100; 1486 let Inst{23} = op23; 1487 let Inst{21-20} = op21_20; 1488 let Inst{11-8} = op11_8; 1489 let Inst{7-4} = op7_4; 1490} 1491 1492class NDataI<dag oops, dag iops, InstrItinClass itin, 1493 string opc, string dt, string asm, string cstr, list<dag> pattern> 1494 : NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, dt, asm, 1495 cstr, pattern> { 1496 let Inst{31-25} = 0b1111001; 1497} 1498 1499class NDataXI<dag oops, dag iops, InstrItinClass itin, 1500 string opc, string asm, string cstr, list<dag> pattern> 1501 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, 1502 cstr, pattern> { 1503 let Inst{31-25} = 0b1111001; 1504} 1505 1506// NEON "one register and a modified immediate" format. 1507class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1508 bit op5, bit op4, 1509 dag oops, dag iops, InstrItinClass itin, 1510 string opc, string dt, string asm, string cstr, list<dag> pattern> 1511 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1512 let Inst{23} = op23; 1513 let Inst{21-19} = op21_19; 1514 let Inst{11-8} = op11_8; 1515 let Inst{7} = op7; 1516 let Inst{6} = op6; 1517 let Inst{5} = op5; 1518 let Inst{4} = op4; 1519} 1520 1521// NEON 2 vector register format. 1522class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1523 bits<5> op11_7, bit op6, bit op4, 1524 dag oops, dag iops, InstrItinClass itin, 1525 string opc, string dt, string asm, string cstr, list<dag> pattern> 1526 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1527 let Inst{24-23} = op24_23; 1528 let Inst{21-20} = op21_20; 1529 let Inst{19-18} = op19_18; 1530 let Inst{17-16} = op17_16; 1531 let Inst{11-7} = op11_7; 1532 let Inst{6} = op6; 1533 let Inst{4} = op4; 1534} 1535 1536// Same as N2V except it doesn't have a datatype suffix. 1537class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1538 bits<5> op11_7, bit op6, bit op4, 1539 dag oops, dag iops, InstrItinClass itin, 1540 string opc, string asm, string cstr, list<dag> pattern> 1541 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> { 1542 let Inst{24-23} = op24_23; 1543 let Inst{21-20} = op21_20; 1544 let Inst{19-18} = op19_18; 1545 let Inst{17-16} = op17_16; 1546 let Inst{11-7} = op11_7; 1547 let Inst{6} = op6; 1548 let Inst{4} = op4; 1549} 1550 1551// NEON 2 vector register with immediate. 1552class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1553 dag oops, dag iops, InstrItinClass itin, 1554 string opc, string dt, string asm, string cstr, list<dag> pattern> 1555 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1556 let Inst{24} = op24; 1557 let Inst{23} = op23; 1558 let Inst{11-8} = op11_8; 1559 let Inst{7} = op7; 1560 let Inst{6} = op6; 1561 let Inst{4} = op4; 1562} 1563 1564// NEON 3 vector register format. 1565class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1566 dag oops, dag iops, InstrItinClass itin, 1567 string opc, string dt, string asm, string cstr, list<dag> pattern> 1568 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1569 let Inst{24} = op24; 1570 let Inst{23} = op23; 1571 let Inst{21-20} = op21_20; 1572 let Inst{11-8} = op11_8; 1573 let Inst{6} = op6; 1574 let Inst{4} = op4; 1575} 1576 1577// Same as N3VX except it doesn't have a data type suffix. 1578class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1579 dag oops, dag iops, InstrItinClass itin, 1580 string opc, string asm, string cstr, list<dag> pattern> 1581 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> { 1582 let Inst{24} = op24; 1583 let Inst{23} = op23; 1584 let Inst{21-20} = op21_20; 1585 let Inst{11-8} = op11_8; 1586 let Inst{6} = op6; 1587 let Inst{4} = op4; 1588} 1589 1590// NEON VMOVs between scalar and core registers. 1591class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1592 dag oops, dag iops, Format f, InstrItinClass itin, 1593 string opc, string dt, string asm, list<dag> pattern> 1594 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain, 1595 "", itin> { 1596 let Inst{27-20} = opcod1; 1597 let Inst{11-8} = opcod2; 1598 let Inst{6-5} = opcod3; 1599 let Inst{4} = 1; 1600 1601 let OutOperandList = oops; 1602 let InOperandList = !con(iops, (ops pred:$p)); 1603 let AsmString = !strconcat( 1604 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), 1605 !strconcat("\t", asm)); 1606 let Pattern = pattern; 1607 list<Predicate> Predicates = [HasNEON]; 1608} 1609class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1610 dag oops, dag iops, InstrItinClass itin, 1611 string opc, string dt, string asm, list<dag> pattern> 1612 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin, 1613 opc, dt, asm, pattern>; 1614class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1615 dag oops, dag iops, InstrItinClass itin, 1616 string opc, string dt, string asm, list<dag> pattern> 1617 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin, 1618 opc, dt, asm, pattern>; 1619class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1620 dag oops, dag iops, InstrItinClass itin, 1621 string opc, string dt, string asm, list<dag> pattern> 1622 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin, 1623 opc, dt, asm, pattern>; 1624 1625// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1626// for single-precision FP. 1627class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1628 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1629} 1630