ARMInstrFormats.td revision 203954
1//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<5> val> { 19 bits<5> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def LdStExFrm : Format<28>; 37 38def ArithMiscFrm : Format<11>; 39def ExtFrm : Format<12>; 40 41def VFPUnaryFrm : Format<13>; 42def VFPBinaryFrm : Format<14>; 43def VFPConv1Frm : Format<15>; 44def VFPConv2Frm : Format<16>; 45def VFPConv3Frm : Format<17>; 46def VFPConv4Frm : Format<18>; 47def VFPConv5Frm : Format<19>; 48def VFPLdStFrm : Format<20>; 49def VFPLdStMulFrm : Format<21>; 50def VFPMiscFrm : Format<22>; 51 52def ThumbFrm : Format<23>; 53 54def NEONFrm : Format<24>; 55def NEONGetLnFrm : Format<25>; 56def NEONSetLnFrm : Format<26>; 57def NEONDupFrm : Format<27>; 58 59def MiscFrm : Format<29>; 60def ThumbMiscFrm : Format<30>; 61 62// Misc flags. 63 64// the instruction has a Rn register operand. 65// UnaryDP - Indicates this is a unary data processing instruction, i.e. 66// it doesn't have a Rn operand. 67class UnaryDP { bit isUnaryDataProc = 1; } 68 69// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 70// a 16-bit Thumb instruction if certain conditions are met. 71class Xform16Bit { bit canXformTo16Bit = 1; } 72 73//===----------------------------------------------------------------------===// 74// ARM Instruction flags. These need to match ARMInstrInfo.h. 75// 76 77// Addressing mode. 78class AddrMode<bits<4> val> { 79 bits<4> Value = val; 80} 81def AddrModeNone : AddrMode<0>; 82def AddrMode1 : AddrMode<1>; 83def AddrMode2 : AddrMode<2>; 84def AddrMode3 : AddrMode<3>; 85def AddrMode4 : AddrMode<4>; 86def AddrMode5 : AddrMode<5>; 87def AddrMode6 : AddrMode<6>; 88def AddrModeT1_1 : AddrMode<7>; 89def AddrModeT1_2 : AddrMode<8>; 90def AddrModeT1_4 : AddrMode<9>; 91def AddrModeT1_s : AddrMode<10>; 92def AddrModeT2_i12: AddrMode<11>; 93def AddrModeT2_i8 : AddrMode<12>; 94def AddrModeT2_so : AddrMode<13>; 95def AddrModeT2_pc : AddrMode<14>; 96def AddrModeT2_i8s4 : AddrMode<15>; 97 98// Instruction size. 99class SizeFlagVal<bits<3> val> { 100 bits<3> Value = val; 101} 102def SizeInvalid : SizeFlagVal<0>; // Unset. 103def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 104def Size8Bytes : SizeFlagVal<2>; 105def Size4Bytes : SizeFlagVal<3>; 106def Size2Bytes : SizeFlagVal<4>; 107 108// Load / store index mode. 109class IndexMode<bits<2> val> { 110 bits<2> Value = val; 111} 112def IndexModeNone : IndexMode<0>; 113def IndexModePre : IndexMode<1>; 114def IndexModePost : IndexMode<2>; 115 116// Instruction execution domain. 117class Domain<bits<2> val> { 118 bits<2> Value = val; 119} 120def GenericDomain : Domain<0>; 121def VFPDomain : Domain<1>; // Instructions in VFP domain only 122def NeonDomain : Domain<2>; // Instructions in Neon domain only 123def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 124 125//===----------------------------------------------------------------------===// 126 127// ARM special operands. 128// 129 130// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 131// register whose default is 0 (no register). 132def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 133 (ops (i32 14), (i32 zero_reg))> { 134 let PrintMethod = "printPredicateOperand"; 135} 136 137// Conditional code result for instructions whose 's' bit is set, e.g. subs. 138def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 139 let PrintMethod = "printSBitModifierOperand"; 140} 141 142// Same as cc_out except it defaults to setting CPSR. 143def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 144 let PrintMethod = "printSBitModifierOperand"; 145} 146 147//===----------------------------------------------------------------------===// 148 149// ARM Instruction templates. 150// 151 152class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 153 Format f, Domain d, string cstr, InstrItinClass itin> 154 : Instruction { 155 let Namespace = "ARM"; 156 157 // TSFlagsFields 158 AddrMode AM = am; 159 bits<4> AddrModeBits = AM.Value; 160 161 SizeFlagVal SZ = sz; 162 bits<3> SizeFlag = SZ.Value; 163 164 IndexMode IM = im; 165 bits<2> IndexModeBits = IM.Value; 166 167 Format F = f; 168 bits<5> Form = F.Value; 169 170 Domain D = d; 171 bits<2> Dom = D.Value; 172 173 // 174 // Attributes specific to ARM instructions... 175 // 176 bit isUnaryDataProc = 0; 177 bit canXformTo16Bit = 0; 178 179 let Constraints = cstr; 180 let Itinerary = itin; 181} 182 183class Encoding { 184 field bits<32> Inst; 185} 186 187class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 188 Format f, Domain d, string cstr, InstrItinClass itin> 189 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 190 191// This Encoding-less class is used by Thumb1 to specify the encoding bits later 192// on by adding flavors to specific instructions. 193class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 194 Format f, Domain d, string cstr, InstrItinClass itin> 195 : InstTemplate<am, sz, im, f, d, cstr, itin>; 196 197class PseudoInst<dag oops, dag iops, InstrItinClass itin, 198 string asm, list<dag> pattern> 199 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 200 "", itin> { 201 let OutOperandList = oops; 202 let InOperandList = iops; 203 let AsmString = asm; 204 let Pattern = pattern; 205} 206 207// Almost all ARM instructions are predicable. 208class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 209 IndexMode im, Format f, InstrItinClass itin, 210 string opc, string asm, string cstr, 211 list<dag> pattern> 212 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 213 let OutOperandList = oops; 214 let InOperandList = !con(iops, (ops pred:$p)); 215 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 216 let Pattern = pattern; 217 list<Predicate> Predicates = [IsARM]; 218} 219// A few are not predicable 220class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 221 IndexMode im, Format f, InstrItinClass itin, 222 string opc, string asm, string cstr, 223 list<dag> pattern> 224 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 225 let OutOperandList = oops; 226 let InOperandList = iops; 227 let AsmString = !strconcat(opc, asm); 228 let Pattern = pattern; 229 let isPredicable = 0; 230 list<Predicate> Predicates = [IsARM]; 231} 232 233// Same as I except it can optionally modify CPSR. Note it's modeled as 234// an input operand since by default it's a zero register. It will 235// become an implicit def once it's "flipped". 236class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 237 IndexMode im, Format f, InstrItinClass itin, 238 string opc, string asm, string cstr, 239 list<dag> pattern> 240 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 241 let OutOperandList = oops; 242 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 243 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); 244 let Pattern = pattern; 245 list<Predicate> Predicates = [IsARM]; 246} 247 248// Special cases 249class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 250 IndexMode im, Format f, InstrItinClass itin, 251 string asm, string cstr, list<dag> pattern> 252 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 253 let OutOperandList = oops; 254 let InOperandList = iops; 255 let AsmString = asm; 256 let Pattern = pattern; 257 list<Predicate> Predicates = [IsARM]; 258} 259 260class AI<dag oops, dag iops, Format f, InstrItinClass itin, 261 string opc, string asm, list<dag> pattern> 262 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 263 opc, asm, "", pattern>; 264class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 265 string opc, string asm, list<dag> pattern> 266 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 267 opc, asm, "", pattern>; 268class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 269 string asm, list<dag> pattern> 270 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 271 asm, "", pattern>; 272class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 273 string opc, string asm, list<dag> pattern> 274 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 275 opc, asm, "", pattern>; 276 277// Ctrl flow instructions 278class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 279 string opc, string asm, list<dag> pattern> 280 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 281 opc, asm, "", pattern> { 282 let Inst{27-24} = opcod; 283} 284class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 285 string asm, list<dag> pattern> 286 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 287 asm, "", pattern> { 288 let Inst{27-24} = opcod; 289} 290class ABXIx2<dag oops, dag iops, InstrItinClass itin, 291 string asm, list<dag> pattern> 292 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin, 293 asm, "", pattern>; 294 295// BR_JT instructions 296class JTI<dag oops, dag iops, InstrItinClass itin, 297 string asm, list<dag> pattern> 298 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 299 asm, "", pattern>; 300 301 302// Atomic load/store instructions 303 304class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 305 string opc, string asm, list<dag> pattern> 306 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 307 opc, asm, "", pattern> { 308 let Inst{27-23} = 0b00011; 309 let Inst{22-21} = opcod; 310 let Inst{20} = 1; 311 let Inst{11-0} = 0b111110011111; 312} 313class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 314 string opc, string asm, list<dag> pattern> 315 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 316 opc, asm, "", pattern> { 317 let Inst{27-23} = 0b00011; 318 let Inst{22-21} = opcod; 319 let Inst{20} = 0; 320 let Inst{11-4} = 0b11111001; 321} 322 323// addrmode1 instructions 324class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 325 string opc, string asm, list<dag> pattern> 326 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 327 opc, asm, "", pattern> { 328 let Inst{24-21} = opcod; 329 let Inst{27-26} = {0,0}; 330} 331class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 332 string opc, string asm, list<dag> pattern> 333 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 334 opc, asm, "", pattern> { 335 let Inst{24-21} = opcod; 336 let Inst{27-26} = {0,0}; 337} 338class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 339 string asm, list<dag> pattern> 340 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 341 asm, "", pattern> { 342 let Inst{24-21} = opcod; 343 let Inst{27-26} = {0,0}; 344} 345class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin, 346 string opc, string asm, list<dag> pattern> 347 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin, 348 opc, asm, "", pattern>; 349 350 351// addrmode2 loads and stores 352class AI2<dag oops, dag iops, Format f, InstrItinClass itin, 353 string opc, string asm, list<dag> pattern> 354 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 355 opc, asm, "", pattern> { 356 let Inst{27-26} = {0,1}; 357} 358 359// loads 360class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 361 string opc, string asm, list<dag> pattern> 362 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 363 opc, asm, "", pattern> { 364 let Inst{20} = 1; // L bit 365 let Inst{21} = 0; // W bit 366 let Inst{22} = 0; // B bit 367 let Inst{24} = 1; // P bit 368 let Inst{27-26} = {0,1}; 369} 370class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 371 string asm, list<dag> pattern> 372 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 373 asm, "", pattern> { 374 let Inst{20} = 1; // L bit 375 let Inst{21} = 0; // W bit 376 let Inst{22} = 0; // B bit 377 let Inst{24} = 1; // P bit 378 let Inst{27-26} = {0,1}; 379} 380class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 381 string opc, string asm, list<dag> pattern> 382 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 383 opc, asm, "", pattern> { 384 let Inst{20} = 1; // L bit 385 let Inst{21} = 0; // W bit 386 let Inst{22} = 1; // B bit 387 let Inst{24} = 1; // P bit 388 let Inst{27-26} = {0,1}; 389} 390class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 391 string asm, list<dag> pattern> 392 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 393 asm, "", pattern> { 394 let Inst{20} = 1; // L bit 395 let Inst{21} = 0; // W bit 396 let Inst{22} = 1; // B bit 397 let Inst{24} = 1; // P bit 398 let Inst{27-26} = {0,1}; 399} 400 401// stores 402class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 403 string opc, string asm, list<dag> pattern> 404 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 405 opc, asm, "", pattern> { 406 let Inst{20} = 0; // L bit 407 let Inst{21} = 0; // W bit 408 let Inst{22} = 0; // B bit 409 let Inst{24} = 1; // P bit 410 let Inst{27-26} = {0,1}; 411} 412class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 413 string asm, list<dag> pattern> 414 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 415 asm, "", pattern> { 416 let Inst{20} = 0; // L bit 417 let Inst{21} = 0; // W bit 418 let Inst{22} = 0; // B bit 419 let Inst{24} = 1; // P bit 420 let Inst{27-26} = {0,1}; 421} 422class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 423 string opc, string asm, list<dag> pattern> 424 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 425 opc, asm, "", pattern> { 426 let Inst{20} = 0; // L bit 427 let Inst{21} = 0; // W bit 428 let Inst{22} = 1; // B bit 429 let Inst{24} = 1; // P bit 430 let Inst{27-26} = {0,1}; 431} 432class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 433 string asm, list<dag> pattern> 434 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 435 asm, "", pattern> { 436 let Inst{20} = 0; // L bit 437 let Inst{21} = 0; // W bit 438 let Inst{22} = 1; // B bit 439 let Inst{24} = 1; // P bit 440 let Inst{27-26} = {0,1}; 441} 442 443// Pre-indexed loads 444class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin, 445 string opc, string asm, string cstr, list<dag> pattern> 446 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 447 opc, asm, cstr, pattern> { 448 let Inst{20} = 1; // L bit 449 let Inst{21} = 1; // W bit 450 let Inst{22} = 0; // B bit 451 let Inst{24} = 1; // P bit 452 let Inst{27-26} = {0,1}; 453} 454class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin, 455 string opc, string asm, string cstr, list<dag> pattern> 456 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 457 opc, asm, cstr, pattern> { 458 let Inst{20} = 1; // L bit 459 let Inst{21} = 1; // W bit 460 let Inst{22} = 1; // B bit 461 let Inst{24} = 1; // P bit 462 let Inst{27-26} = {0,1}; 463} 464 465// Pre-indexed stores 466class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin, 467 string opc, string asm, string cstr, list<dag> pattern> 468 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 469 opc, asm, cstr, pattern> { 470 let Inst{20} = 0; // L bit 471 let Inst{21} = 1; // W bit 472 let Inst{22} = 0; // B bit 473 let Inst{24} = 1; // P bit 474 let Inst{27-26} = {0,1}; 475} 476class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin, 477 string opc, string asm, string cstr, list<dag> pattern> 478 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 479 opc, asm, cstr, pattern> { 480 let Inst{20} = 0; // L bit 481 let Inst{21} = 1; // W bit 482 let Inst{22} = 1; // B bit 483 let Inst{24} = 1; // P bit 484 let Inst{27-26} = {0,1}; 485} 486 487// Post-indexed loads 488class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin, 489 string opc, string asm, string cstr, list<dag> pattern> 490 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 491 opc, asm, cstr,pattern> { 492 let Inst{20} = 1; // L bit 493 let Inst{21} = 0; // W bit 494 let Inst{22} = 0; // B bit 495 let Inst{24} = 0; // P bit 496 let Inst{27-26} = {0,1}; 497} 498class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin, 499 string opc, string asm, string cstr, list<dag> pattern> 500 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 501 opc, asm, cstr,pattern> { 502 let Inst{20} = 1; // L bit 503 let Inst{21} = 0; // W bit 504 let Inst{22} = 1; // B bit 505 let Inst{24} = 0; // P bit 506 let Inst{27-26} = {0,1}; 507} 508 509// Post-indexed stores 510class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin, 511 string opc, string asm, string cstr, list<dag> pattern> 512 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 513 opc, asm, cstr,pattern> { 514 let Inst{20} = 0; // L bit 515 let Inst{21} = 0; // W bit 516 let Inst{22} = 0; // B bit 517 let Inst{24} = 0; // P bit 518 let Inst{27-26} = {0,1}; 519} 520class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin, 521 string opc, string asm, string cstr, list<dag> pattern> 522 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 523 opc, asm, cstr,pattern> { 524 let Inst{20} = 0; // L bit 525 let Inst{21} = 0; // W bit 526 let Inst{22} = 1; // B bit 527 let Inst{24} = 0; // P bit 528 let Inst{27-26} = {0,1}; 529} 530 531// addrmode3 instructions 532class AI3<dag oops, dag iops, Format f, InstrItinClass itin, 533 string opc, string asm, list<dag> pattern> 534 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 535 opc, asm, "", pattern>; 536class AXI3<dag oops, dag iops, Format f, InstrItinClass itin, 537 string asm, list<dag> pattern> 538 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 539 asm, "", pattern>; 540 541// loads 542class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 543 string opc, string asm, list<dag> pattern> 544 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 545 opc, asm, "", pattern> { 546 let Inst{4} = 1; 547 let Inst{5} = 1; // H bit 548 let Inst{6} = 0; // S bit 549 let Inst{7} = 1; 550 let Inst{20} = 1; // L bit 551 let Inst{21} = 0; // W bit 552 let Inst{24} = 1; // P bit 553 let Inst{27-25} = 0b000; 554} 555class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 556 string asm, list<dag> pattern> 557 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 558 asm, "", pattern> { 559 let Inst{4} = 1; 560 let Inst{5} = 1; // H bit 561 let Inst{6} = 0; // S bit 562 let Inst{7} = 1; 563 let Inst{20} = 1; // L bit 564 let Inst{21} = 0; // W bit 565 let Inst{24} = 1; // P bit 566} 567class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 568 string opc, string asm, list<dag> pattern> 569 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 570 opc, asm, "", pattern> { 571 let Inst{4} = 1; 572 let Inst{5} = 1; // H bit 573 let Inst{6} = 1; // S bit 574 let Inst{7} = 1; 575 let Inst{20} = 1; // L bit 576 let Inst{21} = 0; // W bit 577 let Inst{24} = 1; // P bit 578 let Inst{27-25} = 0b000; 579} 580class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 581 string asm, list<dag> pattern> 582 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 583 asm, "", pattern> { 584 let Inst{4} = 1; 585 let Inst{5} = 1; // H bit 586 let Inst{6} = 1; // S bit 587 let Inst{7} = 1; 588 let Inst{20} = 1; // L bit 589 let Inst{21} = 0; // W bit 590 let Inst{24} = 1; // P bit 591} 592class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 593 string opc, string asm, list<dag> pattern> 594 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 595 opc, asm, "", pattern> { 596 let Inst{4} = 1; 597 let Inst{5} = 0; // H bit 598 let Inst{6} = 1; // S bit 599 let Inst{7} = 1; 600 let Inst{20} = 1; // L bit 601 let Inst{21} = 0; // W bit 602 let Inst{24} = 1; // P bit 603 let Inst{27-25} = 0b000; 604} 605class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 606 string asm, list<dag> pattern> 607 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 608 asm, "", pattern> { 609 let Inst{4} = 1; 610 let Inst{5} = 0; // H bit 611 let Inst{6} = 1; // S bit 612 let Inst{7} = 1; 613 let Inst{20} = 1; // L bit 614 let Inst{21} = 0; // W bit 615 let Inst{24} = 1; // P bit 616} 617class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin, 618 string opc, string asm, list<dag> pattern> 619 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 620 opc, asm, "", pattern> { 621 let Inst{4} = 1; 622 let Inst{5} = 0; // H bit 623 let Inst{6} = 1; // S bit 624 let Inst{7} = 1; 625 let Inst{20} = 0; // L bit 626 let Inst{21} = 0; // W bit 627 let Inst{24} = 1; // P bit 628 let Inst{27-25} = 0b000; 629} 630 631// stores 632class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 633 string opc, string asm, list<dag> pattern> 634 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 635 opc, asm, "", pattern> { 636 let Inst{4} = 1; 637 let Inst{5} = 1; // H bit 638 let Inst{6} = 0; // S bit 639 let Inst{7} = 1; 640 let Inst{20} = 0; // L bit 641 let Inst{21} = 0; // W bit 642 let Inst{24} = 1; // P bit 643 let Inst{27-25} = 0b000; 644} 645class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 646 string asm, list<dag> pattern> 647 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 648 asm, "", pattern> { 649 let Inst{4} = 1; 650 let Inst{5} = 1; // H bit 651 let Inst{6} = 0; // S bit 652 let Inst{7} = 1; 653 let Inst{20} = 0; // L bit 654 let Inst{21} = 0; // W bit 655 let Inst{24} = 1; // P bit 656} 657class AI3std<dag oops, dag iops, Format f, InstrItinClass itin, 658 string opc, string asm, list<dag> pattern> 659 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 660 opc, asm, "", pattern> { 661 let Inst{4} = 1; 662 let Inst{5} = 1; // H bit 663 let Inst{6} = 1; // S bit 664 let Inst{7} = 1; 665 let Inst{20} = 0; // L bit 666 let Inst{21} = 0; // W bit 667 let Inst{24} = 1; // P bit 668 let Inst{27-25} = 0b000; 669} 670 671// Pre-indexed loads 672class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin, 673 string opc, string asm, string cstr, list<dag> pattern> 674 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 675 opc, asm, cstr, pattern> { 676 let Inst{4} = 1; 677 let Inst{5} = 1; // H bit 678 let Inst{6} = 0; // S bit 679 let Inst{7} = 1; 680 let Inst{20} = 1; // L bit 681 let Inst{21} = 1; // W bit 682 let Inst{24} = 1; // P bit 683 let Inst{27-25} = 0b000; 684} 685class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin, 686 string opc, string asm, string cstr, list<dag> pattern> 687 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 688 opc, asm, cstr, pattern> { 689 let Inst{4} = 1; 690 let Inst{5} = 1; // H bit 691 let Inst{6} = 1; // S bit 692 let Inst{7} = 1; 693 let Inst{20} = 1; // L bit 694 let Inst{21} = 1; // W bit 695 let Inst{24} = 1; // P bit 696 let Inst{27-25} = 0b000; 697} 698class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin, 699 string opc, string asm, string cstr, list<dag> pattern> 700 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 701 opc, asm, cstr, pattern> { 702 let Inst{4} = 1; 703 let Inst{5} = 0; // H bit 704 let Inst{6} = 1; // S bit 705 let Inst{7} = 1; 706 let Inst{20} = 1; // L bit 707 let Inst{21} = 1; // W bit 708 let Inst{24} = 1; // P bit 709 let Inst{27-25} = 0b000; 710} 711 712// Pre-indexed stores 713class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 714 string opc, string asm, string cstr, list<dag> pattern> 715 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 716 opc, asm, cstr, pattern> { 717 let Inst{4} = 1; 718 let Inst{5} = 1; // H bit 719 let Inst{6} = 0; // S bit 720 let Inst{7} = 1; 721 let Inst{20} = 0; // L bit 722 let Inst{21} = 1; // W bit 723 let Inst{24} = 1; // P bit 724 let Inst{27-25} = 0b000; 725} 726 727// Post-indexed loads 728class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin, 729 string opc, string asm, string cstr, list<dag> pattern> 730 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 731 opc, asm, cstr,pattern> { 732 let Inst{4} = 1; 733 let Inst{5} = 1; // H bit 734 let Inst{6} = 0; // S bit 735 let Inst{7} = 1; 736 let Inst{20} = 1; // L bit 737 let Inst{21} = 1; // W bit 738 let Inst{24} = 0; // P bit 739 let Inst{27-25} = 0b000; 740} 741class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin, 742 string opc, string asm, string cstr, list<dag> pattern> 743 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 744 opc, asm, cstr,pattern> { 745 let Inst{4} = 1; 746 let Inst{5} = 1; // H bit 747 let Inst{6} = 1; // S bit 748 let Inst{7} = 1; 749 let Inst{20} = 1; // L bit 750 let Inst{21} = 1; // W bit 751 let Inst{24} = 0; // P bit 752 let Inst{27-25} = 0b000; 753} 754class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin, 755 string opc, string asm, string cstr, list<dag> pattern> 756 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 757 opc, asm, cstr,pattern> { 758 let Inst{4} = 1; 759 let Inst{5} = 0; // H bit 760 let Inst{6} = 1; // S bit 761 let Inst{7} = 1; 762 let Inst{20} = 1; // L bit 763 let Inst{21} = 1; // W bit 764 let Inst{24} = 0; // P bit 765 let Inst{27-25} = 0b000; 766} 767 768// Post-indexed stores 769class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 770 string opc, string asm, string cstr, list<dag> pattern> 771 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 772 opc, asm, cstr,pattern> { 773 let Inst{4} = 1; 774 let Inst{5} = 1; // H bit 775 let Inst{6} = 0; // S bit 776 let Inst{7} = 1; 777 let Inst{20} = 0; // L bit 778 let Inst{21} = 1; // W bit 779 let Inst{24} = 0; // P bit 780 let Inst{27-25} = 0b000; 781} 782 783 784// addrmode4 instructions 785class AXI4ld<dag oops, dag iops, Format f, InstrItinClass itin, 786 string asm, list<dag> pattern> 787 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin, 788 asm, "", pattern> { 789 let Inst{20} = 1; // L bit 790 let Inst{22} = 0; // S bit 791 let Inst{27-25} = 0b100; 792} 793class AXI4st<dag oops, dag iops, Format f, InstrItinClass itin, 794 string asm, list<dag> pattern> 795 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin, 796 asm, "", pattern> { 797 let Inst{20} = 0; // L bit 798 let Inst{22} = 0; // S bit 799 let Inst{27-25} = 0b100; 800} 801 802// Unsigned multiply, multiply-accumulate instructions. 803class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 804 string opc, string asm, list<dag> pattern> 805 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 806 opc, asm, "", pattern> { 807 let Inst{7-4} = 0b1001; 808 let Inst{20} = 0; // S bit 809 let Inst{27-21} = opcod; 810} 811class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 812 string opc, string asm, list<dag> pattern> 813 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 814 opc, asm, "", pattern> { 815 let Inst{7-4} = 0b1001; 816 let Inst{27-21} = opcod; 817} 818 819// Most significant word multiply 820class AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 821 string opc, string asm, list<dag> pattern> 822 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 823 opc, asm, "", pattern> { 824 let Inst{7-4} = 0b1001; 825 let Inst{20} = 1; 826 let Inst{27-21} = opcod; 827} 828 829// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 830class AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 831 string opc, string asm, list<dag> pattern> 832 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 833 opc, asm, "", pattern> { 834 let Inst{4} = 0; 835 let Inst{7} = 1; 836 let Inst{20} = 0; 837 let Inst{27-21} = opcod; 838} 839 840// Extend instructions. 841class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 842 string opc, string asm, list<dag> pattern> 843 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 844 opc, asm, "", pattern> { 845 let Inst{7-4} = 0b0111; 846 let Inst{27-20} = opcod; 847} 848 849// Misc Arithmetic instructions. 850class AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 851 string opc, string asm, list<dag> pattern> 852 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 853 opc, asm, "", pattern> { 854 let Inst{27-20} = opcod; 855} 856 857//===----------------------------------------------------------------------===// 858 859// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 860class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 861 list<Predicate> Predicates = [IsARM]; 862} 863class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 864 list<Predicate> Predicates = [IsARM, HasV5TE]; 865} 866class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 867 list<Predicate> Predicates = [IsARM, HasV6]; 868} 869 870//===----------------------------------------------------------------------===// 871// 872// Thumb Instruction Format Definitions. 873// 874 875// TI - Thumb instruction. 876 877class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 878 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 879 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 880 let OutOperandList = oops; 881 let InOperandList = iops; 882 let AsmString = asm; 883 let Pattern = pattern; 884 list<Predicate> Predicates = [IsThumb]; 885} 886 887class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 888 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 889 890// Two-address instructions 891class TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 892 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>; 893 894// tBL, tBX 32-bit instructions 895class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 896 dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 897 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding { 898 let Inst{31-27} = opcod1; 899 let Inst{15-14} = opcod2; 900 let Inst{12} = opcod3; 901} 902 903// BR_JT instructions 904class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 905 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 906 907// Thumb1 only 908class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 909 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 910 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 911 let OutOperandList = oops; 912 let InOperandList = iops; 913 let AsmString = asm; 914 let Pattern = pattern; 915 list<Predicate> Predicates = [IsThumb1Only]; 916} 917 918class T1I<dag oops, dag iops, InstrItinClass itin, 919 string asm, list<dag> pattern> 920 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 921class T1Ix2<dag oops, dag iops, InstrItinClass itin, 922 string asm, list<dag> pattern> 923 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 924class T1JTI<dag oops, dag iops, InstrItinClass itin, 925 string asm, list<dag> pattern> 926 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 927 928// Two-address instructions 929class T1It<dag oops, dag iops, InstrItinClass itin, 930 string asm, list<dag> pattern> 931 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 932 asm, "$lhs = $dst", pattern>; 933 934// Thumb1 instruction that can either be predicated or set CPSR. 935class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 936 InstrItinClass itin, 937 string opc, string asm, string cstr, list<dag> pattern> 938 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 939 let OutOperandList = !con(oops, (ops s_cc_out:$s)); 940 let InOperandList = !con(iops, (ops pred:$p)); 941 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 942 let Pattern = pattern; 943 list<Predicate> Predicates = [IsThumb1Only]; 944} 945 946class T1sI<dag oops, dag iops, InstrItinClass itin, 947 string opc, string asm, list<dag> pattern> 948 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 949 950// Two-address instructions 951class T1sIt<dag oops, dag iops, InstrItinClass itin, 952 string opc, string asm, list<dag> pattern> 953 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 954 "$lhs = $dst", pattern>; 955 956// Thumb1 instruction that can be predicated. 957class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 958 InstrItinClass itin, 959 string opc, string asm, string cstr, list<dag> pattern> 960 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 961 let OutOperandList = oops; 962 let InOperandList = !con(iops, (ops pred:$p)); 963 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 964 let Pattern = pattern; 965 list<Predicate> Predicates = [IsThumb1Only]; 966} 967 968class T1pI<dag oops, dag iops, InstrItinClass itin, 969 string opc, string asm, list<dag> pattern> 970 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 971 972// Two-address instructions 973class T1pIt<dag oops, dag iops, InstrItinClass itin, 974 string opc, string asm, list<dag> pattern> 975 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 976 "$lhs = $dst", pattern>; 977 978class T1pI1<dag oops, dag iops, InstrItinClass itin, 979 string opc, string asm, list<dag> pattern> 980 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>; 981class T1pI2<dag oops, dag iops, InstrItinClass itin, 982 string opc, string asm, list<dag> pattern> 983 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>; 984class T1pI4<dag oops, dag iops, InstrItinClass itin, 985 string opc, string asm, list<dag> pattern> 986 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>; 987class T1pIs<dag oops, dag iops, 988 InstrItinClass itin, string opc, string asm, list<dag> pattern> 989 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 990 991class Encoding16 : Encoding { 992 let Inst{31-16} = 0x0000; 993} 994 995// A6.2 16-bit Thumb instruction encoding 996class T1Encoding<bits<6> opcode> : Encoding16 { 997 let Inst{15-10} = opcode; 998} 999 1000// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1001class T1General<bits<5> opcode> : Encoding16 { 1002 let Inst{15-14} = 0b00; 1003 let Inst{13-9} = opcode; 1004} 1005 1006// A6.2.2 Data-processing encoding. 1007class T1DataProcessing<bits<4> opcode> : Encoding16 { 1008 let Inst{15-10} = 0b010000; 1009 let Inst{9-6} = opcode; 1010} 1011 1012// A6.2.3 Special data instructions and branch and exchange encoding. 1013class T1Special<bits<4> opcode> : Encoding16 { 1014 let Inst{15-10} = 0b010001; 1015 let Inst{9-6} = opcode; 1016} 1017 1018// A6.2.4 Load/store single data item encoding. 1019class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1020 let Inst{15-12} = opA; 1021 let Inst{11-9} = opB; 1022} 1023class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>; 1024class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes 1025class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte 1026class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes 1027class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1028 1029// A6.2.5 Miscellaneous 16-bit instructions encoding. 1030class T1Misc<bits<7> opcode> : Encoding16 { 1031 let Inst{15-12} = 0b1011; 1032 let Inst{11-5} = opcode; 1033} 1034 1035// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1036class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1037 InstrItinClass itin, 1038 string opc, string asm, string cstr, list<dag> pattern> 1039 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1040 let OutOperandList = oops; 1041 let InOperandList = !con(iops, (ops pred:$p)); 1042 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1043 let Pattern = pattern; 1044 list<Predicate> Predicates = [IsThumb2]; 1045} 1046 1047// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as 1048// an input operand since by default it's a zero register. It will 1049// become an implicit def once it's "flipped". 1050// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1051// more consistent. 1052class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1053 InstrItinClass itin, 1054 string opc, string asm, string cstr, list<dag> pattern> 1055 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1056 let OutOperandList = oops; 1057 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 1058 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 1059 let Pattern = pattern; 1060 list<Predicate> Predicates = [IsThumb2]; 1061} 1062 1063// Special cases 1064class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1065 InstrItinClass itin, 1066 string asm, string cstr, list<dag> pattern> 1067 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1068 let OutOperandList = oops; 1069 let InOperandList = iops; 1070 let AsmString = asm; 1071 let Pattern = pattern; 1072 list<Predicate> Predicates = [IsThumb2]; 1073} 1074 1075class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1076 InstrItinClass itin, 1077 string asm, string cstr, list<dag> pattern> 1078 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1079 let OutOperandList = oops; 1080 let InOperandList = iops; 1081 let AsmString = asm; 1082 let Pattern = pattern; 1083 list<Predicate> Predicates = [IsThumb1Only]; 1084} 1085 1086class T2I<dag oops, dag iops, InstrItinClass itin, 1087 string opc, string asm, list<dag> pattern> 1088 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1089class T2Ii12<dag oops, dag iops, InstrItinClass itin, 1090 string opc, string asm, list<dag> pattern> 1091 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "", pattern>; 1092class T2Ii8<dag oops, dag iops, InstrItinClass itin, 1093 string opc, string asm, list<dag> pattern> 1094 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 1095class T2Iso<dag oops, dag iops, InstrItinClass itin, 1096 string opc, string asm, list<dag> pattern> 1097 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 1098class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1099 string opc, string asm, list<dag> pattern> 1100 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1101class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin, 1102 string opc, string asm, list<dag> pattern> 1103 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1104 pattern> { 1105 let Inst{31-27} = 0b11101; 1106 let Inst{26-25} = 0b00; 1107 let Inst{24} = P; 1108 let Inst{23} = ?; // The U bit. 1109 let Inst{22} = 1; 1110 let Inst{21} = W; 1111 let Inst{20} = load; 1112} 1113 1114class T2sI<dag oops, dag iops, InstrItinClass itin, 1115 string opc, string asm, list<dag> pattern> 1116 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1117 1118class T2XI<dag oops, dag iops, InstrItinClass itin, 1119 string asm, list<dag> pattern> 1120 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1121class T2JTI<dag oops, dag iops, InstrItinClass itin, 1122 string asm, list<dag> pattern> 1123 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1124 1125class T2Ix2<dag oops, dag iops, InstrItinClass itin, 1126 string opc, string asm, list<dag> pattern> 1127 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>; 1128 1129 1130// T2Iidxldst - Thumb2 indexed load / store instructions. 1131class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1132 dag oops, dag iops, 1133 AddrMode am, IndexMode im, InstrItinClass itin, 1134 string opc, string asm, string cstr, list<dag> pattern> 1135 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1136 let OutOperandList = oops; 1137 let InOperandList = !con(iops, (ops pred:$p)); 1138 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1139 let Pattern = pattern; 1140 list<Predicate> Predicates = [IsThumb2]; 1141 let Inst{31-27} = 0b11111; 1142 let Inst{26-25} = 0b00; 1143 let Inst{24} = signed; 1144 let Inst{23} = 0; 1145 let Inst{22-21} = opcod; 1146 let Inst{20} = load; 1147 let Inst{11} = 1; 1148 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1149 let Inst{10} = pre; // The P bit. 1150 let Inst{8} = 1; // The W bit. 1151} 1152 1153// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1154class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1155 list<Predicate> Predicates = [IsThumb1Only, HasV5T]; 1156} 1157 1158// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1159class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1160 list<Predicate> Predicates = [IsThumb1Only]; 1161} 1162 1163// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1164class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1165 list<Predicate> Predicates = [IsThumb2]; 1166} 1167 1168//===----------------------------------------------------------------------===// 1169 1170//===----------------------------------------------------------------------===// 1171// ARM VFP Instruction templates. 1172// 1173 1174// Almost all VFP instructions are predicable. 1175class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1176 IndexMode im, Format f, InstrItinClass itin, 1177 string opc, string asm, string cstr, list<dag> pattern> 1178 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1179 let OutOperandList = oops; 1180 let InOperandList = !con(iops, (ops pred:$p)); 1181 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1182 let Pattern = pattern; 1183 list<Predicate> Predicates = [HasVFP2]; 1184} 1185 1186// Special cases 1187class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1188 IndexMode im, Format f, InstrItinClass itin, 1189 string asm, string cstr, list<dag> pattern> 1190 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1191 let OutOperandList = oops; 1192 let InOperandList = iops; 1193 let AsmString = asm; 1194 let Pattern = pattern; 1195 list<Predicate> Predicates = [HasVFP2]; 1196} 1197 1198class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1199 string opc, string asm, list<dag> pattern> 1200 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1201 opc, asm, "", pattern>; 1202 1203// ARM VFP addrmode5 loads and stores 1204class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1205 InstrItinClass itin, 1206 string opc, string asm, list<dag> pattern> 1207 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1208 VFPLdStFrm, itin, opc, asm, "", pattern> { 1209 // TODO: Mark the instructions with the appropriate subtarget info. 1210 let Inst{27-24} = opcod1; 1211 let Inst{21-20} = opcod2; 1212 let Inst{11-8} = 0b1011; 1213 1214 // 64-bit loads & stores operate on both NEON and VFP pipelines. 1215 let Dom = VFPNeonDomain.Value; 1216} 1217 1218class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1219 InstrItinClass itin, 1220 string opc, string asm, list<dag> pattern> 1221 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1222 VFPLdStFrm, itin, opc, asm, "", pattern> { 1223 // TODO: Mark the instructions with the appropriate subtarget info. 1224 let Inst{27-24} = opcod1; 1225 let Inst{21-20} = opcod2; 1226 let Inst{11-8} = 0b1010; 1227} 1228 1229// Load / store multiple 1230class AXDI5<dag oops, dag iops, InstrItinClass itin, 1231 string asm, list<dag> pattern> 1232 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1233 VFPLdStMulFrm, itin, asm, "", pattern> { 1234 // TODO: Mark the instructions with the appropriate subtarget info. 1235 let Inst{27-25} = 0b110; 1236 let Inst{11-8} = 0b1011; 1237 1238 // 64-bit loads & stores operate on both NEON and VFP pipelines. 1239 let Dom = VFPNeonDomain.Value; 1240} 1241 1242class AXSI5<dag oops, dag iops, InstrItinClass itin, 1243 string asm, list<dag> pattern> 1244 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1245 VFPLdStMulFrm, itin, asm, "", pattern> { 1246 // TODO: Mark the instructions with the appropriate subtarget info. 1247 let Inst{27-25} = 0b110; 1248 let Inst{11-8} = 0b1010; 1249} 1250 1251// Double precision, unary 1252class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1253 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1254 string asm, list<dag> pattern> 1255 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1256 let Inst{27-23} = opcod1; 1257 let Inst{21-20} = opcod2; 1258 let Inst{19-16} = opcod3; 1259 let Inst{11-8} = 0b1011; 1260 let Inst{7-6} = opcod4; 1261 let Inst{4} = opcod5; 1262} 1263 1264// Double precision, binary 1265class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1266 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 1267 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1268 let Inst{27-23} = opcod1; 1269 let Inst{21-20} = opcod2; 1270 let Inst{11-8} = 0b1011; 1271 let Inst{6} = op6; 1272 let Inst{4} = op4; 1273} 1274 1275// Single precision, unary 1276class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1277 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1278 string asm, list<dag> pattern> 1279 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1280 let Inst{27-23} = opcod1; 1281 let Inst{21-20} = opcod2; 1282 let Inst{19-16} = opcod3; 1283 let Inst{11-8} = 0b1010; 1284 let Inst{7-6} = opcod4; 1285 let Inst{4} = opcod5; 1286} 1287 1288// Single precision unary, if no NEON 1289// Same as ASuI except not available if NEON is enabled 1290class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1291 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1292 string asm, list<dag> pattern> 1293 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1294 pattern> { 1295 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1296} 1297 1298// Single precision, binary 1299class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1300 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1301 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1302 let Inst{27-23} = opcod1; 1303 let Inst{21-20} = opcod2; 1304 let Inst{11-8} = 0b1010; 1305 let Inst{6} = op6; 1306 let Inst{4} = op4; 1307} 1308 1309// Single precision binary, if no NEON 1310// Same as ASbI except not available if NEON is enabled 1311class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1312 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 1313 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1314 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1315} 1316 1317// VFP conversion instructions 1318class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1319 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1320 list<dag> pattern> 1321 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1322 let Inst{27-23} = opcod1; 1323 let Inst{21-20} = opcod2; 1324 let Inst{19-16} = opcod3; 1325 let Inst{11-8} = opcod4; 1326 let Inst{6} = 1; 1327 let Inst{4} = 0; 1328} 1329 1330// VFP conversion between floating-point and fixed-point 1331class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1332 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1333 list<dag> pattern> 1334 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1335 // size (fixed-point number): sx == 0 ? 16 : 32 1336 let Inst{7} = op5; // sx 1337} 1338 1339// VFP conversion instructions, if no NEON 1340class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1341 dag oops, dag iops, InstrItinClass itin, 1342 string opc, string asm, list<dag> pattern> 1343 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1344 pattern> { 1345 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1346} 1347 1348class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1349 InstrItinClass itin, 1350 string opc, string asm, list<dag> pattern> 1351 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1352 let Inst{27-20} = opcod1; 1353 let Inst{11-8} = opcod2; 1354 let Inst{4} = 1; 1355} 1356 1357class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1358 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1359 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1360 1361class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1362 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1363 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1364 1365class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1366 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1367 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1368 1369class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1370 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1371 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1372 1373//===----------------------------------------------------------------------===// 1374 1375//===----------------------------------------------------------------------===// 1376// ARM NEON Instruction templates. 1377// 1378 1379class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, 1380 string opc, string dt, string asm, string cstr, list<dag> pattern> 1381 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> { 1382 let OutOperandList = oops; 1383 let InOperandList = !con(iops, (ops pred:$p)); 1384 let AsmString = !strconcat( 1385 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), 1386 !strconcat("\t", asm)); 1387 let Pattern = pattern; 1388 list<Predicate> Predicates = [HasNEON]; 1389} 1390 1391// Same as NeonI except it does not have a "data type" specifier. 1392class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, 1393 string opc, string asm, string cstr, list<dag> pattern> 1394 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> { 1395 let OutOperandList = oops; 1396 let InOperandList = !con(iops, (ops pred:$p)); 1397 let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm)); 1398 let Pattern = pattern; 1399 list<Predicate> Predicates = [HasNEON]; 1400} 1401 1402class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1403 list<dag> pattern> 1404 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "", 1405 pattern> { 1406} 1407 1408class NI4<dag oops, dag iops, InstrItinClass itin, string opc, 1409 string asm, list<dag> pattern> 1410 : NeonXI<oops, iops, AddrMode4, IndexModeNone, itin, opc, asm, "", 1411 pattern> { 1412} 1413 1414class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1415 dag oops, dag iops, InstrItinClass itin, 1416 string opc, string dt, string asm, string cstr, list<dag> pattern> 1417 : NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, dt, asm, cstr, 1418 pattern> { 1419 let Inst{31-24} = 0b11110100; 1420 let Inst{23} = op23; 1421 let Inst{21-20} = op21_20; 1422 let Inst{11-8} = op11_8; 1423 let Inst{7-4} = op7_4; 1424} 1425 1426class NDataI<dag oops, dag iops, InstrItinClass itin, 1427 string opc, string dt, string asm, string cstr, list<dag> pattern> 1428 : NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, dt, asm, 1429 cstr, pattern> { 1430 let Inst{31-25} = 0b1111001; 1431} 1432 1433class NDataXI<dag oops, dag iops, InstrItinClass itin, 1434 string opc, string asm, string cstr, list<dag> pattern> 1435 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, 1436 cstr, pattern> { 1437 let Inst{31-25} = 0b1111001; 1438} 1439 1440// NEON "one register and a modified immediate" format. 1441class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1442 bit op5, bit op4, 1443 dag oops, dag iops, InstrItinClass itin, 1444 string opc, string dt, string asm, string cstr, list<dag> pattern> 1445 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1446 let Inst{23} = op23; 1447 let Inst{21-19} = op21_19; 1448 let Inst{11-8} = op11_8; 1449 let Inst{7} = op7; 1450 let Inst{6} = op6; 1451 let Inst{5} = op5; 1452 let Inst{4} = op4; 1453} 1454 1455// NEON 2 vector register format. 1456class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1457 bits<5> op11_7, bit op6, bit op4, 1458 dag oops, dag iops, InstrItinClass itin, 1459 string opc, string dt, string asm, string cstr, list<dag> pattern> 1460 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1461 let Inst{24-23} = op24_23; 1462 let Inst{21-20} = op21_20; 1463 let Inst{19-18} = op19_18; 1464 let Inst{17-16} = op17_16; 1465 let Inst{11-7} = op11_7; 1466 let Inst{6} = op6; 1467 let Inst{4} = op4; 1468} 1469 1470// Same as N2V except it doesn't have a datatype suffix. 1471class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1472 bits<5> op11_7, bit op6, bit op4, 1473 dag oops, dag iops, InstrItinClass itin, 1474 string opc, string asm, string cstr, list<dag> pattern> 1475 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> { 1476 let Inst{24-23} = op24_23; 1477 let Inst{21-20} = op21_20; 1478 let Inst{19-18} = op19_18; 1479 let Inst{17-16} = op17_16; 1480 let Inst{11-7} = op11_7; 1481 let Inst{6} = op6; 1482 let Inst{4} = op4; 1483} 1484 1485// NEON 2 vector register with immediate. 1486class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1487 dag oops, dag iops, InstrItinClass itin, 1488 string opc, string dt, string asm, string cstr, list<dag> pattern> 1489 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1490 let Inst{24} = op24; 1491 let Inst{23} = op23; 1492 let Inst{11-8} = op11_8; 1493 let Inst{7} = op7; 1494 let Inst{6} = op6; 1495 let Inst{4} = op4; 1496} 1497 1498// NEON 3 vector register format. 1499class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1500 dag oops, dag iops, InstrItinClass itin, 1501 string opc, string dt, string asm, string cstr, list<dag> pattern> 1502 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1503 let Inst{24} = op24; 1504 let Inst{23} = op23; 1505 let Inst{21-20} = op21_20; 1506 let Inst{11-8} = op11_8; 1507 let Inst{6} = op6; 1508 let Inst{4} = op4; 1509} 1510 1511// Same as N3VX except it doesn't have a data type suffix. 1512class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1513 dag oops, dag iops, InstrItinClass itin, 1514 string opc, string asm, string cstr, list<dag> pattern> 1515 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> { 1516 let Inst{24} = op24; 1517 let Inst{23} = op23; 1518 let Inst{21-20} = op21_20; 1519 let Inst{11-8} = op11_8; 1520 let Inst{6} = op6; 1521 let Inst{4} = op4; 1522} 1523 1524// NEON VMOVs between scalar and core registers. 1525class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1526 dag oops, dag iops, Format f, InstrItinClass itin, 1527 string opc, string dt, string asm, list<dag> pattern> 1528 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain, 1529 "", itin> { 1530 let Inst{27-20} = opcod1; 1531 let Inst{11-8} = opcod2; 1532 let Inst{6-5} = opcod3; 1533 let Inst{4} = 1; 1534 1535 let OutOperandList = oops; 1536 let InOperandList = !con(iops, (ops pred:$p)); 1537 let AsmString = !strconcat( 1538 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), 1539 !strconcat("\t", asm)); 1540 let Pattern = pattern; 1541 list<Predicate> Predicates = [HasNEON]; 1542} 1543class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1544 dag oops, dag iops, InstrItinClass itin, 1545 string opc, string dt, string asm, list<dag> pattern> 1546 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin, 1547 opc, dt, asm, pattern>; 1548class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1549 dag oops, dag iops, InstrItinClass itin, 1550 string opc, string dt, string asm, list<dag> pattern> 1551 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin, 1552 opc, dt, asm, pattern>; 1553class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1554 dag oops, dag iops, InstrItinClass itin, 1555 string opc, string dt, string asm, list<dag> pattern> 1556 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin, 1557 opc, dt, asm, pattern>; 1558 1559// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1560// for single-precision FP. 1561class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1562 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1563} 1564