ARMInstrFormats.td revision 193323
1178476Sjb//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// 2178476Sjb// 3178476Sjb// The LLVM Compiler Infrastructure 4178476Sjb// 5178476Sjb// This file is distributed under the University of Illinois Open Source 6178476Sjb// License. See LICENSE.TXT for details. 7178476Sjb// 8178476Sjb//===----------------------------------------------------------------------===// 9178476Sjb 10178476Sjb//===----------------------------------------------------------------------===// 11178476Sjb// 12178476Sjb// ARM Instruction Format Definitions. 13178476Sjb// 14178476Sjb 15178476Sjb// Format specifies the encoding used by the instruction. This is part of the 16178476Sjb// ad-hoc solution used to emit machine instruction encodings by our machine 17178476Sjb// code emitter. 18178476Sjbclass Format<bits<5> val> { 19178476Sjb bits<5> Value = val; 20178476Sjb} 21178476Sjb 22178476Sjbdef Pseudo : Format<0>; 23178476Sjbdef MulFrm : Format<1>; 24178476Sjbdef BrFrm : Format<2>; 25178476Sjbdef BrMiscFrm : Format<3>; 26178476Sjb 27178476Sjbdef DPFrm : Format<4>; 28178476Sjbdef DPSoRegFrm : Format<5>; 29178476Sjb 30178476Sjbdef LdFrm : Format<6>; 31178476Sjbdef StFrm : Format<7>; 32178476Sjbdef LdMiscFrm : Format<8>; 33178476Sjbdef StMiscFrm : Format<9>; 34178476Sjbdef LdStMulFrm : Format<10>; 35178476Sjb 36178476Sjbdef ArithMiscFrm : Format<11>; 37178476Sjbdef ExtFrm : Format<12>; 38178476Sjb 39178476Sjbdef VFPUnaryFrm : Format<13>; 40178476Sjbdef VFPBinaryFrm : Format<14>; 41178476Sjbdef VFPConv1Frm : Format<15>; 42178476Sjbdef VFPConv2Frm : Format<16>; 43178476Sjbdef VFPConv3Frm : Format<17>; 44178476Sjbdef VFPConv4Frm : Format<18>; 45178476Sjbdef VFPConv5Frm : Format<19>; 46211545Srpaulodef VFPLdStFrm : Format<20>; 47178476Sjbdef VFPLdStMulFrm : Format<21>; 48178476Sjbdef VFPMiscFrm : Format<22>; 49178476Sjb 50178476Sjbdef ThumbFrm : Format<23>; 51178476Sjb 52178476Sjb// Misc flag for data processing instructions that indicates whether 53178476Sjb// the instruction has a Rn register operand. 54178476Sjbclass UnaryDP { bit isUnaryDataProc = 1; } 55178476Sjb 56178476Sjb//===----------------------------------------------------------------------===// 57178476Sjb 58178476Sjb// ARM Instruction templates. 59178476Sjb// 60178476Sjb 61178476Sjbclass InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 62178476Sjb Format f, string cstr> 63178476Sjb : Instruction { 64178476Sjb field bits<32> Inst; 65178476Sjb 66178476Sjb let Namespace = "ARM"; 67178476Sjb 68178476Sjb // TSFlagsFields 69178476Sjb AddrMode AM = am; 70178476Sjb bits<4> AddrModeBits = AM.Value; 71178476Sjb 72178476Sjb SizeFlagVal SZ = sz; 73211545Srpaulo bits<3> SizeFlag = SZ.Value; 74178476Sjb 75178476Sjb IndexMode IM = im; 76178476Sjb bits<2> IndexModeBits = IM.Value; 77178476Sjb 78178476Sjb Format F = f; 79178476Sjb bits<5> Form = F.Value; 80211545Srpaulo 81178476Sjb // 82178476Sjb // Attributes specific to ARM instructions... 83178476Sjb // 84178476Sjb bit isUnaryDataProc = 0; 85178476Sjb 86178476Sjb let Constraints = cstr; 87178476Sjb} 88178476Sjb 89178476Sjbclass PseudoInst<dag oops, dag iops, string asm, list<dag> pattern> 90178476Sjb : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> { 91178476Sjb let OutOperandList = oops; 92178476Sjb let InOperandList = iops; 93178476Sjb let AsmString = asm; 94178476Sjb let Pattern = pattern; 95178476Sjb} 96211545Srpaulo 97178476Sjb// Almost all ARM instructions are predicable. 98class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 99 IndexMode im, Format f, string opc, string asm, string cstr, 100 list<dag> pattern> 101 : InstARM<am, sz, im, f, cstr> { 102 let OutOperandList = oops; 103 let InOperandList = !con(iops, (ops pred:$p)); 104 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 105 let Pattern = pattern; 106 list<Predicate> Predicates = [IsARM]; 107} 108 109// Same as I except it can optionally modify CPSR. Note it's modeled as 110// an input operand since by default it's a zero register. It will 111// become an implicit def once it's "flipped". 112class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 113 IndexMode im, Format f, string opc, string asm, string cstr, 114 list<dag> pattern> 115 : InstARM<am, sz, im, f, cstr> { 116 let OutOperandList = oops; 117 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 118 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); 119 let Pattern = pattern; 120 list<Predicate> Predicates = [IsARM]; 121} 122 123// Special cases 124class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 125 IndexMode im, Format f, string asm, string cstr, list<dag> pattern> 126 : InstARM<am, sz, im, f, cstr> { 127 let OutOperandList = oops; 128 let InOperandList = iops; 129 let AsmString = asm; 130 let Pattern = pattern; 131 list<Predicate> Predicates = [IsARM]; 132} 133 134class AI<dag oops, dag iops, Format f, string opc, 135 string asm, list<dag> pattern> 136 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 137 asm, "", pattern>; 138class AsI<dag oops, dag iops, Format f, string opc, 139 string asm, list<dag> pattern> 140 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 141 asm, "", pattern>; 142class AXI<dag oops, dag iops, Format f, string asm, 143 list<dag> pattern> 144 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, 145 "", pattern>; 146 147// Ctrl flow instructions 148class ABI<bits<4> opcod, dag oops, dag iops, string opc, 149 string asm, list<dag> pattern> 150 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc, 151 asm, "", pattern> { 152 let Inst{27-24} = opcod; 153} 154class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> 155 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm, 156 "", pattern> { 157 let Inst{27-24} = opcod; 158} 159class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern> 160 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm, 161 "", pattern>; 162 163// BR_JT instructions 164class JTI<dag oops, dag iops, string asm, list<dag> pattern> 165 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, 166 asm, "", pattern>; 167 168// addrmode1 instructions 169class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, 170 string asm, list<dag> pattern> 171 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, 172 asm, "", pattern> { 173 let Inst{24-21} = opcod; 174 let Inst{27-26} = {0,0}; 175} 176class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, 177 string asm, list<dag> pattern> 178 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, 179 asm, "", pattern> { 180 let Inst{24-21} = opcod; 181 let Inst{27-26} = {0,0}; 182} 183class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm, 184 list<dag> pattern> 185 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm, 186 "", pattern> { 187 let Inst{24-21} = opcod; 188 let Inst{27-26} = {0,0}; 189} 190class AI1x2<dag oops, dag iops, Format f, string opc, 191 string asm, list<dag> pattern> 192 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc, 193 asm, "", pattern>; 194 195 196// addrmode2 loads and stores 197class AI2<dag oops, dag iops, Format f, string opc, 198 string asm, list<dag> pattern> 199 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 200 asm, "", pattern> { 201 let Inst{27-26} = {0,1}; 202} 203 204// loads 205class AI2ldw<dag oops, dag iops, Format f, string opc, 206 string asm, list<dag> pattern> 207 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 208 asm, "", pattern> { 209 let Inst{20} = 1; // L bit 210 let Inst{21} = 0; // W bit 211 let Inst{22} = 0; // B bit 212 let Inst{24} = 1; // P bit 213 let Inst{27-26} = {0,1}; 214} 215class AXI2ldw<dag oops, dag iops, Format f, string asm, 216 list<dag> pattern> 217 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 218 asm, "", pattern> { 219 let Inst{20} = 1; // L bit 220 let Inst{21} = 0; // W bit 221 let Inst{22} = 0; // B bit 222 let Inst{24} = 1; // P bit 223 let Inst{27-26} = {0,1}; 224} 225class AI2ldb<dag oops, dag iops, Format f, string opc, 226 string asm, list<dag> pattern> 227 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 228 asm, "", pattern> { 229 let Inst{20} = 1; // L bit 230 let Inst{21} = 0; // W bit 231 let Inst{22} = 1; // B bit 232 let Inst{24} = 1; // P bit 233 let Inst{27-26} = {0,1}; 234} 235class AXI2ldb<dag oops, dag iops, Format f, string asm, 236 list<dag> pattern> 237 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 238 asm, "", pattern> { 239 let Inst{20} = 1; // L bit 240 let Inst{21} = 0; // W bit 241 let Inst{22} = 1; // B bit 242 let Inst{24} = 1; // P bit 243 let Inst{27-26} = {0,1}; 244} 245 246// stores 247class AI2stw<dag oops, dag iops, Format f, string opc, 248 string asm, list<dag> pattern> 249 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 250 asm, "", pattern> { 251 let Inst{20} = 0; // L bit 252 let Inst{21} = 0; // W bit 253 let Inst{22} = 0; // B bit 254 let Inst{24} = 1; // P bit 255 let Inst{27-26} = {0,1}; 256} 257class AXI2stw<dag oops, dag iops, Format f, string asm, 258 list<dag> pattern> 259 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 260 asm, "", pattern> { 261 let Inst{20} = 0; // L bit 262 let Inst{21} = 0; // W bit 263 let Inst{22} = 0; // B bit 264 let Inst{24} = 1; // P bit 265 let Inst{27-26} = {0,1}; 266} 267class AI2stb<dag oops, dag iops, Format f, string opc, 268 string asm, list<dag> pattern> 269 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 270 asm, "", pattern> { 271 let Inst{20} = 0; // L bit 272 let Inst{21} = 0; // W bit 273 let Inst{22} = 1; // B bit 274 let Inst{24} = 1; // P bit 275 let Inst{27-26} = {0,1}; 276} 277class AXI2stb<dag oops, dag iops, Format f, string asm, 278 list<dag> pattern> 279 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 280 asm, "", pattern> { 281 let Inst{20} = 0; // L bit 282 let Inst{21} = 0; // W bit 283 let Inst{22} = 1; // B bit 284 let Inst{24} = 1; // P bit 285 let Inst{27-26} = {0,1}; 286} 287 288// Pre-indexed loads 289class AI2ldwpr<dag oops, dag iops, Format f, string opc, 290 string asm, string cstr, list<dag> pattern> 291 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 292 asm, cstr, pattern> { 293 let Inst{20} = 1; // L bit 294 let Inst{21} = 1; // W bit 295 let Inst{22} = 0; // B bit 296 let Inst{24} = 1; // P bit 297 let Inst{27-26} = {0,1}; 298} 299class AI2ldbpr<dag oops, dag iops, Format f, string opc, 300 string asm, string cstr, list<dag> pattern> 301 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 302 asm, cstr, pattern> { 303 let Inst{20} = 1; // L bit 304 let Inst{21} = 1; // W bit 305 let Inst{22} = 1; // B bit 306 let Inst{24} = 1; // P bit 307 let Inst{27-26} = {0,1}; 308} 309 310// Pre-indexed stores 311class AI2stwpr<dag oops, dag iops, Format f, string opc, 312 string asm, string cstr, list<dag> pattern> 313 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 314 asm, cstr, pattern> { 315 let Inst{20} = 0; // L bit 316 let Inst{21} = 1; // W bit 317 let Inst{22} = 0; // B bit 318 let Inst{24} = 1; // P bit 319 let Inst{27-26} = {0,1}; 320} 321class AI2stbpr<dag oops, dag iops, Format f, string opc, 322 string asm, string cstr, list<dag> pattern> 323 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 324 asm, cstr, pattern> { 325 let Inst{20} = 0; // L bit 326 let Inst{21} = 1; // W bit 327 let Inst{22} = 1; // B bit 328 let Inst{24} = 1; // P bit 329 let Inst{27-26} = {0,1}; 330} 331 332// Post-indexed loads 333class AI2ldwpo<dag oops, dag iops, Format f, string opc, 334 string asm, string cstr, list<dag> pattern> 335 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 336 asm, cstr,pattern> { 337 let Inst{20} = 1; // L bit 338 let Inst{21} = 0; // W bit 339 let Inst{22} = 0; // B bit 340 let Inst{24} = 0; // P bit 341 let Inst{27-26} = {0,1}; 342} 343class AI2ldbpo<dag oops, dag iops, Format f, string opc, 344 string asm, string cstr, list<dag> pattern> 345 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 346 asm, cstr,pattern> { 347 let Inst{20} = 1; // L bit 348 let Inst{21} = 0; // W bit 349 let Inst{22} = 1; // B bit 350 let Inst{24} = 0; // P bit 351 let Inst{27-26} = {0,1}; 352} 353 354// Post-indexed stores 355class AI2stwpo<dag oops, dag iops, Format f, string opc, 356 string asm, string cstr, list<dag> pattern> 357 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 358 asm, cstr,pattern> { 359 let Inst{20} = 0; // L bit 360 let Inst{21} = 0; // W bit 361 let Inst{22} = 0; // B bit 362 let Inst{24} = 0; // P bit 363 let Inst{27-26} = {0,1}; 364} 365class AI2stbpo<dag oops, dag iops, Format f, string opc, 366 string asm, string cstr, list<dag> pattern> 367 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 368 asm, cstr,pattern> { 369 let Inst{20} = 0; // L bit 370 let Inst{21} = 0; // W bit 371 let Inst{22} = 1; // B bit 372 let Inst{24} = 0; // P bit 373 let Inst{27-26} = {0,1}; 374} 375 376// addrmode3 instructions 377class AI3<dag oops, dag iops, Format f, string opc, 378 string asm, list<dag> pattern> 379 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 380 asm, "", pattern>; 381class AXI3<dag oops, dag iops, Format f, string asm, 382 list<dag> pattern> 383 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, 384 "", pattern>; 385 386// loads 387class AI3ldh<dag oops, dag iops, Format f, string opc, 388 string asm, list<dag> pattern> 389 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 390 asm, "", pattern> { 391 let Inst{4} = 1; 392 let Inst{5} = 1; // H bit 393 let Inst{6} = 0; // S bit 394 let Inst{7} = 1; 395 let Inst{20} = 1; // L bit 396 let Inst{21} = 0; // W bit 397 let Inst{24} = 1; // P bit 398} 399class AXI3ldh<dag oops, dag iops, Format f, string asm, 400 list<dag> pattern> 401 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 402 asm, "", pattern> { 403 let Inst{4} = 1; 404 let Inst{5} = 1; // H bit 405 let Inst{6} = 0; // S bit 406 let Inst{7} = 1; 407 let Inst{20} = 1; // L bit 408 let Inst{21} = 0; // W bit 409 let Inst{24} = 1; // P bit 410} 411class AI3ldsh<dag oops, dag iops, Format f, string opc, 412 string asm, list<dag> pattern> 413 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 414 asm, "", pattern> { 415 let Inst{4} = 1; 416 let Inst{5} = 1; // H bit 417 let Inst{6} = 1; // S bit 418 let Inst{7} = 1; 419 let Inst{20} = 1; // L bit 420 let Inst{21} = 0; // W bit 421 let Inst{24} = 1; // P bit 422} 423class AXI3ldsh<dag oops, dag iops, Format f, string asm, 424 list<dag> pattern> 425 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 426 asm, "", pattern> { 427 let Inst{4} = 1; 428 let Inst{5} = 1; // H bit 429 let Inst{6} = 1; // S bit 430 let Inst{7} = 1; 431 let Inst{20} = 1; // L bit 432 let Inst{21} = 0; // W bit 433 let Inst{24} = 1; // P bit 434} 435class AI3ldsb<dag oops, dag iops, Format f, string opc, 436 string asm, list<dag> pattern> 437 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 438 asm, "", pattern> { 439 let Inst{4} = 1; 440 let Inst{5} = 0; // H bit 441 let Inst{6} = 1; // S bit 442 let Inst{7} = 1; 443 let Inst{20} = 1; // L bit 444 let Inst{21} = 0; // W bit 445 let Inst{24} = 1; // P bit 446} 447class AXI3ldsb<dag oops, dag iops, Format f, string asm, 448 list<dag> pattern> 449 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 450 asm, "", pattern> { 451 let Inst{4} = 1; 452 let Inst{5} = 0; // H bit 453 let Inst{6} = 1; // S bit 454 let Inst{7} = 1; 455 let Inst{20} = 1; // L bit 456 let Inst{21} = 0; // W bit 457 let Inst{24} = 1; // P bit 458} 459class AI3ldd<dag oops, dag iops, Format f, string opc, 460 string asm, list<dag> pattern> 461 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 462 asm, "", pattern> { 463 let Inst{4} = 1; 464 let Inst{5} = 0; // H bit 465 let Inst{6} = 1; // S bit 466 let Inst{7} = 1; 467 let Inst{20} = 0; // L bit 468 let Inst{21} = 0; // W bit 469 let Inst{24} = 1; // P bit 470} 471 472// stores 473class AI3sth<dag oops, dag iops, Format f, string opc, 474 string asm, list<dag> pattern> 475 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 476 asm, "", pattern> { 477 let Inst{4} = 1; 478 let Inst{5} = 1; // H bit 479 let Inst{6} = 0; // S bit 480 let Inst{7} = 1; 481 let Inst{20} = 0; // L bit 482 let Inst{21} = 0; // W bit 483 let Inst{24} = 1; // P bit 484} 485class AXI3sth<dag oops, dag iops, Format f, string asm, 486 list<dag> pattern> 487 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 488 asm, "", pattern> { 489 let Inst{4} = 1; 490 let Inst{5} = 1; // H bit 491 let Inst{6} = 0; // S bit 492 let Inst{7} = 1; 493 let Inst{20} = 0; // L bit 494 let Inst{21} = 0; // W bit 495 let Inst{24} = 1; // P bit 496} 497class AI3std<dag oops, dag iops, Format f, string opc, 498 string asm, list<dag> pattern> 499 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 500 asm, "", pattern> { 501 let Inst{4} = 1; 502 let Inst{5} = 1; // H bit 503 let Inst{6} = 1; // S bit 504 let Inst{7} = 1; 505 let Inst{20} = 0; // L bit 506 let Inst{21} = 0; // W bit 507 let Inst{24} = 1; // P bit 508} 509 510// Pre-indexed loads 511class AI3ldhpr<dag oops, dag iops, Format f, string opc, 512 string asm, string cstr, list<dag> pattern> 513 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 514 asm, cstr, pattern> { 515 let Inst{4} = 1; 516 let Inst{5} = 1; // H bit 517 let Inst{6} = 0; // S bit 518 let Inst{7} = 1; 519 let Inst{20} = 1; // L bit 520 let Inst{21} = 1; // W bit 521 let Inst{24} = 1; // P bit 522} 523class AI3ldshpr<dag oops, dag iops, Format f, string opc, 524 string asm, string cstr, list<dag> pattern> 525 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 526 asm, cstr, pattern> { 527 let Inst{4} = 1; 528 let Inst{5} = 1; // H bit 529 let Inst{6} = 1; // S bit 530 let Inst{7} = 1; 531 let Inst{20} = 1; // L bit 532 let Inst{21} = 1; // W bit 533 let Inst{24} = 1; // P bit 534} 535class AI3ldsbpr<dag oops, dag iops, Format f, string opc, 536 string asm, string cstr, list<dag> pattern> 537 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 538 asm, cstr, pattern> { 539 let Inst{4} = 1; 540 let Inst{5} = 0; // H bit 541 let Inst{6} = 1; // S bit 542 let Inst{7} = 1; 543 let Inst{20} = 1; // L bit 544 let Inst{21} = 1; // W bit 545 let Inst{24} = 1; // P bit 546} 547 548// Pre-indexed stores 549class AI3sthpr<dag oops, dag iops, Format f, string opc, 550 string asm, string cstr, list<dag> pattern> 551 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 552 asm, cstr, pattern> { 553 let Inst{4} = 1; 554 let Inst{5} = 1; // H bit 555 let Inst{6} = 0; // S bit 556 let Inst{7} = 1; 557 let Inst{20} = 0; // L bit 558 let Inst{21} = 1; // W bit 559 let Inst{24} = 1; // P bit 560} 561 562// Post-indexed loads 563class AI3ldhpo<dag oops, dag iops, Format f, string opc, 564 string asm, string cstr, list<dag> pattern> 565 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 566 asm, cstr,pattern> { 567 let Inst{4} = 1; 568 let Inst{5} = 1; // H bit 569 let Inst{6} = 0; // S bit 570 let Inst{7} = 1; 571 let Inst{20} = 1; // L bit 572 let Inst{21} = 1; // W bit 573 let Inst{24} = 0; // P bit 574} 575class AI3ldshpo<dag oops, dag iops, Format f, string opc, 576 string asm, string cstr, list<dag> pattern> 577 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 578 asm, cstr,pattern> { 579 let Inst{4} = 1; 580 let Inst{5} = 1; // H bit 581 let Inst{6} = 1; // S bit 582 let Inst{7} = 1; 583 let Inst{20} = 1; // L bit 584 let Inst{21} = 1; // W bit 585 let Inst{24} = 0; // P bit 586} 587class AI3ldsbpo<dag oops, dag iops, Format f, string opc, 588 string asm, string cstr, list<dag> pattern> 589 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 590 asm, cstr,pattern> { 591 let Inst{4} = 1; 592 let Inst{5} = 0; // H bit 593 let Inst{6} = 1; // S bit 594 let Inst{7} = 1; 595 let Inst{20} = 1; // L bit 596 let Inst{21} = 1; // W bit 597 let Inst{24} = 0; // P bit 598} 599 600// Post-indexed stores 601class AI3sthpo<dag oops, dag iops, Format f, string opc, 602 string asm, string cstr, list<dag> pattern> 603 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 604 asm, cstr,pattern> { 605 let Inst{4} = 1; 606 let Inst{5} = 1; // H bit 607 let Inst{6} = 0; // S bit 608 let Inst{7} = 1; 609 let Inst{20} = 0; // L bit 610 let Inst{21} = 1; // W bit 611 let Inst{24} = 0; // P bit 612} 613 614 615// addrmode4 instructions 616class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern> 617 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, 618 "", pattern> { 619 let Inst{20} = 1; // L bit 620 let Inst{22} = 0; // S bit 621 let Inst{27-25} = 0b100; 622} 623class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern> 624 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, 625 "", pattern> { 626 let Inst{20} = 0; // L bit 627 let Inst{22} = 0; // S bit 628 let Inst{27-25} = 0b100; 629} 630 631// Unsigned multiply, multiply-accumulate instructions. 632class AMul1I<bits<7> opcod, dag oops, dag iops, string opc, 633 string asm, list<dag> pattern> 634 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 635 asm, "", pattern> { 636 let Inst{7-4} = 0b1001; 637 let Inst{20} = 0; // S bit 638 let Inst{27-21} = opcod; 639} 640class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc, 641 string asm, list<dag> pattern> 642 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 643 asm, "", pattern> { 644 let Inst{7-4} = 0b1001; 645 let Inst{27-21} = opcod; 646} 647 648// Most significant word multiply 649class AMul2I<bits<7> opcod, dag oops, dag iops, string opc, 650 string asm, list<dag> pattern> 651 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 652 asm, "", pattern> { 653 let Inst{7-4} = 0b1001; 654 let Inst{20} = 1; 655 let Inst{27-21} = opcod; 656} 657 658// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 659class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc, 660 string asm, list<dag> pattern> 661 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 662 asm, "", pattern> { 663 let Inst{4} = 0; 664 let Inst{7} = 1; 665 let Inst{20} = 0; 666 let Inst{27-21} = opcod; 667} 668 669// Extend instructions. 670class AExtI<bits<8> opcod, dag oops, dag iops, string opc, 671 string asm, list<dag> pattern> 672 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, opc, 673 asm, "", pattern> { 674 let Inst{7-4} = 0b0111; 675 let Inst{27-20} = opcod; 676} 677 678// Misc Arithmetic instructions. 679class AMiscA1I<bits<8> opcod, dag oops, dag iops, string opc, 680 string asm, list<dag> pattern> 681 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, opc, 682 asm, "", pattern> { 683 let Inst{27-20} = opcod; 684} 685 686//===----------------------------------------------------------------------===// 687 688// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 689class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 690 list<Predicate> Predicates = [IsARM]; 691} 692class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 693 list<Predicate> Predicates = [IsARM, HasV5TE]; 694} 695class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 696 list<Predicate> Predicates = [IsARM, HasV6]; 697} 698 699//===----------------------------------------------------------------------===// 700// 701// Thumb Instruction Format Definitions. 702// 703 704 705// TI - Thumb instruction. 706 707class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz, 708 string asm, string cstr, list<dag> pattern> 709 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 710 let OutOperandList = outs; 711 let InOperandList = ins; 712 let AsmString = asm; 713 let Pattern = pattern; 714 list<Predicate> Predicates = [IsThumb]; 715} 716 717class TI<dag outs, dag ins, string asm, list<dag> pattern> 718 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>; 719class TI1<dag outs, dag ins, string asm, list<dag> pattern> 720 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>; 721class TI2<dag outs, dag ins, string asm, list<dag> pattern> 722 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>; 723class TI4<dag outs, dag ins, string asm, list<dag> pattern> 724 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>; 725class TIs<dag outs, dag ins, string asm, list<dag> pattern> 726 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>; 727 728// Two-address instructions 729class TIt<dag outs, dag ins, string asm, list<dag> pattern> 730 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>; 731 732// BL, BLX(1) are translated by assembler into two instructions 733class TIx2<dag outs, dag ins, string asm, list<dag> pattern> 734 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>; 735 736// BR_JT instructions 737class TJTI<dag outs, dag ins, string asm, list<dag> pattern> 738 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>; 739 740 741//===----------------------------------------------------------------------===// 742 743//===----------------------------------------------------------------------===// 744// ARM VFP Instruction templates. 745// 746 747// ARM VFP addrmode5 loads and stores 748class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 749 string opc, string asm, list<dag> pattern> 750 : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 751 VFPLdStFrm, opc, asm, "", pattern> { 752 // TODO: Mark the instructions with the appropriate subtarget info. 753 let Inst{27-24} = opcod1; 754 let Inst{21-20} = opcod2; 755 let Inst{11-8} = 0b1011; 756} 757 758class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 759 string opc, string asm, list<dag> pattern> 760 : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 761 VFPLdStFrm, opc, asm, "", pattern> { 762 // TODO: Mark the instructions with the appropriate subtarget info. 763 let Inst{27-24} = opcod1; 764 let Inst{21-20} = opcod2; 765 let Inst{11-8} = 0b1010; 766} 767 768// Load / store multiple 769class AXSI5<dag oops, dag iops, string asm, list<dag> pattern> 770 : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 771 VFPLdStMulFrm, asm, "", pattern> { 772 // TODO: Mark the instructions with the appropriate subtarget info. 773 let Inst{27-25} = 0b110; 774 let Inst{11-8} = 0b1011; 775} 776 777class AXDI5<dag oops, dag iops, string asm, list<dag> pattern> 778 : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 779 VFPLdStMulFrm, asm, "", pattern> { 780 // TODO: Mark the instructions with the appropriate subtarget info. 781 let Inst{27-25} = 0b110; 782 let Inst{11-8} = 0b1010; 783} 784 785 786// Double precision, unary 787class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 788 string opc, string asm, list<dag> pattern> 789 : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> { 790 let Inst{27-20} = opcod1; 791 let Inst{19-16} = opcod2; 792 let Inst{11-8} = 0b1011; 793 let Inst{7-4} = opcod3; 794} 795 796// Double precision, binary 797class ADbI<bits<8> opcod, dag oops, dag iops, string opc, 798 string asm, list<dag> pattern> 799 : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> { 800 let Inst{27-20} = opcod; 801 let Inst{11-8} = 0b1011; 802} 803 804// Single precision, unary 805class ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 806 string opc, string asm, list<dag> pattern> 807 : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> { 808 // Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding. 809 let Inst{27-20} = opcod1; 810 let Inst{19-16} = opcod2; 811 let Inst{11-8} = 0b1010; 812 let Inst{7-4} = opcod3; 813} 814 815// Single precision, binary 816class ASbI<bits<8> opcod, dag oops, dag iops, string opc, 817 string asm, list<dag> pattern> 818 : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> { 819 // Bit 22 (D bit) can be changed during instruction encoding. 820 let Inst{27-20} = opcod; 821 let Inst{11-8} = 0b1010; 822} 823 824// VFP conversion instructions 825class AVConv1I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, 826 dag oops, dag iops, string opc, string asm, list<dag> pattern> 827 : AI<oops, iops, VFPConv1Frm, opc, asm, pattern> { 828 let Inst{27-20} = opcod1; 829 let Inst{19-16} = opcod2; 830 let Inst{11-8} = opcod3; 831 let Inst{6} = 1; 832} 833 834class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 835 string opc, string asm, list<dag> pattern> 836 : AI<oops, iops, f, opc, asm, pattern> { 837 let Inst{27-20} = opcod1; 838 let Inst{11-8} = opcod2; 839 let Inst{4} = 1; 840} 841 842class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc, 843 string asm, list<dag> pattern> 844 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, opc, asm, pattern>; 845 846class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc, 847 string asm, list<dag> pattern> 848 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, opc, asm, pattern>; 849 850class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc, 851 string asm, list<dag> pattern> 852 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, opc, asm, pattern>; 853 854class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc, 855 string asm, list<dag> pattern> 856 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, opc, asm, pattern>; 857 858//===----------------------------------------------------------------------===// 859 860 861// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode. 862class ThumbPat<dag pattern, dag result> : Pat<pattern, result> { 863 list<Predicate> Predicates = [IsThumb]; 864} 865 866class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> { 867 list<Predicate> Predicates = [IsThumb, HasV5T]; 868} 869