ARMInstrFormats.td revision 288943
1234353Sdim//===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===// 2206083Srdivacky// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7206083Srdivacky// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// 12193323Sed// ARM Instruction Format Definitions. 13193323Sed// 14193323Sed 15193323Sed// Format specifies the encoding used by the instruction. This is part of the 16193323Sed// ad-hoc solution used to emit machine instruction encodings by our machine 17193323Sed// code emitter. 18205407Srdivackyclass Format<bits<6> val> { 19205407Srdivacky bits<6> Value = val; 20193323Sed} 21193323Sed 22193323Seddef Pseudo : Format<0>; 23193323Seddef MulFrm : Format<1>; 24193323Seddef BrFrm : Format<2>; 25193323Seddef BrMiscFrm : Format<3>; 26193323Sed 27193323Seddef DPFrm : Format<4>; 28226633Sdimdef DPSoRegRegFrm : Format<5>; 29193323Sed 30193323Seddef LdFrm : Format<6>; 31193323Seddef StFrm : Format<7>; 32193323Seddef LdMiscFrm : Format<8>; 33193323Seddef StMiscFrm : Format<9>; 34193323Seddef LdStMulFrm : Format<10>; 35193323Sed 36205407Srdivackydef LdStExFrm : Format<11>; 37200581Srdivacky 38205407Srdivackydef ArithMiscFrm : Format<12>; 39212904Sdimdef SatFrm : Format<13>; 40212904Sdimdef ExtFrm : Format<14>; 41193323Sed 42212904Sdimdef VFPUnaryFrm : Format<15>; 43212904Sdimdef VFPBinaryFrm : Format<16>; 44212904Sdimdef VFPConv1Frm : Format<17>; 45212904Sdimdef VFPConv2Frm : Format<18>; 46212904Sdimdef VFPConv3Frm : Format<19>; 47212904Sdimdef VFPConv4Frm : Format<20>; 48212904Sdimdef VFPConv5Frm : Format<21>; 49212904Sdimdef VFPLdStFrm : Format<22>; 50212904Sdimdef VFPLdStMulFrm : Format<23>; 51212904Sdimdef VFPMiscFrm : Format<24>; 52193323Sed 53212904Sdimdef ThumbFrm : Format<25>; 54212904Sdimdef MiscFrm : Format<26>; 55193323Sed 56212904Sdimdef NGetLnFrm : Format<27>; 57212904Sdimdef NSetLnFrm : Format<28>; 58212904Sdimdef NDupFrm : Format<29>; 59212904Sdimdef NLdStFrm : Format<30>; 60212904Sdimdef N1RegModImmFrm: Format<31>; 61212904Sdimdef N2RegFrm : Format<32>; 62212904Sdimdef NVCVTFrm : Format<33>; 63212904Sdimdef NVDupLnFrm : Format<34>; 64212904Sdimdef N2RegVShLFrm : Format<35>; 65212904Sdimdef N2RegVShRFrm : Format<36>; 66212904Sdimdef N3RegFrm : Format<37>; 67212904Sdimdef N3RegVShFrm : Format<38>; 68212904Sdimdef NVExtFrm : Format<39>; 69212904Sdimdef NVMulSLFrm : Format<40>; 70212904Sdimdef NVTBLFrm : Format<41>; 71226633Sdimdef DPSoRegImmFrm : Format<42>; 72194710Sed 73198090Srdivacky// Misc flags. 74198090Srdivacky 75218893Sdim// The instruction has an Rn register operand. 76198090Srdivacky// UnaryDP - Indicates this is a unary data processing instruction, i.e. 77198090Srdivacky// it doesn't have a Rn operand. 78198090Srdivackyclass UnaryDP { bit isUnaryDataProc = 1; } 79193323Sed 80198090Srdivacky// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 81198090Srdivacky// a 16-bit Thumb instruction if certain conditions are met. 82198090Srdivackyclass Xform16Bit { bit canXformTo16Bit = 1; } 83198090Srdivacky 84193323Sed//===----------------------------------------------------------------------===// 85205407Srdivacky// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 86195340Sed// 87193323Sed 88218893Sdim// FIXME: Once the JIT is MC-ized, these can go away. 89195340Sed// Addressing mode. 90218893Sdimclass AddrMode<bits<5> val> { 91218893Sdim bits<5> Value = val; 92195340Sed} 93212904Sdimdef AddrModeNone : AddrMode<0>; 94212904Sdimdef AddrMode1 : AddrMode<1>; 95212904Sdimdef AddrMode2 : AddrMode<2>; 96212904Sdimdef AddrMode3 : AddrMode<3>; 97212904Sdimdef AddrMode4 : AddrMode<4>; 98212904Sdimdef AddrMode5 : AddrMode<5>; 99212904Sdimdef AddrMode6 : AddrMode<6>; 100212904Sdimdef AddrModeT1_1 : AddrMode<7>; 101212904Sdimdef AddrModeT1_2 : AddrMode<8>; 102212904Sdimdef AddrModeT1_4 : AddrMode<9>; 103212904Sdimdef AddrModeT1_s : AddrMode<10>; 104212904Sdimdef AddrModeT2_i12 : AddrMode<11>; 105212904Sdimdef AddrModeT2_i8 : AddrMode<12>; 106212904Sdimdef AddrModeT2_so : AddrMode<13>; 107212904Sdimdef AddrModeT2_pc : AddrMode<14>; 108195340Seddef AddrModeT2_i8s4 : AddrMode<15>; 109218893Sdimdef AddrMode_i12 : AddrMode<16>; 110195340Sed 111195340Sed// Load / store index mode. 112195340Sedclass IndexMode<bits<2> val> { 113195340Sed bits<2> Value = val; 114195340Sed} 115195340Seddef IndexModeNone : IndexMode<0>; 116195340Seddef IndexModePre : IndexMode<1>; 117195340Seddef IndexModePost : IndexMode<2>; 118205218Srdivackydef IndexModeUpd : IndexMode<3>; 119195340Sed 120198892Srdivacky// Instruction execution domain. 121219077Sdimclass Domain<bits<3> val> { 122219077Sdim bits<3> Value = val; 123198892Srdivacky} 124198892Srdivackydef GenericDomain : Domain<0>; 125198892Srdivackydef VFPDomain : Domain<1>; // Instructions in VFP domain only 126198892Srdivackydef NeonDomain : Domain<2>; // Instructions in Neon domain only 127198892Srdivackydef VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 128219077Sdimdef VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 129198892Srdivacky 130195340Sed//===----------------------------------------------------------------------===// 131198090Srdivacky// ARM special operands. 132198090Srdivacky// 133198090Srdivacky 134226633Sdim// ARM imod and iflag operands, used only by the CPS instruction. 135226633Sdimdef imod_op : Operand<i32> { 136226633Sdim let PrintMethod = "printCPSIMod"; 137212904Sdim} 138212904Sdim 139218893Sdimdef ProcIFlagsOperand : AsmOperandClass { 140218893Sdim let Name = "ProcIFlags"; 141226633Sdim let ParserMethod = "parseProcIFlagsOperand"; 142218893Sdim} 143218893Sdimdef iflags_op : Operand<i32> { 144218893Sdim let PrintMethod = "printCPSIFlag"; 145218893Sdim let ParserMatchClass = ProcIFlagsOperand; 146218893Sdim} 147218893Sdim 148198090Srdivacky// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 149198090Srdivacky// register whose default is 0 (no register). 150226633Sdimdef CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } 151226633Sdimdef pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), 152198090Srdivacky (ops (i32 14), (i32 zero_reg))> { 153198090Srdivacky let PrintMethod = "printPredicateOperand"; 154212904Sdim let ParserMatchClass = CondCodeOperand; 155226633Sdim let DecoderMethod = "DecodePredicateOperand"; 156198090Srdivacky} 157198090Srdivacky 158261991Sdim// Selectable predicate operand for CMOV instructions. We can't use a normal 159261991Sdim// predicate because the default values interfere with instruction selection. In 160261991Sdim// all other respects it is identical though: pseudo-instruction expansion 161261991Sdim// relies on the MachineOperands being compatible. 162261991Sdimdef cmovpred : Operand<i32>, PredicateOp, 163261991Sdim ComplexPattern<i32, 2, "SelectCMOVPred"> { 164261991Sdim let MIOperandInfo = (ops i32imm, i32imm); 165261991Sdim let PrintMethod = "printPredicateOperand"; 166261991Sdim} 167261991Sdim 168198090Srdivacky// Conditional code result for instructions whose 's' bit is set, e.g. subs. 169226633Sdimdef CCOutOperand : AsmOperandClass { let Name = "CCOut"; } 170198090Srdivackydef cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 171218893Sdim let EncoderMethod = "getCCOutOpValue"; 172198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 173218893Sdim let ParserMatchClass = CCOutOperand; 174226633Sdim let DecoderMethod = "DecodeCCOutOperand"; 175198090Srdivacky} 176198090Srdivacky 177198090Srdivacky// Same as cc_out except it defaults to setting CPSR. 178198090Srdivackydef s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 179218893Sdim let EncoderMethod = "getCCOutOpValue"; 180198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 181218893Sdim let ParserMatchClass = CCOutOperand; 182226633Sdim let DecoderMethod = "DecodeCCOutOperand"; 183198090Srdivacky} 184198090Srdivacky 185205218Srdivacky// ARM special operands for disassembly only. 186205218Srdivacky// 187234353Sdimdef SetEndAsmOperand : ImmAsmOperand { 188226633Sdim let Name = "SetEndImm"; 189226633Sdim let ParserMethod = "parseSetEndImm"; 190226633Sdim} 191218893Sdimdef setend_op : Operand<i32> { 192218893Sdim let PrintMethod = "printSetendOperand"; 193226633Sdim let ParserMatchClass = SetEndAsmOperand; 194218893Sdim} 195205218Srdivacky 196226633Sdimdef MSRMaskOperand : AsmOperandClass { 197226633Sdim let Name = "MSRMask"; 198226633Sdim let ParserMethod = "parseMSRMaskOperand"; 199226633Sdim} 200205218Srdivackydef msr_mask : Operand<i32> { 201205218Srdivacky let PrintMethod = "printMSRMaskOperand"; 202226633Sdim let DecoderMethod = "DecodeMSRMask"; 203218893Sdim let ParserMatchClass = MSRMaskOperand; 204205218Srdivacky} 205205218Srdivacky 206280031Sdimdef BankedRegOperand : AsmOperandClass { 207280031Sdim let Name = "BankedReg"; 208280031Sdim let ParserMethod = "parseBankedRegOperand"; 209280031Sdim} 210280031Sdimdef banked_reg : Operand<i32> { 211280031Sdim let PrintMethod = "printBankedRegOperand"; 212280031Sdim let DecoderMethod = "DecodeBankedReg"; 213280031Sdim let ParserMatchClass = BankedRegOperand; 214280031Sdim} 215280031Sdim 216221345Sdim// Shift Right Immediate - A shift right immediate is encoded differently from 217221345Sdim// other shift immediates. The imm6 field is encoded like so: 218221345Sdim// 219221345Sdim// Offset Encoding 220221345Sdim// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 221221345Sdim// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 222221345Sdim// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 223221345Sdim// 64 64 - <imm> is encoded in imm6<5:0> 224234353Sdimdef shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; } 225276479Sdimdef shr_imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 8; }]> { 226221345Sdim let EncoderMethod = "getShiftRight8Imm"; 227226633Sdim let DecoderMethod = "DecodeShiftRight8Imm"; 228234353Sdim let ParserMatchClass = shr_imm8_asm_operand; 229205218Srdivacky} 230234353Sdimdef shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; } 231276479Sdimdef shr_imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 16; }]> { 232221345Sdim let EncoderMethod = "getShiftRight16Imm"; 233226633Sdim let DecoderMethod = "DecodeShiftRight16Imm"; 234234353Sdim let ParserMatchClass = shr_imm16_asm_operand; 235221345Sdim} 236234353Sdimdef shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; } 237276479Sdimdef shr_imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]> { 238221345Sdim let EncoderMethod = "getShiftRight32Imm"; 239226633Sdim let DecoderMethod = "DecodeShiftRight32Imm"; 240234353Sdim let ParserMatchClass = shr_imm32_asm_operand; 241221345Sdim} 242234353Sdimdef shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; } 243276479Sdimdef shr_imm64 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 64; }]> { 244221345Sdim let EncoderMethod = "getShiftRight64Imm"; 245226633Sdim let DecoderMethod = "DecodeShiftRight64Imm"; 246234353Sdim let ParserMatchClass = shr_imm64_asm_operand; 247221345Sdim} 248205218Srdivacky 249198090Srdivacky//===----------------------------------------------------------------------===// 250226633Sdim// ARM Assembler alias templates. 251226633Sdim// 252226633Sdimclass ARMInstAlias<string Asm, dag Result, bit Emit = 0b1> 253226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>; 254226633Sdimclass tInstAlias<string Asm, dag Result, bit Emit = 0b1> 255226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>; 256226633Sdimclass t2InstAlias<string Asm, dag Result, bit Emit = 0b1> 257226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>; 258226633Sdimclass VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1> 259226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>; 260261991Sdimclass VFP2DPInstAlias<string Asm, dag Result, bit Emit = 0b1> 261261991Sdim : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2,HasDPVFP]>; 262226633Sdimclass VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1> 263226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>; 264234353Sdimclass NEONInstAlias<string Asm, dag Result, bit Emit = 0b1> 265234353Sdim : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>; 266226633Sdim 267234353Sdim 268234353Sdimclass VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, 269234353Sdim Requires<[HasVFP2]>; 270234353Sdimclass NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, 271234353Sdim Requires<[HasNEON]>; 272234353Sdim 273226633Sdim//===----------------------------------------------------------------------===// 274193323Sed// ARM Instruction templates. 275193323Sed// 276193323Sed 277226633Sdim 278224145Sdimclass InstTemplate<AddrMode am, int sz, IndexMode im, 279201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 280193323Sed : Instruction { 281193323Sed let Namespace = "ARM"; 282193323Sed 283193323Sed AddrMode AM = am; 284224145Sdim int Size = sz; 285193323Sed IndexMode IM = im; 286193323Sed bits<2> IndexModeBits = IM.Value; 287193323Sed Format F = f; 288205407Srdivacky bits<6> Form = F.Value; 289198892Srdivacky Domain D = d; 290193323Sed bit isUnaryDataProc = 0; 291198090Srdivacky bit canXformTo16Bit = 0; 292226633Sdim // The instruction is a 16-bit flag setting Thumb instruction. Used 293226633Sdim // by the parser to determine whether to require the 'S' suffix on the 294226633Sdim // mnemonic (when not in an IT block) or preclude it (when in an IT block). 295226633Sdim bit thumbArithFlagSetting = 0; 296206083Srdivacky 297218893Sdim // If this is a pseudo instruction, mark it isCodeGenOnly. 298218893Sdim let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 299218893Sdim 300226633Sdim // The layout of TSFlags should be kept in sync with ARMBaseInfo.h. 301218893Sdim let TSFlags{4-0} = AM.Value; 302224145Sdim let TSFlags{6-5} = IndexModeBits; 303224145Sdim let TSFlags{12-7} = Form; 304224145Sdim let TSFlags{13} = isUnaryDataProc; 305224145Sdim let TSFlags{14} = canXformTo16Bit; 306224145Sdim let TSFlags{17-15} = D.Value; 307226633Sdim let TSFlags{18} = thumbArithFlagSetting; 308206274Srdivacky 309193323Sed let Constraints = cstr; 310198090Srdivacky let Itinerary = itin; 311193323Sed} 312193323Sed 313201360Srdivackyclass Encoding { 314201360Srdivacky field bits<32> Inst; 315234353Sdim // Mask of bits that cause an encoding to be UNPREDICTABLE. 316234353Sdim // If a bit is set, then if the corresponding bit in the 317234353Sdim // target encoding differs from its value in the "Inst" field, 318234353Sdim // the instruction is UNPREDICTABLE (SoftFail in abstract parlance). 319234353Sdim field bits<32> Unpredictable = 0; 320234353Sdim // SoftFail is the generic name for this field, but we alias it so 321234353Sdim // as to make it more obvious what it means in ARM-land. 322234353Sdim field bits<32> SoftFail = Unpredictable; 323201360Srdivacky} 324201360Srdivacky 325224145Sdimclass InstARM<AddrMode am, int sz, IndexMode im, 326201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 327226633Sdim : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding { 328226633Sdim let DecoderNamespace = "ARM"; 329226633Sdim} 330201360Srdivacky 331201360Srdivacky// This Encoding-less class is used by Thumb1 to specify the encoding bits later 332201360Srdivacky// on by adding flavors to specific instructions. 333224145Sdimclass InstThumb<AddrMode am, int sz, IndexMode im, 334201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 335226633Sdim : InstTemplate<am, sz, im, f, d, cstr, itin> { 336226633Sdim let DecoderNamespace = "Thumb"; 337226633Sdim} 338201360Srdivacky 339234353Sdim// Pseudo-instructions for alternate assembly syntax (never used by codegen). 340234353Sdim// These are aliases that require C++ handling to convert to the target 341234353Sdim// instruction, while InstAliases can be handled directly by tblgen. 342276479Sdimclass AsmPseudoInst<string asm, dag iops, dag oops = (outs)> 343234353Sdim : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 344234353Sdim "", NoItinerary> { 345276479Sdim let OutOperandList = oops; 346234353Sdim let InOperandList = iops; 347234353Sdim let Pattern = []; 348234353Sdim let isCodeGenOnly = 0; // So we get asm matcher for it. 349234353Sdim let AsmString = asm; 350234353Sdim let isPseudo = 1; 351234353Sdim} 352234353Sdim 353276479Sdimclass ARMAsmPseudo<string asm, dag iops, dag oops = (outs)> 354276479Sdim : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>; 355276479Sdimclass tAsmPseudo<string asm, dag iops, dag oops = (outs)> 356276479Sdim : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>; 357276479Sdimclass t2AsmPseudo<string asm, dag iops, dag oops = (outs)> 358276479Sdim : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>; 359276479Sdimclass VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)> 360276479Sdim : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>; 361276479Sdimclass NEONAsmPseudo<string asm, dag iops, dag oops = (outs)> 362276479Sdim : AsmPseudoInst<asm, iops, oops>, Requires<[HasNEON]>; 363234353Sdim 364234353Sdim// Pseudo instructions for the code generator. 365218893Sdimclass PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 366224145Sdim : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, 367224145Sdim GenericDomain, "", itin> { 368193323Sed let OutOperandList = oops; 369193323Sed let InOperandList = iops; 370193323Sed let Pattern = pattern; 371221345Sdim let isCodeGenOnly = 1; 372224145Sdim let isPseudo = 1; 373193323Sed} 374193323Sed 375218893Sdim// PseudoInst that's ARM-mode only. 376224145Sdimclass ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 377218893Sdim list<dag> pattern> 378218893Sdim : PseudoInst<oops, iops, itin, pattern> { 379224145Sdim let Size = sz; 380218893Sdim list<Predicate> Predicates = [IsARM]; 381218893Sdim} 382218893Sdim 383218893Sdim// PseudoInst that's Thumb-mode only. 384224145Sdimclass tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 385218893Sdim list<dag> pattern> 386218893Sdim : PseudoInst<oops, iops, itin, pattern> { 387224145Sdim let Size = sz; 388218893Sdim list<Predicate> Predicates = [IsThumb]; 389218893Sdim} 390218893Sdim 391218893Sdim// PseudoInst that's Thumb2-mode only. 392224145Sdimclass t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 393218893Sdim list<dag> pattern> 394218893Sdim : PseudoInst<oops, iops, itin, pattern> { 395224145Sdim let Size = sz; 396218893Sdim list<Predicate> Predicates = [IsThumb2]; 397218893Sdim} 398224145Sdim 399224145Sdimclass ARMPseudoExpand<dag oops, dag iops, int sz, 400224145Sdim InstrItinClass itin, list<dag> pattern, 401224145Sdim dag Result> 402224145Sdim : ARMPseudoInst<oops, iops, sz, itin, pattern>, 403224145Sdim PseudoInstExpansion<Result>; 404224145Sdim 405224145Sdimclass tPseudoExpand<dag oops, dag iops, int sz, 406224145Sdim InstrItinClass itin, list<dag> pattern, 407224145Sdim dag Result> 408224145Sdim : tPseudoInst<oops, iops, sz, itin, pattern>, 409224145Sdim PseudoInstExpansion<Result>; 410224145Sdim 411224145Sdimclass t2PseudoExpand<dag oops, dag iops, int sz, 412224145Sdim InstrItinClass itin, list<dag> pattern, 413224145Sdim dag Result> 414224145Sdim : t2PseudoInst<oops, iops, sz, itin, pattern>, 415224145Sdim PseudoInstExpansion<Result>; 416224145Sdim 417193323Sed// Almost all ARM instructions are predicable. 418224145Sdimclass I<dag oops, dag iops, AddrMode am, int sz, 419206083Srdivacky IndexMode im, Format f, InstrItinClass itin, 420198090Srdivacky string opc, string asm, string cstr, 421193323Sed list<dag> pattern> 422198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 423218893Sdim bits<4> p; 424218893Sdim let Inst{31-28} = p; 425193323Sed let OutOperandList = oops; 426205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 427218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 428193323Sed let Pattern = pattern; 429193323Sed list<Predicate> Predicates = [IsARM]; 430193323Sed} 431212904Sdim 432200581Srdivacky// A few are not predicable 433224145Sdimclass InoP<dag oops, dag iops, AddrMode am, int sz, 434206083Srdivacky IndexMode im, Format f, InstrItinClass itin, 435206083Srdivacky string opc, string asm, string cstr, 436206083Srdivacky list<dag> pattern> 437200581Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 438200581Srdivacky let OutOperandList = oops; 439200581Srdivacky let InOperandList = iops; 440208599Srdivacky let AsmString = !strconcat(opc, asm); 441200581Srdivacky let Pattern = pattern; 442200581Srdivacky let isPredicable = 0; 443200581Srdivacky list<Predicate> Predicates = [IsARM]; 444200581Srdivacky} 445193323Sed 446212904Sdim// Same as I except it can optionally modify CPSR. Note it's modeled as an input 447212904Sdim// operand since by default it's a zero register. It will become an implicit def 448212904Sdim// once it's "flipped". 449224145Sdimclass sI<dag oops, dag iops, AddrMode am, int sz, 450198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 451198090Srdivacky string opc, string asm, string cstr, 452193323Sed list<dag> pattern> 453198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 454218893Sdim bits<4> p; // Predicate operand 455218893Sdim bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 456218893Sdim let Inst{31-28} = p; 457218893Sdim let Inst{20} = s; 458218893Sdim 459193323Sed let OutOperandList = oops; 460205407Srdivacky let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 461218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 462193323Sed let Pattern = pattern; 463193323Sed list<Predicate> Predicates = [IsARM]; 464193323Sed} 465193323Sed 466193323Sed// Special cases 467224145Sdimclass XI<dag oops, dag iops, AddrMode am, int sz, 468198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 469198090Srdivacky string asm, string cstr, list<dag> pattern> 470198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 471193323Sed let OutOperandList = oops; 472193323Sed let InOperandList = iops; 473208599Srdivacky let AsmString = asm; 474193323Sed let Pattern = pattern; 475193323Sed list<Predicate> Predicates = [IsARM]; 476193323Sed} 477193323Sed 478198090Srdivackyclass AI<dag oops, dag iops, Format f, InstrItinClass itin, 479198090Srdivacky string opc, string asm, list<dag> pattern> 480224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 481198090Srdivacky opc, asm, "", pattern>; 482198090Srdivackyclass AsI<dag oops, dag iops, Format f, InstrItinClass itin, 483198090Srdivacky string opc, string asm, list<dag> pattern> 484224145Sdim : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 485198090Srdivacky opc, asm, "", pattern>; 486198090Srdivackyclass AXI<dag oops, dag iops, Format f, InstrItinClass itin, 487193323Sed string asm, list<dag> pattern> 488224145Sdim : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 489193323Sed asm, "", pattern>; 490276479Sdimclass AXIM<dag oops, dag iops, AddrMode am, Format f, InstrItinClass itin, 491276479Sdim string asm, list<dag> pattern> 492276479Sdim : XI<oops, iops, am, 4, IndexModeNone, f, itin, 493276479Sdim asm, "", pattern>; 494200581Srdivackyclass AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 495206083Srdivacky string opc, string asm, list<dag> pattern> 496224145Sdim : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 497206083Srdivacky opc, asm, "", pattern>; 498193323Sed 499193323Sed// Ctrl flow instructions 500198090Srdivackyclass ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 501198090Srdivacky string opc, string asm, list<dag> pattern> 502224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 503198090Srdivacky opc, asm, "", pattern> { 504193323Sed let Inst{27-24} = opcod; 505193323Sed} 506198090Srdivackyclass ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 507198090Srdivacky string asm, list<dag> pattern> 508224145Sdim : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 509198090Srdivacky asm, "", pattern> { 510193323Sed let Inst{27-24} = opcod; 511193323Sed} 512193323Sed 513193323Sed// BR_JT instructions 514198090Srdivackyclass JTI<dag oops, dag iops, InstrItinClass itin, 515198090Srdivacky string asm, list<dag> pattern> 516224145Sdim : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin, 517193323Sed asm, "", pattern>; 518193323Sed 519261991Sdimclass AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, 520200581Srdivacky string opc, string asm, list<dag> pattern> 521224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 522200581Srdivacky opc, asm, "", pattern> { 523218893Sdim bits<4> Rt; 524226633Sdim bits<4> addr; 525200581Srdivacky let Inst{27-23} = 0b00011; 526200581Srdivacky let Inst{22-21} = opcod; 527212904Sdim let Inst{20} = 1; 528226633Sdim let Inst{19-16} = addr; 529218893Sdim let Inst{15-12} = Rt; 530261991Sdim let Inst{11-10} = 0b11; 531261991Sdim let Inst{9-8} = opcod2; 532261991Sdim let Inst{7-0} = 0b10011111; 533200581Srdivacky} 534261991Sdimclass AIstr_ex_or_rel<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, 535200581Srdivacky string opc, string asm, list<dag> pattern> 536224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 537200581Srdivacky opc, asm, "", pattern> { 538218893Sdim bits<4> Rt; 539221345Sdim bits<4> addr; 540200581Srdivacky let Inst{27-23} = 0b00011; 541200581Srdivacky let Inst{22-21} = opcod; 542212904Sdim let Inst{20} = 0; 543221345Sdim let Inst{19-16} = addr; 544261991Sdim let Inst{11-10} = 0b11; 545261991Sdim let Inst{9-8} = opcod2; 546261991Sdim let Inst{7-4} = 0b1001; 547218893Sdim let Inst{3-0} = Rt; 548200581Srdivacky} 549261991Sdim// Atomic load/store instructions 550261991Sdimclass AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 551261991Sdim string opc, string asm, list<dag> pattern> 552261991Sdim : AIldr_ex_or_acq<opcod, 0b11, oops, iops, itin, opc, asm, pattern>; 553261991Sdim 554261991Sdimclass AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 555261991Sdim string opc, string asm, list<dag> pattern> 556261991Sdim : AIstr_ex_or_rel<opcod, 0b11, oops, iops, itin, opc, asm, pattern> { 557261991Sdim bits<4> Rd; 558261991Sdim let Inst{15-12} = Rd; 559261991Sdim} 560261991Sdim 561261991Sdim// Exclusive load/store instructions 562261991Sdim 563261991Sdimclass AIldaex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 564261991Sdim string opc, string asm, list<dag> pattern> 565261991Sdim : AIldr_ex_or_acq<opcod, 0b10, oops, iops, itin, opc, asm, pattern>, 566261991Sdim Requires<[IsARM, HasV8]>; 567261991Sdim 568261991Sdimclass AIstlex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 569261991Sdim string opc, string asm, list<dag> pattern> 570261991Sdim : AIstr_ex_or_rel<opcod, 0b10, oops, iops, itin, opc, asm, pattern>, 571261991Sdim Requires<[IsARM, HasV8]> { 572261991Sdim bits<4> Rd; 573261991Sdim let Inst{15-12} = Rd; 574261991Sdim} 575261991Sdim 576218893Sdimclass AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 577226633Sdim : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> { 578218893Sdim bits<4> Rt; 579218893Sdim bits<4> Rt2; 580226633Sdim bits<4> addr; 581218893Sdim let Inst{27-23} = 0b00010; 582218893Sdim let Inst{22} = b; 583218893Sdim let Inst{21-20} = 0b00; 584226633Sdim let Inst{19-16} = addr; 585218893Sdim let Inst{15-12} = Rt; 586218893Sdim let Inst{11-4} = 0b00001001; 587218893Sdim let Inst{3-0} = Rt2; 588234353Sdim 589234982Sdim let Unpredictable{11-8} = 0b1111; 590234353Sdim let DecoderMethod = "DecodeSwap"; 591218893Sdim} 592261991Sdim// Acquire/Release load/store instructions 593261991Sdimclass AIldracq<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 594261991Sdim string opc, string asm, list<dag> pattern> 595261991Sdim : AIldr_ex_or_acq<opcod, 0b00, oops, iops, itin, opc, asm, pattern>, 596261991Sdim Requires<[IsARM, HasV8]>; 597200581Srdivacky 598261991Sdimclass AIstrrel<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 599261991Sdim string opc, string asm, list<dag> pattern> 600261991Sdim : AIstr_ex_or_rel<opcod, 0b00, oops, iops, itin, opc, asm, pattern>, 601261991Sdim Requires<[IsARM, HasV8]> { 602261991Sdim let Inst{15-12} = 0b1111; 603261991Sdim} 604261991Sdim 605193323Sed// addrmode1 instructions 606198090Srdivackyclass AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 607198090Srdivacky string opc, string asm, list<dag> pattern> 608224145Sdim : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 609198090Srdivacky opc, asm, "", pattern> { 610193323Sed let Inst{24-21} = opcod; 611212904Sdim let Inst{27-26} = 0b00; 612193323Sed} 613198090Srdivackyclass AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 614198090Srdivacky string opc, string asm, list<dag> pattern> 615224145Sdim : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 616198090Srdivacky opc, asm, "", pattern> { 617193323Sed let Inst{24-21} = opcod; 618212904Sdim let Inst{27-26} = 0b00; 619193323Sed} 620198090Srdivackyclass AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 621198090Srdivacky string asm, list<dag> pattern> 622224145Sdim : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 623198090Srdivacky asm, "", pattern> { 624193323Sed let Inst{24-21} = opcod; 625212904Sdim let Inst{27-26} = 0b00; 626193323Sed} 627193323Sed 628193323Sed// loads 629193323Sed 630218893Sdim// LDR/LDRB/STR/STRB/... 631218893Sdimclass AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 632218893Sdim Format f, InstrItinClass itin, string opc, string asm, 633218893Sdim list<dag> pattern> 634224145Sdim : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm, 635218893Sdim "", pattern> { 636218893Sdim let Inst{27-25} = op; 637218893Sdim let Inst{24} = 1; // 24 == P 638218893Sdim // 23 == U 639218893Sdim let Inst{22} = isByte; 640218893Sdim let Inst{21} = 0; // 21 == W 641218893Sdim let Inst{20} = isLd; 642193323Sed} 643218893Sdim// Indexed load/stores 644218893Sdimclass AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 645218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 646218893Sdim string asm, string cstr, list<dag> pattern> 647224145Sdim : I<oops, iops, AddrMode2, 4, im, f, itin, 648198090Srdivacky opc, asm, cstr, pattern> { 649218893Sdim bits<4> Rt; 650212904Sdim let Inst{27-26} = 0b01; 651218893Sdim let Inst{24} = isPre; // P bit 652218893Sdim let Inst{22} = isByte; // B bit 653218893Sdim let Inst{21} = isPre; // W bit 654218893Sdim let Inst{20} = isLd; // L bit 655218893Sdim let Inst{15-12} = Rt; 656193323Sed} 657226633Sdimclass AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops, 658218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 659218893Sdim string asm, string cstr, list<dag> pattern> 660218893Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 661218893Sdim pattern> { 662218893Sdim // AM2 store w/ two operands: (GPR, am2offset) 663218893Sdim // {12} isAdd 664218893Sdim // {11-0} imm12/Rm 665218893Sdim bits<14> offset; 666218893Sdim bits<4> Rn; 667226633Sdim let Inst{25} = 1; 668218893Sdim let Inst{23} = offset{12}; 669218893Sdim let Inst{19-16} = Rn; 670226633Sdim let Inst{11-5} = offset{11-5}; 671226633Sdim let Inst{4} = 0; 672226633Sdim let Inst{3-0} = offset{3-0}; 673226633Sdim} 674226633Sdim 675226633Sdimclass AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops, 676226633Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 677226633Sdim string asm, string cstr, list<dag> pattern> 678226633Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 679226633Sdim pattern> { 680226633Sdim // AM2 store w/ two operands: (GPR, am2offset) 681226633Sdim // {12} isAdd 682226633Sdim // {11-0} imm12/Rm 683226633Sdim bits<14> offset; 684226633Sdim bits<4> Rn; 685226633Sdim let Inst{25} = 0; 686226633Sdim let Inst{23} = offset{12}; 687226633Sdim let Inst{19-16} = Rn; 688218893Sdim let Inst{11-0} = offset{11-0}; 689193323Sed} 690226633Sdim 691226633Sdim 692221345Sdim// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB 693221345Sdim// but for now use this class for STRT and STRBT. 694221345Sdimclass AI2stridxT<bit isByte, bit isPre, dag oops, dag iops, 695221345Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 696221345Sdim string asm, string cstr, list<dag> pattern> 697221345Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 698221345Sdim pattern> { 699221345Sdim // AM2 store w/ two operands: (GPR, am2offset) 700221345Sdim // {17-14} Rn 701221345Sdim // {13} 1 == Rm, 0 == imm12 702221345Sdim // {12} isAdd 703221345Sdim // {11-0} imm12/Rm 704221345Sdim bits<18> addr; 705221345Sdim let Inst{25} = addr{13}; 706221345Sdim let Inst{23} = addr{12}; 707221345Sdim let Inst{19-16} = addr{17-14}; 708221345Sdim let Inst{11-0} = addr{11-0}; 709221345Sdim} 710193323Sed 711193323Sed// addrmode3 instructions 712218893Sdimclass AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 713218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 714224145Sdim : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 715198090Srdivacky opc, asm, "", pattern> { 716218893Sdim bits<14> addr; 717218893Sdim bits<4> Rt; 718198090Srdivacky let Inst{27-25} = 0b000; 719218893Sdim let Inst{24} = 1; // P bit 720218893Sdim let Inst{23} = addr{8}; // U bit 721218893Sdim let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 722218893Sdim let Inst{21} = 0; // W bit 723218893Sdim let Inst{20} = op20; // L bit 724218893Sdim let Inst{19-16} = addr{12-9}; // Rn 725218893Sdim let Inst{15-12} = Rt; // Rt 726218893Sdim let Inst{11-8} = addr{7-4}; // imm7_4/zero 727218893Sdim let Inst{7-4} = op; 728218893Sdim let Inst{3-0} = addr{3-0}; // imm3_0/Rm 729226633Sdim 730226633Sdim let DecoderMethod = "DecodeAddrMode3Instruction"; 731193323Sed} 732218893Sdim 733226633Sdimclass AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops, 734218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 735218893Sdim string asm, string cstr, list<dag> pattern> 736224145Sdim : I<oops, iops, AddrMode3, 4, im, f, itin, 737218893Sdim opc, asm, cstr, pattern> { 738218893Sdim bits<4> Rt; 739198090Srdivacky let Inst{27-25} = 0b000; 740218893Sdim let Inst{24} = isPre; // P bit 741218893Sdim let Inst{21} = isPre; // W bit 742218893Sdim let Inst{20} = op20; // L bit 743218893Sdim let Inst{15-12} = Rt; // Rt 744218893Sdim let Inst{7-4} = op; 745193323Sed} 746221345Sdim 747221345Sdim// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB 748221345Sdim// but for now use this class for LDRSBT, LDRHT, LDSHT. 749226633Sdimclass AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops, 750221345Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 751221345Sdim string asm, string cstr, list<dag> pattern> 752226633Sdim : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> { 753221345Sdim // {13} 1 == imm8, 0 == Rm 754221345Sdim // {12-9} Rn 755221345Sdim // {8} isAdd 756221345Sdim // {7-4} imm7_4/zero 757221345Sdim // {3-0} imm3_0/Rm 758226633Sdim bits<4> addr; 759221345Sdim bits<4> Rt; 760221345Sdim let Inst{27-25} = 0b000; 761226633Sdim let Inst{24} = 0; // P bit 762226633Sdim let Inst{21} = 1; 763226633Sdim let Inst{20} = isLoad; // L bit 764226633Sdim let Inst{19-16} = addr; // Rn 765221345Sdim let Inst{15-12} = Rt; // Rt 766221345Sdim let Inst{7-4} = op; 767221345Sdim} 768221345Sdim 769193323Sed// stores 770218893Sdimclass AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 771198090Srdivacky string opc, string asm, list<dag> pattern> 772224145Sdim : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 773198090Srdivacky opc, asm, "", pattern> { 774218893Sdim bits<14> addr; 775218893Sdim bits<4> Rt; 776198090Srdivacky let Inst{27-25} = 0b000; 777218893Sdim let Inst{24} = 1; // P bit 778218893Sdim let Inst{23} = addr{8}; // U bit 779218893Sdim let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 780218893Sdim let Inst{21} = 0; // W bit 781218893Sdim let Inst{20} = 0; // L bit 782218893Sdim let Inst{19-16} = addr{12-9}; // Rn 783218893Sdim let Inst{15-12} = Rt; // Rt 784218893Sdim let Inst{11-8} = addr{7-4}; // imm7_4/zero 785218893Sdim let Inst{7-4} = op; 786218893Sdim let Inst{3-0} = addr{3-0}; // imm3_0/Rm 787226633Sdim let DecoderMethod = "DecodeAddrMode3Instruction"; 788193323Sed} 789193323Sed 790193323Sed// addrmode4 instructions 791218893Sdimclass AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 792218893Sdim string asm, string cstr, list<dag> pattern> 793224145Sdim : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> { 794218893Sdim bits<4> p; 795218893Sdim bits<16> regs; 796218893Sdim bits<4> Rn; 797218893Sdim let Inst{31-28} = p; 798193323Sed let Inst{27-25} = 0b100; 799193323Sed let Inst{22} = 0; // S bit 800218893Sdim let Inst{19-16} = Rn; 801218893Sdim let Inst{15-0} = regs; 802193323Sed} 803193323Sed 804193323Sed// Unsigned multiply, multiply-accumulate instructions. 805198090Srdivackyclass AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 806198090Srdivacky string opc, string asm, list<dag> pattern> 807224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 808198090Srdivacky opc, asm, "", pattern> { 809193323Sed let Inst{7-4} = 0b1001; 810193323Sed let Inst{20} = 0; // S bit 811193323Sed let Inst{27-21} = opcod; 812193323Sed} 813198090Srdivackyclass AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 814198090Srdivacky string opc, string asm, list<dag> pattern> 815224145Sdim : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 816198090Srdivacky opc, asm, "", pattern> { 817193323Sed let Inst{7-4} = 0b1001; 818193323Sed let Inst{27-21} = opcod; 819193323Sed} 820193323Sed 821193323Sed// Most significant word multiply 822218893Sdimclass AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 823218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 824224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 825198090Srdivacky opc, asm, "", pattern> { 826218893Sdim bits<4> Rd; 827218893Sdim bits<4> Rn; 828218893Sdim bits<4> Rm; 829218893Sdim let Inst{7-4} = opc7_4; 830193323Sed let Inst{20} = 1; 831193323Sed let Inst{27-21} = opcod; 832218893Sdim let Inst{19-16} = Rd; 833218893Sdim let Inst{11-8} = Rm; 834218893Sdim let Inst{3-0} = Rn; 835193323Sed} 836218893Sdim// MSW multiple w/ Ra operand 837218893Sdimclass AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 838218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 839218893Sdim : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 840218893Sdim bits<4> Ra; 841218893Sdim let Inst{15-12} = Ra; 842218893Sdim} 843193323Sed 844193323Sed// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 845218893Sdimclass AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 846218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 847224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 848198090Srdivacky opc, asm, "", pattern> { 849218893Sdim bits<4> Rn; 850218893Sdim bits<4> Rm; 851193323Sed let Inst{4} = 0; 852193323Sed let Inst{7} = 1; 853193323Sed let Inst{20} = 0; 854193323Sed let Inst{27-21} = opcod; 855218893Sdim let Inst{6-5} = bit6_5; 856218893Sdim let Inst{11-8} = Rm; 857218893Sdim let Inst{3-0} = Rn; 858193323Sed} 859218893Sdimclass AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 860218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 861218893Sdim : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 862218893Sdim bits<4> Rd; 863218893Sdim let Inst{19-16} = Rd; 864218893Sdim} 865193323Sed 866218893Sdim// AMulxyI with Ra operand 867218893Sdimclass AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 868218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 869218893Sdim : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 870218893Sdim bits<4> Ra; 871218893Sdim let Inst{15-12} = Ra; 872218893Sdim} 873218893Sdim// SMLAL* 874218893Sdimclass AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 875218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 876218893Sdim : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 877218893Sdim bits<4> RdLo; 878218893Sdim bits<4> RdHi; 879218893Sdim let Inst{19-16} = RdHi; 880218893Sdim let Inst{15-12} = RdLo; 881218893Sdim} 882218893Sdim 883193323Sed// Extend instructions. 884198090Srdivackyclass AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 885198090Srdivacky string opc, string asm, list<dag> pattern> 886224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin, 887198090Srdivacky opc, asm, "", pattern> { 888218893Sdim // All AExtI instructions have Rd and Rm register operands. 889218893Sdim bits<4> Rd; 890218893Sdim bits<4> Rm; 891218893Sdim let Inst{15-12} = Rd; 892218893Sdim let Inst{3-0} = Rm; 893193323Sed let Inst{7-4} = 0b0111; 894218893Sdim let Inst{9-8} = 0b00; 895193323Sed let Inst{27-20} = opcod; 896239462Sdim 897239462Sdim let Unpredictable{9-8} = 0b11; 898193323Sed} 899193323Sed 900193323Sed// Misc Arithmetic instructions. 901218893Sdimclass AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 902218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 903224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 904198090Srdivacky opc, asm, "", pattern> { 905218893Sdim bits<4> Rd; 906218893Sdim bits<4> Rm; 907193323Sed let Inst{27-20} = opcod; 908218893Sdim let Inst{19-16} = 0b1111; 909218893Sdim let Inst{15-12} = Rd; 910218893Sdim let Inst{11-8} = 0b1111; 911218893Sdim let Inst{7-4} = opc7_4; 912218893Sdim let Inst{3-0} = Rm; 913193323Sed} 914193323Sed 915243830Sdim// Division instructions. 916243830Sdimclass ADivA1I<bits<3> opcod, dag oops, dag iops, 917243830Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 918243830Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 919243830Sdim opc, asm, "", pattern> { 920243830Sdim bits<4> Rd; 921243830Sdim bits<4> Rn; 922243830Sdim bits<4> Rm; 923243830Sdim let Inst{27-23} = 0b01110; 924243830Sdim let Inst{22-20} = opcod; 925243830Sdim let Inst{19-16} = Rd; 926243830Sdim let Inst{15-12} = 0b1111; 927243830Sdim let Inst{11-8} = Rm; 928243830Sdim let Inst{7-4} = 0b0001; 929243830Sdim let Inst{3-0} = Rn; 930243830Sdim} 931243830Sdim 932218893Sdim// PKH instructions 933234353Sdimdef PKHLSLAsmOperand : ImmAsmOperand { 934226633Sdim let Name = "PKHLSLImm"; 935226633Sdim let ParserMethod = "parsePKHLSLImm"; 936226633Sdim} 937226633Sdimdef pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{ 938226633Sdim let PrintMethod = "printPKHLSLShiftImm"; 939226633Sdim let ParserMatchClass = PKHLSLAsmOperand; 940226633Sdim} 941226633Sdimdef PKHASRAsmOperand : AsmOperandClass { 942226633Sdim let Name = "PKHASRImm"; 943226633Sdim let ParserMethod = "parsePKHASRImm"; 944226633Sdim} 945226633Sdimdef pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{ 946226633Sdim let PrintMethod = "printPKHASRShiftImm"; 947226633Sdim let ParserMatchClass = PKHASRAsmOperand; 948226633Sdim} 949226633Sdim 950218893Sdimclass APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 951218893Sdim string opc, string asm, list<dag> pattern> 952224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 953218893Sdim opc, asm, "", pattern> { 954218893Sdim bits<4> Rd; 955218893Sdim bits<4> Rn; 956218893Sdim bits<4> Rm; 957226633Sdim bits<5> sh; 958218893Sdim let Inst{27-20} = opcod; 959218893Sdim let Inst{19-16} = Rn; 960218893Sdim let Inst{15-12} = Rd; 961226633Sdim let Inst{11-7} = sh; 962218893Sdim let Inst{6} = tb; 963218893Sdim let Inst{5-4} = 0b01; 964218893Sdim let Inst{3-0} = Rm; 965218893Sdim} 966218893Sdim 967193323Sed//===----------------------------------------------------------------------===// 968193323Sed 969193323Sed// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 970193323Sedclass ARMPat<dag pattern, dag result> : Pat<pattern, result> { 971193323Sed list<Predicate> Predicates = [IsARM]; 972193323Sed} 973223017Sdimclass ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> { 974223017Sdim list<Predicate> Predicates = [IsARM, HasV5T]; 975223017Sdim} 976193323Sedclass ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 977193323Sed list<Predicate> Predicates = [IsARM, HasV5TE]; 978193323Sed} 979243830Sdim// ARMV5MOPat - Same as ARMV5TEPat with UseMulOps. 980243830Sdimclass ARMV5MOPat<dag pattern, dag result> : Pat<pattern, result> { 981243830Sdim list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps]; 982243830Sdim} 983193323Sedclass ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 984193323Sed list<Predicate> Predicates = [IsARM, HasV6]; 985193323Sed} 986288943Sdimclass VFPPat<dag pattern, dag result> : Pat<pattern, result> { 987288943Sdim list<Predicate> Predicates = [HasVFP2]; 988288943Sdim} 989288943Sdimclass VFPNoNEONPat<dag pattern, dag result> : Pat<pattern, result> { 990288943Sdim list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP]; 991288943Sdim} 992193323Sed//===----------------------------------------------------------------------===// 993193323Sed// Thumb Instruction Format Definitions. 994193323Sed// 995193323Sed 996224145Sdimclass ThumbI<dag oops, dag iops, AddrMode am, int sz, 997198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 998201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 999198090Srdivacky let OutOperandList = oops; 1000198090Srdivacky let InOperandList = iops; 1001208599Srdivacky let AsmString = asm; 1002193323Sed let Pattern = pattern; 1003193323Sed list<Predicate> Predicates = [IsThumb]; 1004193323Sed} 1005193323Sed 1006218893Sdim// TI - Thumb instruction. 1007198090Srdivackyclass TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 1008224145Sdim : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 1009193323Sed 1010198090Srdivacky// Two-address instructions 1011206083Srdivackyclass TIt<dag oops, dag iops, InstrItinClass itin, string asm, 1012206083Srdivacky list<dag> pattern> 1013224145Sdim : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst", 1014206083Srdivacky pattern>; 1015193323Sed 1016201360Srdivacky// tBL, tBX 32-bit instructions 1017201360Srdivackyclass TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 1018206083Srdivacky dag oops, dag iops, InstrItinClass itin, string asm, 1019206083Srdivacky list<dag> pattern> 1020224145Sdim : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>, 1021206083Srdivacky Encoding { 1022201360Srdivacky let Inst{31-27} = opcod1; 1023201360Srdivacky let Inst{15-14} = opcod2; 1024212904Sdim let Inst{12} = opcod3; 1025201360Srdivacky} 1026198090Srdivacky 1027193323Sed// BR_JT instructions 1028206083Srdivackyclass TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 1029206083Srdivacky list<dag> pattern> 1030224145Sdim : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 1031193323Sed 1032198090Srdivacky// Thumb1 only 1033224145Sdimclass Thumb1I<dag oops, dag iops, AddrMode am, int sz, 1034198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 1035201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1036198090Srdivacky let OutOperandList = oops; 1037198090Srdivacky let InOperandList = iops; 1038208599Srdivacky let AsmString = asm; 1039198090Srdivacky let Pattern = pattern; 1040218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1041194710Sed} 1042193323Sed 1043198090Srdivackyclass T1I<dag oops, dag iops, InstrItinClass itin, 1044198090Srdivacky string asm, list<dag> pattern> 1045224145Sdim : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 1046198090Srdivackyclass T1Ix2<dag oops, dag iops, InstrItinClass itin, 1047198090Srdivacky string asm, list<dag> pattern> 1048224145Sdim : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 1049194710Sed 1050198090Srdivacky// Two-address instructions 1051198090Srdivackyclass T1It<dag oops, dag iops, InstrItinClass itin, 1052205218Srdivacky string asm, string cstr, list<dag> pattern> 1053224145Sdim : Thumb1I<oops, iops, AddrModeNone, 2, itin, 1054205218Srdivacky asm, cstr, pattern>; 1055198090Srdivacky 1056198090Srdivacky// Thumb1 instruction that can either be predicated or set CPSR. 1057224145Sdimclass Thumb1sI<dag oops, dag iops, AddrMode am, int sz, 1058198090Srdivacky InstrItinClass itin, 1059198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1060201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1061205407Srdivacky let OutOperandList = !con(oops, (outs s_cc_out:$s)); 1062205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1063218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 1064194754Sed let Pattern = pattern; 1065226633Sdim let thumbArithFlagSetting = 1; 1066218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1067226633Sdim let DecoderNamespace = "ThumbSBit"; 1068195098Sed} 1069195098Sed 1070198090Srdivackyclass T1sI<dag oops, dag iops, InstrItinClass itin, 1071198090Srdivacky string opc, string asm, list<dag> pattern> 1072224145Sdim : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 1073195098Sed 1074195098Sed// Two-address instructions 1075198090Srdivackyclass T1sIt<dag oops, dag iops, InstrItinClass itin, 1076198090Srdivacky string opc, string asm, list<dag> pattern> 1077224145Sdim : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, 1078218893Sdim "$Rn = $Rdn", pattern>; 1079195098Sed 1080198090Srdivacky// Thumb1 instruction that can be predicated. 1081224145Sdimclass Thumb1pI<dag oops, dag iops, AddrMode am, int sz, 1082198090Srdivacky InstrItinClass itin, 1083198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1084201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1085198090Srdivacky let OutOperandList = oops; 1086205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1087218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1088198090Srdivacky let Pattern = pattern; 1089218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1090195098Sed} 1091195098Sed 1092198090Srdivackyclass T1pI<dag oops, dag iops, InstrItinClass itin, 1093198090Srdivacky string opc, string asm, list<dag> pattern> 1094224145Sdim : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 1095198090Srdivacky 1096198090Srdivacky// Two-address instructions 1097198090Srdivackyclass T1pIt<dag oops, dag iops, InstrItinClass itin, 1098198090Srdivacky string opc, string asm, list<dag> pattern> 1099224145Sdim : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, 1100218893Sdim "$Rn = $Rdn", pattern>; 1101198090Srdivacky 1102206083Srdivackyclass T1pIs<dag oops, dag iops, 1103198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1104224145Sdim : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>; 1105198090Srdivacky 1106201360Srdivackyclass Encoding16 : Encoding { 1107201360Srdivacky let Inst{31-16} = 0x0000; 1108201360Srdivacky} 1109201360Srdivacky 1110201360Srdivacky// A6.2 16-bit Thumb instruction encoding 1111201360Srdivackyclass T1Encoding<bits<6> opcode> : Encoding16 { 1112201360Srdivacky let Inst{15-10} = opcode; 1113201360Srdivacky} 1114201360Srdivacky 1115201360Srdivacky// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1116201360Srdivackyclass T1General<bits<5> opcode> : Encoding16 { 1117201360Srdivacky let Inst{15-14} = 0b00; 1118201360Srdivacky let Inst{13-9} = opcode; 1119201360Srdivacky} 1120201360Srdivacky 1121201360Srdivacky// A6.2.2 Data-processing encoding. 1122201360Srdivackyclass T1DataProcessing<bits<4> opcode> : Encoding16 { 1123201360Srdivacky let Inst{15-10} = 0b010000; 1124201360Srdivacky let Inst{9-6} = opcode; 1125201360Srdivacky} 1126201360Srdivacky 1127201360Srdivacky// A6.2.3 Special data instructions and branch and exchange encoding. 1128201360Srdivackyclass T1Special<bits<4> opcode> : Encoding16 { 1129201360Srdivacky let Inst{15-10} = 0b010001; 1130218893Sdim let Inst{9-6} = opcode; 1131201360Srdivacky} 1132201360Srdivacky 1133201360Srdivacky// A6.2.4 Load/store single data item encoding. 1134201360Srdivackyclass T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1135201360Srdivacky let Inst{15-12} = opA; 1136212904Sdim let Inst{11-9} = opB; 1137201360Srdivacky} 1138212904Sdimclass T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1139201360Srdivacky 1140223017Sdimclass T1BranchCond<bits<4> opcode> : Encoding16 { 1141223017Sdim let Inst{15-12} = opcode; 1142223017Sdim} 1143223017Sdim 1144218893Sdim// Helper classes to encode Thumb1 loads and stores. For immediates, the 1145218893Sdim// following bits are used for "opA" (see A6.2.4): 1146218893Sdim// 1147218893Sdim// 0b0110 => Immediate, 4 bytes 1148218893Sdim// 0b1000 => Immediate, 2 bytes 1149218893Sdim// 0b0111 => Immediate, 1 byte 1150218893Sdimclass T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 1151218893Sdim InstrItinClass itin, string opc, string asm, 1152218893Sdim list<dag> pattern> 1153224145Sdim : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1154218893Sdim T1LoadStore<0b0101, opcode> { 1155218893Sdim bits<3> Rt; 1156218893Sdim bits<8> addr; 1157218893Sdim let Inst{8-6} = addr{5-3}; // Rm 1158218893Sdim let Inst{5-3} = addr{2-0}; // Rn 1159218893Sdim let Inst{2-0} = Rt; 1160218893Sdim} 1161218893Sdimclass T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 1162218893Sdim InstrItinClass itin, string opc, string asm, 1163218893Sdim list<dag> pattern> 1164224145Sdim : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1165218893Sdim T1LoadStore<opA, {opB,?,?}> { 1166218893Sdim bits<3> Rt; 1167218893Sdim bits<8> addr; 1168218893Sdim let Inst{10-6} = addr{7-3}; // imm5 1169218893Sdim let Inst{5-3} = addr{2-0}; // Rn 1170218893Sdim let Inst{2-0} = Rt; 1171218893Sdim} 1172218893Sdim 1173201360Srdivacky// A6.2.5 Miscellaneous 16-bit instructions encoding. 1174201360Srdivackyclass T1Misc<bits<7> opcode> : Encoding16 { 1175201360Srdivacky let Inst{15-12} = 0b1011; 1176201360Srdivacky let Inst{11-5} = opcode; 1177201360Srdivacky} 1178201360Srdivacky 1179195098Sed// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1180224145Sdimclass Thumb2I<dag oops, dag iops, AddrMode am, int sz, 1181198090Srdivacky InstrItinClass itin, 1182195098Sed string opc, string asm, string cstr, list<dag> pattern> 1183198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1184195098Sed let OutOperandList = oops; 1185205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1186218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1187195098Sed let Pattern = pattern; 1188195340Sed list<Predicate> Predicates = [IsThumb2]; 1189226633Sdim let DecoderNamespace = "Thumb2"; 1190194754Sed} 1191194754Sed 1192212904Sdim// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 1193212904Sdim// input operand since by default it's a zero register. It will become an 1194212904Sdim// implicit def once it's "flipped". 1195218893Sdim// 1196195098Sed// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1197195098Sed// more consistent. 1198224145Sdimclass Thumb2sI<dag oops, dag iops, AddrMode am, int sz, 1199198090Srdivacky InstrItinClass itin, 1200195098Sed string opc, string asm, string cstr, list<dag> pattern> 1201198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1202218893Sdim bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 1203218893Sdim let Inst{20} = s; 1204218893Sdim 1205195098Sed let OutOperandList = oops; 1206205407Srdivacky let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1207218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 1208195098Sed let Pattern = pattern; 1209195340Sed list<Predicate> Predicates = [IsThumb2]; 1210226633Sdim let DecoderNamespace = "Thumb2"; 1211195098Sed} 1212194754Sed 1213195098Sed// Special cases 1214224145Sdimclass Thumb2XI<dag oops, dag iops, AddrMode am, int sz, 1215198090Srdivacky InstrItinClass itin, 1216195098Sed string asm, string cstr, list<dag> pattern> 1217198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1218195098Sed let OutOperandList = oops; 1219195098Sed let InOperandList = iops; 1220208599Srdivacky let AsmString = asm; 1221195098Sed let Pattern = pattern; 1222195340Sed list<Predicate> Predicates = [IsThumb2]; 1223226633Sdim let DecoderNamespace = "Thumb2"; 1224194754Sed} 1225194754Sed 1226224145Sdimclass ThumbXI<dag oops, dag iops, AddrMode am, int sz, 1227206083Srdivacky InstrItinClass itin, 1228206083Srdivacky string asm, string cstr, list<dag> pattern> 1229200581Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1230200581Srdivacky let OutOperandList = oops; 1231200581Srdivacky let InOperandList = iops; 1232208599Srdivacky let AsmString = asm; 1233200581Srdivacky let Pattern = pattern; 1234218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1235226633Sdim let DecoderNamespace = "Thumb"; 1236200581Srdivacky} 1237200581Srdivacky 1238198090Srdivackyclass T2I<dag oops, dag iops, InstrItinClass itin, 1239198090Srdivacky string opc, string asm, list<dag> pattern> 1240224145Sdim : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1241198090Srdivackyclass T2Ii12<dag oops, dag iops, InstrItinClass itin, 1242198090Srdivacky string opc, string asm, list<dag> pattern> 1243224145Sdim : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>; 1244198090Srdivackyclass T2Ii8<dag oops, dag iops, InstrItinClass itin, 1245198090Srdivacky string opc, string asm, list<dag> pattern> 1246224145Sdim : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>; 1247198090Srdivackyclass T2Iso<dag oops, dag iops, InstrItinClass itin, 1248198090Srdivacky string opc, string asm, list<dag> pattern> 1249224145Sdim : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>; 1250198090Srdivackyclass T2Ipc<dag oops, dag iops, InstrItinClass itin, 1251198090Srdivacky string opc, string asm, list<dag> pattern> 1252224145Sdim : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>; 1253218893Sdimclass T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, 1254226633Sdim string opc, string asm, string cstr, list<dag> pattern> 1255226633Sdim : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, 1256201360Srdivacky pattern> { 1257218893Sdim bits<4> Rt; 1258218893Sdim bits<4> Rt2; 1259218893Sdim bits<13> addr; 1260218893Sdim let Inst{31-25} = 0b1110100; 1261212904Sdim let Inst{24} = P; 1262218893Sdim let Inst{23} = addr{8}; 1263212904Sdim let Inst{22} = 1; 1264212904Sdim let Inst{21} = W; 1265218893Sdim let Inst{20} = isLoad; 1266218893Sdim let Inst{19-16} = addr{12-9}; 1267218893Sdim let Inst{15-12} = Rt{3-0}; 1268218893Sdim let Inst{11-8} = Rt2{3-0}; 1269218893Sdim let Inst{7-0} = addr{7-0}; 1270201360Srdivacky} 1271226633Sdimclass T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops, 1272226633Sdim InstrItinClass itin, string opc, string asm, string cstr, 1273226633Sdim list<dag> pattern> 1274226633Sdim : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, 1275226633Sdim pattern> { 1276226633Sdim bits<4> Rt; 1277226633Sdim bits<4> Rt2; 1278226633Sdim bits<4> addr; 1279226633Sdim bits<9> imm; 1280226633Sdim let Inst{31-25} = 0b1110100; 1281226633Sdim let Inst{24} = P; 1282226633Sdim let Inst{23} = imm{8}; 1283226633Sdim let Inst{22} = 1; 1284226633Sdim let Inst{21} = W; 1285226633Sdim let Inst{20} = isLoad; 1286226633Sdim let Inst{19-16} = addr; 1287226633Sdim let Inst{15-12} = Rt{3-0}; 1288226633Sdim let Inst{11-8} = Rt2{3-0}; 1289226633Sdim let Inst{7-0} = imm{7-0}; 1290226633Sdim} 1291195098Sed 1292198090Srdivackyclass T2sI<dag oops, dag iops, InstrItinClass itin, 1293198090Srdivacky string opc, string asm, list<dag> pattern> 1294224145Sdim : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1295195098Sed 1296198090Srdivackyclass T2XI<dag oops, dag iops, InstrItinClass itin, 1297198090Srdivacky string asm, list<dag> pattern> 1298224145Sdim : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 1299198090Srdivackyclass T2JTI<dag oops, dag iops, InstrItinClass itin, 1300198090Srdivacky string asm, list<dag> pattern> 1301224145Sdim : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 1302195098Sed 1303218893Sdim// Move to/from coprocessor instructions 1304261991Sdimclass T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm, 1305261991Sdim list<dag> pattern> 1306261991Sdim : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> { 1307224145Sdim let Inst{31-28} = opc; 1308218893Sdim} 1309198090Srdivacky 1310205218Srdivacky// Two-address instructions 1311205218Srdivackyclass T2XIt<dag oops, dag iops, InstrItinClass itin, 1312205218Srdivacky string asm, string cstr, list<dag> pattern> 1313224145Sdim : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>; 1314198090Srdivacky 1315226633Sdim// T2Ipreldst - Thumb2 pre-indexed load / store instructions. 1316226633Sdimclass T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre, 1317201360Srdivacky dag oops, dag iops, 1318201360Srdivacky AddrMode am, IndexMode im, InstrItinClass itin, 1319195340Sed string opc, string asm, string cstr, list<dag> pattern> 1320224145Sdim : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1321195340Sed let OutOperandList = oops; 1322205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1323218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1324195340Sed let Pattern = pattern; 1325195340Sed list<Predicate> Predicates = [IsThumb2]; 1326226633Sdim let DecoderNamespace = "Thumb2"; 1327226633Sdim 1328226633Sdim bits<4> Rt; 1329226633Sdim bits<13> addr; 1330201360Srdivacky let Inst{31-27} = 0b11111; 1331201360Srdivacky let Inst{26-25} = 0b00; 1332212904Sdim let Inst{24} = signed; 1333212904Sdim let Inst{23} = 0; 1334201360Srdivacky let Inst{22-21} = opcod; 1335212904Sdim let Inst{20} = load; 1336226633Sdim let Inst{19-16} = addr{12-9}; 1337226633Sdim let Inst{15-12} = Rt{3-0}; 1338212904Sdim let Inst{11} = 1; 1339201360Srdivacky // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1340212904Sdim let Inst{10} = pre; // The P bit. 1341226633Sdim let Inst{9} = addr{8}; // Sign bit 1342212904Sdim let Inst{8} = 1; // The W bit. 1343226633Sdim let Inst{7-0} = addr{7-0}; 1344195340Sed 1345226633Sdim let DecoderMethod = "DecodeT2LdStPre"; 1346226633Sdim} 1347218893Sdim 1348226633Sdim// T2Ipostldst - Thumb2 post-indexed load / store instructions. 1349226633Sdimclass T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre, 1350226633Sdim dag oops, dag iops, 1351226633Sdim AddrMode am, IndexMode im, InstrItinClass itin, 1352226633Sdim string opc, string asm, string cstr, list<dag> pattern> 1353226633Sdim : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1354226633Sdim let OutOperandList = oops; 1355226633Sdim let InOperandList = !con(iops, (ins pred:$p)); 1356226633Sdim let AsmString = !strconcat(opc, "${p}", asm); 1357226633Sdim let Pattern = pattern; 1358226633Sdim list<Predicate> Predicates = [IsThumb2]; 1359226633Sdim let DecoderNamespace = "Thumb2"; 1360226633Sdim 1361218893Sdim bits<4> Rt; 1362218893Sdim bits<4> Rn; 1363226633Sdim bits<9> offset; 1364226633Sdim let Inst{31-27} = 0b11111; 1365226633Sdim let Inst{26-25} = 0b00; 1366226633Sdim let Inst{24} = signed; 1367226633Sdim let Inst{23} = 0; 1368226633Sdim let Inst{22-21} = opcod; 1369226633Sdim let Inst{20} = load; 1370226633Sdim let Inst{19-16} = Rn; 1371218893Sdim let Inst{15-12} = Rt{3-0}; 1372226633Sdim let Inst{11} = 1; 1373226633Sdim // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1374226633Sdim let Inst{10} = pre; // The P bit. 1375226633Sdim let Inst{9} = offset{8}; // Sign bit 1376226633Sdim let Inst{8} = 1; // The W bit. 1377226633Sdim let Inst{7-0} = offset{7-0}; 1378226633Sdim 1379226633Sdim let DecoderMethod = "DecodeT2LdStPre"; 1380204642Srdivacky} 1381204642Srdivacky 1382198090Srdivacky// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1383198090Srdivackyclass Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1384218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1385198090Srdivacky} 1386195340Sed 1387198090Srdivacky// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1388198090Srdivackyclass T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1389218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1390198090Srdivacky} 1391198090Srdivacky 1392223017Sdim// T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode. 1393223017Sdimclass T2v6Pat<dag pattern, dag result> : Pat<pattern, result> { 1394223017Sdim list<Predicate> Predicates = [IsThumb2, HasV6T2]; 1395223017Sdim} 1396223017Sdim 1397195098Sed// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1398195098Sedclass T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1399195340Sed list<Predicate> Predicates = [IsThumb2]; 1400195098Sed} 1401195098Sed 1402193323Sed//===----------------------------------------------------------------------===// 1403193323Sed 1404193323Sed//===----------------------------------------------------------------------===// 1405193323Sed// ARM VFP Instruction templates. 1406193323Sed// 1407193323Sed 1408198090Srdivacky// Almost all VFP instructions are predicable. 1409224145Sdimclass VFPI<dag oops, dag iops, AddrMode am, int sz, 1410198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1411198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1412198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1413218893Sdim bits<4> p; 1414218893Sdim let Inst{31-28} = p; 1415198090Srdivacky let OutOperandList = oops; 1416205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1417218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1418198090Srdivacky let Pattern = pattern; 1419218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1420226633Sdim let DecoderNamespace = "VFP"; 1421198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1422198090Srdivacky} 1423198090Srdivacky 1424198090Srdivacky// Special cases 1425224145Sdimclass VFPXI<dag oops, dag iops, AddrMode am, int sz, 1426198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1427198090Srdivacky string asm, string cstr, list<dag> pattern> 1428198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1429218893Sdim bits<4> p; 1430218893Sdim let Inst{31-28} = p; 1431198090Srdivacky let OutOperandList = oops; 1432198090Srdivacky let InOperandList = iops; 1433208599Srdivacky let AsmString = asm; 1434198090Srdivacky let Pattern = pattern; 1435218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1436226633Sdim let DecoderNamespace = "VFP"; 1437198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1438198090Srdivacky} 1439198090Srdivacky 1440198090Srdivackyclass VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1441198090Srdivacky string opc, string asm, list<dag> pattern> 1442224145Sdim : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 1443218893Sdim opc, asm, "", pattern> { 1444218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1445218893Sdim} 1446198090Srdivacky 1447193323Sed// ARM VFP addrmode5 loads and stores 1448193323Sedclass ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1449198090Srdivacky InstrItinClass itin, 1450193323Sed string opc, string asm, list<dag> pattern> 1451224145Sdim : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1452206083Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1453218893Sdim // Instruction operands. 1454218893Sdim bits<5> Dd; 1455218893Sdim bits<13> addr; 1456218893Sdim 1457218893Sdim // Encode instruction operands. 1458218893Sdim let Inst{23} = addr{8}; // U (add = (U == '1')) 1459218893Sdim let Inst{22} = Dd{4}; 1460218893Sdim let Inst{19-16} = addr{12-9}; // Rn 1461218893Sdim let Inst{15-12} = Dd{3-0}; 1462218893Sdim let Inst{7-0} = addr{7-0}; // imm8 1463218893Sdim 1464193323Sed let Inst{27-24} = opcod1; 1465193323Sed let Inst{21-20} = opcod2; 1466218893Sdim let Inst{11-9} = 0b101; 1467218893Sdim let Inst{8} = 1; // Double precision 1468198892Srdivacky 1469218893Sdim // Loads & stores operate on both NEON and VFP pipelines. 1470206274Srdivacky let D = VFPNeonDomain; 1471193323Sed} 1472193323Sed 1473193323Sedclass ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1474198090Srdivacky InstrItinClass itin, 1475193323Sed string opc, string asm, list<dag> pattern> 1476224145Sdim : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1477206083Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1478218893Sdim // Instruction operands. 1479218893Sdim bits<5> Sd; 1480218893Sdim bits<13> addr; 1481218893Sdim 1482218893Sdim // Encode instruction operands. 1483218893Sdim let Inst{23} = addr{8}; // U (add = (U == '1')) 1484218893Sdim let Inst{22} = Sd{0}; 1485218893Sdim let Inst{19-16} = addr{12-9}; // Rn 1486218893Sdim let Inst{15-12} = Sd{4-1}; 1487218893Sdim let Inst{7-0} = addr{7-0}; // imm8 1488218893Sdim 1489193323Sed let Inst{27-24} = opcod1; 1490193323Sed let Inst{21-20} = opcod2; 1491218893Sdim let Inst{11-9} = 0b101; 1492218893Sdim let Inst{8} = 0; // Single precision 1493218893Sdim 1494218893Sdim // Loads & stores operate on both NEON and VFP pipelines. 1495218893Sdim let D = VFPNeonDomain; 1496193323Sed} 1497193323Sed 1498218893Sdim// VFP Load / store multiple pseudo instructions. 1499218893Sdimclass PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1500218893Sdim list<dag> pattern> 1501224145Sdim : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain, 1502218893Sdim cstr, itin> { 1503218893Sdim let OutOperandList = oops; 1504218893Sdim let InOperandList = !con(iops, (ins pred:$p)); 1505218893Sdim let Pattern = pattern; 1506218893Sdim list<Predicate> Predicates = [HasVFP2]; 1507218893Sdim} 1508218893Sdim 1509193323Sed// Load / store multiple 1510261991Sdim 1511261991Sdim// Unknown precision 1512261991Sdimclass AXXI4<dag oops, dag iops, IndexMode im, 1513261991Sdim string asm, string cstr, list<dag> pattern> 1514261991Sdim : VFPXI<oops, iops, AddrMode4, 4, im, 1515261991Sdim VFPLdStFrm, NoItinerary, asm, cstr, pattern> { 1516261991Sdim // Instruction operands. 1517261991Sdim bits<4> Rn; 1518261991Sdim bits<13> regs; 1519261991Sdim 1520261991Sdim // Encode instruction operands. 1521261991Sdim let Inst{19-16} = Rn; 1522261991Sdim let Inst{22} = 0; 1523261991Sdim let Inst{15-12} = regs{11-8}; 1524261991Sdim let Inst{7-1} = regs{7-1}; 1525261991Sdim 1526261991Sdim let Inst{27-25} = 0b110; 1527261991Sdim let Inst{11-8} = 0b1011; 1528261991Sdim let Inst{0} = 1; 1529261991Sdim} 1530261991Sdim 1531261991Sdim// Double precision 1532212904Sdimclass AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1533205218Srdivacky string asm, string cstr, list<dag> pattern> 1534224145Sdim : VFPXI<oops, iops, AddrMode4, 4, im, 1535206083Srdivacky VFPLdStMulFrm, itin, asm, cstr, pattern> { 1536218893Sdim // Instruction operands. 1537218893Sdim bits<4> Rn; 1538218893Sdim bits<13> regs; 1539218893Sdim 1540218893Sdim // Encode instruction operands. 1541218893Sdim let Inst{19-16} = Rn; 1542218893Sdim let Inst{22} = regs{12}; 1543218893Sdim let Inst{15-12} = regs{11-8}; 1544261991Sdim let Inst{7-1} = regs{7-1}; 1545218893Sdim 1546193323Sed let Inst{27-25} = 0b110; 1547218893Sdim let Inst{11-9} = 0b101; 1548218893Sdim let Inst{8} = 1; // Double precision 1549261991Sdim let Inst{0} = 0; 1550193323Sed} 1551193323Sed 1552261991Sdim// Single Precision 1553212904Sdimclass AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1554205218Srdivacky string asm, string cstr, list<dag> pattern> 1555224145Sdim : VFPXI<oops, iops, AddrMode4, 4, im, 1556206083Srdivacky VFPLdStMulFrm, itin, asm, cstr, pattern> { 1557218893Sdim // Instruction operands. 1558218893Sdim bits<4> Rn; 1559218893Sdim bits<13> regs; 1560218893Sdim 1561218893Sdim // Encode instruction operands. 1562218893Sdim let Inst{19-16} = Rn; 1563218893Sdim let Inst{22} = regs{8}; 1564218893Sdim let Inst{15-12} = regs{12-9}; 1565218893Sdim let Inst{7-0} = regs{7-0}; 1566218893Sdim 1567193323Sed let Inst{27-25} = 0b110; 1568218893Sdim let Inst{11-9} = 0b101; 1569218893Sdim let Inst{8} = 0; // Single precision 1570193323Sed} 1571193323Sed 1572193323Sed// Double precision, unary 1573203954Srdivackyclass ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1574203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1575203954Srdivacky string asm, list<dag> pattern> 1576198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1577218893Sdim // Instruction operands. 1578218893Sdim bits<5> Dd; 1579218893Sdim bits<5> Dm; 1580218893Sdim 1581218893Sdim // Encode instruction operands. 1582218893Sdim let Inst{3-0} = Dm{3-0}; 1583218893Sdim let Inst{5} = Dm{4}; 1584218893Sdim let Inst{15-12} = Dd{3-0}; 1585218893Sdim let Inst{22} = Dd{4}; 1586218893Sdim 1587203954Srdivacky let Inst{27-23} = opcod1; 1588203954Srdivacky let Inst{21-20} = opcod2; 1589203954Srdivacky let Inst{19-16} = opcod3; 1590218893Sdim let Inst{11-9} = 0b101; 1591218893Sdim let Inst{8} = 1; // Double precision 1592203954Srdivacky let Inst{7-6} = opcod4; 1593203954Srdivacky let Inst{4} = opcod5; 1594261991Sdim 1595261991Sdim let Predicates = [HasVFP2, HasDPVFP]; 1596193323Sed} 1597193323Sed 1598261991Sdim// Double precision, unary, not-predicated 1599261991Sdimclass ADuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1600261991Sdim bit opcod5, dag oops, dag iops, InstrItinClass itin, 1601261991Sdim string asm, list<dag> pattern> 1602261991Sdim : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPUnaryFrm, itin, asm, "", pattern> { 1603261991Sdim // Instruction operands. 1604261991Sdim bits<5> Dd; 1605261991Sdim bits<5> Dm; 1606261991Sdim 1607261991Sdim let Inst{31-28} = 0b1111; 1608261991Sdim 1609261991Sdim // Encode instruction operands. 1610261991Sdim let Inst{3-0} = Dm{3-0}; 1611261991Sdim let Inst{5} = Dm{4}; 1612261991Sdim let Inst{15-12} = Dd{3-0}; 1613261991Sdim let Inst{22} = Dd{4}; 1614261991Sdim 1615261991Sdim let Inst{27-23} = opcod1; 1616261991Sdim let Inst{21-20} = opcod2; 1617261991Sdim let Inst{19-16} = opcod3; 1618261991Sdim let Inst{11-9} = 0b101; 1619261991Sdim let Inst{8} = 1; // Double precision 1620261991Sdim let Inst{7-6} = opcod4; 1621261991Sdim let Inst{4} = opcod5; 1622261991Sdim} 1623261991Sdim 1624193323Sed// Double precision, binary 1625203954Srdivackyclass ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1626206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1627206083Srdivacky list<dag> pattern> 1628198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1629218893Sdim // Instruction operands. 1630218893Sdim bits<5> Dd; 1631218893Sdim bits<5> Dn; 1632218893Sdim bits<5> Dm; 1633193323Sed 1634218893Sdim // Encode instruction operands. 1635218893Sdim let Inst{3-0} = Dm{3-0}; 1636218893Sdim let Inst{5} = Dm{4}; 1637218893Sdim let Inst{19-16} = Dn{3-0}; 1638218893Sdim let Inst{7} = Dn{4}; 1639218893Sdim let Inst{15-12} = Dd{3-0}; 1640218893Sdim let Inst{22} = Dd{4}; 1641218893Sdim 1642206083Srdivacky let Inst{27-23} = opcod1; 1643206083Srdivacky let Inst{21-20} = opcod2; 1644218893Sdim let Inst{11-9} = 0b101; 1645218893Sdim let Inst{8} = 1; // Double precision 1646212904Sdim let Inst{6} = op6; 1647212904Sdim let Inst{4} = op4; 1648261991Sdim 1649261991Sdim let Predicates = [HasVFP2, HasDPVFP]; 1650206083Srdivacky} 1651206083Srdivacky 1652261991Sdim// FP, binary, not predicated 1653261991Sdimclass ADbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, 1654261991Sdim InstrItinClass itin, string asm, list<dag> pattern> 1655261991Sdim : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPBinaryFrm, itin, 1656261991Sdim asm, "", pattern> 1657261991Sdim{ 1658261991Sdim // Instruction operands. 1659261991Sdim bits<5> Dd; 1660261991Sdim bits<5> Dn; 1661261991Sdim bits<5> Dm; 1662261991Sdim 1663261991Sdim let Inst{31-28} = 0b1111; 1664261991Sdim 1665261991Sdim // Encode instruction operands. 1666261991Sdim let Inst{3-0} = Dm{3-0}; 1667261991Sdim let Inst{5} = Dm{4}; 1668261991Sdim let Inst{19-16} = Dn{3-0}; 1669261991Sdim let Inst{7} = Dn{4}; 1670261991Sdim let Inst{15-12} = Dd{3-0}; 1671261991Sdim let Inst{22} = Dd{4}; 1672261991Sdim 1673261991Sdim let Inst{27-23} = opcod1; 1674261991Sdim let Inst{21-20} = opcod2; 1675261991Sdim let Inst{11-9} = 0b101; 1676261991Sdim let Inst{8} = 1; // double precision 1677261991Sdim let Inst{6} = opcod3; 1678261991Sdim let Inst{4} = 0; 1679261991Sdim 1680261991Sdim let Predicates = [HasVFP2, HasDPVFP]; 1681261991Sdim} 1682261991Sdim 1683261991Sdim// Single precision, unary, predicated 1684203954Srdivackyclass ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1685203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1686203954Srdivacky string asm, list<dag> pattern> 1687198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1688218893Sdim // Instruction operands. 1689218893Sdim bits<5> Sd; 1690218893Sdim bits<5> Sm; 1691218893Sdim 1692218893Sdim // Encode instruction operands. 1693218893Sdim let Inst{3-0} = Sm{4-1}; 1694218893Sdim let Inst{5} = Sm{0}; 1695218893Sdim let Inst{15-12} = Sd{4-1}; 1696218893Sdim let Inst{22} = Sd{0}; 1697218893Sdim 1698203954Srdivacky let Inst{27-23} = opcod1; 1699203954Srdivacky let Inst{21-20} = opcod2; 1700203954Srdivacky let Inst{19-16} = opcod3; 1701218893Sdim let Inst{11-9} = 0b101; 1702218893Sdim let Inst{8} = 0; // Single precision 1703203954Srdivacky let Inst{7-6} = opcod4; 1704203954Srdivacky let Inst{4} = opcod5; 1705193323Sed} 1706193323Sed 1707261991Sdim// Single precision, unary, non-predicated 1708261991Sdimclass ASuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1709261991Sdim bit opcod5, dag oops, dag iops, InstrItinClass itin, 1710261991Sdim string asm, list<dag> pattern> 1711261991Sdim : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, 1712261991Sdim VFPUnaryFrm, itin, asm, "", pattern> { 1713261991Sdim // Instruction operands. 1714261991Sdim bits<5> Sd; 1715261991Sdim bits<5> Sm; 1716261991Sdim 1717261991Sdim let Inst{31-28} = 0b1111; 1718261991Sdim 1719261991Sdim // Encode instruction operands. 1720261991Sdim let Inst{3-0} = Sm{4-1}; 1721261991Sdim let Inst{5} = Sm{0}; 1722261991Sdim let Inst{15-12} = Sd{4-1}; 1723261991Sdim let Inst{22} = Sd{0}; 1724261991Sdim 1725261991Sdim let Inst{27-23} = opcod1; 1726261991Sdim let Inst{21-20} = opcod2; 1727261991Sdim let Inst{19-16} = opcod3; 1728261991Sdim let Inst{11-9} = 0b101; 1729261991Sdim let Inst{8} = 0; // Single precision 1730261991Sdim let Inst{7-6} = opcod4; 1731261991Sdim let Inst{4} = opcod5; 1732261991Sdim} 1733261991Sdim 1734218893Sdim// Single precision unary, if no NEON. Same as ASuI except not available if 1735218893Sdim// NEON is enabled. 1736203954Srdivackyclass ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1737203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1738203954Srdivacky string asm, list<dag> pattern> 1739203954Srdivacky : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1740203954Srdivacky pattern> { 1741198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1742198090Srdivacky} 1743198090Srdivacky 1744193323Sed// Single precision, binary 1745203954Srdivackyclass ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1746203954Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1747198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1748218893Sdim // Instruction operands. 1749218893Sdim bits<5> Sd; 1750218893Sdim bits<5> Sn; 1751218893Sdim bits<5> Sm; 1752218893Sdim 1753218893Sdim // Encode instruction operands. 1754218893Sdim let Inst{3-0} = Sm{4-1}; 1755218893Sdim let Inst{5} = Sm{0}; 1756218893Sdim let Inst{19-16} = Sn{4-1}; 1757218893Sdim let Inst{7} = Sn{0}; 1758218893Sdim let Inst{15-12} = Sd{4-1}; 1759218893Sdim let Inst{22} = Sd{0}; 1760218893Sdim 1761203954Srdivacky let Inst{27-23} = opcod1; 1762203954Srdivacky let Inst{21-20} = opcod2; 1763218893Sdim let Inst{11-9} = 0b101; 1764218893Sdim let Inst{8} = 0; // Single precision 1765212904Sdim let Inst{6} = op6; 1766212904Sdim let Inst{4} = op4; 1767193323Sed} 1768193323Sed 1769261991Sdim// Single precision, binary, not predicated 1770261991Sdimclass ASbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, 1771261991Sdim InstrItinClass itin, string asm, list<dag> pattern> 1772261991Sdim : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, 1773261991Sdim VFPBinaryFrm, itin, asm, "", pattern> 1774261991Sdim{ 1775261991Sdim // Instruction operands. 1776261991Sdim bits<5> Sd; 1777261991Sdim bits<5> Sn; 1778261991Sdim bits<5> Sm; 1779261991Sdim 1780261991Sdim let Inst{31-28} = 0b1111; 1781261991Sdim 1782261991Sdim // Encode instruction operands. 1783261991Sdim let Inst{3-0} = Sm{4-1}; 1784261991Sdim let Inst{5} = Sm{0}; 1785261991Sdim let Inst{19-16} = Sn{4-1}; 1786261991Sdim let Inst{7} = Sn{0}; 1787261991Sdim let Inst{15-12} = Sd{4-1}; 1788261991Sdim let Inst{22} = Sd{0}; 1789261991Sdim 1790261991Sdim let Inst{27-23} = opcod1; 1791261991Sdim let Inst{21-20} = opcod2; 1792261991Sdim let Inst{11-9} = 0b101; 1793261991Sdim let Inst{8} = 0; // Single precision 1794261991Sdim let Inst{6} = opcod3; 1795261991Sdim let Inst{4} = 0; 1796261991Sdim} 1797261991Sdim 1798218893Sdim// Single precision binary, if no NEON. Same as ASbI except not available if 1799218893Sdim// NEON is enabled. 1800203954Srdivackyclass ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1801206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1802206083Srdivacky list<dag> pattern> 1803203954Srdivacky : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1804198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1805218893Sdim 1806218893Sdim // Instruction operands. 1807218893Sdim bits<5> Sd; 1808218893Sdim bits<5> Sn; 1809218893Sdim bits<5> Sm; 1810218893Sdim 1811218893Sdim // Encode instruction operands. 1812218893Sdim let Inst{3-0} = Sm{4-1}; 1813218893Sdim let Inst{5} = Sm{0}; 1814218893Sdim let Inst{19-16} = Sn{4-1}; 1815218893Sdim let Inst{7} = Sn{0}; 1816218893Sdim let Inst{15-12} = Sd{4-1}; 1817218893Sdim let Inst{22} = Sd{0}; 1818198090Srdivacky} 1819198090Srdivacky 1820193323Sed// VFP conversion instructions 1821203954Srdivackyclass AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1822203954Srdivacky dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1823203954Srdivacky list<dag> pattern> 1824198090Srdivacky : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1825203954Srdivacky let Inst{27-23} = opcod1; 1826203954Srdivacky let Inst{21-20} = opcod2; 1827203954Srdivacky let Inst{19-16} = opcod3; 1828203954Srdivacky let Inst{11-8} = opcod4; 1829193323Sed let Inst{6} = 1; 1830203954Srdivacky let Inst{4} = 0; 1831193323Sed} 1832193323Sed 1833203954Srdivacky// VFP conversion between floating-point and fixed-point 1834203954Srdivackyclass AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1835206083Srdivacky dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1836206083Srdivacky list<dag> pattern> 1837203954Srdivacky : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1838234353Sdim bits<5> fbits; 1839203954Srdivacky // size (fixed-point number): sx == 0 ? 16 : 32 1840203954Srdivacky let Inst{7} = op5; // sx 1841234353Sdim let Inst{5} = fbits{0}; 1842234353Sdim let Inst{3-0} = fbits{4-1}; 1843203954Srdivacky} 1844203954Srdivacky 1845198090Srdivacky// VFP conversion instructions, if no NEON 1846203954Srdivackyclass AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1847198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1848198090Srdivacky string opc, string asm, list<dag> pattern> 1849203954Srdivacky : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1850203954Srdivacky pattern> { 1851198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1852198090Srdivacky} 1853198090Srdivacky 1854193323Sedclass AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1855198090Srdivacky InstrItinClass itin, 1856198090Srdivacky string opc, string asm, list<dag> pattern> 1857198090Srdivacky : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1858193323Sed let Inst{27-20} = opcod1; 1859193323Sed let Inst{11-8} = opcod2; 1860193323Sed let Inst{4} = 1; 1861193323Sed} 1862193323Sed 1863198090Srdivackyclass AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1864198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1865198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1866193323Sed 1867206083Srdivackyclass AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1868198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1869198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1870193323Sed 1871198090Srdivackyclass AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1872198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1873198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1874193323Sed 1875198090Srdivackyclass AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1876198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1877198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1878193323Sed 1879193323Sed//===----------------------------------------------------------------------===// 1880193323Sed 1881194710Sed//===----------------------------------------------------------------------===// 1882194710Sed// ARM NEON Instruction templates. 1883194710Sed// 1884193323Sed 1885205407Srdivackyclass NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1886205407Srdivacky InstrItinClass itin, string opc, string dt, string asm, string cstr, 1887205407Srdivacky list<dag> pattern> 1888224145Sdim : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1889194710Sed let OutOperandList = oops; 1890205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1891218893Sdim let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1892194710Sed let Pattern = pattern; 1893194710Sed list<Predicate> Predicates = [HasNEON]; 1894226633Sdim let DecoderNamespace = "NEON"; 1895193323Sed} 1896193323Sed 1897199989Srdivacky// Same as NeonI except it does not have a "data type" specifier. 1898206083Srdivackyclass NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1899206083Srdivacky InstrItinClass itin, string opc, string asm, string cstr, 1900206083Srdivacky list<dag> pattern> 1901224145Sdim : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1902199989Srdivacky let OutOperandList = oops; 1903205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1904218893Sdim let AsmString = !strconcat(opc, "${p}", "\t", asm); 1905199989Srdivacky let Pattern = pattern; 1906199989Srdivacky list<Predicate> Predicates = [HasNEON]; 1907226633Sdim let DecoderNamespace = "NEON"; 1908193323Sed} 1909194710Sed 1910261991Sdim// Same as NeonI except it is not predicated 1911261991Sdimclass NeonInp<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1912261991Sdim InstrItinClass itin, string opc, string dt, string asm, string cstr, 1913261991Sdim list<dag> pattern> 1914261991Sdim : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1915261991Sdim let OutOperandList = oops; 1916261991Sdim let InOperandList = iops; 1917261991Sdim let AsmString = !strconcat(opc, ".", dt, "\t", asm); 1918261991Sdim let Pattern = pattern; 1919261991Sdim list<Predicate> Predicates = [HasNEON]; 1920261991Sdim let DecoderNamespace = "NEON"; 1921261991Sdim 1922261991Sdim let Inst{31-28} = 0b1111; 1923261991Sdim} 1924261991Sdim 1925198090Srdivackyclass NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1926198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1927199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1928205407Srdivacky : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1929205407Srdivacky cstr, pattern> { 1930198090Srdivacky let Inst{31-24} = 0b11110100; 1931212904Sdim let Inst{23} = op23; 1932198396Srdivacky let Inst{21-20} = op21_20; 1933212904Sdim let Inst{11-8} = op11_8; 1934212904Sdim let Inst{7-4} = op7_4; 1935218893Sdim 1936218893Sdim let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1937226633Sdim let DecoderNamespace = "NEONLoadStore"; 1938218893Sdim 1939218893Sdim bits<5> Vd; 1940218893Sdim bits<6> Rn; 1941218893Sdim bits<4> Rm; 1942218893Sdim 1943218893Sdim let Inst{22} = Vd{4}; 1944218893Sdim let Inst{15-12} = Vd{3-0}; 1945218893Sdim let Inst{19-16} = Rn{3-0}; 1946218893Sdim let Inst{3-0} = Rm{3-0}; 1947198090Srdivacky} 1948198090Srdivacky 1949218893Sdimclass NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1950218893Sdim dag oops, dag iops, InstrItinClass itin, 1951218893Sdim string opc, string dt, string asm, string cstr, list<dag> pattern> 1952218893Sdim : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1953218893Sdim dt, asm, cstr, pattern> { 1954218893Sdim bits<3> lane; 1955218893Sdim} 1956218893Sdim 1957212904Sdimclass PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1958224145Sdim : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1959212904Sdim itin> { 1960212904Sdim let OutOperandList = oops; 1961212904Sdim let InOperandList = !con(iops, (ins pred:$p)); 1962212904Sdim list<Predicate> Predicates = [HasNEON]; 1963212904Sdim} 1964212904Sdim 1965218893Sdimclass PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1966218893Sdim list<dag> pattern> 1967224145Sdim : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1968218893Sdim itin> { 1969218893Sdim let OutOperandList = oops; 1970218893Sdim let InOperandList = !con(iops, (ins pred:$p)); 1971218893Sdim let Pattern = pattern; 1972218893Sdim list<Predicate> Predicates = [HasNEON]; 1973218893Sdim} 1974218893Sdim 1975206083Srdivackyclass NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1976199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1977206083Srdivacky : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1978206083Srdivacky pattern> { 1979194710Sed let Inst{31-25} = 0b1111001; 1980218893Sdim let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1981226633Sdim let DecoderNamespace = "NEONData"; 1982194710Sed} 1983194710Sed 1984206083Srdivackyclass NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1985206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1986206083Srdivacky : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1987206083Srdivacky cstr, pattern> { 1988199989Srdivacky let Inst{31-25} = 0b1111001; 1989218893Sdim let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1990226633Sdim let DecoderNamespace = "NEONData"; 1991199989Srdivacky} 1992199989Srdivacky 1993194710Sed// NEON "one register and a modified immediate" format. 1994194710Sedclass N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1995194710Sed bit op5, bit op4, 1996198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1997206083Srdivacky string opc, string dt, string asm, string cstr, 1998206083Srdivacky list<dag> pattern> 1999206083Srdivacky : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 2000212904Sdim let Inst{23} = op23; 2001194710Sed let Inst{21-19} = op21_19; 2002212904Sdim let Inst{11-8} = op11_8; 2003212904Sdim let Inst{7} = op7; 2004212904Sdim let Inst{6} = op6; 2005212904Sdim let Inst{5} = op5; 2006212904Sdim let Inst{4} = op4; 2007218893Sdim 2008218893Sdim // Instruction operands. 2009218893Sdim bits<5> Vd; 2010218893Sdim bits<13> SIMM; 2011218893Sdim 2012218893Sdim let Inst{15-12} = Vd{3-0}; 2013218893Sdim let Inst{22} = Vd{4}; 2014218893Sdim let Inst{24} = SIMM{7}; 2015218893Sdim let Inst{18-16} = SIMM{6-4}; 2016218893Sdim let Inst{3-0} = SIMM{3-0}; 2017226633Sdim let DecoderMethod = "DecodeNEONModImmInstruction"; 2018194710Sed} 2019194710Sed 2020194710Sed// NEON 2 vector register format. 2021194710Sedclass N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 2022194710Sed bits<5> op11_7, bit op6, bit op4, 2023198090Srdivacky dag oops, dag iops, InstrItinClass itin, 2024199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 2025206083Srdivacky : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 2026194710Sed let Inst{24-23} = op24_23; 2027194710Sed let Inst{21-20} = op21_20; 2028194710Sed let Inst{19-18} = op19_18; 2029194710Sed let Inst{17-16} = op17_16; 2030212904Sdim let Inst{11-7} = op11_7; 2031212904Sdim let Inst{6} = op6; 2032212904Sdim let Inst{4} = op4; 2033218893Sdim 2034218893Sdim // Instruction operands. 2035218893Sdim bits<5> Vd; 2036218893Sdim bits<5> Vm; 2037218893Sdim 2038218893Sdim let Inst{15-12} = Vd{3-0}; 2039218893Sdim let Inst{22} = Vd{4}; 2040218893Sdim let Inst{3-0} = Vm{3-0}; 2041218893Sdim let Inst{5} = Vm{4}; 2042194710Sed} 2043194710Sed 2044261991Sdim// Same as N2V but not predicated. 2045261991Sdimclass N2Vnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6, 2046261991Sdim dag oops, dag iops, InstrItinClass itin, string OpcodeStr, 2047276479Sdim string Dt, list<dag> pattern> 2048261991Sdim : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N2RegFrm, itin, 2049261991Sdim OpcodeStr, Dt, "$Vd, $Vm", "", pattern> { 2050261991Sdim bits<5> Vd; 2051261991Sdim bits<5> Vm; 2052261991Sdim 2053261991Sdim // Encode instruction operands 2054261991Sdim let Inst{22} = Vd{4}; 2055261991Sdim let Inst{15-12} = Vd{3-0}; 2056261991Sdim let Inst{5} = Vm{4}; 2057261991Sdim let Inst{3-0} = Vm{3-0}; 2058261991Sdim 2059261991Sdim // Encode constant bits 2060261991Sdim let Inst{27-23} = 0b00111; 2061261991Sdim let Inst{21-20} = 0b11; 2062261991Sdim let Inst{19-18} = op19_18; 2063261991Sdim let Inst{17-16} = op17_16; 2064261991Sdim let Inst{11} = 0; 2065261991Sdim let Inst{10-8} = op10_8; 2066261991Sdim let Inst{7} = op7; 2067261991Sdim let Inst{6} = op6; 2068261991Sdim let Inst{4} = 0; 2069261991Sdim 2070261991Sdim let DecoderNamespace = "NEON"; 2071261991Sdim} 2072261991Sdim 2073199989Srdivacky// Same as N2V except it doesn't have a datatype suffix. 2074199989Srdivackyclass N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 2075206083Srdivacky bits<5> op11_7, bit op6, bit op4, 2076206083Srdivacky dag oops, dag iops, InstrItinClass itin, 2077206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 2078206083Srdivacky : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 2079198396Srdivacky let Inst{24-23} = op24_23; 2080198396Srdivacky let Inst{21-20} = op21_20; 2081199989Srdivacky let Inst{19-18} = op19_18; 2082199989Srdivacky let Inst{17-16} = op17_16; 2083212904Sdim let Inst{11-7} = op11_7; 2084212904Sdim let Inst{6} = op6; 2085212904Sdim let Inst{4} = op4; 2086218893Sdim 2087218893Sdim // Instruction operands. 2088218893Sdim bits<5> Vd; 2089218893Sdim bits<5> Vm; 2090218893Sdim 2091218893Sdim let Inst{15-12} = Vd{3-0}; 2092218893Sdim let Inst{22} = Vd{4}; 2093218893Sdim let Inst{3-0} = Vm{3-0}; 2094218893Sdim let Inst{5} = Vm{4}; 2095198396Srdivacky} 2096198396Srdivacky 2097194710Sed// NEON 2 vector register with immediate. 2098198396Srdivackyclass N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 2099206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 2100199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 2101206083Srdivacky : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2102212904Sdim let Inst{24} = op24; 2103212904Sdim let Inst{23} = op23; 2104194710Sed let Inst{11-8} = op11_8; 2105212904Sdim let Inst{7} = op7; 2106212904Sdim let Inst{6} = op6; 2107212904Sdim let Inst{4} = op4; 2108218893Sdim 2109218893Sdim // Instruction operands. 2110218893Sdim bits<5> Vd; 2111218893Sdim bits<5> Vm; 2112218893Sdim bits<6> SIMM; 2113218893Sdim 2114218893Sdim let Inst{15-12} = Vd{3-0}; 2115218893Sdim let Inst{22} = Vd{4}; 2116218893Sdim let Inst{3-0} = Vm{3-0}; 2117218893Sdim let Inst{5} = Vm{4}; 2118218893Sdim let Inst{21-16} = SIMM{5-0}; 2119194710Sed} 2120194710Sed 2121194710Sed// NEON 3 vector register format. 2122221345Sdim 2123223017Sdimclass N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 2124223017Sdim bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 2125223017Sdim string opc, string dt, string asm, string cstr, 2126223017Sdim list<dag> pattern> 2127206083Srdivacky : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2128212904Sdim let Inst{24} = op24; 2129212904Sdim let Inst{23} = op23; 2130194710Sed let Inst{21-20} = op21_20; 2131212904Sdim let Inst{11-8} = op11_8; 2132212904Sdim let Inst{6} = op6; 2133212904Sdim let Inst{4} = op4; 2134221345Sdim} 2135218893Sdim 2136221345Sdimclass N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 2137221345Sdim dag oops, dag iops, Format f, InstrItinClass itin, 2138221345Sdim string opc, string dt, string asm, string cstr, list<dag> pattern> 2139221345Sdim : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 2140221345Sdim oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2141218893Sdim // Instruction operands. 2142218893Sdim bits<5> Vd; 2143218893Sdim bits<5> Vn; 2144218893Sdim bits<5> Vm; 2145218893Sdim 2146218893Sdim let Inst{15-12} = Vd{3-0}; 2147218893Sdim let Inst{22} = Vd{4}; 2148218893Sdim let Inst{19-16} = Vn{3-0}; 2149218893Sdim let Inst{7} = Vn{4}; 2150218893Sdim let Inst{3-0} = Vm{3-0}; 2151218893Sdim let Inst{5} = Vm{4}; 2152194710Sed} 2153194710Sed 2154261991Sdimclass N3Vnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6, 2155261991Sdim bit op4, dag oops, dag iops,Format f, InstrItinClass itin, 2156276479Sdim string OpcodeStr, string Dt, list<dag> pattern> 2157261991Sdim : NeonInp<oops, iops, AddrModeNone, IndexModeNone, f, itin, OpcodeStr, 2158261991Sdim Dt, "$Vd, $Vn, $Vm", "", pattern> { 2159261991Sdim bits<5> Vd; 2160261991Sdim bits<5> Vn; 2161261991Sdim bits<5> Vm; 2162261991Sdim 2163261991Sdim // Encode instruction operands 2164261991Sdim let Inst{22} = Vd{4}; 2165261991Sdim let Inst{15-12} = Vd{3-0}; 2166261991Sdim let Inst{19-16} = Vn{3-0}; 2167261991Sdim let Inst{7} = Vn{4}; 2168261991Sdim let Inst{5} = Vm{4}; 2169261991Sdim let Inst{3-0} = Vm{3-0}; 2170261991Sdim 2171261991Sdim // Encode constant bits 2172261991Sdim let Inst{27-23} = op27_23; 2173261991Sdim let Inst{21-20} = op21_20; 2174261991Sdim let Inst{11-8} = op11_8; 2175261991Sdim let Inst{6} = op6; 2176261991Sdim let Inst{4} = op4; 2177261991Sdim} 2178261991Sdim 2179223017Sdimclass N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 2180223017Sdim bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 2181223017Sdim string opc, string dt, string asm, string cstr, 2182223017Sdim list<dag> pattern> 2183221345Sdim : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 2184221345Sdim oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2185221345Sdim 2186221345Sdim // Instruction operands. 2187221345Sdim bits<5> Vd; 2188221345Sdim bits<5> Vn; 2189221345Sdim bits<5> Vm; 2190221345Sdim bit lane; 2191221345Sdim 2192221345Sdim let Inst{15-12} = Vd{3-0}; 2193221345Sdim let Inst{22} = Vd{4}; 2194221345Sdim let Inst{19-16} = Vn{3-0}; 2195221345Sdim let Inst{7} = Vn{4}; 2196221345Sdim let Inst{3-0} = Vm{3-0}; 2197221345Sdim let Inst{5} = lane; 2198221345Sdim} 2199221345Sdim 2200223017Sdimclass N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 2201223017Sdim bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 2202223017Sdim string opc, string dt, string asm, string cstr, 2203223017Sdim list<dag> pattern> 2204221345Sdim : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 2205221345Sdim oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2206221345Sdim 2207221345Sdim // Instruction operands. 2208221345Sdim bits<5> Vd; 2209221345Sdim bits<5> Vn; 2210221345Sdim bits<5> Vm; 2211221345Sdim bits<2> lane; 2212221345Sdim 2213221345Sdim let Inst{15-12} = Vd{3-0}; 2214221345Sdim let Inst{22} = Vd{4}; 2215221345Sdim let Inst{19-16} = Vn{3-0}; 2216221345Sdim let Inst{7} = Vn{4}; 2217221345Sdim let Inst{2-0} = Vm{2-0}; 2218221345Sdim let Inst{5} = lane{1}; 2219221345Sdim let Inst{3} = lane{0}; 2220221345Sdim} 2221221345Sdim 2222206083Srdivacky// Same as N3V except it doesn't have a data type suffix. 2223206083Srdivackyclass N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 2224206083Srdivacky bit op4, 2225206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 2226206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 2227206083Srdivacky : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 2228212904Sdim let Inst{24} = op24; 2229212904Sdim let Inst{23} = op23; 2230198396Srdivacky let Inst{21-20} = op21_20; 2231212904Sdim let Inst{11-8} = op11_8; 2232212904Sdim let Inst{6} = op6; 2233212904Sdim let Inst{4} = op4; 2234218893Sdim 2235218893Sdim // Instruction operands. 2236218893Sdim bits<5> Vd; 2237218893Sdim bits<5> Vn; 2238218893Sdim bits<5> Vm; 2239218893Sdim 2240218893Sdim let Inst{15-12} = Vd{3-0}; 2241218893Sdim let Inst{22} = Vd{4}; 2242218893Sdim let Inst{19-16} = Vn{3-0}; 2243218893Sdim let Inst{7} = Vn{4}; 2244218893Sdim let Inst{3-0} = Vm{3-0}; 2245218893Sdim let Inst{5} = Vm{4}; 2246198396Srdivacky} 2247198396Srdivacky 2248194710Sed// NEON VMOVs between scalar and core registers. 2249194710Sedclass NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2250198090Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 2251199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 2252224145Sdim : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain, 2253206083Srdivacky "", itin> { 2254194710Sed let Inst{27-20} = opcod1; 2255212904Sdim let Inst{11-8} = opcod2; 2256212904Sdim let Inst{6-5} = opcod3; 2257212904Sdim let Inst{4} = 1; 2258221345Sdim // A8.6.303, A8.6.328, A8.6.329 2259221345Sdim let Inst{3-0} = 0b0000; 2260199989Srdivacky 2261199989Srdivacky let OutOperandList = oops; 2262205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 2263218893Sdim let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 2264199989Srdivacky let Pattern = pattern; 2265194710Sed list<Predicate> Predicates = [HasNEON]; 2266218893Sdim 2267218893Sdim let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 2268226633Sdim let DecoderNamespace = "NEONDup"; 2269218893Sdim 2270218893Sdim bits<5> V; 2271218893Sdim bits<4> R; 2272218893Sdim bits<4> p; 2273218893Sdim bits<4> lane; 2274218893Sdim 2275218893Sdim let Inst{31-28} = p{3-0}; 2276218893Sdim let Inst{7} = V{4}; 2277218893Sdim let Inst{19-16} = V{3-0}; 2278218893Sdim let Inst{15-12} = R{3-0}; 2279194710Sed} 2280194710Sedclass NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2281198090Srdivacky dag oops, dag iops, InstrItinClass itin, 2282199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 2283210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 2284199989Srdivacky opc, dt, asm, pattern>; 2285194710Sedclass NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2286198090Srdivacky dag oops, dag iops, InstrItinClass itin, 2287199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 2288210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 2289199989Srdivacky opc, dt, asm, pattern>; 2290194710Sedclass NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2291198090Srdivacky dag oops, dag iops, InstrItinClass itin, 2292199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 2293210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 2294199989Srdivacky opc, dt, asm, pattern>; 2295198090Srdivacky 2296206083Srdivacky// Vector Duplicate Lane (from scalar to all elements) 2297206083Srdivackyclass NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 2298206083Srdivacky InstrItinClass itin, string opc, string dt, string asm, 2299206083Srdivacky list<dag> pattern> 2300206083Srdivacky : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 2301206083Srdivacky let Inst{24-23} = 0b11; 2302206083Srdivacky let Inst{21-20} = 0b11; 2303206083Srdivacky let Inst{19-16} = op19_16; 2304212904Sdim let Inst{11-7} = 0b11000; 2305212904Sdim let Inst{6} = op6; 2306212904Sdim let Inst{4} = 0; 2307218893Sdim 2308218893Sdim bits<5> Vd; 2309218893Sdim bits<5> Vm; 2310218893Sdim 2311218893Sdim let Inst{22} = Vd{4}; 2312218893Sdim let Inst{15-12} = Vd{3-0}; 2313218893Sdim let Inst{5} = Vm{4}; 2314218893Sdim let Inst{3-0} = Vm{3-0}; 2315206083Srdivacky} 2316206083Srdivacky 2317198090Srdivacky// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 2318198090Srdivacky// for single-precision FP. 2319198090Srdivackyclass NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 2320198090Srdivacky list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 2321198090Srdivacky} 2322234353Sdim 2323234353Sdim// VFP/NEON Instruction aliases for type suffices. 2324234353Sdimclass VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> : 2325234353Sdim InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>; 2326234353Sdim 2327234353Sdimmulticlass VFPDTAnyInstAlias<string opc, string asm, dag Result> { 2328234353Sdim def : VFPDataTypeInstAlias<opc, ".8", asm, Result>; 2329234353Sdim def : VFPDataTypeInstAlias<opc, ".16", asm, Result>; 2330234353Sdim def : VFPDataTypeInstAlias<opc, ".32", asm, Result>; 2331234353Sdim def : VFPDataTypeInstAlias<opc, ".64", asm, Result>; 2332234353Sdim} 2333234353Sdim 2334234353Sdimmulticlass NEONDTAnyInstAlias<string opc, string asm, dag Result> { 2335234353Sdim let Predicates = [HasNEON] in { 2336234353Sdim def : VFPDataTypeInstAlias<opc, ".8", asm, Result>; 2337234353Sdim def : VFPDataTypeInstAlias<opc, ".16", asm, Result>; 2338234353Sdim def : VFPDataTypeInstAlias<opc, ".32", asm, Result>; 2339234353Sdim def : VFPDataTypeInstAlias<opc, ".64", asm, Result>; 2340234353Sdim} 2341234353Sdim} 2342234353Sdim 2343234353Sdim// The same alias classes using AsmPseudo instead, for the more complex 2344234353Sdim// stuff in NEON that InstAlias can't quite handle. 2345234353Sdim// Note that we can't use anonymous defm references here like we can 2346234353Sdim// above, as we care about the ultimate instruction enum names generated, unlike 2347234353Sdim// for instalias defs. 2348234353Sdimclass NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> : 2349234353Sdim AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>; 2350234353Sdim 2351234353Sdim// Data type suffix token aliases. Implements Table A7-3 in the ARM ARM. 2352234353Sdimdef : TokenAlias<".s8", ".i8">; 2353234353Sdimdef : TokenAlias<".u8", ".i8">; 2354234353Sdimdef : TokenAlias<".s16", ".i16">; 2355234353Sdimdef : TokenAlias<".u16", ".i16">; 2356234353Sdimdef : TokenAlias<".s32", ".i32">; 2357234353Sdimdef : TokenAlias<".u32", ".i32">; 2358234353Sdimdef : TokenAlias<".s64", ".i64">; 2359234353Sdimdef : TokenAlias<".u64", ".i64">; 2360234353Sdim 2361234353Sdimdef : TokenAlias<".i8", ".8">; 2362234353Sdimdef : TokenAlias<".i16", ".16">; 2363234353Sdimdef : TokenAlias<".i32", ".32">; 2364234353Sdimdef : TokenAlias<".i64", ".64">; 2365234353Sdim 2366234353Sdimdef : TokenAlias<".p8", ".8">; 2367234353Sdimdef : TokenAlias<".p16", ".16">; 2368234353Sdim 2369234353Sdimdef : TokenAlias<".f32", ".32">; 2370234353Sdimdef : TokenAlias<".f64", ".64">; 2371234353Sdimdef : TokenAlias<".f", ".f32">; 2372234353Sdimdef : TokenAlias<".d", ".f64">; 2373