ARMInstrFormats.td revision 234982
1234353Sdim//===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===// 2206083Srdivacky// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7206083Srdivacky// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// 12193323Sed// ARM Instruction Format Definitions. 13193323Sed// 14193323Sed 15193323Sed// Format specifies the encoding used by the instruction. This is part of the 16193323Sed// ad-hoc solution used to emit machine instruction encodings by our machine 17193323Sed// code emitter. 18205407Srdivackyclass Format<bits<6> val> { 19205407Srdivacky bits<6> Value = val; 20193323Sed} 21193323Sed 22193323Seddef Pseudo : Format<0>; 23193323Seddef MulFrm : Format<1>; 24193323Seddef BrFrm : Format<2>; 25193323Seddef BrMiscFrm : Format<3>; 26193323Sed 27193323Seddef DPFrm : Format<4>; 28226633Sdimdef DPSoRegRegFrm : Format<5>; 29193323Sed 30193323Seddef LdFrm : Format<6>; 31193323Seddef StFrm : Format<7>; 32193323Seddef LdMiscFrm : Format<8>; 33193323Seddef StMiscFrm : Format<9>; 34193323Seddef LdStMulFrm : Format<10>; 35193323Sed 36205407Srdivackydef LdStExFrm : Format<11>; 37200581Srdivacky 38205407Srdivackydef ArithMiscFrm : Format<12>; 39212904Sdimdef SatFrm : Format<13>; 40212904Sdimdef ExtFrm : Format<14>; 41193323Sed 42212904Sdimdef VFPUnaryFrm : Format<15>; 43212904Sdimdef VFPBinaryFrm : Format<16>; 44212904Sdimdef VFPConv1Frm : Format<17>; 45212904Sdimdef VFPConv2Frm : Format<18>; 46212904Sdimdef VFPConv3Frm : Format<19>; 47212904Sdimdef VFPConv4Frm : Format<20>; 48212904Sdimdef VFPConv5Frm : Format<21>; 49212904Sdimdef VFPLdStFrm : Format<22>; 50212904Sdimdef VFPLdStMulFrm : Format<23>; 51212904Sdimdef VFPMiscFrm : Format<24>; 52193323Sed 53212904Sdimdef ThumbFrm : Format<25>; 54212904Sdimdef MiscFrm : Format<26>; 55193323Sed 56212904Sdimdef NGetLnFrm : Format<27>; 57212904Sdimdef NSetLnFrm : Format<28>; 58212904Sdimdef NDupFrm : Format<29>; 59212904Sdimdef NLdStFrm : Format<30>; 60212904Sdimdef N1RegModImmFrm: Format<31>; 61212904Sdimdef N2RegFrm : Format<32>; 62212904Sdimdef NVCVTFrm : Format<33>; 63212904Sdimdef NVDupLnFrm : Format<34>; 64212904Sdimdef N2RegVShLFrm : Format<35>; 65212904Sdimdef N2RegVShRFrm : Format<36>; 66212904Sdimdef N3RegFrm : Format<37>; 67212904Sdimdef N3RegVShFrm : Format<38>; 68212904Sdimdef NVExtFrm : Format<39>; 69212904Sdimdef NVMulSLFrm : Format<40>; 70212904Sdimdef NVTBLFrm : Format<41>; 71226633Sdimdef DPSoRegImmFrm : Format<42>; 72194710Sed 73198090Srdivacky// Misc flags. 74198090Srdivacky 75218893Sdim// The instruction has an Rn register operand. 76198090Srdivacky// UnaryDP - Indicates this is a unary data processing instruction, i.e. 77198090Srdivacky// it doesn't have a Rn operand. 78198090Srdivackyclass UnaryDP { bit isUnaryDataProc = 1; } 79193323Sed 80198090Srdivacky// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 81198090Srdivacky// a 16-bit Thumb instruction if certain conditions are met. 82198090Srdivackyclass Xform16Bit { bit canXformTo16Bit = 1; } 83198090Srdivacky 84193323Sed//===----------------------------------------------------------------------===// 85205407Srdivacky// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 86195340Sed// 87193323Sed 88218893Sdim// FIXME: Once the JIT is MC-ized, these can go away. 89195340Sed// Addressing mode. 90218893Sdimclass AddrMode<bits<5> val> { 91218893Sdim bits<5> Value = val; 92195340Sed} 93212904Sdimdef AddrModeNone : AddrMode<0>; 94212904Sdimdef AddrMode1 : AddrMode<1>; 95212904Sdimdef AddrMode2 : AddrMode<2>; 96212904Sdimdef AddrMode3 : AddrMode<3>; 97212904Sdimdef AddrMode4 : AddrMode<4>; 98212904Sdimdef AddrMode5 : AddrMode<5>; 99212904Sdimdef AddrMode6 : AddrMode<6>; 100212904Sdimdef AddrModeT1_1 : AddrMode<7>; 101212904Sdimdef AddrModeT1_2 : AddrMode<8>; 102212904Sdimdef AddrModeT1_4 : AddrMode<9>; 103212904Sdimdef AddrModeT1_s : AddrMode<10>; 104212904Sdimdef AddrModeT2_i12 : AddrMode<11>; 105212904Sdimdef AddrModeT2_i8 : AddrMode<12>; 106212904Sdimdef AddrModeT2_so : AddrMode<13>; 107212904Sdimdef AddrModeT2_pc : AddrMode<14>; 108195340Seddef AddrModeT2_i8s4 : AddrMode<15>; 109218893Sdimdef AddrMode_i12 : AddrMode<16>; 110195340Sed 111195340Sed// Load / store index mode. 112195340Sedclass IndexMode<bits<2> val> { 113195340Sed bits<2> Value = val; 114195340Sed} 115195340Seddef IndexModeNone : IndexMode<0>; 116195340Seddef IndexModePre : IndexMode<1>; 117195340Seddef IndexModePost : IndexMode<2>; 118205218Srdivackydef IndexModeUpd : IndexMode<3>; 119195340Sed 120198892Srdivacky// Instruction execution domain. 121219077Sdimclass Domain<bits<3> val> { 122219077Sdim bits<3> Value = val; 123198892Srdivacky} 124198892Srdivackydef GenericDomain : Domain<0>; 125198892Srdivackydef VFPDomain : Domain<1>; // Instructions in VFP domain only 126198892Srdivackydef NeonDomain : Domain<2>; // Instructions in Neon domain only 127198892Srdivackydef VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 128219077Sdimdef VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 129198892Srdivacky 130195340Sed//===----------------------------------------------------------------------===// 131198090Srdivacky// ARM special operands. 132198090Srdivacky// 133198090Srdivacky 134226633Sdim// ARM imod and iflag operands, used only by the CPS instruction. 135226633Sdimdef imod_op : Operand<i32> { 136226633Sdim let PrintMethod = "printCPSIMod"; 137212904Sdim} 138212904Sdim 139218893Sdimdef ProcIFlagsOperand : AsmOperandClass { 140218893Sdim let Name = "ProcIFlags"; 141226633Sdim let ParserMethod = "parseProcIFlagsOperand"; 142218893Sdim} 143218893Sdimdef iflags_op : Operand<i32> { 144218893Sdim let PrintMethod = "printCPSIFlag"; 145218893Sdim let ParserMatchClass = ProcIFlagsOperand; 146218893Sdim} 147218893Sdim 148198090Srdivacky// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 149198090Srdivacky// register whose default is 0 (no register). 150226633Sdimdef CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } 151226633Sdimdef pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), 152198090Srdivacky (ops (i32 14), (i32 zero_reg))> { 153198090Srdivacky let PrintMethod = "printPredicateOperand"; 154212904Sdim let ParserMatchClass = CondCodeOperand; 155226633Sdim let DecoderMethod = "DecodePredicateOperand"; 156198090Srdivacky} 157198090Srdivacky 158198090Srdivacky// Conditional code result for instructions whose 's' bit is set, e.g. subs. 159226633Sdimdef CCOutOperand : AsmOperandClass { let Name = "CCOut"; } 160198090Srdivackydef cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 161218893Sdim let EncoderMethod = "getCCOutOpValue"; 162198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 163218893Sdim let ParserMatchClass = CCOutOperand; 164226633Sdim let DecoderMethod = "DecodeCCOutOperand"; 165198090Srdivacky} 166198090Srdivacky 167198090Srdivacky// Same as cc_out except it defaults to setting CPSR. 168198090Srdivackydef s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 169218893Sdim let EncoderMethod = "getCCOutOpValue"; 170198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 171218893Sdim let ParserMatchClass = CCOutOperand; 172226633Sdim let DecoderMethod = "DecodeCCOutOperand"; 173198090Srdivacky} 174198090Srdivacky 175205218Srdivacky// ARM special operands for disassembly only. 176205218Srdivacky// 177234353Sdimdef SetEndAsmOperand : ImmAsmOperand { 178226633Sdim let Name = "SetEndImm"; 179226633Sdim let ParserMethod = "parseSetEndImm"; 180226633Sdim} 181218893Sdimdef setend_op : Operand<i32> { 182218893Sdim let PrintMethod = "printSetendOperand"; 183226633Sdim let ParserMatchClass = SetEndAsmOperand; 184218893Sdim} 185205218Srdivacky 186226633Sdimdef MSRMaskOperand : AsmOperandClass { 187226633Sdim let Name = "MSRMask"; 188226633Sdim let ParserMethod = "parseMSRMaskOperand"; 189226633Sdim} 190205218Srdivackydef msr_mask : Operand<i32> { 191205218Srdivacky let PrintMethod = "printMSRMaskOperand"; 192226633Sdim let DecoderMethod = "DecodeMSRMask"; 193218893Sdim let ParserMatchClass = MSRMaskOperand; 194205218Srdivacky} 195205218Srdivacky 196221345Sdim// Shift Right Immediate - A shift right immediate is encoded differently from 197221345Sdim// other shift immediates. The imm6 field is encoded like so: 198221345Sdim// 199221345Sdim// Offset Encoding 200221345Sdim// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 201221345Sdim// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 202221345Sdim// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 203221345Sdim// 64 64 - <imm> is encoded in imm6<5:0> 204234353Sdimdef shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; } 205221345Sdimdef shr_imm8 : Operand<i32> { 206221345Sdim let EncoderMethod = "getShiftRight8Imm"; 207226633Sdim let DecoderMethod = "DecodeShiftRight8Imm"; 208234353Sdim let ParserMatchClass = shr_imm8_asm_operand; 209205218Srdivacky} 210234353Sdimdef shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; } 211221345Sdimdef shr_imm16 : Operand<i32> { 212221345Sdim let EncoderMethod = "getShiftRight16Imm"; 213226633Sdim let DecoderMethod = "DecodeShiftRight16Imm"; 214234353Sdim let ParserMatchClass = shr_imm16_asm_operand; 215221345Sdim} 216234353Sdimdef shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; } 217221345Sdimdef shr_imm32 : Operand<i32> { 218221345Sdim let EncoderMethod = "getShiftRight32Imm"; 219226633Sdim let DecoderMethod = "DecodeShiftRight32Imm"; 220234353Sdim let ParserMatchClass = shr_imm32_asm_operand; 221221345Sdim} 222234353Sdimdef shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; } 223221345Sdimdef shr_imm64 : Operand<i32> { 224221345Sdim let EncoderMethod = "getShiftRight64Imm"; 225226633Sdim let DecoderMethod = "DecodeShiftRight64Imm"; 226234353Sdim let ParserMatchClass = shr_imm64_asm_operand; 227221345Sdim} 228205218Srdivacky 229198090Srdivacky//===----------------------------------------------------------------------===// 230226633Sdim// ARM Assembler alias templates. 231226633Sdim// 232226633Sdimclass ARMInstAlias<string Asm, dag Result, bit Emit = 0b1> 233226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>; 234226633Sdimclass tInstAlias<string Asm, dag Result, bit Emit = 0b1> 235226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>; 236226633Sdimclass t2InstAlias<string Asm, dag Result, bit Emit = 0b1> 237226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>; 238226633Sdimclass VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1> 239226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>; 240226633Sdimclass VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1> 241226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>; 242234353Sdimclass NEONInstAlias<string Asm, dag Result, bit Emit = 0b1> 243234353Sdim : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>; 244226633Sdim 245234353Sdim 246234353Sdimclass VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, 247234353Sdim Requires<[HasVFP2]>; 248234353Sdimclass NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, 249234353Sdim Requires<[HasNEON]>; 250234353Sdim 251226633Sdim//===----------------------------------------------------------------------===// 252193323Sed// ARM Instruction templates. 253193323Sed// 254193323Sed 255226633Sdim 256224145Sdimclass InstTemplate<AddrMode am, int sz, IndexMode im, 257201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 258193323Sed : Instruction { 259193323Sed let Namespace = "ARM"; 260193323Sed 261193323Sed AddrMode AM = am; 262224145Sdim int Size = sz; 263193323Sed IndexMode IM = im; 264193323Sed bits<2> IndexModeBits = IM.Value; 265193323Sed Format F = f; 266205407Srdivacky bits<6> Form = F.Value; 267198892Srdivacky Domain D = d; 268193323Sed bit isUnaryDataProc = 0; 269198090Srdivacky bit canXformTo16Bit = 0; 270226633Sdim // The instruction is a 16-bit flag setting Thumb instruction. Used 271226633Sdim // by the parser to determine whether to require the 'S' suffix on the 272226633Sdim // mnemonic (when not in an IT block) or preclude it (when in an IT block). 273226633Sdim bit thumbArithFlagSetting = 0; 274206083Srdivacky 275218893Sdim // If this is a pseudo instruction, mark it isCodeGenOnly. 276218893Sdim let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 277218893Sdim 278226633Sdim // The layout of TSFlags should be kept in sync with ARMBaseInfo.h. 279218893Sdim let TSFlags{4-0} = AM.Value; 280224145Sdim let TSFlags{6-5} = IndexModeBits; 281224145Sdim let TSFlags{12-7} = Form; 282224145Sdim let TSFlags{13} = isUnaryDataProc; 283224145Sdim let TSFlags{14} = canXformTo16Bit; 284224145Sdim let TSFlags{17-15} = D.Value; 285226633Sdim let TSFlags{18} = thumbArithFlagSetting; 286206274Srdivacky 287193323Sed let Constraints = cstr; 288198090Srdivacky let Itinerary = itin; 289193323Sed} 290193323Sed 291201360Srdivackyclass Encoding { 292201360Srdivacky field bits<32> Inst; 293234353Sdim // Mask of bits that cause an encoding to be UNPREDICTABLE. 294234353Sdim // If a bit is set, then if the corresponding bit in the 295234353Sdim // target encoding differs from its value in the "Inst" field, 296234353Sdim // the instruction is UNPREDICTABLE (SoftFail in abstract parlance). 297234353Sdim field bits<32> Unpredictable = 0; 298234353Sdim // SoftFail is the generic name for this field, but we alias it so 299234353Sdim // as to make it more obvious what it means in ARM-land. 300234353Sdim field bits<32> SoftFail = Unpredictable; 301201360Srdivacky} 302201360Srdivacky 303224145Sdimclass InstARM<AddrMode am, int sz, IndexMode im, 304201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 305226633Sdim : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding { 306226633Sdim let DecoderNamespace = "ARM"; 307226633Sdim} 308201360Srdivacky 309201360Srdivacky// This Encoding-less class is used by Thumb1 to specify the encoding bits later 310201360Srdivacky// on by adding flavors to specific instructions. 311224145Sdimclass InstThumb<AddrMode am, int sz, IndexMode im, 312201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 313226633Sdim : InstTemplate<am, sz, im, f, d, cstr, itin> { 314226633Sdim let DecoderNamespace = "Thumb"; 315226633Sdim} 316201360Srdivacky 317234353Sdim// Pseudo-instructions for alternate assembly syntax (never used by codegen). 318234353Sdim// These are aliases that require C++ handling to convert to the target 319234353Sdim// instruction, while InstAliases can be handled directly by tblgen. 320234353Sdimclass AsmPseudoInst<string asm, dag iops> 321234353Sdim : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 322234353Sdim "", NoItinerary> { 323234353Sdim let OutOperandList = (outs); 324234353Sdim let InOperandList = iops; 325234353Sdim let Pattern = []; 326234353Sdim let isCodeGenOnly = 0; // So we get asm matcher for it. 327234353Sdim let AsmString = asm; 328234353Sdim let isPseudo = 1; 329234353Sdim} 330234353Sdim 331234353Sdimclass ARMAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 332234353Sdim Requires<[IsARM]>; 333234353Sdimclass tAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 334234353Sdim Requires<[IsThumb]>; 335234353Sdimclass t2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 336234353Sdim Requires<[IsThumb2]>; 337234353Sdimclass VFP2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 338234353Sdim Requires<[HasVFP2]>; 339234353Sdimclass NEONAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 340234353Sdim Requires<[HasNEON]>; 341234353Sdim 342234353Sdim// Pseudo instructions for the code generator. 343218893Sdimclass PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 344224145Sdim : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, 345224145Sdim GenericDomain, "", itin> { 346193323Sed let OutOperandList = oops; 347193323Sed let InOperandList = iops; 348193323Sed let Pattern = pattern; 349221345Sdim let isCodeGenOnly = 1; 350224145Sdim let isPseudo = 1; 351193323Sed} 352193323Sed 353218893Sdim// PseudoInst that's ARM-mode only. 354224145Sdimclass ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 355218893Sdim list<dag> pattern> 356218893Sdim : PseudoInst<oops, iops, itin, pattern> { 357224145Sdim let Size = sz; 358218893Sdim list<Predicate> Predicates = [IsARM]; 359218893Sdim} 360218893Sdim 361218893Sdim// PseudoInst that's Thumb-mode only. 362224145Sdimclass tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 363218893Sdim list<dag> pattern> 364218893Sdim : PseudoInst<oops, iops, itin, pattern> { 365224145Sdim let Size = sz; 366218893Sdim list<Predicate> Predicates = [IsThumb]; 367218893Sdim} 368218893Sdim 369218893Sdim// PseudoInst that's Thumb2-mode only. 370224145Sdimclass t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 371218893Sdim list<dag> pattern> 372218893Sdim : PseudoInst<oops, iops, itin, pattern> { 373224145Sdim let Size = sz; 374218893Sdim list<Predicate> Predicates = [IsThumb2]; 375218893Sdim} 376224145Sdim 377224145Sdimclass ARMPseudoExpand<dag oops, dag iops, int sz, 378224145Sdim InstrItinClass itin, list<dag> pattern, 379224145Sdim dag Result> 380224145Sdim : ARMPseudoInst<oops, iops, sz, itin, pattern>, 381224145Sdim PseudoInstExpansion<Result>; 382224145Sdim 383224145Sdimclass tPseudoExpand<dag oops, dag iops, int sz, 384224145Sdim InstrItinClass itin, list<dag> pattern, 385224145Sdim dag Result> 386224145Sdim : tPseudoInst<oops, iops, sz, itin, pattern>, 387224145Sdim PseudoInstExpansion<Result>; 388224145Sdim 389224145Sdimclass t2PseudoExpand<dag oops, dag iops, int sz, 390224145Sdim InstrItinClass itin, list<dag> pattern, 391224145Sdim dag Result> 392224145Sdim : t2PseudoInst<oops, iops, sz, itin, pattern>, 393224145Sdim PseudoInstExpansion<Result>; 394224145Sdim 395193323Sed// Almost all ARM instructions are predicable. 396224145Sdimclass I<dag oops, dag iops, AddrMode am, int sz, 397206083Srdivacky IndexMode im, Format f, InstrItinClass itin, 398198090Srdivacky string opc, string asm, string cstr, 399193323Sed list<dag> pattern> 400198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 401218893Sdim bits<4> p; 402218893Sdim let Inst{31-28} = p; 403193323Sed let OutOperandList = oops; 404205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 405218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 406193323Sed let Pattern = pattern; 407193323Sed list<Predicate> Predicates = [IsARM]; 408193323Sed} 409212904Sdim 410200581Srdivacky// A few are not predicable 411224145Sdimclass InoP<dag oops, dag iops, AddrMode am, int sz, 412206083Srdivacky IndexMode im, Format f, InstrItinClass itin, 413206083Srdivacky string opc, string asm, string cstr, 414206083Srdivacky list<dag> pattern> 415200581Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 416200581Srdivacky let OutOperandList = oops; 417200581Srdivacky let InOperandList = iops; 418208599Srdivacky let AsmString = !strconcat(opc, asm); 419200581Srdivacky let Pattern = pattern; 420200581Srdivacky let isPredicable = 0; 421200581Srdivacky list<Predicate> Predicates = [IsARM]; 422200581Srdivacky} 423193323Sed 424212904Sdim// Same as I except it can optionally modify CPSR. Note it's modeled as an input 425212904Sdim// operand since by default it's a zero register. It will become an implicit def 426212904Sdim// once it's "flipped". 427224145Sdimclass sI<dag oops, dag iops, AddrMode am, int sz, 428198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 429198090Srdivacky string opc, string asm, string cstr, 430193323Sed list<dag> pattern> 431198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 432218893Sdim bits<4> p; // Predicate operand 433218893Sdim bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 434218893Sdim let Inst{31-28} = p; 435218893Sdim let Inst{20} = s; 436218893Sdim 437193323Sed let OutOperandList = oops; 438205407Srdivacky let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 439218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 440193323Sed let Pattern = pattern; 441193323Sed list<Predicate> Predicates = [IsARM]; 442193323Sed} 443193323Sed 444193323Sed// Special cases 445224145Sdimclass XI<dag oops, dag iops, AddrMode am, int sz, 446198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 447198090Srdivacky string asm, string cstr, list<dag> pattern> 448198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 449193323Sed let OutOperandList = oops; 450193323Sed let InOperandList = iops; 451208599Srdivacky let AsmString = asm; 452193323Sed let Pattern = pattern; 453193323Sed list<Predicate> Predicates = [IsARM]; 454193323Sed} 455193323Sed 456198090Srdivackyclass AI<dag oops, dag iops, Format f, InstrItinClass itin, 457198090Srdivacky string opc, string asm, list<dag> pattern> 458224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 459198090Srdivacky opc, asm, "", pattern>; 460198090Srdivackyclass AsI<dag oops, dag iops, Format f, InstrItinClass itin, 461198090Srdivacky string opc, string asm, list<dag> pattern> 462224145Sdim : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 463198090Srdivacky opc, asm, "", pattern>; 464198090Srdivackyclass AXI<dag oops, dag iops, Format f, InstrItinClass itin, 465193323Sed string asm, list<dag> pattern> 466224145Sdim : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 467193323Sed asm, "", pattern>; 468200581Srdivackyclass AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 469206083Srdivacky string opc, string asm, list<dag> pattern> 470224145Sdim : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 471206083Srdivacky opc, asm, "", pattern>; 472193323Sed 473193323Sed// Ctrl flow instructions 474198090Srdivackyclass ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 475198090Srdivacky string opc, string asm, list<dag> pattern> 476224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 477198090Srdivacky opc, asm, "", pattern> { 478193323Sed let Inst{27-24} = opcod; 479193323Sed} 480198090Srdivackyclass ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 481198090Srdivacky string asm, list<dag> pattern> 482224145Sdim : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 483198090Srdivacky asm, "", pattern> { 484193323Sed let Inst{27-24} = opcod; 485193323Sed} 486193323Sed 487193323Sed// BR_JT instructions 488198090Srdivackyclass JTI<dag oops, dag iops, InstrItinClass itin, 489198090Srdivacky string asm, list<dag> pattern> 490224145Sdim : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin, 491193323Sed asm, "", pattern>; 492193323Sed 493200581Srdivacky// Atomic load/store instructions 494200581Srdivackyclass AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 495200581Srdivacky string opc, string asm, list<dag> pattern> 496224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 497200581Srdivacky opc, asm, "", pattern> { 498218893Sdim bits<4> Rt; 499226633Sdim bits<4> addr; 500200581Srdivacky let Inst{27-23} = 0b00011; 501200581Srdivacky let Inst{22-21} = opcod; 502212904Sdim let Inst{20} = 1; 503226633Sdim let Inst{19-16} = addr; 504218893Sdim let Inst{15-12} = Rt; 505200581Srdivacky let Inst{11-0} = 0b111110011111; 506200581Srdivacky} 507200581Srdivackyclass AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 508200581Srdivacky string opc, string asm, list<dag> pattern> 509224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 510200581Srdivacky opc, asm, "", pattern> { 511218893Sdim bits<4> Rd; 512218893Sdim bits<4> Rt; 513221345Sdim bits<4> addr; 514200581Srdivacky let Inst{27-23} = 0b00011; 515200581Srdivacky let Inst{22-21} = opcod; 516212904Sdim let Inst{20} = 0; 517221345Sdim let Inst{19-16} = addr; 518218893Sdim let Inst{15-12} = Rd; 519200581Srdivacky let Inst{11-4} = 0b11111001; 520218893Sdim let Inst{3-0} = Rt; 521200581Srdivacky} 522218893Sdimclass AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 523226633Sdim : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> { 524218893Sdim bits<4> Rt; 525218893Sdim bits<4> Rt2; 526226633Sdim bits<4> addr; 527218893Sdim let Inst{27-23} = 0b00010; 528218893Sdim let Inst{22} = b; 529218893Sdim let Inst{21-20} = 0b00; 530226633Sdim let Inst{19-16} = addr; 531218893Sdim let Inst{15-12} = Rt; 532218893Sdim let Inst{11-4} = 0b00001001; 533218893Sdim let Inst{3-0} = Rt2; 534234353Sdim 535234982Sdim let Unpredictable{11-8} = 0b1111; 536234353Sdim let DecoderMethod = "DecodeSwap"; 537218893Sdim} 538200581Srdivacky 539193323Sed// addrmode1 instructions 540198090Srdivackyclass AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 541198090Srdivacky string opc, string asm, list<dag> pattern> 542224145Sdim : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 543198090Srdivacky opc, asm, "", pattern> { 544193323Sed let Inst{24-21} = opcod; 545212904Sdim let Inst{27-26} = 0b00; 546193323Sed} 547198090Srdivackyclass AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 548198090Srdivacky string opc, string asm, list<dag> pattern> 549224145Sdim : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 550198090Srdivacky opc, asm, "", pattern> { 551193323Sed let Inst{24-21} = opcod; 552212904Sdim let Inst{27-26} = 0b00; 553193323Sed} 554198090Srdivackyclass AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 555198090Srdivacky string asm, list<dag> pattern> 556224145Sdim : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 557198090Srdivacky asm, "", pattern> { 558193323Sed let Inst{24-21} = opcod; 559212904Sdim let Inst{27-26} = 0b00; 560193323Sed} 561193323Sed 562193323Sed// loads 563193323Sed 564218893Sdim// LDR/LDRB/STR/STRB/... 565218893Sdimclass AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 566218893Sdim Format f, InstrItinClass itin, string opc, string asm, 567218893Sdim list<dag> pattern> 568224145Sdim : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm, 569218893Sdim "", pattern> { 570218893Sdim let Inst{27-25} = op; 571218893Sdim let Inst{24} = 1; // 24 == P 572218893Sdim // 23 == U 573218893Sdim let Inst{22} = isByte; 574218893Sdim let Inst{21} = 0; // 21 == W 575218893Sdim let Inst{20} = isLd; 576193323Sed} 577218893Sdim// Indexed load/stores 578218893Sdimclass AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 579218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 580218893Sdim string asm, string cstr, list<dag> pattern> 581224145Sdim : I<oops, iops, AddrMode2, 4, im, f, itin, 582198090Srdivacky opc, asm, cstr, pattern> { 583218893Sdim bits<4> Rt; 584212904Sdim let Inst{27-26} = 0b01; 585218893Sdim let Inst{24} = isPre; // P bit 586218893Sdim let Inst{22} = isByte; // B bit 587218893Sdim let Inst{21} = isPre; // W bit 588218893Sdim let Inst{20} = isLd; // L bit 589218893Sdim let Inst{15-12} = Rt; 590193323Sed} 591226633Sdimclass AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops, 592218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 593218893Sdim string asm, string cstr, list<dag> pattern> 594218893Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 595218893Sdim pattern> { 596218893Sdim // AM2 store w/ two operands: (GPR, am2offset) 597218893Sdim // {12} isAdd 598218893Sdim // {11-0} imm12/Rm 599218893Sdim bits<14> offset; 600218893Sdim bits<4> Rn; 601226633Sdim let Inst{25} = 1; 602218893Sdim let Inst{23} = offset{12}; 603218893Sdim let Inst{19-16} = Rn; 604226633Sdim let Inst{11-5} = offset{11-5}; 605226633Sdim let Inst{4} = 0; 606226633Sdim let Inst{3-0} = offset{3-0}; 607226633Sdim} 608226633Sdim 609226633Sdimclass AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops, 610226633Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 611226633Sdim string asm, string cstr, list<dag> pattern> 612226633Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 613226633Sdim pattern> { 614226633Sdim // AM2 store w/ two operands: (GPR, am2offset) 615226633Sdim // {12} isAdd 616226633Sdim // {11-0} imm12/Rm 617226633Sdim bits<14> offset; 618226633Sdim bits<4> Rn; 619226633Sdim let Inst{25} = 0; 620226633Sdim let Inst{23} = offset{12}; 621226633Sdim let Inst{19-16} = Rn; 622218893Sdim let Inst{11-0} = offset{11-0}; 623193323Sed} 624226633Sdim 625226633Sdim 626221345Sdim// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB 627221345Sdim// but for now use this class for STRT and STRBT. 628221345Sdimclass AI2stridxT<bit isByte, bit isPre, dag oops, dag iops, 629221345Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 630221345Sdim string asm, string cstr, list<dag> pattern> 631221345Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 632221345Sdim pattern> { 633221345Sdim // AM2 store w/ two operands: (GPR, am2offset) 634221345Sdim // {17-14} Rn 635221345Sdim // {13} 1 == Rm, 0 == imm12 636221345Sdim // {12} isAdd 637221345Sdim // {11-0} imm12/Rm 638221345Sdim bits<18> addr; 639221345Sdim let Inst{25} = addr{13}; 640221345Sdim let Inst{23} = addr{12}; 641221345Sdim let Inst{19-16} = addr{17-14}; 642221345Sdim let Inst{11-0} = addr{11-0}; 643221345Sdim} 644193323Sed 645193323Sed// addrmode3 instructions 646218893Sdimclass AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 647218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 648224145Sdim : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 649198090Srdivacky opc, asm, "", pattern> { 650218893Sdim bits<14> addr; 651218893Sdim bits<4> Rt; 652198090Srdivacky let Inst{27-25} = 0b000; 653218893Sdim let Inst{24} = 1; // P bit 654218893Sdim let Inst{23} = addr{8}; // U bit 655218893Sdim let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 656218893Sdim let Inst{21} = 0; // W bit 657218893Sdim let Inst{20} = op20; // L bit 658218893Sdim let Inst{19-16} = addr{12-9}; // Rn 659218893Sdim let Inst{15-12} = Rt; // Rt 660218893Sdim let Inst{11-8} = addr{7-4}; // imm7_4/zero 661218893Sdim let Inst{7-4} = op; 662218893Sdim let Inst{3-0} = addr{3-0}; // imm3_0/Rm 663226633Sdim 664226633Sdim let DecoderMethod = "DecodeAddrMode3Instruction"; 665193323Sed} 666218893Sdim 667226633Sdimclass AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops, 668218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 669218893Sdim string asm, string cstr, list<dag> pattern> 670224145Sdim : I<oops, iops, AddrMode3, 4, im, f, itin, 671218893Sdim opc, asm, cstr, pattern> { 672218893Sdim bits<4> Rt; 673198090Srdivacky let Inst{27-25} = 0b000; 674218893Sdim let Inst{24} = isPre; // P bit 675218893Sdim let Inst{21} = isPre; // W bit 676218893Sdim let Inst{20} = op20; // L bit 677218893Sdim let Inst{15-12} = Rt; // Rt 678218893Sdim let Inst{7-4} = op; 679193323Sed} 680221345Sdim 681221345Sdim// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB 682221345Sdim// but for now use this class for LDRSBT, LDRHT, LDSHT. 683226633Sdimclass AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops, 684221345Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 685221345Sdim string asm, string cstr, list<dag> pattern> 686226633Sdim : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> { 687221345Sdim // {13} 1 == imm8, 0 == Rm 688221345Sdim // {12-9} Rn 689221345Sdim // {8} isAdd 690221345Sdim // {7-4} imm7_4/zero 691221345Sdim // {3-0} imm3_0/Rm 692226633Sdim bits<4> addr; 693221345Sdim bits<4> Rt; 694221345Sdim let Inst{27-25} = 0b000; 695226633Sdim let Inst{24} = 0; // P bit 696226633Sdim let Inst{21} = 1; 697226633Sdim let Inst{20} = isLoad; // L bit 698226633Sdim let Inst{19-16} = addr; // Rn 699221345Sdim let Inst{15-12} = Rt; // Rt 700221345Sdim let Inst{7-4} = op; 701221345Sdim} 702221345Sdim 703193323Sed// stores 704218893Sdimclass AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 705198090Srdivacky string opc, string asm, list<dag> pattern> 706224145Sdim : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 707198090Srdivacky opc, asm, "", pattern> { 708218893Sdim bits<14> addr; 709218893Sdim bits<4> Rt; 710198090Srdivacky let Inst{27-25} = 0b000; 711218893Sdim let Inst{24} = 1; // P bit 712218893Sdim let Inst{23} = addr{8}; // U bit 713218893Sdim let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 714218893Sdim let Inst{21} = 0; // W bit 715218893Sdim let Inst{20} = 0; // L bit 716218893Sdim let Inst{19-16} = addr{12-9}; // Rn 717218893Sdim let Inst{15-12} = Rt; // Rt 718218893Sdim let Inst{11-8} = addr{7-4}; // imm7_4/zero 719218893Sdim let Inst{7-4} = op; 720218893Sdim let Inst{3-0} = addr{3-0}; // imm3_0/Rm 721226633Sdim let DecoderMethod = "DecodeAddrMode3Instruction"; 722193323Sed} 723193323Sed 724193323Sed// addrmode4 instructions 725218893Sdimclass AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 726218893Sdim string asm, string cstr, list<dag> pattern> 727224145Sdim : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> { 728218893Sdim bits<4> p; 729218893Sdim bits<16> regs; 730218893Sdim bits<4> Rn; 731218893Sdim let Inst{31-28} = p; 732193323Sed let Inst{27-25} = 0b100; 733193323Sed let Inst{22} = 0; // S bit 734218893Sdim let Inst{19-16} = Rn; 735218893Sdim let Inst{15-0} = regs; 736193323Sed} 737193323Sed 738193323Sed// Unsigned multiply, multiply-accumulate instructions. 739198090Srdivackyclass AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 740198090Srdivacky string opc, string asm, list<dag> pattern> 741224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 742198090Srdivacky opc, asm, "", pattern> { 743193323Sed let Inst{7-4} = 0b1001; 744193323Sed let Inst{20} = 0; // S bit 745193323Sed let Inst{27-21} = opcod; 746193323Sed} 747198090Srdivackyclass AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 748198090Srdivacky string opc, string asm, list<dag> pattern> 749224145Sdim : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 750198090Srdivacky opc, asm, "", pattern> { 751193323Sed let Inst{7-4} = 0b1001; 752193323Sed let Inst{27-21} = opcod; 753193323Sed} 754193323Sed 755193323Sed// Most significant word multiply 756218893Sdimclass AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 757218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 758224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 759198090Srdivacky opc, asm, "", pattern> { 760218893Sdim bits<4> Rd; 761218893Sdim bits<4> Rn; 762218893Sdim bits<4> Rm; 763218893Sdim let Inst{7-4} = opc7_4; 764193323Sed let Inst{20} = 1; 765193323Sed let Inst{27-21} = opcod; 766218893Sdim let Inst{19-16} = Rd; 767218893Sdim let Inst{11-8} = Rm; 768218893Sdim let Inst{3-0} = Rn; 769193323Sed} 770218893Sdim// MSW multiple w/ Ra operand 771218893Sdimclass AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 772218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 773218893Sdim : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 774218893Sdim bits<4> Ra; 775218893Sdim let Inst{15-12} = Ra; 776218893Sdim} 777193323Sed 778193323Sed// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 779218893Sdimclass AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 780218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 781224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 782198090Srdivacky opc, asm, "", pattern> { 783218893Sdim bits<4> Rn; 784218893Sdim bits<4> Rm; 785193323Sed let Inst{4} = 0; 786193323Sed let Inst{7} = 1; 787193323Sed let Inst{20} = 0; 788193323Sed let Inst{27-21} = opcod; 789218893Sdim let Inst{6-5} = bit6_5; 790218893Sdim let Inst{11-8} = Rm; 791218893Sdim let Inst{3-0} = Rn; 792193323Sed} 793218893Sdimclass AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 794218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 795218893Sdim : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 796218893Sdim bits<4> Rd; 797218893Sdim let Inst{19-16} = Rd; 798218893Sdim} 799193323Sed 800218893Sdim// AMulxyI with Ra operand 801218893Sdimclass AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 802218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 803218893Sdim : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 804218893Sdim bits<4> Ra; 805218893Sdim let Inst{15-12} = Ra; 806218893Sdim} 807218893Sdim// SMLAL* 808218893Sdimclass AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 809218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 810218893Sdim : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 811218893Sdim bits<4> RdLo; 812218893Sdim bits<4> RdHi; 813218893Sdim let Inst{19-16} = RdHi; 814218893Sdim let Inst{15-12} = RdLo; 815218893Sdim} 816218893Sdim 817193323Sed// Extend instructions. 818198090Srdivackyclass AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 819198090Srdivacky string opc, string asm, list<dag> pattern> 820224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin, 821198090Srdivacky opc, asm, "", pattern> { 822218893Sdim // All AExtI instructions have Rd and Rm register operands. 823218893Sdim bits<4> Rd; 824218893Sdim bits<4> Rm; 825218893Sdim let Inst{15-12} = Rd; 826218893Sdim let Inst{3-0} = Rm; 827193323Sed let Inst{7-4} = 0b0111; 828218893Sdim let Inst{9-8} = 0b00; 829193323Sed let Inst{27-20} = opcod; 830193323Sed} 831193323Sed 832193323Sed// Misc Arithmetic instructions. 833218893Sdimclass AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 834218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 835224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 836198090Srdivacky opc, asm, "", pattern> { 837218893Sdim bits<4> Rd; 838218893Sdim bits<4> Rm; 839193323Sed let Inst{27-20} = opcod; 840218893Sdim let Inst{19-16} = 0b1111; 841218893Sdim let Inst{15-12} = Rd; 842218893Sdim let Inst{11-8} = 0b1111; 843218893Sdim let Inst{7-4} = opc7_4; 844218893Sdim let Inst{3-0} = Rm; 845193323Sed} 846193323Sed 847218893Sdim// PKH instructions 848234353Sdimdef PKHLSLAsmOperand : ImmAsmOperand { 849226633Sdim let Name = "PKHLSLImm"; 850226633Sdim let ParserMethod = "parsePKHLSLImm"; 851226633Sdim} 852226633Sdimdef pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{ 853226633Sdim let PrintMethod = "printPKHLSLShiftImm"; 854226633Sdim let ParserMatchClass = PKHLSLAsmOperand; 855226633Sdim} 856226633Sdimdef PKHASRAsmOperand : AsmOperandClass { 857226633Sdim let Name = "PKHASRImm"; 858226633Sdim let ParserMethod = "parsePKHASRImm"; 859226633Sdim} 860226633Sdimdef pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{ 861226633Sdim let PrintMethod = "printPKHASRShiftImm"; 862226633Sdim let ParserMatchClass = PKHASRAsmOperand; 863226633Sdim} 864226633Sdim 865218893Sdimclass APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 866218893Sdim string opc, string asm, list<dag> pattern> 867224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 868218893Sdim opc, asm, "", pattern> { 869218893Sdim bits<4> Rd; 870218893Sdim bits<4> Rn; 871218893Sdim bits<4> Rm; 872226633Sdim bits<5> sh; 873218893Sdim let Inst{27-20} = opcod; 874218893Sdim let Inst{19-16} = Rn; 875218893Sdim let Inst{15-12} = Rd; 876226633Sdim let Inst{11-7} = sh; 877218893Sdim let Inst{6} = tb; 878218893Sdim let Inst{5-4} = 0b01; 879218893Sdim let Inst{3-0} = Rm; 880218893Sdim} 881218893Sdim 882193323Sed//===----------------------------------------------------------------------===// 883193323Sed 884193323Sed// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 885193323Sedclass ARMPat<dag pattern, dag result> : Pat<pattern, result> { 886193323Sed list<Predicate> Predicates = [IsARM]; 887193323Sed} 888223017Sdimclass ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> { 889223017Sdim list<Predicate> Predicates = [IsARM, HasV5T]; 890223017Sdim} 891193323Sedclass ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 892193323Sed list<Predicate> Predicates = [IsARM, HasV5TE]; 893193323Sed} 894193323Sedclass ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 895193323Sed list<Predicate> Predicates = [IsARM, HasV6]; 896193323Sed} 897193323Sed 898193323Sed//===----------------------------------------------------------------------===// 899193323Sed// Thumb Instruction Format Definitions. 900193323Sed// 901193323Sed 902224145Sdimclass ThumbI<dag oops, dag iops, AddrMode am, int sz, 903198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 904201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 905198090Srdivacky let OutOperandList = oops; 906198090Srdivacky let InOperandList = iops; 907208599Srdivacky let AsmString = asm; 908193323Sed let Pattern = pattern; 909193323Sed list<Predicate> Predicates = [IsThumb]; 910193323Sed} 911193323Sed 912218893Sdim// TI - Thumb instruction. 913198090Srdivackyclass TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 914224145Sdim : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 915193323Sed 916198090Srdivacky// Two-address instructions 917206083Srdivackyclass TIt<dag oops, dag iops, InstrItinClass itin, string asm, 918206083Srdivacky list<dag> pattern> 919224145Sdim : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst", 920206083Srdivacky pattern>; 921193323Sed 922201360Srdivacky// tBL, tBX 32-bit instructions 923201360Srdivackyclass TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 924206083Srdivacky dag oops, dag iops, InstrItinClass itin, string asm, 925206083Srdivacky list<dag> pattern> 926224145Sdim : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>, 927206083Srdivacky Encoding { 928201360Srdivacky let Inst{31-27} = opcod1; 929201360Srdivacky let Inst{15-14} = opcod2; 930212904Sdim let Inst{12} = opcod3; 931201360Srdivacky} 932198090Srdivacky 933193323Sed// BR_JT instructions 934206083Srdivackyclass TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 935206083Srdivacky list<dag> pattern> 936224145Sdim : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 937193323Sed 938198090Srdivacky// Thumb1 only 939224145Sdimclass Thumb1I<dag oops, dag iops, AddrMode am, int sz, 940198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 941201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 942198090Srdivacky let OutOperandList = oops; 943198090Srdivacky let InOperandList = iops; 944208599Srdivacky let AsmString = asm; 945198090Srdivacky let Pattern = pattern; 946218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 947194710Sed} 948193323Sed 949198090Srdivackyclass T1I<dag oops, dag iops, InstrItinClass itin, 950198090Srdivacky string asm, list<dag> pattern> 951224145Sdim : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 952198090Srdivackyclass T1Ix2<dag oops, dag iops, InstrItinClass itin, 953198090Srdivacky string asm, list<dag> pattern> 954224145Sdim : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 955194710Sed 956198090Srdivacky// Two-address instructions 957198090Srdivackyclass T1It<dag oops, dag iops, InstrItinClass itin, 958205218Srdivacky string asm, string cstr, list<dag> pattern> 959224145Sdim : Thumb1I<oops, iops, AddrModeNone, 2, itin, 960205218Srdivacky asm, cstr, pattern>; 961198090Srdivacky 962198090Srdivacky// Thumb1 instruction that can either be predicated or set CPSR. 963224145Sdimclass Thumb1sI<dag oops, dag iops, AddrMode am, int sz, 964198090Srdivacky InstrItinClass itin, 965198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 966201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 967205407Srdivacky let OutOperandList = !con(oops, (outs s_cc_out:$s)); 968205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 969218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 970194754Sed let Pattern = pattern; 971226633Sdim let thumbArithFlagSetting = 1; 972218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 973226633Sdim let DecoderNamespace = "ThumbSBit"; 974195098Sed} 975195098Sed 976198090Srdivackyclass T1sI<dag oops, dag iops, InstrItinClass itin, 977198090Srdivacky string opc, string asm, list<dag> pattern> 978224145Sdim : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 979195098Sed 980195098Sed// Two-address instructions 981198090Srdivackyclass T1sIt<dag oops, dag iops, InstrItinClass itin, 982198090Srdivacky string opc, string asm, list<dag> pattern> 983224145Sdim : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, 984218893Sdim "$Rn = $Rdn", pattern>; 985195098Sed 986198090Srdivacky// Thumb1 instruction that can be predicated. 987224145Sdimclass Thumb1pI<dag oops, dag iops, AddrMode am, int sz, 988198090Srdivacky InstrItinClass itin, 989198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 990201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 991198090Srdivacky let OutOperandList = oops; 992205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 993218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 994198090Srdivacky let Pattern = pattern; 995218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 996195098Sed} 997195098Sed 998198090Srdivackyclass T1pI<dag oops, dag iops, InstrItinClass itin, 999198090Srdivacky string opc, string asm, list<dag> pattern> 1000224145Sdim : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 1001198090Srdivacky 1002198090Srdivacky// Two-address instructions 1003198090Srdivackyclass T1pIt<dag oops, dag iops, InstrItinClass itin, 1004198090Srdivacky string opc, string asm, list<dag> pattern> 1005224145Sdim : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, 1006218893Sdim "$Rn = $Rdn", pattern>; 1007198090Srdivacky 1008206083Srdivackyclass T1pIs<dag oops, dag iops, 1009198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1010224145Sdim : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>; 1011198090Srdivacky 1012201360Srdivackyclass Encoding16 : Encoding { 1013201360Srdivacky let Inst{31-16} = 0x0000; 1014201360Srdivacky} 1015201360Srdivacky 1016201360Srdivacky// A6.2 16-bit Thumb instruction encoding 1017201360Srdivackyclass T1Encoding<bits<6> opcode> : Encoding16 { 1018201360Srdivacky let Inst{15-10} = opcode; 1019201360Srdivacky} 1020201360Srdivacky 1021201360Srdivacky// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1022201360Srdivackyclass T1General<bits<5> opcode> : Encoding16 { 1023201360Srdivacky let Inst{15-14} = 0b00; 1024201360Srdivacky let Inst{13-9} = opcode; 1025201360Srdivacky} 1026201360Srdivacky 1027201360Srdivacky// A6.2.2 Data-processing encoding. 1028201360Srdivackyclass T1DataProcessing<bits<4> opcode> : Encoding16 { 1029201360Srdivacky let Inst{15-10} = 0b010000; 1030201360Srdivacky let Inst{9-6} = opcode; 1031201360Srdivacky} 1032201360Srdivacky 1033201360Srdivacky// A6.2.3 Special data instructions and branch and exchange encoding. 1034201360Srdivackyclass T1Special<bits<4> opcode> : Encoding16 { 1035201360Srdivacky let Inst{15-10} = 0b010001; 1036218893Sdim let Inst{9-6} = opcode; 1037201360Srdivacky} 1038201360Srdivacky 1039201360Srdivacky// A6.2.4 Load/store single data item encoding. 1040201360Srdivackyclass T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1041201360Srdivacky let Inst{15-12} = opA; 1042212904Sdim let Inst{11-9} = opB; 1043201360Srdivacky} 1044212904Sdimclass T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1045201360Srdivacky 1046223017Sdimclass T1BranchCond<bits<4> opcode> : Encoding16 { 1047223017Sdim let Inst{15-12} = opcode; 1048223017Sdim} 1049223017Sdim 1050218893Sdim// Helper classes to encode Thumb1 loads and stores. For immediates, the 1051218893Sdim// following bits are used for "opA" (see A6.2.4): 1052218893Sdim// 1053218893Sdim// 0b0110 => Immediate, 4 bytes 1054218893Sdim// 0b1000 => Immediate, 2 bytes 1055218893Sdim// 0b0111 => Immediate, 1 byte 1056218893Sdimclass T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 1057218893Sdim InstrItinClass itin, string opc, string asm, 1058218893Sdim list<dag> pattern> 1059224145Sdim : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1060218893Sdim T1LoadStore<0b0101, opcode> { 1061218893Sdim bits<3> Rt; 1062218893Sdim bits<8> addr; 1063218893Sdim let Inst{8-6} = addr{5-3}; // Rm 1064218893Sdim let Inst{5-3} = addr{2-0}; // Rn 1065218893Sdim let Inst{2-0} = Rt; 1066218893Sdim} 1067218893Sdimclass T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 1068218893Sdim InstrItinClass itin, string opc, string asm, 1069218893Sdim list<dag> pattern> 1070224145Sdim : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1071218893Sdim T1LoadStore<opA, {opB,?,?}> { 1072218893Sdim bits<3> Rt; 1073218893Sdim bits<8> addr; 1074218893Sdim let Inst{10-6} = addr{7-3}; // imm5 1075218893Sdim let Inst{5-3} = addr{2-0}; // Rn 1076218893Sdim let Inst{2-0} = Rt; 1077218893Sdim} 1078218893Sdim 1079201360Srdivacky// A6.2.5 Miscellaneous 16-bit instructions encoding. 1080201360Srdivackyclass T1Misc<bits<7> opcode> : Encoding16 { 1081201360Srdivacky let Inst{15-12} = 0b1011; 1082201360Srdivacky let Inst{11-5} = opcode; 1083201360Srdivacky} 1084201360Srdivacky 1085195098Sed// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1086224145Sdimclass Thumb2I<dag oops, dag iops, AddrMode am, int sz, 1087198090Srdivacky InstrItinClass itin, 1088195098Sed string opc, string asm, string cstr, list<dag> pattern> 1089198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1090195098Sed let OutOperandList = oops; 1091205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1092218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1093195098Sed let Pattern = pattern; 1094195340Sed list<Predicate> Predicates = [IsThumb2]; 1095226633Sdim let DecoderNamespace = "Thumb2"; 1096194754Sed} 1097194754Sed 1098212904Sdim// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 1099212904Sdim// input operand since by default it's a zero register. It will become an 1100212904Sdim// implicit def once it's "flipped". 1101218893Sdim// 1102195098Sed// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1103195098Sed// more consistent. 1104224145Sdimclass Thumb2sI<dag oops, dag iops, AddrMode am, int sz, 1105198090Srdivacky InstrItinClass itin, 1106195098Sed string opc, string asm, string cstr, list<dag> pattern> 1107198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1108218893Sdim bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 1109218893Sdim let Inst{20} = s; 1110218893Sdim 1111195098Sed let OutOperandList = oops; 1112205407Srdivacky let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1113218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 1114195098Sed let Pattern = pattern; 1115195340Sed list<Predicate> Predicates = [IsThumb2]; 1116226633Sdim let DecoderNamespace = "Thumb2"; 1117195098Sed} 1118194754Sed 1119195098Sed// Special cases 1120224145Sdimclass Thumb2XI<dag oops, dag iops, AddrMode am, int sz, 1121198090Srdivacky InstrItinClass itin, 1122195098Sed string asm, string cstr, list<dag> pattern> 1123198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1124195098Sed let OutOperandList = oops; 1125195098Sed let InOperandList = iops; 1126208599Srdivacky let AsmString = asm; 1127195098Sed let Pattern = pattern; 1128195340Sed list<Predicate> Predicates = [IsThumb2]; 1129226633Sdim let DecoderNamespace = "Thumb2"; 1130194754Sed} 1131194754Sed 1132224145Sdimclass ThumbXI<dag oops, dag iops, AddrMode am, int sz, 1133206083Srdivacky InstrItinClass itin, 1134206083Srdivacky string asm, string cstr, list<dag> pattern> 1135200581Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1136200581Srdivacky let OutOperandList = oops; 1137200581Srdivacky let InOperandList = iops; 1138208599Srdivacky let AsmString = asm; 1139200581Srdivacky let Pattern = pattern; 1140218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1141226633Sdim let DecoderNamespace = "Thumb"; 1142200581Srdivacky} 1143200581Srdivacky 1144198090Srdivackyclass T2I<dag oops, dag iops, InstrItinClass itin, 1145198090Srdivacky string opc, string asm, list<dag> pattern> 1146224145Sdim : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1147198090Srdivackyclass T2Ii12<dag oops, dag iops, InstrItinClass itin, 1148198090Srdivacky string opc, string asm, list<dag> pattern> 1149224145Sdim : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>; 1150198090Srdivackyclass T2Ii8<dag oops, dag iops, InstrItinClass itin, 1151198090Srdivacky string opc, string asm, list<dag> pattern> 1152224145Sdim : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>; 1153198090Srdivackyclass T2Iso<dag oops, dag iops, InstrItinClass itin, 1154198090Srdivacky string opc, string asm, list<dag> pattern> 1155224145Sdim : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>; 1156198090Srdivackyclass T2Ipc<dag oops, dag iops, InstrItinClass itin, 1157198090Srdivacky string opc, string asm, list<dag> pattern> 1158224145Sdim : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>; 1159218893Sdimclass T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, 1160226633Sdim string opc, string asm, string cstr, list<dag> pattern> 1161226633Sdim : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, 1162201360Srdivacky pattern> { 1163218893Sdim bits<4> Rt; 1164218893Sdim bits<4> Rt2; 1165218893Sdim bits<13> addr; 1166218893Sdim let Inst{31-25} = 0b1110100; 1167212904Sdim let Inst{24} = P; 1168218893Sdim let Inst{23} = addr{8}; 1169212904Sdim let Inst{22} = 1; 1170212904Sdim let Inst{21} = W; 1171218893Sdim let Inst{20} = isLoad; 1172218893Sdim let Inst{19-16} = addr{12-9}; 1173218893Sdim let Inst{15-12} = Rt{3-0}; 1174218893Sdim let Inst{11-8} = Rt2{3-0}; 1175218893Sdim let Inst{7-0} = addr{7-0}; 1176201360Srdivacky} 1177226633Sdimclass T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops, 1178226633Sdim InstrItinClass itin, string opc, string asm, string cstr, 1179226633Sdim list<dag> pattern> 1180226633Sdim : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, 1181226633Sdim pattern> { 1182226633Sdim bits<4> Rt; 1183226633Sdim bits<4> Rt2; 1184226633Sdim bits<4> addr; 1185226633Sdim bits<9> imm; 1186226633Sdim let Inst{31-25} = 0b1110100; 1187226633Sdim let Inst{24} = P; 1188226633Sdim let Inst{23} = imm{8}; 1189226633Sdim let Inst{22} = 1; 1190226633Sdim let Inst{21} = W; 1191226633Sdim let Inst{20} = isLoad; 1192226633Sdim let Inst{19-16} = addr; 1193226633Sdim let Inst{15-12} = Rt{3-0}; 1194226633Sdim let Inst{11-8} = Rt2{3-0}; 1195226633Sdim let Inst{7-0} = imm{7-0}; 1196226633Sdim} 1197195098Sed 1198198090Srdivackyclass T2sI<dag oops, dag iops, InstrItinClass itin, 1199198090Srdivacky string opc, string asm, list<dag> pattern> 1200224145Sdim : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1201195098Sed 1202198090Srdivackyclass T2XI<dag oops, dag iops, InstrItinClass itin, 1203198090Srdivacky string asm, list<dag> pattern> 1204224145Sdim : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 1205198090Srdivackyclass T2JTI<dag oops, dag iops, InstrItinClass itin, 1206198090Srdivacky string asm, list<dag> pattern> 1207224145Sdim : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 1208195098Sed 1209218893Sdim// Move to/from coprocessor instructions 1210224145Sdimclass T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern> 1211224145Sdim : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> { 1212224145Sdim let Inst{31-28} = opc; 1213218893Sdim} 1214198090Srdivacky 1215205218Srdivacky// Two-address instructions 1216205218Srdivackyclass T2XIt<dag oops, dag iops, InstrItinClass itin, 1217205218Srdivacky string asm, string cstr, list<dag> pattern> 1218224145Sdim : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>; 1219198090Srdivacky 1220226633Sdim// T2Ipreldst - Thumb2 pre-indexed load / store instructions. 1221226633Sdimclass T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre, 1222201360Srdivacky dag oops, dag iops, 1223201360Srdivacky AddrMode am, IndexMode im, InstrItinClass itin, 1224195340Sed string opc, string asm, string cstr, list<dag> pattern> 1225224145Sdim : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1226195340Sed let OutOperandList = oops; 1227205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1228218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1229195340Sed let Pattern = pattern; 1230195340Sed list<Predicate> Predicates = [IsThumb2]; 1231226633Sdim let DecoderNamespace = "Thumb2"; 1232226633Sdim 1233226633Sdim bits<4> Rt; 1234226633Sdim bits<13> addr; 1235201360Srdivacky let Inst{31-27} = 0b11111; 1236201360Srdivacky let Inst{26-25} = 0b00; 1237212904Sdim let Inst{24} = signed; 1238212904Sdim let Inst{23} = 0; 1239201360Srdivacky let Inst{22-21} = opcod; 1240212904Sdim let Inst{20} = load; 1241226633Sdim let Inst{19-16} = addr{12-9}; 1242226633Sdim let Inst{15-12} = Rt{3-0}; 1243212904Sdim let Inst{11} = 1; 1244201360Srdivacky // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1245212904Sdim let Inst{10} = pre; // The P bit. 1246226633Sdim let Inst{9} = addr{8}; // Sign bit 1247212904Sdim let Inst{8} = 1; // The W bit. 1248226633Sdim let Inst{7-0} = addr{7-0}; 1249195340Sed 1250226633Sdim let DecoderMethod = "DecodeT2LdStPre"; 1251226633Sdim} 1252218893Sdim 1253226633Sdim// T2Ipostldst - Thumb2 post-indexed load / store instructions. 1254226633Sdimclass T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre, 1255226633Sdim dag oops, dag iops, 1256226633Sdim AddrMode am, IndexMode im, InstrItinClass itin, 1257226633Sdim string opc, string asm, string cstr, list<dag> pattern> 1258226633Sdim : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1259226633Sdim let OutOperandList = oops; 1260226633Sdim let InOperandList = !con(iops, (ins pred:$p)); 1261226633Sdim let AsmString = !strconcat(opc, "${p}", asm); 1262226633Sdim let Pattern = pattern; 1263226633Sdim list<Predicate> Predicates = [IsThumb2]; 1264226633Sdim let DecoderNamespace = "Thumb2"; 1265226633Sdim 1266218893Sdim bits<4> Rt; 1267218893Sdim bits<4> Rn; 1268226633Sdim bits<9> offset; 1269226633Sdim let Inst{31-27} = 0b11111; 1270226633Sdim let Inst{26-25} = 0b00; 1271226633Sdim let Inst{24} = signed; 1272226633Sdim let Inst{23} = 0; 1273226633Sdim let Inst{22-21} = opcod; 1274226633Sdim let Inst{20} = load; 1275226633Sdim let Inst{19-16} = Rn; 1276218893Sdim let Inst{15-12} = Rt{3-0}; 1277226633Sdim let Inst{11} = 1; 1278226633Sdim // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1279226633Sdim let Inst{10} = pre; // The P bit. 1280226633Sdim let Inst{9} = offset{8}; // Sign bit 1281226633Sdim let Inst{8} = 1; // The W bit. 1282226633Sdim let Inst{7-0} = offset{7-0}; 1283226633Sdim 1284226633Sdim let DecoderMethod = "DecodeT2LdStPre"; 1285204642Srdivacky} 1286204642Srdivacky 1287198090Srdivacky// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1288198090Srdivackyclass Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1289218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1290198090Srdivacky} 1291195340Sed 1292198090Srdivacky// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1293198090Srdivackyclass T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1294218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1295198090Srdivacky} 1296198090Srdivacky 1297223017Sdim// T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode. 1298223017Sdimclass T2v6Pat<dag pattern, dag result> : Pat<pattern, result> { 1299223017Sdim list<Predicate> Predicates = [IsThumb2, HasV6T2]; 1300223017Sdim} 1301223017Sdim 1302195098Sed// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1303195098Sedclass T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1304195340Sed list<Predicate> Predicates = [IsThumb2]; 1305195098Sed} 1306195098Sed 1307193323Sed//===----------------------------------------------------------------------===// 1308193323Sed 1309193323Sed//===----------------------------------------------------------------------===// 1310193323Sed// ARM VFP Instruction templates. 1311193323Sed// 1312193323Sed 1313198090Srdivacky// Almost all VFP instructions are predicable. 1314224145Sdimclass VFPI<dag oops, dag iops, AddrMode am, int sz, 1315198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1316198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1317198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1318218893Sdim bits<4> p; 1319218893Sdim let Inst{31-28} = p; 1320198090Srdivacky let OutOperandList = oops; 1321205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1322218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1323198090Srdivacky let Pattern = pattern; 1324218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1325226633Sdim let DecoderNamespace = "VFP"; 1326198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1327198090Srdivacky} 1328198090Srdivacky 1329198090Srdivacky// Special cases 1330224145Sdimclass VFPXI<dag oops, dag iops, AddrMode am, int sz, 1331198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1332198090Srdivacky string asm, string cstr, list<dag> pattern> 1333198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1334218893Sdim bits<4> p; 1335218893Sdim let Inst{31-28} = p; 1336198090Srdivacky let OutOperandList = oops; 1337198090Srdivacky let InOperandList = iops; 1338208599Srdivacky let AsmString = asm; 1339198090Srdivacky let Pattern = pattern; 1340218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1341226633Sdim let DecoderNamespace = "VFP"; 1342198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1343198090Srdivacky} 1344198090Srdivacky 1345198090Srdivackyclass VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1346198090Srdivacky string opc, string asm, list<dag> pattern> 1347224145Sdim : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 1348218893Sdim opc, asm, "", pattern> { 1349218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1350218893Sdim} 1351198090Srdivacky 1352193323Sed// ARM VFP addrmode5 loads and stores 1353193323Sedclass ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1354198090Srdivacky InstrItinClass itin, 1355193323Sed string opc, string asm, list<dag> pattern> 1356224145Sdim : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1357206083Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1358218893Sdim // Instruction operands. 1359218893Sdim bits<5> Dd; 1360218893Sdim bits<13> addr; 1361218893Sdim 1362218893Sdim // Encode instruction operands. 1363218893Sdim let Inst{23} = addr{8}; // U (add = (U == '1')) 1364218893Sdim let Inst{22} = Dd{4}; 1365218893Sdim let Inst{19-16} = addr{12-9}; // Rn 1366218893Sdim let Inst{15-12} = Dd{3-0}; 1367218893Sdim let Inst{7-0} = addr{7-0}; // imm8 1368218893Sdim 1369193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1370193323Sed let Inst{27-24} = opcod1; 1371193323Sed let Inst{21-20} = opcod2; 1372218893Sdim let Inst{11-9} = 0b101; 1373218893Sdim let Inst{8} = 1; // Double precision 1374198892Srdivacky 1375218893Sdim // Loads & stores operate on both NEON and VFP pipelines. 1376206274Srdivacky let D = VFPNeonDomain; 1377193323Sed} 1378193323Sed 1379193323Sedclass ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1380198090Srdivacky InstrItinClass itin, 1381193323Sed string opc, string asm, list<dag> pattern> 1382224145Sdim : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1383206083Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1384218893Sdim // Instruction operands. 1385218893Sdim bits<5> Sd; 1386218893Sdim bits<13> addr; 1387218893Sdim 1388218893Sdim // Encode instruction operands. 1389218893Sdim let Inst{23} = addr{8}; // U (add = (U == '1')) 1390218893Sdim let Inst{22} = Sd{0}; 1391218893Sdim let Inst{19-16} = addr{12-9}; // Rn 1392218893Sdim let Inst{15-12} = Sd{4-1}; 1393218893Sdim let Inst{7-0} = addr{7-0}; // imm8 1394218893Sdim 1395193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1396193323Sed let Inst{27-24} = opcod1; 1397193323Sed let Inst{21-20} = opcod2; 1398218893Sdim let Inst{11-9} = 0b101; 1399218893Sdim let Inst{8} = 0; // Single precision 1400218893Sdim 1401218893Sdim // Loads & stores operate on both NEON and VFP pipelines. 1402218893Sdim let D = VFPNeonDomain; 1403193323Sed} 1404193323Sed 1405218893Sdim// VFP Load / store multiple pseudo instructions. 1406218893Sdimclass PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1407218893Sdim list<dag> pattern> 1408224145Sdim : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain, 1409218893Sdim cstr, itin> { 1410218893Sdim let OutOperandList = oops; 1411218893Sdim let InOperandList = !con(iops, (ins pred:$p)); 1412218893Sdim let Pattern = pattern; 1413218893Sdim list<Predicate> Predicates = [HasVFP2]; 1414218893Sdim} 1415218893Sdim 1416193323Sed// Load / store multiple 1417212904Sdimclass AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1418205218Srdivacky string asm, string cstr, list<dag> pattern> 1419224145Sdim : VFPXI<oops, iops, AddrMode4, 4, im, 1420206083Srdivacky VFPLdStMulFrm, itin, asm, cstr, pattern> { 1421218893Sdim // Instruction operands. 1422218893Sdim bits<4> Rn; 1423218893Sdim bits<13> regs; 1424218893Sdim 1425218893Sdim // Encode instruction operands. 1426218893Sdim let Inst{19-16} = Rn; 1427218893Sdim let Inst{22} = regs{12}; 1428218893Sdim let Inst{15-12} = regs{11-8}; 1429218893Sdim let Inst{7-0} = regs{7-0}; 1430218893Sdim 1431193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1432193323Sed let Inst{27-25} = 0b110; 1433218893Sdim let Inst{11-9} = 0b101; 1434218893Sdim let Inst{8} = 1; // Double precision 1435193323Sed} 1436193323Sed 1437212904Sdimclass AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1438205218Srdivacky string asm, string cstr, list<dag> pattern> 1439224145Sdim : VFPXI<oops, iops, AddrMode4, 4, im, 1440206083Srdivacky VFPLdStMulFrm, itin, asm, cstr, pattern> { 1441218893Sdim // Instruction operands. 1442218893Sdim bits<4> Rn; 1443218893Sdim bits<13> regs; 1444218893Sdim 1445218893Sdim // Encode instruction operands. 1446218893Sdim let Inst{19-16} = Rn; 1447218893Sdim let Inst{22} = regs{8}; 1448218893Sdim let Inst{15-12} = regs{12-9}; 1449218893Sdim let Inst{7-0} = regs{7-0}; 1450218893Sdim 1451193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1452193323Sed let Inst{27-25} = 0b110; 1453218893Sdim let Inst{11-9} = 0b101; 1454218893Sdim let Inst{8} = 0; // Single precision 1455193323Sed} 1456193323Sed 1457193323Sed// Double precision, unary 1458203954Srdivackyclass ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1459203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1460203954Srdivacky string asm, list<dag> pattern> 1461198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1462218893Sdim // Instruction operands. 1463218893Sdim bits<5> Dd; 1464218893Sdim bits<5> Dm; 1465218893Sdim 1466218893Sdim // Encode instruction operands. 1467218893Sdim let Inst{3-0} = Dm{3-0}; 1468218893Sdim let Inst{5} = Dm{4}; 1469218893Sdim let Inst{15-12} = Dd{3-0}; 1470218893Sdim let Inst{22} = Dd{4}; 1471218893Sdim 1472203954Srdivacky let Inst{27-23} = opcod1; 1473203954Srdivacky let Inst{21-20} = opcod2; 1474203954Srdivacky let Inst{19-16} = opcod3; 1475218893Sdim let Inst{11-9} = 0b101; 1476218893Sdim let Inst{8} = 1; // Double precision 1477203954Srdivacky let Inst{7-6} = opcod4; 1478203954Srdivacky let Inst{4} = opcod5; 1479193323Sed} 1480193323Sed 1481193323Sed// Double precision, binary 1482203954Srdivackyclass ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1483206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1484206083Srdivacky list<dag> pattern> 1485198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1486218893Sdim // Instruction operands. 1487218893Sdim bits<5> Dd; 1488218893Sdim bits<5> Dn; 1489218893Sdim bits<5> Dm; 1490193323Sed 1491218893Sdim // Encode instruction operands. 1492218893Sdim let Inst{3-0} = Dm{3-0}; 1493218893Sdim let Inst{5} = Dm{4}; 1494218893Sdim let Inst{19-16} = Dn{3-0}; 1495218893Sdim let Inst{7} = Dn{4}; 1496218893Sdim let Inst{15-12} = Dd{3-0}; 1497218893Sdim let Inst{22} = Dd{4}; 1498218893Sdim 1499206083Srdivacky let Inst{27-23} = opcod1; 1500206083Srdivacky let Inst{21-20} = opcod2; 1501218893Sdim let Inst{11-9} = 0b101; 1502218893Sdim let Inst{8} = 1; // Double precision 1503212904Sdim let Inst{6} = op6; 1504212904Sdim let Inst{4} = op4; 1505206083Srdivacky} 1506206083Srdivacky 1507193323Sed// Single precision, unary 1508203954Srdivackyclass ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1509203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1510203954Srdivacky string asm, list<dag> pattern> 1511198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1512218893Sdim // Instruction operands. 1513218893Sdim bits<5> Sd; 1514218893Sdim bits<5> Sm; 1515218893Sdim 1516218893Sdim // Encode instruction operands. 1517218893Sdim let Inst{3-0} = Sm{4-1}; 1518218893Sdim let Inst{5} = Sm{0}; 1519218893Sdim let Inst{15-12} = Sd{4-1}; 1520218893Sdim let Inst{22} = Sd{0}; 1521218893Sdim 1522203954Srdivacky let Inst{27-23} = opcod1; 1523203954Srdivacky let Inst{21-20} = opcod2; 1524203954Srdivacky let Inst{19-16} = opcod3; 1525218893Sdim let Inst{11-9} = 0b101; 1526218893Sdim let Inst{8} = 0; // Single precision 1527203954Srdivacky let Inst{7-6} = opcod4; 1528203954Srdivacky let Inst{4} = opcod5; 1529193323Sed} 1530193323Sed 1531218893Sdim// Single precision unary, if no NEON. Same as ASuI except not available if 1532218893Sdim// NEON is enabled. 1533203954Srdivackyclass ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1534203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1535203954Srdivacky string asm, list<dag> pattern> 1536203954Srdivacky : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1537203954Srdivacky pattern> { 1538198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1539198090Srdivacky} 1540198090Srdivacky 1541193323Sed// Single precision, binary 1542203954Srdivackyclass ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1543203954Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1544198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1545218893Sdim // Instruction operands. 1546218893Sdim bits<5> Sd; 1547218893Sdim bits<5> Sn; 1548218893Sdim bits<5> Sm; 1549218893Sdim 1550218893Sdim // Encode instruction operands. 1551218893Sdim let Inst{3-0} = Sm{4-1}; 1552218893Sdim let Inst{5} = Sm{0}; 1553218893Sdim let Inst{19-16} = Sn{4-1}; 1554218893Sdim let Inst{7} = Sn{0}; 1555218893Sdim let Inst{15-12} = Sd{4-1}; 1556218893Sdim let Inst{22} = Sd{0}; 1557218893Sdim 1558203954Srdivacky let Inst{27-23} = opcod1; 1559203954Srdivacky let Inst{21-20} = opcod2; 1560218893Sdim let Inst{11-9} = 0b101; 1561218893Sdim let Inst{8} = 0; // Single precision 1562212904Sdim let Inst{6} = op6; 1563212904Sdim let Inst{4} = op4; 1564193323Sed} 1565193323Sed 1566218893Sdim// Single precision binary, if no NEON. Same as ASbI except not available if 1567218893Sdim// NEON is enabled. 1568203954Srdivackyclass ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1569206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1570206083Srdivacky list<dag> pattern> 1571203954Srdivacky : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1572198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1573218893Sdim 1574218893Sdim // Instruction operands. 1575218893Sdim bits<5> Sd; 1576218893Sdim bits<5> Sn; 1577218893Sdim bits<5> Sm; 1578218893Sdim 1579218893Sdim // Encode instruction operands. 1580218893Sdim let Inst{3-0} = Sm{4-1}; 1581218893Sdim let Inst{5} = Sm{0}; 1582218893Sdim let Inst{19-16} = Sn{4-1}; 1583218893Sdim let Inst{7} = Sn{0}; 1584218893Sdim let Inst{15-12} = Sd{4-1}; 1585218893Sdim let Inst{22} = Sd{0}; 1586198090Srdivacky} 1587198090Srdivacky 1588193323Sed// VFP conversion instructions 1589203954Srdivackyclass AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1590203954Srdivacky dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1591203954Srdivacky list<dag> pattern> 1592198090Srdivacky : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1593203954Srdivacky let Inst{27-23} = opcod1; 1594203954Srdivacky let Inst{21-20} = opcod2; 1595203954Srdivacky let Inst{19-16} = opcod3; 1596203954Srdivacky let Inst{11-8} = opcod4; 1597193323Sed let Inst{6} = 1; 1598203954Srdivacky let Inst{4} = 0; 1599193323Sed} 1600193323Sed 1601203954Srdivacky// VFP conversion between floating-point and fixed-point 1602203954Srdivackyclass AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1603206083Srdivacky dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1604206083Srdivacky list<dag> pattern> 1605203954Srdivacky : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1606234353Sdim bits<5> fbits; 1607203954Srdivacky // size (fixed-point number): sx == 0 ? 16 : 32 1608203954Srdivacky let Inst{7} = op5; // sx 1609234353Sdim let Inst{5} = fbits{0}; 1610234353Sdim let Inst{3-0} = fbits{4-1}; 1611203954Srdivacky} 1612203954Srdivacky 1613198090Srdivacky// VFP conversion instructions, if no NEON 1614203954Srdivackyclass AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1615198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1616198090Srdivacky string opc, string asm, list<dag> pattern> 1617203954Srdivacky : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1618203954Srdivacky pattern> { 1619198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1620198090Srdivacky} 1621198090Srdivacky 1622193323Sedclass AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1623198090Srdivacky InstrItinClass itin, 1624198090Srdivacky string opc, string asm, list<dag> pattern> 1625198090Srdivacky : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1626193323Sed let Inst{27-20} = opcod1; 1627193323Sed let Inst{11-8} = opcod2; 1628193323Sed let Inst{4} = 1; 1629193323Sed} 1630193323Sed 1631198090Srdivackyclass AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1632198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1633198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1634193323Sed 1635206083Srdivackyclass AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1636198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1637198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1638193323Sed 1639198090Srdivackyclass AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1640198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1641198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1642193323Sed 1643198090Srdivackyclass AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1644198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1645198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1646193323Sed 1647193323Sed//===----------------------------------------------------------------------===// 1648193323Sed 1649194710Sed//===----------------------------------------------------------------------===// 1650194710Sed// ARM NEON Instruction templates. 1651194710Sed// 1652193323Sed 1653205407Srdivackyclass NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1654205407Srdivacky InstrItinClass itin, string opc, string dt, string asm, string cstr, 1655205407Srdivacky list<dag> pattern> 1656224145Sdim : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1657194710Sed let OutOperandList = oops; 1658205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1659218893Sdim let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1660194710Sed let Pattern = pattern; 1661194710Sed list<Predicate> Predicates = [HasNEON]; 1662226633Sdim let DecoderNamespace = "NEON"; 1663193323Sed} 1664193323Sed 1665199989Srdivacky// Same as NeonI except it does not have a "data type" specifier. 1666206083Srdivackyclass NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1667206083Srdivacky InstrItinClass itin, string opc, string asm, string cstr, 1668206083Srdivacky list<dag> pattern> 1669224145Sdim : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1670199989Srdivacky let OutOperandList = oops; 1671205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1672218893Sdim let AsmString = !strconcat(opc, "${p}", "\t", asm); 1673199989Srdivacky let Pattern = pattern; 1674199989Srdivacky list<Predicate> Predicates = [HasNEON]; 1675226633Sdim let DecoderNamespace = "NEON"; 1676193323Sed} 1677194710Sed 1678198090Srdivackyclass NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1679198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1680199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1681205407Srdivacky : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1682205407Srdivacky cstr, pattern> { 1683198090Srdivacky let Inst{31-24} = 0b11110100; 1684212904Sdim let Inst{23} = op23; 1685198396Srdivacky let Inst{21-20} = op21_20; 1686212904Sdim let Inst{11-8} = op11_8; 1687212904Sdim let Inst{7-4} = op7_4; 1688218893Sdim 1689218893Sdim let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1690226633Sdim let DecoderNamespace = "NEONLoadStore"; 1691218893Sdim 1692218893Sdim bits<5> Vd; 1693218893Sdim bits<6> Rn; 1694218893Sdim bits<4> Rm; 1695218893Sdim 1696218893Sdim let Inst{22} = Vd{4}; 1697218893Sdim let Inst{15-12} = Vd{3-0}; 1698218893Sdim let Inst{19-16} = Rn{3-0}; 1699218893Sdim let Inst{3-0} = Rm{3-0}; 1700198090Srdivacky} 1701198090Srdivacky 1702218893Sdimclass NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1703218893Sdim dag oops, dag iops, InstrItinClass itin, 1704218893Sdim string opc, string dt, string asm, string cstr, list<dag> pattern> 1705218893Sdim : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1706218893Sdim dt, asm, cstr, pattern> { 1707218893Sdim bits<3> lane; 1708218893Sdim} 1709218893Sdim 1710212904Sdimclass PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1711224145Sdim : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1712212904Sdim itin> { 1713212904Sdim let OutOperandList = oops; 1714212904Sdim let InOperandList = !con(iops, (ins pred:$p)); 1715212904Sdim list<Predicate> Predicates = [HasNEON]; 1716212904Sdim} 1717212904Sdim 1718218893Sdimclass PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1719218893Sdim list<dag> pattern> 1720224145Sdim : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1721218893Sdim itin> { 1722218893Sdim let OutOperandList = oops; 1723218893Sdim let InOperandList = !con(iops, (ins pred:$p)); 1724218893Sdim let Pattern = pattern; 1725218893Sdim list<Predicate> Predicates = [HasNEON]; 1726218893Sdim} 1727218893Sdim 1728206083Srdivackyclass NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1729199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1730206083Srdivacky : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1731206083Srdivacky pattern> { 1732194710Sed let Inst{31-25} = 0b1111001; 1733218893Sdim let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1734226633Sdim let DecoderNamespace = "NEONData"; 1735194710Sed} 1736194710Sed 1737206083Srdivackyclass NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1738206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1739206083Srdivacky : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1740206083Srdivacky cstr, pattern> { 1741199989Srdivacky let Inst{31-25} = 0b1111001; 1742218893Sdim let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1743226633Sdim let DecoderNamespace = "NEONData"; 1744199989Srdivacky} 1745199989Srdivacky 1746194710Sed// NEON "one register and a modified immediate" format. 1747194710Sedclass N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1748194710Sed bit op5, bit op4, 1749198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1750206083Srdivacky string opc, string dt, string asm, string cstr, 1751206083Srdivacky list<dag> pattern> 1752206083Srdivacky : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1753212904Sdim let Inst{23} = op23; 1754194710Sed let Inst{21-19} = op21_19; 1755212904Sdim let Inst{11-8} = op11_8; 1756212904Sdim let Inst{7} = op7; 1757212904Sdim let Inst{6} = op6; 1758212904Sdim let Inst{5} = op5; 1759212904Sdim let Inst{4} = op4; 1760218893Sdim 1761218893Sdim // Instruction operands. 1762218893Sdim bits<5> Vd; 1763218893Sdim bits<13> SIMM; 1764218893Sdim 1765218893Sdim let Inst{15-12} = Vd{3-0}; 1766218893Sdim let Inst{22} = Vd{4}; 1767218893Sdim let Inst{24} = SIMM{7}; 1768218893Sdim let Inst{18-16} = SIMM{6-4}; 1769218893Sdim let Inst{3-0} = SIMM{3-0}; 1770226633Sdim let DecoderMethod = "DecodeNEONModImmInstruction"; 1771194710Sed} 1772194710Sed 1773194710Sed// NEON 2 vector register format. 1774194710Sedclass N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1775194710Sed bits<5> op11_7, bit op6, bit op4, 1776198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1777199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1778206083Srdivacky : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 1779194710Sed let Inst{24-23} = op24_23; 1780194710Sed let Inst{21-20} = op21_20; 1781194710Sed let Inst{19-18} = op19_18; 1782194710Sed let Inst{17-16} = op17_16; 1783212904Sdim let Inst{11-7} = op11_7; 1784212904Sdim let Inst{6} = op6; 1785212904Sdim let Inst{4} = op4; 1786218893Sdim 1787218893Sdim // Instruction operands. 1788218893Sdim bits<5> Vd; 1789218893Sdim bits<5> Vm; 1790218893Sdim 1791218893Sdim let Inst{15-12} = Vd{3-0}; 1792218893Sdim let Inst{22} = Vd{4}; 1793218893Sdim let Inst{3-0} = Vm{3-0}; 1794218893Sdim let Inst{5} = Vm{4}; 1795194710Sed} 1796194710Sed 1797199989Srdivacky// Same as N2V except it doesn't have a datatype suffix. 1798199989Srdivackyclass N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1799206083Srdivacky bits<5> op11_7, bit op6, bit op4, 1800206083Srdivacky dag oops, dag iops, InstrItinClass itin, 1801206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1802206083Srdivacky : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 1803198396Srdivacky let Inst{24-23} = op24_23; 1804198396Srdivacky let Inst{21-20} = op21_20; 1805199989Srdivacky let Inst{19-18} = op19_18; 1806199989Srdivacky let Inst{17-16} = op17_16; 1807212904Sdim let Inst{11-7} = op11_7; 1808212904Sdim let Inst{6} = op6; 1809212904Sdim let Inst{4} = op4; 1810218893Sdim 1811218893Sdim // Instruction operands. 1812218893Sdim bits<5> Vd; 1813218893Sdim bits<5> Vm; 1814218893Sdim 1815218893Sdim let Inst{15-12} = Vd{3-0}; 1816218893Sdim let Inst{22} = Vd{4}; 1817218893Sdim let Inst{3-0} = Vm{3-0}; 1818218893Sdim let Inst{5} = Vm{4}; 1819198396Srdivacky} 1820198396Srdivacky 1821194710Sed// NEON 2 vector register with immediate. 1822198396Srdivackyclass N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1823206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1824199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1825206083Srdivacky : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1826212904Sdim let Inst{24} = op24; 1827212904Sdim let Inst{23} = op23; 1828194710Sed let Inst{11-8} = op11_8; 1829212904Sdim let Inst{7} = op7; 1830212904Sdim let Inst{6} = op6; 1831212904Sdim let Inst{4} = op4; 1832218893Sdim 1833218893Sdim // Instruction operands. 1834218893Sdim bits<5> Vd; 1835218893Sdim bits<5> Vm; 1836218893Sdim bits<6> SIMM; 1837218893Sdim 1838218893Sdim let Inst{15-12} = Vd{3-0}; 1839218893Sdim let Inst{22} = Vd{4}; 1840218893Sdim let Inst{3-0} = Vm{3-0}; 1841218893Sdim let Inst{5} = Vm{4}; 1842218893Sdim let Inst{21-16} = SIMM{5-0}; 1843194710Sed} 1844194710Sed 1845194710Sed// NEON 3 vector register format. 1846221345Sdim 1847223017Sdimclass N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1848223017Sdim bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1849223017Sdim string opc, string dt, string asm, string cstr, 1850223017Sdim list<dag> pattern> 1851206083Srdivacky : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1852212904Sdim let Inst{24} = op24; 1853212904Sdim let Inst{23} = op23; 1854194710Sed let Inst{21-20} = op21_20; 1855212904Sdim let Inst{11-8} = op11_8; 1856212904Sdim let Inst{6} = op6; 1857212904Sdim let Inst{4} = op4; 1858221345Sdim} 1859218893Sdim 1860221345Sdimclass N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1861221345Sdim dag oops, dag iops, Format f, InstrItinClass itin, 1862221345Sdim string opc, string dt, string asm, string cstr, list<dag> pattern> 1863221345Sdim : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1864221345Sdim oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1865221345Sdim 1866218893Sdim // Instruction operands. 1867218893Sdim bits<5> Vd; 1868218893Sdim bits<5> Vn; 1869218893Sdim bits<5> Vm; 1870218893Sdim 1871218893Sdim let Inst{15-12} = Vd{3-0}; 1872218893Sdim let Inst{22} = Vd{4}; 1873218893Sdim let Inst{19-16} = Vn{3-0}; 1874218893Sdim let Inst{7} = Vn{4}; 1875218893Sdim let Inst{3-0} = Vm{3-0}; 1876218893Sdim let Inst{5} = Vm{4}; 1877194710Sed} 1878194710Sed 1879223017Sdimclass N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1880223017Sdim bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1881223017Sdim string opc, string dt, string asm, string cstr, 1882223017Sdim list<dag> pattern> 1883221345Sdim : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1884221345Sdim oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1885221345Sdim 1886221345Sdim // Instruction operands. 1887221345Sdim bits<5> Vd; 1888221345Sdim bits<5> Vn; 1889221345Sdim bits<5> Vm; 1890221345Sdim bit lane; 1891221345Sdim 1892221345Sdim let Inst{15-12} = Vd{3-0}; 1893221345Sdim let Inst{22} = Vd{4}; 1894221345Sdim let Inst{19-16} = Vn{3-0}; 1895221345Sdim let Inst{7} = Vn{4}; 1896221345Sdim let Inst{3-0} = Vm{3-0}; 1897221345Sdim let Inst{5} = lane; 1898221345Sdim} 1899221345Sdim 1900223017Sdimclass N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1901223017Sdim bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1902223017Sdim string opc, string dt, string asm, string cstr, 1903223017Sdim list<dag> pattern> 1904221345Sdim : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1905221345Sdim oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1906221345Sdim 1907221345Sdim // Instruction operands. 1908221345Sdim bits<5> Vd; 1909221345Sdim bits<5> Vn; 1910221345Sdim bits<5> Vm; 1911221345Sdim bits<2> lane; 1912221345Sdim 1913221345Sdim let Inst{15-12} = Vd{3-0}; 1914221345Sdim let Inst{22} = Vd{4}; 1915221345Sdim let Inst{19-16} = Vn{3-0}; 1916221345Sdim let Inst{7} = Vn{4}; 1917221345Sdim let Inst{2-0} = Vm{2-0}; 1918221345Sdim let Inst{5} = lane{1}; 1919221345Sdim let Inst{3} = lane{0}; 1920221345Sdim} 1921221345Sdim 1922206083Srdivacky// Same as N3V except it doesn't have a data type suffix. 1923206083Srdivackyclass N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1924206083Srdivacky bit op4, 1925206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1926206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1927206083Srdivacky : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 1928212904Sdim let Inst{24} = op24; 1929212904Sdim let Inst{23} = op23; 1930198396Srdivacky let Inst{21-20} = op21_20; 1931212904Sdim let Inst{11-8} = op11_8; 1932212904Sdim let Inst{6} = op6; 1933212904Sdim let Inst{4} = op4; 1934218893Sdim 1935218893Sdim // Instruction operands. 1936218893Sdim bits<5> Vd; 1937218893Sdim bits<5> Vn; 1938218893Sdim bits<5> Vm; 1939218893Sdim 1940218893Sdim let Inst{15-12} = Vd{3-0}; 1941218893Sdim let Inst{22} = Vd{4}; 1942218893Sdim let Inst{19-16} = Vn{3-0}; 1943218893Sdim let Inst{7} = Vn{4}; 1944218893Sdim let Inst{3-0} = Vm{3-0}; 1945218893Sdim let Inst{5} = Vm{4}; 1946198396Srdivacky} 1947198396Srdivacky 1948194710Sed// NEON VMOVs between scalar and core registers. 1949194710Sedclass NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1950198090Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1951199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1952224145Sdim : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain, 1953206083Srdivacky "", itin> { 1954194710Sed let Inst{27-20} = opcod1; 1955212904Sdim let Inst{11-8} = opcod2; 1956212904Sdim let Inst{6-5} = opcod3; 1957212904Sdim let Inst{4} = 1; 1958221345Sdim // A8.6.303, A8.6.328, A8.6.329 1959221345Sdim let Inst{3-0} = 0b0000; 1960199989Srdivacky 1961199989Srdivacky let OutOperandList = oops; 1962205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1963218893Sdim let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1964199989Srdivacky let Pattern = pattern; 1965194710Sed list<Predicate> Predicates = [HasNEON]; 1966218893Sdim 1967218893Sdim let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 1968226633Sdim let DecoderNamespace = "NEONDup"; 1969218893Sdim 1970218893Sdim bits<5> V; 1971218893Sdim bits<4> R; 1972218893Sdim bits<4> p; 1973218893Sdim bits<4> lane; 1974218893Sdim 1975218893Sdim let Inst{31-28} = p{3-0}; 1976218893Sdim let Inst{7} = V{4}; 1977218893Sdim let Inst{19-16} = V{3-0}; 1978218893Sdim let Inst{15-12} = R{3-0}; 1979194710Sed} 1980194710Sedclass NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1981198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1982199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1983210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 1984199989Srdivacky opc, dt, asm, pattern>; 1985194710Sedclass NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1986198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1987199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1988210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 1989199989Srdivacky opc, dt, asm, pattern>; 1990194710Sedclass NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1991198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1992199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1993210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 1994199989Srdivacky opc, dt, asm, pattern>; 1995198090Srdivacky 1996206083Srdivacky// Vector Duplicate Lane (from scalar to all elements) 1997206083Srdivackyclass NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 1998206083Srdivacky InstrItinClass itin, string opc, string dt, string asm, 1999206083Srdivacky list<dag> pattern> 2000206083Srdivacky : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 2001206083Srdivacky let Inst{24-23} = 0b11; 2002206083Srdivacky let Inst{21-20} = 0b11; 2003206083Srdivacky let Inst{19-16} = op19_16; 2004212904Sdim let Inst{11-7} = 0b11000; 2005212904Sdim let Inst{6} = op6; 2006212904Sdim let Inst{4} = 0; 2007218893Sdim 2008218893Sdim bits<5> Vd; 2009218893Sdim bits<5> Vm; 2010218893Sdim 2011218893Sdim let Inst{22} = Vd{4}; 2012218893Sdim let Inst{15-12} = Vd{3-0}; 2013218893Sdim let Inst{5} = Vm{4}; 2014218893Sdim let Inst{3-0} = Vm{3-0}; 2015206083Srdivacky} 2016206083Srdivacky 2017198090Srdivacky// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 2018198090Srdivacky// for single-precision FP. 2019198090Srdivackyclass NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 2020198090Srdivacky list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 2021198090Srdivacky} 2022234353Sdim 2023234353Sdim// VFP/NEON Instruction aliases for type suffices. 2024234353Sdimclass VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> : 2025234353Sdim InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>; 2026234353Sdim 2027234353Sdimmulticlass VFPDTAnyInstAlias<string opc, string asm, dag Result> { 2028234353Sdim def : VFPDataTypeInstAlias<opc, ".8", asm, Result>; 2029234353Sdim def : VFPDataTypeInstAlias<opc, ".16", asm, Result>; 2030234353Sdim def : VFPDataTypeInstAlias<opc, ".32", asm, Result>; 2031234353Sdim def : VFPDataTypeInstAlias<opc, ".64", asm, Result>; 2032234353Sdim} 2033234353Sdim 2034234353Sdimmulticlass NEONDTAnyInstAlias<string opc, string asm, dag Result> { 2035234353Sdim let Predicates = [HasNEON] in { 2036234353Sdim def : VFPDataTypeInstAlias<opc, ".8", asm, Result>; 2037234353Sdim def : VFPDataTypeInstAlias<opc, ".16", asm, Result>; 2038234353Sdim def : VFPDataTypeInstAlias<opc, ".32", asm, Result>; 2039234353Sdim def : VFPDataTypeInstAlias<opc, ".64", asm, Result>; 2040234353Sdim} 2041234353Sdim} 2042234353Sdim 2043234353Sdim// The same alias classes using AsmPseudo instead, for the more complex 2044234353Sdim// stuff in NEON that InstAlias can't quite handle. 2045234353Sdim// Note that we can't use anonymous defm references here like we can 2046234353Sdim// above, as we care about the ultimate instruction enum names generated, unlike 2047234353Sdim// for instalias defs. 2048234353Sdimclass NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> : 2049234353Sdim AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>; 2050234353Sdim 2051234353Sdim// Data type suffix token aliases. Implements Table A7-3 in the ARM ARM. 2052234353Sdimdef : TokenAlias<".s8", ".i8">; 2053234353Sdimdef : TokenAlias<".u8", ".i8">; 2054234353Sdimdef : TokenAlias<".s16", ".i16">; 2055234353Sdimdef : TokenAlias<".u16", ".i16">; 2056234353Sdimdef : TokenAlias<".s32", ".i32">; 2057234353Sdimdef : TokenAlias<".u32", ".i32">; 2058234353Sdimdef : TokenAlias<".s64", ".i64">; 2059234353Sdimdef : TokenAlias<".u64", ".i64">; 2060234353Sdim 2061234353Sdimdef : TokenAlias<".i8", ".8">; 2062234353Sdimdef : TokenAlias<".i16", ".16">; 2063234353Sdimdef : TokenAlias<".i32", ".32">; 2064234353Sdimdef : TokenAlias<".i64", ".64">; 2065234353Sdim 2066234353Sdimdef : TokenAlias<".p8", ".8">; 2067234353Sdimdef : TokenAlias<".p16", ".16">; 2068234353Sdim 2069234353Sdimdef : TokenAlias<".f32", ".32">; 2070234353Sdimdef : TokenAlias<".f64", ".64">; 2071234353Sdimdef : TokenAlias<".f", ".f32">; 2072234353Sdimdef : TokenAlias<".d", ".f64">; 2073