ARMInstrFormats.td revision 219077
1218893Sdim//===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=// 2206083Srdivacky// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7206083Srdivacky// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// 12193323Sed// ARM Instruction Format Definitions. 13193323Sed// 14193323Sed 15193323Sed// Format specifies the encoding used by the instruction. This is part of the 16193323Sed// ad-hoc solution used to emit machine instruction encodings by our machine 17193323Sed// code emitter. 18205407Srdivackyclass Format<bits<6> val> { 19205407Srdivacky bits<6> Value = val; 20193323Sed} 21193323Sed 22193323Seddef Pseudo : Format<0>; 23193323Seddef MulFrm : Format<1>; 24193323Seddef BrFrm : Format<2>; 25193323Seddef BrMiscFrm : Format<3>; 26193323Sed 27193323Seddef DPFrm : Format<4>; 28193323Seddef DPSoRegFrm : Format<5>; 29193323Sed 30193323Seddef LdFrm : Format<6>; 31193323Seddef StFrm : Format<7>; 32193323Seddef LdMiscFrm : Format<8>; 33193323Seddef StMiscFrm : Format<9>; 34193323Seddef LdStMulFrm : Format<10>; 35193323Sed 36205407Srdivackydef LdStExFrm : Format<11>; 37200581Srdivacky 38205407Srdivackydef ArithMiscFrm : Format<12>; 39212904Sdimdef SatFrm : Format<13>; 40212904Sdimdef ExtFrm : Format<14>; 41193323Sed 42212904Sdimdef VFPUnaryFrm : Format<15>; 43212904Sdimdef VFPBinaryFrm : Format<16>; 44212904Sdimdef VFPConv1Frm : Format<17>; 45212904Sdimdef VFPConv2Frm : Format<18>; 46212904Sdimdef VFPConv3Frm : Format<19>; 47212904Sdimdef VFPConv4Frm : Format<20>; 48212904Sdimdef VFPConv5Frm : Format<21>; 49212904Sdimdef VFPLdStFrm : Format<22>; 50212904Sdimdef VFPLdStMulFrm : Format<23>; 51212904Sdimdef VFPMiscFrm : Format<24>; 52193323Sed 53212904Sdimdef ThumbFrm : Format<25>; 54212904Sdimdef MiscFrm : Format<26>; 55193323Sed 56212904Sdimdef NGetLnFrm : Format<27>; 57212904Sdimdef NSetLnFrm : Format<28>; 58212904Sdimdef NDupFrm : Format<29>; 59212904Sdimdef NLdStFrm : Format<30>; 60212904Sdimdef N1RegModImmFrm: Format<31>; 61212904Sdimdef N2RegFrm : Format<32>; 62212904Sdimdef NVCVTFrm : Format<33>; 63212904Sdimdef NVDupLnFrm : Format<34>; 64212904Sdimdef N2RegVShLFrm : Format<35>; 65212904Sdimdef N2RegVShRFrm : Format<36>; 66212904Sdimdef N3RegFrm : Format<37>; 67212904Sdimdef N3RegVShFrm : Format<38>; 68212904Sdimdef NVExtFrm : Format<39>; 69212904Sdimdef NVMulSLFrm : Format<40>; 70212904Sdimdef NVTBLFrm : Format<41>; 71194710Sed 72198090Srdivacky// Misc flags. 73198090Srdivacky 74218893Sdim// The instruction has an Rn register operand. 75198090Srdivacky// UnaryDP - Indicates this is a unary data processing instruction, i.e. 76198090Srdivacky// it doesn't have a Rn operand. 77198090Srdivackyclass UnaryDP { bit isUnaryDataProc = 1; } 78193323Sed 79198090Srdivacky// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 80198090Srdivacky// a 16-bit Thumb instruction if certain conditions are met. 81198090Srdivackyclass Xform16Bit { bit canXformTo16Bit = 1; } 82198090Srdivacky 83193323Sed//===----------------------------------------------------------------------===// 84205407Srdivacky// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 85195340Sed// 86193323Sed 87218893Sdim// FIXME: Once the JIT is MC-ized, these can go away. 88195340Sed// Addressing mode. 89218893Sdimclass AddrMode<bits<5> val> { 90218893Sdim bits<5> Value = val; 91195340Sed} 92212904Sdimdef AddrModeNone : AddrMode<0>; 93212904Sdimdef AddrMode1 : AddrMode<1>; 94212904Sdimdef AddrMode2 : AddrMode<2>; 95212904Sdimdef AddrMode3 : AddrMode<3>; 96212904Sdimdef AddrMode4 : AddrMode<4>; 97212904Sdimdef AddrMode5 : AddrMode<5>; 98212904Sdimdef AddrMode6 : AddrMode<6>; 99212904Sdimdef AddrModeT1_1 : AddrMode<7>; 100212904Sdimdef AddrModeT1_2 : AddrMode<8>; 101212904Sdimdef AddrModeT1_4 : AddrMode<9>; 102212904Sdimdef AddrModeT1_s : AddrMode<10>; 103212904Sdimdef AddrModeT2_i12 : AddrMode<11>; 104212904Sdimdef AddrModeT2_i8 : AddrMode<12>; 105212904Sdimdef AddrModeT2_so : AddrMode<13>; 106212904Sdimdef AddrModeT2_pc : AddrMode<14>; 107195340Seddef AddrModeT2_i8s4 : AddrMode<15>; 108218893Sdimdef AddrMode_i12 : AddrMode<16>; 109195340Sed 110195340Sed// Instruction size. 111195340Sedclass SizeFlagVal<bits<3> val> { 112195340Sed bits<3> Value = val; 113195340Sed} 114195340Seddef SizeInvalid : SizeFlagVal<0>; // Unset. 115195340Seddef SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 116195340Seddef Size8Bytes : SizeFlagVal<2>; 117195340Seddef Size4Bytes : SizeFlagVal<3>; 118195340Seddef Size2Bytes : SizeFlagVal<4>; 119195340Sed 120195340Sed// Load / store index mode. 121195340Sedclass IndexMode<bits<2> val> { 122195340Sed bits<2> Value = val; 123195340Sed} 124195340Seddef IndexModeNone : IndexMode<0>; 125195340Seddef IndexModePre : IndexMode<1>; 126195340Seddef IndexModePost : IndexMode<2>; 127205218Srdivackydef IndexModeUpd : IndexMode<3>; 128195340Sed 129198892Srdivacky// Instruction execution domain. 130219077Sdimclass Domain<bits<3> val> { 131219077Sdim bits<3> Value = val; 132198892Srdivacky} 133198892Srdivackydef GenericDomain : Domain<0>; 134198892Srdivackydef VFPDomain : Domain<1>; // Instructions in VFP domain only 135198892Srdivackydef NeonDomain : Domain<2>; // Instructions in Neon domain only 136198892Srdivackydef VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 137219077Sdimdef VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 138198892Srdivacky 139195340Sed//===----------------------------------------------------------------------===// 140198090Srdivacky// ARM special operands. 141198090Srdivacky// 142198090Srdivacky 143212904Sdimdef CondCodeOperand : AsmOperandClass { 144212904Sdim let Name = "CondCode"; 145212904Sdim let SuperClasses = []; 146212904Sdim} 147212904Sdim 148218893Sdimdef CCOutOperand : AsmOperandClass { 149218893Sdim let Name = "CCOut"; 150218893Sdim let SuperClasses = []; 151218893Sdim} 152218893Sdim 153218893Sdimdef MemBarrierOptOperand : AsmOperandClass { 154218893Sdim let Name = "MemBarrierOpt"; 155218893Sdim let SuperClasses = []; 156218893Sdim let ParserMethod = "tryParseMemBarrierOptOperand"; 157218893Sdim} 158218893Sdim 159218893Sdimdef ProcIFlagsOperand : AsmOperandClass { 160218893Sdim let Name = "ProcIFlags"; 161218893Sdim let SuperClasses = []; 162218893Sdim let ParserMethod = "tryParseProcIFlagsOperand"; 163218893Sdim} 164218893Sdim 165218893Sdimdef MSRMaskOperand : AsmOperandClass { 166218893Sdim let Name = "MSRMask"; 167218893Sdim let SuperClasses = []; 168218893Sdim let ParserMethod = "tryParseMSRMaskOperand"; 169218893Sdim} 170218893Sdim 171218893Sdim// ARM imod and iflag operands, used only by the CPS instruction. 172218893Sdimdef imod_op : Operand<i32> { 173218893Sdim let PrintMethod = "printCPSIMod"; 174218893Sdim} 175218893Sdim 176218893Sdimdef iflags_op : Operand<i32> { 177218893Sdim let PrintMethod = "printCPSIFlag"; 178218893Sdim let ParserMatchClass = ProcIFlagsOperand; 179218893Sdim} 180218893Sdim 181198090Srdivacky// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 182198090Srdivacky// register whose default is 0 (no register). 183198090Srdivackydef pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 184198090Srdivacky (ops (i32 14), (i32 zero_reg))> { 185198090Srdivacky let PrintMethod = "printPredicateOperand"; 186212904Sdim let ParserMatchClass = CondCodeOperand; 187198090Srdivacky} 188198090Srdivacky 189198090Srdivacky// Conditional code result for instructions whose 's' bit is set, e.g. subs. 190198090Srdivackydef cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 191218893Sdim let EncoderMethod = "getCCOutOpValue"; 192198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 193218893Sdim let ParserMatchClass = CCOutOperand; 194198090Srdivacky} 195198090Srdivacky 196198090Srdivacky// Same as cc_out except it defaults to setting CPSR. 197198090Srdivackydef s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 198218893Sdim let EncoderMethod = "getCCOutOpValue"; 199198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 200218893Sdim let ParserMatchClass = CCOutOperand; 201198090Srdivacky} 202198090Srdivacky 203205218Srdivacky// ARM special operands for disassembly only. 204205218Srdivacky// 205218893Sdimdef setend_op : Operand<i32> { 206218893Sdim let PrintMethod = "printSetendOperand"; 207218893Sdim} 208205218Srdivacky 209205218Srdivackydef cps_opt : Operand<i32> { 210205218Srdivacky let PrintMethod = "printCPSOptionOperand"; 211205218Srdivacky} 212205218Srdivacky 213205218Srdivackydef msr_mask : Operand<i32> { 214205218Srdivacky let PrintMethod = "printMSRMaskOperand"; 215218893Sdim let ParserMatchClass = MSRMaskOperand; 216205218Srdivacky} 217205218Srdivacky 218205218Srdivacky// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. 219205218Srdivacky// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. 220205218Srdivackydef neg_zero : Operand<i32> { 221205218Srdivacky let PrintMethod = "printNegZeroOperand"; 222205218Srdivacky} 223205218Srdivacky 224198090Srdivacky//===----------------------------------------------------------------------===// 225193323Sed// ARM Instruction templates. 226193323Sed// 227193323Sed 228201360Srdivackyclass InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 229201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 230193323Sed : Instruction { 231193323Sed let Namespace = "ARM"; 232193323Sed 233193323Sed AddrMode AM = am; 234193323Sed SizeFlagVal SZ = sz; 235193323Sed IndexMode IM = im; 236193323Sed bits<2> IndexModeBits = IM.Value; 237193323Sed Format F = f; 238205407Srdivacky bits<6> Form = F.Value; 239198892Srdivacky Domain D = d; 240193323Sed bit isUnaryDataProc = 0; 241198090Srdivacky bit canXformTo16Bit = 0; 242206083Srdivacky 243218893Sdim // If this is a pseudo instruction, mark it isCodeGenOnly. 244218893Sdim let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 245218893Sdim 246206274Srdivacky // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h. 247218893Sdim let TSFlags{4-0} = AM.Value; 248218893Sdim let TSFlags{7-5} = SZ.Value; 249218893Sdim let TSFlags{9-8} = IndexModeBits; 250218893Sdim let TSFlags{15-10} = Form; 251218893Sdim let TSFlags{16} = isUnaryDataProc; 252218893Sdim let TSFlags{17} = canXformTo16Bit; 253219077Sdim let TSFlags{20-18} = D.Value; 254206274Srdivacky 255193323Sed let Constraints = cstr; 256198090Srdivacky let Itinerary = itin; 257193323Sed} 258193323Sed 259201360Srdivackyclass Encoding { 260201360Srdivacky field bits<32> Inst; 261201360Srdivacky} 262201360Srdivacky 263201360Srdivackyclass InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 264201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 265201360Srdivacky : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 266201360Srdivacky 267201360Srdivacky// This Encoding-less class is used by Thumb1 to specify the encoding bits later 268201360Srdivacky// on by adding flavors to specific instructions. 269201360Srdivackyclass InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 270201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 271201360Srdivacky : InstTemplate<am, sz, im, f, d, cstr, itin>; 272201360Srdivacky 273218893Sdimclass PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 274218893Sdim // FIXME: This really should derive from InstTemplate instead, as pseudos 275218893Sdim // don't need encoding information. TableGen doesn't like that 276218893Sdim // currently. Need to figure out why and fix it. 277206083Srdivacky : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 278198892Srdivacky "", itin> { 279193323Sed let OutOperandList = oops; 280193323Sed let InOperandList = iops; 281193323Sed let Pattern = pattern; 282193323Sed} 283193323Sed 284218893Sdim// PseudoInst that's ARM-mode only. 285218893Sdimclass ARMPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 286218893Sdim list<dag> pattern> 287218893Sdim : PseudoInst<oops, iops, itin, pattern> { 288218893Sdim let SZ = sz; 289218893Sdim list<Predicate> Predicates = [IsARM]; 290218893Sdim} 291218893Sdim 292218893Sdim// PseudoInst that's Thumb-mode only. 293218893Sdimclass tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 294218893Sdim list<dag> pattern> 295218893Sdim : PseudoInst<oops, iops, itin, pattern> { 296218893Sdim let SZ = sz; 297218893Sdim list<Predicate> Predicates = [IsThumb]; 298218893Sdim} 299218893Sdim 300218893Sdim// PseudoInst that's Thumb2-mode only. 301218893Sdimclass t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 302218893Sdim list<dag> pattern> 303218893Sdim : PseudoInst<oops, iops, itin, pattern> { 304218893Sdim let SZ = sz; 305218893Sdim list<Predicate> Predicates = [IsThumb2]; 306218893Sdim} 307193323Sed// Almost all ARM instructions are predicable. 308193323Sedclass I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 309206083Srdivacky IndexMode im, Format f, InstrItinClass itin, 310198090Srdivacky string opc, string asm, string cstr, 311193323Sed list<dag> pattern> 312198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 313218893Sdim bits<4> p; 314218893Sdim let Inst{31-28} = p; 315193323Sed let OutOperandList = oops; 316205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 317218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 318193323Sed let Pattern = pattern; 319193323Sed list<Predicate> Predicates = [IsARM]; 320193323Sed} 321212904Sdim 322200581Srdivacky// A few are not predicable 323200581Srdivackyclass InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 324206083Srdivacky IndexMode im, Format f, InstrItinClass itin, 325206083Srdivacky string opc, string asm, string cstr, 326206083Srdivacky list<dag> pattern> 327200581Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 328200581Srdivacky let OutOperandList = oops; 329200581Srdivacky let InOperandList = iops; 330208599Srdivacky let AsmString = !strconcat(opc, asm); 331200581Srdivacky let Pattern = pattern; 332200581Srdivacky let isPredicable = 0; 333200581Srdivacky list<Predicate> Predicates = [IsARM]; 334200581Srdivacky} 335193323Sed 336212904Sdim// Same as I except it can optionally modify CPSR. Note it's modeled as an input 337212904Sdim// operand since by default it's a zero register. It will become an implicit def 338212904Sdim// once it's "flipped". 339193323Sedclass sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 340198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 341198090Srdivacky string opc, string asm, string cstr, 342193323Sed list<dag> pattern> 343198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 344218893Sdim bits<4> p; // Predicate operand 345218893Sdim bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 346218893Sdim let Inst{31-28} = p; 347218893Sdim let Inst{20} = s; 348218893Sdim 349193323Sed let OutOperandList = oops; 350205407Srdivacky let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 351218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 352193323Sed let Pattern = pattern; 353193323Sed list<Predicate> Predicates = [IsARM]; 354193323Sed} 355193323Sed 356193323Sed// Special cases 357193323Sedclass XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 358198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 359198090Srdivacky string asm, string cstr, list<dag> pattern> 360198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 361193323Sed let OutOperandList = oops; 362193323Sed let InOperandList = iops; 363208599Srdivacky let AsmString = asm; 364193323Sed let Pattern = pattern; 365193323Sed list<Predicate> Predicates = [IsARM]; 366193323Sed} 367193323Sed 368198090Srdivackyclass AI<dag oops, dag iops, Format f, InstrItinClass itin, 369198090Srdivacky string opc, string asm, list<dag> pattern> 370198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 371198090Srdivacky opc, asm, "", pattern>; 372198090Srdivackyclass AsI<dag oops, dag iops, Format f, InstrItinClass itin, 373198090Srdivacky string opc, string asm, list<dag> pattern> 374198090Srdivacky : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 375198090Srdivacky opc, asm, "", pattern>; 376198090Srdivackyclass AXI<dag oops, dag iops, Format f, InstrItinClass itin, 377193323Sed string asm, list<dag> pattern> 378198090Srdivacky : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 379193323Sed asm, "", pattern>; 380200581Srdivackyclass AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 381206083Srdivacky string opc, string asm, list<dag> pattern> 382200581Srdivacky : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 383206083Srdivacky opc, asm, "", pattern>; 384193323Sed 385193323Sed// Ctrl flow instructions 386198090Srdivackyclass ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 387198090Srdivacky string opc, string asm, list<dag> pattern> 388198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 389198090Srdivacky opc, asm, "", pattern> { 390193323Sed let Inst{27-24} = opcod; 391193323Sed} 392198090Srdivackyclass ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 393198090Srdivacky string asm, list<dag> pattern> 394198090Srdivacky : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 395198090Srdivacky asm, "", pattern> { 396193323Sed let Inst{27-24} = opcod; 397193323Sed} 398193323Sed 399193323Sed// BR_JT instructions 400198090Srdivackyclass JTI<dag oops, dag iops, InstrItinClass itin, 401198090Srdivacky string asm, list<dag> pattern> 402198090Srdivacky : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 403193323Sed asm, "", pattern>; 404193323Sed 405200581Srdivacky// Atomic load/store instructions 406200581Srdivackyclass AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 407200581Srdivacky string opc, string asm, list<dag> pattern> 408200581Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 409200581Srdivacky opc, asm, "", pattern> { 410218893Sdim bits<4> Rt; 411218893Sdim bits<4> Rn; 412200581Srdivacky let Inst{27-23} = 0b00011; 413200581Srdivacky let Inst{22-21} = opcod; 414212904Sdim let Inst{20} = 1; 415218893Sdim let Inst{19-16} = Rn; 416218893Sdim let Inst{15-12} = Rt; 417200581Srdivacky let Inst{11-0} = 0b111110011111; 418200581Srdivacky} 419200581Srdivackyclass AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 420200581Srdivacky string opc, string asm, list<dag> pattern> 421200581Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 422200581Srdivacky opc, asm, "", pattern> { 423218893Sdim bits<4> Rd; 424218893Sdim bits<4> Rt; 425218893Sdim bits<4> Rn; 426200581Srdivacky let Inst{27-23} = 0b00011; 427200581Srdivacky let Inst{22-21} = opcod; 428212904Sdim let Inst{20} = 0; 429218893Sdim let Inst{19-16} = Rn; 430218893Sdim let Inst{15-12} = Rd; 431200581Srdivacky let Inst{11-4} = 0b11111001; 432218893Sdim let Inst{3-0} = Rt; 433200581Srdivacky} 434218893Sdimclass AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 435218893Sdim : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> { 436218893Sdim bits<4> Rt; 437218893Sdim bits<4> Rt2; 438218893Sdim bits<4> Rn; 439218893Sdim let Inst{27-23} = 0b00010; 440218893Sdim let Inst{22} = b; 441218893Sdim let Inst{21-20} = 0b00; 442218893Sdim let Inst{19-16} = Rn; 443218893Sdim let Inst{15-12} = Rt; 444218893Sdim let Inst{11-4} = 0b00001001; 445218893Sdim let Inst{3-0} = Rt2; 446218893Sdim} 447200581Srdivacky 448193323Sed// addrmode1 instructions 449198090Srdivackyclass AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 450198090Srdivacky string opc, string asm, list<dag> pattern> 451198090Srdivacky : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 452198090Srdivacky opc, asm, "", pattern> { 453193323Sed let Inst{24-21} = opcod; 454212904Sdim let Inst{27-26} = 0b00; 455193323Sed} 456198090Srdivackyclass AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 457198090Srdivacky string opc, string asm, list<dag> pattern> 458198090Srdivacky : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 459198090Srdivacky opc, asm, "", pattern> { 460193323Sed let Inst{24-21} = opcod; 461212904Sdim let Inst{27-26} = 0b00; 462193323Sed} 463198090Srdivackyclass AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 464198090Srdivacky string asm, list<dag> pattern> 465198090Srdivacky : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 466198090Srdivacky asm, "", pattern> { 467193323Sed let Inst{24-21} = opcod; 468212904Sdim let Inst{27-26} = 0b00; 469193323Sed} 470193323Sed 471193323Sed// loads 472193323Sed 473218893Sdim// LDR/LDRB/STR/STRB/... 474218893Sdimclass AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 475218893Sdim Format f, InstrItinClass itin, string opc, string asm, 476218893Sdim list<dag> pattern> 477218893Sdim : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm, 478218893Sdim "", pattern> { 479218893Sdim let Inst{27-25} = op; 480218893Sdim let Inst{24} = 1; // 24 == P 481218893Sdim // 23 == U 482218893Sdim let Inst{22} = isByte; 483218893Sdim let Inst{21} = 0; // 21 == W 484218893Sdim let Inst{20} = isLd; 485193323Sed} 486218893Sdim// Indexed load/stores 487218893Sdimclass AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 488218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 489218893Sdim string asm, string cstr, list<dag> pattern> 490218893Sdim : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin, 491198090Srdivacky opc, asm, cstr, pattern> { 492218893Sdim bits<4> Rt; 493212904Sdim let Inst{27-26} = 0b01; 494218893Sdim let Inst{24} = isPre; // P bit 495218893Sdim let Inst{22} = isByte; // B bit 496218893Sdim let Inst{21} = isPre; // W bit 497218893Sdim let Inst{20} = isLd; // L bit 498218893Sdim let Inst{15-12} = Rt; 499193323Sed} 500218893Sdimclass AI2stridx<bit isByte, bit isPre, dag oops, dag iops, 501218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 502218893Sdim string asm, string cstr, list<dag> pattern> 503218893Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 504218893Sdim pattern> { 505218893Sdim // AM2 store w/ two operands: (GPR, am2offset) 506218893Sdim // {13} 1 == Rm, 0 == imm12 507218893Sdim // {12} isAdd 508218893Sdim // {11-0} imm12/Rm 509218893Sdim bits<14> offset; 510218893Sdim bits<4> Rn; 511218893Sdim let Inst{25} = offset{13}; 512218893Sdim let Inst{23} = offset{12}; 513218893Sdim let Inst{19-16} = Rn; 514218893Sdim let Inst{11-0} = offset{11-0}; 515193323Sed} 516193323Sed 517193323Sed// addrmode3 instructions 518218893Sdimclass AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 519218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 520198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 521198090Srdivacky opc, asm, "", pattern> { 522218893Sdim bits<14> addr; 523218893Sdim bits<4> Rt; 524198090Srdivacky let Inst{27-25} = 0b000; 525218893Sdim let Inst{24} = 1; // P bit 526218893Sdim let Inst{23} = addr{8}; // U bit 527218893Sdim let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 528218893Sdim let Inst{21} = 0; // W bit 529218893Sdim let Inst{20} = op20; // L bit 530218893Sdim let Inst{19-16} = addr{12-9}; // Rn 531218893Sdim let Inst{15-12} = Rt; // Rt 532218893Sdim let Inst{11-8} = addr{7-4}; // imm7_4/zero 533218893Sdim let Inst{7-4} = op; 534218893Sdim let Inst{3-0} = addr{3-0}; // imm3_0/Rm 535193323Sed} 536218893Sdim 537218893Sdimclass AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, 538218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 539218893Sdim string asm, string cstr, list<dag> pattern> 540218893Sdim : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin, 541218893Sdim opc, asm, cstr, pattern> { 542218893Sdim bits<4> Rt; 543198090Srdivacky let Inst{27-25} = 0b000; 544218893Sdim let Inst{24} = isPre; // P bit 545218893Sdim let Inst{21} = isPre; // W bit 546218893Sdim let Inst{20} = op20; // L bit 547218893Sdim let Inst{15-12} = Rt; // Rt 548218893Sdim let Inst{7-4} = op; 549193323Sed} 550218893Sdimclass AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops, 551218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 552218893Sdim string asm, string cstr, list<dag> pattern> 553218893Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 554218893Sdim pattern> { 555218893Sdim // AM3 store w/ two operands: (GPR, am3offset) 556218893Sdim bits<14> offset; 557218893Sdim bits<4> Rt; 558218893Sdim bits<4> Rn; 559198090Srdivacky let Inst{27-25} = 0b000; 560218893Sdim let Inst{23} = offset{8}; 561218893Sdim let Inst{22} = offset{9}; 562218893Sdim let Inst{19-16} = Rn; 563218893Sdim let Inst{15-12} = Rt; // Rt 564218893Sdim let Inst{11-8} = offset{7-4}; // imm7_4/zero 565218893Sdim let Inst{7-4} = op; 566218893Sdim let Inst{3-0} = offset{3-0}; // imm3_0/Rm 567193323Sed} 568193323Sed 569193323Sed// stores 570218893Sdimclass AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 571198090Srdivacky string opc, string asm, list<dag> pattern> 572198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 573198090Srdivacky opc, asm, "", pattern> { 574218893Sdim bits<14> addr; 575218893Sdim bits<4> Rt; 576198090Srdivacky let Inst{27-25} = 0b000; 577218893Sdim let Inst{24} = 1; // P bit 578218893Sdim let Inst{23} = addr{8}; // U bit 579218893Sdim let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 580218893Sdim let Inst{21} = 0; // W bit 581218893Sdim let Inst{20} = 0; // L bit 582218893Sdim let Inst{19-16} = addr{12-9}; // Rn 583218893Sdim let Inst{15-12} = Rt; // Rt 584218893Sdim let Inst{11-8} = addr{7-4}; // imm7_4/zero 585218893Sdim let Inst{7-4} = op; 586218893Sdim let Inst{3-0} = addr{3-0}; // imm3_0/Rm 587193323Sed} 588193323Sed 589193323Sed// Pre-indexed stores 590198090Srdivackyclass AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 591198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 592198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 593198090Srdivacky opc, asm, cstr, pattern> { 594193323Sed let Inst{4} = 1; 595193323Sed let Inst{5} = 1; // H bit 596193323Sed let Inst{6} = 0; // S bit 597193323Sed let Inst{7} = 1; 598193323Sed let Inst{20} = 0; // L bit 599193323Sed let Inst{21} = 1; // W bit 600193323Sed let Inst{24} = 1; // P bit 601198090Srdivacky let Inst{27-25} = 0b000; 602193323Sed} 603204642Srdivackyclass AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin, 604204642Srdivacky string opc, string asm, string cstr, list<dag> pattern> 605204642Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 606204642Srdivacky opc, asm, cstr, pattern> { 607204642Srdivacky let Inst{4} = 1; 608204642Srdivacky let Inst{5} = 1; // H bit 609204642Srdivacky let Inst{6} = 1; // S bit 610204642Srdivacky let Inst{7} = 1; 611204642Srdivacky let Inst{20} = 0; // L bit 612204642Srdivacky let Inst{21} = 1; // W bit 613204642Srdivacky let Inst{24} = 1; // P bit 614204642Srdivacky let Inst{27-25} = 0b000; 615204642Srdivacky} 616193323Sed 617193323Sed// Post-indexed stores 618198090Srdivackyclass AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 619198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 620198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 621198090Srdivacky opc, asm, cstr,pattern> { 622193323Sed let Inst{4} = 1; 623193323Sed let Inst{5} = 1; // H bit 624193323Sed let Inst{6} = 0; // S bit 625193323Sed let Inst{7} = 1; 626193323Sed let Inst{20} = 0; // L bit 627204642Srdivacky let Inst{21} = 0; // W bit 628193323Sed let Inst{24} = 0; // P bit 629198090Srdivacky let Inst{27-25} = 0b000; 630193323Sed} 631204642Srdivackyclass AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin, 632204642Srdivacky string opc, string asm, string cstr, list<dag> pattern> 633204642Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 634204642Srdivacky opc, asm, cstr, pattern> { 635204642Srdivacky let Inst{4} = 1; 636204642Srdivacky let Inst{5} = 1; // H bit 637204642Srdivacky let Inst{6} = 1; // S bit 638204642Srdivacky let Inst{7} = 1; 639204642Srdivacky let Inst{20} = 0; // L bit 640204642Srdivacky let Inst{21} = 0; // W bit 641204642Srdivacky let Inst{24} = 0; // P bit 642204642Srdivacky let Inst{27-25} = 0b000; 643204642Srdivacky} 644193323Sed 645193323Sed// addrmode4 instructions 646218893Sdimclass AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 647218893Sdim string asm, string cstr, list<dag> pattern> 648218893Sdim : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> { 649218893Sdim bits<4> p; 650218893Sdim bits<16> regs; 651218893Sdim bits<4> Rn; 652218893Sdim let Inst{31-28} = p; 653193323Sed let Inst{27-25} = 0b100; 654193323Sed let Inst{22} = 0; // S bit 655218893Sdim let Inst{19-16} = Rn; 656218893Sdim let Inst{15-0} = regs; 657193323Sed} 658193323Sed 659193323Sed// Unsigned multiply, multiply-accumulate instructions. 660198090Srdivackyclass AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 661198090Srdivacky string opc, string asm, list<dag> pattern> 662198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 663198090Srdivacky opc, asm, "", pattern> { 664193323Sed let Inst{7-4} = 0b1001; 665193323Sed let Inst{20} = 0; // S bit 666193323Sed let Inst{27-21} = opcod; 667193323Sed} 668198090Srdivackyclass AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 669198090Srdivacky string opc, string asm, list<dag> pattern> 670198090Srdivacky : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 671198090Srdivacky opc, asm, "", pattern> { 672193323Sed let Inst{7-4} = 0b1001; 673193323Sed let Inst{27-21} = opcod; 674193323Sed} 675193323Sed 676193323Sed// Most significant word multiply 677218893Sdimclass AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 678218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 679198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 680198090Srdivacky opc, asm, "", pattern> { 681218893Sdim bits<4> Rd; 682218893Sdim bits<4> Rn; 683218893Sdim bits<4> Rm; 684218893Sdim let Inst{7-4} = opc7_4; 685193323Sed let Inst{20} = 1; 686193323Sed let Inst{27-21} = opcod; 687218893Sdim let Inst{19-16} = Rd; 688218893Sdim let Inst{11-8} = Rm; 689218893Sdim let Inst{3-0} = Rn; 690193323Sed} 691218893Sdim// MSW multiple w/ Ra operand 692218893Sdimclass AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 693218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 694218893Sdim : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 695218893Sdim bits<4> Ra; 696218893Sdim let Inst{15-12} = Ra; 697218893Sdim} 698193323Sed 699193323Sed// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 700218893Sdimclass AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 701218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 702198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 703198090Srdivacky opc, asm, "", pattern> { 704218893Sdim bits<4> Rn; 705218893Sdim bits<4> Rm; 706193323Sed let Inst{4} = 0; 707193323Sed let Inst{7} = 1; 708193323Sed let Inst{20} = 0; 709193323Sed let Inst{27-21} = opcod; 710218893Sdim let Inst{6-5} = bit6_5; 711218893Sdim let Inst{11-8} = Rm; 712218893Sdim let Inst{3-0} = Rn; 713193323Sed} 714218893Sdimclass AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 715218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 716218893Sdim : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 717218893Sdim bits<4> Rd; 718218893Sdim let Inst{19-16} = Rd; 719218893Sdim} 720193323Sed 721218893Sdim// AMulxyI with Ra operand 722218893Sdimclass AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 723218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 724218893Sdim : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 725218893Sdim bits<4> Ra; 726218893Sdim let Inst{15-12} = Ra; 727218893Sdim} 728218893Sdim// SMLAL* 729218893Sdimclass AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 730218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 731218893Sdim : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 732218893Sdim bits<4> RdLo; 733218893Sdim bits<4> RdHi; 734218893Sdim let Inst{19-16} = RdHi; 735218893Sdim let Inst{15-12} = RdLo; 736218893Sdim} 737218893Sdim 738193323Sed// Extend instructions. 739198090Srdivackyclass AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 740198090Srdivacky string opc, string asm, list<dag> pattern> 741198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 742198090Srdivacky opc, asm, "", pattern> { 743218893Sdim // All AExtI instructions have Rd and Rm register operands. 744218893Sdim bits<4> Rd; 745218893Sdim bits<4> Rm; 746218893Sdim let Inst{15-12} = Rd; 747218893Sdim let Inst{3-0} = Rm; 748193323Sed let Inst{7-4} = 0b0111; 749218893Sdim let Inst{9-8} = 0b00; 750193323Sed let Inst{27-20} = opcod; 751193323Sed} 752193323Sed 753193323Sed// Misc Arithmetic instructions. 754218893Sdimclass AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 755218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 756198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 757198090Srdivacky opc, asm, "", pattern> { 758218893Sdim bits<4> Rd; 759218893Sdim bits<4> Rm; 760193323Sed let Inst{27-20} = opcod; 761218893Sdim let Inst{19-16} = 0b1111; 762218893Sdim let Inst{15-12} = Rd; 763218893Sdim let Inst{11-8} = 0b1111; 764218893Sdim let Inst{7-4} = opc7_4; 765218893Sdim let Inst{3-0} = Rm; 766193323Sed} 767193323Sed 768218893Sdim// PKH instructions 769218893Sdimclass APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 770218893Sdim string opc, string asm, list<dag> pattern> 771218893Sdim : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 772218893Sdim opc, asm, "", pattern> { 773218893Sdim bits<4> Rd; 774218893Sdim bits<4> Rn; 775218893Sdim bits<4> Rm; 776218893Sdim bits<8> sh; 777218893Sdim let Inst{27-20} = opcod; 778218893Sdim let Inst{19-16} = Rn; 779218893Sdim let Inst{15-12} = Rd; 780218893Sdim let Inst{11-7} = sh{7-3}; 781218893Sdim let Inst{6} = tb; 782218893Sdim let Inst{5-4} = 0b01; 783218893Sdim let Inst{3-0} = Rm; 784218893Sdim} 785218893Sdim 786193323Sed//===----------------------------------------------------------------------===// 787193323Sed 788193323Sed// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 789193323Sedclass ARMPat<dag pattern, dag result> : Pat<pattern, result> { 790193323Sed list<Predicate> Predicates = [IsARM]; 791193323Sed} 792193323Sedclass ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 793193323Sed list<Predicate> Predicates = [IsARM, HasV5TE]; 794193323Sed} 795193323Sedclass ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 796193323Sed list<Predicate> Predicates = [IsARM, HasV6]; 797193323Sed} 798193323Sed 799193323Sed//===----------------------------------------------------------------------===// 800193323Sed// Thumb Instruction Format Definitions. 801193323Sed// 802193323Sed 803198090Srdivackyclass ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 804198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 805201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 806198090Srdivacky let OutOperandList = oops; 807198090Srdivacky let InOperandList = iops; 808208599Srdivacky let AsmString = asm; 809193323Sed let Pattern = pattern; 810193323Sed list<Predicate> Predicates = [IsThumb]; 811193323Sed} 812193323Sed 813218893Sdim// TI - Thumb instruction. 814198090Srdivackyclass TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 815198090Srdivacky : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 816193323Sed 817198090Srdivacky// Two-address instructions 818206083Srdivackyclass TIt<dag oops, dag iops, InstrItinClass itin, string asm, 819206083Srdivacky list<dag> pattern> 820206083Srdivacky : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", 821206083Srdivacky pattern>; 822193323Sed 823201360Srdivacky// tBL, tBX 32-bit instructions 824201360Srdivackyclass TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 825206083Srdivacky dag oops, dag iops, InstrItinClass itin, string asm, 826206083Srdivacky list<dag> pattern> 827206083Srdivacky : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, 828206083Srdivacky Encoding { 829201360Srdivacky let Inst{31-27} = opcod1; 830201360Srdivacky let Inst{15-14} = opcod2; 831212904Sdim let Inst{12} = opcod3; 832201360Srdivacky} 833198090Srdivacky 834218893Sdim// Move to/from coprocessor instructions 835218893Sdimclass T1Cop<dag oops, dag iops, string asm, list<dag> pattern> 836218893Sdim : ThumbI<oops, iops, AddrModeNone, Size4Bytes, NoItinerary, asm, "", pattern>, 837218893Sdim Encoding, Requires<[IsThumb, HasV6]> { 838218893Sdim let Inst{31-28} = 0b1110; 839218893Sdim} 840218893Sdim 841193323Sed// BR_JT instructions 842206083Srdivackyclass TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 843206083Srdivacky list<dag> pattern> 844198090Srdivacky : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 845193323Sed 846198090Srdivacky// Thumb1 only 847198090Srdivackyclass Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 848198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 849201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 850198090Srdivacky let OutOperandList = oops; 851198090Srdivacky let InOperandList = iops; 852208599Srdivacky let AsmString = asm; 853198090Srdivacky let Pattern = pattern; 854218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 855194710Sed} 856193323Sed 857198090Srdivackyclass T1I<dag oops, dag iops, InstrItinClass itin, 858198090Srdivacky string asm, list<dag> pattern> 859198090Srdivacky : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 860198090Srdivackyclass T1Ix2<dag oops, dag iops, InstrItinClass itin, 861198090Srdivacky string asm, list<dag> pattern> 862198090Srdivacky : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 863194710Sed 864198090Srdivacky// Two-address instructions 865198090Srdivackyclass T1It<dag oops, dag iops, InstrItinClass itin, 866205218Srdivacky string asm, string cstr, list<dag> pattern> 867206083Srdivacky : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 868205218Srdivacky asm, cstr, pattern>; 869198090Srdivacky 870198090Srdivacky// Thumb1 instruction that can either be predicated or set CPSR. 871198090Srdivackyclass Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 872198090Srdivacky InstrItinClass itin, 873198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 874201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 875205407Srdivacky let OutOperandList = !con(oops, (outs s_cc_out:$s)); 876205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 877218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 878194754Sed let Pattern = pattern; 879218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 880195098Sed} 881195098Sed 882198090Srdivackyclass T1sI<dag oops, dag iops, InstrItinClass itin, 883198090Srdivacky string opc, string asm, list<dag> pattern> 884198090Srdivacky : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 885195098Sed 886195098Sed// Two-address instructions 887198090Srdivackyclass T1sIt<dag oops, dag iops, InstrItinClass itin, 888198090Srdivacky string opc, string asm, list<dag> pattern> 889198090Srdivacky : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 890218893Sdim "$Rn = $Rdn", pattern>; 891195098Sed 892198090Srdivacky// Thumb1 instruction that can be predicated. 893198090Srdivackyclass Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 894198090Srdivacky InstrItinClass itin, 895198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 896201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 897198090Srdivacky let OutOperandList = oops; 898205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 899218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 900198090Srdivacky let Pattern = pattern; 901218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 902195098Sed} 903195098Sed 904198090Srdivackyclass T1pI<dag oops, dag iops, InstrItinClass itin, 905198090Srdivacky string opc, string asm, list<dag> pattern> 906198090Srdivacky : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 907198090Srdivacky 908198090Srdivacky// Two-address instructions 909198090Srdivackyclass T1pIt<dag oops, dag iops, InstrItinClass itin, 910198090Srdivacky string opc, string asm, list<dag> pattern> 911198090Srdivacky : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 912218893Sdim "$Rn = $Rdn", pattern>; 913198090Srdivacky 914206083Srdivackyclass T1pIs<dag oops, dag iops, 915198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 916198090Srdivacky : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 917198090Srdivacky 918201360Srdivackyclass Encoding16 : Encoding { 919201360Srdivacky let Inst{31-16} = 0x0000; 920201360Srdivacky} 921201360Srdivacky 922201360Srdivacky// A6.2 16-bit Thumb instruction encoding 923201360Srdivackyclass T1Encoding<bits<6> opcode> : Encoding16 { 924201360Srdivacky let Inst{15-10} = opcode; 925201360Srdivacky} 926201360Srdivacky 927201360Srdivacky// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 928201360Srdivackyclass T1General<bits<5> opcode> : Encoding16 { 929201360Srdivacky let Inst{15-14} = 0b00; 930201360Srdivacky let Inst{13-9} = opcode; 931201360Srdivacky} 932201360Srdivacky 933201360Srdivacky// A6.2.2 Data-processing encoding. 934201360Srdivackyclass T1DataProcessing<bits<4> opcode> : Encoding16 { 935201360Srdivacky let Inst{15-10} = 0b010000; 936201360Srdivacky let Inst{9-6} = opcode; 937201360Srdivacky} 938201360Srdivacky 939201360Srdivacky// A6.2.3 Special data instructions and branch and exchange encoding. 940201360Srdivackyclass T1Special<bits<4> opcode> : Encoding16 { 941201360Srdivacky let Inst{15-10} = 0b010001; 942218893Sdim let Inst{9-6} = opcode; 943201360Srdivacky} 944201360Srdivacky 945201360Srdivacky// A6.2.4 Load/store single data item encoding. 946201360Srdivackyclass T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 947201360Srdivacky let Inst{15-12} = opA; 948212904Sdim let Inst{11-9} = opB; 949201360Srdivacky} 950212904Sdimclass T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 951201360Srdivacky 952218893Sdim// Helper classes to encode Thumb1 loads and stores. For immediates, the 953218893Sdim// following bits are used for "opA" (see A6.2.4): 954218893Sdim// 955218893Sdim// 0b0110 => Immediate, 4 bytes 956218893Sdim// 0b1000 => Immediate, 2 bytes 957218893Sdim// 0b0111 => Immediate, 1 byte 958218893Sdimclass T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 959218893Sdim InstrItinClass itin, string opc, string asm, 960218893Sdim list<dag> pattern> 961218893Sdim : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>, 962218893Sdim T1LoadStore<0b0101, opcode> { 963218893Sdim bits<3> Rt; 964218893Sdim bits<8> addr; 965218893Sdim let Inst{8-6} = addr{5-3}; // Rm 966218893Sdim let Inst{5-3} = addr{2-0}; // Rn 967218893Sdim let Inst{2-0} = Rt; 968218893Sdim} 969218893Sdimclass T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 970218893Sdim InstrItinClass itin, string opc, string asm, 971218893Sdim list<dag> pattern> 972218893Sdim : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>, 973218893Sdim T1LoadStore<opA, {opB,?,?}> { 974218893Sdim bits<3> Rt; 975218893Sdim bits<8> addr; 976218893Sdim let Inst{10-6} = addr{7-3}; // imm5 977218893Sdim let Inst{5-3} = addr{2-0}; // Rn 978218893Sdim let Inst{2-0} = Rt; 979218893Sdim} 980218893Sdim 981201360Srdivacky// A6.2.5 Miscellaneous 16-bit instructions encoding. 982201360Srdivackyclass T1Misc<bits<7> opcode> : Encoding16 { 983201360Srdivacky let Inst{15-12} = 0b1011; 984201360Srdivacky let Inst{11-5} = opcode; 985201360Srdivacky} 986201360Srdivacky 987195098Sed// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 988195098Sedclass Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 989198090Srdivacky InstrItinClass itin, 990195098Sed string opc, string asm, string cstr, list<dag> pattern> 991198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 992195098Sed let OutOperandList = oops; 993205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 994218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 995195098Sed let Pattern = pattern; 996195340Sed list<Predicate> Predicates = [IsThumb2]; 997194754Sed} 998194754Sed 999212904Sdim// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 1000212904Sdim// input operand since by default it's a zero register. It will become an 1001212904Sdim// implicit def once it's "flipped". 1002218893Sdim// 1003195098Sed// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1004195098Sed// more consistent. 1005195098Sedclass Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1006198090Srdivacky InstrItinClass itin, 1007195098Sed string opc, string asm, string cstr, list<dag> pattern> 1008198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1009218893Sdim bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 1010218893Sdim let Inst{20} = s; 1011218893Sdim 1012195098Sed let OutOperandList = oops; 1013205407Srdivacky let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1014218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 1015195098Sed let Pattern = pattern; 1016195340Sed list<Predicate> Predicates = [IsThumb2]; 1017195098Sed} 1018194754Sed 1019195098Sed// Special cases 1020195098Sedclass Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1021198090Srdivacky InstrItinClass itin, 1022195098Sed string asm, string cstr, list<dag> pattern> 1023198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1024195098Sed let OutOperandList = oops; 1025195098Sed let InOperandList = iops; 1026208599Srdivacky let AsmString = asm; 1027195098Sed let Pattern = pattern; 1028195340Sed list<Predicate> Predicates = [IsThumb2]; 1029194754Sed} 1030194754Sed 1031200581Srdivackyclass ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1032206083Srdivacky InstrItinClass itin, 1033206083Srdivacky string asm, string cstr, list<dag> pattern> 1034200581Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1035200581Srdivacky let OutOperandList = oops; 1036200581Srdivacky let InOperandList = iops; 1037208599Srdivacky let AsmString = asm; 1038200581Srdivacky let Pattern = pattern; 1039218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1040200581Srdivacky} 1041200581Srdivacky 1042198090Srdivackyclass T2I<dag oops, dag iops, InstrItinClass itin, 1043198090Srdivacky string opc, string asm, list<dag> pattern> 1044198090Srdivacky : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1045198090Srdivackyclass T2Ii12<dag oops, dag iops, InstrItinClass itin, 1046198090Srdivacky string opc, string asm, list<dag> pattern> 1047206083Srdivacky : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>; 1048198090Srdivackyclass T2Ii8<dag oops, dag iops, InstrItinClass itin, 1049198090Srdivacky string opc, string asm, list<dag> pattern> 1050198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 1051198090Srdivackyclass T2Iso<dag oops, dag iops, InstrItinClass itin, 1052198090Srdivacky string opc, string asm, list<dag> pattern> 1053198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 1054198090Srdivackyclass T2Ipc<dag oops, dag iops, InstrItinClass itin, 1055198090Srdivacky string opc, string asm, list<dag> pattern> 1056198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1057218893Sdimclass T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, 1058198090Srdivacky string opc, string asm, list<dag> pattern> 1059201360Srdivacky : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1060201360Srdivacky pattern> { 1061218893Sdim bits<4> Rt; 1062218893Sdim bits<4> Rt2; 1063218893Sdim bits<13> addr; 1064218893Sdim let Inst{31-25} = 0b1110100; 1065212904Sdim let Inst{24} = P; 1066218893Sdim let Inst{23} = addr{8}; 1067212904Sdim let Inst{22} = 1; 1068212904Sdim let Inst{21} = W; 1069218893Sdim let Inst{20} = isLoad; 1070218893Sdim let Inst{19-16} = addr{12-9}; 1071218893Sdim let Inst{15-12} = Rt{3-0}; 1072218893Sdim let Inst{11-8} = Rt2{3-0}; 1073218893Sdim let Inst{7-0} = addr{7-0}; 1074201360Srdivacky} 1075195098Sed 1076198090Srdivackyclass T2sI<dag oops, dag iops, InstrItinClass itin, 1077198090Srdivacky string opc, string asm, list<dag> pattern> 1078198090Srdivacky : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1079195098Sed 1080198090Srdivackyclass T2XI<dag oops, dag iops, InstrItinClass itin, 1081198090Srdivacky string asm, list<dag> pattern> 1082198090Srdivacky : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1083198090Srdivackyclass T2JTI<dag oops, dag iops, InstrItinClass itin, 1084198090Srdivacky string asm, list<dag> pattern> 1085198090Srdivacky : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1086195098Sed 1087218893Sdim// Move to/from coprocessor instructions 1088218893Sdimclass T2Cop<dag oops, dag iops, string asm, list<dag> pattern> 1089218893Sdim : T2XI<oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2, HasV6]> { 1090218893Sdim let Inst{31-28} = 0b1111; 1091218893Sdim} 1092198090Srdivacky 1093205218Srdivacky// Two-address instructions 1094205218Srdivackyclass T2XIt<dag oops, dag iops, InstrItinClass itin, 1095205218Srdivacky string asm, string cstr, list<dag> pattern> 1096205218Srdivacky : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>; 1097198090Srdivacky 1098195340Sed// T2Iidxldst - Thumb2 indexed load / store instructions. 1099201360Srdivackyclass T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1100201360Srdivacky dag oops, dag iops, 1101201360Srdivacky AddrMode am, IndexMode im, InstrItinClass itin, 1102195340Sed string opc, string asm, string cstr, list<dag> pattern> 1103198892Srdivacky : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1104195340Sed let OutOperandList = oops; 1105205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1106218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1107195340Sed let Pattern = pattern; 1108195340Sed list<Predicate> Predicates = [IsThumb2]; 1109201360Srdivacky let Inst{31-27} = 0b11111; 1110201360Srdivacky let Inst{26-25} = 0b00; 1111212904Sdim let Inst{24} = signed; 1112212904Sdim let Inst{23} = 0; 1113201360Srdivacky let Inst{22-21} = opcod; 1114212904Sdim let Inst{20} = load; 1115212904Sdim let Inst{11} = 1; 1116201360Srdivacky // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1117212904Sdim let Inst{10} = pre; // The P bit. 1118212904Sdim let Inst{8} = 1; // The W bit. 1119195340Sed 1120218893Sdim bits<9> addr; 1121218893Sdim let Inst{7-0} = addr{7-0}; 1122218893Sdim let Inst{9} = addr{8}; // Sign bit 1123218893Sdim 1124218893Sdim bits<4> Rt; 1125218893Sdim bits<4> Rn; 1126218893Sdim let Inst{15-12} = Rt{3-0}; 1127218893Sdim let Inst{19-16} = Rn{3-0}; 1128204642Srdivacky} 1129204642Srdivacky 1130198090Srdivacky// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1131198090Srdivackyclass Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1132218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1133198090Srdivacky} 1134195340Sed 1135198090Srdivacky// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1136198090Srdivackyclass T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1137218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1138198090Srdivacky} 1139198090Srdivacky 1140195098Sed// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1141195098Sedclass T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1142195340Sed list<Predicate> Predicates = [IsThumb2]; 1143195098Sed} 1144195098Sed 1145193323Sed//===----------------------------------------------------------------------===// 1146193323Sed 1147193323Sed//===----------------------------------------------------------------------===// 1148193323Sed// ARM VFP Instruction templates. 1149193323Sed// 1150193323Sed 1151198090Srdivacky// Almost all VFP instructions are predicable. 1152198090Srdivackyclass VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1153198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1154198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1155198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1156218893Sdim bits<4> p; 1157218893Sdim let Inst{31-28} = p; 1158198090Srdivacky let OutOperandList = oops; 1159205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1160218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1161198090Srdivacky let Pattern = pattern; 1162218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1163198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1164198090Srdivacky} 1165198090Srdivacky 1166198090Srdivacky// Special cases 1167198090Srdivackyclass VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1168198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1169198090Srdivacky string asm, string cstr, list<dag> pattern> 1170198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1171218893Sdim bits<4> p; 1172218893Sdim let Inst{31-28} = p; 1173198090Srdivacky let OutOperandList = oops; 1174198090Srdivacky let InOperandList = iops; 1175208599Srdivacky let AsmString = asm; 1176198090Srdivacky let Pattern = pattern; 1177218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1178198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1179198090Srdivacky} 1180198090Srdivacky 1181198090Srdivackyclass VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1182198090Srdivacky string opc, string asm, list<dag> pattern> 1183198090Srdivacky : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1184218893Sdim opc, asm, "", pattern> { 1185218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1186218893Sdim} 1187198090Srdivacky 1188193323Sed// ARM VFP addrmode5 loads and stores 1189193323Sedclass ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1190198090Srdivacky InstrItinClass itin, 1191193323Sed string opc, string asm, list<dag> pattern> 1192198090Srdivacky : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1193206083Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1194218893Sdim // Instruction operands. 1195218893Sdim bits<5> Dd; 1196218893Sdim bits<13> addr; 1197218893Sdim 1198218893Sdim // Encode instruction operands. 1199218893Sdim let Inst{23} = addr{8}; // U (add = (U == '1')) 1200218893Sdim let Inst{22} = Dd{4}; 1201218893Sdim let Inst{19-16} = addr{12-9}; // Rn 1202218893Sdim let Inst{15-12} = Dd{3-0}; 1203218893Sdim let Inst{7-0} = addr{7-0}; // imm8 1204218893Sdim 1205193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1206193323Sed let Inst{27-24} = opcod1; 1207193323Sed let Inst{21-20} = opcod2; 1208218893Sdim let Inst{11-9} = 0b101; 1209218893Sdim let Inst{8} = 1; // Double precision 1210198892Srdivacky 1211218893Sdim // Loads & stores operate on both NEON and VFP pipelines. 1212206274Srdivacky let D = VFPNeonDomain; 1213193323Sed} 1214193323Sed 1215193323Sedclass ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1216198090Srdivacky InstrItinClass itin, 1217193323Sed string opc, string asm, list<dag> pattern> 1218198090Srdivacky : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1219206083Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1220218893Sdim // Instruction operands. 1221218893Sdim bits<5> Sd; 1222218893Sdim bits<13> addr; 1223218893Sdim 1224218893Sdim // Encode instruction operands. 1225218893Sdim let Inst{23} = addr{8}; // U (add = (U == '1')) 1226218893Sdim let Inst{22} = Sd{0}; 1227218893Sdim let Inst{19-16} = addr{12-9}; // Rn 1228218893Sdim let Inst{15-12} = Sd{4-1}; 1229218893Sdim let Inst{7-0} = addr{7-0}; // imm8 1230218893Sdim 1231193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1232193323Sed let Inst{27-24} = opcod1; 1233193323Sed let Inst{21-20} = opcod2; 1234218893Sdim let Inst{11-9} = 0b101; 1235218893Sdim let Inst{8} = 0; // Single precision 1236218893Sdim 1237218893Sdim // Loads & stores operate on both NEON and VFP pipelines. 1238218893Sdim let D = VFPNeonDomain; 1239193323Sed} 1240193323Sed 1241218893Sdim// VFP Load / store multiple pseudo instructions. 1242218893Sdimclass PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1243218893Sdim list<dag> pattern> 1244218893Sdim : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain, 1245218893Sdim cstr, itin> { 1246218893Sdim let OutOperandList = oops; 1247218893Sdim let InOperandList = !con(iops, (ins pred:$p)); 1248218893Sdim let Pattern = pattern; 1249218893Sdim list<Predicate> Predicates = [HasVFP2]; 1250218893Sdim} 1251218893Sdim 1252193323Sed// Load / store multiple 1253212904Sdimclass AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1254205218Srdivacky string asm, string cstr, list<dag> pattern> 1255212904Sdim : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1256206083Srdivacky VFPLdStMulFrm, itin, asm, cstr, pattern> { 1257218893Sdim // Instruction operands. 1258218893Sdim bits<4> Rn; 1259218893Sdim bits<13> regs; 1260218893Sdim 1261218893Sdim // Encode instruction operands. 1262218893Sdim let Inst{19-16} = Rn; 1263218893Sdim let Inst{22} = regs{12}; 1264218893Sdim let Inst{15-12} = regs{11-8}; 1265218893Sdim let Inst{7-0} = regs{7-0}; 1266218893Sdim 1267193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1268193323Sed let Inst{27-25} = 0b110; 1269218893Sdim let Inst{11-9} = 0b101; 1270218893Sdim let Inst{8} = 1; // Double precision 1271193323Sed} 1272193323Sed 1273212904Sdimclass AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1274205218Srdivacky string asm, string cstr, list<dag> pattern> 1275212904Sdim : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1276206083Srdivacky VFPLdStMulFrm, itin, asm, cstr, pattern> { 1277218893Sdim // Instruction operands. 1278218893Sdim bits<4> Rn; 1279218893Sdim bits<13> regs; 1280218893Sdim 1281218893Sdim // Encode instruction operands. 1282218893Sdim let Inst{19-16} = Rn; 1283218893Sdim let Inst{22} = regs{8}; 1284218893Sdim let Inst{15-12} = regs{12-9}; 1285218893Sdim let Inst{7-0} = regs{7-0}; 1286218893Sdim 1287193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1288193323Sed let Inst{27-25} = 0b110; 1289218893Sdim let Inst{11-9} = 0b101; 1290218893Sdim let Inst{8} = 0; // Single precision 1291193323Sed} 1292193323Sed 1293193323Sed// Double precision, unary 1294203954Srdivackyclass ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1295203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1296203954Srdivacky string asm, list<dag> pattern> 1297198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1298218893Sdim // Instruction operands. 1299218893Sdim bits<5> Dd; 1300218893Sdim bits<5> Dm; 1301218893Sdim 1302218893Sdim // Encode instruction operands. 1303218893Sdim let Inst{3-0} = Dm{3-0}; 1304218893Sdim let Inst{5} = Dm{4}; 1305218893Sdim let Inst{15-12} = Dd{3-0}; 1306218893Sdim let Inst{22} = Dd{4}; 1307218893Sdim 1308203954Srdivacky let Inst{27-23} = opcod1; 1309203954Srdivacky let Inst{21-20} = opcod2; 1310203954Srdivacky let Inst{19-16} = opcod3; 1311218893Sdim let Inst{11-9} = 0b101; 1312218893Sdim let Inst{8} = 1; // Double precision 1313203954Srdivacky let Inst{7-6} = opcod4; 1314203954Srdivacky let Inst{4} = opcod5; 1315193323Sed} 1316193323Sed 1317193323Sed// Double precision, binary 1318203954Srdivackyclass ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1319206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1320206083Srdivacky list<dag> pattern> 1321198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1322218893Sdim // Instruction operands. 1323218893Sdim bits<5> Dd; 1324218893Sdim bits<5> Dn; 1325218893Sdim bits<5> Dm; 1326193323Sed 1327218893Sdim // Encode instruction operands. 1328218893Sdim let Inst{3-0} = Dm{3-0}; 1329218893Sdim let Inst{5} = Dm{4}; 1330218893Sdim let Inst{19-16} = Dn{3-0}; 1331218893Sdim let Inst{7} = Dn{4}; 1332218893Sdim let Inst{15-12} = Dd{3-0}; 1333218893Sdim let Inst{22} = Dd{4}; 1334218893Sdim 1335206083Srdivacky let Inst{27-23} = opcod1; 1336206083Srdivacky let Inst{21-20} = opcod2; 1337218893Sdim let Inst{11-9} = 0b101; 1338218893Sdim let Inst{8} = 1; // Double precision 1339212904Sdim let Inst{6} = op6; 1340212904Sdim let Inst{4} = op4; 1341206083Srdivacky} 1342206083Srdivacky 1343193323Sed// Single precision, unary 1344203954Srdivackyclass ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1345203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1346203954Srdivacky string asm, list<dag> pattern> 1347198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1348218893Sdim // Instruction operands. 1349218893Sdim bits<5> Sd; 1350218893Sdim bits<5> Sm; 1351218893Sdim 1352218893Sdim // Encode instruction operands. 1353218893Sdim let Inst{3-0} = Sm{4-1}; 1354218893Sdim let Inst{5} = Sm{0}; 1355218893Sdim let Inst{15-12} = Sd{4-1}; 1356218893Sdim let Inst{22} = Sd{0}; 1357218893Sdim 1358203954Srdivacky let Inst{27-23} = opcod1; 1359203954Srdivacky let Inst{21-20} = opcod2; 1360203954Srdivacky let Inst{19-16} = opcod3; 1361218893Sdim let Inst{11-9} = 0b101; 1362218893Sdim let Inst{8} = 0; // Single precision 1363203954Srdivacky let Inst{7-6} = opcod4; 1364203954Srdivacky let Inst{4} = opcod5; 1365193323Sed} 1366193323Sed 1367218893Sdim// Single precision unary, if no NEON. Same as ASuI except not available if 1368218893Sdim// NEON is enabled. 1369203954Srdivackyclass ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1370203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1371203954Srdivacky string asm, list<dag> pattern> 1372203954Srdivacky : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1373203954Srdivacky pattern> { 1374198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1375198090Srdivacky} 1376198090Srdivacky 1377193323Sed// Single precision, binary 1378203954Srdivackyclass ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1379203954Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1380198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1381218893Sdim // Instruction operands. 1382218893Sdim bits<5> Sd; 1383218893Sdim bits<5> Sn; 1384218893Sdim bits<5> Sm; 1385218893Sdim 1386218893Sdim // Encode instruction operands. 1387218893Sdim let Inst{3-0} = Sm{4-1}; 1388218893Sdim let Inst{5} = Sm{0}; 1389218893Sdim let Inst{19-16} = Sn{4-1}; 1390218893Sdim let Inst{7} = Sn{0}; 1391218893Sdim let Inst{15-12} = Sd{4-1}; 1392218893Sdim let Inst{22} = Sd{0}; 1393218893Sdim 1394203954Srdivacky let Inst{27-23} = opcod1; 1395203954Srdivacky let Inst{21-20} = opcod2; 1396218893Sdim let Inst{11-9} = 0b101; 1397218893Sdim let Inst{8} = 0; // Single precision 1398212904Sdim let Inst{6} = op6; 1399212904Sdim let Inst{4} = op4; 1400193323Sed} 1401193323Sed 1402218893Sdim// Single precision binary, if no NEON. Same as ASbI except not available if 1403218893Sdim// NEON is enabled. 1404203954Srdivackyclass ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1405206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1406206083Srdivacky list<dag> pattern> 1407203954Srdivacky : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1408198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1409218893Sdim 1410218893Sdim // Instruction operands. 1411218893Sdim bits<5> Sd; 1412218893Sdim bits<5> Sn; 1413218893Sdim bits<5> Sm; 1414218893Sdim 1415218893Sdim // Encode instruction operands. 1416218893Sdim let Inst{3-0} = Sm{4-1}; 1417218893Sdim let Inst{5} = Sm{0}; 1418218893Sdim let Inst{19-16} = Sn{4-1}; 1419218893Sdim let Inst{7} = Sn{0}; 1420218893Sdim let Inst{15-12} = Sd{4-1}; 1421218893Sdim let Inst{22} = Sd{0}; 1422198090Srdivacky} 1423198090Srdivacky 1424193323Sed// VFP conversion instructions 1425203954Srdivackyclass AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1426203954Srdivacky dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1427203954Srdivacky list<dag> pattern> 1428198090Srdivacky : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1429203954Srdivacky let Inst{27-23} = opcod1; 1430203954Srdivacky let Inst{21-20} = opcod2; 1431203954Srdivacky let Inst{19-16} = opcod3; 1432203954Srdivacky let Inst{11-8} = opcod4; 1433193323Sed let Inst{6} = 1; 1434203954Srdivacky let Inst{4} = 0; 1435193323Sed} 1436193323Sed 1437203954Srdivacky// VFP conversion between floating-point and fixed-point 1438203954Srdivackyclass AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1439206083Srdivacky dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1440206083Srdivacky list<dag> pattern> 1441203954Srdivacky : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1442203954Srdivacky // size (fixed-point number): sx == 0 ? 16 : 32 1443203954Srdivacky let Inst{7} = op5; // sx 1444203954Srdivacky} 1445203954Srdivacky 1446198090Srdivacky// VFP conversion instructions, if no NEON 1447203954Srdivackyclass AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1448198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1449198090Srdivacky string opc, string asm, list<dag> pattern> 1450203954Srdivacky : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1451203954Srdivacky pattern> { 1452198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1453198090Srdivacky} 1454198090Srdivacky 1455193323Sedclass AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1456198090Srdivacky InstrItinClass itin, 1457198090Srdivacky string opc, string asm, list<dag> pattern> 1458198090Srdivacky : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1459193323Sed let Inst{27-20} = opcod1; 1460193323Sed let Inst{11-8} = opcod2; 1461193323Sed let Inst{4} = 1; 1462193323Sed} 1463193323Sed 1464198090Srdivackyclass AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1465198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1466198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1467193323Sed 1468206083Srdivackyclass AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1469198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1470198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1471193323Sed 1472198090Srdivackyclass AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1473198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1474198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1475193323Sed 1476198090Srdivackyclass AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1477198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1478198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1479193323Sed 1480193323Sed//===----------------------------------------------------------------------===// 1481193323Sed 1482194710Sed//===----------------------------------------------------------------------===// 1483194710Sed// ARM NEON Instruction templates. 1484194710Sed// 1485193323Sed 1486205407Srdivackyclass NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1487205407Srdivacky InstrItinClass itin, string opc, string dt, string asm, string cstr, 1488205407Srdivacky list<dag> pattern> 1489205407Srdivacky : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1490194710Sed let OutOperandList = oops; 1491205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1492218893Sdim let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1493194710Sed let Pattern = pattern; 1494194710Sed list<Predicate> Predicates = [HasNEON]; 1495193323Sed} 1496193323Sed 1497199989Srdivacky// Same as NeonI except it does not have a "data type" specifier. 1498206083Srdivackyclass NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1499206083Srdivacky InstrItinClass itin, string opc, string asm, string cstr, 1500206083Srdivacky list<dag> pattern> 1501206083Srdivacky : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1502199989Srdivacky let OutOperandList = oops; 1503205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1504218893Sdim let AsmString = !strconcat(opc, "${p}", "\t", asm); 1505199989Srdivacky let Pattern = pattern; 1506199989Srdivacky list<Predicate> Predicates = [HasNEON]; 1507193323Sed} 1508194710Sed 1509198090Srdivackyclass NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1510198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1511199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1512205407Srdivacky : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1513205407Srdivacky cstr, pattern> { 1514198090Srdivacky let Inst{31-24} = 0b11110100; 1515212904Sdim let Inst{23} = op23; 1516198396Srdivacky let Inst{21-20} = op21_20; 1517212904Sdim let Inst{11-8} = op11_8; 1518212904Sdim let Inst{7-4} = op7_4; 1519218893Sdim 1520218893Sdim let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1521218893Sdim 1522218893Sdim bits<5> Vd; 1523218893Sdim bits<6> Rn; 1524218893Sdim bits<4> Rm; 1525218893Sdim 1526218893Sdim let Inst{22} = Vd{4}; 1527218893Sdim let Inst{15-12} = Vd{3-0}; 1528218893Sdim let Inst{19-16} = Rn{3-0}; 1529218893Sdim let Inst{3-0} = Rm{3-0}; 1530198090Srdivacky} 1531198090Srdivacky 1532218893Sdimclass NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1533218893Sdim dag oops, dag iops, InstrItinClass itin, 1534218893Sdim string opc, string dt, string asm, string cstr, list<dag> pattern> 1535218893Sdim : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1536218893Sdim dt, asm, cstr, pattern> { 1537218893Sdim bits<3> lane; 1538218893Sdim} 1539218893Sdim 1540212904Sdimclass PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1541212904Sdim : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1542212904Sdim itin> { 1543212904Sdim let OutOperandList = oops; 1544212904Sdim let InOperandList = !con(iops, (ins pred:$p)); 1545212904Sdim list<Predicate> Predicates = [HasNEON]; 1546212904Sdim} 1547212904Sdim 1548218893Sdimclass PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1549218893Sdim list<dag> pattern> 1550218893Sdim : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1551218893Sdim itin> { 1552218893Sdim let OutOperandList = oops; 1553218893Sdim let InOperandList = !con(iops, (ins pred:$p)); 1554218893Sdim let Pattern = pattern; 1555218893Sdim list<Predicate> Predicates = [HasNEON]; 1556218893Sdim} 1557218893Sdim 1558206083Srdivackyclass NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1559199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1560206083Srdivacky : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1561206083Srdivacky pattern> { 1562194710Sed let Inst{31-25} = 0b1111001; 1563218893Sdim let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1564194710Sed} 1565194710Sed 1566206083Srdivackyclass NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1567206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1568206083Srdivacky : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1569206083Srdivacky cstr, pattern> { 1570199989Srdivacky let Inst{31-25} = 0b1111001; 1571218893Sdim let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1572199989Srdivacky} 1573199989Srdivacky 1574194710Sed// NEON "one register and a modified immediate" format. 1575194710Sedclass N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1576194710Sed bit op5, bit op4, 1577198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1578206083Srdivacky string opc, string dt, string asm, string cstr, 1579206083Srdivacky list<dag> pattern> 1580206083Srdivacky : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1581212904Sdim let Inst{23} = op23; 1582194710Sed let Inst{21-19} = op21_19; 1583212904Sdim let Inst{11-8} = op11_8; 1584212904Sdim let Inst{7} = op7; 1585212904Sdim let Inst{6} = op6; 1586212904Sdim let Inst{5} = op5; 1587212904Sdim let Inst{4} = op4; 1588218893Sdim 1589218893Sdim // Instruction operands. 1590218893Sdim bits<5> Vd; 1591218893Sdim bits<13> SIMM; 1592218893Sdim 1593218893Sdim let Inst{15-12} = Vd{3-0}; 1594218893Sdim let Inst{22} = Vd{4}; 1595218893Sdim let Inst{24} = SIMM{7}; 1596218893Sdim let Inst{18-16} = SIMM{6-4}; 1597218893Sdim let Inst{3-0} = SIMM{3-0}; 1598194710Sed} 1599194710Sed 1600194710Sed// NEON 2 vector register format. 1601194710Sedclass N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1602194710Sed bits<5> op11_7, bit op6, bit op4, 1603198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1604199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1605206083Srdivacky : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 1606194710Sed let Inst{24-23} = op24_23; 1607194710Sed let Inst{21-20} = op21_20; 1608194710Sed let Inst{19-18} = op19_18; 1609194710Sed let Inst{17-16} = op17_16; 1610212904Sdim let Inst{11-7} = op11_7; 1611212904Sdim let Inst{6} = op6; 1612212904Sdim let Inst{4} = op4; 1613218893Sdim 1614218893Sdim // Instruction operands. 1615218893Sdim bits<5> Vd; 1616218893Sdim bits<5> Vm; 1617218893Sdim 1618218893Sdim let Inst{15-12} = Vd{3-0}; 1619218893Sdim let Inst{22} = Vd{4}; 1620218893Sdim let Inst{3-0} = Vm{3-0}; 1621218893Sdim let Inst{5} = Vm{4}; 1622194710Sed} 1623194710Sed 1624199989Srdivacky// Same as N2V except it doesn't have a datatype suffix. 1625199989Srdivackyclass N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1626206083Srdivacky bits<5> op11_7, bit op6, bit op4, 1627206083Srdivacky dag oops, dag iops, InstrItinClass itin, 1628206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1629206083Srdivacky : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 1630198396Srdivacky let Inst{24-23} = op24_23; 1631198396Srdivacky let Inst{21-20} = op21_20; 1632199989Srdivacky let Inst{19-18} = op19_18; 1633199989Srdivacky let Inst{17-16} = op17_16; 1634212904Sdim let Inst{11-7} = op11_7; 1635212904Sdim let Inst{6} = op6; 1636212904Sdim let Inst{4} = op4; 1637218893Sdim 1638218893Sdim // Instruction operands. 1639218893Sdim bits<5> Vd; 1640218893Sdim bits<5> Vm; 1641218893Sdim 1642218893Sdim let Inst{15-12} = Vd{3-0}; 1643218893Sdim let Inst{22} = Vd{4}; 1644218893Sdim let Inst{3-0} = Vm{3-0}; 1645218893Sdim let Inst{5} = Vm{4}; 1646198396Srdivacky} 1647198396Srdivacky 1648194710Sed// NEON 2 vector register with immediate. 1649198396Srdivackyclass N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1650206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1651199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1652206083Srdivacky : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1653212904Sdim let Inst{24} = op24; 1654212904Sdim let Inst{23} = op23; 1655194710Sed let Inst{11-8} = op11_8; 1656212904Sdim let Inst{7} = op7; 1657212904Sdim let Inst{6} = op6; 1658212904Sdim let Inst{4} = op4; 1659218893Sdim 1660218893Sdim // Instruction operands. 1661218893Sdim bits<5> Vd; 1662218893Sdim bits<5> Vm; 1663218893Sdim bits<6> SIMM; 1664218893Sdim 1665218893Sdim let Inst{15-12} = Vd{3-0}; 1666218893Sdim let Inst{22} = Vd{4}; 1667218893Sdim let Inst{3-0} = Vm{3-0}; 1668218893Sdim let Inst{5} = Vm{4}; 1669218893Sdim let Inst{21-16} = SIMM{5-0}; 1670194710Sed} 1671194710Sed 1672194710Sed// NEON 3 vector register format. 1673194710Sedclass N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1674206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1675199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1676206083Srdivacky : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1677212904Sdim let Inst{24} = op24; 1678212904Sdim let Inst{23} = op23; 1679194710Sed let Inst{21-20} = op21_20; 1680212904Sdim let Inst{11-8} = op11_8; 1681212904Sdim let Inst{6} = op6; 1682212904Sdim let Inst{4} = op4; 1683218893Sdim 1684218893Sdim // Instruction operands. 1685218893Sdim bits<5> Vd; 1686218893Sdim bits<5> Vn; 1687218893Sdim bits<5> Vm; 1688218893Sdim 1689218893Sdim let Inst{15-12} = Vd{3-0}; 1690218893Sdim let Inst{22} = Vd{4}; 1691218893Sdim let Inst{19-16} = Vn{3-0}; 1692218893Sdim let Inst{7} = Vn{4}; 1693218893Sdim let Inst{3-0} = Vm{3-0}; 1694218893Sdim let Inst{5} = Vm{4}; 1695194710Sed} 1696194710Sed 1697206083Srdivacky// Same as N3V except it doesn't have a data type suffix. 1698206083Srdivackyclass N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1699206083Srdivacky bit op4, 1700206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1701206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1702206083Srdivacky : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 1703212904Sdim let Inst{24} = op24; 1704212904Sdim let Inst{23} = op23; 1705198396Srdivacky let Inst{21-20} = op21_20; 1706212904Sdim let Inst{11-8} = op11_8; 1707212904Sdim let Inst{6} = op6; 1708212904Sdim let Inst{4} = op4; 1709218893Sdim 1710218893Sdim // Instruction operands. 1711218893Sdim bits<5> Vd; 1712218893Sdim bits<5> Vn; 1713218893Sdim bits<5> Vm; 1714218893Sdim 1715218893Sdim let Inst{15-12} = Vd{3-0}; 1716218893Sdim let Inst{22} = Vd{4}; 1717218893Sdim let Inst{19-16} = Vn{3-0}; 1718218893Sdim let Inst{7} = Vn{4}; 1719218893Sdim let Inst{3-0} = Vm{3-0}; 1720218893Sdim let Inst{5} = Vm{4}; 1721198396Srdivacky} 1722198396Srdivacky 1723194710Sed// NEON VMOVs between scalar and core registers. 1724194710Sedclass NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1725198090Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1726199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1727218893Sdim : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain, 1728206083Srdivacky "", itin> { 1729194710Sed let Inst{27-20} = opcod1; 1730212904Sdim let Inst{11-8} = opcod2; 1731212904Sdim let Inst{6-5} = opcod3; 1732212904Sdim let Inst{4} = 1; 1733199989Srdivacky 1734199989Srdivacky let OutOperandList = oops; 1735205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1736218893Sdim let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1737199989Srdivacky let Pattern = pattern; 1738194710Sed list<Predicate> Predicates = [HasNEON]; 1739218893Sdim 1740218893Sdim let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 1741218893Sdim 1742218893Sdim bits<5> V; 1743218893Sdim bits<4> R; 1744218893Sdim bits<4> p; 1745218893Sdim bits<4> lane; 1746218893Sdim 1747218893Sdim let Inst{31-28} = p{3-0}; 1748218893Sdim let Inst{7} = V{4}; 1749218893Sdim let Inst{19-16} = V{3-0}; 1750218893Sdim let Inst{15-12} = R{3-0}; 1751194710Sed} 1752194710Sedclass NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1753198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1754199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1755210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 1756199989Srdivacky opc, dt, asm, pattern>; 1757194710Sedclass NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1758198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1759199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1760210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 1761199989Srdivacky opc, dt, asm, pattern>; 1762194710Sedclass NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1763198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1764199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1765210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 1766199989Srdivacky opc, dt, asm, pattern>; 1767198090Srdivacky 1768206083Srdivacky// Vector Duplicate Lane (from scalar to all elements) 1769206083Srdivackyclass NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 1770206083Srdivacky InstrItinClass itin, string opc, string dt, string asm, 1771206083Srdivacky list<dag> pattern> 1772206083Srdivacky : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 1773206083Srdivacky let Inst{24-23} = 0b11; 1774206083Srdivacky let Inst{21-20} = 0b11; 1775206083Srdivacky let Inst{19-16} = op19_16; 1776212904Sdim let Inst{11-7} = 0b11000; 1777212904Sdim let Inst{6} = op6; 1778212904Sdim let Inst{4} = 0; 1779218893Sdim 1780218893Sdim bits<5> Vd; 1781218893Sdim bits<5> Vm; 1782218893Sdim bits<4> lane; 1783218893Sdim 1784218893Sdim let Inst{22} = Vd{4}; 1785218893Sdim let Inst{15-12} = Vd{3-0}; 1786218893Sdim let Inst{5} = Vm{4}; 1787218893Sdim let Inst{3-0} = Vm{3-0}; 1788206083Srdivacky} 1789206083Srdivacky 1790198090Srdivacky// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1791198090Srdivacky// for single-precision FP. 1792198090Srdivackyclass NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1793198090Srdivacky list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1794198090Srdivacky} 1795