ARMInstrFormats.td revision 206083
1193323Sed//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// 2206083Srdivacky// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7206083Srdivacky// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// 12193323Sed// ARM Instruction Format Definitions. 13193323Sed// 14193323Sed 15193323Sed// Format specifies the encoding used by the instruction. This is part of the 16193323Sed// ad-hoc solution used to emit machine instruction encodings by our machine 17193323Sed// code emitter. 18205407Srdivackyclass Format<bits<6> val> { 19205407Srdivacky bits<6> Value = val; 20193323Sed} 21193323Sed 22193323Seddef Pseudo : Format<0>; 23193323Seddef MulFrm : Format<1>; 24193323Seddef BrFrm : Format<2>; 25193323Seddef BrMiscFrm : Format<3>; 26193323Sed 27193323Seddef DPFrm : Format<4>; 28193323Seddef DPSoRegFrm : Format<5>; 29193323Sed 30193323Seddef LdFrm : Format<6>; 31193323Seddef StFrm : Format<7>; 32193323Seddef LdMiscFrm : Format<8>; 33193323Seddef StMiscFrm : Format<9>; 34193323Seddef LdStMulFrm : Format<10>; 35193323Sed 36205407Srdivackydef LdStExFrm : Format<11>; 37200581Srdivacky 38205407Srdivackydef ArithMiscFrm : Format<12>; 39205407Srdivackydef ExtFrm : Format<13>; 40193323Sed 41205407Srdivackydef VFPUnaryFrm : Format<14>; 42205407Srdivackydef VFPBinaryFrm : Format<15>; 43205407Srdivackydef VFPConv1Frm : Format<16>; 44205407Srdivackydef VFPConv2Frm : Format<17>; 45205407Srdivackydef VFPConv3Frm : Format<18>; 46205407Srdivackydef VFPConv4Frm : Format<19>; 47205407Srdivackydef VFPConv5Frm : Format<20>; 48205407Srdivackydef VFPLdStFrm : Format<21>; 49205407Srdivackydef VFPLdStMulFrm : Format<22>; 50205407Srdivackydef VFPMiscFrm : Format<23>; 51193323Sed 52205407Srdivackydef ThumbFrm : Format<24>; 53193323Sed 54205407Srdivackydef NEONFrm : Format<25>; 55205407Srdivackydef NEONGetLnFrm : Format<26>; 56205407Srdivackydef NEONSetLnFrm : Format<27>; 57205407Srdivackydef NEONDupFrm : Format<28>; 58194710Sed 59203954Srdivackydef MiscFrm : Format<29>; 60203954Srdivackydef ThumbMiscFrm : Format<30>; 61203954Srdivacky 62206083Srdivackydef NLdStFrm : Format<31>; 63206083Srdivackydef N1RegModImmFrm : Format<32>; 64206083Srdivackydef N2RegFrm : Format<33>; 65206083Srdivackydef NVCVTFrm : Format<34>; 66206083Srdivackydef NVDupLnFrm : Format<35>; 67206083Srdivackydef N2RegVShLFrm : Format<36>; 68206083Srdivackydef N2RegVShRFrm : Format<37>; 69206083Srdivackydef N3RegFrm : Format<38>; 70206083Srdivackydef N3RegVShFrm : Format<39>; 71206083Srdivackydef NVExtFrm : Format<40>; 72206083Srdivackydef NVMulSLFrm : Format<41>; 73206083Srdivackydef NVTBLFrm : Format<42>; 74205407Srdivacky 75198090Srdivacky// Misc flags. 76198090Srdivacky 77193323Sed// the instruction has a Rn register operand. 78198090Srdivacky// UnaryDP - Indicates this is a unary data processing instruction, i.e. 79198090Srdivacky// it doesn't have a Rn operand. 80198090Srdivackyclass UnaryDP { bit isUnaryDataProc = 1; } 81193323Sed 82198090Srdivacky// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 83198090Srdivacky// a 16-bit Thumb instruction if certain conditions are met. 84198090Srdivackyclass Xform16Bit { bit canXformTo16Bit = 1; } 85198090Srdivacky 86193323Sed//===----------------------------------------------------------------------===// 87205407Srdivacky// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 88195340Sed// 89193323Sed 90195340Sed// Addressing mode. 91195340Sedclass AddrMode<bits<4> val> { 92195340Sed bits<4> Value = val; 93195340Sed} 94195340Seddef AddrModeNone : AddrMode<0>; 95195340Seddef AddrMode1 : AddrMode<1>; 96195340Seddef AddrMode2 : AddrMode<2>; 97195340Seddef AddrMode3 : AddrMode<3>; 98195340Seddef AddrMode4 : AddrMode<4>; 99195340Seddef AddrMode5 : AddrMode<5>; 100195340Seddef AddrMode6 : AddrMode<6>; 101195340Seddef AddrModeT1_1 : AddrMode<7>; 102195340Seddef AddrModeT1_2 : AddrMode<8>; 103195340Seddef AddrModeT1_4 : AddrMode<9>; 104195340Seddef AddrModeT1_s : AddrMode<10>; 105198090Srdivackydef AddrModeT2_i12: AddrMode<11>; 106195340Seddef AddrModeT2_i8 : AddrMode<12>; 107195340Seddef AddrModeT2_so : AddrMode<13>; 108195340Seddef AddrModeT2_pc : AddrMode<14>; 109195340Seddef AddrModeT2_i8s4 : AddrMode<15>; 110195340Sed 111195340Sed// Instruction size. 112195340Sedclass SizeFlagVal<bits<3> val> { 113195340Sed bits<3> Value = val; 114195340Sed} 115195340Seddef SizeInvalid : SizeFlagVal<0>; // Unset. 116195340Seddef SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 117195340Seddef Size8Bytes : SizeFlagVal<2>; 118195340Seddef Size4Bytes : SizeFlagVal<3>; 119195340Seddef Size2Bytes : SizeFlagVal<4>; 120195340Sed 121195340Sed// Load / store index mode. 122195340Sedclass IndexMode<bits<2> val> { 123195340Sed bits<2> Value = val; 124195340Sed} 125195340Seddef IndexModeNone : IndexMode<0>; 126195340Seddef IndexModePre : IndexMode<1>; 127195340Seddef IndexModePost : IndexMode<2>; 128205218Srdivackydef IndexModeUpd : IndexMode<3>; 129195340Sed 130198892Srdivacky// Instruction execution domain. 131198892Srdivackyclass Domain<bits<2> val> { 132198892Srdivacky bits<2> Value = val; 133198892Srdivacky} 134198892Srdivackydef GenericDomain : Domain<0>; 135198892Srdivackydef VFPDomain : Domain<1>; // Instructions in VFP domain only 136198892Srdivackydef NeonDomain : Domain<2>; // Instructions in Neon domain only 137198892Srdivackydef VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 138198892Srdivacky 139195340Sed//===----------------------------------------------------------------------===// 140195340Sed 141198090Srdivacky// ARM special operands. 142198090Srdivacky// 143198090Srdivacky 144198090Srdivacky// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 145198090Srdivacky// register whose default is 0 (no register). 146198090Srdivackydef pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 147198090Srdivacky (ops (i32 14), (i32 zero_reg))> { 148198090Srdivacky let PrintMethod = "printPredicateOperand"; 149198090Srdivacky} 150198090Srdivacky 151198090Srdivacky// Conditional code result for instructions whose 's' bit is set, e.g. subs. 152198090Srdivackydef cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 153198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 154198090Srdivacky} 155198090Srdivacky 156198090Srdivacky// Same as cc_out except it defaults to setting CPSR. 157198090Srdivackydef s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 158198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 159198090Srdivacky} 160198090Srdivacky 161205218Srdivacky// ARM special operands for disassembly only. 162205218Srdivacky// 163205218Srdivacky 164205218Srdivackydef cps_opt : Operand<i32> { 165205218Srdivacky let PrintMethod = "printCPSOptionOperand"; 166205218Srdivacky} 167205218Srdivacky 168205218Srdivackydef msr_mask : Operand<i32> { 169205218Srdivacky let PrintMethod = "printMSRMaskOperand"; 170205218Srdivacky} 171205218Srdivacky 172205218Srdivacky// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. 173205218Srdivacky// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. 174205218Srdivackydef neg_zero : Operand<i32> { 175205218Srdivacky let PrintMethod = "printNegZeroOperand"; 176205218Srdivacky} 177205218Srdivacky 178198090Srdivacky//===----------------------------------------------------------------------===// 179198090Srdivacky 180193323Sed// ARM Instruction templates. 181193323Sed// 182193323Sed 183201360Srdivackyclass InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 184201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 185193323Sed : Instruction { 186193323Sed let Namespace = "ARM"; 187193323Sed 188193323Sed // TSFlagsFields 189193323Sed AddrMode AM = am; 190193323Sed bits<4> AddrModeBits = AM.Value; 191206083Srdivacky 192193323Sed SizeFlagVal SZ = sz; 193193323Sed bits<3> SizeFlag = SZ.Value; 194193323Sed 195193323Sed IndexMode IM = im; 196193323Sed bits<2> IndexModeBits = IM.Value; 197206083Srdivacky 198193323Sed Format F = f; 199205407Srdivacky bits<6> Form = F.Value; 200193323Sed 201198892Srdivacky Domain D = d; 202198892Srdivacky bits<2> Dom = D.Value; 203198892Srdivacky 204193323Sed // 205193323Sed // Attributes specific to ARM instructions... 206193323Sed // 207193323Sed bit isUnaryDataProc = 0; 208198090Srdivacky bit canXformTo16Bit = 0; 209206083Srdivacky 210193323Sed let Constraints = cstr; 211198090Srdivacky let Itinerary = itin; 212193323Sed} 213193323Sed 214201360Srdivackyclass Encoding { 215201360Srdivacky field bits<32> Inst; 216201360Srdivacky} 217201360Srdivacky 218201360Srdivackyclass InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 219201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 220201360Srdivacky : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 221201360Srdivacky 222201360Srdivacky// This Encoding-less class is used by Thumb1 to specify the encoding bits later 223201360Srdivacky// on by adding flavors to specific instructions. 224201360Srdivackyclass InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 225201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 226201360Srdivacky : InstTemplate<am, sz, im, f, d, cstr, itin>; 227201360Srdivacky 228206083Srdivackyclass PseudoInst<dag oops, dag iops, InstrItinClass itin, 229198090Srdivacky string asm, list<dag> pattern> 230206083Srdivacky : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 231198892Srdivacky "", itin> { 232193323Sed let OutOperandList = oops; 233193323Sed let InOperandList = iops; 234193323Sed let AsmString = asm; 235193323Sed let Pattern = pattern; 236193323Sed} 237193323Sed 238193323Sed// Almost all ARM instructions are predicable. 239193323Sedclass I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 240206083Srdivacky IndexMode im, Format f, InstrItinClass itin, 241198090Srdivacky string opc, string asm, string cstr, 242193323Sed list<dag> pattern> 243198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 244193323Sed let OutOperandList = oops; 245205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 246193323Sed let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 247193323Sed let Pattern = pattern; 248193323Sed list<Predicate> Predicates = [IsARM]; 249193323Sed} 250200581Srdivacky// A few are not predicable 251200581Srdivackyclass InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 252206083Srdivacky IndexMode im, Format f, InstrItinClass itin, 253206083Srdivacky string opc, string asm, string cstr, 254206083Srdivacky list<dag> pattern> 255200581Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 256200581Srdivacky let OutOperandList = oops; 257200581Srdivacky let InOperandList = iops; 258200581Srdivacky let AsmString = !strconcat(opc, asm); 259200581Srdivacky let Pattern = pattern; 260200581Srdivacky let isPredicable = 0; 261200581Srdivacky list<Predicate> Predicates = [IsARM]; 262200581Srdivacky} 263193323Sed 264193323Sed// Same as I except it can optionally modify CPSR. Note it's modeled as 265193323Sed// an input operand since by default it's a zero register. It will 266193323Sed// become an implicit def once it's "flipped". 267193323Sedclass sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 268198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 269198090Srdivacky string opc, string asm, string cstr, 270193323Sed list<dag> pattern> 271198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 272193323Sed let OutOperandList = oops; 273205407Srdivacky let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 274193323Sed let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); 275193323Sed let Pattern = pattern; 276193323Sed list<Predicate> Predicates = [IsARM]; 277193323Sed} 278193323Sed 279193323Sed// Special cases 280193323Sedclass XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 281198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 282198090Srdivacky string asm, string cstr, list<dag> pattern> 283198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 284193323Sed let OutOperandList = oops; 285193323Sed let InOperandList = iops; 286193323Sed let AsmString = asm; 287193323Sed let Pattern = pattern; 288193323Sed list<Predicate> Predicates = [IsARM]; 289193323Sed} 290193323Sed 291198090Srdivackyclass AI<dag oops, dag iops, Format f, InstrItinClass itin, 292198090Srdivacky string opc, string asm, list<dag> pattern> 293198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 294198090Srdivacky opc, asm, "", pattern>; 295198090Srdivackyclass AsI<dag oops, dag iops, Format f, InstrItinClass itin, 296198090Srdivacky string opc, string asm, list<dag> pattern> 297198090Srdivacky : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 298198090Srdivacky opc, asm, "", pattern>; 299198090Srdivackyclass AXI<dag oops, dag iops, Format f, InstrItinClass itin, 300193323Sed string asm, list<dag> pattern> 301198090Srdivacky : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 302193323Sed asm, "", pattern>; 303200581Srdivackyclass AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 304206083Srdivacky string opc, string asm, list<dag> pattern> 305200581Srdivacky : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 306206083Srdivacky opc, asm, "", pattern>; 307193323Sed 308193323Sed// Ctrl flow instructions 309198090Srdivackyclass ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 310198090Srdivacky string opc, string asm, list<dag> pattern> 311198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 312198090Srdivacky opc, asm, "", pattern> { 313193323Sed let Inst{27-24} = opcod; 314193323Sed} 315198090Srdivackyclass ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 316198090Srdivacky string asm, list<dag> pattern> 317198090Srdivacky : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 318198090Srdivacky asm, "", pattern> { 319193323Sed let Inst{27-24} = opcod; 320193323Sed} 321198090Srdivackyclass ABXIx2<dag oops, dag iops, InstrItinClass itin, 322198090Srdivacky string asm, list<dag> pattern> 323198090Srdivacky : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin, 324198090Srdivacky asm, "", pattern>; 325193323Sed 326193323Sed// BR_JT instructions 327198090Srdivackyclass JTI<dag oops, dag iops, InstrItinClass itin, 328198090Srdivacky string asm, list<dag> pattern> 329198090Srdivacky : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 330193323Sed asm, "", pattern>; 331193323Sed 332200581Srdivacky 333200581Srdivacky// Atomic load/store instructions 334200581Srdivacky 335200581Srdivackyclass AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 336200581Srdivacky string opc, string asm, list<dag> pattern> 337200581Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 338200581Srdivacky opc, asm, "", pattern> { 339200581Srdivacky let Inst{27-23} = 0b00011; 340200581Srdivacky let Inst{22-21} = opcod; 341200581Srdivacky let Inst{20} = 1; 342200581Srdivacky let Inst{11-0} = 0b111110011111; 343200581Srdivacky} 344200581Srdivackyclass AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 345200581Srdivacky string opc, string asm, list<dag> pattern> 346200581Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 347200581Srdivacky opc, asm, "", pattern> { 348200581Srdivacky let Inst{27-23} = 0b00011; 349200581Srdivacky let Inst{22-21} = opcod; 350200581Srdivacky let Inst{20} = 0; 351200581Srdivacky let Inst{11-4} = 0b11111001; 352200581Srdivacky} 353200581Srdivacky 354193323Sed// addrmode1 instructions 355198090Srdivackyclass AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 356198090Srdivacky string opc, string asm, list<dag> pattern> 357198090Srdivacky : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 358198090Srdivacky opc, asm, "", pattern> { 359193323Sed let Inst{24-21} = opcod; 360193323Sed let Inst{27-26} = {0,0}; 361193323Sed} 362198090Srdivackyclass AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 363198090Srdivacky string opc, string asm, list<dag> pattern> 364198090Srdivacky : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 365198090Srdivacky opc, asm, "", pattern> { 366193323Sed let Inst{24-21} = opcod; 367193323Sed let Inst{27-26} = {0,0}; 368193323Sed} 369198090Srdivackyclass AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 370198090Srdivacky string asm, list<dag> pattern> 371198090Srdivacky : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 372198090Srdivacky asm, "", pattern> { 373193323Sed let Inst{24-21} = opcod; 374193323Sed let Inst{27-26} = {0,0}; 375193323Sed} 376206083Srdivackyclass AI1x2<dag oops, dag iops, Format f, InstrItinClass itin, 377198090Srdivacky string opc, string asm, list<dag> pattern> 378198090Srdivacky : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin, 379198090Srdivacky opc, asm, "", pattern>; 380193323Sed 381193323Sed 382193323Sed// addrmode2 loads and stores 383198090Srdivackyclass AI2<dag oops, dag iops, Format f, InstrItinClass itin, 384198090Srdivacky string opc, string asm, list<dag> pattern> 385198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 386198090Srdivacky opc, asm, "", pattern> { 387193323Sed let Inst{27-26} = {0,1}; 388193323Sed} 389193323Sed 390193323Sed// loads 391198090Srdivackyclass AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 392198090Srdivacky string opc, string asm, list<dag> pattern> 393198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 394198090Srdivacky opc, asm, "", pattern> { 395193323Sed let Inst{20} = 1; // L bit 396193323Sed let Inst{21} = 0; // W bit 397193323Sed let Inst{22} = 0; // B bit 398193323Sed let Inst{24} = 1; // P bit 399193323Sed let Inst{27-26} = {0,1}; 400193323Sed} 401206083Srdivackyclass AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 402198090Srdivacky string asm, list<dag> pattern> 403198090Srdivacky : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 404193323Sed asm, "", pattern> { 405193323Sed let Inst{20} = 1; // L bit 406193323Sed let Inst{21} = 0; // W bit 407193323Sed let Inst{22} = 0; // B bit 408193323Sed let Inst{24} = 1; // P bit 409193323Sed let Inst{27-26} = {0,1}; 410193323Sed} 411198090Srdivackyclass AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 412198090Srdivacky string opc, string asm, list<dag> pattern> 413198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 414198090Srdivacky opc, asm, "", pattern> { 415193323Sed let Inst{20} = 1; // L bit 416193323Sed let Inst{21} = 0; // W bit 417193323Sed let Inst{22} = 1; // B bit 418193323Sed let Inst{24} = 1; // P bit 419193323Sed let Inst{27-26} = {0,1}; 420193323Sed} 421206083Srdivackyclass AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 422198090Srdivacky string asm, list<dag> pattern> 423198090Srdivacky : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 424193323Sed asm, "", pattern> { 425193323Sed let Inst{20} = 1; // L bit 426193323Sed let Inst{21} = 0; // W bit 427193323Sed let Inst{22} = 1; // B bit 428193323Sed let Inst{24} = 1; // P bit 429193323Sed let Inst{27-26} = {0,1}; 430193323Sed} 431193323Sed 432193323Sed// stores 433198090Srdivackyclass AI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 434198090Srdivacky string opc, string asm, list<dag> pattern> 435198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 436198090Srdivacky opc, asm, "", pattern> { 437193323Sed let Inst{20} = 0; // L bit 438193323Sed let Inst{21} = 0; // W bit 439193323Sed let Inst{22} = 0; // B bit 440193323Sed let Inst{24} = 1; // P bit 441193323Sed let Inst{27-26} = {0,1}; 442193323Sed} 443198090Srdivackyclass AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 444198090Srdivacky string asm, list<dag> pattern> 445198090Srdivacky : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 446193323Sed asm, "", pattern> { 447193323Sed let Inst{20} = 0; // L bit 448193323Sed let Inst{21} = 0; // W bit 449193323Sed let Inst{22} = 0; // B bit 450193323Sed let Inst{24} = 1; // P bit 451193323Sed let Inst{27-26} = {0,1}; 452193323Sed} 453198090Srdivackyclass AI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 454198090Srdivacky string opc, string asm, list<dag> pattern> 455198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 456198090Srdivacky opc, asm, "", pattern> { 457193323Sed let Inst{20} = 0; // L bit 458193323Sed let Inst{21} = 0; // W bit 459193323Sed let Inst{22} = 1; // B bit 460193323Sed let Inst{24} = 1; // P bit 461193323Sed let Inst{27-26} = {0,1}; 462193323Sed} 463198090Srdivackyclass AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 464198090Srdivacky string asm, list<dag> pattern> 465198090Srdivacky : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 466193323Sed asm, "", pattern> { 467193323Sed let Inst{20} = 0; // L bit 468193323Sed let Inst{21} = 0; // W bit 469193323Sed let Inst{22} = 1; // B bit 470193323Sed let Inst{24} = 1; // P bit 471193323Sed let Inst{27-26} = {0,1}; 472193323Sed} 473193323Sed 474193323Sed// Pre-indexed loads 475198090Srdivackyclass AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin, 476198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 477198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 478198090Srdivacky opc, asm, cstr, pattern> { 479193323Sed let Inst{20} = 1; // L bit 480193323Sed let Inst{21} = 1; // W bit 481193323Sed let Inst{22} = 0; // B bit 482193323Sed let Inst{24} = 1; // P bit 483193323Sed let Inst{27-26} = {0,1}; 484193323Sed} 485198090Srdivackyclass AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin, 486198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 487198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 488198090Srdivacky opc, asm, cstr, pattern> { 489193323Sed let Inst{20} = 1; // L bit 490193323Sed let Inst{21} = 1; // W bit 491193323Sed let Inst{22} = 1; // B bit 492193323Sed let Inst{24} = 1; // P bit 493193323Sed let Inst{27-26} = {0,1}; 494193323Sed} 495193323Sed 496193323Sed// Pre-indexed stores 497198090Srdivackyclass AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin, 498198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 499198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 500198090Srdivacky opc, asm, cstr, pattern> { 501193323Sed let Inst{20} = 0; // L bit 502193323Sed let Inst{21} = 1; // W bit 503193323Sed let Inst{22} = 0; // B bit 504193323Sed let Inst{24} = 1; // P bit 505193323Sed let Inst{27-26} = {0,1}; 506193323Sed} 507198090Srdivackyclass AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin, 508198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 509198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 510198090Srdivacky opc, asm, cstr, pattern> { 511193323Sed let Inst{20} = 0; // L bit 512193323Sed let Inst{21} = 1; // W bit 513193323Sed let Inst{22} = 1; // B bit 514193323Sed let Inst{24} = 1; // P bit 515193323Sed let Inst{27-26} = {0,1}; 516193323Sed} 517193323Sed 518193323Sed// Post-indexed loads 519198090Srdivackyclass AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin, 520198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 521198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 522198090Srdivacky opc, asm, cstr,pattern> { 523193323Sed let Inst{20} = 1; // L bit 524193323Sed let Inst{21} = 0; // W bit 525193323Sed let Inst{22} = 0; // B bit 526193323Sed let Inst{24} = 0; // P bit 527193323Sed let Inst{27-26} = {0,1}; 528193323Sed} 529198090Srdivackyclass AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin, 530198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 531198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 532198090Srdivacky opc, asm, cstr,pattern> { 533193323Sed let Inst{20} = 1; // L bit 534193323Sed let Inst{21} = 0; // W bit 535193323Sed let Inst{22} = 1; // B bit 536193323Sed let Inst{24} = 0; // P bit 537193323Sed let Inst{27-26} = {0,1}; 538193323Sed} 539193323Sed 540193323Sed// Post-indexed stores 541198090Srdivackyclass AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin, 542198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 543198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 544198090Srdivacky opc, asm, cstr,pattern> { 545193323Sed let Inst{20} = 0; // L bit 546193323Sed let Inst{21} = 0; // W bit 547193323Sed let Inst{22} = 0; // B bit 548193323Sed let Inst{24} = 0; // P bit 549193323Sed let Inst{27-26} = {0,1}; 550193323Sed} 551198090Srdivackyclass AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin, 552198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 553198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 554198090Srdivacky opc, asm, cstr,pattern> { 555193323Sed let Inst{20} = 0; // L bit 556193323Sed let Inst{21} = 0; // W bit 557193323Sed let Inst{22} = 1; // B bit 558193323Sed let Inst{24} = 0; // P bit 559193323Sed let Inst{27-26} = {0,1}; 560193323Sed} 561193323Sed 562193323Sed// addrmode3 instructions 563206083Srdivackyclass AI3<dag oops, dag iops, Format f, InstrItinClass itin, 564198090Srdivacky string opc, string asm, list<dag> pattern> 565198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 566198090Srdivacky opc, asm, "", pattern>; 567198090Srdivackyclass AXI3<dag oops, dag iops, Format f, InstrItinClass itin, 568198090Srdivacky string asm, list<dag> pattern> 569198090Srdivacky : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 570198090Srdivacky asm, "", pattern>; 571193323Sed 572193323Sed// loads 573198090Srdivackyclass AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 574198090Srdivacky string opc, string asm, list<dag> pattern> 575198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 576198090Srdivacky opc, asm, "", pattern> { 577193323Sed let Inst{4} = 1; 578193323Sed let Inst{5} = 1; // H bit 579193323Sed let Inst{6} = 0; // S bit 580193323Sed let Inst{7} = 1; 581193323Sed let Inst{20} = 1; // L bit 582193323Sed let Inst{21} = 0; // W bit 583193323Sed let Inst{24} = 1; // P bit 584198090Srdivacky let Inst{27-25} = 0b000; 585193323Sed} 586198090Srdivackyclass AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 587198090Srdivacky string asm, list<dag> pattern> 588198090Srdivacky : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 589193323Sed asm, "", pattern> { 590193323Sed let Inst{4} = 1; 591193323Sed let Inst{5} = 1; // H bit 592193323Sed let Inst{6} = 0; // S bit 593193323Sed let Inst{7} = 1; 594193323Sed let Inst{20} = 1; // L bit 595193323Sed let Inst{21} = 0; // W bit 596193323Sed let Inst{24} = 1; // P bit 597193323Sed} 598198090Srdivackyclass AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 599198090Srdivacky string opc, string asm, list<dag> pattern> 600198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 601198090Srdivacky opc, asm, "", pattern> { 602193323Sed let Inst{4} = 1; 603193323Sed let Inst{5} = 1; // H bit 604193323Sed let Inst{6} = 1; // S bit 605193323Sed let Inst{7} = 1; 606193323Sed let Inst{20} = 1; // L bit 607193323Sed let Inst{21} = 0; // W bit 608193323Sed let Inst{24} = 1; // P bit 609198090Srdivacky let Inst{27-25} = 0b000; 610193323Sed} 611198090Srdivackyclass AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 612198090Srdivacky string asm, list<dag> pattern> 613198090Srdivacky : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 614193323Sed asm, "", pattern> { 615193323Sed let Inst{4} = 1; 616193323Sed let Inst{5} = 1; // H bit 617193323Sed let Inst{6} = 1; // S bit 618193323Sed let Inst{7} = 1; 619193323Sed let Inst{20} = 1; // L bit 620193323Sed let Inst{21} = 0; // W bit 621193323Sed let Inst{24} = 1; // P bit 622193323Sed} 623198090Srdivackyclass AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 624198090Srdivacky string opc, string asm, list<dag> pattern> 625198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 626198090Srdivacky opc, asm, "", pattern> { 627193323Sed let Inst{4} = 1; 628193323Sed let Inst{5} = 0; // H bit 629193323Sed let Inst{6} = 1; // S bit 630193323Sed let Inst{7} = 1; 631193323Sed let Inst{20} = 1; // L bit 632193323Sed let Inst{21} = 0; // W bit 633193323Sed let Inst{24} = 1; // P bit 634198090Srdivacky let Inst{27-25} = 0b000; 635193323Sed} 636198090Srdivackyclass AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 637198090Srdivacky string asm, list<dag> pattern> 638198090Srdivacky : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 639193323Sed asm, "", pattern> { 640193323Sed let Inst{4} = 1; 641193323Sed let Inst{5} = 0; // H bit 642193323Sed let Inst{6} = 1; // S bit 643193323Sed let Inst{7} = 1; 644193323Sed let Inst{20} = 1; // L bit 645193323Sed let Inst{21} = 0; // W bit 646193323Sed let Inst{24} = 1; // P bit 647193323Sed} 648198090Srdivackyclass AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin, 649198090Srdivacky string opc, string asm, list<dag> pattern> 650198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 651198090Srdivacky opc, asm, "", pattern> { 652193323Sed let Inst{4} = 1; 653193323Sed let Inst{5} = 0; // H bit 654193323Sed let Inst{6} = 1; // S bit 655193323Sed let Inst{7} = 1; 656193323Sed let Inst{20} = 0; // L bit 657193323Sed let Inst{21} = 0; // W bit 658193323Sed let Inst{24} = 1; // P bit 659198090Srdivacky let Inst{27-25} = 0b000; 660193323Sed} 661193323Sed 662193323Sed// stores 663198090Srdivackyclass AI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 664198090Srdivacky string opc, string asm, list<dag> pattern> 665198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 666198090Srdivacky opc, asm, "", pattern> { 667193323Sed let Inst{4} = 1; 668193323Sed let Inst{5} = 1; // H bit 669193323Sed let Inst{6} = 0; // S bit 670193323Sed let Inst{7} = 1; 671193323Sed let Inst{20} = 0; // L bit 672193323Sed let Inst{21} = 0; // W bit 673193323Sed let Inst{24} = 1; // P bit 674198090Srdivacky let Inst{27-25} = 0b000; 675193323Sed} 676198090Srdivackyclass AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 677198090Srdivacky string asm, list<dag> pattern> 678198090Srdivacky : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 679193323Sed asm, "", pattern> { 680193323Sed let Inst{4} = 1; 681193323Sed let Inst{5} = 1; // H bit 682193323Sed let Inst{6} = 0; // S bit 683193323Sed let Inst{7} = 1; 684193323Sed let Inst{20} = 0; // L bit 685193323Sed let Inst{21} = 0; // W bit 686193323Sed let Inst{24} = 1; // P bit 687193323Sed} 688198090Srdivackyclass AI3std<dag oops, dag iops, Format f, InstrItinClass itin, 689198090Srdivacky string opc, string asm, list<dag> pattern> 690198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 691198090Srdivacky opc, asm, "", pattern> { 692193323Sed let Inst{4} = 1; 693193323Sed let Inst{5} = 1; // H bit 694193323Sed let Inst{6} = 1; // S bit 695193323Sed let Inst{7} = 1; 696193323Sed let Inst{20} = 0; // L bit 697193323Sed let Inst{21} = 0; // W bit 698193323Sed let Inst{24} = 1; // P bit 699198090Srdivacky let Inst{27-25} = 0b000; 700193323Sed} 701193323Sed 702193323Sed// Pre-indexed loads 703198090Srdivackyclass AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin, 704198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 705198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 706198090Srdivacky opc, asm, cstr, pattern> { 707193323Sed let Inst{4} = 1; 708193323Sed let Inst{5} = 1; // H bit 709193323Sed let Inst{6} = 0; // S bit 710193323Sed let Inst{7} = 1; 711193323Sed let Inst{20} = 1; // L bit 712193323Sed let Inst{21} = 1; // W bit 713193323Sed let Inst{24} = 1; // P bit 714198090Srdivacky let Inst{27-25} = 0b000; 715193323Sed} 716198090Srdivackyclass AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin, 717198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 718198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 719198090Srdivacky opc, asm, cstr, pattern> { 720193323Sed let Inst{4} = 1; 721193323Sed let Inst{5} = 1; // H bit 722193323Sed let Inst{6} = 1; // S bit 723193323Sed let Inst{7} = 1; 724193323Sed let Inst{20} = 1; // L bit 725193323Sed let Inst{21} = 1; // W bit 726193323Sed let Inst{24} = 1; // P bit 727198090Srdivacky let Inst{27-25} = 0b000; 728193323Sed} 729198090Srdivackyclass AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin, 730198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 731198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 732198090Srdivacky opc, asm, cstr, pattern> { 733193323Sed let Inst{4} = 1; 734193323Sed let Inst{5} = 0; // H bit 735193323Sed let Inst{6} = 1; // S bit 736193323Sed let Inst{7} = 1; 737193323Sed let Inst{20} = 1; // L bit 738193323Sed let Inst{21} = 1; // W bit 739193323Sed let Inst{24} = 1; // P bit 740198090Srdivacky let Inst{27-25} = 0b000; 741193323Sed} 742204642Srdivackyclass AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin, 743204642Srdivacky string opc, string asm, string cstr, list<dag> pattern> 744204642Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 745204642Srdivacky opc, asm, cstr, pattern> { 746204642Srdivacky let Inst{4} = 1; 747204642Srdivacky let Inst{5} = 0; // H bit 748204642Srdivacky let Inst{6} = 1; // S bit 749204642Srdivacky let Inst{7} = 1; 750204642Srdivacky let Inst{20} = 0; // L bit 751204642Srdivacky let Inst{21} = 1; // W bit 752204642Srdivacky let Inst{24} = 1; // P bit 753204642Srdivacky let Inst{27-25} = 0b000; 754204642Srdivacky} 755193323Sed 756204642Srdivacky 757193323Sed// Pre-indexed stores 758198090Srdivackyclass AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 759198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 760198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 761198090Srdivacky opc, asm, cstr, pattern> { 762193323Sed let Inst{4} = 1; 763193323Sed let Inst{5} = 1; // H bit 764193323Sed let Inst{6} = 0; // S bit 765193323Sed let Inst{7} = 1; 766193323Sed let Inst{20} = 0; // L bit 767193323Sed let Inst{21} = 1; // W bit 768193323Sed let Inst{24} = 1; // P bit 769198090Srdivacky let Inst{27-25} = 0b000; 770193323Sed} 771204642Srdivackyclass AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin, 772204642Srdivacky string opc, string asm, string cstr, list<dag> pattern> 773204642Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 774204642Srdivacky opc, asm, cstr, pattern> { 775204642Srdivacky let Inst{4} = 1; 776204642Srdivacky let Inst{5} = 1; // H bit 777204642Srdivacky let Inst{6} = 1; // S bit 778204642Srdivacky let Inst{7} = 1; 779204642Srdivacky let Inst{20} = 0; // L bit 780204642Srdivacky let Inst{21} = 1; // W bit 781204642Srdivacky let Inst{24} = 1; // P bit 782204642Srdivacky let Inst{27-25} = 0b000; 783204642Srdivacky} 784193323Sed 785193323Sed// Post-indexed loads 786198090Srdivackyclass AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin, 787198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 788198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 789198090Srdivacky opc, asm, cstr,pattern> { 790193323Sed let Inst{4} = 1; 791193323Sed let Inst{5} = 1; // H bit 792193323Sed let Inst{6} = 0; // S bit 793193323Sed let Inst{7} = 1; 794193323Sed let Inst{20} = 1; // L bit 795204642Srdivacky let Inst{21} = 0; // W bit 796193323Sed let Inst{24} = 0; // P bit 797198090Srdivacky let Inst{27-25} = 0b000; 798193323Sed} 799198090Srdivackyclass AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin, 800198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 801198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 802198090Srdivacky opc, asm, cstr,pattern> { 803193323Sed let Inst{4} = 1; 804193323Sed let Inst{5} = 1; // H bit 805193323Sed let Inst{6} = 1; // S bit 806193323Sed let Inst{7} = 1; 807193323Sed let Inst{20} = 1; // L bit 808204642Srdivacky let Inst{21} = 0; // W bit 809193323Sed let Inst{24} = 0; // P bit 810198090Srdivacky let Inst{27-25} = 0b000; 811193323Sed} 812198090Srdivackyclass AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin, 813198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 814198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 815198090Srdivacky opc, asm, cstr,pattern> { 816193323Sed let Inst{4} = 1; 817193323Sed let Inst{5} = 0; // H bit 818193323Sed let Inst{6} = 1; // S bit 819193323Sed let Inst{7} = 1; 820193323Sed let Inst{20} = 1; // L bit 821204642Srdivacky let Inst{21} = 0; // W bit 822193323Sed let Inst{24} = 0; // P bit 823198090Srdivacky let Inst{27-25} = 0b000; 824193323Sed} 825204642Srdivackyclass AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin, 826204642Srdivacky string opc, string asm, string cstr, list<dag> pattern> 827204642Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 828204642Srdivacky opc, asm, cstr, pattern> { 829204642Srdivacky let Inst{4} = 1; 830204642Srdivacky let Inst{5} = 0; // H bit 831204642Srdivacky let Inst{6} = 1; // S bit 832204642Srdivacky let Inst{7} = 1; 833204642Srdivacky let Inst{20} = 0; // L bit 834204642Srdivacky let Inst{21} = 0; // W bit 835204642Srdivacky let Inst{24} = 0; // P bit 836204642Srdivacky let Inst{27-25} = 0b000; 837204642Srdivacky} 838193323Sed 839193323Sed// Post-indexed stores 840198090Srdivackyclass AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 841198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 842198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 843198090Srdivacky opc, asm, cstr,pattern> { 844193323Sed let Inst{4} = 1; 845193323Sed let Inst{5} = 1; // H bit 846193323Sed let Inst{6} = 0; // S bit 847193323Sed let Inst{7} = 1; 848193323Sed let Inst{20} = 0; // L bit 849204642Srdivacky let Inst{21} = 0; // W bit 850193323Sed let Inst{24} = 0; // P bit 851198090Srdivacky let Inst{27-25} = 0b000; 852193323Sed} 853204642Srdivackyclass AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin, 854204642Srdivacky string opc, string asm, string cstr, list<dag> pattern> 855204642Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 856204642Srdivacky opc, asm, cstr, pattern> { 857204642Srdivacky let Inst{4} = 1; 858204642Srdivacky let Inst{5} = 1; // H bit 859204642Srdivacky let Inst{6} = 1; // S bit 860204642Srdivacky let Inst{7} = 1; 861204642Srdivacky let Inst{20} = 0; // L bit 862204642Srdivacky let Inst{21} = 0; // W bit 863204642Srdivacky let Inst{24} = 0; // P bit 864204642Srdivacky let Inst{27-25} = 0b000; 865204642Srdivacky} 866193323Sed 867193323Sed// addrmode4 instructions 868205218Srdivackyclass AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 869205218Srdivacky string asm, string cstr, list<dag> pattern> 870205218Srdivacky : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, 871205218Srdivacky asm, cstr, pattern> { 872193323Sed let Inst{20} = 1; // L bit 873193323Sed let Inst{22} = 0; // S bit 874193323Sed let Inst{27-25} = 0b100; 875193323Sed} 876205218Srdivackyclass AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 877205218Srdivacky string asm, string cstr, list<dag> pattern> 878205218Srdivacky : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, 879205218Srdivacky asm, cstr, pattern> { 880193323Sed let Inst{20} = 0; // L bit 881193323Sed let Inst{22} = 0; // S bit 882193323Sed let Inst{27-25} = 0b100; 883193323Sed} 884193323Sed 885193323Sed// Unsigned multiply, multiply-accumulate instructions. 886198090Srdivackyclass AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 887198090Srdivacky string opc, string asm, list<dag> pattern> 888198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 889198090Srdivacky opc, asm, "", pattern> { 890193323Sed let Inst{7-4} = 0b1001; 891193323Sed let Inst{20} = 0; // S bit 892193323Sed let Inst{27-21} = opcod; 893193323Sed} 894198090Srdivackyclass AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 895198090Srdivacky string opc, string asm, list<dag> pattern> 896198090Srdivacky : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 897198090Srdivacky opc, asm, "", pattern> { 898193323Sed let Inst{7-4} = 0b1001; 899193323Sed let Inst{27-21} = opcod; 900193323Sed} 901193323Sed 902193323Sed// Most significant word multiply 903198090Srdivackyclass AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 904198090Srdivacky string opc, string asm, list<dag> pattern> 905198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 906198090Srdivacky opc, asm, "", pattern> { 907193323Sed let Inst{7-4} = 0b1001; 908193323Sed let Inst{20} = 1; 909193323Sed let Inst{27-21} = opcod; 910193323Sed} 911193323Sed 912193323Sed// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 913198090Srdivackyclass AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 914198090Srdivacky string opc, string asm, list<dag> pattern> 915198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 916198090Srdivacky opc, asm, "", pattern> { 917193323Sed let Inst{4} = 0; 918193323Sed let Inst{7} = 1; 919193323Sed let Inst{20} = 0; 920193323Sed let Inst{27-21} = opcod; 921193323Sed} 922193323Sed 923193323Sed// Extend instructions. 924198090Srdivackyclass AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 925198090Srdivacky string opc, string asm, list<dag> pattern> 926198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 927198090Srdivacky opc, asm, "", pattern> { 928193323Sed let Inst{7-4} = 0b0111; 929193323Sed let Inst{27-20} = opcod; 930193323Sed} 931193323Sed 932193323Sed// Misc Arithmetic instructions. 933198090Srdivackyclass AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 934198090Srdivacky string opc, string asm, list<dag> pattern> 935198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 936198090Srdivacky opc, asm, "", pattern> { 937193323Sed let Inst{27-20} = opcod; 938193323Sed} 939193323Sed 940193323Sed//===----------------------------------------------------------------------===// 941193323Sed 942193323Sed// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 943193323Sedclass ARMPat<dag pattern, dag result> : Pat<pattern, result> { 944193323Sed list<Predicate> Predicates = [IsARM]; 945193323Sed} 946193323Sedclass ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 947193323Sed list<Predicate> Predicates = [IsARM, HasV5TE]; 948193323Sed} 949193323Sedclass ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 950193323Sed list<Predicate> Predicates = [IsARM, HasV6]; 951193323Sed} 952193323Sed 953193323Sed//===----------------------------------------------------------------------===// 954193323Sed// 955193323Sed// Thumb Instruction Format Definitions. 956193323Sed// 957193323Sed 958193323Sed// TI - Thumb instruction. 959193323Sed 960198090Srdivackyclass ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 961198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 962201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 963198090Srdivacky let OutOperandList = oops; 964198090Srdivacky let InOperandList = iops; 965193323Sed let AsmString = asm; 966193323Sed let Pattern = pattern; 967193323Sed list<Predicate> Predicates = [IsThumb]; 968193323Sed} 969193323Sed 970198090Srdivackyclass TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 971198090Srdivacky : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 972193323Sed 973198090Srdivacky// Two-address instructions 974206083Srdivackyclass TIt<dag oops, dag iops, InstrItinClass itin, string asm, 975206083Srdivacky list<dag> pattern> 976206083Srdivacky : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", 977206083Srdivacky pattern>; 978193323Sed 979201360Srdivacky// tBL, tBX 32-bit instructions 980201360Srdivackyclass TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 981206083Srdivacky dag oops, dag iops, InstrItinClass itin, string asm, 982206083Srdivacky list<dag> pattern> 983206083Srdivacky : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, 984206083Srdivacky Encoding { 985201360Srdivacky let Inst{31-27} = opcod1; 986201360Srdivacky let Inst{15-14} = opcod2; 987201360Srdivacky let Inst{12} = opcod3; 988201360Srdivacky} 989198090Srdivacky 990193323Sed// BR_JT instructions 991206083Srdivackyclass TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 992206083Srdivacky list<dag> pattern> 993198090Srdivacky : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 994193323Sed 995198090Srdivacky// Thumb1 only 996198090Srdivackyclass Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 997198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 998201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 999198090Srdivacky let OutOperandList = oops; 1000198090Srdivacky let InOperandList = iops; 1001198090Srdivacky let AsmString = asm; 1002198090Srdivacky let Pattern = pattern; 1003198090Srdivacky list<Predicate> Predicates = [IsThumb1Only]; 1004194710Sed} 1005193323Sed 1006198090Srdivackyclass T1I<dag oops, dag iops, InstrItinClass itin, 1007198090Srdivacky string asm, list<dag> pattern> 1008198090Srdivacky : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 1009198090Srdivackyclass T1Ix2<dag oops, dag iops, InstrItinClass itin, 1010198090Srdivacky string asm, list<dag> pattern> 1011198090Srdivacky : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1012198090Srdivackyclass T1JTI<dag oops, dag iops, InstrItinClass itin, 1013198090Srdivacky string asm, list<dag> pattern> 1014198090Srdivacky : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1015194710Sed 1016198090Srdivacky// Two-address instructions 1017198090Srdivackyclass T1It<dag oops, dag iops, InstrItinClass itin, 1018205218Srdivacky string asm, string cstr, list<dag> pattern> 1019206083Srdivacky : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 1020205218Srdivacky asm, cstr, pattern>; 1021198090Srdivacky 1022198090Srdivacky// Thumb1 instruction that can either be predicated or set CPSR. 1023198090Srdivackyclass Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1024198090Srdivacky InstrItinClass itin, 1025198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1026201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1027205407Srdivacky let OutOperandList = !con(oops, (outs s_cc_out:$s)); 1028205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1029198090Srdivacky let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 1030194754Sed let Pattern = pattern; 1031195098Sed list<Predicate> Predicates = [IsThumb1Only]; 1032195098Sed} 1033195098Sed 1034198090Srdivackyclass T1sI<dag oops, dag iops, InstrItinClass itin, 1035198090Srdivacky string opc, string asm, list<dag> pattern> 1036198090Srdivacky : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 1037195098Sed 1038195098Sed// Two-address instructions 1039198090Srdivackyclass T1sIt<dag oops, dag iops, InstrItinClass itin, 1040198090Srdivacky string opc, string asm, list<dag> pattern> 1041198090Srdivacky : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 1042206083Srdivacky "$lhs = $dst", pattern>; 1043195098Sed 1044198090Srdivacky// Thumb1 instruction that can be predicated. 1045198090Srdivackyclass Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1046198090Srdivacky InstrItinClass itin, 1047198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1048201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1049198090Srdivacky let OutOperandList = oops; 1050205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1051198090Srdivacky let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1052198090Srdivacky let Pattern = pattern; 1053195098Sed list<Predicate> Predicates = [IsThumb1Only]; 1054195098Sed} 1055195098Sed 1056198090Srdivackyclass T1pI<dag oops, dag iops, InstrItinClass itin, 1057198090Srdivacky string opc, string asm, list<dag> pattern> 1058198090Srdivacky : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 1059198090Srdivacky 1060198090Srdivacky// Two-address instructions 1061198090Srdivackyclass T1pIt<dag oops, dag iops, InstrItinClass itin, 1062198090Srdivacky string opc, string asm, list<dag> pattern> 1063198090Srdivacky : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 1064206083Srdivacky "$lhs = $dst", pattern>; 1065198090Srdivacky 1066198090Srdivackyclass T1pI1<dag oops, dag iops, InstrItinClass itin, 1067198090Srdivacky string opc, string asm, list<dag> pattern> 1068198090Srdivacky : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>; 1069198090Srdivackyclass T1pI2<dag oops, dag iops, InstrItinClass itin, 1070198090Srdivacky string opc, string asm, list<dag> pattern> 1071198090Srdivacky : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>; 1072198090Srdivackyclass T1pI4<dag oops, dag iops, InstrItinClass itin, 1073198090Srdivacky string opc, string asm, list<dag> pattern> 1074198090Srdivacky : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>; 1075206083Srdivackyclass T1pIs<dag oops, dag iops, 1076198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1077198090Srdivacky : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 1078198090Srdivacky 1079201360Srdivackyclass Encoding16 : Encoding { 1080201360Srdivacky let Inst{31-16} = 0x0000; 1081201360Srdivacky} 1082201360Srdivacky 1083201360Srdivacky// A6.2 16-bit Thumb instruction encoding 1084201360Srdivackyclass T1Encoding<bits<6> opcode> : Encoding16 { 1085201360Srdivacky let Inst{15-10} = opcode; 1086201360Srdivacky} 1087201360Srdivacky 1088201360Srdivacky// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1089201360Srdivackyclass T1General<bits<5> opcode> : Encoding16 { 1090201360Srdivacky let Inst{15-14} = 0b00; 1091201360Srdivacky let Inst{13-9} = opcode; 1092201360Srdivacky} 1093201360Srdivacky 1094201360Srdivacky// A6.2.2 Data-processing encoding. 1095201360Srdivackyclass T1DataProcessing<bits<4> opcode> : Encoding16 { 1096201360Srdivacky let Inst{15-10} = 0b010000; 1097201360Srdivacky let Inst{9-6} = opcode; 1098201360Srdivacky} 1099201360Srdivacky 1100201360Srdivacky// A6.2.3 Special data instructions and branch and exchange encoding. 1101201360Srdivackyclass T1Special<bits<4> opcode> : Encoding16 { 1102201360Srdivacky let Inst{15-10} = 0b010001; 1103201360Srdivacky let Inst{9-6} = opcode; 1104201360Srdivacky} 1105201360Srdivacky 1106201360Srdivacky// A6.2.4 Load/store single data item encoding. 1107201360Srdivackyclass T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1108201360Srdivacky let Inst{15-12} = opA; 1109201360Srdivacky let Inst{11-9} = opB; 1110201360Srdivacky} 1111201360Srdivackyclass T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>; 1112201360Srdivackyclass T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes 1113201360Srdivackyclass T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte 1114201360Srdivackyclass T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes 1115201360Srdivackyclass T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1116201360Srdivacky 1117201360Srdivacky// A6.2.5 Miscellaneous 16-bit instructions encoding. 1118201360Srdivackyclass T1Misc<bits<7> opcode> : Encoding16 { 1119201360Srdivacky let Inst{15-12} = 0b1011; 1120201360Srdivacky let Inst{11-5} = opcode; 1121201360Srdivacky} 1122201360Srdivacky 1123195098Sed// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1124195098Sedclass Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1125198090Srdivacky InstrItinClass itin, 1126195098Sed string opc, string asm, string cstr, list<dag> pattern> 1127198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1128195098Sed let OutOperandList = oops; 1129205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1130195098Sed let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1131195098Sed let Pattern = pattern; 1132195340Sed list<Predicate> Predicates = [IsThumb2]; 1133194754Sed} 1134194754Sed 1135195098Sed// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as 1136195098Sed// an input operand since by default it's a zero register. It will 1137195098Sed// become an implicit def once it's "flipped". 1138195098Sed// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1139195098Sed// more consistent. 1140195098Sedclass Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1141198090Srdivacky InstrItinClass itin, 1142195098Sed string opc, string asm, string cstr, list<dag> pattern> 1143198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1144195098Sed let OutOperandList = oops; 1145205407Srdivacky let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1146195098Sed let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 1147195098Sed let Pattern = pattern; 1148195340Sed list<Predicate> Predicates = [IsThumb2]; 1149195098Sed} 1150194754Sed 1151195098Sed// Special cases 1152195098Sedclass Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1153198090Srdivacky InstrItinClass itin, 1154195098Sed string asm, string cstr, list<dag> pattern> 1155198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1156195098Sed let OutOperandList = oops; 1157195098Sed let InOperandList = iops; 1158195098Sed let AsmString = asm; 1159195098Sed let Pattern = pattern; 1160195340Sed list<Predicate> Predicates = [IsThumb2]; 1161194754Sed} 1162194754Sed 1163200581Srdivackyclass ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1164206083Srdivacky InstrItinClass itin, 1165206083Srdivacky string asm, string cstr, list<dag> pattern> 1166200581Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1167200581Srdivacky let OutOperandList = oops; 1168200581Srdivacky let InOperandList = iops; 1169200581Srdivacky let AsmString = asm; 1170200581Srdivacky let Pattern = pattern; 1171200581Srdivacky list<Predicate> Predicates = [IsThumb1Only]; 1172200581Srdivacky} 1173200581Srdivacky 1174198090Srdivackyclass T2I<dag oops, dag iops, InstrItinClass itin, 1175198090Srdivacky string opc, string asm, list<dag> pattern> 1176198090Srdivacky : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1177198090Srdivackyclass T2Ii12<dag oops, dag iops, InstrItinClass itin, 1178198090Srdivacky string opc, string asm, list<dag> pattern> 1179206083Srdivacky : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>; 1180198090Srdivackyclass T2Ii8<dag oops, dag iops, InstrItinClass itin, 1181198090Srdivacky string opc, string asm, list<dag> pattern> 1182198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 1183198090Srdivackyclass T2Iso<dag oops, dag iops, InstrItinClass itin, 1184198090Srdivacky string opc, string asm, list<dag> pattern> 1185198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 1186198090Srdivackyclass T2Ipc<dag oops, dag iops, InstrItinClass itin, 1187198090Srdivacky string opc, string asm, list<dag> pattern> 1188198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1189201360Srdivackyclass T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin, 1190198090Srdivacky string opc, string asm, list<dag> pattern> 1191201360Srdivacky : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1192201360Srdivacky pattern> { 1193201360Srdivacky let Inst{31-27} = 0b11101; 1194201360Srdivacky let Inst{26-25} = 0b00; 1195201360Srdivacky let Inst{24} = P; 1196201360Srdivacky let Inst{23} = ?; // The U bit. 1197201360Srdivacky let Inst{22} = 1; 1198201360Srdivacky let Inst{21} = W; 1199201360Srdivacky let Inst{20} = load; 1200201360Srdivacky} 1201195098Sed 1202198090Srdivackyclass T2sI<dag oops, dag iops, InstrItinClass itin, 1203198090Srdivacky string opc, string asm, list<dag> pattern> 1204198090Srdivacky : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1205195098Sed 1206198090Srdivackyclass T2XI<dag oops, dag iops, InstrItinClass itin, 1207198090Srdivacky string asm, list<dag> pattern> 1208198090Srdivacky : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1209198090Srdivackyclass T2JTI<dag oops, dag iops, InstrItinClass itin, 1210198090Srdivacky string asm, list<dag> pattern> 1211198090Srdivacky : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1212195098Sed 1213198090Srdivackyclass T2Ix2<dag oops, dag iops, InstrItinClass itin, 1214206083Srdivacky string opc, string asm, list<dag> pattern> 1215198090Srdivacky : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>; 1216198090Srdivacky 1217205218Srdivacky// Two-address instructions 1218205218Srdivackyclass T2XIt<dag oops, dag iops, InstrItinClass itin, 1219205218Srdivacky string asm, string cstr, list<dag> pattern> 1220205218Srdivacky : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>; 1221198090Srdivacky 1222195340Sed// T2Iidxldst - Thumb2 indexed load / store instructions. 1223201360Srdivackyclass T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1224201360Srdivacky dag oops, dag iops, 1225201360Srdivacky AddrMode am, IndexMode im, InstrItinClass itin, 1226195340Sed string opc, string asm, string cstr, list<dag> pattern> 1227198892Srdivacky : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1228195340Sed let OutOperandList = oops; 1229205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1230195340Sed let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1231195340Sed let Pattern = pattern; 1232195340Sed list<Predicate> Predicates = [IsThumb2]; 1233201360Srdivacky let Inst{31-27} = 0b11111; 1234201360Srdivacky let Inst{26-25} = 0b00; 1235201360Srdivacky let Inst{24} = signed; 1236201360Srdivacky let Inst{23} = 0; 1237201360Srdivacky let Inst{22-21} = opcod; 1238201360Srdivacky let Inst{20} = load; 1239201360Srdivacky let Inst{11} = 1; 1240201360Srdivacky // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1241201360Srdivacky let Inst{10} = pre; // The P bit. 1242201360Srdivacky let Inst{8} = 1; // The W bit. 1243195340Sed} 1244195340Sed 1245204642Srdivacky// Helper class for disassembly only 1246204642Srdivacky// A6.3.16 & A6.3.17 1247204642Srdivacky// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions. 1248204642Srdivackyclass T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops, 1249204642Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1250204642Srdivacky : T2I<oops, iops, itin, opc, asm, pattern> { 1251204642Srdivacky let Inst{31-27} = 0b11111; 1252204642Srdivacky let Inst{26-24} = 0b011; 1253204642Srdivacky let Inst{23} = long; 1254204642Srdivacky let Inst{22-20} = op22_20; 1255204642Srdivacky let Inst{7-4} = op7_4; 1256204642Srdivacky} 1257204642Srdivacky 1258198090Srdivacky// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1259198090Srdivackyclass Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1260198090Srdivacky list<Predicate> Predicates = [IsThumb1Only, HasV5T]; 1261198090Srdivacky} 1262195340Sed 1263198090Srdivacky// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1264198090Srdivackyclass T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1265198090Srdivacky list<Predicate> Predicates = [IsThumb1Only]; 1266198090Srdivacky} 1267198090Srdivacky 1268195098Sed// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1269195098Sedclass T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1270195340Sed list<Predicate> Predicates = [IsThumb2]; 1271195098Sed} 1272195098Sed 1273193323Sed//===----------------------------------------------------------------------===// 1274193323Sed 1275193323Sed//===----------------------------------------------------------------------===// 1276193323Sed// ARM VFP Instruction templates. 1277193323Sed// 1278193323Sed 1279198090Srdivacky// Almost all VFP instructions are predicable. 1280198090Srdivackyclass VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1281198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1282198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1283198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1284198090Srdivacky let OutOperandList = oops; 1285205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1286198090Srdivacky let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1287198090Srdivacky let Pattern = pattern; 1288198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1289198090Srdivacky} 1290198090Srdivacky 1291198090Srdivacky// Special cases 1292198090Srdivackyclass VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1293198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1294198090Srdivacky string asm, string cstr, list<dag> pattern> 1295198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1296198090Srdivacky let OutOperandList = oops; 1297198090Srdivacky let InOperandList = iops; 1298198090Srdivacky let AsmString = asm; 1299198090Srdivacky let Pattern = pattern; 1300198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1301198090Srdivacky} 1302198090Srdivacky 1303198090Srdivackyclass VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1304198090Srdivacky string opc, string asm, list<dag> pattern> 1305198090Srdivacky : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1306198090Srdivacky opc, asm, "", pattern>; 1307198090Srdivacky 1308193323Sed// ARM VFP addrmode5 loads and stores 1309193323Sedclass ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1310198090Srdivacky InstrItinClass itin, 1311193323Sed string opc, string asm, list<dag> pattern> 1312198090Srdivacky : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1313206083Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1314193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1315193323Sed let Inst{27-24} = opcod1; 1316193323Sed let Inst{21-20} = opcod2; 1317193323Sed let Inst{11-8} = 0b1011; 1318198892Srdivacky 1319198892Srdivacky // 64-bit loads & stores operate on both NEON and VFP pipelines. 1320198892Srdivacky let Dom = VFPNeonDomain.Value; 1321193323Sed} 1322193323Sed 1323193323Sedclass ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1324198090Srdivacky InstrItinClass itin, 1325193323Sed string opc, string asm, list<dag> pattern> 1326198090Srdivacky : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1327206083Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1328193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1329193323Sed let Inst{27-24} = opcod1; 1330193323Sed let Inst{21-20} = opcod2; 1331193323Sed let Inst{11-8} = 0b1010; 1332193323Sed} 1333193323Sed 1334193323Sed// Load / store multiple 1335205218Srdivackyclass AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1336205218Srdivacky string asm, string cstr, list<dag> pattern> 1337205218Srdivacky : VFPXI<oops, iops, AddrMode5, Size4Bytes, im, 1338206083Srdivacky VFPLdStMulFrm, itin, asm, cstr, pattern> { 1339193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1340193323Sed let Inst{27-25} = 0b110; 1341193323Sed let Inst{11-8} = 0b1011; 1342198892Srdivacky 1343198892Srdivacky // 64-bit loads & stores operate on both NEON and VFP pipelines. 1344198892Srdivacky let Dom = VFPNeonDomain.Value; 1345193323Sed} 1346193323Sed 1347205218Srdivackyclass AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1348205218Srdivacky string asm, string cstr, list<dag> pattern> 1349205218Srdivacky : VFPXI<oops, iops, AddrMode5, Size4Bytes, im, 1350206083Srdivacky VFPLdStMulFrm, itin, asm, cstr, pattern> { 1351193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1352193323Sed let Inst{27-25} = 0b110; 1353193323Sed let Inst{11-8} = 0b1010; 1354193323Sed} 1355193323Sed 1356193323Sed// Double precision, unary 1357203954Srdivackyclass ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1358203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1359203954Srdivacky string asm, list<dag> pattern> 1360198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1361203954Srdivacky let Inst{27-23} = opcod1; 1362203954Srdivacky let Inst{21-20} = opcod2; 1363203954Srdivacky let Inst{19-16} = opcod3; 1364193323Sed let Inst{11-8} = 0b1011; 1365203954Srdivacky let Inst{7-6} = opcod4; 1366203954Srdivacky let Inst{4} = opcod5; 1367193323Sed} 1368193323Sed 1369193323Sed// Double precision, binary 1370203954Srdivackyclass ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1371206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1372206083Srdivacky list<dag> pattern> 1373198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1374203954Srdivacky let Inst{27-23} = opcod1; 1375203954Srdivacky let Inst{21-20} = opcod2; 1376193323Sed let Inst{11-8} = 0b1011; 1377203954Srdivacky let Inst{6} = op6; 1378203954Srdivacky let Inst{4} = op4; 1379193323Sed} 1380193323Sed 1381206083Srdivacky// Double precision, binary, VML[AS] (for additional predicate) 1382206083Srdivackyclass ADbI_vmlX<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1383206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1384206083Srdivacky list<dag> pattern> 1385206083Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1386206083Srdivacky let Inst{27-23} = opcod1; 1387206083Srdivacky let Inst{21-20} = opcod2; 1388206083Srdivacky let Inst{11-8} = 0b1011; 1389206083Srdivacky let Inst{6} = op6; 1390206083Srdivacky let Inst{4} = op4; 1391206083Srdivacky list<Predicate> Predicates = [HasVFP2, UseVMLx]; 1392206083Srdivacky} 1393206083Srdivacky 1394206083Srdivacky 1395193323Sed// Single precision, unary 1396203954Srdivackyclass ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1397203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1398203954Srdivacky string asm, list<dag> pattern> 1399198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1400203954Srdivacky let Inst{27-23} = opcod1; 1401203954Srdivacky let Inst{21-20} = opcod2; 1402203954Srdivacky let Inst{19-16} = opcod3; 1403193323Sed let Inst{11-8} = 0b1010; 1404203954Srdivacky let Inst{7-6} = opcod4; 1405203954Srdivacky let Inst{4} = opcod5; 1406193323Sed} 1407193323Sed 1408198090Srdivacky// Single precision unary, if no NEON 1409198090Srdivacky// Same as ASuI except not available if NEON is enabled 1410203954Srdivackyclass ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1411203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1412203954Srdivacky string asm, list<dag> pattern> 1413203954Srdivacky : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1414203954Srdivacky pattern> { 1415198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1416198090Srdivacky} 1417198090Srdivacky 1418193323Sed// Single precision, binary 1419203954Srdivackyclass ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1420203954Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1421198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1422203954Srdivacky let Inst{27-23} = opcod1; 1423203954Srdivacky let Inst{21-20} = opcod2; 1424193323Sed let Inst{11-8} = 0b1010; 1425203954Srdivacky let Inst{6} = op6; 1426203954Srdivacky let Inst{4} = op4; 1427193323Sed} 1428193323Sed 1429198090Srdivacky// Single precision binary, if no NEON 1430198090Srdivacky// Same as ASbI except not available if NEON is enabled 1431203954Srdivackyclass ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1432206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1433206083Srdivacky list<dag> pattern> 1434203954Srdivacky : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1435198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1436198090Srdivacky} 1437198090Srdivacky 1438193323Sed// VFP conversion instructions 1439203954Srdivackyclass AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1440203954Srdivacky dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1441203954Srdivacky list<dag> pattern> 1442198090Srdivacky : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1443203954Srdivacky let Inst{27-23} = opcod1; 1444203954Srdivacky let Inst{21-20} = opcod2; 1445203954Srdivacky let Inst{19-16} = opcod3; 1446203954Srdivacky let Inst{11-8} = opcod4; 1447193323Sed let Inst{6} = 1; 1448203954Srdivacky let Inst{4} = 0; 1449193323Sed} 1450193323Sed 1451203954Srdivacky// VFP conversion between floating-point and fixed-point 1452203954Srdivackyclass AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1453206083Srdivacky dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1454206083Srdivacky list<dag> pattern> 1455203954Srdivacky : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1456203954Srdivacky // size (fixed-point number): sx == 0 ? 16 : 32 1457203954Srdivacky let Inst{7} = op5; // sx 1458203954Srdivacky} 1459203954Srdivacky 1460198090Srdivacky// VFP conversion instructions, if no NEON 1461203954Srdivackyclass AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1462198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1463198090Srdivacky string opc, string asm, list<dag> pattern> 1464203954Srdivacky : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1465203954Srdivacky pattern> { 1466198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1467198090Srdivacky} 1468198090Srdivacky 1469193323Sedclass AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1470198090Srdivacky InstrItinClass itin, 1471198090Srdivacky string opc, string asm, list<dag> pattern> 1472198090Srdivacky : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1473193323Sed let Inst{27-20} = opcod1; 1474193323Sed let Inst{11-8} = opcod2; 1475193323Sed let Inst{4} = 1; 1476193323Sed} 1477193323Sed 1478198090Srdivackyclass AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1479198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1480198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1481193323Sed 1482206083Srdivackyclass AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1483198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1484198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1485193323Sed 1486198090Srdivackyclass AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1487198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1488198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1489193323Sed 1490198090Srdivackyclass AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1491198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1492198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1493193323Sed 1494193323Sed//===----------------------------------------------------------------------===// 1495193323Sed 1496194710Sed//===----------------------------------------------------------------------===// 1497194710Sed// ARM NEON Instruction templates. 1498194710Sed// 1499193323Sed 1500205407Srdivackyclass NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1501205407Srdivacky InstrItinClass itin, string opc, string dt, string asm, string cstr, 1502205407Srdivacky list<dag> pattern> 1503205407Srdivacky : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1504194710Sed let OutOperandList = oops; 1505205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1506199989Srdivacky let AsmString = !strconcat( 1507199989Srdivacky !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), 1508199989Srdivacky !strconcat("\t", asm)); 1509194710Sed let Pattern = pattern; 1510194710Sed list<Predicate> Predicates = [HasNEON]; 1511193323Sed} 1512193323Sed 1513199989Srdivacky// Same as NeonI except it does not have a "data type" specifier. 1514206083Srdivackyclass NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1515206083Srdivacky InstrItinClass itin, string opc, string asm, string cstr, 1516206083Srdivacky list<dag> pattern> 1517206083Srdivacky : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1518199989Srdivacky let OutOperandList = oops; 1519205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1520199989Srdivacky let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm)); 1521199989Srdivacky let Pattern = pattern; 1522199989Srdivacky list<Predicate> Predicates = [HasNEON]; 1523193323Sed} 1524194710Sed 1525198090Srdivackyclass NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1526198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1527199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1528205407Srdivacky : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1529205407Srdivacky cstr, pattern> { 1530198090Srdivacky let Inst{31-24} = 0b11110100; 1531198396Srdivacky let Inst{23} = op23; 1532198396Srdivacky let Inst{21-20} = op21_20; 1533198396Srdivacky let Inst{11-8} = op11_8; 1534198396Srdivacky let Inst{7-4} = op7_4; 1535198090Srdivacky} 1536198090Srdivacky 1537206083Srdivackyclass NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1538199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1539206083Srdivacky : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1540206083Srdivacky pattern> { 1541194710Sed let Inst{31-25} = 0b1111001; 1542194710Sed} 1543194710Sed 1544206083Srdivackyclass NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1545206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1546206083Srdivacky : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1547206083Srdivacky cstr, pattern> { 1548199989Srdivacky let Inst{31-25} = 0b1111001; 1549199989Srdivacky} 1550199989Srdivacky 1551194710Sed// NEON "one register and a modified immediate" format. 1552194710Sedclass N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1553194710Sed bit op5, bit op4, 1554198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1555206083Srdivacky string opc, string dt, string asm, string cstr, 1556206083Srdivacky list<dag> pattern> 1557206083Srdivacky : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1558194710Sed let Inst{23} = op23; 1559194710Sed let Inst{21-19} = op21_19; 1560194710Sed let Inst{11-8} = op11_8; 1561194710Sed let Inst{7} = op7; 1562194710Sed let Inst{6} = op6; 1563194710Sed let Inst{5} = op5; 1564194710Sed let Inst{4} = op4; 1565194710Sed} 1566194710Sed 1567194710Sed// NEON 2 vector register format. 1568194710Sedclass N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1569194710Sed bits<5> op11_7, bit op6, bit op4, 1570198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1571199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1572206083Srdivacky : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 1573194710Sed let Inst{24-23} = op24_23; 1574194710Sed let Inst{21-20} = op21_20; 1575194710Sed let Inst{19-18} = op19_18; 1576194710Sed let Inst{17-16} = op17_16; 1577194710Sed let Inst{11-7} = op11_7; 1578194710Sed let Inst{6} = op6; 1579194710Sed let Inst{4} = op4; 1580194710Sed} 1581194710Sed 1582199989Srdivacky// Same as N2V except it doesn't have a datatype suffix. 1583199989Srdivackyclass N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1584206083Srdivacky bits<5> op11_7, bit op6, bit op4, 1585206083Srdivacky dag oops, dag iops, InstrItinClass itin, 1586206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1587206083Srdivacky : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 1588198396Srdivacky let Inst{24-23} = op24_23; 1589198396Srdivacky let Inst{21-20} = op21_20; 1590199989Srdivacky let Inst{19-18} = op19_18; 1591199989Srdivacky let Inst{17-16} = op17_16; 1592198396Srdivacky let Inst{11-7} = op11_7; 1593198396Srdivacky let Inst{6} = op6; 1594198396Srdivacky let Inst{4} = op4; 1595198396Srdivacky} 1596198396Srdivacky 1597194710Sed// NEON 2 vector register with immediate. 1598198396Srdivackyclass N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1599206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1600199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1601206083Srdivacky : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1602194710Sed let Inst{24} = op24; 1603194710Sed let Inst{23} = op23; 1604194710Sed let Inst{11-8} = op11_8; 1605194710Sed let Inst{7} = op7; 1606194710Sed let Inst{6} = op6; 1607194710Sed let Inst{4} = op4; 1608194710Sed} 1609194710Sed 1610194710Sed// NEON 3 vector register format. 1611194710Sedclass N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1612206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1613199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1614206083Srdivacky : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1615194710Sed let Inst{24} = op24; 1616194710Sed let Inst{23} = op23; 1617194710Sed let Inst{21-20} = op21_20; 1618194710Sed let Inst{11-8} = op11_8; 1619194710Sed let Inst{6} = op6; 1620194710Sed let Inst{4} = op4; 1621194710Sed} 1622194710Sed 1623206083Srdivacky// Same as N3V except it doesn't have a data type suffix. 1624206083Srdivackyclass N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1625206083Srdivacky bit op4, 1626206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1627206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1628206083Srdivacky : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 1629198396Srdivacky let Inst{24} = op24; 1630198396Srdivacky let Inst{23} = op23; 1631198396Srdivacky let Inst{21-20} = op21_20; 1632199989Srdivacky let Inst{11-8} = op11_8; 1633198396Srdivacky let Inst{6} = op6; 1634198396Srdivacky let Inst{4} = op4; 1635198396Srdivacky} 1636198396Srdivacky 1637194710Sed// NEON VMOVs between scalar and core registers. 1638194710Sedclass NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1639198090Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1640199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1641199989Srdivacky : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain, 1642206083Srdivacky "", itin> { 1643194710Sed let Inst{27-20} = opcod1; 1644194710Sed let Inst{11-8} = opcod2; 1645194710Sed let Inst{6-5} = opcod3; 1646194710Sed let Inst{4} = 1; 1647199989Srdivacky 1648199989Srdivacky let OutOperandList = oops; 1649205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1650199989Srdivacky let AsmString = !strconcat( 1651199989Srdivacky !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), 1652199989Srdivacky !strconcat("\t", asm)); 1653199989Srdivacky let Pattern = pattern; 1654194710Sed list<Predicate> Predicates = [HasNEON]; 1655194710Sed} 1656194710Sedclass NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1657198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1658199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1659198090Srdivacky : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin, 1660199989Srdivacky opc, dt, asm, pattern>; 1661194710Sedclass NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1662198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1663199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1664198090Srdivacky : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin, 1665199989Srdivacky opc, dt, asm, pattern>; 1666194710Sedclass NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1667198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1668199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1669198090Srdivacky : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin, 1670199989Srdivacky opc, dt, asm, pattern>; 1671198090Srdivacky 1672206083Srdivacky// Vector Duplicate Lane (from scalar to all elements) 1673206083Srdivackyclass NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 1674206083Srdivacky InstrItinClass itin, string opc, string dt, string asm, 1675206083Srdivacky list<dag> pattern> 1676206083Srdivacky : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 1677206083Srdivacky let Inst{24-23} = 0b11; 1678206083Srdivacky let Inst{21-20} = 0b11; 1679206083Srdivacky let Inst{19-16} = op19_16; 1680206083Srdivacky let Inst{11-7} = 0b11000; 1681206083Srdivacky let Inst{6} = op6; 1682206083Srdivacky let Inst{4} = 0; 1683206083Srdivacky} 1684206083Srdivacky 1685198090Srdivacky// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1686198090Srdivacky// for single-precision FP. 1687198090Srdivackyclass NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1688198090Srdivacky list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1689198090Srdivacky} 1690