ARMInstrFormats.td revision 195340
1193323Sed//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// 12193323Sed// ARM Instruction Format Definitions. 13193323Sed// 14193323Sed 15193323Sed// Format specifies the encoding used by the instruction. This is part of the 16193323Sed// ad-hoc solution used to emit machine instruction encodings by our machine 17193323Sed// code emitter. 18193323Sedclass Format<bits<5> val> { 19193323Sed bits<5> Value = val; 20193323Sed} 21193323Sed 22193323Seddef Pseudo : Format<0>; 23193323Seddef MulFrm : Format<1>; 24193323Seddef BrFrm : Format<2>; 25193323Seddef BrMiscFrm : Format<3>; 26193323Sed 27193323Seddef DPFrm : Format<4>; 28193323Seddef DPSoRegFrm : Format<5>; 29193323Sed 30193323Seddef LdFrm : Format<6>; 31193323Seddef StFrm : Format<7>; 32193323Seddef LdMiscFrm : Format<8>; 33193323Seddef StMiscFrm : Format<9>; 34193323Seddef LdStMulFrm : Format<10>; 35193323Sed 36193323Seddef ArithMiscFrm : Format<11>; 37193323Seddef ExtFrm : Format<12>; 38193323Sed 39193323Seddef VFPUnaryFrm : Format<13>; 40193323Seddef VFPBinaryFrm : Format<14>; 41193323Seddef VFPConv1Frm : Format<15>; 42193323Seddef VFPConv2Frm : Format<16>; 43193323Seddef VFPConv3Frm : Format<17>; 44193323Seddef VFPConv4Frm : Format<18>; 45193323Seddef VFPConv5Frm : Format<19>; 46193323Seddef VFPLdStFrm : Format<20>; 47193323Seddef VFPLdStMulFrm : Format<21>; 48193323Seddef VFPMiscFrm : Format<22>; 49193323Sed 50193323Seddef ThumbFrm : Format<23>; 51193323Sed 52194710Seddef NEONFrm : Format<24>; 53194710Seddef NEONGetLnFrm : Format<25>; 54194710Seddef NEONSetLnFrm : Format<26>; 55194710Seddef NEONDupFrm : Format<27>; 56194710Sed 57193323Sed// Misc flag for data processing instructions that indicates whether 58193323Sed// the instruction has a Rn register operand. 59193323Sedclass UnaryDP { bit isUnaryDataProc = 1; } 60193323Sed 61193323Sed//===----------------------------------------------------------------------===// 62195340Sed// ARM Instruction flags. These need to match ARMInstrInfo.h. 63195340Sed// 64193323Sed 65195340Sed// Addressing mode. 66195340Sedclass AddrMode<bits<4> val> { 67195340Sed bits<4> Value = val; 68195340Sed} 69195340Seddef AddrModeNone : AddrMode<0>; 70195340Seddef AddrMode1 : AddrMode<1>; 71195340Seddef AddrMode2 : AddrMode<2>; 72195340Seddef AddrMode3 : AddrMode<3>; 73195340Seddef AddrMode4 : AddrMode<4>; 74195340Seddef AddrMode5 : AddrMode<5>; 75195340Seddef AddrMode6 : AddrMode<6>; 76195340Seddef AddrModeT1_1 : AddrMode<7>; 77195340Seddef AddrModeT1_2 : AddrMode<8>; 78195340Seddef AddrModeT1_4 : AddrMode<9>; 79195340Seddef AddrModeT1_s : AddrMode<10>; 80195340Seddef AddrModeT2_i12: AddrMode<12>; 81195340Seddef AddrModeT2_i8 : AddrMode<12>; 82195340Seddef AddrModeT2_so : AddrMode<13>; 83195340Seddef AddrModeT2_pc : AddrMode<14>; 84195340Seddef AddrModeT2_i8s4 : AddrMode<15>; 85195340Sed 86195340Sed// Instruction size. 87195340Sedclass SizeFlagVal<bits<3> val> { 88195340Sed bits<3> Value = val; 89195340Sed} 90195340Seddef SizeInvalid : SizeFlagVal<0>; // Unset. 91195340Seddef SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 92195340Seddef Size8Bytes : SizeFlagVal<2>; 93195340Seddef Size4Bytes : SizeFlagVal<3>; 94195340Seddef Size2Bytes : SizeFlagVal<4>; 95195340Sed 96195340Sed// Load / store index mode. 97195340Sedclass IndexMode<bits<2> val> { 98195340Sed bits<2> Value = val; 99195340Sed} 100195340Seddef IndexModeNone : IndexMode<0>; 101195340Seddef IndexModePre : IndexMode<1>; 102195340Seddef IndexModePost : IndexMode<2>; 103195340Sed 104195340Sed//===----------------------------------------------------------------------===// 105195340Sed 106193323Sed// ARM Instruction templates. 107193323Sed// 108193323Sed 109193323Sedclass InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 110193323Sed Format f, string cstr> 111193323Sed : Instruction { 112193323Sed field bits<32> Inst; 113193323Sed 114193323Sed let Namespace = "ARM"; 115193323Sed 116193323Sed // TSFlagsFields 117193323Sed AddrMode AM = am; 118193323Sed bits<4> AddrModeBits = AM.Value; 119193323Sed 120193323Sed SizeFlagVal SZ = sz; 121193323Sed bits<3> SizeFlag = SZ.Value; 122193323Sed 123193323Sed IndexMode IM = im; 124193323Sed bits<2> IndexModeBits = IM.Value; 125193323Sed 126193323Sed Format F = f; 127193323Sed bits<5> Form = F.Value; 128193323Sed 129193323Sed // 130193323Sed // Attributes specific to ARM instructions... 131193323Sed // 132193323Sed bit isUnaryDataProc = 0; 133193323Sed 134193323Sed let Constraints = cstr; 135193323Sed} 136193323Sed 137193323Sedclass PseudoInst<dag oops, dag iops, string asm, list<dag> pattern> 138193323Sed : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> { 139193323Sed let OutOperandList = oops; 140193323Sed let InOperandList = iops; 141193323Sed let AsmString = asm; 142193323Sed let Pattern = pattern; 143193323Sed} 144193323Sed 145193323Sed// Almost all ARM instructions are predicable. 146193323Sedclass I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 147193323Sed IndexMode im, Format f, string opc, string asm, string cstr, 148193323Sed list<dag> pattern> 149193323Sed : InstARM<am, sz, im, f, cstr> { 150193323Sed let OutOperandList = oops; 151193323Sed let InOperandList = !con(iops, (ops pred:$p)); 152193323Sed let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 153193323Sed let Pattern = pattern; 154193323Sed list<Predicate> Predicates = [IsARM]; 155193323Sed} 156193323Sed 157193323Sed// Same as I except it can optionally modify CPSR. Note it's modeled as 158193323Sed// an input operand since by default it's a zero register. It will 159193323Sed// become an implicit def once it's "flipped". 160193323Sedclass sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 161193323Sed IndexMode im, Format f, string opc, string asm, string cstr, 162193323Sed list<dag> pattern> 163193323Sed : InstARM<am, sz, im, f, cstr> { 164193323Sed let OutOperandList = oops; 165193323Sed let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 166193323Sed let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); 167193323Sed let Pattern = pattern; 168193323Sed list<Predicate> Predicates = [IsARM]; 169193323Sed} 170193323Sed 171193323Sed// Special cases 172193323Sedclass XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 173193323Sed IndexMode im, Format f, string asm, string cstr, list<dag> pattern> 174193323Sed : InstARM<am, sz, im, f, cstr> { 175193323Sed let OutOperandList = oops; 176193323Sed let InOperandList = iops; 177193323Sed let AsmString = asm; 178193323Sed let Pattern = pattern; 179193323Sed list<Predicate> Predicates = [IsARM]; 180193323Sed} 181193323Sed 182193323Sedclass AI<dag oops, dag iops, Format f, string opc, 183193323Sed string asm, list<dag> pattern> 184193323Sed : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 185193323Sed asm, "", pattern>; 186193323Sedclass AsI<dag oops, dag iops, Format f, string opc, 187193323Sed string asm, list<dag> pattern> 188193323Sed : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 189193323Sed asm, "", pattern>; 190193323Sedclass AXI<dag oops, dag iops, Format f, string asm, 191193323Sed list<dag> pattern> 192193323Sed : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, 193193323Sed "", pattern>; 194193323Sed 195193323Sed// Ctrl flow instructions 196193323Sedclass ABI<bits<4> opcod, dag oops, dag iops, string opc, 197193323Sed string asm, list<dag> pattern> 198193323Sed : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc, 199193323Sed asm, "", pattern> { 200193323Sed let Inst{27-24} = opcod; 201193323Sed} 202193323Sedclass ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> 203193323Sed : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm, 204193323Sed "", pattern> { 205193323Sed let Inst{27-24} = opcod; 206193323Sed} 207193323Sedclass ABXIx2<dag oops, dag iops, string asm, list<dag> pattern> 208193323Sed : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm, 209193323Sed "", pattern>; 210193323Sed 211193323Sed// BR_JT instructions 212193323Sedclass JTI<dag oops, dag iops, string asm, list<dag> pattern> 213193323Sed : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, 214193323Sed asm, "", pattern>; 215193323Sed 216193323Sed// addrmode1 instructions 217193323Sedclass AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, 218193323Sed string asm, list<dag> pattern> 219193323Sed : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, 220193323Sed asm, "", pattern> { 221193323Sed let Inst{24-21} = opcod; 222193323Sed let Inst{27-26} = {0,0}; 223193323Sed} 224193323Sedclass AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, 225193323Sed string asm, list<dag> pattern> 226193323Sed : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, 227193323Sed asm, "", pattern> { 228193323Sed let Inst{24-21} = opcod; 229193323Sed let Inst{27-26} = {0,0}; 230193323Sed} 231193323Sedclass AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm, 232193323Sed list<dag> pattern> 233193323Sed : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm, 234193323Sed "", pattern> { 235193323Sed let Inst{24-21} = opcod; 236193323Sed let Inst{27-26} = {0,0}; 237193323Sed} 238193323Sedclass AI1x2<dag oops, dag iops, Format f, string opc, 239193323Sed string asm, list<dag> pattern> 240193323Sed : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc, 241193323Sed asm, "", pattern>; 242193323Sed 243193323Sed 244193323Sed// addrmode2 loads and stores 245193323Sedclass AI2<dag oops, dag iops, Format f, string opc, 246193323Sed string asm, list<dag> pattern> 247193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 248193323Sed asm, "", pattern> { 249193323Sed let Inst{27-26} = {0,1}; 250193323Sed} 251193323Sed 252193323Sed// loads 253193323Sedclass AI2ldw<dag oops, dag iops, Format f, string opc, 254193323Sed string asm, list<dag> pattern> 255193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 256193323Sed asm, "", pattern> { 257193323Sed let Inst{20} = 1; // L bit 258193323Sed let Inst{21} = 0; // W bit 259193323Sed let Inst{22} = 0; // B bit 260193323Sed let Inst{24} = 1; // P bit 261193323Sed let Inst{27-26} = {0,1}; 262193323Sed} 263193323Sedclass AXI2ldw<dag oops, dag iops, Format f, string asm, 264193323Sed list<dag> pattern> 265193323Sed : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 266193323Sed asm, "", pattern> { 267193323Sed let Inst{20} = 1; // L bit 268193323Sed let Inst{21} = 0; // W bit 269193323Sed let Inst{22} = 0; // B bit 270193323Sed let Inst{24} = 1; // P bit 271193323Sed let Inst{27-26} = {0,1}; 272193323Sed} 273193323Sedclass AI2ldb<dag oops, dag iops, Format f, string opc, 274193323Sed string asm, list<dag> pattern> 275193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 276193323Sed asm, "", pattern> { 277193323Sed let Inst{20} = 1; // L bit 278193323Sed let Inst{21} = 0; // W bit 279193323Sed let Inst{22} = 1; // B bit 280193323Sed let Inst{24} = 1; // P bit 281193323Sed let Inst{27-26} = {0,1}; 282193323Sed} 283193323Sedclass AXI2ldb<dag oops, dag iops, Format f, string asm, 284193323Sed list<dag> pattern> 285193323Sed : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 286193323Sed asm, "", pattern> { 287193323Sed let Inst{20} = 1; // L bit 288193323Sed let Inst{21} = 0; // W bit 289193323Sed let Inst{22} = 1; // B bit 290193323Sed let Inst{24} = 1; // P bit 291193323Sed let Inst{27-26} = {0,1}; 292193323Sed} 293193323Sed 294193323Sed// stores 295193323Sedclass AI2stw<dag oops, dag iops, Format f, string opc, 296193323Sed string asm, list<dag> pattern> 297193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 298193323Sed asm, "", pattern> { 299193323Sed let Inst{20} = 0; // L bit 300193323Sed let Inst{21} = 0; // W bit 301193323Sed let Inst{22} = 0; // B bit 302193323Sed let Inst{24} = 1; // P bit 303193323Sed let Inst{27-26} = {0,1}; 304193323Sed} 305193323Sedclass AXI2stw<dag oops, dag iops, Format f, string asm, 306193323Sed list<dag> pattern> 307193323Sed : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 308193323Sed asm, "", pattern> { 309193323Sed let Inst{20} = 0; // L bit 310193323Sed let Inst{21} = 0; // W bit 311193323Sed let Inst{22} = 0; // B bit 312193323Sed let Inst{24} = 1; // P bit 313193323Sed let Inst{27-26} = {0,1}; 314193323Sed} 315193323Sedclass AI2stb<dag oops, dag iops, Format f, string opc, 316193323Sed string asm, list<dag> pattern> 317193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 318193323Sed asm, "", pattern> { 319193323Sed let Inst{20} = 0; // L bit 320193323Sed let Inst{21} = 0; // W bit 321193323Sed let Inst{22} = 1; // B bit 322193323Sed let Inst{24} = 1; // P bit 323193323Sed let Inst{27-26} = {0,1}; 324193323Sed} 325193323Sedclass AXI2stb<dag oops, dag iops, Format f, string asm, 326193323Sed list<dag> pattern> 327193323Sed : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 328193323Sed asm, "", pattern> { 329193323Sed let Inst{20} = 0; // L bit 330193323Sed let Inst{21} = 0; // W bit 331193323Sed let Inst{22} = 1; // B bit 332193323Sed let Inst{24} = 1; // P bit 333193323Sed let Inst{27-26} = {0,1}; 334193323Sed} 335193323Sed 336193323Sed// Pre-indexed loads 337193323Sedclass AI2ldwpr<dag oops, dag iops, Format f, string opc, 338193323Sed string asm, string cstr, list<dag> pattern> 339193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 340193323Sed asm, cstr, pattern> { 341193323Sed let Inst{20} = 1; // L bit 342193323Sed let Inst{21} = 1; // W bit 343193323Sed let Inst{22} = 0; // B bit 344193323Sed let Inst{24} = 1; // P bit 345193323Sed let Inst{27-26} = {0,1}; 346193323Sed} 347193323Sedclass AI2ldbpr<dag oops, dag iops, Format f, string opc, 348193323Sed string asm, string cstr, list<dag> pattern> 349193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 350193323Sed asm, cstr, pattern> { 351193323Sed let Inst{20} = 1; // L bit 352193323Sed let Inst{21} = 1; // W bit 353193323Sed let Inst{22} = 1; // B bit 354193323Sed let Inst{24} = 1; // P bit 355193323Sed let Inst{27-26} = {0,1}; 356193323Sed} 357193323Sed 358193323Sed// Pre-indexed stores 359193323Sedclass AI2stwpr<dag oops, dag iops, Format f, string opc, 360193323Sed string asm, string cstr, list<dag> pattern> 361193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 362193323Sed asm, cstr, pattern> { 363193323Sed let Inst{20} = 0; // L bit 364193323Sed let Inst{21} = 1; // W bit 365193323Sed let Inst{22} = 0; // B bit 366193323Sed let Inst{24} = 1; // P bit 367193323Sed let Inst{27-26} = {0,1}; 368193323Sed} 369193323Sedclass AI2stbpr<dag oops, dag iops, Format f, string opc, 370193323Sed string asm, string cstr, list<dag> pattern> 371193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 372193323Sed asm, cstr, pattern> { 373193323Sed let Inst{20} = 0; // L bit 374193323Sed let Inst{21} = 1; // W bit 375193323Sed let Inst{22} = 1; // B bit 376193323Sed let Inst{24} = 1; // P bit 377193323Sed let Inst{27-26} = {0,1}; 378193323Sed} 379193323Sed 380193323Sed// Post-indexed loads 381193323Sedclass AI2ldwpo<dag oops, dag iops, Format f, string opc, 382193323Sed string asm, string cstr, list<dag> pattern> 383193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 384193323Sed asm, cstr,pattern> { 385193323Sed let Inst{20} = 1; // L bit 386193323Sed let Inst{21} = 0; // W bit 387193323Sed let Inst{22} = 0; // B bit 388193323Sed let Inst{24} = 0; // P bit 389193323Sed let Inst{27-26} = {0,1}; 390193323Sed} 391193323Sedclass AI2ldbpo<dag oops, dag iops, Format f, string opc, 392193323Sed string asm, string cstr, list<dag> pattern> 393193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 394193323Sed asm, cstr,pattern> { 395193323Sed let Inst{20} = 1; // L bit 396193323Sed let Inst{21} = 0; // W bit 397193323Sed let Inst{22} = 1; // B bit 398193323Sed let Inst{24} = 0; // P bit 399193323Sed let Inst{27-26} = {0,1}; 400193323Sed} 401193323Sed 402193323Sed// Post-indexed stores 403193323Sedclass AI2stwpo<dag oops, dag iops, Format f, string opc, 404193323Sed string asm, string cstr, list<dag> pattern> 405193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 406193323Sed asm, cstr,pattern> { 407193323Sed let Inst{20} = 0; // L bit 408193323Sed let Inst{21} = 0; // W bit 409193323Sed let Inst{22} = 0; // B bit 410193323Sed let Inst{24} = 0; // P bit 411193323Sed let Inst{27-26} = {0,1}; 412193323Sed} 413193323Sedclass AI2stbpo<dag oops, dag iops, Format f, string opc, 414193323Sed string asm, string cstr, list<dag> pattern> 415193323Sed : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 416193323Sed asm, cstr,pattern> { 417193323Sed let Inst{20} = 0; // L bit 418193323Sed let Inst{21} = 0; // W bit 419193323Sed let Inst{22} = 1; // B bit 420193323Sed let Inst{24} = 0; // P bit 421193323Sed let Inst{27-26} = {0,1}; 422193323Sed} 423193323Sed 424193323Sed// addrmode3 instructions 425193323Sedclass AI3<dag oops, dag iops, Format f, string opc, 426193323Sed string asm, list<dag> pattern> 427193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 428193323Sed asm, "", pattern>; 429193323Sedclass AXI3<dag oops, dag iops, Format f, string asm, 430193323Sed list<dag> pattern> 431193323Sed : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, 432193323Sed "", pattern>; 433193323Sed 434193323Sed// loads 435193323Sedclass AI3ldh<dag oops, dag iops, Format f, string opc, 436193323Sed string asm, list<dag> pattern> 437193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 438193323Sed asm, "", pattern> { 439193323Sed let Inst{4} = 1; 440193323Sed let Inst{5} = 1; // H bit 441193323Sed let Inst{6} = 0; // S bit 442193323Sed let Inst{7} = 1; 443193323Sed let Inst{20} = 1; // L bit 444193323Sed let Inst{21} = 0; // W bit 445193323Sed let Inst{24} = 1; // P bit 446193323Sed} 447193323Sedclass AXI3ldh<dag oops, dag iops, Format f, string asm, 448193323Sed list<dag> pattern> 449193323Sed : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 450193323Sed asm, "", pattern> { 451193323Sed let Inst{4} = 1; 452193323Sed let Inst{5} = 1; // H bit 453193323Sed let Inst{6} = 0; // S bit 454193323Sed let Inst{7} = 1; 455193323Sed let Inst{20} = 1; // L bit 456193323Sed let Inst{21} = 0; // W bit 457193323Sed let Inst{24} = 1; // P bit 458193323Sed} 459193323Sedclass AI3ldsh<dag oops, dag iops, Format f, string opc, 460193323Sed string asm, list<dag> pattern> 461193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 462193323Sed asm, "", pattern> { 463193323Sed let Inst{4} = 1; 464193323Sed let Inst{5} = 1; // H bit 465193323Sed let Inst{6} = 1; // S bit 466193323Sed let Inst{7} = 1; 467193323Sed let Inst{20} = 1; // L bit 468193323Sed let Inst{21} = 0; // W bit 469193323Sed let Inst{24} = 1; // P bit 470193323Sed} 471193323Sedclass AXI3ldsh<dag oops, dag iops, Format f, string asm, 472193323Sed list<dag> pattern> 473193323Sed : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 474193323Sed asm, "", pattern> { 475193323Sed let Inst{4} = 1; 476193323Sed let Inst{5} = 1; // H bit 477193323Sed let Inst{6} = 1; // S bit 478193323Sed let Inst{7} = 1; 479193323Sed let Inst{20} = 1; // L bit 480193323Sed let Inst{21} = 0; // W bit 481193323Sed let Inst{24} = 1; // P bit 482193323Sed} 483193323Sedclass AI3ldsb<dag oops, dag iops, Format f, string opc, 484193323Sed string asm, list<dag> pattern> 485193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 486193323Sed asm, "", pattern> { 487193323Sed let Inst{4} = 1; 488193323Sed let Inst{5} = 0; // H bit 489193323Sed let Inst{6} = 1; // S bit 490193323Sed let Inst{7} = 1; 491193323Sed let Inst{20} = 1; // L bit 492193323Sed let Inst{21} = 0; // W bit 493193323Sed let Inst{24} = 1; // P bit 494193323Sed} 495193323Sedclass AXI3ldsb<dag oops, dag iops, Format f, string asm, 496193323Sed list<dag> pattern> 497193323Sed : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 498193323Sed asm, "", pattern> { 499193323Sed let Inst{4} = 1; 500193323Sed let Inst{5} = 0; // H bit 501193323Sed let Inst{6} = 1; // S bit 502193323Sed let Inst{7} = 1; 503193323Sed let Inst{20} = 1; // L bit 504193323Sed let Inst{21} = 0; // W bit 505193323Sed let Inst{24} = 1; // P bit 506193323Sed} 507193323Sedclass AI3ldd<dag oops, dag iops, Format f, string opc, 508193323Sed string asm, list<dag> pattern> 509193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 510193323Sed asm, "", pattern> { 511193323Sed let Inst{4} = 1; 512193323Sed let Inst{5} = 0; // H bit 513193323Sed let Inst{6} = 1; // S bit 514193323Sed let Inst{7} = 1; 515193323Sed let Inst{20} = 0; // L bit 516193323Sed let Inst{21} = 0; // W bit 517193323Sed let Inst{24} = 1; // P bit 518193323Sed} 519193323Sed 520193323Sed// stores 521193323Sedclass AI3sth<dag oops, dag iops, Format f, string opc, 522193323Sed string asm, list<dag> pattern> 523193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 524193323Sed asm, "", pattern> { 525193323Sed let Inst{4} = 1; 526193323Sed let Inst{5} = 1; // H bit 527193323Sed let Inst{6} = 0; // S bit 528193323Sed let Inst{7} = 1; 529193323Sed let Inst{20} = 0; // L bit 530193323Sed let Inst{21} = 0; // W bit 531193323Sed let Inst{24} = 1; // P bit 532193323Sed} 533193323Sedclass AXI3sth<dag oops, dag iops, Format f, string asm, 534193323Sed list<dag> pattern> 535193323Sed : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 536193323Sed asm, "", pattern> { 537193323Sed let Inst{4} = 1; 538193323Sed let Inst{5} = 1; // H bit 539193323Sed let Inst{6} = 0; // S bit 540193323Sed let Inst{7} = 1; 541193323Sed let Inst{20} = 0; // L bit 542193323Sed let Inst{21} = 0; // W bit 543193323Sed let Inst{24} = 1; // P bit 544193323Sed} 545193323Sedclass AI3std<dag oops, dag iops, Format f, string opc, 546193323Sed string asm, list<dag> pattern> 547193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 548193323Sed asm, "", pattern> { 549193323Sed let Inst{4} = 1; 550193323Sed let Inst{5} = 1; // H bit 551193323Sed let Inst{6} = 1; // S bit 552193323Sed let Inst{7} = 1; 553193323Sed let Inst{20} = 0; // L bit 554193323Sed let Inst{21} = 0; // W bit 555193323Sed let Inst{24} = 1; // P bit 556193323Sed} 557193323Sed 558193323Sed// Pre-indexed loads 559193323Sedclass AI3ldhpr<dag oops, dag iops, Format f, string opc, 560193323Sed string asm, string cstr, list<dag> pattern> 561193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 562193323Sed asm, cstr, pattern> { 563193323Sed let Inst{4} = 1; 564193323Sed let Inst{5} = 1; // H bit 565193323Sed let Inst{6} = 0; // S bit 566193323Sed let Inst{7} = 1; 567193323Sed let Inst{20} = 1; // L bit 568193323Sed let Inst{21} = 1; // W bit 569193323Sed let Inst{24} = 1; // P bit 570193323Sed} 571193323Sedclass AI3ldshpr<dag oops, dag iops, Format f, string opc, 572193323Sed string asm, string cstr, list<dag> pattern> 573193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 574193323Sed asm, cstr, pattern> { 575193323Sed let Inst{4} = 1; 576193323Sed let Inst{5} = 1; // H bit 577193323Sed let Inst{6} = 1; // S bit 578193323Sed let Inst{7} = 1; 579193323Sed let Inst{20} = 1; // L bit 580193323Sed let Inst{21} = 1; // W bit 581193323Sed let Inst{24} = 1; // P bit 582193323Sed} 583193323Sedclass AI3ldsbpr<dag oops, dag iops, Format f, string opc, 584193323Sed string asm, string cstr, list<dag> pattern> 585193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 586193323Sed asm, cstr, pattern> { 587193323Sed let Inst{4} = 1; 588193323Sed let Inst{5} = 0; // H bit 589193323Sed let Inst{6} = 1; // S bit 590193323Sed let Inst{7} = 1; 591193323Sed let Inst{20} = 1; // L bit 592193323Sed let Inst{21} = 1; // W bit 593193323Sed let Inst{24} = 1; // P bit 594193323Sed} 595193323Sed 596193323Sed// Pre-indexed stores 597193323Sedclass AI3sthpr<dag oops, dag iops, Format f, string opc, 598193323Sed string asm, string cstr, list<dag> pattern> 599193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 600193323Sed asm, cstr, pattern> { 601193323Sed let Inst{4} = 1; 602193323Sed let Inst{5} = 1; // H bit 603193323Sed let Inst{6} = 0; // S bit 604193323Sed let Inst{7} = 1; 605193323Sed let Inst{20} = 0; // L bit 606193323Sed let Inst{21} = 1; // W bit 607193323Sed let Inst{24} = 1; // P bit 608193323Sed} 609193323Sed 610193323Sed// Post-indexed loads 611193323Sedclass AI3ldhpo<dag oops, dag iops, Format f, string opc, 612193323Sed string asm, string cstr, list<dag> pattern> 613193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 614193323Sed asm, cstr,pattern> { 615193323Sed let Inst{4} = 1; 616193323Sed let Inst{5} = 1; // H bit 617193323Sed let Inst{6} = 0; // S bit 618193323Sed let Inst{7} = 1; 619193323Sed let Inst{20} = 1; // L bit 620193323Sed let Inst{21} = 1; // W bit 621193323Sed let Inst{24} = 0; // P bit 622193323Sed} 623193323Sedclass AI3ldshpo<dag oops, dag iops, Format f, string opc, 624193323Sed string asm, string cstr, list<dag> pattern> 625193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 626193323Sed asm, cstr,pattern> { 627193323Sed let Inst{4} = 1; 628193323Sed let Inst{5} = 1; // H bit 629193323Sed let Inst{6} = 1; // S bit 630193323Sed let Inst{7} = 1; 631193323Sed let Inst{20} = 1; // L bit 632193323Sed let Inst{21} = 1; // W bit 633193323Sed let Inst{24} = 0; // P bit 634193323Sed} 635193323Sedclass AI3ldsbpo<dag oops, dag iops, Format f, string opc, 636193323Sed string asm, string cstr, list<dag> pattern> 637193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 638193323Sed asm, cstr,pattern> { 639193323Sed let Inst{4} = 1; 640193323Sed let Inst{5} = 0; // H bit 641193323Sed let Inst{6} = 1; // S bit 642193323Sed let Inst{7} = 1; 643193323Sed let Inst{20} = 1; // L bit 644193323Sed let Inst{21} = 1; // W bit 645193323Sed let Inst{24} = 0; // P bit 646193323Sed} 647193323Sed 648193323Sed// Post-indexed stores 649193323Sedclass AI3sthpo<dag oops, dag iops, Format f, string opc, 650193323Sed string asm, string cstr, list<dag> pattern> 651193323Sed : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 652193323Sed asm, cstr,pattern> { 653193323Sed let Inst{4} = 1; 654193323Sed let Inst{5} = 1; // H bit 655193323Sed let Inst{6} = 0; // S bit 656193323Sed let Inst{7} = 1; 657193323Sed let Inst{20} = 0; // L bit 658193323Sed let Inst{21} = 1; // W bit 659193323Sed let Inst{24} = 0; // P bit 660193323Sed} 661193323Sed 662193323Sed 663193323Sed// addrmode4 instructions 664193323Sedclass AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern> 665193323Sed : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, 666193323Sed "", pattern> { 667193323Sed let Inst{20} = 1; // L bit 668193323Sed let Inst{22} = 0; // S bit 669193323Sed let Inst{27-25} = 0b100; 670193323Sed} 671193323Sedclass AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern> 672193323Sed : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, 673193323Sed "", pattern> { 674193323Sed let Inst{20} = 0; // L bit 675193323Sed let Inst{22} = 0; // S bit 676193323Sed let Inst{27-25} = 0b100; 677193323Sed} 678193323Sed 679193323Sed// Unsigned multiply, multiply-accumulate instructions. 680193323Sedclass AMul1I<bits<7> opcod, dag oops, dag iops, string opc, 681193323Sed string asm, list<dag> pattern> 682193323Sed : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 683193323Sed asm, "", pattern> { 684193323Sed let Inst{7-4} = 0b1001; 685193323Sed let Inst{20} = 0; // S bit 686193323Sed let Inst{27-21} = opcod; 687193323Sed} 688193323Sedclass AsMul1I<bits<7> opcod, dag oops, dag iops, string opc, 689193323Sed string asm, list<dag> pattern> 690193323Sed : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 691193323Sed asm, "", pattern> { 692193323Sed let Inst{7-4} = 0b1001; 693193323Sed let Inst{27-21} = opcod; 694193323Sed} 695193323Sed 696193323Sed// Most significant word multiply 697193323Sedclass AMul2I<bits<7> opcod, dag oops, dag iops, string opc, 698193323Sed string asm, list<dag> pattern> 699193323Sed : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 700193323Sed asm, "", pattern> { 701193323Sed let Inst{7-4} = 0b1001; 702193323Sed let Inst{20} = 1; 703193323Sed let Inst{27-21} = opcod; 704193323Sed} 705193323Sed 706193323Sed// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 707193323Sedclass AMulxyI<bits<7> opcod, dag oops, dag iops, string opc, 708193323Sed string asm, list<dag> pattern> 709193323Sed : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 710193323Sed asm, "", pattern> { 711193323Sed let Inst{4} = 0; 712193323Sed let Inst{7} = 1; 713193323Sed let Inst{20} = 0; 714193323Sed let Inst{27-21} = opcod; 715193323Sed} 716193323Sed 717193323Sed// Extend instructions. 718193323Sedclass AExtI<bits<8> opcod, dag oops, dag iops, string opc, 719193323Sed string asm, list<dag> pattern> 720193323Sed : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, opc, 721193323Sed asm, "", pattern> { 722193323Sed let Inst{7-4} = 0b0111; 723193323Sed let Inst{27-20} = opcod; 724193323Sed} 725193323Sed 726193323Sed// Misc Arithmetic instructions. 727193323Sedclass AMiscA1I<bits<8> opcod, dag oops, dag iops, string opc, 728193323Sed string asm, list<dag> pattern> 729193323Sed : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, opc, 730193323Sed asm, "", pattern> { 731193323Sed let Inst{27-20} = opcod; 732193323Sed} 733193323Sed 734193323Sed//===----------------------------------------------------------------------===// 735193323Sed 736193323Sed// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 737193323Sedclass ARMPat<dag pattern, dag result> : Pat<pattern, result> { 738193323Sed list<Predicate> Predicates = [IsARM]; 739193323Sed} 740193323Sedclass ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 741193323Sed list<Predicate> Predicates = [IsARM, HasV5TE]; 742193323Sed} 743193323Sedclass ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 744193323Sed list<Predicate> Predicates = [IsARM, HasV6]; 745193323Sed} 746193323Sed 747193323Sed//===----------------------------------------------------------------------===// 748193323Sed// 749193323Sed// Thumb Instruction Format Definitions. 750193323Sed// 751193323Sed 752193323Sed// TI - Thumb instruction. 753193323Sed 754193323Sedclass ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz, 755193323Sed string asm, string cstr, list<dag> pattern> 756193323Sed : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 757193323Sed let OutOperandList = outs; 758193323Sed let InOperandList = ins; 759193323Sed let AsmString = asm; 760193323Sed let Pattern = pattern; 761193323Sed list<Predicate> Predicates = [IsThumb]; 762193323Sed} 763193323Sed 764193323Sedclass TI<dag outs, dag ins, string asm, list<dag> pattern> 765193323Sed : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>; 766193323Sed 767193323Sed// BL, BLX(1) are translated by assembler into two instructions 768193323Sedclass TIx2<dag outs, dag ins, string asm, list<dag> pattern> 769193323Sed : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>; 770193323Sed 771193323Sed// BR_JT instructions 772193323Sedclass TJTI<dag outs, dag ins, string asm, list<dag> pattern> 773193323Sed : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>; 774193323Sed 775195098Sed// TPat - Same as Pat<>, but requires that the compiler be in Thumb mode. 776195098Sedclass TPat<dag pattern, dag result> : Pat<pattern, result> { 777194710Sed list<Predicate> Predicates = [IsThumb]; 778194710Sed} 779193323Sed 780195098Sedclass Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 781194710Sed list<Predicate> Predicates = [IsThumb, HasV5T]; 782194710Sed} 783194710Sed 784195098Sed// Thumb1 only 785195098Sedclass Thumb1I<dag outs, dag ins, AddrMode am, SizeFlagVal sz, 786194754Sed string asm, string cstr, list<dag> pattern> 787194754Sed : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 788194754Sed let OutOperandList = outs; 789194754Sed let InOperandList = ins; 790194754Sed let AsmString = asm; 791194754Sed let Pattern = pattern; 792195098Sed list<Predicate> Predicates = [IsThumb1Only]; 793195098Sed} 794195098Sed 795195098Sedclass T1I<dag outs, dag ins, string asm, list<dag> pattern> 796195098Sed : Thumb1I<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>; 797195340Sedclass T1I1<dag outs, dag ins, string asm, list<dag> pattern> 798195340Sed : Thumb1I<outs, ins, AddrModeT1_1, Size2Bytes, asm, "", pattern>; 799195340Sedclass T1I2<dag outs, dag ins, string asm, list<dag> pattern> 800195340Sed : Thumb1I<outs, ins, AddrModeT1_2, Size2Bytes, asm, "", pattern>; 801195340Sedclass T1I4<dag outs, dag ins, string asm, list<dag> pattern> 802195340Sed : Thumb1I<outs, ins, AddrModeT1_4, Size2Bytes, asm, "", pattern>; 803195340Sedclass T1Is<dag outs, dag ins, string asm, list<dag> pattern> 804195340Sed : Thumb1I<outs, ins, AddrModeT1_s, Size2Bytes, asm, "", pattern>; 805195340Sedclass T1Ix2<dag outs, dag ins, string asm, list<dag> pattern> 806195340Sed : Thumb1I<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>; 807195340Sedclass T1JTI<dag outs, dag ins, string asm, list<dag> pattern> 808195340Sed : Thumb1I<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>; 809195098Sed 810195098Sed// Two-address instructions 811195098Sedclass T1It<dag outs, dag ins, string asm, list<dag> pattern> 812195098Sed : Thumb1I<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>; 813195098Sed 814195098Sedclass T1Pat<dag pattern, dag result> : Pat<pattern, result> { 815195098Sed list<Predicate> Predicates = [IsThumb1Only]; 816195098Sed} 817195098Sed 818195098Sed// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 819195098Sedclass Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 820195098Sed string opc, string asm, string cstr, list<dag> pattern> 821195098Sed : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 822195098Sed let OutOperandList = oops; 823195098Sed let InOperandList = !con(iops, (ops pred:$p)); 824195098Sed let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 825195098Sed let Pattern = pattern; 826195340Sed list<Predicate> Predicates = [IsThumb2]; 827194754Sed} 828194754Sed 829195098Sed// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as 830195098Sed// an input operand since by default it's a zero register. It will 831195098Sed// become an implicit def once it's "flipped". 832195098Sed// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 833195098Sed// more consistent. 834195098Sedclass Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 835195098Sed string opc, string asm, string cstr, list<dag> pattern> 836195098Sed : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 837195098Sed let OutOperandList = oops; 838195098Sed let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 839195098Sed let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 840195098Sed let Pattern = pattern; 841195340Sed list<Predicate> Predicates = [IsThumb2]; 842195098Sed} 843194754Sed 844195098Sed// Special cases 845195098Sedclass Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 846195098Sed string asm, string cstr, list<dag> pattern> 847195098Sed : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 848195098Sed let OutOperandList = oops; 849195098Sed let InOperandList = iops; 850195098Sed let AsmString = asm; 851195098Sed let Pattern = pattern; 852195340Sed list<Predicate> Predicates = [IsThumb2]; 853194754Sed} 854194754Sed 855195098Sedclass T2I<dag oops, dag iops, string opc, string asm, list<dag> pattern> 856195098Sed : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, opc, asm, "", pattern>; 857195340Sedclass T2Ii12<dag oops, dag iops, string opc, string asm, list<dag> pattern> 858195340Sed : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, opc, asm, "", pattern>; 859195340Sedclass T2Ii8<dag oops, dag iops, string opc, string asm, list<dag> pattern> 860195340Sed : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, opc, asm, "", pattern>; 861195340Sedclass T2Iso<dag oops, dag iops, string opc, string asm, list<dag> pattern> 862195340Sed : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, opc, asm, "", pattern>; 863195340Sedclass T2Ipc<dag oops, dag iops, string opc, string asm, list<dag> pattern> 864195340Sed : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, opc, asm, "", pattern>; 865195340Sedclass T2Ii8s4<dag oops, dag iops, string opc, string asm, list<dag> pattern> 866195340Sed : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, opc, asm, "", pattern>; 867195098Sed 868195098Sedclass T2sI<dag oops, dag iops, string opc, string asm, list<dag> pattern> 869195098Sed : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, opc, asm, "", pattern>; 870195098Sed 871195098Sedclass T2XI<dag oops, dag iops, string asm, list<dag> pattern> 872195098Sed : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, asm, "", pattern>; 873195340Sedclass T2JTI<dag oops, dag iops, string asm, list<dag> pattern> 874195340Sed : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, asm, "", pattern>; 875195098Sed 876195340Sed// T2Iidxldst - Thumb2 indexed load / store instructions. 877195340Sedclass T2Iidxldst<dag oops, dag iops, AddrMode am, IndexMode im, 878195340Sed string opc, string asm, string cstr, list<dag> pattern> 879195340Sed : InstARM<am, Size4Bytes, im, ThumbFrm, cstr> { 880195340Sed let OutOperandList = oops; 881195340Sed let InOperandList = !con(iops, (ops pred:$p)); 882195340Sed let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 883195340Sed let Pattern = pattern; 884195340Sed list<Predicate> Predicates = [IsThumb2]; 885195340Sed} 886195340Sed 887195340Sed 888195098Sed// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 889195098Sedclass T2Pat<dag pattern, dag result> : Pat<pattern, result> { 890195340Sed list<Predicate> Predicates = [IsThumb2]; 891195098Sed} 892195098Sed 893193323Sed//===----------------------------------------------------------------------===// 894193323Sed 895193323Sed//===----------------------------------------------------------------------===// 896193323Sed// ARM VFP Instruction templates. 897193323Sed// 898193323Sed 899193323Sed// ARM VFP addrmode5 loads and stores 900193323Sedclass ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 901193323Sed string opc, string asm, list<dag> pattern> 902193323Sed : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 903193323Sed VFPLdStFrm, opc, asm, "", pattern> { 904193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 905193323Sed let Inst{27-24} = opcod1; 906193323Sed let Inst{21-20} = opcod2; 907193323Sed let Inst{11-8} = 0b1011; 908193323Sed} 909193323Sed 910193323Sedclass ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 911193323Sed string opc, string asm, list<dag> pattern> 912193323Sed : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 913193323Sed VFPLdStFrm, opc, asm, "", pattern> { 914193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 915193323Sed let Inst{27-24} = opcod1; 916193323Sed let Inst{21-20} = opcod2; 917193323Sed let Inst{11-8} = 0b1010; 918193323Sed} 919193323Sed 920193323Sed// Load / store multiple 921193323Sedclass AXSI5<dag oops, dag iops, string asm, list<dag> pattern> 922193323Sed : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 923193323Sed VFPLdStMulFrm, asm, "", pattern> { 924193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 925193323Sed let Inst{27-25} = 0b110; 926193323Sed let Inst{11-8} = 0b1011; 927193323Sed} 928193323Sed 929193323Sedclass AXDI5<dag oops, dag iops, string asm, list<dag> pattern> 930193323Sed : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 931193323Sed VFPLdStMulFrm, asm, "", pattern> { 932193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 933193323Sed let Inst{27-25} = 0b110; 934193323Sed let Inst{11-8} = 0b1010; 935193323Sed} 936193323Sed 937193323Sed 938193323Sed// Double precision, unary 939193323Sedclass ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 940193323Sed string opc, string asm, list<dag> pattern> 941193323Sed : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> { 942193323Sed let Inst{27-20} = opcod1; 943193323Sed let Inst{19-16} = opcod2; 944193323Sed let Inst{11-8} = 0b1011; 945193323Sed let Inst{7-4} = opcod3; 946193323Sed} 947193323Sed 948193323Sed// Double precision, binary 949193323Sedclass ADbI<bits<8> opcod, dag oops, dag iops, string opc, 950193323Sed string asm, list<dag> pattern> 951193323Sed : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> { 952193323Sed let Inst{27-20} = opcod; 953193323Sed let Inst{11-8} = 0b1011; 954193323Sed} 955193323Sed 956193323Sed// Single precision, unary 957193323Sedclass ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 958193323Sed string opc, string asm, list<dag> pattern> 959193323Sed : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> { 960193323Sed // Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding. 961193323Sed let Inst{27-20} = opcod1; 962193323Sed let Inst{19-16} = opcod2; 963193323Sed let Inst{11-8} = 0b1010; 964193323Sed let Inst{7-4} = opcod3; 965193323Sed} 966193323Sed 967193323Sed// Single precision, binary 968193323Sedclass ASbI<bits<8> opcod, dag oops, dag iops, string opc, 969193323Sed string asm, list<dag> pattern> 970193323Sed : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> { 971193323Sed // Bit 22 (D bit) can be changed during instruction encoding. 972193323Sed let Inst{27-20} = opcod; 973193323Sed let Inst{11-8} = 0b1010; 974193323Sed} 975193323Sed 976193323Sed// VFP conversion instructions 977193323Sedclass AVConv1I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, 978193323Sed dag oops, dag iops, string opc, string asm, list<dag> pattern> 979193323Sed : AI<oops, iops, VFPConv1Frm, opc, asm, pattern> { 980193323Sed let Inst{27-20} = opcod1; 981193323Sed let Inst{19-16} = opcod2; 982193323Sed let Inst{11-8} = opcod3; 983193323Sed let Inst{6} = 1; 984193323Sed} 985193323Sed 986193323Sedclass AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 987193323Sed string opc, string asm, list<dag> pattern> 988193323Sed : AI<oops, iops, f, opc, asm, pattern> { 989193323Sed let Inst{27-20} = opcod1; 990193323Sed let Inst{11-8} = opcod2; 991193323Sed let Inst{4} = 1; 992193323Sed} 993193323Sed 994193323Sedclass AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc, 995193323Sed string asm, list<dag> pattern> 996193323Sed : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, opc, asm, pattern>; 997193323Sed 998193323Sedclass AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc, 999193323Sed string asm, list<dag> pattern> 1000193323Sed : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, opc, asm, pattern>; 1001193323Sed 1002193323Sedclass AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc, 1003193323Sed string asm, list<dag> pattern> 1004193323Sed : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, opc, asm, pattern>; 1005193323Sed 1006193323Sedclass AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc, 1007193323Sed string asm, list<dag> pattern> 1008193323Sed : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, opc, asm, pattern>; 1009193323Sed 1010193323Sed//===----------------------------------------------------------------------===// 1011193323Sed 1012194710Sed//===----------------------------------------------------------------------===// 1013194710Sed// ARM NEON Instruction templates. 1014194710Sed// 1015193323Sed 1016194710Sedclass NeonI<dag oops, dag iops, AddrMode am, IndexMode im, string asm, 1017194710Sed string cstr, list<dag> pattern> 1018194710Sed : InstARM<am, Size4Bytes, im, NEONFrm, cstr> { 1019194710Sed let OutOperandList = oops; 1020194710Sed let InOperandList = iops; 1021194710Sed let AsmString = asm; 1022194710Sed let Pattern = pattern; 1023194710Sed list<Predicate> Predicates = [HasNEON]; 1024193323Sed} 1025193323Sed 1026194710Sedclass NI<dag oops, dag iops, string asm, list<dag> pattern> 1027194710Sed : NeonI<oops, iops, AddrModeNone, IndexModeNone, asm, "", pattern> { 1028193323Sed} 1029194710Sed 1030194710Sedclass NDataI<dag oops, dag iops, string asm, string cstr, list<dag> pattern> 1031194710Sed : NeonI<oops, iops, AddrModeNone, IndexModeNone, asm, cstr, pattern> { 1032194710Sed let Inst{31-25} = 0b1111001; 1033194710Sed} 1034194710Sed 1035194710Sed// NEON "one register and a modified immediate" format. 1036194710Sedclass N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1037194710Sed bit op5, bit op4, 1038194710Sed dag oops, dag iops, string asm, string cstr, list<dag> pattern> 1039194710Sed : NDataI<oops, iops, asm, cstr, pattern> { 1040194710Sed let Inst{23} = op23; 1041194710Sed let Inst{21-19} = op21_19; 1042194710Sed let Inst{11-8} = op11_8; 1043194710Sed let Inst{7} = op7; 1044194710Sed let Inst{6} = op6; 1045194710Sed let Inst{5} = op5; 1046194710Sed let Inst{4} = op4; 1047194710Sed} 1048194710Sed 1049194710Sed// NEON 2 vector register format. 1050194710Sedclass N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1051194710Sed bits<5> op11_7, bit op6, bit op4, 1052194710Sed dag oops, dag iops, string asm, string cstr, list<dag> pattern> 1053194710Sed : NDataI<oops, iops, asm, cstr, pattern> { 1054194710Sed let Inst{24-23} = op24_23; 1055194710Sed let Inst{21-20} = op21_20; 1056194710Sed let Inst{19-18} = op19_18; 1057194710Sed let Inst{17-16} = op17_16; 1058194710Sed let Inst{11-7} = op11_7; 1059194710Sed let Inst{6} = op6; 1060194710Sed let Inst{4} = op4; 1061194710Sed} 1062194710Sed 1063194710Sed// NEON 2 vector register with immediate. 1064194710Sedclass N2VImm<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 1065194710Sed bit op6, bit op4, 1066194710Sed dag oops, dag iops, string asm, string cstr, list<dag> pattern> 1067194710Sed : NDataI<oops, iops, asm, cstr, pattern> { 1068194710Sed let Inst{24} = op24; 1069194710Sed let Inst{23} = op23; 1070194710Sed let Inst{21-16} = op21_16; 1071194710Sed let Inst{11-8} = op11_8; 1072194710Sed let Inst{7} = op7; 1073194710Sed let Inst{6} = op6; 1074194710Sed let Inst{4} = op4; 1075194710Sed} 1076194710Sed 1077194710Sed// NEON 3 vector register format. 1078194710Sedclass N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1079194710Sed dag oops, dag iops, string asm, string cstr, list<dag> pattern> 1080194710Sed : NDataI<oops, iops, asm, cstr, pattern> { 1081194710Sed let Inst{24} = op24; 1082194710Sed let Inst{23} = op23; 1083194710Sed let Inst{21-20} = op21_20; 1084194710Sed let Inst{11-8} = op11_8; 1085194710Sed let Inst{6} = op6; 1086194710Sed let Inst{4} = op4; 1087194710Sed} 1088194710Sed 1089194710Sed// NEON VMOVs between scalar and core registers. 1090194710Sedclass NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1091194710Sed dag oops, dag iops, Format f, string opc, string asm, 1092194710Sed list<dag> pattern> 1093194710Sed : AI<oops, iops, f, opc, asm, pattern> { 1094194710Sed let Inst{27-20} = opcod1; 1095194710Sed let Inst{11-8} = opcod2; 1096194710Sed let Inst{6-5} = opcod3; 1097194710Sed let Inst{4} = 1; 1098194710Sed list<Predicate> Predicates = [HasNEON]; 1099194710Sed} 1100194710Sedclass NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1101194710Sed dag oops, dag iops, string opc, string asm, list<dag> pattern> 1102194710Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, opc, asm, 1103194710Sed pattern>; 1104194710Sedclass NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1105194710Sed dag oops, dag iops, string opc, string asm, list<dag> pattern> 1106194710Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, opc, asm, 1107194710Sed pattern>; 1108194710Sedclass NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1109194710Sed dag oops, dag iops, string opc, string asm, list<dag> pattern> 1110194710Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, opc, asm, pattern>; 1111