ARMISelDAGToDAG.cpp revision 218893 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "arm-isel"
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMAddressingModes.h"
18#include "ARMTargetMachine.h"
19#include "llvm/CallingConv.h"
20#include "llvm/Constants.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/SelectionDAG.h"
29#include "llvm/CodeGen/SelectionDAGISel.h"
30#include "llvm/Target/TargetLowering.h"
31#include "llvm/Target/TargetOptions.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37
38using namespace llvm;
39
40static cl::opt<bool>
41DisableShifterOp("disable-shifter-op", cl::Hidden,
42  cl::desc("Disable isel of shifter-op"),
43  cl::init(false));
44
45static cl::opt<bool>
46CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47  cl::desc("Check fp vmla / vmls hazard at isel time"),
48  cl::init(false));
49
50//===--------------------------------------------------------------------===//
51/// ARMDAGToDAGISel - ARM specific code to select ARM machine
52/// instructions for SelectionDAG operations.
53///
54namespace {
55
56enum AddrMode2Type {
57  AM2_BASE, // Simple AM2 (+-imm12)
58  AM2_SHOP  // Shifter-op AM2
59};
60
61class ARMDAGToDAGISel : public SelectionDAGISel {
62  ARMBaseTargetMachine &TM;
63  const ARMBaseInstrInfo *TII;
64
65  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66  /// make the right decision when generating code for different targets.
67  const ARMSubtarget *Subtarget;
68
69public:
70  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
71                           CodeGenOpt::Level OptLevel)
72    : SelectionDAGISel(tm, OptLevel), TM(tm),
73      TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
74      Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
75  }
76
77  virtual const char *getPassName() const {
78    return "ARM Instruction Selection";
79  }
80
81  /// getI32Imm - Return a target constant of type i32 with the specified
82  /// value.
83  inline SDValue getI32Imm(unsigned Imm) {
84    return CurDAG->getTargetConstant(Imm, MVT::i32);
85  }
86
87  SDNode *Select(SDNode *N);
88
89
90  bool hasNoVMLxHazardUse(SDNode *N) const;
91  bool isShifterOpProfitable(const SDValue &Shift,
92                             ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
93  bool SelectShifterOperandReg(SDValue N, SDValue &A,
94                               SDValue &B, SDValue &C);
95  bool SelectShiftShifterOperandReg(SDValue N, SDValue &A,
96                                    SDValue &B, SDValue &C);
97  bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
98  bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
99
100  AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
101                                      SDValue &Offset, SDValue &Opc);
102  bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
103                           SDValue &Opc) {
104    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
105  }
106
107  bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
108                           SDValue &Opc) {
109    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
110  }
111
112  bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
113                       SDValue &Opc) {
114    SelectAddrMode2Worker(N, Base, Offset, Opc);
115//    return SelectAddrMode2ShOp(N, Base, Offset, Opc);
116    // This always matches one way or another.
117    return true;
118  }
119
120  bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
121                             SDValue &Offset, SDValue &Opc);
122  bool SelectAddrMode3(SDValue N, SDValue &Base,
123                       SDValue &Offset, SDValue &Opc);
124  bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
125                             SDValue &Offset, SDValue &Opc);
126  bool SelectAddrMode5(SDValue N, SDValue &Base,
127                       SDValue &Offset);
128  bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
129
130  bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
131
132  // Thumb Addressing Modes:
133  bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
134  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
135                             unsigned Scale);
136  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
137  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
138  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
139  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
140                                SDValue &OffImm);
141  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
142                                 SDValue &OffImm);
143  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
144                                 SDValue &OffImm);
145  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
146                                 SDValue &OffImm);
147  bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
148
149  // Thumb 2 Addressing Modes:
150  bool SelectT2ShifterOperandReg(SDValue N,
151                                 SDValue &BaseReg, SDValue &Opc);
152  bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
153  bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
154                            SDValue &OffImm);
155  bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
156                                 SDValue &OffImm);
157  bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
158                             SDValue &OffReg, SDValue &ShImm);
159
160  inline bool is_so_imm(unsigned Imm) const {
161    return ARM_AM::getSOImmVal(Imm) != -1;
162  }
163
164  inline bool is_so_imm_not(unsigned Imm) const {
165    return ARM_AM::getSOImmVal(~Imm) != -1;
166  }
167
168  inline bool is_t2_so_imm(unsigned Imm) const {
169    return ARM_AM::getT2SOImmVal(Imm) != -1;
170  }
171
172  inline bool is_t2_so_imm_not(unsigned Imm) const {
173    return ARM_AM::getT2SOImmVal(~Imm) != -1;
174  }
175
176  inline bool Pred_so_imm(SDNode *inN) const {
177    ConstantSDNode *N = cast<ConstantSDNode>(inN);
178    return is_so_imm(N->getZExtValue());
179  }
180
181  inline bool Pred_t2_so_imm(SDNode *inN) const {
182    ConstantSDNode *N = cast<ConstantSDNode>(inN);
183    return is_t2_so_imm(N->getZExtValue());
184  }
185
186  // Include the pieces autogenerated from the target description.
187#include "ARMGenDAGISel.inc"
188
189private:
190  /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
191  /// ARM.
192  SDNode *SelectARMIndexedLoad(SDNode *N);
193  SDNode *SelectT2IndexedLoad(SDNode *N);
194
195  /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
196  /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
197  /// loads of D registers and even subregs and odd subregs of Q registers.
198  /// For NumVecs <= 2, QOpcodes1 is not used.
199  SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
200                    unsigned *DOpcodes,
201                    unsigned *QOpcodes0, unsigned *QOpcodes1);
202
203  /// SelectVST - Select NEON store intrinsics.  NumVecs should
204  /// be 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
205  /// stores of D registers and even subregs and odd subregs of Q registers.
206  /// For NumVecs <= 2, QOpcodes1 is not used.
207  SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
208                    unsigned *DOpcodes,
209                    unsigned *QOpcodes0, unsigned *QOpcodes1);
210
211  /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
212  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
213  /// load/store of D registers and Q registers.
214  SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
215                          bool isUpdating, unsigned NumVecs,
216                          unsigned *DOpcodes, unsigned *QOpcodes);
217
218  /// SelectVLDDup - Select NEON load-duplicate intrinsics.  NumVecs
219  /// should be 2, 3 or 4.  The opcode array specifies the instructions used
220  /// for loading D registers.  (Q registers are not supported.)
221  SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
222                       unsigned *Opcodes);
223
224  /// SelectVTBL - Select NEON VTBL and VTBX intrinsics.  NumVecs should be 2,
225  /// 3 or 4.  These are custom-selected so that a REG_SEQUENCE can be
226  /// generated to force the table registers to be consecutive.
227  SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
228
229  /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
230  SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
231
232  /// SelectCMOVOp - Select CMOV instructions for ARM.
233  SDNode *SelectCMOVOp(SDNode *N);
234  SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
235                              ARMCC::CondCodes CCVal, SDValue CCR,
236                              SDValue InFlag);
237  SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
238                               ARMCC::CondCodes CCVal, SDValue CCR,
239                               SDValue InFlag);
240  SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
241                              ARMCC::CondCodes CCVal, SDValue CCR,
242                              SDValue InFlag);
243  SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
244                               ARMCC::CondCodes CCVal, SDValue CCR,
245                               SDValue InFlag);
246
247  SDNode *SelectConcatVector(SDNode *N);
248
249  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
250  /// inline asm expressions.
251  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
252                                            char ConstraintCode,
253                                            std::vector<SDValue> &OutOps);
254
255  // Form pairs of consecutive S, D, or Q registers.
256  SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
257  SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
258  SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
259
260  // Form sequences of 4 consecutive S, D, or Q registers.
261  SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
262  SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
263  SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
264
265  // Get the alignment operand for a NEON VLD or VST instruction.
266  SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
267};
268}
269
270/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
271/// operand. If so Imm will receive the 32-bit value.
272static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
273  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
274    Imm = cast<ConstantSDNode>(N)->getZExtValue();
275    return true;
276  }
277  return false;
278}
279
280// isInt32Immediate - This method tests to see if a constant operand.
281// If so Imm will receive the 32 bit value.
282static bool isInt32Immediate(SDValue N, unsigned &Imm) {
283  return isInt32Immediate(N.getNode(), Imm);
284}
285
286// isOpcWithIntImmediate - This method tests to see if the node is a specific
287// opcode and that it has a immediate integer right operand.
288// If so Imm will receive the 32 bit value.
289static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
290  return N->getOpcode() == Opc &&
291         isInt32Immediate(N->getOperand(1).getNode(), Imm);
292}
293
294/// \brief Check whether a particular node is a constant value representable as
295/// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
296///
297/// \param ScaledConstant [out] - On success, the pre-scaled constant value.
298static bool isScaledConstantInRange(SDValue Node, unsigned Scale,
299                                    int RangeMin, int RangeMax,
300                                    int &ScaledConstant) {
301  assert(Scale && "Invalid scale!");
302
303  // Check that this is a constant.
304  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
305  if (!C)
306    return false;
307
308  ScaledConstant = (int) C->getZExtValue();
309  if ((ScaledConstant % Scale) != 0)
310    return false;
311
312  ScaledConstant /= Scale;
313  return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
314}
315
316/// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
317/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
318/// least on current ARM implementations) which should be avoidded.
319bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
320  if (OptLevel == CodeGenOpt::None)
321    return true;
322
323  if (!CheckVMLxHazard)
324    return true;
325
326  if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
327    return true;
328
329  if (!N->hasOneUse())
330    return false;
331
332  SDNode *Use = *N->use_begin();
333  if (Use->getOpcode() == ISD::CopyToReg)
334    return true;
335  if (Use->isMachineOpcode()) {
336    const TargetInstrDesc &TID = TII->get(Use->getMachineOpcode());
337    if (TID.mayStore())
338      return true;
339    unsigned Opcode = TID.getOpcode();
340    if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
341      return true;
342    // vmlx feeding into another vmlx. We actually want to unfold
343    // the use later in the MLxExpansion pass. e.g.
344    // vmla
345    // vmla (stall 8 cycles)
346    //
347    // vmul (5 cycles)
348    // vadd (5 cycles)
349    // vmla
350    // This adds up to about 18 - 19 cycles.
351    //
352    // vmla
353    // vmul (stall 4 cycles)
354    // vadd adds up to about 14 cycles.
355    return TII->isFpMLxInstruction(Opcode);
356  }
357
358  return false;
359}
360
361bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
362                                            ARM_AM::ShiftOpc ShOpcVal,
363                                            unsigned ShAmt) {
364  if (!Subtarget->isCortexA9())
365    return true;
366  if (Shift.hasOneUse())
367    return true;
368  // R << 2 is free.
369  return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
370}
371
372bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
373                                              SDValue &BaseReg,
374                                              SDValue &ShReg,
375                                              SDValue &Opc) {
376  if (DisableShifterOp)
377    return false;
378
379  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
380
381  // Don't match base register only case. That is matched to a separate
382  // lower complexity pattern with explicit register operand.
383  if (ShOpcVal == ARM_AM::no_shift) return false;
384
385  BaseReg = N.getOperand(0);
386  unsigned ShImmVal = 0;
387  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
388    ShReg = CurDAG->getRegister(0, MVT::i32);
389    ShImmVal = RHS->getZExtValue() & 31;
390  } else {
391    ShReg = N.getOperand(1);
392    if (!isShifterOpProfitable(N, ShOpcVal, ShImmVal))
393      return false;
394  }
395  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
396                                  MVT::i32);
397  return true;
398}
399
400bool ARMDAGToDAGISel::SelectShiftShifterOperandReg(SDValue N,
401                                                   SDValue &BaseReg,
402                                                   SDValue &ShReg,
403                                                   SDValue &Opc) {
404  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
405
406  // Don't match base register only case. That is matched to a separate
407  // lower complexity pattern with explicit register operand.
408  if (ShOpcVal == ARM_AM::no_shift) return false;
409
410  BaseReg = N.getOperand(0);
411  unsigned ShImmVal = 0;
412  // Do not check isShifterOpProfitable. This must return true.
413  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
414    ShReg = CurDAG->getRegister(0, MVT::i32);
415    ShImmVal = RHS->getZExtValue() & 31;
416  } else {
417    ShReg = N.getOperand(1);
418  }
419  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
420                                  MVT::i32);
421  return true;
422}
423
424bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
425                                          SDValue &Base,
426                                          SDValue &OffImm) {
427  // Match simple R + imm12 operands.
428
429  // Base only.
430  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
431      !CurDAG->isBaseWithConstantOffset(N)) {
432    if (N.getOpcode() == ISD::FrameIndex) {
433      // Match frame index.
434      int FI = cast<FrameIndexSDNode>(N)->getIndex();
435      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
436      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
437      return true;
438    }
439
440    if (N.getOpcode() == ARMISD::Wrapper &&
441        !(Subtarget->useMovt() &&
442                     N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
443      Base = N.getOperand(0);
444    } else
445      Base = N;
446    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
447    return true;
448  }
449
450  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
451    int RHSC = (int)RHS->getZExtValue();
452    if (N.getOpcode() == ISD::SUB)
453      RHSC = -RHSC;
454
455    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
456      Base   = N.getOperand(0);
457      if (Base.getOpcode() == ISD::FrameIndex) {
458        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
459        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
460      }
461      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
462      return true;
463    }
464  }
465
466  // Base only.
467  Base = N;
468  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
469  return true;
470}
471
472
473
474bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
475                                      SDValue &Opc) {
476  if (N.getOpcode() == ISD::MUL &&
477      (!Subtarget->isCortexA9() || N.hasOneUse())) {
478    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
479      // X * [3,5,9] -> X + X * [2,4,8] etc.
480      int RHSC = (int)RHS->getZExtValue();
481      if (RHSC & 1) {
482        RHSC = RHSC & ~1;
483        ARM_AM::AddrOpc AddSub = ARM_AM::add;
484        if (RHSC < 0) {
485          AddSub = ARM_AM::sub;
486          RHSC = - RHSC;
487        }
488        if (isPowerOf2_32(RHSC)) {
489          unsigned ShAmt = Log2_32(RHSC);
490          Base = Offset = N.getOperand(0);
491          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
492                                                            ARM_AM::lsl),
493                                          MVT::i32);
494          return true;
495        }
496      }
497    }
498  }
499
500  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
501      // ISD::OR that is equivalent to an ISD::ADD.
502      !CurDAG->isBaseWithConstantOffset(N))
503    return false;
504
505  // Leave simple R +/- imm12 operands for LDRi12
506  if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
507    int RHSC;
508    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
509                                -0x1000+1, 0x1000, RHSC)) // 12 bits.
510      return false;
511  }
512
513  if (Subtarget->isCortexA9() && !N.hasOneUse())
514    // Compute R +/- (R << N) and reuse it.
515    return false;
516
517  // Otherwise this is R +/- [possibly shifted] R.
518  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
519  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
520  unsigned ShAmt = 0;
521
522  Base   = N.getOperand(0);
523  Offset = N.getOperand(1);
524
525  if (ShOpcVal != ARM_AM::no_shift) {
526    // Check to see if the RHS of the shift is a constant, if not, we can't fold
527    // it.
528    if (ConstantSDNode *Sh =
529           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
530      ShAmt = Sh->getZExtValue();
531      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
532        Offset = N.getOperand(1).getOperand(0);
533      else {
534        ShAmt = 0;
535        ShOpcVal = ARM_AM::no_shift;
536      }
537    } else {
538      ShOpcVal = ARM_AM::no_shift;
539    }
540  }
541
542  // Try matching (R shl C) + (R).
543  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
544      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
545    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
546    if (ShOpcVal != ARM_AM::no_shift) {
547      // Check to see if the RHS of the shift is a constant, if not, we can't
548      // fold it.
549      if (ConstantSDNode *Sh =
550          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
551        ShAmt = Sh->getZExtValue();
552        if (!Subtarget->isCortexA9() ||
553            (N.hasOneUse() &&
554             isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
555          Offset = N.getOperand(0).getOperand(0);
556          Base = N.getOperand(1);
557        } else {
558          ShAmt = 0;
559          ShOpcVal = ARM_AM::no_shift;
560        }
561      } else {
562        ShOpcVal = ARM_AM::no_shift;
563      }
564    }
565  }
566
567  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
568                                  MVT::i32);
569  return true;
570}
571
572
573
574
575//-----
576
577AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
578                                                     SDValue &Base,
579                                                     SDValue &Offset,
580                                                     SDValue &Opc) {
581  if (N.getOpcode() == ISD::MUL &&
582      (!Subtarget->isCortexA9() || N.hasOneUse())) {
583    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
584      // X * [3,5,9] -> X + X * [2,4,8] etc.
585      int RHSC = (int)RHS->getZExtValue();
586      if (RHSC & 1) {
587        RHSC = RHSC & ~1;
588        ARM_AM::AddrOpc AddSub = ARM_AM::add;
589        if (RHSC < 0) {
590          AddSub = ARM_AM::sub;
591          RHSC = - RHSC;
592        }
593        if (isPowerOf2_32(RHSC)) {
594          unsigned ShAmt = Log2_32(RHSC);
595          Base = Offset = N.getOperand(0);
596          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
597                                                            ARM_AM::lsl),
598                                          MVT::i32);
599          return AM2_SHOP;
600        }
601      }
602    }
603  }
604
605  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
606      // ISD::OR that is equivalent to an ADD.
607      !CurDAG->isBaseWithConstantOffset(N)) {
608    Base = N;
609    if (N.getOpcode() == ISD::FrameIndex) {
610      int FI = cast<FrameIndexSDNode>(N)->getIndex();
611      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
612    } else if (N.getOpcode() == ARMISD::Wrapper &&
613               !(Subtarget->useMovt() &&
614                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
615      Base = N.getOperand(0);
616    }
617    Offset = CurDAG->getRegister(0, MVT::i32);
618    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
619                                                      ARM_AM::no_shift),
620                                    MVT::i32);
621    return AM2_BASE;
622  }
623
624  // Match simple R +/- imm12 operands.
625  if (N.getOpcode() != ISD::SUB) {
626    int RHSC;
627    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
628                                -0x1000+1, 0x1000, RHSC)) { // 12 bits.
629      Base = N.getOperand(0);
630      if (Base.getOpcode() == ISD::FrameIndex) {
631        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
632        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
633      }
634      Offset = CurDAG->getRegister(0, MVT::i32);
635
636      ARM_AM::AddrOpc AddSub = ARM_AM::add;
637      if (RHSC < 0) {
638        AddSub = ARM_AM::sub;
639        RHSC = - RHSC;
640      }
641      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
642                                                        ARM_AM::no_shift),
643                                      MVT::i32);
644      return AM2_BASE;
645    }
646  }
647
648  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
649    // Compute R +/- (R << N) and reuse it.
650    Base = N;
651    Offset = CurDAG->getRegister(0, MVT::i32);
652    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
653                                                      ARM_AM::no_shift),
654                                    MVT::i32);
655    return AM2_BASE;
656  }
657
658  // Otherwise this is R +/- [possibly shifted] R.
659  ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
660  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
661  unsigned ShAmt = 0;
662
663  Base   = N.getOperand(0);
664  Offset = N.getOperand(1);
665
666  if (ShOpcVal != ARM_AM::no_shift) {
667    // Check to see if the RHS of the shift is a constant, if not, we can't fold
668    // it.
669    if (ConstantSDNode *Sh =
670           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
671      ShAmt = Sh->getZExtValue();
672      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
673        Offset = N.getOperand(1).getOperand(0);
674      else {
675        ShAmt = 0;
676        ShOpcVal = ARM_AM::no_shift;
677      }
678    } else {
679      ShOpcVal = ARM_AM::no_shift;
680    }
681  }
682
683  // Try matching (R shl C) + (R).
684  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
685      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
686    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
687    if (ShOpcVal != ARM_AM::no_shift) {
688      // Check to see if the RHS of the shift is a constant, if not, we can't
689      // fold it.
690      if (ConstantSDNode *Sh =
691          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
692        ShAmt = Sh->getZExtValue();
693        if (!Subtarget->isCortexA9() ||
694            (N.hasOneUse() &&
695             isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
696          Offset = N.getOperand(0).getOperand(0);
697          Base = N.getOperand(1);
698        } else {
699          ShAmt = 0;
700          ShOpcVal = ARM_AM::no_shift;
701        }
702      } else {
703        ShOpcVal = ARM_AM::no_shift;
704      }
705    }
706  }
707
708  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
709                                  MVT::i32);
710  return AM2_SHOP;
711}
712
713bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
714                                            SDValue &Offset, SDValue &Opc) {
715  unsigned Opcode = Op->getOpcode();
716  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
717    ? cast<LoadSDNode>(Op)->getAddressingMode()
718    : cast<StoreSDNode>(Op)->getAddressingMode();
719  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
720    ? ARM_AM::add : ARM_AM::sub;
721  int Val;
722  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
723    Offset = CurDAG->getRegister(0, MVT::i32);
724    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
725                                                      ARM_AM::no_shift),
726                                    MVT::i32);
727    return true;
728  }
729
730  Offset = N;
731  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
732  unsigned ShAmt = 0;
733  if (ShOpcVal != ARM_AM::no_shift) {
734    // Check to see if the RHS of the shift is a constant, if not, we can't fold
735    // it.
736    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
737      ShAmt = Sh->getZExtValue();
738      if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
739        Offset = N.getOperand(0);
740      else {
741        ShAmt = 0;
742        ShOpcVal = ARM_AM::no_shift;
743      }
744    } else {
745      ShOpcVal = ARM_AM::no_shift;
746    }
747  }
748
749  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
750                                  MVT::i32);
751  return true;
752}
753
754
755bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
756                                      SDValue &Base, SDValue &Offset,
757                                      SDValue &Opc) {
758  if (N.getOpcode() == ISD::SUB) {
759    // X - C  is canonicalize to X + -C, no need to handle it here.
760    Base = N.getOperand(0);
761    Offset = N.getOperand(1);
762    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
763    return true;
764  }
765
766  if (!CurDAG->isBaseWithConstantOffset(N)) {
767    Base = N;
768    if (N.getOpcode() == ISD::FrameIndex) {
769      int FI = cast<FrameIndexSDNode>(N)->getIndex();
770      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
771    }
772    Offset = CurDAG->getRegister(0, MVT::i32);
773    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
774    return true;
775  }
776
777  // If the RHS is +/- imm8, fold into addr mode.
778  int RHSC;
779  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
780                              -256 + 1, 256, RHSC)) { // 8 bits.
781    Base = N.getOperand(0);
782    if (Base.getOpcode() == ISD::FrameIndex) {
783      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
784      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
785    }
786    Offset = CurDAG->getRegister(0, MVT::i32);
787
788    ARM_AM::AddrOpc AddSub = ARM_AM::add;
789    if (RHSC < 0) {
790      AddSub = ARM_AM::sub;
791      RHSC = -RHSC;
792    }
793    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
794    return true;
795  }
796
797  Base = N.getOperand(0);
798  Offset = N.getOperand(1);
799  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
800  return true;
801}
802
803bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
804                                            SDValue &Offset, SDValue &Opc) {
805  unsigned Opcode = Op->getOpcode();
806  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
807    ? cast<LoadSDNode>(Op)->getAddressingMode()
808    : cast<StoreSDNode>(Op)->getAddressingMode();
809  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
810    ? ARM_AM::add : ARM_AM::sub;
811  int Val;
812  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
813    Offset = CurDAG->getRegister(0, MVT::i32);
814    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
815    return true;
816  }
817
818  Offset = N;
819  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
820  return true;
821}
822
823bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
824                                      SDValue &Base, SDValue &Offset) {
825  if (!CurDAG->isBaseWithConstantOffset(N)) {
826    Base = N;
827    if (N.getOpcode() == ISD::FrameIndex) {
828      int FI = cast<FrameIndexSDNode>(N)->getIndex();
829      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
830    } else if (N.getOpcode() == ARMISD::Wrapper &&
831               !(Subtarget->useMovt() &&
832                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
833      Base = N.getOperand(0);
834    }
835    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
836                                       MVT::i32);
837    return true;
838  }
839
840  // If the RHS is +/- imm8, fold into addr mode.
841  int RHSC;
842  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
843                              -256 + 1, 256, RHSC)) {
844    Base = N.getOperand(0);
845    if (Base.getOpcode() == ISD::FrameIndex) {
846      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
847      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
848    }
849
850    ARM_AM::AddrOpc AddSub = ARM_AM::add;
851    if (RHSC < 0) {
852      AddSub = ARM_AM::sub;
853      RHSC = -RHSC;
854    }
855    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
856                                       MVT::i32);
857    return true;
858  }
859
860  Base = N;
861  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
862                                     MVT::i32);
863  return true;
864}
865
866bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
867                                      SDValue &Align) {
868  Addr = N;
869
870  unsigned Alignment = 0;
871  if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
872    // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
873    // The maximum alignment is equal to the memory size being referenced.
874    unsigned LSNAlign = LSN->getAlignment();
875    unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
876    if (LSNAlign > MemSize && MemSize > 1)
877      Alignment = MemSize;
878  } else {
879    // All other uses of addrmode6 are for intrinsics.  For now just record
880    // the raw alignment value; it will be refined later based on the legal
881    // alignment operands for the intrinsic.
882    Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
883  }
884
885  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
886  return true;
887}
888
889bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
890                                       SDValue &Offset, SDValue &Label) {
891  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
892    Offset = N.getOperand(0);
893    SDValue N1 = N.getOperand(1);
894    Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
895                                      MVT::i32);
896    return true;
897  }
898
899  return false;
900}
901
902
903//===----------------------------------------------------------------------===//
904//                         Thumb Addressing Modes
905//===----------------------------------------------------------------------===//
906
907bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
908                                            SDValue &Base, SDValue &Offset){
909  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
910    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
911    if (!NC || !NC->isNullValue())
912      return false;
913
914    Base = Offset = N;
915    return true;
916  }
917
918  Base = N.getOperand(0);
919  Offset = N.getOperand(1);
920  return true;
921}
922
923bool
924ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
925                                       SDValue &Offset, unsigned Scale) {
926  if (Scale == 4) {
927    SDValue TmpBase, TmpOffImm;
928    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
929      return false;  // We want to select tLDRspi / tSTRspi instead.
930
931    if (N.getOpcode() == ARMISD::Wrapper &&
932        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
933      return false;  // We want to select tLDRpci instead.
934  }
935
936  if (!CurDAG->isBaseWithConstantOffset(N))
937    return false;
938
939  // Thumb does not have [sp, r] address mode.
940  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
941  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
942  if ((LHSR && LHSR->getReg() == ARM::SP) ||
943      (RHSR && RHSR->getReg() == ARM::SP))
944    return false;
945
946  // FIXME: Why do we explicitly check for a match here and then return false?
947  // Presumably to allow something else to match, but shouldn't this be
948  // documented?
949  int RHSC;
950  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
951    return false;
952
953  Base = N.getOperand(0);
954  Offset = N.getOperand(1);
955  return true;
956}
957
958bool
959ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
960                                          SDValue &Base,
961                                          SDValue &Offset) {
962  return SelectThumbAddrModeRI(N, Base, Offset, 1);
963}
964
965bool
966ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
967                                          SDValue &Base,
968                                          SDValue &Offset) {
969  return SelectThumbAddrModeRI(N, Base, Offset, 2);
970}
971
972bool
973ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
974                                          SDValue &Base,
975                                          SDValue &Offset) {
976  return SelectThumbAddrModeRI(N, Base, Offset, 4);
977}
978
979bool
980ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
981                                          SDValue &Base, SDValue &OffImm) {
982  if (Scale == 4) {
983    SDValue TmpBase, TmpOffImm;
984    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
985      return false;  // We want to select tLDRspi / tSTRspi instead.
986
987    if (N.getOpcode() == ARMISD::Wrapper &&
988        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
989      return false;  // We want to select tLDRpci instead.
990  }
991
992  if (!CurDAG->isBaseWithConstantOffset(N)) {
993    if (N.getOpcode() == ARMISD::Wrapper &&
994        !(Subtarget->useMovt() &&
995          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
996      Base = N.getOperand(0);
997    } else {
998      Base = N;
999    }
1000
1001    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1002    return true;
1003  }
1004
1005  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1006  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1007  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1008      (RHSR && RHSR->getReg() == ARM::SP)) {
1009    ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1010    ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1011    unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1012    unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1013
1014    // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1015    if (LHSC != 0 || RHSC != 0) return false;
1016
1017    Base = N;
1018    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1019    return true;
1020  }
1021
1022  // If the RHS is + imm5 * scale, fold into addr mode.
1023  int RHSC;
1024  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1025    Base = N.getOperand(0);
1026    OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1027    return true;
1028  }
1029
1030  Base = N.getOperand(0);
1031  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1032  return true;
1033}
1034
1035bool
1036ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1037                                           SDValue &OffImm) {
1038  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1039}
1040
1041bool
1042ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1043                                           SDValue &OffImm) {
1044  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1045}
1046
1047bool
1048ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1049                                           SDValue &OffImm) {
1050  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1051}
1052
1053bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1054                                            SDValue &Base, SDValue &OffImm) {
1055  if (N.getOpcode() == ISD::FrameIndex) {
1056    int FI = cast<FrameIndexSDNode>(N)->getIndex();
1057    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1058    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1059    return true;
1060  }
1061
1062  if (!CurDAG->isBaseWithConstantOffset(N))
1063    return false;
1064
1065  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1066  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1067      (LHSR && LHSR->getReg() == ARM::SP)) {
1068    // If the RHS is + imm8 * scale, fold into addr mode.
1069    int RHSC;
1070    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1071      Base = N.getOperand(0);
1072      if (Base.getOpcode() == ISD::FrameIndex) {
1073        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1074        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1075      }
1076      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1077      return true;
1078    }
1079  }
1080
1081  return false;
1082}
1083
1084
1085//===----------------------------------------------------------------------===//
1086//                        Thumb 2 Addressing Modes
1087//===----------------------------------------------------------------------===//
1088
1089
1090bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1091                                                SDValue &Opc) {
1092  if (DisableShifterOp)
1093    return false;
1094
1095  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
1096
1097  // Don't match base register only case. That is matched to a separate
1098  // lower complexity pattern with explicit register operand.
1099  if (ShOpcVal == ARM_AM::no_shift) return false;
1100
1101  BaseReg = N.getOperand(0);
1102  unsigned ShImmVal = 0;
1103  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1104    ShImmVal = RHS->getZExtValue() & 31;
1105    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1106    return true;
1107  }
1108
1109  return false;
1110}
1111
1112bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1113                                            SDValue &Base, SDValue &OffImm) {
1114  // Match simple R + imm12 operands.
1115
1116  // Base only.
1117  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1118      !CurDAG->isBaseWithConstantOffset(N)) {
1119    if (N.getOpcode() == ISD::FrameIndex) {
1120      // Match frame index.
1121      int FI = cast<FrameIndexSDNode>(N)->getIndex();
1122      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1123      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1124      return true;
1125    }
1126
1127    if (N.getOpcode() == ARMISD::Wrapper &&
1128               !(Subtarget->useMovt() &&
1129                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1130      Base = N.getOperand(0);
1131      if (Base.getOpcode() == ISD::TargetConstantPool)
1132        return false;  // We want to select t2LDRpci instead.
1133    } else
1134      Base = N;
1135    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1136    return true;
1137  }
1138
1139  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1140    if (SelectT2AddrModeImm8(N, Base, OffImm))
1141      // Let t2LDRi8 handle (R - imm8).
1142      return false;
1143
1144    int RHSC = (int)RHS->getZExtValue();
1145    if (N.getOpcode() == ISD::SUB)
1146      RHSC = -RHSC;
1147
1148    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1149      Base   = N.getOperand(0);
1150      if (Base.getOpcode() == ISD::FrameIndex) {
1151        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1152        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1153      }
1154      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1155      return true;
1156    }
1157  }
1158
1159  // Base only.
1160  Base = N;
1161  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1162  return true;
1163}
1164
1165bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1166                                           SDValue &Base, SDValue &OffImm) {
1167  // Match simple R - imm8 operands.
1168  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1169      !CurDAG->isBaseWithConstantOffset(N))
1170    return false;
1171
1172  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1173    int RHSC = (int)RHS->getSExtValue();
1174    if (N.getOpcode() == ISD::SUB)
1175      RHSC = -RHSC;
1176
1177    if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1178      Base = N.getOperand(0);
1179      if (Base.getOpcode() == ISD::FrameIndex) {
1180        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1181        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1182      }
1183      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1184      return true;
1185    }
1186  }
1187
1188  return false;
1189}
1190
1191bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1192                                                 SDValue &OffImm){
1193  unsigned Opcode = Op->getOpcode();
1194  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1195    ? cast<LoadSDNode>(Op)->getAddressingMode()
1196    : cast<StoreSDNode>(Op)->getAddressingMode();
1197  int RHSC;
1198  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1199    OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1200      ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1201      : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1202    return true;
1203  }
1204
1205  return false;
1206}
1207
1208bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1209                                            SDValue &Base,
1210                                            SDValue &OffReg, SDValue &ShImm) {
1211  // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1212  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1213    return false;
1214
1215  // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1216  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1217    int RHSC = (int)RHS->getZExtValue();
1218    if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1219      return false;
1220    else if (RHSC < 0 && RHSC >= -255) // 8 bits
1221      return false;
1222  }
1223
1224  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1225    // Compute R + (R << [1,2,3]) and reuse it.
1226    Base = N;
1227    return false;
1228  }
1229
1230  // Look for (R + R) or (R + (R << [1,2,3])).
1231  unsigned ShAmt = 0;
1232  Base   = N.getOperand(0);
1233  OffReg = N.getOperand(1);
1234
1235  // Swap if it is ((R << c) + R).
1236  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
1237  if (ShOpcVal != ARM_AM::lsl) {
1238    ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
1239    if (ShOpcVal == ARM_AM::lsl)
1240      std::swap(Base, OffReg);
1241  }
1242
1243  if (ShOpcVal == ARM_AM::lsl) {
1244    // Check to see if the RHS of the shift is a constant, if not, we can't fold
1245    // it.
1246    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1247      ShAmt = Sh->getZExtValue();
1248      if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1249        OffReg = OffReg.getOperand(0);
1250      else {
1251        ShAmt = 0;
1252        ShOpcVal = ARM_AM::no_shift;
1253      }
1254    } else {
1255      ShOpcVal = ARM_AM::no_shift;
1256    }
1257  }
1258
1259  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1260
1261  return true;
1262}
1263
1264//===--------------------------------------------------------------------===//
1265
1266/// getAL - Returns a ARMCC::AL immediate node.
1267static inline SDValue getAL(SelectionDAG *CurDAG) {
1268  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1269}
1270
1271SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1272  LoadSDNode *LD = cast<LoadSDNode>(N);
1273  ISD::MemIndexedMode AM = LD->getAddressingMode();
1274  if (AM == ISD::UNINDEXED)
1275    return NULL;
1276
1277  EVT LoadedVT = LD->getMemoryVT();
1278  SDValue Offset, AMOpc;
1279  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1280  unsigned Opcode = 0;
1281  bool Match = false;
1282  if (LoadedVT == MVT::i32 &&
1283      SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1284    Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
1285    Match = true;
1286  } else if (LoadedVT == MVT::i16 &&
1287             SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1288    Match = true;
1289    Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1290      ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1291      : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1292  } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1293    if (LD->getExtensionType() == ISD::SEXTLOAD) {
1294      if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1295        Match = true;
1296        Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1297      }
1298    } else {
1299      if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1300        Match = true;
1301        Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
1302      }
1303    }
1304  }
1305
1306  if (Match) {
1307    SDValue Chain = LD->getChain();
1308    SDValue Base = LD->getBasePtr();
1309    SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1310                     CurDAG->getRegister(0, MVT::i32), Chain };
1311    return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1312                                  MVT::Other, Ops, 6);
1313  }
1314
1315  return NULL;
1316}
1317
1318SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1319  LoadSDNode *LD = cast<LoadSDNode>(N);
1320  ISD::MemIndexedMode AM = LD->getAddressingMode();
1321  if (AM == ISD::UNINDEXED)
1322    return NULL;
1323
1324  EVT LoadedVT = LD->getMemoryVT();
1325  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1326  SDValue Offset;
1327  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1328  unsigned Opcode = 0;
1329  bool Match = false;
1330  if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1331    switch (LoadedVT.getSimpleVT().SimpleTy) {
1332    case MVT::i32:
1333      Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1334      break;
1335    case MVT::i16:
1336      if (isSExtLd)
1337        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1338      else
1339        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1340      break;
1341    case MVT::i8:
1342    case MVT::i1:
1343      if (isSExtLd)
1344        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1345      else
1346        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1347      break;
1348    default:
1349      return NULL;
1350    }
1351    Match = true;
1352  }
1353
1354  if (Match) {
1355    SDValue Chain = LD->getChain();
1356    SDValue Base = LD->getBasePtr();
1357    SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1358                     CurDAG->getRegister(0, MVT::i32), Chain };
1359    return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1360                                  MVT::Other, Ops, 5);
1361  }
1362
1363  return NULL;
1364}
1365
1366/// PairSRegs - Form a D register from a pair of S registers.
1367///
1368SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1369  DebugLoc dl = V0.getNode()->getDebugLoc();
1370  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1371  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1372  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1373  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1374}
1375
1376/// PairDRegs - Form a quad register from a pair of D registers.
1377///
1378SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1379  DebugLoc dl = V0.getNode()->getDebugLoc();
1380  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1381  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1382  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1383  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1384}
1385
1386/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1387///
1388SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1389  DebugLoc dl = V0.getNode()->getDebugLoc();
1390  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1391  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1392  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1393  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1394}
1395
1396/// QuadSRegs - Form 4 consecutive S registers.
1397///
1398SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1399                                   SDValue V2, SDValue V3) {
1400  DebugLoc dl = V0.getNode()->getDebugLoc();
1401  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1402  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1403  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1404  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1405  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1406  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1407}
1408
1409/// QuadDRegs - Form 4 consecutive D registers.
1410///
1411SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1412                                   SDValue V2, SDValue V3) {
1413  DebugLoc dl = V0.getNode()->getDebugLoc();
1414  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1415  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1416  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1417  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1418  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1419  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1420}
1421
1422/// QuadQRegs - Form 4 consecutive Q registers.
1423///
1424SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1425                                   SDValue V2, SDValue V3) {
1426  DebugLoc dl = V0.getNode()->getDebugLoc();
1427  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1428  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1429  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1430  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1431  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1432  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1433}
1434
1435/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1436/// of a NEON VLD or VST instruction.  The supported values depend on the
1437/// number of registers being loaded.
1438SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1439                                       bool is64BitVector) {
1440  unsigned NumRegs = NumVecs;
1441  if (!is64BitVector && NumVecs < 3)
1442    NumRegs *= 2;
1443
1444  unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1445  if (Alignment >= 32 && NumRegs == 4)
1446    Alignment = 32;
1447  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1448    Alignment = 16;
1449  else if (Alignment >= 8)
1450    Alignment = 8;
1451  else
1452    Alignment = 0;
1453
1454  return CurDAG->getTargetConstant(Alignment, MVT::i32);
1455}
1456
1457SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1458                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1459                                   unsigned *QOpcodes1) {
1460  assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1461  DebugLoc dl = N->getDebugLoc();
1462
1463  SDValue MemAddr, Align;
1464  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1465  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1466    return NULL;
1467
1468  SDValue Chain = N->getOperand(0);
1469  EVT VT = N->getValueType(0);
1470  bool is64BitVector = VT.is64BitVector();
1471  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1472
1473  unsigned OpcodeIndex;
1474  switch (VT.getSimpleVT().SimpleTy) {
1475  default: llvm_unreachable("unhandled vld type");
1476    // Double-register operations:
1477  case MVT::v8i8:  OpcodeIndex = 0; break;
1478  case MVT::v4i16: OpcodeIndex = 1; break;
1479  case MVT::v2f32:
1480  case MVT::v2i32: OpcodeIndex = 2; break;
1481  case MVT::v1i64: OpcodeIndex = 3; break;
1482    // Quad-register operations:
1483  case MVT::v16i8: OpcodeIndex = 0; break;
1484  case MVT::v8i16: OpcodeIndex = 1; break;
1485  case MVT::v4f32:
1486  case MVT::v4i32: OpcodeIndex = 2; break;
1487  case MVT::v2i64: OpcodeIndex = 3;
1488    assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1489    break;
1490  }
1491
1492  EVT ResTy;
1493  if (NumVecs == 1)
1494    ResTy = VT;
1495  else {
1496    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1497    if (!is64BitVector)
1498      ResTyElts *= 2;
1499    ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1500  }
1501  std::vector<EVT> ResTys;
1502  ResTys.push_back(ResTy);
1503  if (isUpdating)
1504    ResTys.push_back(MVT::i32);
1505  ResTys.push_back(MVT::Other);
1506
1507  SDValue Pred = getAL(CurDAG);
1508  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1509  SDNode *VLd;
1510  SmallVector<SDValue, 7> Ops;
1511
1512  // Double registers and VLD1/VLD2 quad registers are directly supported.
1513  if (is64BitVector || NumVecs <= 2) {
1514    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1515                    QOpcodes0[OpcodeIndex]);
1516    Ops.push_back(MemAddr);
1517    Ops.push_back(Align);
1518    if (isUpdating) {
1519      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1520      Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1521    }
1522    Ops.push_back(Pred);
1523    Ops.push_back(Reg0);
1524    Ops.push_back(Chain);
1525    VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1526
1527  } else {
1528    // Otherwise, quad registers are loaded with two separate instructions,
1529    // where one loads the even registers and the other loads the odd registers.
1530    EVT AddrTy = MemAddr.getValueType();
1531
1532    // Load the even subregs.  This is always an updating load, so that it
1533    // provides the address to the second load for the odd subregs.
1534    SDValue ImplDef =
1535      SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1536    const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1537    SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1538                                          ResTy, AddrTy, MVT::Other, OpsA, 7);
1539    Chain = SDValue(VLdA, 2);
1540
1541    // Load the odd subregs.
1542    Ops.push_back(SDValue(VLdA, 1));
1543    Ops.push_back(Align);
1544    if (isUpdating) {
1545      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1546      assert(isa<ConstantSDNode>(Inc.getNode()) &&
1547             "only constant post-increment update allowed for VLD3/4");
1548      (void)Inc;
1549      Ops.push_back(Reg0);
1550    }
1551    Ops.push_back(SDValue(VLdA, 0));
1552    Ops.push_back(Pred);
1553    Ops.push_back(Reg0);
1554    Ops.push_back(Chain);
1555    VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1556                                 Ops.data(), Ops.size());
1557  }
1558
1559  if (NumVecs == 1)
1560    return VLd;
1561
1562  // Extract out the subregisters.
1563  SDValue SuperReg = SDValue(VLd, 0);
1564  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1565         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1566  unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1567  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1568    ReplaceUses(SDValue(N, Vec),
1569                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1570  ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1571  if (isUpdating)
1572    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1573  return NULL;
1574}
1575
1576SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1577                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1578                                   unsigned *QOpcodes1) {
1579  assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1580  DebugLoc dl = N->getDebugLoc();
1581
1582  SDValue MemAddr, Align;
1583  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1584  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1585  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1586    return NULL;
1587
1588  SDValue Chain = N->getOperand(0);
1589  EVT VT = N->getOperand(Vec0Idx).getValueType();
1590  bool is64BitVector = VT.is64BitVector();
1591  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1592
1593  unsigned OpcodeIndex;
1594  switch (VT.getSimpleVT().SimpleTy) {
1595  default: llvm_unreachable("unhandled vst type");
1596    // Double-register operations:
1597  case MVT::v8i8:  OpcodeIndex = 0; break;
1598  case MVT::v4i16: OpcodeIndex = 1; break;
1599  case MVT::v2f32:
1600  case MVT::v2i32: OpcodeIndex = 2; break;
1601  case MVT::v1i64: OpcodeIndex = 3; break;
1602    // Quad-register operations:
1603  case MVT::v16i8: OpcodeIndex = 0; break;
1604  case MVT::v8i16: OpcodeIndex = 1; break;
1605  case MVT::v4f32:
1606  case MVT::v4i32: OpcodeIndex = 2; break;
1607  case MVT::v2i64: OpcodeIndex = 3;
1608    assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1609    break;
1610  }
1611
1612  std::vector<EVT> ResTys;
1613  if (isUpdating)
1614    ResTys.push_back(MVT::i32);
1615  ResTys.push_back(MVT::Other);
1616
1617  SDValue Pred = getAL(CurDAG);
1618  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1619  SmallVector<SDValue, 7> Ops;
1620
1621  // Double registers and VST1/VST2 quad registers are directly supported.
1622  if (is64BitVector || NumVecs <= 2) {
1623    SDValue SrcReg;
1624    if (NumVecs == 1) {
1625      SrcReg = N->getOperand(Vec0Idx);
1626    } else if (is64BitVector) {
1627      // Form a REG_SEQUENCE to force register allocation.
1628      SDValue V0 = N->getOperand(Vec0Idx + 0);
1629      SDValue V1 = N->getOperand(Vec0Idx + 1);
1630      if (NumVecs == 2)
1631        SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1632      else {
1633        SDValue V2 = N->getOperand(Vec0Idx + 2);
1634        // If it's a vst3, form a quad D-register and leave the last part as
1635        // an undef.
1636        SDValue V3 = (NumVecs == 3)
1637          ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1638          : N->getOperand(Vec0Idx + 3);
1639        SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1640      }
1641    } else {
1642      // Form a QQ register.
1643      SDValue Q0 = N->getOperand(Vec0Idx);
1644      SDValue Q1 = N->getOperand(Vec0Idx + 1);
1645      SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1646    }
1647
1648    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1649                    QOpcodes0[OpcodeIndex]);
1650    Ops.push_back(MemAddr);
1651    Ops.push_back(Align);
1652    if (isUpdating) {
1653      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1654      Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1655    }
1656    Ops.push_back(SrcReg);
1657    Ops.push_back(Pred);
1658    Ops.push_back(Reg0);
1659    Ops.push_back(Chain);
1660    return CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1661  }
1662
1663  // Otherwise, quad registers are stored with two separate instructions,
1664  // where one stores the even registers and the other stores the odd registers.
1665
1666  // Form the QQQQ REG_SEQUENCE.
1667  SDValue V0 = N->getOperand(Vec0Idx + 0);
1668  SDValue V1 = N->getOperand(Vec0Idx + 1);
1669  SDValue V2 = N->getOperand(Vec0Idx + 2);
1670  SDValue V3 = (NumVecs == 3)
1671    ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1672    : N->getOperand(Vec0Idx + 3);
1673  SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1674
1675  // Store the even D registers.  This is always an updating store, so that it
1676  // provides the address to the second store for the odd subregs.
1677  const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1678  SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1679                                        MemAddr.getValueType(),
1680                                        MVT::Other, OpsA, 7);
1681  Chain = SDValue(VStA, 1);
1682
1683  // Store the odd D registers.
1684  Ops.push_back(SDValue(VStA, 0));
1685  Ops.push_back(Align);
1686  if (isUpdating) {
1687    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1688    assert(isa<ConstantSDNode>(Inc.getNode()) &&
1689           "only constant post-increment update allowed for VST3/4");
1690    (void)Inc;
1691    Ops.push_back(Reg0);
1692  }
1693  Ops.push_back(RegSeq);
1694  Ops.push_back(Pred);
1695  Ops.push_back(Reg0);
1696  Ops.push_back(Chain);
1697  return CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1698                                Ops.data(), Ops.size());
1699}
1700
1701SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1702                                         bool isUpdating, unsigned NumVecs,
1703                                         unsigned *DOpcodes,
1704                                         unsigned *QOpcodes) {
1705  assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1706  DebugLoc dl = N->getDebugLoc();
1707
1708  SDValue MemAddr, Align;
1709  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1710  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1711  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1712    return NULL;
1713
1714  SDValue Chain = N->getOperand(0);
1715  unsigned Lane =
1716    cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1717  EVT VT = N->getOperand(Vec0Idx).getValueType();
1718  bool is64BitVector = VT.is64BitVector();
1719
1720  unsigned Alignment = 0;
1721  if (NumVecs != 3) {
1722    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1723    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1724    if (Alignment > NumBytes)
1725      Alignment = NumBytes;
1726    if (Alignment < 8 && Alignment < NumBytes)
1727      Alignment = 0;
1728    // Alignment must be a power of two; make sure of that.
1729    Alignment = (Alignment & -Alignment);
1730    if (Alignment == 1)
1731      Alignment = 0;
1732  }
1733  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1734
1735  unsigned OpcodeIndex;
1736  switch (VT.getSimpleVT().SimpleTy) {
1737  default: llvm_unreachable("unhandled vld/vst lane type");
1738    // Double-register operations:
1739  case MVT::v8i8:  OpcodeIndex = 0; break;
1740  case MVT::v4i16: OpcodeIndex = 1; break;
1741  case MVT::v2f32:
1742  case MVT::v2i32: OpcodeIndex = 2; break;
1743    // Quad-register operations:
1744  case MVT::v8i16: OpcodeIndex = 0; break;
1745  case MVT::v4f32:
1746  case MVT::v4i32: OpcodeIndex = 1; break;
1747  }
1748
1749  std::vector<EVT> ResTys;
1750  if (IsLoad) {
1751    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1752    if (!is64BitVector)
1753      ResTyElts *= 2;
1754    ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1755                                      MVT::i64, ResTyElts));
1756  }
1757  if (isUpdating)
1758    ResTys.push_back(MVT::i32);
1759  ResTys.push_back(MVT::Other);
1760
1761  SDValue Pred = getAL(CurDAG);
1762  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1763
1764  SmallVector<SDValue, 8> Ops;
1765  Ops.push_back(MemAddr);
1766  Ops.push_back(Align);
1767  if (isUpdating) {
1768    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1769    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1770  }
1771
1772  SDValue SuperReg;
1773  SDValue V0 = N->getOperand(Vec0Idx + 0);
1774  SDValue V1 = N->getOperand(Vec0Idx + 1);
1775  if (NumVecs == 2) {
1776    if (is64BitVector)
1777      SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1778    else
1779      SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1780  } else {
1781    SDValue V2 = N->getOperand(Vec0Idx + 2);
1782    SDValue V3 = (NumVecs == 3)
1783      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1784      : N->getOperand(Vec0Idx + 3);
1785    if (is64BitVector)
1786      SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1787    else
1788      SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1789  }
1790  Ops.push_back(SuperReg);
1791  Ops.push_back(getI32Imm(Lane));
1792  Ops.push_back(Pred);
1793  Ops.push_back(Reg0);
1794  Ops.push_back(Chain);
1795
1796  unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1797                                  QOpcodes[OpcodeIndex]);
1798  SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1799                                         Ops.data(), Ops.size());
1800  if (!IsLoad)
1801    return VLdLn;
1802
1803  // Extract the subregisters.
1804  SuperReg = SDValue(VLdLn, 0);
1805  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1806         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1807  unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1808  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1809    ReplaceUses(SDValue(N, Vec),
1810                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1811  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1812  if (isUpdating)
1813    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1814  return NULL;
1815}
1816
1817SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
1818                                      unsigned NumVecs, unsigned *Opcodes) {
1819  assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1820  DebugLoc dl = N->getDebugLoc();
1821
1822  SDValue MemAddr, Align;
1823  if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
1824    return NULL;
1825
1826  SDValue Chain = N->getOperand(0);
1827  EVT VT = N->getValueType(0);
1828
1829  unsigned Alignment = 0;
1830  if (NumVecs != 3) {
1831    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1832    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1833    if (Alignment > NumBytes)
1834      Alignment = NumBytes;
1835    if (Alignment < 8 && Alignment < NumBytes)
1836      Alignment = 0;
1837    // Alignment must be a power of two; make sure of that.
1838    Alignment = (Alignment & -Alignment);
1839    if (Alignment == 1)
1840      Alignment = 0;
1841  }
1842  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1843
1844  unsigned OpcodeIndex;
1845  switch (VT.getSimpleVT().SimpleTy) {
1846  default: llvm_unreachable("unhandled vld-dup type");
1847  case MVT::v8i8:  OpcodeIndex = 0; break;
1848  case MVT::v4i16: OpcodeIndex = 1; break;
1849  case MVT::v2f32:
1850  case MVT::v2i32: OpcodeIndex = 2; break;
1851  }
1852
1853  SDValue Pred = getAL(CurDAG);
1854  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1855  SDValue SuperReg;
1856  unsigned Opc = Opcodes[OpcodeIndex];
1857  SmallVector<SDValue, 6> Ops;
1858  Ops.push_back(MemAddr);
1859  Ops.push_back(Align);
1860  if (isUpdating) {
1861    SDValue Inc = N->getOperand(2);
1862    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1863  }
1864  Ops.push_back(Pred);
1865  Ops.push_back(Reg0);
1866  Ops.push_back(Chain);
1867
1868  unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1869  std::vector<EVT> ResTys;
1870  ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts));
1871  if (isUpdating)
1872    ResTys.push_back(MVT::i32);
1873  ResTys.push_back(MVT::Other);
1874  SDNode *VLdDup =
1875    CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1876  SuperReg = SDValue(VLdDup, 0);
1877
1878  // Extract the subregisters.
1879  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1880  unsigned SubIdx = ARM::dsub_0;
1881  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1882    ReplaceUses(SDValue(N, Vec),
1883                CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1884  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
1885  if (isUpdating)
1886    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
1887  return NULL;
1888}
1889
1890SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1891                                    unsigned Opc) {
1892  assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1893  DebugLoc dl = N->getDebugLoc();
1894  EVT VT = N->getValueType(0);
1895  unsigned FirstTblReg = IsExt ? 2 : 1;
1896
1897  // Form a REG_SEQUENCE to force register allocation.
1898  SDValue RegSeq;
1899  SDValue V0 = N->getOperand(FirstTblReg + 0);
1900  SDValue V1 = N->getOperand(FirstTblReg + 1);
1901  if (NumVecs == 2)
1902    RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1903  else {
1904    SDValue V2 = N->getOperand(FirstTblReg + 2);
1905    // If it's a vtbl3, form a quad D-register and leave the last part as
1906    // an undef.
1907    SDValue V3 = (NumVecs == 3)
1908      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1909      : N->getOperand(FirstTblReg + 3);
1910    RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1911  }
1912
1913  SmallVector<SDValue, 6> Ops;
1914  if (IsExt)
1915    Ops.push_back(N->getOperand(1));
1916  Ops.push_back(RegSeq);
1917  Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1918  Ops.push_back(getAL(CurDAG)); // predicate
1919  Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1920  return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1921}
1922
1923SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1924                                                     bool isSigned) {
1925  if (!Subtarget->hasV6T2Ops())
1926    return NULL;
1927
1928  unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1929    : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1930
1931
1932  // For unsigned extracts, check for a shift right and mask
1933  unsigned And_imm = 0;
1934  if (N->getOpcode() == ISD::AND) {
1935    if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1936
1937      // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1938      if (And_imm & (And_imm + 1))
1939        return NULL;
1940
1941      unsigned Srl_imm = 0;
1942      if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1943                                Srl_imm)) {
1944        assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1945
1946        unsigned Width = CountTrailingOnes_32(And_imm);
1947        unsigned LSB = Srl_imm;
1948        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1949        SDValue Ops[] = { N->getOperand(0).getOperand(0),
1950                          CurDAG->getTargetConstant(LSB, MVT::i32),
1951                          CurDAG->getTargetConstant(Width, MVT::i32),
1952          getAL(CurDAG), Reg0 };
1953        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1954      }
1955    }
1956    return NULL;
1957  }
1958
1959  // Otherwise, we're looking for a shift of a shift
1960  unsigned Shl_imm = 0;
1961  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1962    assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1963    unsigned Srl_imm = 0;
1964    if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1965      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1966      unsigned Width = 32 - Srl_imm;
1967      int LSB = Srl_imm - Shl_imm;
1968      if (LSB < 0)
1969        return NULL;
1970      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1971      SDValue Ops[] = { N->getOperand(0).getOperand(0),
1972                        CurDAG->getTargetConstant(LSB, MVT::i32),
1973                        CurDAG->getTargetConstant(Width, MVT::i32),
1974                        getAL(CurDAG), Reg0 };
1975      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1976    }
1977  }
1978  return NULL;
1979}
1980
1981SDNode *ARMDAGToDAGISel::
1982SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1983                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1984  SDValue CPTmp0;
1985  SDValue CPTmp1;
1986  if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
1987    unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1988    unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1989    unsigned Opc = 0;
1990    switch (SOShOp) {
1991    case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1992    case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1993    case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1994    case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1995    default:
1996      llvm_unreachable("Unknown so_reg opcode!");
1997      break;
1998    }
1999    SDValue SOShImm =
2000      CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
2001    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2002    SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2003    return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2004  }
2005  return 0;
2006}
2007
2008SDNode *ARMDAGToDAGISel::
2009SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2010                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2011  SDValue CPTmp0;
2012  SDValue CPTmp1;
2013  SDValue CPTmp2;
2014  if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2015    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2016    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2017    return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
2018  }
2019  return 0;
2020}
2021
2022SDNode *ARMDAGToDAGISel::
2023SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2024                  ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2025  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2026  if (!T)
2027    return 0;
2028
2029  unsigned Opc = 0;
2030  unsigned TrueImm = T->getZExtValue();
2031  if (is_t2_so_imm(TrueImm)) {
2032    Opc = ARM::t2MOVCCi;
2033  } else if (TrueImm <= 0xffff) {
2034    Opc = ARM::t2MOVCCi16;
2035  } else if (is_t2_so_imm_not(TrueImm)) {
2036    TrueImm = ~TrueImm;
2037    Opc = ARM::t2MVNCCi;
2038  } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2039    // Large immediate.
2040    Opc = ARM::t2MOVCCi32imm;
2041  }
2042
2043  if (Opc) {
2044    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2045    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2046    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2047    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2048  }
2049
2050  return 0;
2051}
2052
2053SDNode *ARMDAGToDAGISel::
2054SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2055                   ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2056  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2057  if (!T)
2058    return 0;
2059
2060  unsigned Opc = 0;
2061  unsigned TrueImm = T->getZExtValue();
2062  bool isSoImm = is_so_imm(TrueImm);
2063  if (isSoImm) {
2064    Opc = ARM::MOVCCi;
2065  } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2066    Opc = ARM::MOVCCi16;
2067  } else if (is_so_imm_not(TrueImm)) {
2068    TrueImm = ~TrueImm;
2069    Opc = ARM::MVNCCi;
2070  } else if (TrueVal.getNode()->hasOneUse() &&
2071             (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2072    // Large immediate.
2073    Opc = ARM::MOVCCi32imm;
2074  }
2075
2076  if (Opc) {
2077    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2078    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2079    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2080    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2081  }
2082
2083  return 0;
2084}
2085
2086SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2087  EVT VT = N->getValueType(0);
2088  SDValue FalseVal = N->getOperand(0);
2089  SDValue TrueVal  = N->getOperand(1);
2090  SDValue CC = N->getOperand(2);
2091  SDValue CCR = N->getOperand(3);
2092  SDValue InFlag = N->getOperand(4);
2093  assert(CC.getOpcode() == ISD::Constant);
2094  assert(CCR.getOpcode() == ISD::Register);
2095  ARMCC::CondCodes CCVal =
2096    (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2097
2098  if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2099    // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2100    // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2101    // Pattern complexity = 18  cost = 1  size = 0
2102    SDValue CPTmp0;
2103    SDValue CPTmp1;
2104    SDValue CPTmp2;
2105    if (Subtarget->isThumb()) {
2106      SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2107                                        CCVal, CCR, InFlag);
2108      if (!Res)
2109        Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2110                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2111      if (Res)
2112        return Res;
2113    } else {
2114      SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2115                                         CCVal, CCR, InFlag);
2116      if (!Res)
2117        Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2118                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2119      if (Res)
2120        return Res;
2121    }
2122
2123    // Pattern: (ARMcmov:i32 GPR:i32:$false,
2124    //             (imm:i32)<<P:Pred_so_imm>>:$true,
2125    //             (imm:i32):$cc)
2126    // Emits: (MOVCCi:i32 GPR:i32:$false,
2127    //           (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2128    // Pattern complexity = 10  cost = 1  size = 0
2129    if (Subtarget->isThumb()) {
2130      SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2131                                        CCVal, CCR, InFlag);
2132      if (!Res)
2133        Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2134                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2135      if (Res)
2136        return Res;
2137    } else {
2138      SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2139                                         CCVal, CCR, InFlag);
2140      if (!Res)
2141        Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2142                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2143      if (Res)
2144        return Res;
2145    }
2146  }
2147
2148  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2149  // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2150  // Pattern complexity = 6  cost = 1  size = 0
2151  //
2152  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2153  // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2154  // Pattern complexity = 6  cost = 11  size = 0
2155  //
2156  // Also FCPYScc and FCPYDcc.
2157  SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2158  SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2159  unsigned Opc = 0;
2160  switch (VT.getSimpleVT().SimpleTy) {
2161  default: assert(false && "Illegal conditional move type!");
2162    break;
2163  case MVT::i32:
2164    Opc = Subtarget->isThumb()
2165      ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2166      : ARM::MOVCCr;
2167    break;
2168  case MVT::f32:
2169    Opc = ARM::VMOVScc;
2170    break;
2171  case MVT::f64:
2172    Opc = ARM::VMOVDcc;
2173    break;
2174  }
2175  return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2176}
2177
2178SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2179  // The only time a CONCAT_VECTORS operation can have legal types is when
2180  // two 64-bit vectors are concatenated to a 128-bit vector.
2181  EVT VT = N->getValueType(0);
2182  if (!VT.is128BitVector() || N->getNumOperands() != 2)
2183    llvm_unreachable("unexpected CONCAT_VECTORS");
2184  return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2185}
2186
2187SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2188  DebugLoc dl = N->getDebugLoc();
2189
2190  if (N->isMachineOpcode())
2191    return NULL;   // Already selected.
2192
2193  switch (N->getOpcode()) {
2194  default: break;
2195  case ISD::Constant: {
2196    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2197    bool UseCP = true;
2198    if (Subtarget->hasThumb2())
2199      // Thumb2-aware targets have the MOVT instruction, so all immediates can
2200      // be done with MOV + MOVT, at worst.
2201      UseCP = 0;
2202    else {
2203      if (Subtarget->isThumb()) {
2204        UseCP = (Val > 255 &&                          // MOV
2205                 ~Val > 255 &&                         // MOV + MVN
2206                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
2207      } else
2208        UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
2209                 ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
2210                 !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
2211    }
2212
2213    if (UseCP) {
2214      SDValue CPIdx =
2215        CurDAG->getTargetConstantPool(ConstantInt::get(
2216                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
2217                                      TLI.getPointerTy());
2218
2219      SDNode *ResNode;
2220      if (Subtarget->isThumb1Only()) {
2221        SDValue Pred = getAL(CurDAG);
2222        SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2223        SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2224        ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2225                                         Ops, 4);
2226      } else {
2227        SDValue Ops[] = {
2228          CPIdx,
2229          CurDAG->getTargetConstant(0, MVT::i32),
2230          getAL(CurDAG),
2231          CurDAG->getRegister(0, MVT::i32),
2232          CurDAG->getEntryNode()
2233        };
2234        ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2235                                       Ops, 5);
2236      }
2237      ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2238      return NULL;
2239    }
2240
2241    // Other cases are autogenerated.
2242    break;
2243  }
2244  case ISD::FrameIndex: {
2245    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2246    int FI = cast<FrameIndexSDNode>(N)->getIndex();
2247    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2248    if (Subtarget->isThumb1Only()) {
2249      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
2250                                  CurDAG->getTargetConstant(0, MVT::i32));
2251    } else {
2252      unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2253                      ARM::t2ADDri : ARM::ADDri);
2254      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2255                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2256                        CurDAG->getRegister(0, MVT::i32) };
2257      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2258    }
2259  }
2260  case ISD::SRL:
2261    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2262      return I;
2263    break;
2264  case ISD::SRA:
2265    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2266      return I;
2267    break;
2268  case ISD::MUL:
2269    if (Subtarget->isThumb1Only())
2270      break;
2271    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2272      unsigned RHSV = C->getZExtValue();
2273      if (!RHSV) break;
2274      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
2275        unsigned ShImm = Log2_32(RHSV-1);
2276        if (ShImm >= 32)
2277          break;
2278        SDValue V = N->getOperand(0);
2279        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2280        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2281        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2282        if (Subtarget->isThumb()) {
2283          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2284          return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2285        } else {
2286          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2287          return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
2288        }
2289      }
2290      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
2291        unsigned ShImm = Log2_32(RHSV+1);
2292        if (ShImm >= 32)
2293          break;
2294        SDValue V = N->getOperand(0);
2295        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2296        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2297        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2298        if (Subtarget->isThumb()) {
2299          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2300          return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2301        } else {
2302          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2303          return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
2304        }
2305      }
2306    }
2307    break;
2308  case ISD::AND: {
2309    // Check for unsigned bitfield extract
2310    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2311      return I;
2312
2313    // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2314    // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2315    // are entirely contributed by c2 and lower 16-bits are entirely contributed
2316    // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2317    // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2318    EVT VT = N->getValueType(0);
2319    if (VT != MVT::i32)
2320      break;
2321    unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2322      ? ARM::t2MOVTi16
2323      : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2324    if (!Opc)
2325      break;
2326    SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2327    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2328    if (!N1C)
2329      break;
2330    if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2331      SDValue N2 = N0.getOperand(1);
2332      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2333      if (!N2C)
2334        break;
2335      unsigned N1CVal = N1C->getZExtValue();
2336      unsigned N2CVal = N2C->getZExtValue();
2337      if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2338          (N1CVal & 0xffffU) == 0xffffU &&
2339          (N2CVal & 0xffffU) == 0x0U) {
2340        SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2341                                                  MVT::i32);
2342        SDValue Ops[] = { N0.getOperand(0), Imm16,
2343                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2344        return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2345      }
2346    }
2347    break;
2348  }
2349  case ARMISD::VMOVRRD:
2350    return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2351                                  N->getOperand(0), getAL(CurDAG),
2352                                  CurDAG->getRegister(0, MVT::i32));
2353  case ISD::UMUL_LOHI: {
2354    if (Subtarget->isThumb1Only())
2355      break;
2356    if (Subtarget->isThumb()) {
2357      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2358                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2359                        CurDAG->getRegister(0, MVT::i32) };
2360      return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2361    } else {
2362      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2363                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2364                        CurDAG->getRegister(0, MVT::i32) };
2365      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2366                                    ARM::UMULL : ARM::UMULLv5,
2367                                    dl, MVT::i32, MVT::i32, Ops, 5);
2368    }
2369  }
2370  case ISD::SMUL_LOHI: {
2371    if (Subtarget->isThumb1Only())
2372      break;
2373    if (Subtarget->isThumb()) {
2374      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2375                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2376      return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2377    } else {
2378      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2379                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2380                        CurDAG->getRegister(0, MVT::i32) };
2381      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2382                                    ARM::SMULL : ARM::SMULLv5,
2383                                    dl, MVT::i32, MVT::i32, Ops, 5);
2384    }
2385  }
2386  case ISD::LOAD: {
2387    SDNode *ResNode = 0;
2388    if (Subtarget->isThumb() && Subtarget->hasThumb2())
2389      ResNode = SelectT2IndexedLoad(N);
2390    else
2391      ResNode = SelectARMIndexedLoad(N);
2392    if (ResNode)
2393      return ResNode;
2394    // Other cases are autogenerated.
2395    break;
2396  }
2397  case ARMISD::BRCOND: {
2398    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2399    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2400    // Pattern complexity = 6  cost = 1  size = 0
2401
2402    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2403    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2404    // Pattern complexity = 6  cost = 1  size = 0
2405
2406    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2407    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2408    // Pattern complexity = 6  cost = 1  size = 0
2409
2410    unsigned Opc = Subtarget->isThumb() ?
2411      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2412    SDValue Chain = N->getOperand(0);
2413    SDValue N1 = N->getOperand(1);
2414    SDValue N2 = N->getOperand(2);
2415    SDValue N3 = N->getOperand(3);
2416    SDValue InFlag = N->getOperand(4);
2417    assert(N1.getOpcode() == ISD::BasicBlock);
2418    assert(N2.getOpcode() == ISD::Constant);
2419    assert(N3.getOpcode() == ISD::Register);
2420
2421    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2422                               cast<ConstantSDNode>(N2)->getZExtValue()),
2423                               MVT::i32);
2424    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2425    SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2426                                             MVT::Glue, Ops, 5);
2427    Chain = SDValue(ResNode, 0);
2428    if (N->getNumValues() == 2) {
2429      InFlag = SDValue(ResNode, 1);
2430      ReplaceUses(SDValue(N, 1), InFlag);
2431    }
2432    ReplaceUses(SDValue(N, 0),
2433                SDValue(Chain.getNode(), Chain.getResNo()));
2434    return NULL;
2435  }
2436  case ARMISD::CMOV:
2437    return SelectCMOVOp(N);
2438  case ARMISD::CNEG: {
2439    EVT VT = N->getValueType(0);
2440    SDValue N0 = N->getOperand(0);
2441    SDValue N1 = N->getOperand(1);
2442    SDValue N2 = N->getOperand(2);
2443    SDValue N3 = N->getOperand(3);
2444    SDValue InFlag = N->getOperand(4);
2445    assert(N2.getOpcode() == ISD::Constant);
2446    assert(N3.getOpcode() == ISD::Register);
2447
2448    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2449                               cast<ConstantSDNode>(N2)->getZExtValue()),
2450                               MVT::i32);
2451    SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
2452    unsigned Opc = 0;
2453    switch (VT.getSimpleVT().SimpleTy) {
2454    default: assert(false && "Illegal conditional move type!");
2455      break;
2456    case MVT::f32:
2457      Opc = ARM::VNEGScc;
2458      break;
2459    case MVT::f64:
2460      Opc = ARM::VNEGDcc;
2461      break;
2462    }
2463    return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2464  }
2465
2466  case ARMISD::VZIP: {
2467    unsigned Opc = 0;
2468    EVT VT = N->getValueType(0);
2469    switch (VT.getSimpleVT().SimpleTy) {
2470    default: return NULL;
2471    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
2472    case MVT::v4i16: Opc = ARM::VZIPd16; break;
2473    case MVT::v2f32:
2474    case MVT::v2i32: Opc = ARM::VZIPd32; break;
2475    case MVT::v16i8: Opc = ARM::VZIPq8; break;
2476    case MVT::v8i16: Opc = ARM::VZIPq16; break;
2477    case MVT::v4f32:
2478    case MVT::v4i32: Opc = ARM::VZIPq32; break;
2479    }
2480    SDValue Pred = getAL(CurDAG);
2481    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2482    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2483    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2484  }
2485  case ARMISD::VUZP: {
2486    unsigned Opc = 0;
2487    EVT VT = N->getValueType(0);
2488    switch (VT.getSimpleVT().SimpleTy) {
2489    default: return NULL;
2490    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
2491    case MVT::v4i16: Opc = ARM::VUZPd16; break;
2492    case MVT::v2f32:
2493    case MVT::v2i32: Opc = ARM::VUZPd32; break;
2494    case MVT::v16i8: Opc = ARM::VUZPq8; break;
2495    case MVT::v8i16: Opc = ARM::VUZPq16; break;
2496    case MVT::v4f32:
2497    case MVT::v4i32: Opc = ARM::VUZPq32; break;
2498    }
2499    SDValue Pred = getAL(CurDAG);
2500    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2501    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2502    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2503  }
2504  case ARMISD::VTRN: {
2505    unsigned Opc = 0;
2506    EVT VT = N->getValueType(0);
2507    switch (VT.getSimpleVT().SimpleTy) {
2508    default: return NULL;
2509    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
2510    case MVT::v4i16: Opc = ARM::VTRNd16; break;
2511    case MVT::v2f32:
2512    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2513    case MVT::v16i8: Opc = ARM::VTRNq8; break;
2514    case MVT::v8i16: Opc = ARM::VTRNq16; break;
2515    case MVT::v4f32:
2516    case MVT::v4i32: Opc = ARM::VTRNq32; break;
2517    }
2518    SDValue Pred = getAL(CurDAG);
2519    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2520    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2521    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2522  }
2523  case ARMISD::BUILD_VECTOR: {
2524    EVT VecVT = N->getValueType(0);
2525    EVT EltVT = VecVT.getVectorElementType();
2526    unsigned NumElts = VecVT.getVectorNumElements();
2527    if (EltVT == MVT::f64) {
2528      assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2529      return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2530    }
2531    assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2532    if (NumElts == 2)
2533      return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2534    assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2535    return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2536                     N->getOperand(2), N->getOperand(3));
2537  }
2538
2539  case ARMISD::VLD2DUP: {
2540    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2541                           ARM::VLD2DUPd32Pseudo };
2542    return SelectVLDDup(N, false, 2, Opcodes);
2543  }
2544
2545  case ARMISD::VLD3DUP: {
2546    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2547                           ARM::VLD3DUPd32Pseudo };
2548    return SelectVLDDup(N, false, 3, Opcodes);
2549  }
2550
2551  case ARMISD::VLD4DUP: {
2552    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2553                           ARM::VLD4DUPd32Pseudo };
2554    return SelectVLDDup(N, false, 4, Opcodes);
2555  }
2556
2557  case ARMISD::VLD2DUP_UPD: {
2558    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd16Pseudo_UPD,
2559                           ARM::VLD2DUPd32Pseudo_UPD };
2560    return SelectVLDDup(N, true, 2, Opcodes);
2561  }
2562
2563  case ARMISD::VLD3DUP_UPD: {
2564    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd16Pseudo_UPD,
2565                           ARM::VLD3DUPd32Pseudo_UPD };
2566    return SelectVLDDup(N, true, 3, Opcodes);
2567  }
2568
2569  case ARMISD::VLD4DUP_UPD: {
2570    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd16Pseudo_UPD,
2571                           ARM::VLD4DUPd32Pseudo_UPD };
2572    return SelectVLDDup(N, true, 4, Opcodes);
2573  }
2574
2575  case ARMISD::VLD1_UPD: {
2576    unsigned DOpcodes[] = { ARM::VLD1d8_UPD, ARM::VLD1d16_UPD,
2577                            ARM::VLD1d32_UPD, ARM::VLD1d64_UPD };
2578    unsigned QOpcodes[] = { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q16Pseudo_UPD,
2579                            ARM::VLD1q32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2580    return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2581  }
2582
2583  case ARMISD::VLD2_UPD: {
2584    unsigned DOpcodes[] = { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d16Pseudo_UPD,
2585                            ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2586    unsigned QOpcodes[] = { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q16Pseudo_UPD,
2587                            ARM::VLD2q32Pseudo_UPD };
2588    return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2589  }
2590
2591  case ARMISD::VLD3_UPD: {
2592    unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2593                            ARM::VLD3d32Pseudo_UPD, ARM::VLD1d64TPseudo_UPD };
2594    unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2595                             ARM::VLD3q16Pseudo_UPD,
2596                             ARM::VLD3q32Pseudo_UPD };
2597    unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2598                             ARM::VLD3q16oddPseudo_UPD,
2599                             ARM::VLD3q32oddPseudo_UPD };
2600    return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2601  }
2602
2603  case ARMISD::VLD4_UPD: {
2604    unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2605                            ARM::VLD4d32Pseudo_UPD, ARM::VLD1d64QPseudo_UPD };
2606    unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2607                             ARM::VLD4q16Pseudo_UPD,
2608                             ARM::VLD4q32Pseudo_UPD };
2609    unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2610                             ARM::VLD4q16oddPseudo_UPD,
2611                             ARM::VLD4q32oddPseudo_UPD };
2612    return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2613  }
2614
2615  case ARMISD::VLD2LN_UPD: {
2616    unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd16Pseudo_UPD,
2617                            ARM::VLD2LNd32Pseudo_UPD };
2618    unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2619                            ARM::VLD2LNq32Pseudo_UPD };
2620    return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2621  }
2622
2623  case ARMISD::VLD3LN_UPD: {
2624    unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd16Pseudo_UPD,
2625                            ARM::VLD3LNd32Pseudo_UPD };
2626    unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2627                            ARM::VLD3LNq32Pseudo_UPD };
2628    return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2629  }
2630
2631  case ARMISD::VLD4LN_UPD: {
2632    unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd16Pseudo_UPD,
2633                            ARM::VLD4LNd32Pseudo_UPD };
2634    unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2635                            ARM::VLD4LNq32Pseudo_UPD };
2636    return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2637  }
2638
2639  case ARMISD::VST1_UPD: {
2640    unsigned DOpcodes[] = { ARM::VST1d8_UPD, ARM::VST1d16_UPD,
2641                            ARM::VST1d32_UPD, ARM::VST1d64_UPD };
2642    unsigned QOpcodes[] = { ARM::VST1q8Pseudo_UPD, ARM::VST1q16Pseudo_UPD,
2643                            ARM::VST1q32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2644    return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2645  }
2646
2647  case ARMISD::VST2_UPD: {
2648    unsigned DOpcodes[] = { ARM::VST2d8Pseudo_UPD, ARM::VST2d16Pseudo_UPD,
2649                            ARM::VST2d32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2650    unsigned QOpcodes[] = { ARM::VST2q8Pseudo_UPD, ARM::VST2q16Pseudo_UPD,
2651                            ARM::VST2q32Pseudo_UPD };
2652    return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2653  }
2654
2655  case ARMISD::VST3_UPD: {
2656    unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
2657                            ARM::VST3d32Pseudo_UPD, ARM::VST1d64TPseudo_UPD };
2658    unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2659                             ARM::VST3q16Pseudo_UPD,
2660                             ARM::VST3q32Pseudo_UPD };
2661    unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2662                             ARM::VST3q16oddPseudo_UPD,
2663                             ARM::VST3q32oddPseudo_UPD };
2664    return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2665  }
2666
2667  case ARMISD::VST4_UPD: {
2668    unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
2669                            ARM::VST4d32Pseudo_UPD, ARM::VST1d64QPseudo_UPD };
2670    unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2671                             ARM::VST4q16Pseudo_UPD,
2672                             ARM::VST4q32Pseudo_UPD };
2673    unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2674                             ARM::VST4q16oddPseudo_UPD,
2675                             ARM::VST4q32oddPseudo_UPD };
2676    return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2677  }
2678
2679  case ARMISD::VST2LN_UPD: {
2680    unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd16Pseudo_UPD,
2681                            ARM::VST2LNd32Pseudo_UPD };
2682    unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2683                            ARM::VST2LNq32Pseudo_UPD };
2684    return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2685  }
2686
2687  case ARMISD::VST3LN_UPD: {
2688    unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd16Pseudo_UPD,
2689                            ARM::VST3LNd32Pseudo_UPD };
2690    unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2691                            ARM::VST3LNq32Pseudo_UPD };
2692    return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2693  }
2694
2695  case ARMISD::VST4LN_UPD: {
2696    unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd16Pseudo_UPD,
2697                            ARM::VST4LNd32Pseudo_UPD };
2698    unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2699                            ARM::VST4LNq32Pseudo_UPD };
2700    return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2701  }
2702
2703  case ISD::INTRINSIC_VOID:
2704  case ISD::INTRINSIC_W_CHAIN: {
2705    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2706    switch (IntNo) {
2707    default:
2708      break;
2709
2710    case Intrinsic::arm_neon_vld1: {
2711      unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2712                              ARM::VLD1d32, ARM::VLD1d64 };
2713      unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2714                              ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2715      return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
2716    }
2717
2718    case Intrinsic::arm_neon_vld2: {
2719      unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2720                              ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2721      unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2722                              ARM::VLD2q32Pseudo };
2723      return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
2724    }
2725
2726    case Intrinsic::arm_neon_vld3: {
2727      unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2728                              ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2729      unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2730                               ARM::VLD3q16Pseudo_UPD,
2731                               ARM::VLD3q32Pseudo_UPD };
2732      unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo,
2733                               ARM::VLD3q16oddPseudo,
2734                               ARM::VLD3q32oddPseudo };
2735      return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2736    }
2737
2738    case Intrinsic::arm_neon_vld4: {
2739      unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2740                              ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2741      unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2742                               ARM::VLD4q16Pseudo_UPD,
2743                               ARM::VLD4q32Pseudo_UPD };
2744      unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo,
2745                               ARM::VLD4q16oddPseudo,
2746                               ARM::VLD4q32oddPseudo };
2747      return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2748    }
2749
2750    case Intrinsic::arm_neon_vld2lane: {
2751      unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2752                              ARM::VLD2LNd32Pseudo };
2753      unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2754      return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
2755    }
2756
2757    case Intrinsic::arm_neon_vld3lane: {
2758      unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2759                              ARM::VLD3LNd32Pseudo };
2760      unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2761      return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
2762    }
2763
2764    case Intrinsic::arm_neon_vld4lane: {
2765      unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2766                              ARM::VLD4LNd32Pseudo };
2767      unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2768      return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
2769    }
2770
2771    case Intrinsic::arm_neon_vst1: {
2772      unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2773                              ARM::VST1d32, ARM::VST1d64 };
2774      unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2775                              ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2776      return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
2777    }
2778
2779    case Intrinsic::arm_neon_vst2: {
2780      unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
2781                              ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
2782      unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
2783                              ARM::VST2q32Pseudo };
2784      return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
2785    }
2786
2787    case Intrinsic::arm_neon_vst3: {
2788      unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
2789                              ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
2790      unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2791                               ARM::VST3q16Pseudo_UPD,
2792                               ARM::VST3q32Pseudo_UPD };
2793      unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo,
2794                               ARM::VST3q16oddPseudo,
2795                               ARM::VST3q32oddPseudo };
2796      return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2797    }
2798
2799    case Intrinsic::arm_neon_vst4: {
2800      unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
2801                              ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
2802      unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2803                               ARM::VST4q16Pseudo_UPD,
2804                               ARM::VST4q32Pseudo_UPD };
2805      unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo,
2806                               ARM::VST4q16oddPseudo,
2807                               ARM::VST4q32oddPseudo };
2808      return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2809    }
2810
2811    case Intrinsic::arm_neon_vst2lane: {
2812      unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
2813                              ARM::VST2LNd32Pseudo };
2814      unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
2815      return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
2816    }
2817
2818    case Intrinsic::arm_neon_vst3lane: {
2819      unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
2820                              ARM::VST3LNd32Pseudo };
2821      unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
2822      return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
2823    }
2824
2825    case Intrinsic::arm_neon_vst4lane: {
2826      unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
2827                              ARM::VST4LNd32Pseudo };
2828      unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
2829      return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
2830    }
2831    }
2832    break;
2833  }
2834
2835  case ISD::INTRINSIC_WO_CHAIN: {
2836    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2837    switch (IntNo) {
2838    default:
2839      break;
2840
2841    case Intrinsic::arm_neon_vtbl2:
2842      return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
2843    case Intrinsic::arm_neon_vtbl3:
2844      return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
2845    case Intrinsic::arm_neon_vtbl4:
2846      return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
2847
2848    case Intrinsic::arm_neon_vtbx2:
2849      return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
2850    case Intrinsic::arm_neon_vtbx3:
2851      return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
2852    case Intrinsic::arm_neon_vtbx4:
2853      return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
2854    }
2855    break;
2856  }
2857
2858  case ISD::CONCAT_VECTORS:
2859    return SelectConcatVector(N);
2860  }
2861
2862  return SelectCode(N);
2863}
2864
2865bool ARMDAGToDAGISel::
2866SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2867                             std::vector<SDValue> &OutOps) {
2868  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2869  // Require the address to be in a register.  That is safe for all ARM
2870  // variants and it is hard to do anything much smarter without knowing
2871  // how the operand is used.
2872  OutOps.push_back(Op);
2873  return false;
2874}
2875
2876/// createARMISelDag - This pass converts a legalized DAG into a
2877/// ARM-specific DAG, ready for instruction scheduling.
2878///
2879FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2880                                     CodeGenOpt::Level OptLevel) {
2881  return new ARMDAGToDAGISel(TM, OptLevel);
2882}
2883