ARMISelDAGToDAG.cpp revision 212904
150471Speter//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===// 21556Srgrimes// 31556Srgrimes// The LLVM Compiler Infrastructure 41556Srgrimes// 51556Srgrimes// This file is distributed under the University of Illinois Open Source 61556Srgrimes// License. See LICENSE.TXT for details. 71556Srgrimes// 81556Srgrimes//===----------------------------------------------------------------------===// 9265420Simp// 10156813Sru// This file defines an instruction selector for the ARM target. 1159576Sobrien// 1259355Sobrien//===----------------------------------------------------------------------===// 1359355Sobrien 141556Srgrimes#define DEBUG_TYPE "arm-isel" 15117036Sgordon#include "ARM.h" 16117036Sgordon#include "ARMAddressingModes.h" 17117036Sgordon#include "ARMTargetMachine.h" 1869551Sache#include "llvm/CallingConv.h" 19117036Sgordon#include "llvm/Constants.h" 2069640Sobrien#include "llvm/DerivedTypes.h" 21231990Smp#include "llvm/Function.h" 2259355Sobrien#include "llvm/Intrinsics.h" 2359355Sobrien#include "llvm/LLVMContext.h" 2459355Sobrien#include "llvm/CodeGen/MachineFrameInfo.h" 2569415Sache#include "llvm/CodeGen/MachineFunction.h" 2659355Sobrien#include "llvm/CodeGen/MachineInstrBuilder.h" 2759355Sobrien#include "llvm/CodeGen/SelectionDAG.h" 2859355Sobrien#include "llvm/CodeGen/SelectionDAGISel.h" 2959355Sobrien#include "llvm/Target/TargetLowering.h" 3059355Sobrien#include "llvm/Target/TargetOptions.h" 3159355Sobrien#include "llvm/Support/CommandLine.h" 32145481Smp#include "llvm/Support/Compiler.h" 3359355Sobrien#include "llvm/Support/Debug.h" 3459355Sobrien#include "llvm/Support/ErrorHandling.h" 3569415Sache#include "llvm/Support/raw_ostream.h" 3660599Sbde 371556Srgrimesusing namespace llvm; 3860029Sjkoshy 3951090Ssheldonhstatic cl::opt<bool> 4051090SsheldonhDisableShifterOp("disable-shifter-op", cl::Hidden, 4151090Ssheldonh cl::desc("Disable isel of shifter-op"), 4251090Ssheldonh cl::init(false)); 4362759Sache 4462759Sache//===--------------------------------------------------------------------===// 451556Srgrimes/// ARMDAGToDAGISel - ARM specific code to select ARM machine 4659393Sobrien/// instructions for SelectionDAG operations. 4759393Sobrien/// 4869415Sachenamespace { 4960599Sbdeclass ARMDAGToDAGISel : public SelectionDAGISel { 50156813Sru ARMBaseTargetMachine &TM; 5190559Smp 5290559Smp /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 53148673Sphk /// make the right decision when generating code for different targets. 5490559Smp const ARMSubtarget *Subtarget; 5599257Sru 5699257Srupublic: 5799257Sru explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, 5899257Sru CodeGenOpt::Level OptLevel) 5999257Sru : SelectionDAGISel(tm, OptLevel), TM(tm), 6099257Sru Subtarget(&TM.getSubtarget<ARMSubtarget>()) { 6199257Sru } 6299257Sru 6399257Sru virtual const char *getPassName() const { 6499257Sru return "ARM Instruction Selection"; 6599257Sru } 6699257Sru 6799257Sru /// getI32Imm - Return a target constant of type i32 with the specified 6899257Sru /// value. 6999257Sru inline SDValue getI32Imm(unsigned Imm) { 7099257Sru return CurDAG->getTargetConstant(Imm, MVT::i32); 7199257Sru } 7299257Sru 7399257Sru SDNode *Select(SDNode *N); 7499257Sru 75156813Sru bool SelectShifterOperandReg(SDNode *Op, SDValue N, SDValue &A, 76155835Sume SDValue &B, SDValue &C); 77155835Sume bool SelectAddrMode2(SDNode *Op, SDValue N, SDValue &Base, 78155835Sume SDValue &Offset, SDValue &Opc); 79219061Sume bool SelectAddrMode2Offset(SDNode *Op, SDValue N, 80219061Sume SDValue &Offset, SDValue &Opc); 81219061Sume bool SelectAddrMode3(SDNode *Op, SDValue N, SDValue &Base, 82219061Sume SDValue &Offset, SDValue &Opc); 83219061Sume bool SelectAddrMode3Offset(SDNode *Op, SDValue N, 84219061Sume SDValue &Offset, SDValue &Opc); 85219061Sume bool SelectAddrMode4(SDNode *Op, SDValue N, SDValue &Addr, 86219061Sume SDValue &Mode); 87219061Sume bool SelectAddrMode5(SDNode *Op, SDValue N, SDValue &Base, 88219061Sume SDValue &Offset); 89219061Sume bool SelectAddrMode6(SDNode *Op, SDValue N, SDValue &Addr, SDValue &Align); 90219061Sume 91219061Sume bool SelectAddrModePC(SDNode *Op, SDValue N, SDValue &Offset, 92219061Sume SDValue &Label); 93219061Sume 94155835Sume bool SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base, 95219061Sume SDValue &Offset); 96219061Sume bool SelectThumbAddrModeRI5(SDNode *Op, SDValue N, unsigned Scale, 97219061Sume SDValue &Base, SDValue &OffImm, 98155835Sume SDValue &Offset); 99219061Sume bool SelectThumbAddrModeS1(SDNode *Op, SDValue N, SDValue &Base, 100155835Sume SDValue &OffImm, SDValue &Offset); 10199257Sru bool SelectThumbAddrModeS2(SDNode *Op, SDValue N, SDValue &Base, 10299257Sru SDValue &OffImm, SDValue &Offset); 10399257Sru bool SelectThumbAddrModeS4(SDNode *Op, SDValue N, SDValue &Base, 10499257Sru SDValue &OffImm, SDValue &Offset); 10599257Sru bool SelectThumbAddrModeSP(SDNode *Op, SDValue N, SDValue &Base, 106155835Sume SDValue &OffImm); 10799257Sru 10899257Sru bool SelectT2ShifterOperandReg(SDNode *Op, SDValue N, 10959355Sobrien SDValue &BaseReg, SDValue &Opc); 110115898Skuriyama bool SelectT2AddrModeImm12(SDNode *Op, SDValue N, SDValue &Base, 1111556Srgrimes SDValue &OffImm); 11269551Sache bool SelectT2AddrModeImm8(SDNode *Op, SDValue N, SDValue &Base, 11369551Sache SDValue &OffImm); 11469415Sache bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N, 11569415Sache SDValue &OffImm); 116219061Sume bool SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, SDValue &Base, 117219061Sume SDValue &OffImm); 11869415Sache bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base, 119231990Smp SDValue &OffReg, SDValue &ShImm); 12069415Sache 12169415Sache inline bool Pred_so_imm(SDNode *inN) const { 122231990Smp ConstantSDNode *N = cast<ConstantSDNode>(inN); 12369415Sache return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; 12459355Sobrien } 12527965Ssteve 12627965Ssteve inline bool Pred_t2_so_imm(SDNode *inN) const { 12759355Sobrien ConstantSDNode *N = cast<ConstantSDNode>(inN); 12859355Sobrien return ARM_AM::getT2SOImmVal(N->getZExtValue()) != -1; 12959355Sobrien } 13059355Sobrien 13159355Sobrien // Include the pieces autogenerated from the target description. 13259355Sobrien#include "ARMGenDAGISel.inc" 13359355Sobrien 13459355Sobrienprivate: 13559355Sobrien /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for 13659355Sobrien /// ARM. 13769415Sache SDNode *SelectARMIndexedLoad(SDNode *N); 13859355Sobrien SDNode *SelectT2IndexedLoad(SDNode *N); 1391556Srgrimes 14059355Sobrien /// SelectVLD - Select NEON load intrinsics. NumVecs should be 14127969Ssteve /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for 14227969Ssteve /// loads of D registers and even subregs and odd subregs of Q registers. 14359355Sobrien /// For NumVecs <= 2, QOpcodes1 is not used. 14459355Sobrien SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes, 145219061Sume unsigned *QOpcodes0, unsigned *QOpcodes1); 146219061Sume 1471556Srgrimes /// SelectVST - Select NEON store intrinsics. NumVecs should 14827969Ssteve /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for 14959355Sobrien /// stores of D registers and even subregs and odd subregs of Q registers. 1501556Srgrimes /// For NumVecs <= 2, QOpcodes1 is not used. 1511556Srgrimes SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes, 152 unsigned *QOpcodes0, unsigned *QOpcodes1); 153 154 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should 155 /// be 2, 3 or 4. The opcode arrays specify the instructions used for 156 /// load/store of D registers and even subregs and odd subregs of Q registers. 157 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs, 158 unsigned *DOpcodes, unsigned *QOpcodes0, 159 unsigned *QOpcodes1); 160 161 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2, 162 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be 163 /// generated to force the table registers to be consecutive. 164 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc); 165 166 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM. 167 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned); 168 169 /// SelectCMOVOp - Select CMOV instructions for ARM. 170 SDNode *SelectCMOVOp(SDNode *N); 171 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 172 ARMCC::CondCodes CCVal, SDValue CCR, 173 SDValue InFlag); 174 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 175 ARMCC::CondCodes CCVal, SDValue CCR, 176 SDValue InFlag); 177 SDNode *SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 178 ARMCC::CondCodes CCVal, SDValue CCR, 179 SDValue InFlag); 180 SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 181 ARMCC::CondCodes CCVal, SDValue CCR, 182 SDValue InFlag); 183 184 SDNode *SelectConcatVector(SDNode *N); 185 186 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 187 /// inline asm expressions. 188 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 189 char ConstraintCode, 190 std::vector<SDValue> &OutOps); 191 192 // Form pairs of consecutive S, D, or Q registers. 193 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1); 194 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1); 195 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1); 196 197 // Form sequences of 4 consecutive S, D, or Q registers. 198 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 199 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 200 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 201 202 // Form sequences of 8 consecutive D registers. 203 SDNode *OctoDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3, 204 SDValue V4, SDValue V5, SDValue V6, SDValue V7); 205}; 206} 207 208/// isInt32Immediate - This method tests to see if the node is a 32-bit constant 209/// operand. If so Imm will receive the 32-bit value. 210static bool isInt32Immediate(SDNode *N, unsigned &Imm) { 211 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 212 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 213 return true; 214 } 215 return false; 216} 217 218// isInt32Immediate - This method tests to see if a constant operand. 219// If so Imm will receive the 32 bit value. 220static bool isInt32Immediate(SDValue N, unsigned &Imm) { 221 return isInt32Immediate(N.getNode(), Imm); 222} 223 224// isOpcWithIntImmediate - This method tests to see if the node is a specific 225// opcode and that it has a immediate integer right operand. 226// If so Imm will receive the 32 bit value. 227static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { 228 return N->getOpcode() == Opc && 229 isInt32Immediate(N->getOperand(1).getNode(), Imm); 230} 231 232 233bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op, 234 SDValue N, 235 SDValue &BaseReg, 236 SDValue &ShReg, 237 SDValue &Opc) { 238 if (DisableShifterOp) 239 return false; 240 241 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); 242 243 // Don't match base register only case. That is matched to a separate 244 // lower complexity pattern with explicit register operand. 245 if (ShOpcVal == ARM_AM::no_shift) return false; 246 247 BaseReg = N.getOperand(0); 248 unsigned ShImmVal = 0; 249 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 250 ShReg = CurDAG->getRegister(0, MVT::i32); 251 ShImmVal = RHS->getZExtValue() & 31; 252 } else { 253 ShReg = N.getOperand(1); 254 } 255 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), 256 MVT::i32); 257 return true; 258} 259 260bool ARMDAGToDAGISel::SelectAddrMode2(SDNode *Op, SDValue N, 261 SDValue &Base, SDValue &Offset, 262 SDValue &Opc) { 263 if (N.getOpcode() == ISD::MUL) { 264 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 265 // X * [3,5,9] -> X + X * [2,4,8] etc. 266 int RHSC = (int)RHS->getZExtValue(); 267 if (RHSC & 1) { 268 RHSC = RHSC & ~1; 269 ARM_AM::AddrOpc AddSub = ARM_AM::add; 270 if (RHSC < 0) { 271 AddSub = ARM_AM::sub; 272 RHSC = - RHSC; 273 } 274 if (isPowerOf2_32(RHSC)) { 275 unsigned ShAmt = Log2_32(RHSC); 276 Base = Offset = N.getOperand(0); 277 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, 278 ARM_AM::lsl), 279 MVT::i32); 280 return true; 281 } 282 } 283 } 284 } 285 286 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) { 287 Base = N; 288 if (N.getOpcode() == ISD::FrameIndex) { 289 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 290 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 291 } else if (N.getOpcode() == ARMISD::Wrapper && 292 !(Subtarget->useMovt() && 293 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 294 Base = N.getOperand(0); 295 } 296 Offset = CurDAG->getRegister(0, MVT::i32); 297 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0, 298 ARM_AM::no_shift), 299 MVT::i32); 300 return true; 301 } 302 303 // Match simple R +/- imm12 operands. 304 if (N.getOpcode() == ISD::ADD) 305 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 306 int RHSC = (int)RHS->getZExtValue(); 307 if ((RHSC >= 0 && RHSC < 0x1000) || 308 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits. 309 Base = N.getOperand(0); 310 if (Base.getOpcode() == ISD::FrameIndex) { 311 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 312 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 313 } 314 Offset = CurDAG->getRegister(0, MVT::i32); 315 316 ARM_AM::AddrOpc AddSub = ARM_AM::add; 317 if (RHSC < 0) { 318 AddSub = ARM_AM::sub; 319 RHSC = - RHSC; 320 } 321 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC, 322 ARM_AM::no_shift), 323 MVT::i32); 324 return true; 325 } 326 } 327 328 // Otherwise this is R +/- [possibly shifted] R. 329 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub; 330 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1)); 331 unsigned ShAmt = 0; 332 333 Base = N.getOperand(0); 334 Offset = N.getOperand(1); 335 336 if (ShOpcVal != ARM_AM::no_shift) { 337 // Check to see if the RHS of the shift is a constant, if not, we can't fold 338 // it. 339 if (ConstantSDNode *Sh = 340 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) { 341 ShAmt = Sh->getZExtValue(); 342 Offset = N.getOperand(1).getOperand(0); 343 } else { 344 ShOpcVal = ARM_AM::no_shift; 345 } 346 } 347 348 // Try matching (R shl C) + (R). 349 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) { 350 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0)); 351 if (ShOpcVal != ARM_AM::no_shift) { 352 // Check to see if the RHS of the shift is a constant, if not, we can't 353 // fold it. 354 if (ConstantSDNode *Sh = 355 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) { 356 ShAmt = Sh->getZExtValue(); 357 Offset = N.getOperand(0).getOperand(0); 358 Base = N.getOperand(1); 359 } else { 360 ShOpcVal = ARM_AM::no_shift; 361 } 362 } 363 } 364 365 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), 366 MVT::i32); 367 return true; 368} 369 370bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N, 371 SDValue &Offset, SDValue &Opc) { 372 unsigned Opcode = Op->getOpcode(); 373 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 374 ? cast<LoadSDNode>(Op)->getAddressingMode() 375 : cast<StoreSDNode>(Op)->getAddressingMode(); 376 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 377 ? ARM_AM::add : ARM_AM::sub; 378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) { 379 int Val = (int)C->getZExtValue(); 380 if (Val >= 0 && Val < 0x1000) { // 12 bits. 381 Offset = CurDAG->getRegister(0, MVT::i32); 382 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val, 383 ARM_AM::no_shift), 384 MVT::i32); 385 return true; 386 } 387 } 388 389 Offset = N; 390 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); 391 unsigned ShAmt = 0; 392 if (ShOpcVal != ARM_AM::no_shift) { 393 // Check to see if the RHS of the shift is a constant, if not, we can't fold 394 // it. 395 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 396 ShAmt = Sh->getZExtValue(); 397 Offset = N.getOperand(0); 398 } else { 399 ShOpcVal = ARM_AM::no_shift; 400 } 401 } 402 403 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), 404 MVT::i32); 405 return true; 406} 407 408 409bool ARMDAGToDAGISel::SelectAddrMode3(SDNode *Op, SDValue N, 410 SDValue &Base, SDValue &Offset, 411 SDValue &Opc) { 412 if (N.getOpcode() == ISD::SUB) { 413 // X - C is canonicalize to X + -C, no need to handle it here. 414 Base = N.getOperand(0); 415 Offset = N.getOperand(1); 416 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32); 417 return true; 418 } 419 420 if (N.getOpcode() != ISD::ADD) { 421 Base = N; 422 if (N.getOpcode() == ISD::FrameIndex) { 423 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 424 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 425 } 426 Offset = CurDAG->getRegister(0, MVT::i32); 427 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32); 428 return true; 429 } 430 431 // If the RHS is +/- imm8, fold into addr mode. 432 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 433 int RHSC = (int)RHS->getZExtValue(); 434 if ((RHSC >= 0 && RHSC < 256) || 435 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed. 436 Base = N.getOperand(0); 437 if (Base.getOpcode() == ISD::FrameIndex) { 438 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 439 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 440 } 441 Offset = CurDAG->getRegister(0, MVT::i32); 442 443 ARM_AM::AddrOpc AddSub = ARM_AM::add; 444 if (RHSC < 0) { 445 AddSub = ARM_AM::sub; 446 RHSC = - RHSC; 447 } 448 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32); 449 return true; 450 } 451 } 452 453 Base = N.getOperand(0); 454 Offset = N.getOperand(1); 455 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32); 456 return true; 457} 458 459bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N, 460 SDValue &Offset, SDValue &Opc) { 461 unsigned Opcode = Op->getOpcode(); 462 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 463 ? cast<LoadSDNode>(Op)->getAddressingMode() 464 : cast<StoreSDNode>(Op)->getAddressingMode(); 465 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 466 ? ARM_AM::add : ARM_AM::sub; 467 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) { 468 int Val = (int)C->getZExtValue(); 469 if (Val >= 0 && Val < 256) { 470 Offset = CurDAG->getRegister(0, MVT::i32); 471 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32); 472 return true; 473 } 474 } 475 476 Offset = N; 477 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32); 478 return true; 479} 480 481bool ARMDAGToDAGISel::SelectAddrMode4(SDNode *Op, SDValue N, 482 SDValue &Addr, SDValue &Mode) { 483 Addr = N; 484 Mode = CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32); 485 return true; 486} 487 488bool ARMDAGToDAGISel::SelectAddrMode5(SDNode *Op, SDValue N, 489 SDValue &Base, SDValue &Offset) { 490 if (N.getOpcode() != ISD::ADD) { 491 Base = N; 492 if (N.getOpcode() == ISD::FrameIndex) { 493 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 494 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 495 } else if (N.getOpcode() == ARMISD::Wrapper && 496 !(Subtarget->useMovt() && 497 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 498 Base = N.getOperand(0); 499 } 500 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), 501 MVT::i32); 502 return true; 503 } 504 505 // If the RHS is +/- imm8, fold into addr mode. 506 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 507 int RHSC = (int)RHS->getZExtValue(); 508 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4. 509 RHSC >>= 2; 510 if ((RHSC >= 0 && RHSC < 256) || 511 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed. 512 Base = N.getOperand(0); 513 if (Base.getOpcode() == ISD::FrameIndex) { 514 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 515 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 516 } 517 518 ARM_AM::AddrOpc AddSub = ARM_AM::add; 519 if (RHSC < 0) { 520 AddSub = ARM_AM::sub; 521 RHSC = - RHSC; 522 } 523 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC), 524 MVT::i32); 525 return true; 526 } 527 } 528 } 529 530 Base = N; 531 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), 532 MVT::i32); 533 return true; 534} 535 536bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Op, SDValue N, 537 SDValue &Addr, SDValue &Align) { 538 Addr = N; 539 // Default to no alignment. 540 Align = CurDAG->getTargetConstant(0, MVT::i32); 541 return true; 542} 543 544bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N, 545 SDValue &Offset, SDValue &Label) { 546 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) { 547 Offset = N.getOperand(0); 548 SDValue N1 = N.getOperand(1); 549 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(), 550 MVT::i32); 551 return true; 552 } 553 return false; 554} 555 556bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N, 557 SDValue &Base, SDValue &Offset){ 558 // FIXME dl should come from the parent load or store, not the address 559 if (N.getOpcode() != ISD::ADD) { 560 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N); 561 if (!NC || !NC->isNullValue()) 562 return false; 563 564 Base = Offset = N; 565 return true; 566 } 567 568 Base = N.getOperand(0); 569 Offset = N.getOperand(1); 570 return true; 571} 572 573bool 574ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDNode *Op, SDValue N, 575 unsigned Scale, SDValue &Base, 576 SDValue &OffImm, SDValue &Offset) { 577 if (Scale == 4) { 578 SDValue TmpBase, TmpOffImm; 579 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm)) 580 return false; // We want to select tLDRspi / tSTRspi instead. 581 if (N.getOpcode() == ARMISD::Wrapper && 582 N.getOperand(0).getOpcode() == ISD::TargetConstantPool) 583 return false; // We want to select tLDRpci instead. 584 } 585 586 if (N.getOpcode() != ISD::ADD) { 587 if (N.getOpcode() == ARMISD::Wrapper && 588 !(Subtarget->useMovt() && 589 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 590 Base = N.getOperand(0); 591 } else 592 Base = N; 593 594 Offset = CurDAG->getRegister(0, MVT::i32); 595 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 596 return true; 597 } 598 599 // Thumb does not have [sp, r] address mode. 600 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); 601 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1)); 602 if ((LHSR && LHSR->getReg() == ARM::SP) || 603 (RHSR && RHSR->getReg() == ARM::SP)) { 604 Base = N; 605 Offset = CurDAG->getRegister(0, MVT::i32); 606 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 607 return true; 608 } 609 610 // If the RHS is + imm5 * scale, fold into addr mode. 611 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 612 int RHSC = (int)RHS->getZExtValue(); 613 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied. 614 RHSC /= Scale; 615 if (RHSC >= 0 && RHSC < 32) { 616 Base = N.getOperand(0); 617 Offset = CurDAG->getRegister(0, MVT::i32); 618 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 619 return true; 620 } 621 } 622 } 623 624 Base = N.getOperand(0); 625 Offset = N.getOperand(1); 626 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 627 return true; 628} 629 630bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDNode *Op, SDValue N, 631 SDValue &Base, SDValue &OffImm, 632 SDValue &Offset) { 633 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset); 634} 635 636bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDNode *Op, SDValue N, 637 SDValue &Base, SDValue &OffImm, 638 SDValue &Offset) { 639 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset); 640} 641 642bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDNode *Op, SDValue N, 643 SDValue &Base, SDValue &OffImm, 644 SDValue &Offset) { 645 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset); 646} 647 648bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDNode *Op, SDValue N, 649 SDValue &Base, SDValue &OffImm) { 650 if (N.getOpcode() == ISD::FrameIndex) { 651 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 652 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 653 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 654 return true; 655 } 656 657 if (N.getOpcode() != ISD::ADD) 658 return false; 659 660 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); 661 if (N.getOperand(0).getOpcode() == ISD::FrameIndex || 662 (LHSR && LHSR->getReg() == ARM::SP)) { 663 // If the RHS is + imm8 * scale, fold into addr mode. 664 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 665 int RHSC = (int)RHS->getZExtValue(); 666 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied. 667 RHSC >>= 2; 668 if (RHSC >= 0 && RHSC < 256) { 669 Base = N.getOperand(0); 670 if (Base.getOpcode() == ISD::FrameIndex) { 671 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 672 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 673 } 674 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 675 return true; 676 } 677 } 678 } 679 } 680 681 return false; 682} 683 684bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N, 685 SDValue &BaseReg, 686 SDValue &Opc) { 687 if (DisableShifterOp) 688 return false; 689 690 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); 691 692 // Don't match base register only case. That is matched to a separate 693 // lower complexity pattern with explicit register operand. 694 if (ShOpcVal == ARM_AM::no_shift) return false; 695 696 BaseReg = N.getOperand(0); 697 unsigned ShImmVal = 0; 698 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 699 ShImmVal = RHS->getZExtValue() & 31; 700 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal)); 701 return true; 702 } 703 704 return false; 705} 706 707bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDNode *Op, SDValue N, 708 SDValue &Base, SDValue &OffImm) { 709 // Match simple R + imm12 operands. 710 711 // Base only. 712 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) { 713 if (N.getOpcode() == ISD::FrameIndex) { 714 // Match frame index... 715 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 716 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 717 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 718 return true; 719 } else if (N.getOpcode() == ARMISD::Wrapper && 720 !(Subtarget->useMovt() && 721 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 722 Base = N.getOperand(0); 723 if (Base.getOpcode() == ISD::TargetConstantPool) 724 return false; // We want to select t2LDRpci instead. 725 } else 726 Base = N; 727 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 728 return true; 729 } 730 731 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 732 if (SelectT2AddrModeImm8(Op, N, Base, OffImm)) 733 // Let t2LDRi8 handle (R - imm8). 734 return false; 735 736 int RHSC = (int)RHS->getZExtValue(); 737 if (N.getOpcode() == ISD::SUB) 738 RHSC = -RHSC; 739 740 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned) 741 Base = N.getOperand(0); 742 if (Base.getOpcode() == ISD::FrameIndex) { 743 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 744 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 745 } 746 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 747 return true; 748 } 749 } 750 751 // Base only. 752 Base = N; 753 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 754 return true; 755} 756 757bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDNode *Op, SDValue N, 758 SDValue &Base, SDValue &OffImm) { 759 // Match simple R - imm8 operands. 760 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) { 761 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 762 int RHSC = (int)RHS->getSExtValue(); 763 if (N.getOpcode() == ISD::SUB) 764 RHSC = -RHSC; 765 766 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative) 767 Base = N.getOperand(0); 768 if (Base.getOpcode() == ISD::FrameIndex) { 769 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 770 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 771 } 772 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 773 return true; 774 } 775 } 776 } 777 778 return false; 779} 780 781bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N, 782 SDValue &OffImm){ 783 unsigned Opcode = Op->getOpcode(); 784 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 785 ? cast<LoadSDNode>(Op)->getAddressingMode() 786 : cast<StoreSDNode>(Op)->getAddressingMode(); 787 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) { 788 int RHSC = (int)RHS->getZExtValue(); 789 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits. 790 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) 791 ? CurDAG->getTargetConstant(RHSC, MVT::i32) 792 : CurDAG->getTargetConstant(-RHSC, MVT::i32); 793 return true; 794 } 795 } 796 797 return false; 798} 799 800bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, 801 SDValue &Base, SDValue &OffImm) { 802 if (N.getOpcode() == ISD::ADD) { 803 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 804 int RHSC = (int)RHS->getZExtValue(); 805 // 8 bits. 806 if (((RHSC & 0x3) == 0) && 807 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { 808 Base = N.getOperand(0); 809 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 810 return true; 811 } 812 } 813 } else if (N.getOpcode() == ISD::SUB) { 814 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 815 int RHSC = (int)RHS->getZExtValue(); 816 // 8 bits. 817 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { 818 Base = N.getOperand(0); 819 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32); 820 return true; 821 } 822 } 823 } 824 825 return false; 826} 827 828bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDNode *Op, SDValue N, 829 SDValue &Base, 830 SDValue &OffReg, SDValue &ShImm) { 831 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12. 832 if (N.getOpcode() != ISD::ADD) 833 return false; 834 835 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8. 836 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 837 int RHSC = (int)RHS->getZExtValue(); 838 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned) 839 return false; 840 else if (RHSC < 0 && RHSC >= -255) // 8 bits 841 return false; 842 } 843 844 // Look for (R + R) or (R + (R << [1,2,3])). 845 unsigned ShAmt = 0; 846 Base = N.getOperand(0); 847 OffReg = N.getOperand(1); 848 849 // Swap if it is ((R << c) + R). 850 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg); 851 if (ShOpcVal != ARM_AM::lsl) { 852 ShOpcVal = ARM_AM::getShiftOpcForNode(Base); 853 if (ShOpcVal == ARM_AM::lsl) 854 std::swap(Base, OffReg); 855 } 856 857 if (ShOpcVal == ARM_AM::lsl) { 858 // Check to see if the RHS of the shift is a constant, if not, we can't fold 859 // it. 860 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) { 861 ShAmt = Sh->getZExtValue(); 862 if (ShAmt >= 4) { 863 ShAmt = 0; 864 ShOpcVal = ARM_AM::no_shift; 865 } else 866 OffReg = OffReg.getOperand(0); 867 } else { 868 ShOpcVal = ARM_AM::no_shift; 869 } 870 } 871 872 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32); 873 874 return true; 875} 876 877//===--------------------------------------------------------------------===// 878 879/// getAL - Returns a ARMCC::AL immediate node. 880static inline SDValue getAL(SelectionDAG *CurDAG) { 881 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32); 882} 883 884SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) { 885 LoadSDNode *LD = cast<LoadSDNode>(N); 886 ISD::MemIndexedMode AM = LD->getAddressingMode(); 887 if (AM == ISD::UNINDEXED) 888 return NULL; 889 890 EVT LoadedVT = LD->getMemoryVT(); 891 SDValue Offset, AMOpc; 892 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); 893 unsigned Opcode = 0; 894 bool Match = false; 895 if (LoadedVT == MVT::i32 && 896 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) { 897 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST; 898 Match = true; 899 } else if (LoadedVT == MVT::i16 && 900 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) { 901 Match = true; 902 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD) 903 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) 904 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); 905 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { 906 if (LD->getExtensionType() == ISD::SEXTLOAD) { 907 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) { 908 Match = true; 909 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; 910 } 911 } else { 912 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) { 913 Match = true; 914 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST; 915 } 916 } 917 } 918 919 if (Match) { 920 SDValue Chain = LD->getChain(); 921 SDValue Base = LD->getBasePtr(); 922 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), 923 CurDAG->getRegister(0, MVT::i32), Chain }; 924 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32, 925 MVT::Other, Ops, 6); 926 } 927 928 return NULL; 929} 930 931SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) { 932 LoadSDNode *LD = cast<LoadSDNode>(N); 933 ISD::MemIndexedMode AM = LD->getAddressingMode(); 934 if (AM == ISD::UNINDEXED) 935 return NULL; 936 937 EVT LoadedVT = LD->getMemoryVT(); 938 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD; 939 SDValue Offset; 940 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); 941 unsigned Opcode = 0; 942 bool Match = false; 943 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) { 944 switch (LoadedVT.getSimpleVT().SimpleTy) { 945 case MVT::i32: 946 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; 947 break; 948 case MVT::i16: 949 if (isSExtLd) 950 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST; 951 else 952 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST; 953 break; 954 case MVT::i8: 955 case MVT::i1: 956 if (isSExtLd) 957 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST; 958 else 959 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST; 960 break; 961 default: 962 return NULL; 963 } 964 Match = true; 965 } 966 967 if (Match) { 968 SDValue Chain = LD->getChain(); 969 SDValue Base = LD->getBasePtr(); 970 SDValue Ops[]= { Base, Offset, getAL(CurDAG), 971 CurDAG->getRegister(0, MVT::i32), Chain }; 972 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32, 973 MVT::Other, Ops, 5); 974 } 975 976 return NULL; 977} 978 979/// PairSRegs - Form a D register from a pair of S registers. 980/// 981SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) { 982 DebugLoc dl = V0.getNode()->getDebugLoc(); 983 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); 984 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); 985 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; 986 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); 987} 988 989/// PairDRegs - Form a quad register from a pair of D registers. 990/// 991SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) { 992 DebugLoc dl = V0.getNode()->getDebugLoc(); 993 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 994 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 995 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; 996 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); 997} 998 999/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers. 1000/// 1001SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) { 1002 DebugLoc dl = V0.getNode()->getDebugLoc(); 1003 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); 1004 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); 1005 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; 1006 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); 1007} 1008 1009/// QuadSRegs - Form 4 consecutive S registers. 1010/// 1011SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1, 1012 SDValue V2, SDValue V3) { 1013 DebugLoc dl = V0.getNode()->getDebugLoc(); 1014 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); 1015 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); 1016 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32); 1017 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32); 1018 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 }; 1019 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8); 1020} 1021 1022/// QuadDRegs - Form 4 consecutive D registers. 1023/// 1024SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1, 1025 SDValue V2, SDValue V3) { 1026 DebugLoc dl = V0.getNode()->getDebugLoc(); 1027 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 1028 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 1029 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32); 1030 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32); 1031 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 }; 1032 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8); 1033} 1034 1035/// QuadQRegs - Form 4 consecutive Q registers. 1036/// 1037SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1, 1038 SDValue V2, SDValue V3) { 1039 DebugLoc dl = V0.getNode()->getDebugLoc(); 1040 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); 1041 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); 1042 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32); 1043 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32); 1044 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 }; 1045 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8); 1046} 1047 1048/// OctoDRegs - Form 8 consecutive D registers. 1049/// 1050SDNode *ARMDAGToDAGISel::OctoDRegs(EVT VT, SDValue V0, SDValue V1, 1051 SDValue V2, SDValue V3, 1052 SDValue V4, SDValue V5, 1053 SDValue V6, SDValue V7) { 1054 DebugLoc dl = V0.getNode()->getDebugLoc(); 1055 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 1056 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 1057 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32); 1058 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32); 1059 SDValue SubReg4 = CurDAG->getTargetConstant(ARM::dsub_4, MVT::i32); 1060 SDValue SubReg5 = CurDAG->getTargetConstant(ARM::dsub_5, MVT::i32); 1061 SDValue SubReg6 = CurDAG->getTargetConstant(ARM::dsub_6, MVT::i32); 1062 SDValue SubReg7 = CurDAG->getTargetConstant(ARM::dsub_7, MVT::i32); 1063 const SDValue Ops[] ={ V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3, 1064 V4, SubReg4, V5, SubReg5, V6, SubReg6, V7, SubReg7 }; 1065 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 16); 1066} 1067 1068/// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type 1069/// for a 64-bit subregister of the vector. 1070static EVT GetNEONSubregVT(EVT VT) { 1071 switch (VT.getSimpleVT().SimpleTy) { 1072 default: llvm_unreachable("unhandled NEON type"); 1073 case MVT::v16i8: return MVT::v8i8; 1074 case MVT::v8i16: return MVT::v4i16; 1075 case MVT::v4f32: return MVT::v2f32; 1076 case MVT::v4i32: return MVT::v2i32; 1077 case MVT::v2i64: return MVT::v1i64; 1078 } 1079} 1080 1081SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs, 1082 unsigned *DOpcodes, unsigned *QOpcodes0, 1083 unsigned *QOpcodes1) { 1084 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); 1085 DebugLoc dl = N->getDebugLoc(); 1086 1087 SDValue MemAddr, Align; 1088 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align)) 1089 return NULL; 1090 1091 SDValue Chain = N->getOperand(0); 1092 EVT VT = N->getValueType(0); 1093 bool is64BitVector = VT.is64BitVector(); 1094 1095 unsigned OpcodeIndex; 1096 switch (VT.getSimpleVT().SimpleTy) { 1097 default: llvm_unreachable("unhandled vld type"); 1098 // Double-register operations: 1099 case MVT::v8i8: OpcodeIndex = 0; break; 1100 case MVT::v4i16: OpcodeIndex = 1; break; 1101 case MVT::v2f32: 1102 case MVT::v2i32: OpcodeIndex = 2; break; 1103 case MVT::v1i64: OpcodeIndex = 3; break; 1104 // Quad-register operations: 1105 case MVT::v16i8: OpcodeIndex = 0; break; 1106 case MVT::v8i16: OpcodeIndex = 1; break; 1107 case MVT::v4f32: 1108 case MVT::v4i32: OpcodeIndex = 2; break; 1109 case MVT::v2i64: OpcodeIndex = 3; 1110 assert(NumVecs == 1 && "v2i64 type only supported for VLD1"); 1111 break; 1112 } 1113 1114 EVT ResTy; 1115 if (NumVecs == 1) 1116 ResTy = VT; 1117 else { 1118 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; 1119 if (!is64BitVector) 1120 ResTyElts *= 2; 1121 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts); 1122 } 1123 1124 SDValue Pred = getAL(CurDAG); 1125 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1126 SDValue SuperReg; 1127 if (is64BitVector) { 1128 unsigned Opc = DOpcodes[OpcodeIndex]; 1129 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain }; 1130 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5); 1131 if (NumVecs == 1) 1132 return VLd; 1133 1134 SuperReg = SDValue(VLd, 0); 1135 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 1136 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { 1137 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec, 1138 dl, VT, SuperReg); 1139 ReplaceUses(SDValue(N, Vec), D); 1140 } 1141 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1)); 1142 return NULL; 1143 } 1144 1145 if (NumVecs <= 2) { 1146 // Quad registers are directly supported for VLD1 and VLD2, 1147 // loading pairs of D regs. 1148 unsigned Opc = QOpcodes0[OpcodeIndex]; 1149 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain }; 1150 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5); 1151 if (NumVecs == 1) 1152 return VLd; 1153 1154 SuperReg = SDValue(VLd, 0); 1155 Chain = SDValue(VLd, 1); 1156 1157 } else { 1158 // Otherwise, quad registers are loaded with two separate instructions, 1159 // where one loads the even registers and the other loads the odd registers. 1160 EVT AddrTy = MemAddr.getValueType(); 1161 1162 // Load the even subregs. 1163 unsigned Opc = QOpcodes0[OpcodeIndex]; 1164 SDValue ImplDef = 1165 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0); 1166 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; 1167 SDNode *VLdA = 1168 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsA, 7); 1169 Chain = SDValue(VLdA, 2); 1170 1171 // Load the odd subregs. 1172 Opc = QOpcodes1[OpcodeIndex]; 1173 const SDValue OpsB[] = { SDValue(VLdA, 1), Align, Reg0, SDValue(VLdA, 0), 1174 Pred, Reg0, Chain }; 1175 SDNode *VLdB = 1176 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsB, 7); 1177 SuperReg = SDValue(VLdB, 0); 1178 Chain = SDValue(VLdB, 2); 1179 } 1180 1181 // Extract out the Q registers. 1182 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); 1183 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { 1184 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec, 1185 dl, VT, SuperReg); 1186 ReplaceUses(SDValue(N, Vec), Q); 1187 } 1188 ReplaceUses(SDValue(N, NumVecs), Chain); 1189 return NULL; 1190} 1191 1192SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs, 1193 unsigned *DOpcodes, unsigned *QOpcodes0, 1194 unsigned *QOpcodes1) { 1195 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); 1196 DebugLoc dl = N->getDebugLoc(); 1197 1198 SDValue MemAddr, Align; 1199 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align)) 1200 return NULL; 1201 1202 SDValue Chain = N->getOperand(0); 1203 EVT VT = N->getOperand(3).getValueType(); 1204 bool is64BitVector = VT.is64BitVector(); 1205 1206 unsigned OpcodeIndex; 1207 switch (VT.getSimpleVT().SimpleTy) { 1208 default: llvm_unreachable("unhandled vst type"); 1209 // Double-register operations: 1210 case MVT::v8i8: OpcodeIndex = 0; break; 1211 case MVT::v4i16: OpcodeIndex = 1; break; 1212 case MVT::v2f32: 1213 case MVT::v2i32: OpcodeIndex = 2; break; 1214 case MVT::v1i64: OpcodeIndex = 3; break; 1215 // Quad-register operations: 1216 case MVT::v16i8: OpcodeIndex = 0; break; 1217 case MVT::v8i16: OpcodeIndex = 1; break; 1218 case MVT::v4f32: 1219 case MVT::v4i32: OpcodeIndex = 2; break; 1220 case MVT::v2i64: OpcodeIndex = 3; 1221 assert(NumVecs == 1 && "v2i64 type only supported for VST1"); 1222 break; 1223 } 1224 1225 SDValue Pred = getAL(CurDAG); 1226 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1227 1228 SmallVector<SDValue, 7> Ops; 1229 Ops.push_back(MemAddr); 1230 Ops.push_back(Align); 1231 1232 if (is64BitVector) { 1233 if (NumVecs == 1) { 1234 Ops.push_back(N->getOperand(3)); 1235 } else { 1236 SDValue RegSeq; 1237 SDValue V0 = N->getOperand(0+3); 1238 SDValue V1 = N->getOperand(1+3); 1239 1240 // Form a REG_SEQUENCE to force register allocation. 1241 if (NumVecs == 2) 1242 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1243 else { 1244 SDValue V2 = N->getOperand(2+3); 1245 // If it's a vld3, form a quad D-register and leave the last part as 1246 // an undef. 1247 SDValue V3 = (NumVecs == 3) 1248 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1249 : N->getOperand(3+3); 1250 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1251 } 1252 Ops.push_back(RegSeq); 1253 } 1254 Ops.push_back(Pred); 1255 Ops.push_back(Reg0); // predicate register 1256 Ops.push_back(Chain); 1257 unsigned Opc = DOpcodes[OpcodeIndex]; 1258 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6); 1259 } 1260 1261 if (NumVecs <= 2) { 1262 // Quad registers are directly supported for VST1 and VST2. 1263 unsigned Opc = QOpcodes0[OpcodeIndex]; 1264 if (NumVecs == 1) { 1265 Ops.push_back(N->getOperand(3)); 1266 } else { 1267 // Form a QQ register. 1268 SDValue Q0 = N->getOperand(3); 1269 SDValue Q1 = N->getOperand(4); 1270 Ops.push_back(SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0)); 1271 } 1272 Ops.push_back(Pred); 1273 Ops.push_back(Reg0); // predicate register 1274 Ops.push_back(Chain); 1275 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6); 1276 } 1277 1278 // Otherwise, quad registers are stored with two separate instructions, 1279 // where one stores the even registers and the other stores the odd registers. 1280 1281 // Form the QQQQ REG_SEQUENCE. 1282 SDValue V0 = N->getOperand(0+3); 1283 SDValue V1 = N->getOperand(1+3); 1284 SDValue V2 = N->getOperand(2+3); 1285 SDValue V3 = (NumVecs == 3) 1286 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) 1287 : N->getOperand(3+3); 1288 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); 1289 1290 // Store the even D registers. 1291 Ops.push_back(Reg0); // post-access address offset 1292 Ops.push_back(RegSeq); 1293 Ops.push_back(Pred); 1294 Ops.push_back(Reg0); // predicate register 1295 Ops.push_back(Chain); 1296 unsigned Opc = QOpcodes0[OpcodeIndex]; 1297 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), 1298 MVT::Other, Ops.data(), 7); 1299 Chain = SDValue(VStA, 1); 1300 1301 // Store the odd D registers. 1302 Ops[0] = SDValue(VStA, 0); // MemAddr 1303 Ops[6] = Chain; 1304 Opc = QOpcodes1[OpcodeIndex]; 1305 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), 1306 MVT::Other, Ops.data(), 7); 1307 Chain = SDValue(VStB, 1); 1308 ReplaceUses(SDValue(N, 0), Chain); 1309 return NULL; 1310} 1311 1312SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, 1313 unsigned NumVecs, unsigned *DOpcodes, 1314 unsigned *QOpcodes0, 1315 unsigned *QOpcodes1) { 1316 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range"); 1317 DebugLoc dl = N->getDebugLoc(); 1318 1319 SDValue MemAddr, Align; 1320 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align)) 1321 return NULL; 1322 1323 SDValue Chain = N->getOperand(0); 1324 unsigned Lane = 1325 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue(); 1326 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType(); 1327 bool is64BitVector = VT.is64BitVector(); 1328 1329 // Quad registers are handled by load/store of subregs. Find the subreg info. 1330 unsigned NumElts = 0; 1331 bool Even = false; 1332 EVT RegVT = VT; 1333 if (!is64BitVector) { 1334 RegVT = GetNEONSubregVT(VT); 1335 NumElts = RegVT.getVectorNumElements(); 1336 Even = Lane < NumElts; 1337 } 1338 1339 unsigned OpcodeIndex; 1340 switch (VT.getSimpleVT().SimpleTy) { 1341 default: llvm_unreachable("unhandled vld/vst lane type"); 1342 // Double-register operations: 1343 case MVT::v8i8: OpcodeIndex = 0; break; 1344 case MVT::v4i16: OpcodeIndex = 1; break; 1345 case MVT::v2f32: 1346 case MVT::v2i32: OpcodeIndex = 2; break; 1347 // Quad-register operations: 1348 case MVT::v8i16: OpcodeIndex = 0; break; 1349 case MVT::v4f32: 1350 case MVT::v4i32: OpcodeIndex = 1; break; 1351 } 1352 1353 SDValue Pred = getAL(CurDAG); 1354 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1355 1356 SmallVector<SDValue, 10> Ops; 1357 Ops.push_back(MemAddr); 1358 Ops.push_back(Align); 1359 1360 unsigned Opc = 0; 1361 if (is64BitVector) { 1362 Opc = DOpcodes[OpcodeIndex]; 1363 SDValue RegSeq; 1364 SDValue V0 = N->getOperand(0+3); 1365 SDValue V1 = N->getOperand(1+3); 1366 if (NumVecs == 2) { 1367 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1368 } else { 1369 SDValue V2 = N->getOperand(2+3); 1370 SDValue V3 = (NumVecs == 3) 1371 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1372 : N->getOperand(3+3); 1373 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1374 } 1375 1376 // Now extract the D registers back out. 1377 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq)); 1378 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq)); 1379 if (NumVecs > 2) 1380 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,RegSeq)); 1381 if (NumVecs > 3) 1382 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,RegSeq)); 1383 } else { 1384 // Check if this is loading the even or odd subreg of a Q register. 1385 if (Lane < NumElts) { 1386 Opc = QOpcodes0[OpcodeIndex]; 1387 } else { 1388 Lane -= NumElts; 1389 Opc = QOpcodes1[OpcodeIndex]; 1390 } 1391 1392 SDValue RegSeq; 1393 SDValue V0 = N->getOperand(0+3); 1394 SDValue V1 = N->getOperand(1+3); 1395 if (NumVecs == 2) { 1396 RegSeq = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0); 1397 } else { 1398 SDValue V2 = N->getOperand(2+3); 1399 SDValue V3 = (NumVecs == 3) 1400 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1401 : N->getOperand(3+3); 1402 RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); 1403 } 1404 1405 // Extract the subregs of the input vector. 1406 unsigned SubIdx = Even ? ARM::dsub_0 : ARM::dsub_1; 1407 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1408 Ops.push_back(CurDAG->getTargetExtractSubreg(SubIdx+Vec*2, dl, RegVT, 1409 RegSeq)); 1410 } 1411 Ops.push_back(getI32Imm(Lane)); 1412 Ops.push_back(Pred); 1413 Ops.push_back(Reg0); 1414 Ops.push_back(Chain); 1415 1416 if (!IsLoad) 1417 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+6); 1418 1419 std::vector<EVT> ResTys(NumVecs, RegVT); 1420 ResTys.push_back(MVT::Other); 1421 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(),NumVecs+6); 1422 1423 // Form a REG_SEQUENCE to force register allocation. 1424 SDValue RegSeq; 1425 if (is64BitVector) { 1426 SDValue V0 = SDValue(VLdLn, 0); 1427 SDValue V1 = SDValue(VLdLn, 1); 1428 if (NumVecs == 2) { 1429 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1430 } else { 1431 SDValue V2 = SDValue(VLdLn, 2); 1432 // If it's a vld3, form a quad D-register but discard the last part. 1433 SDValue V3 = (NumVecs == 3) 1434 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1435 : SDValue(VLdLn, 3); 1436 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1437 } 1438 } else { 1439 // For 128-bit vectors, take the 64-bit results of the load and insert 1440 // them as subregs into the result. 1441 SDValue V[8]; 1442 for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) { 1443 if (Even) { 1444 V[i] = SDValue(VLdLn, Vec); 1445 V[i+1] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1446 dl, RegVT), 0); 1447 } else { 1448 V[i] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1449 dl, RegVT), 0); 1450 V[i+1] = SDValue(VLdLn, Vec); 1451 } 1452 } 1453 if (NumVecs == 3) 1454 V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1455 dl, RegVT), 0); 1456 1457 if (NumVecs == 2) 1458 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V[0], V[1], V[2], V[3]), 0); 1459 else 1460 RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3], 1461 V[4], V[5], V[6], V[7]), 0); 1462 } 1463 1464 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 1465 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); 1466 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; 1467 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1468 ReplaceUses(SDValue(N, Vec), 1469 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, RegSeq)); 1470 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, NumVecs)); 1471 return NULL; 1472} 1473 1474SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, 1475 unsigned Opc) { 1476 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range"); 1477 DebugLoc dl = N->getDebugLoc(); 1478 EVT VT = N->getValueType(0); 1479 unsigned FirstTblReg = IsExt ? 2 : 1; 1480 1481 // Form a REG_SEQUENCE to force register allocation. 1482 SDValue RegSeq; 1483 SDValue V0 = N->getOperand(FirstTblReg + 0); 1484 SDValue V1 = N->getOperand(FirstTblReg + 1); 1485 if (NumVecs == 2) 1486 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0); 1487 else { 1488 SDValue V2 = N->getOperand(FirstTblReg + 2); 1489 // If it's a vtbl3, form a quad D-register and leave the last part as 1490 // an undef. 1491 SDValue V3 = (NumVecs == 3) 1492 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) 1493 : N->getOperand(FirstTblReg + 3); 1494 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1495 } 1496 1497 // Now extract the D registers back out. 1498 SmallVector<SDValue, 6> Ops; 1499 if (IsExt) 1500 Ops.push_back(N->getOperand(1)); 1501 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq)); 1502 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq)); 1503 if (NumVecs > 2) 1504 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT, RegSeq)); 1505 if (NumVecs > 3) 1506 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT, RegSeq)); 1507 1508 Ops.push_back(N->getOperand(FirstTblReg + NumVecs)); 1509 Ops.push_back(getAL(CurDAG)); // predicate 1510 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register 1511 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size()); 1512} 1513 1514SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N, 1515 bool isSigned) { 1516 if (!Subtarget->hasV6T2Ops()) 1517 return NULL; 1518 1519 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX) 1520 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX); 1521 1522 1523 // For unsigned extracts, check for a shift right and mask 1524 unsigned And_imm = 0; 1525 if (N->getOpcode() == ISD::AND) { 1526 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) { 1527 1528 // The immediate is a mask of the low bits iff imm & (imm+1) == 0 1529 if (And_imm & (And_imm + 1)) 1530 return NULL; 1531 1532 unsigned Srl_imm = 0; 1533 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, 1534 Srl_imm)) { 1535 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!"); 1536 1537 unsigned Width = CountTrailingOnes_32(And_imm); 1538 unsigned LSB = Srl_imm; 1539 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1540 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1541 CurDAG->getTargetConstant(LSB, MVT::i32), 1542 CurDAG->getTargetConstant(Width, MVT::i32), 1543 getAL(CurDAG), Reg0 }; 1544 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 1545 } 1546 } 1547 return NULL; 1548 } 1549 1550 // Otherwise, we're looking for a shift of a shift 1551 unsigned Shl_imm = 0; 1552 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) { 1553 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!"); 1554 unsigned Srl_imm = 0; 1555 if (isInt32Immediate(N->getOperand(1), Srl_imm)) { 1556 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!"); 1557 unsigned Width = 32 - Srl_imm; 1558 int LSB = Srl_imm - Shl_imm; 1559 if (LSB < 0) 1560 return NULL; 1561 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1562 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1563 CurDAG->getTargetConstant(LSB, MVT::i32), 1564 CurDAG->getTargetConstant(Width, MVT::i32), 1565 getAL(CurDAG), Reg0 }; 1566 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 1567 } 1568 } 1569 return NULL; 1570} 1571 1572SDNode *ARMDAGToDAGISel:: 1573SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 1574 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 1575 SDValue CPTmp0; 1576 SDValue CPTmp1; 1577 if (SelectT2ShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1)) { 1578 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue(); 1579 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal); 1580 unsigned Opc = 0; 1581 switch (SOShOp) { 1582 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break; 1583 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break; 1584 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break; 1585 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break; 1586 default: 1587 llvm_unreachable("Unknown so_reg opcode!"); 1588 break; 1589 } 1590 SDValue SOShImm = 1591 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32); 1592 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 1593 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag }; 1594 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6); 1595 } 1596 return 0; 1597} 1598 1599SDNode *ARMDAGToDAGISel:: 1600SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 1601 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 1602 SDValue CPTmp0; 1603 SDValue CPTmp1; 1604 SDValue CPTmp2; 1605 if (SelectShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1, CPTmp2)) { 1606 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 1607 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag }; 1608 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7); 1609 } 1610 return 0; 1611} 1612 1613SDNode *ARMDAGToDAGISel:: 1614SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 1615 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 1616 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal); 1617 if (!T) 1618 return 0; 1619 1620 if (Pred_t2_so_imm(TrueVal.getNode())) { 1621 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); 1622 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 1623 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; 1624 return CurDAG->SelectNodeTo(N, 1625 ARM::t2MOVCCi, MVT::i32, Ops, 5); 1626 } 1627 return 0; 1628} 1629 1630SDNode *ARMDAGToDAGISel:: 1631SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 1632 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 1633 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal); 1634 if (!T) 1635 return 0; 1636 1637 if (Pred_so_imm(TrueVal.getNode())) { 1638 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); 1639 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 1640 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; 1641 return CurDAG->SelectNodeTo(N, 1642 ARM::MOVCCi, MVT::i32, Ops, 5); 1643 } 1644 return 0; 1645} 1646 1647SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) { 1648 EVT VT = N->getValueType(0); 1649 SDValue FalseVal = N->getOperand(0); 1650 SDValue TrueVal = N->getOperand(1); 1651 SDValue CC = N->getOperand(2); 1652 SDValue CCR = N->getOperand(3); 1653 SDValue InFlag = N->getOperand(4); 1654 assert(CC.getOpcode() == ISD::Constant); 1655 assert(CCR.getOpcode() == ISD::Register); 1656 ARMCC::CondCodes CCVal = 1657 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue(); 1658 1659 if (!Subtarget->isThumb1Only() && VT == MVT::i32) { 1660 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) 1661 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) 1662 // Pattern complexity = 18 cost = 1 size = 0 1663 SDValue CPTmp0; 1664 SDValue CPTmp1; 1665 SDValue CPTmp2; 1666 if (Subtarget->isThumb()) { 1667 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal, 1668 CCVal, CCR, InFlag); 1669 if (!Res) 1670 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal, 1671 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 1672 if (Res) 1673 return Res; 1674 } else { 1675 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal, 1676 CCVal, CCR, InFlag); 1677 if (!Res) 1678 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal, 1679 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 1680 if (Res) 1681 return Res; 1682 } 1683 1684 // Pattern: (ARMcmov:i32 GPR:i32:$false, 1685 // (imm:i32)<<P:Pred_so_imm>>:$true, 1686 // (imm:i32):$cc) 1687 // Emits: (MOVCCi:i32 GPR:i32:$false, 1688 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc) 1689 // Pattern complexity = 10 cost = 1 size = 0 1690 if (Subtarget->isThumb()) { 1691 SDNode *Res = SelectT2CMOVSoImmOp(N, FalseVal, TrueVal, 1692 CCVal, CCR, InFlag); 1693 if (!Res) 1694 Res = SelectT2CMOVSoImmOp(N, TrueVal, FalseVal, 1695 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 1696 if (Res) 1697 return Res; 1698 } else { 1699 SDNode *Res = SelectARMCMOVSoImmOp(N, FalseVal, TrueVal, 1700 CCVal, CCR, InFlag); 1701 if (!Res) 1702 Res = SelectARMCMOVSoImmOp(N, TrueVal, FalseVal, 1703 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 1704 if (Res) 1705 return Res; 1706 } 1707 } 1708 1709 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 1710 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 1711 // Pattern complexity = 6 cost = 1 size = 0 1712 // 1713 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 1714 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 1715 // Pattern complexity = 6 cost = 11 size = 0 1716 // 1717 // Also FCPYScc and FCPYDcc. 1718 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32); 1719 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag }; 1720 unsigned Opc = 0; 1721 switch (VT.getSimpleVT().SimpleTy) { 1722 default: assert(false && "Illegal conditional move type!"); 1723 break; 1724 case MVT::i32: 1725 Opc = Subtarget->isThumb() 1726 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo) 1727 : ARM::MOVCCr; 1728 break; 1729 case MVT::f32: 1730 Opc = ARM::VMOVScc; 1731 break; 1732 case MVT::f64: 1733 Opc = ARM::VMOVDcc; 1734 break; 1735 } 1736 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5); 1737} 1738 1739SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) { 1740 // The only time a CONCAT_VECTORS operation can have legal types is when 1741 // two 64-bit vectors are concatenated to a 128-bit vector. 1742 EVT VT = N->getValueType(0); 1743 if (!VT.is128BitVector() || N->getNumOperands() != 2) 1744 llvm_unreachable("unexpected CONCAT_VECTORS"); 1745 DebugLoc dl = N->getDebugLoc(); 1746 SDValue V0 = N->getOperand(0); 1747 SDValue V1 = N->getOperand(1); 1748 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 1749 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 1750 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; 1751 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); 1752} 1753 1754SDNode *ARMDAGToDAGISel::Select(SDNode *N) { 1755 DebugLoc dl = N->getDebugLoc(); 1756 1757 if (N->isMachineOpcode()) 1758 return NULL; // Already selected. 1759 1760 switch (N->getOpcode()) { 1761 default: break; 1762 case ISD::Constant: { 1763 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue(); 1764 bool UseCP = true; 1765 if (Subtarget->hasThumb2()) 1766 // Thumb2-aware targets have the MOVT instruction, so all immediates can 1767 // be done with MOV + MOVT, at worst. 1768 UseCP = 0; 1769 else { 1770 if (Subtarget->isThumb()) { 1771 UseCP = (Val > 255 && // MOV 1772 ~Val > 255 && // MOV + MVN 1773 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL 1774 } else 1775 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV 1776 ARM_AM::getSOImmVal(~Val) == -1 && // MVN 1777 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs. 1778 } 1779 1780 if (UseCP) { 1781 SDValue CPIdx = 1782 CurDAG->getTargetConstantPool(ConstantInt::get( 1783 Type::getInt32Ty(*CurDAG->getContext()), Val), 1784 TLI.getPointerTy()); 1785 1786 SDNode *ResNode; 1787 if (Subtarget->isThumb1Only()) { 1788 SDValue Pred = getAL(CurDAG); 1789 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 1790 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; 1791 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, 1792 Ops, 4); 1793 } else { 1794 SDValue Ops[] = { 1795 CPIdx, 1796 CurDAG->getRegister(0, MVT::i32), 1797 CurDAG->getTargetConstant(0, MVT::i32), 1798 getAL(CurDAG), 1799 CurDAG->getRegister(0, MVT::i32), 1800 CurDAG->getEntryNode() 1801 }; 1802 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, 1803 Ops, 6); 1804 } 1805 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0)); 1806 return NULL; 1807 } 1808 1809 // Other cases are autogenerated. 1810 break; 1811 } 1812 case ISD::FrameIndex: { 1813 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm. 1814 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 1815 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 1816 if (Subtarget->isThumb1Only()) { 1817 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI, 1818 CurDAG->getTargetConstant(0, MVT::i32)); 1819 } else { 1820 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? 1821 ARM::t2ADDri : ARM::ADDri); 1822 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), 1823 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 1824 CurDAG->getRegister(0, MVT::i32) }; 1825 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 1826 } 1827 } 1828 case ISD::SRL: 1829 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false)) 1830 return I; 1831 break; 1832 case ISD::SRA: 1833 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true)) 1834 return I; 1835 break; 1836 case ISD::MUL: 1837 if (Subtarget->isThumb1Only()) 1838 break; 1839 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 1840 unsigned RHSV = C->getZExtValue(); 1841 if (!RHSV) break; 1842 if (isPowerOf2_32(RHSV-1)) { // 2^n+1? 1843 unsigned ShImm = Log2_32(RHSV-1); 1844 if (ShImm >= 32) 1845 break; 1846 SDValue V = N->getOperand(0); 1847 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); 1848 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32); 1849 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1850 if (Subtarget->isThumb()) { 1851 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 1852 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6); 1853 } else { 1854 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 1855 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7); 1856 } 1857 } 1858 if (isPowerOf2_32(RHSV+1)) { // 2^n-1? 1859 unsigned ShImm = Log2_32(RHSV+1); 1860 if (ShImm >= 32) 1861 break; 1862 SDValue V = N->getOperand(0); 1863 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); 1864 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32); 1865 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1866 if (Subtarget->isThumb()) { 1867 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 1868 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6); 1869 } else { 1870 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 1871 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7); 1872 } 1873 } 1874 } 1875 break; 1876 case ISD::AND: { 1877 // Check for unsigned bitfield extract 1878 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false)) 1879 return I; 1880 1881 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits 1882 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits 1883 // are entirely contributed by c2 and lower 16-bits are entirely contributed 1884 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)). 1885 // Select it to: "movt x, ((c1 & 0xffff) >> 16) 1886 EVT VT = N->getValueType(0); 1887 if (VT != MVT::i32) 1888 break; 1889 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2()) 1890 ? ARM::t2MOVTi16 1891 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0); 1892 if (!Opc) 1893 break; 1894 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1895 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1896 if (!N1C) 1897 break; 1898 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) { 1899 SDValue N2 = N0.getOperand(1); 1900 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1901 if (!N2C) 1902 break; 1903 unsigned N1CVal = N1C->getZExtValue(); 1904 unsigned N2CVal = N2C->getZExtValue(); 1905 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) && 1906 (N1CVal & 0xffffU) == 0xffffU && 1907 (N2CVal & 0xffffU) == 0x0U) { 1908 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16, 1909 MVT::i32); 1910 SDValue Ops[] = { N0.getOperand(0), Imm16, 1911 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; 1912 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4); 1913 } 1914 } 1915 break; 1916 } 1917 case ARMISD::VMOVRRD: 1918 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, 1919 N->getOperand(0), getAL(CurDAG), 1920 CurDAG->getRegister(0, MVT::i32)); 1921 case ISD::UMUL_LOHI: { 1922 if (Subtarget->isThumb1Only()) 1923 break; 1924 if (Subtarget->isThumb()) { 1925 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 1926 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 1927 CurDAG->getRegister(0, MVT::i32) }; 1928 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4); 1929 } else { 1930 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 1931 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 1932 CurDAG->getRegister(0, MVT::i32) }; 1933 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5); 1934 } 1935 } 1936 case ISD::SMUL_LOHI: { 1937 if (Subtarget->isThumb1Only()) 1938 break; 1939 if (Subtarget->isThumb()) { 1940 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 1941 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; 1942 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4); 1943 } else { 1944 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 1945 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 1946 CurDAG->getRegister(0, MVT::i32) }; 1947 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5); 1948 } 1949 } 1950 case ISD::LOAD: { 1951 SDNode *ResNode = 0; 1952 if (Subtarget->isThumb() && Subtarget->hasThumb2()) 1953 ResNode = SelectT2IndexedLoad(N); 1954 else 1955 ResNode = SelectARMIndexedLoad(N); 1956 if (ResNode) 1957 return ResNode; 1958 // Other cases are autogenerated. 1959 break; 1960 } 1961 case ARMISD::BRCOND: { 1962 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 1963 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc) 1964 // Pattern complexity = 6 cost = 1 size = 0 1965 1966 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 1967 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc) 1968 // Pattern complexity = 6 cost = 1 size = 0 1969 1970 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 1971 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc) 1972 // Pattern complexity = 6 cost = 1 size = 0 1973 1974 unsigned Opc = Subtarget->isThumb() ? 1975 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc; 1976 SDValue Chain = N->getOperand(0); 1977 SDValue N1 = N->getOperand(1); 1978 SDValue N2 = N->getOperand(2); 1979 SDValue N3 = N->getOperand(3); 1980 SDValue InFlag = N->getOperand(4); 1981 assert(N1.getOpcode() == ISD::BasicBlock); 1982 assert(N2.getOpcode() == ISD::Constant); 1983 assert(N3.getOpcode() == ISD::Register); 1984 1985 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) 1986 cast<ConstantSDNode>(N2)->getZExtValue()), 1987 MVT::i32); 1988 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; 1989 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other, 1990 MVT::Flag, Ops, 5); 1991 Chain = SDValue(ResNode, 0); 1992 if (N->getNumValues() == 2) { 1993 InFlag = SDValue(ResNode, 1); 1994 ReplaceUses(SDValue(N, 1), InFlag); 1995 } 1996 ReplaceUses(SDValue(N, 0), 1997 SDValue(Chain.getNode(), Chain.getResNo())); 1998 return NULL; 1999 } 2000 case ARMISD::CMOV: 2001 return SelectCMOVOp(N); 2002 case ARMISD::CNEG: { 2003 EVT VT = N->getValueType(0); 2004 SDValue N0 = N->getOperand(0); 2005 SDValue N1 = N->getOperand(1); 2006 SDValue N2 = N->getOperand(2); 2007 SDValue N3 = N->getOperand(3); 2008 SDValue InFlag = N->getOperand(4); 2009 assert(N2.getOpcode() == ISD::Constant); 2010 assert(N3.getOpcode() == ISD::Register); 2011 2012 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) 2013 cast<ConstantSDNode>(N2)->getZExtValue()), 2014 MVT::i32); 2015 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag }; 2016 unsigned Opc = 0; 2017 switch (VT.getSimpleVT().SimpleTy) { 2018 default: assert(false && "Illegal conditional move type!"); 2019 break; 2020 case MVT::f32: 2021 Opc = ARM::VNEGScc; 2022 break; 2023 case MVT::f64: 2024 Opc = ARM::VNEGDcc; 2025 break; 2026 } 2027 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5); 2028 } 2029 2030 case ARMISD::VZIP: { 2031 unsigned Opc = 0; 2032 EVT VT = N->getValueType(0); 2033 switch (VT.getSimpleVT().SimpleTy) { 2034 default: return NULL; 2035 case MVT::v8i8: Opc = ARM::VZIPd8; break; 2036 case MVT::v4i16: Opc = ARM::VZIPd16; break; 2037 case MVT::v2f32: 2038 case MVT::v2i32: Opc = ARM::VZIPd32; break; 2039 case MVT::v16i8: Opc = ARM::VZIPq8; break; 2040 case MVT::v8i16: Opc = ARM::VZIPq16; break; 2041 case MVT::v4f32: 2042 case MVT::v4i32: Opc = ARM::VZIPq32; break; 2043 } 2044 SDValue Pred = getAL(CurDAG); 2045 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2046 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2047 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); 2048 } 2049 case ARMISD::VUZP: { 2050 unsigned Opc = 0; 2051 EVT VT = N->getValueType(0); 2052 switch (VT.getSimpleVT().SimpleTy) { 2053 default: return NULL; 2054 case MVT::v8i8: Opc = ARM::VUZPd8; break; 2055 case MVT::v4i16: Opc = ARM::VUZPd16; break; 2056 case MVT::v2f32: 2057 case MVT::v2i32: Opc = ARM::VUZPd32; break; 2058 case MVT::v16i8: Opc = ARM::VUZPq8; break; 2059 case MVT::v8i16: Opc = ARM::VUZPq16; break; 2060 case MVT::v4f32: 2061 case MVT::v4i32: Opc = ARM::VUZPq32; break; 2062 } 2063 SDValue Pred = getAL(CurDAG); 2064 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2065 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2066 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); 2067 } 2068 case ARMISD::VTRN: { 2069 unsigned Opc = 0; 2070 EVT VT = N->getValueType(0); 2071 switch (VT.getSimpleVT().SimpleTy) { 2072 default: return NULL; 2073 case MVT::v8i8: Opc = ARM::VTRNd8; break; 2074 case MVT::v4i16: Opc = ARM::VTRNd16; break; 2075 case MVT::v2f32: 2076 case MVT::v2i32: Opc = ARM::VTRNd32; break; 2077 case MVT::v16i8: Opc = ARM::VTRNq8; break; 2078 case MVT::v8i16: Opc = ARM::VTRNq16; break; 2079 case MVT::v4f32: 2080 case MVT::v4i32: Opc = ARM::VTRNq32; break; 2081 } 2082 SDValue Pred = getAL(CurDAG); 2083 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2084 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2085 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); 2086 } 2087 case ARMISD::BUILD_VECTOR: { 2088 EVT VecVT = N->getValueType(0); 2089 EVT EltVT = VecVT.getVectorElementType(); 2090 unsigned NumElts = VecVT.getVectorNumElements(); 2091 if (EltVT.getSimpleVT() == MVT::f64) { 2092 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR"); 2093 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1)); 2094 } 2095 assert(EltVT.getSimpleVT() == MVT::f32 && 2096 "unexpected type for BUILD_VECTOR"); 2097 if (NumElts == 2) 2098 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1)); 2099 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR"); 2100 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1), 2101 N->getOperand(2), N->getOperand(3)); 2102 } 2103 2104 case ISD::INTRINSIC_VOID: 2105 case ISD::INTRINSIC_W_CHAIN: { 2106 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 2107 switch (IntNo) { 2108 default: 2109 break; 2110 2111 case Intrinsic::arm_neon_vld1: { 2112 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16, 2113 ARM::VLD1d32, ARM::VLD1d64 }; 2114 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo, 2115 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo }; 2116 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0); 2117 } 2118 2119 case Intrinsic::arm_neon_vld2: { 2120 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo, 2121 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo }; 2122 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo, 2123 ARM::VLD2q32Pseudo }; 2124 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0); 2125 } 2126 2127 case Intrinsic::arm_neon_vld3: { 2128 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo, 2129 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo }; 2130 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, 2131 ARM::VLD3q16Pseudo_UPD, 2132 ARM::VLD3q32Pseudo_UPD }; 2133 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD, 2134 ARM::VLD3q16oddPseudo_UPD, 2135 ARM::VLD3q32oddPseudo_UPD }; 2136 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1); 2137 } 2138 2139 case Intrinsic::arm_neon_vld4: { 2140 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo, 2141 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo }; 2142 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD, 2143 ARM::VLD4q16Pseudo_UPD, 2144 ARM::VLD4q32Pseudo_UPD }; 2145 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD, 2146 ARM::VLD4q16oddPseudo_UPD, 2147 ARM::VLD4q32oddPseudo_UPD }; 2148 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1); 2149 } 2150 2151 case Intrinsic::arm_neon_vld2lane: { 2152 unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 }; 2153 unsigned QOpcodes0[] = { ARM::VLD2LNq16, ARM::VLD2LNq32 }; 2154 unsigned QOpcodes1[] = { ARM::VLD2LNq16odd, ARM::VLD2LNq32odd }; 2155 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes0, QOpcodes1); 2156 } 2157 2158 case Intrinsic::arm_neon_vld3lane: { 2159 unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 }; 2160 unsigned QOpcodes0[] = { ARM::VLD3LNq16, ARM::VLD3LNq32 }; 2161 unsigned QOpcodes1[] = { ARM::VLD3LNq16odd, ARM::VLD3LNq32odd }; 2162 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1); 2163 } 2164 2165 case Intrinsic::arm_neon_vld4lane: { 2166 unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 }; 2167 unsigned QOpcodes0[] = { ARM::VLD4LNq16, ARM::VLD4LNq32 }; 2168 unsigned QOpcodes1[] = { ARM::VLD4LNq16odd, ARM::VLD4LNq32odd }; 2169 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1); 2170 } 2171 2172 case Intrinsic::arm_neon_vst1: { 2173 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16, 2174 ARM::VST1d32, ARM::VST1d64 }; 2175 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo, 2176 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo }; 2177 return SelectVST(N, 1, DOpcodes, QOpcodes, 0); 2178 } 2179 2180 case Intrinsic::arm_neon_vst2: { 2181 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo, 2182 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo }; 2183 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo, 2184 ARM::VST2q32Pseudo }; 2185 return SelectVST(N, 2, DOpcodes, QOpcodes, 0); 2186 } 2187 2188 case Intrinsic::arm_neon_vst3: { 2189 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo, 2190 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo }; 2191 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD, 2192 ARM::VST3q16Pseudo_UPD, 2193 ARM::VST3q32Pseudo_UPD }; 2194 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD, 2195 ARM::VST3q16oddPseudo_UPD, 2196 ARM::VST3q32oddPseudo_UPD }; 2197 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1); 2198 } 2199 2200 case Intrinsic::arm_neon_vst4: { 2201 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo, 2202 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo }; 2203 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD, 2204 ARM::VST4q16Pseudo_UPD, 2205 ARM::VST4q32Pseudo_UPD }; 2206 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD, 2207 ARM::VST4q16oddPseudo_UPD, 2208 ARM::VST4q32oddPseudo_UPD }; 2209 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1); 2210 } 2211 2212 case Intrinsic::arm_neon_vst2lane: { 2213 unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 }; 2214 unsigned QOpcodes0[] = { ARM::VST2LNq16, ARM::VST2LNq32 }; 2215 unsigned QOpcodes1[] = { ARM::VST2LNq16odd, ARM::VST2LNq32odd }; 2216 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes0, QOpcodes1); 2217 } 2218 2219 case Intrinsic::arm_neon_vst3lane: { 2220 unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 }; 2221 unsigned QOpcodes0[] = { ARM::VST3LNq16, ARM::VST3LNq32 }; 2222 unsigned QOpcodes1[] = { ARM::VST3LNq16odd, ARM::VST3LNq32odd }; 2223 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1); 2224 } 2225 2226 case Intrinsic::arm_neon_vst4lane: { 2227 unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 }; 2228 unsigned QOpcodes0[] = { ARM::VST4LNq16, ARM::VST4LNq32 }; 2229 unsigned QOpcodes1[] = { ARM::VST4LNq16odd, ARM::VST4LNq32odd }; 2230 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1); 2231 } 2232 } 2233 break; 2234 } 2235 2236 case ISD::INTRINSIC_WO_CHAIN: { 2237 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 2238 switch (IntNo) { 2239 default: 2240 break; 2241 2242 case Intrinsic::arm_neon_vtbl2: 2243 return SelectVTBL(N, false, 2, ARM::VTBL2); 2244 case Intrinsic::arm_neon_vtbl3: 2245 return SelectVTBL(N, false, 3, ARM::VTBL3); 2246 case Intrinsic::arm_neon_vtbl4: 2247 return SelectVTBL(N, false, 4, ARM::VTBL4); 2248 2249 case Intrinsic::arm_neon_vtbx2: 2250 return SelectVTBL(N, true, 2, ARM::VTBX2); 2251 case Intrinsic::arm_neon_vtbx3: 2252 return SelectVTBL(N, true, 3, ARM::VTBX3); 2253 case Intrinsic::arm_neon_vtbx4: 2254 return SelectVTBL(N, true, 4, ARM::VTBX4); 2255 } 2256 break; 2257 } 2258 2259 case ISD::CONCAT_VECTORS: 2260 return SelectConcatVector(N); 2261 } 2262 2263 return SelectCode(N); 2264} 2265 2266bool ARMDAGToDAGISel:: 2267SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 2268 std::vector<SDValue> &OutOps) { 2269 assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); 2270 // Require the address to be in a register. That is safe for all ARM 2271 // variants and it is hard to do anything much smarter without knowing 2272 // how the operand is used. 2273 OutOps.push_back(Op); 2274 return false; 2275} 2276 2277/// createARMISelDag - This pass converts a legalized DAG into a 2278/// ARM-specific DAG, ready for instruction scheduling. 2279/// 2280FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM, 2281 CodeGenOpt::Level OptLevel) { 2282 return new ARMDAGToDAGISel(TM, OptLevel); 2283} 2284