ARMISelDAGToDAG.cpp revision 199989 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMISelLowering.h"
17#include "ARMTargetMachine.h"
18#include "llvm/CallingConv.h"
19#include "llvm/Constants.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/LLVMContext.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/SelectionDAG.h"
28#include "llvm/CodeGen/SelectionDAGISel.h"
29#include "llvm/Target/TargetLowering.h"
30#include "llvm/Target/TargetOptions.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35
36using namespace llvm;
37
38//===--------------------------------------------------------------------===//
39/// ARMDAGToDAGISel - ARM specific code to select ARM machine
40/// instructions for SelectionDAG operations.
41///
42namespace {
43class ARMDAGToDAGISel : public SelectionDAGISel {
44  ARMBaseTargetMachine &TM;
45
46  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
47  /// make the right decision when generating code for different targets.
48  const ARMSubtarget *Subtarget;
49
50public:
51  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
52                           CodeGenOpt::Level OptLevel)
53    : SelectionDAGISel(tm, OptLevel), TM(tm),
54    Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
55  }
56
57  virtual const char *getPassName() const {
58    return "ARM Instruction Selection";
59  }
60
61  /// getI32Imm - Return a target constant of type i32 with the specified
62  /// value.
63  inline SDValue getI32Imm(unsigned Imm) {
64    return CurDAG->getTargetConstant(Imm, MVT::i32);
65  }
66
67  SDNode *Select(SDValue Op);
68  virtual void InstructionSelect();
69  bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
70                               SDValue &B, SDValue &C);
71  bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
72                       SDValue &Offset, SDValue &Opc);
73  bool SelectAddrMode2Offset(SDValue Op, SDValue N,
74                             SDValue &Offset, SDValue &Opc);
75  bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
76                       SDValue &Offset, SDValue &Opc);
77  bool SelectAddrMode3Offset(SDValue Op, SDValue N,
78                             SDValue &Offset, SDValue &Opc);
79  bool SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr,
80                       SDValue &Mode);
81  bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
82                       SDValue &Offset);
83  bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
84                       SDValue &Opc, SDValue &Align);
85
86  bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
87                        SDValue &Label);
88
89  bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
90                             SDValue &Offset);
91  bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
92                              SDValue &Base, SDValue &OffImm,
93                              SDValue &Offset);
94  bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
95                             SDValue &OffImm, SDValue &Offset);
96  bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
97                             SDValue &OffImm, SDValue &Offset);
98  bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
99                             SDValue &OffImm, SDValue &Offset);
100  bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
101                             SDValue &OffImm);
102
103  bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
104                                 SDValue &BaseReg, SDValue &Opc);
105  bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
106                             SDValue &OffImm);
107  bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
108                            SDValue &OffImm);
109  bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
110                                 SDValue &OffImm);
111  bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
112                              SDValue &OffImm);
113  bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
114                             SDValue &OffReg, SDValue &ShImm);
115
116  // Include the pieces autogenerated from the target description.
117#include "ARMGenDAGISel.inc"
118
119private:
120  /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
121  /// ARM.
122  SDNode *SelectARMIndexedLoad(SDValue Op);
123  SDNode *SelectT2IndexedLoad(SDValue Op);
124
125  /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
126  SDNode *SelectDYN_ALLOC(SDValue Op);
127
128  /// SelectVLD - Select NEON load intrinsics.  NumVecs should
129  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
130  /// loads of D registers and even subregs and odd subregs of Q registers.
131  /// For NumVecs == 2, QOpcodes1 is not used.
132  SDNode *SelectVLD(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
133                    unsigned *QOpcodes0, unsigned *QOpcodes1);
134
135  /// SelectVST - Select NEON store intrinsics.  NumVecs should
136  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
137  /// stores of D registers and even subregs and odd subregs of Q registers.
138  /// For NumVecs == 2, QOpcodes1 is not used.
139  SDNode *SelectVST(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
140                    unsigned *QOpcodes0, unsigned *QOpcodes1);
141
142  /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
143  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
144  /// load/store of D registers and even subregs and odd subregs of Q registers.
145  SDNode *SelectVLDSTLane(SDValue Op, bool IsLoad, unsigned NumVecs,
146                          unsigned *DOpcodes, unsigned *QOpcodes0,
147                          unsigned *QOpcodes1);
148
149  /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
150  SDNode *SelectV6T2BitfieldExtractOp(SDValue Op, unsigned Opc);
151
152  /// SelectCMOVOp - Select CMOV instructions for ARM.
153  SDNode *SelectCMOVOp(SDValue Op);
154  SDNode *SelectT2CMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
155                              ARMCC::CondCodes CCVal, SDValue CCR,
156                              SDValue InFlag);
157  SDNode *SelectARMCMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
158                               ARMCC::CondCodes CCVal, SDValue CCR,
159                               SDValue InFlag);
160  SDNode *SelectT2CMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
161                              ARMCC::CondCodes CCVal, SDValue CCR,
162                              SDValue InFlag);
163  SDNode *SelectARMCMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
164                               ARMCC::CondCodes CCVal, SDValue CCR,
165                               SDValue InFlag);
166
167  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
168  /// inline asm expressions.
169  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
170                                            char ConstraintCode,
171                                            std::vector<SDValue> &OutOps);
172
173  /// PairDRegs - Insert a pair of double registers into an implicit def to
174  /// form a quad register.
175  SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
176};
177}
178
179/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
180/// operand. If so Imm will receive the 32-bit value.
181static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
182  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
183    Imm = cast<ConstantSDNode>(N)->getZExtValue();
184    return true;
185  }
186  return false;
187}
188
189// isInt32Immediate - This method tests to see if a constant operand.
190// If so Imm will receive the 32 bit value.
191static bool isInt32Immediate(SDValue N, unsigned &Imm) {
192  return isInt32Immediate(N.getNode(), Imm);
193}
194
195// isOpcWithIntImmediate - This method tests to see if the node is a specific
196// opcode and that it has a immediate integer right operand.
197// If so Imm will receive the 32 bit value.
198static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
199  return N->getOpcode() == Opc &&
200         isInt32Immediate(N->getOperand(1).getNode(), Imm);
201}
202
203
204void ARMDAGToDAGISel::InstructionSelect() {
205  SelectRoot(*CurDAG);
206  CurDAG->RemoveDeadNodes();
207}
208
209bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
210                                              SDValue N,
211                                              SDValue &BaseReg,
212                                              SDValue &ShReg,
213                                              SDValue &Opc) {
214  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
215
216  // Don't match base register only case. That is matched to a separate
217  // lower complexity pattern with explicit register operand.
218  if (ShOpcVal == ARM_AM::no_shift) return false;
219
220  BaseReg = N.getOperand(0);
221  unsigned ShImmVal = 0;
222  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
223    ShReg = CurDAG->getRegister(0, MVT::i32);
224    ShImmVal = RHS->getZExtValue() & 31;
225  } else {
226    ShReg = N.getOperand(1);
227  }
228  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
229                                  MVT::i32);
230  return true;
231}
232
233bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
234                                      SDValue &Base, SDValue &Offset,
235                                      SDValue &Opc) {
236  if (N.getOpcode() == ISD::MUL) {
237    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
238      // X * [3,5,9] -> X + X * [2,4,8] etc.
239      int RHSC = (int)RHS->getZExtValue();
240      if (RHSC & 1) {
241        RHSC = RHSC & ~1;
242        ARM_AM::AddrOpc AddSub = ARM_AM::add;
243        if (RHSC < 0) {
244          AddSub = ARM_AM::sub;
245          RHSC = - RHSC;
246        }
247        if (isPowerOf2_32(RHSC)) {
248          unsigned ShAmt = Log2_32(RHSC);
249          Base = Offset = N.getOperand(0);
250          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
251                                                            ARM_AM::lsl),
252                                          MVT::i32);
253          return true;
254        }
255      }
256    }
257  }
258
259  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
260    Base = N;
261    if (N.getOpcode() == ISD::FrameIndex) {
262      int FI = cast<FrameIndexSDNode>(N)->getIndex();
263      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
264    } else if (N.getOpcode() == ARMISD::Wrapper &&
265               !(Subtarget->useMovt() &&
266                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
267      Base = N.getOperand(0);
268    }
269    Offset = CurDAG->getRegister(0, MVT::i32);
270    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
271                                                      ARM_AM::no_shift),
272                                    MVT::i32);
273    return true;
274  }
275
276  // Match simple R +/- imm12 operands.
277  if (N.getOpcode() == ISD::ADD)
278    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
279      int RHSC = (int)RHS->getZExtValue();
280      if ((RHSC >= 0 && RHSC < 0x1000) ||
281          (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
282        Base = N.getOperand(0);
283        if (Base.getOpcode() == ISD::FrameIndex) {
284          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
285          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
286        }
287        Offset = CurDAG->getRegister(0, MVT::i32);
288
289        ARM_AM::AddrOpc AddSub = ARM_AM::add;
290        if (RHSC < 0) {
291          AddSub = ARM_AM::sub;
292          RHSC = - RHSC;
293        }
294        Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
295                                                          ARM_AM::no_shift),
296                                        MVT::i32);
297        return true;
298      }
299    }
300
301  // Otherwise this is R +/- [possibly shifted] R.
302  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
303  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
304  unsigned ShAmt = 0;
305
306  Base   = N.getOperand(0);
307  Offset = N.getOperand(1);
308
309  if (ShOpcVal != ARM_AM::no_shift) {
310    // Check to see if the RHS of the shift is a constant, if not, we can't fold
311    // it.
312    if (ConstantSDNode *Sh =
313           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
314      ShAmt = Sh->getZExtValue();
315      Offset = N.getOperand(1).getOperand(0);
316    } else {
317      ShOpcVal = ARM_AM::no_shift;
318    }
319  }
320
321  // Try matching (R shl C) + (R).
322  if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
323    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
324    if (ShOpcVal != ARM_AM::no_shift) {
325      // Check to see if the RHS of the shift is a constant, if not, we can't
326      // fold it.
327      if (ConstantSDNode *Sh =
328          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
329        ShAmt = Sh->getZExtValue();
330        Offset = N.getOperand(0).getOperand(0);
331        Base = N.getOperand(1);
332      } else {
333        ShOpcVal = ARM_AM::no_shift;
334      }
335    }
336  }
337
338  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
339                                  MVT::i32);
340  return true;
341}
342
343bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
344                                            SDValue &Offset, SDValue &Opc) {
345  unsigned Opcode = Op.getOpcode();
346  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
347    ? cast<LoadSDNode>(Op)->getAddressingMode()
348    : cast<StoreSDNode>(Op)->getAddressingMode();
349  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
350    ? ARM_AM::add : ARM_AM::sub;
351  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
352    int Val = (int)C->getZExtValue();
353    if (Val >= 0 && Val < 0x1000) { // 12 bits.
354      Offset = CurDAG->getRegister(0, MVT::i32);
355      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
356                                                        ARM_AM::no_shift),
357                                      MVT::i32);
358      return true;
359    }
360  }
361
362  Offset = N;
363  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
364  unsigned ShAmt = 0;
365  if (ShOpcVal != ARM_AM::no_shift) {
366    // Check to see if the RHS of the shift is a constant, if not, we can't fold
367    // it.
368    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
369      ShAmt = Sh->getZExtValue();
370      Offset = N.getOperand(0);
371    } else {
372      ShOpcVal = ARM_AM::no_shift;
373    }
374  }
375
376  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
377                                  MVT::i32);
378  return true;
379}
380
381
382bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
383                                      SDValue &Base, SDValue &Offset,
384                                      SDValue &Opc) {
385  if (N.getOpcode() == ISD::SUB) {
386    // X - C  is canonicalize to X + -C, no need to handle it here.
387    Base = N.getOperand(0);
388    Offset = N.getOperand(1);
389    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
390    return true;
391  }
392
393  if (N.getOpcode() != ISD::ADD) {
394    Base = N;
395    if (N.getOpcode() == ISD::FrameIndex) {
396      int FI = cast<FrameIndexSDNode>(N)->getIndex();
397      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
398    }
399    Offset = CurDAG->getRegister(0, MVT::i32);
400    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
401    return true;
402  }
403
404  // If the RHS is +/- imm8, fold into addr mode.
405  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
406    int RHSC = (int)RHS->getZExtValue();
407    if ((RHSC >= 0 && RHSC < 256) ||
408        (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
409      Base = N.getOperand(0);
410      if (Base.getOpcode() == ISD::FrameIndex) {
411        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
412        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
413      }
414      Offset = CurDAG->getRegister(0, MVT::i32);
415
416      ARM_AM::AddrOpc AddSub = ARM_AM::add;
417      if (RHSC < 0) {
418        AddSub = ARM_AM::sub;
419        RHSC = - RHSC;
420      }
421      Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
422      return true;
423    }
424  }
425
426  Base = N.getOperand(0);
427  Offset = N.getOperand(1);
428  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
429  return true;
430}
431
432bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
433                                            SDValue &Offset, SDValue &Opc) {
434  unsigned Opcode = Op.getOpcode();
435  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
436    ? cast<LoadSDNode>(Op)->getAddressingMode()
437    : cast<StoreSDNode>(Op)->getAddressingMode();
438  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
439    ? ARM_AM::add : ARM_AM::sub;
440  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
441    int Val = (int)C->getZExtValue();
442    if (Val >= 0 && Val < 256) {
443      Offset = CurDAG->getRegister(0, MVT::i32);
444      Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
445      return true;
446    }
447  }
448
449  Offset = N;
450  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
451  return true;
452}
453
454bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
455                                      SDValue &Addr, SDValue &Mode) {
456  Addr = N;
457  Mode = CurDAG->getTargetConstant(0, MVT::i32);
458  return true;
459}
460
461bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
462                                      SDValue &Base, SDValue &Offset) {
463  if (N.getOpcode() != ISD::ADD) {
464    Base = N;
465    if (N.getOpcode() == ISD::FrameIndex) {
466      int FI = cast<FrameIndexSDNode>(N)->getIndex();
467      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
468    } else if (N.getOpcode() == ARMISD::Wrapper &&
469               !(Subtarget->useMovt() &&
470                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
471      Base = N.getOperand(0);
472    }
473    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
474                                       MVT::i32);
475    return true;
476  }
477
478  // If the RHS is +/- imm8, fold into addr mode.
479  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
480    int RHSC = (int)RHS->getZExtValue();
481    if ((RHSC & 3) == 0) {  // The constant is implicitly multiplied by 4.
482      RHSC >>= 2;
483      if ((RHSC >= 0 && RHSC < 256) ||
484          (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
485        Base = N.getOperand(0);
486        if (Base.getOpcode() == ISD::FrameIndex) {
487          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
488          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
489        }
490
491        ARM_AM::AddrOpc AddSub = ARM_AM::add;
492        if (RHSC < 0) {
493          AddSub = ARM_AM::sub;
494          RHSC = - RHSC;
495        }
496        Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
497                                           MVT::i32);
498        return true;
499      }
500    }
501  }
502
503  Base = N;
504  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
505                                     MVT::i32);
506  return true;
507}
508
509bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
510                                      SDValue &Addr, SDValue &Update,
511                                      SDValue &Opc, SDValue &Align) {
512  Addr = N;
513  // Default to no writeback.
514  Update = CurDAG->getRegister(0, MVT::i32);
515  Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
516  // Default to no alignment.
517  Align = CurDAG->getTargetConstant(0, MVT::i32);
518  return true;
519}
520
521bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
522                                       SDValue &Offset, SDValue &Label) {
523  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
524    Offset = N.getOperand(0);
525    SDValue N1 = N.getOperand(1);
526    Label  = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
527                                       MVT::i32);
528    return true;
529  }
530  return false;
531}
532
533bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
534                                            SDValue &Base, SDValue &Offset){
535  // FIXME dl should come from the parent load or store, not the address
536  DebugLoc dl = Op.getDebugLoc();
537  if (N.getOpcode() != ISD::ADD) {
538    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
539    if (!NC || NC->getZExtValue() != 0)
540      return false;
541
542    Base = Offset = N;
543    return true;
544  }
545
546  Base = N.getOperand(0);
547  Offset = N.getOperand(1);
548  return true;
549}
550
551bool
552ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
553                                        unsigned Scale, SDValue &Base,
554                                        SDValue &OffImm, SDValue &Offset) {
555  if (Scale == 4) {
556    SDValue TmpBase, TmpOffImm;
557    if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
558      return false;  // We want to select tLDRspi / tSTRspi instead.
559    if (N.getOpcode() == ARMISD::Wrapper &&
560        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
561      return false;  // We want to select tLDRpci instead.
562  }
563
564  if (N.getOpcode() != ISD::ADD) {
565    if (N.getOpcode() == ARMISD::Wrapper &&
566        !(Subtarget->useMovt() &&
567          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
568      Base = N.getOperand(0);
569    } else
570      Base = N;
571
572    Offset = CurDAG->getRegister(0, MVT::i32);
573    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
574    return true;
575  }
576
577  // Thumb does not have [sp, r] address mode.
578  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
579  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
580  if ((LHSR && LHSR->getReg() == ARM::SP) ||
581      (RHSR && RHSR->getReg() == ARM::SP)) {
582    Base = N;
583    Offset = CurDAG->getRegister(0, MVT::i32);
584    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
585    return true;
586  }
587
588  // If the RHS is + imm5 * scale, fold into addr mode.
589  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
590    int RHSC = (int)RHS->getZExtValue();
591    if ((RHSC & (Scale-1)) == 0) {  // The constant is implicitly multiplied.
592      RHSC /= Scale;
593      if (RHSC >= 0 && RHSC < 32) {
594        Base = N.getOperand(0);
595        Offset = CurDAG->getRegister(0, MVT::i32);
596        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
597        return true;
598      }
599    }
600  }
601
602  Base = N.getOperand(0);
603  Offset = N.getOperand(1);
604  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
605  return true;
606}
607
608bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
609                                            SDValue &Base, SDValue &OffImm,
610                                            SDValue &Offset) {
611  return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
612}
613
614bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
615                                            SDValue &Base, SDValue &OffImm,
616                                            SDValue &Offset) {
617  return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
618}
619
620bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
621                                            SDValue &Base, SDValue &OffImm,
622                                            SDValue &Offset) {
623  return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
624}
625
626bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
627                                           SDValue &Base, SDValue &OffImm) {
628  if (N.getOpcode() == ISD::FrameIndex) {
629    int FI = cast<FrameIndexSDNode>(N)->getIndex();
630    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
631    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
632    return true;
633  }
634
635  if (N.getOpcode() != ISD::ADD)
636    return false;
637
638  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
639  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
640      (LHSR && LHSR->getReg() == ARM::SP)) {
641    // If the RHS is + imm8 * scale, fold into addr mode.
642    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
643      int RHSC = (int)RHS->getZExtValue();
644      if ((RHSC & 3) == 0) {  // The constant is implicitly multiplied.
645        RHSC >>= 2;
646        if (RHSC >= 0 && RHSC < 256) {
647          Base = N.getOperand(0);
648          if (Base.getOpcode() == ISD::FrameIndex) {
649            int FI = cast<FrameIndexSDNode>(Base)->getIndex();
650            Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
651          }
652          OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
653          return true;
654        }
655      }
656    }
657  }
658
659  return false;
660}
661
662bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
663                                                SDValue &BaseReg,
664                                                SDValue &Opc) {
665  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
666
667  // Don't match base register only case. That is matched to a separate
668  // lower complexity pattern with explicit register operand.
669  if (ShOpcVal == ARM_AM::no_shift) return false;
670
671  BaseReg = N.getOperand(0);
672  unsigned ShImmVal = 0;
673  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
674    ShImmVal = RHS->getZExtValue() & 31;
675    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
676    return true;
677  }
678
679  return false;
680}
681
682bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
683                                            SDValue &Base, SDValue &OffImm) {
684  // Match simple R + imm12 operands.
685
686  // Base only.
687  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
688    if (N.getOpcode() == ISD::FrameIndex) {
689      // Match frame index...
690      int FI = cast<FrameIndexSDNode>(N)->getIndex();
691      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
692      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
693      return true;
694    } else if (N.getOpcode() == ARMISD::Wrapper &&
695               !(Subtarget->useMovt() &&
696                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
697      Base = N.getOperand(0);
698      if (Base.getOpcode() == ISD::TargetConstantPool)
699        return false;  // We want to select t2LDRpci instead.
700    } else
701      Base = N;
702    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
703    return true;
704  }
705
706  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
707    if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
708      // Let t2LDRi8 handle (R - imm8).
709      return false;
710
711    int RHSC = (int)RHS->getZExtValue();
712    if (N.getOpcode() == ISD::SUB)
713      RHSC = -RHSC;
714
715    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
716      Base   = N.getOperand(0);
717      if (Base.getOpcode() == ISD::FrameIndex) {
718        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
719        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
720      }
721      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
722      return true;
723    }
724  }
725
726  // Base only.
727  Base = N;
728  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
729  return true;
730}
731
732bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
733                                           SDValue &Base, SDValue &OffImm) {
734  // Match simple R - imm8 operands.
735  if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
736    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
737      int RHSC = (int)RHS->getSExtValue();
738      if (N.getOpcode() == ISD::SUB)
739        RHSC = -RHSC;
740
741      if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
742        Base = N.getOperand(0);
743        if (Base.getOpcode() == ISD::FrameIndex) {
744          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
745          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
746        }
747        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
748        return true;
749      }
750    }
751  }
752
753  return false;
754}
755
756bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
757                                                 SDValue &OffImm){
758  unsigned Opcode = Op.getOpcode();
759  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
760    ? cast<LoadSDNode>(Op)->getAddressingMode()
761    : cast<StoreSDNode>(Op)->getAddressingMode();
762  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
763    int RHSC = (int)RHS->getZExtValue();
764    if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
765      OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
766        ? CurDAG->getTargetConstant(RHSC, MVT::i32)
767        : CurDAG->getTargetConstant(-RHSC, MVT::i32);
768      return true;
769    }
770  }
771
772  return false;
773}
774
775bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
776                                             SDValue &Base, SDValue &OffImm) {
777  if (N.getOpcode() == ISD::ADD) {
778    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
779      int RHSC = (int)RHS->getZExtValue();
780      if (((RHSC & 0x3) == 0) &&
781          ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
782        Base   = N.getOperand(0);
783        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
784        return true;
785      }
786    }
787  } else if (N.getOpcode() == ISD::SUB) {
788    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
789      int RHSC = (int)RHS->getZExtValue();
790      if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
791        Base   = N.getOperand(0);
792        OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
793        return true;
794      }
795    }
796  }
797
798  return false;
799}
800
801bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
802                                            SDValue &Base,
803                                            SDValue &OffReg, SDValue &ShImm) {
804  // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
805  if (N.getOpcode() != ISD::ADD)
806    return false;
807
808  // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
809  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
810    int RHSC = (int)RHS->getZExtValue();
811    if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
812      return false;
813    else if (RHSC < 0 && RHSC >= -255) // 8 bits
814      return false;
815  }
816
817  // Look for (R + R) or (R + (R << [1,2,3])).
818  unsigned ShAmt = 0;
819  Base   = N.getOperand(0);
820  OffReg = N.getOperand(1);
821
822  // Swap if it is ((R << c) + R).
823  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
824  if (ShOpcVal != ARM_AM::lsl) {
825    ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
826    if (ShOpcVal == ARM_AM::lsl)
827      std::swap(Base, OffReg);
828  }
829
830  if (ShOpcVal == ARM_AM::lsl) {
831    // Check to see if the RHS of the shift is a constant, if not, we can't fold
832    // it.
833    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
834      ShAmt = Sh->getZExtValue();
835      if (ShAmt >= 4) {
836        ShAmt = 0;
837        ShOpcVal = ARM_AM::no_shift;
838      } else
839        OffReg = OffReg.getOperand(0);
840    } else {
841      ShOpcVal = ARM_AM::no_shift;
842    }
843  }
844
845  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
846
847  return true;
848}
849
850//===--------------------------------------------------------------------===//
851
852/// getAL - Returns a ARMCC::AL immediate node.
853static inline SDValue getAL(SelectionDAG *CurDAG) {
854  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
855}
856
857SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
858  LoadSDNode *LD = cast<LoadSDNode>(Op);
859  ISD::MemIndexedMode AM = LD->getAddressingMode();
860  if (AM == ISD::UNINDEXED)
861    return NULL;
862
863  EVT LoadedVT = LD->getMemoryVT();
864  SDValue Offset, AMOpc;
865  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
866  unsigned Opcode = 0;
867  bool Match = false;
868  if (LoadedVT == MVT::i32 &&
869      SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
870    Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
871    Match = true;
872  } else if (LoadedVT == MVT::i16 &&
873             SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
874    Match = true;
875    Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
876      ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
877      : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
878  } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
879    if (LD->getExtensionType() == ISD::SEXTLOAD) {
880      if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
881        Match = true;
882        Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
883      }
884    } else {
885      if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
886        Match = true;
887        Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
888      }
889    }
890  }
891
892  if (Match) {
893    SDValue Chain = LD->getChain();
894    SDValue Base = LD->getBasePtr();
895    SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
896                     CurDAG->getRegister(0, MVT::i32), Chain };
897    return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
898                                  MVT::Other, Ops, 6);
899  }
900
901  return NULL;
902}
903
904SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
905  LoadSDNode *LD = cast<LoadSDNode>(Op);
906  ISD::MemIndexedMode AM = LD->getAddressingMode();
907  if (AM == ISD::UNINDEXED)
908    return NULL;
909
910  EVT LoadedVT = LD->getMemoryVT();
911  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
912  SDValue Offset;
913  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
914  unsigned Opcode = 0;
915  bool Match = false;
916  if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
917    switch (LoadedVT.getSimpleVT().SimpleTy) {
918    case MVT::i32:
919      Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
920      break;
921    case MVT::i16:
922      if (isSExtLd)
923        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
924      else
925        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
926      break;
927    case MVT::i8:
928    case MVT::i1:
929      if (isSExtLd)
930        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
931      else
932        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
933      break;
934    default:
935      return NULL;
936    }
937    Match = true;
938  }
939
940  if (Match) {
941    SDValue Chain = LD->getChain();
942    SDValue Base = LD->getBasePtr();
943    SDValue Ops[]= { Base, Offset, getAL(CurDAG),
944                     CurDAG->getRegister(0, MVT::i32), Chain };
945    return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
946                                  MVT::Other, Ops, 5);
947  }
948
949  return NULL;
950}
951
952SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
953  SDNode *N = Op.getNode();
954  DebugLoc dl = N->getDebugLoc();
955  EVT VT = Op.getValueType();
956  SDValue Chain = Op.getOperand(0);
957  SDValue Size = Op.getOperand(1);
958  SDValue Align = Op.getOperand(2);
959  SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
960  int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
961  if (AlignVal < 0)
962    // We need to align the stack. Use Thumb1 tAND which is the only thumb
963    // instruction that can read and write SP. This matches to a pseudo
964    // instruction that has a chain to ensure the result is written back to
965    // the stack pointer.
966    SP = SDValue(CurDAG->getMachineNode(ARM::tANDsp, dl, VT, SP, Align), 0);
967
968  bool isC = isa<ConstantSDNode>(Size);
969  uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
970  // Handle the most common case for both Thumb1 and Thumb2:
971  // tSUBspi - immediate is between 0 ... 508 inclusive.
972  if (C <= 508 && ((C & 3) == 0))
973    // FIXME: tSUBspi encode scale 4 implicitly.
974    return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
975                                CurDAG->getTargetConstant(C/4, MVT::i32),
976                                Chain);
977
978  if (Subtarget->isThumb1Only()) {
979    // Use tADDspr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
980    // should have negated the size operand already. FIXME: We can't insert
981    // new target independent node at this stage so we are forced to negate
982    // it earlier. Is there a better solution?
983    return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
984                                Chain);
985  } else if (Subtarget->isThumb2()) {
986    if (isC && Predicate_t2_so_imm(Size.getNode())) {
987      // t2SUBrSPi
988      SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
989      return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
990    } else if (isC && Predicate_imm0_4095(Size.getNode())) {
991      // t2SUBrSPi12
992      SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
993      return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
994    } else {
995      // t2SUBrSPs
996      SDValue Ops[] = { SP, Size,
997                        getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
998      return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
999    }
1000  }
1001
1002  // FIXME: Add ADD / SUB sp instructions for ARM.
1003  return 0;
1004}
1005
1006/// PairDRegs - Insert a pair of double registers into an implicit def to
1007/// form a quad register.
1008SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1009  DebugLoc dl = V0.getNode()->getDebugLoc();
1010  SDValue Undef =
1011    SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT), 0);
1012  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
1013  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
1014  SDNode *Pair = CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
1015                                        VT, Undef, V0, SubReg0);
1016  return CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
1017                                VT, SDValue(Pair, 0), V1, SubReg1);
1018}
1019
1020/// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type
1021/// for a 64-bit subregister of the vector.
1022static EVT GetNEONSubregVT(EVT VT) {
1023  switch (VT.getSimpleVT().SimpleTy) {
1024  default: llvm_unreachable("unhandled NEON type");
1025  case MVT::v16i8: return MVT::v8i8;
1026  case MVT::v8i16: return MVT::v4i16;
1027  case MVT::v4f32: return MVT::v2f32;
1028  case MVT::v4i32: return MVT::v2i32;
1029  case MVT::v2i64: return MVT::v1i64;
1030  }
1031}
1032
1033SDNode *ARMDAGToDAGISel::SelectVLD(SDValue Op, unsigned NumVecs,
1034                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1035                                   unsigned *QOpcodes1) {
1036  assert(NumVecs >=2 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1037  SDNode *N = Op.getNode();
1038  DebugLoc dl = N->getDebugLoc();
1039
1040  SDValue MemAddr, MemUpdate, MemOpc, Align;
1041  if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1042    return NULL;
1043
1044  SDValue Chain = N->getOperand(0);
1045  EVT VT = N->getValueType(0);
1046  bool is64BitVector = VT.is64BitVector();
1047
1048  unsigned OpcodeIndex;
1049  switch (VT.getSimpleVT().SimpleTy) {
1050  default: llvm_unreachable("unhandled vld type");
1051    // Double-register operations:
1052  case MVT::v8i8:  OpcodeIndex = 0; break;
1053  case MVT::v4i16: OpcodeIndex = 1; break;
1054  case MVT::v2f32:
1055  case MVT::v2i32: OpcodeIndex = 2; break;
1056  case MVT::v1i64: OpcodeIndex = 3; break;
1057    // Quad-register operations:
1058  case MVT::v16i8: OpcodeIndex = 0; break;
1059  case MVT::v8i16: OpcodeIndex = 1; break;
1060  case MVT::v4f32:
1061  case MVT::v4i32: OpcodeIndex = 2; break;
1062  }
1063
1064  SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1065  SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1066  if (is64BitVector) {
1067    unsigned Opc = DOpcodes[OpcodeIndex];
1068    const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align,
1069                            Pred, PredReg, Chain };
1070    std::vector<EVT> ResTys(NumVecs, VT);
1071    ResTys.push_back(MVT::Other);
1072    return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 7);
1073  }
1074
1075  EVT RegVT = GetNEONSubregVT(VT);
1076  if (NumVecs == 2) {
1077    // Quad registers are directly supported for VLD2,
1078    // loading 2 pairs of D regs.
1079    unsigned Opc = QOpcodes0[OpcodeIndex];
1080    const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align,
1081                            Pred, PredReg, Chain };
1082    std::vector<EVT> ResTys(4, VT);
1083    ResTys.push_back(MVT::Other);
1084    SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 7);
1085    Chain = SDValue(VLd, 4);
1086
1087    // Combine the even and odd subregs to produce the result.
1088    for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1089      SDNode *Q = PairDRegs(VT, SDValue(VLd, 2*Vec), SDValue(VLd, 2*Vec+1));
1090      ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1091    }
1092  } else {
1093    // Otherwise, quad registers are loaded with two separate instructions,
1094    // where one loads the even registers and the other loads the odd registers.
1095
1096    // Enable writeback to the address register.
1097    MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1098
1099    std::vector<EVT> ResTys(NumVecs, RegVT);
1100    ResTys.push_back(MemAddr.getValueType());
1101    ResTys.push_back(MVT::Other);
1102
1103    // Load the even subregs.
1104    unsigned Opc = QOpcodes0[OpcodeIndex];
1105    const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Align,
1106                             Pred, PredReg, Chain };
1107    SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 7);
1108    Chain = SDValue(VLdA, NumVecs+1);
1109
1110    // Load the odd subregs.
1111    Opc = QOpcodes1[OpcodeIndex];
1112    const SDValue OpsB[] = { SDValue(VLdA, NumVecs), MemUpdate, MemOpc,
1113                             Align, Pred, PredReg, Chain };
1114    SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 7);
1115    Chain = SDValue(VLdB, NumVecs+1);
1116
1117    // Combine the even and odd subregs to produce the result.
1118    for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1119      SDNode *Q = PairDRegs(VT, SDValue(VLdA, Vec), SDValue(VLdB, Vec));
1120      ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1121    }
1122  }
1123  ReplaceUses(SDValue(N, NumVecs), Chain);
1124  return NULL;
1125}
1126
1127SDNode *ARMDAGToDAGISel::SelectVST(SDValue Op, unsigned NumVecs,
1128                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1129                                   unsigned *QOpcodes1) {
1130  assert(NumVecs >=2 && NumVecs <= 4 && "VST NumVecs out-of-range");
1131  SDNode *N = Op.getNode();
1132  DebugLoc dl = N->getDebugLoc();
1133
1134  SDValue MemAddr, MemUpdate, MemOpc, Align;
1135  if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1136    return NULL;
1137
1138  SDValue Chain = N->getOperand(0);
1139  EVT VT = N->getOperand(3).getValueType();
1140  bool is64BitVector = VT.is64BitVector();
1141
1142  unsigned OpcodeIndex;
1143  switch (VT.getSimpleVT().SimpleTy) {
1144  default: llvm_unreachable("unhandled vst type");
1145    // Double-register operations:
1146  case MVT::v8i8:  OpcodeIndex = 0; break;
1147  case MVT::v4i16: OpcodeIndex = 1; break;
1148  case MVT::v2f32:
1149  case MVT::v2i32: OpcodeIndex = 2; break;
1150  case MVT::v1i64: OpcodeIndex = 3; break;
1151    // Quad-register operations:
1152  case MVT::v16i8: OpcodeIndex = 0; break;
1153  case MVT::v8i16: OpcodeIndex = 1; break;
1154  case MVT::v4f32:
1155  case MVT::v4i32: OpcodeIndex = 2; break;
1156  }
1157
1158  SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1159  SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1160
1161  SmallVector<SDValue, 8> Ops;
1162  Ops.push_back(MemAddr);
1163  Ops.push_back(MemUpdate);
1164  Ops.push_back(MemOpc);
1165  Ops.push_back(Align);
1166
1167  if (is64BitVector) {
1168    unsigned Opc = DOpcodes[OpcodeIndex];
1169    for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1170      Ops.push_back(N->getOperand(Vec+3));
1171    Ops.push_back(Pred);
1172    Ops.push_back(PredReg);
1173    Ops.push_back(Chain);
1174    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+7);
1175  }
1176
1177  EVT RegVT = GetNEONSubregVT(VT);
1178  if (NumVecs == 2) {
1179    // Quad registers are directly supported for VST2,
1180    // storing 2 pairs of D regs.
1181    unsigned Opc = QOpcodes0[OpcodeIndex];
1182    for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1183      Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1184                                                   N->getOperand(Vec+3)));
1185      Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1186                                                   N->getOperand(Vec+3)));
1187    }
1188    Ops.push_back(Pred);
1189    Ops.push_back(PredReg);
1190    Ops.push_back(Chain);
1191    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 11);
1192  }
1193
1194  // Otherwise, quad registers are stored with two separate instructions,
1195  // where one stores the even registers and the other stores the odd registers.
1196
1197  // Enable writeback to the address register.
1198  MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1199
1200  // Store the even subregs.
1201  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1202    Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1203                                                 N->getOperand(Vec+3)));
1204  Ops.push_back(Pred);
1205  Ops.push_back(PredReg);
1206  Ops.push_back(Chain);
1207  unsigned Opc = QOpcodes0[OpcodeIndex];
1208  SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1209                                        MVT::Other, Ops.data(), NumVecs+7);
1210  Chain = SDValue(VStA, 1);
1211
1212  // Store the odd subregs.
1213  Ops[0] = SDValue(VStA, 0); // MemAddr
1214  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1215    Ops[Vec+4] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1216                                                N->getOperand(Vec+3));
1217  Ops[NumVecs+4] = Pred;
1218  Ops[NumVecs+5] = PredReg;
1219  Ops[NumVecs+6] = Chain;
1220  Opc = QOpcodes1[OpcodeIndex];
1221  SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1222                                        MVT::Other, Ops.data(), NumVecs+7);
1223  Chain = SDValue(VStB, 1);
1224  ReplaceUses(SDValue(N, 0), Chain);
1225  return NULL;
1226}
1227
1228SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDValue Op, bool IsLoad,
1229                                         unsigned NumVecs, unsigned *DOpcodes,
1230                                         unsigned *QOpcodes0,
1231                                         unsigned *QOpcodes1) {
1232  assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1233  SDNode *N = Op.getNode();
1234  DebugLoc dl = N->getDebugLoc();
1235
1236  SDValue MemAddr, MemUpdate, MemOpc, Align;
1237  if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1238    return NULL;
1239
1240  SDValue Chain = N->getOperand(0);
1241  unsigned Lane =
1242    cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1243  EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1244  bool is64BitVector = VT.is64BitVector();
1245
1246  // Quad registers are handled by load/store of subregs. Find the subreg info.
1247  unsigned NumElts = 0;
1248  int SubregIdx = 0;
1249  EVT RegVT = VT;
1250  if (!is64BitVector) {
1251    RegVT = GetNEONSubregVT(VT);
1252    NumElts = RegVT.getVectorNumElements();
1253    SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1254  }
1255
1256  unsigned OpcodeIndex;
1257  switch (VT.getSimpleVT().SimpleTy) {
1258  default: llvm_unreachable("unhandled vld/vst lane type");
1259    // Double-register operations:
1260  case MVT::v8i8:  OpcodeIndex = 0; break;
1261  case MVT::v4i16: OpcodeIndex = 1; break;
1262  case MVT::v2f32:
1263  case MVT::v2i32: OpcodeIndex = 2; break;
1264    // Quad-register operations:
1265  case MVT::v8i16: OpcodeIndex = 0; break;
1266  case MVT::v4f32:
1267  case MVT::v4i32: OpcodeIndex = 1; break;
1268  }
1269
1270  SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1271  SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1272
1273  SmallVector<SDValue, 9> Ops;
1274  Ops.push_back(MemAddr);
1275  Ops.push_back(MemUpdate);
1276  Ops.push_back(MemOpc);
1277  Ops.push_back(Align);
1278
1279  unsigned Opc = 0;
1280  if (is64BitVector) {
1281    Opc = DOpcodes[OpcodeIndex];
1282    for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1283      Ops.push_back(N->getOperand(Vec+3));
1284  } else {
1285    // Check if this is loading the even or odd subreg of a Q register.
1286    if (Lane < NumElts) {
1287      Opc = QOpcodes0[OpcodeIndex];
1288    } else {
1289      Lane -= NumElts;
1290      Opc = QOpcodes1[OpcodeIndex];
1291    }
1292    // Extract the subregs of the input vector.
1293    for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1294      Ops.push_back(CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1295                                                   N->getOperand(Vec+3)));
1296  }
1297  Ops.push_back(getI32Imm(Lane));
1298  Ops.push_back(Pred);
1299  Ops.push_back(PredReg);
1300  Ops.push_back(Chain);
1301
1302  if (!IsLoad)
1303    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+7);
1304
1305  std::vector<EVT> ResTys(NumVecs, RegVT);
1306  ResTys.push_back(MVT::Other);
1307  SDNode *VLdLn =
1308    CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+7);
1309  // For a 64-bit vector load to D registers, nothing more needs to be done.
1310  if (is64BitVector)
1311    return VLdLn;
1312
1313  // For 128-bit vectors, take the 64-bit results of the load and insert them
1314  // as subregs into the result.
1315  for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1316    SDValue QuadVec = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1317                                                    N->getOperand(Vec+3),
1318                                                    SDValue(VLdLn, Vec));
1319    ReplaceUses(SDValue(N, Vec), QuadVec);
1320  }
1321
1322  Chain = SDValue(VLdLn, NumVecs);
1323  ReplaceUses(SDValue(N, NumVecs), Chain);
1324  return NULL;
1325}
1326
1327SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDValue Op,
1328                                                     unsigned Opc) {
1329  if (!Subtarget->hasV6T2Ops())
1330    return NULL;
1331
1332  unsigned Shl_imm = 0;
1333  if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1334    assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1335    unsigned Srl_imm = 0;
1336    if (isInt32Immediate(Op.getOperand(1), Srl_imm)) {
1337      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1338      unsigned Width = 32 - Srl_imm;
1339      int LSB = Srl_imm - Shl_imm;
1340      if (LSB < 0)
1341        return NULL;
1342      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1343      SDValue Ops[] = { Op.getOperand(0).getOperand(0),
1344                        CurDAG->getTargetConstant(LSB, MVT::i32),
1345                        CurDAG->getTargetConstant(Width, MVT::i32),
1346                        getAL(CurDAG), Reg0 };
1347      return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32, Ops, 5);
1348    }
1349  }
1350  return NULL;
1351}
1352
1353SDNode *ARMDAGToDAGISel::
1354SelectT2CMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
1355                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1356  SDValue CPTmp0;
1357  SDValue CPTmp1;
1358  if (SelectT2ShifterOperandReg(Op, TrueVal, CPTmp0, CPTmp1)) {
1359    unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1360    unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1361    unsigned Opc = 0;
1362    switch (SOShOp) {
1363    case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1364    case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1365    case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1366    case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1367    default:
1368      llvm_unreachable("Unknown so_reg opcode!");
1369      break;
1370    }
1371    SDValue SOShImm =
1372      CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1373    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1374    SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1375    return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
1376  }
1377  return 0;
1378}
1379
1380SDNode *ARMDAGToDAGISel::
1381SelectARMCMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
1382                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1383  SDValue CPTmp0;
1384  SDValue CPTmp1;
1385  SDValue CPTmp2;
1386  if (SelectShifterOperandReg(Op, TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1387    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1388    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1389    return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
1390  }
1391  return 0;
1392}
1393
1394SDNode *ARMDAGToDAGISel::
1395SelectT2CMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
1396                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1397  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1398  if (!T)
1399    return 0;
1400
1401  if (Predicate_t2_so_imm(TrueVal.getNode())) {
1402    SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1403    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1404    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1405    return CurDAG->SelectNodeTo(Op.getNode(),
1406                                ARM::t2MOVCCi, MVT::i32, Ops, 5);
1407  }
1408  return 0;
1409}
1410
1411SDNode *ARMDAGToDAGISel::
1412SelectARMCMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
1413                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1414  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1415  if (!T)
1416    return 0;
1417
1418  if (Predicate_so_imm(TrueVal.getNode())) {
1419    SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1420    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1421    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1422    return CurDAG->SelectNodeTo(Op.getNode(),
1423                                ARM::MOVCCi, MVT::i32, Ops, 5);
1424  }
1425  return 0;
1426}
1427
1428SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) {
1429  EVT VT = Op.getValueType();
1430  SDValue FalseVal = Op.getOperand(0);
1431  SDValue TrueVal  = Op.getOperand(1);
1432  SDValue CC = Op.getOperand(2);
1433  SDValue CCR = Op.getOperand(3);
1434  SDValue InFlag = Op.getOperand(4);
1435  assert(CC.getOpcode() == ISD::Constant);
1436  assert(CCR.getOpcode() == ISD::Register);
1437  ARMCC::CondCodes CCVal =
1438    (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1439
1440  if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1441    // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1442    // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1443    // Pattern complexity = 18  cost = 1  size = 0
1444    SDValue CPTmp0;
1445    SDValue CPTmp1;
1446    SDValue CPTmp2;
1447    if (Subtarget->isThumb()) {
1448      SDNode *Res = SelectT2CMOVShiftOp(Op, FalseVal, TrueVal,
1449                                        CCVal, CCR, InFlag);
1450      if (!Res)
1451        Res = SelectT2CMOVShiftOp(Op, TrueVal, FalseVal,
1452                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1453      if (Res)
1454        return Res;
1455    } else {
1456      SDNode *Res = SelectARMCMOVShiftOp(Op, FalseVal, TrueVal,
1457                                         CCVal, CCR, InFlag);
1458      if (!Res)
1459        Res = SelectARMCMOVShiftOp(Op, TrueVal, FalseVal,
1460                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1461      if (Res)
1462        return Res;
1463    }
1464
1465    // Pattern: (ARMcmov:i32 GPR:i32:$false,
1466    //             (imm:i32)<<P:Predicate_so_imm>>:$true,
1467    //             (imm:i32):$cc)
1468    // Emits: (MOVCCi:i32 GPR:i32:$false,
1469    //           (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1470    // Pattern complexity = 10  cost = 1  size = 0
1471    if (Subtarget->isThumb()) {
1472      SDNode *Res = SelectT2CMOVSoImmOp(Op, FalseVal, TrueVal,
1473                                        CCVal, CCR, InFlag);
1474      if (!Res)
1475        Res = SelectT2CMOVSoImmOp(Op, TrueVal, FalseVal,
1476                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1477      if (Res)
1478        return Res;
1479    } else {
1480      SDNode *Res = SelectARMCMOVSoImmOp(Op, FalseVal, TrueVal,
1481                                         CCVal, CCR, InFlag);
1482      if (!Res)
1483        Res = SelectARMCMOVSoImmOp(Op, TrueVal, FalseVal,
1484                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1485      if (Res)
1486        return Res;
1487    }
1488  }
1489
1490  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1491  // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1492  // Pattern complexity = 6  cost = 1  size = 0
1493  //
1494  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1495  // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1496  // Pattern complexity = 6  cost = 11  size = 0
1497  //
1498  // Also FCPYScc and FCPYDcc.
1499  SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1500  SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1501  unsigned Opc = 0;
1502  switch (VT.getSimpleVT().SimpleTy) {
1503  default: assert(false && "Illegal conditional move type!");
1504    break;
1505  case MVT::i32:
1506    Opc = Subtarget->isThumb()
1507      ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1508      : ARM::MOVCCr;
1509    break;
1510  case MVT::f32:
1511    Opc = ARM::VMOVScc;
1512    break;
1513  case MVT::f64:
1514    Opc = ARM::VMOVDcc;
1515    break;
1516  }
1517  return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1518}
1519
1520SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
1521  SDNode *N = Op.getNode();
1522  DebugLoc dl = N->getDebugLoc();
1523
1524  if (N->isMachineOpcode())
1525    return NULL;   // Already selected.
1526
1527  switch (N->getOpcode()) {
1528  default: break;
1529  case ISD::Constant: {
1530    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1531    bool UseCP = true;
1532    if (Subtarget->hasThumb2())
1533      // Thumb2-aware targets have the MOVT instruction, so all immediates can
1534      // be done with MOV + MOVT, at worst.
1535      UseCP = 0;
1536    else {
1537      if (Subtarget->isThumb()) {
1538        UseCP = (Val > 255 &&                          // MOV
1539                 ~Val > 255 &&                         // MOV + MVN
1540                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
1541      } else
1542        UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
1543                 ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
1544                 !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
1545    }
1546
1547    if (UseCP) {
1548      SDValue CPIdx =
1549        CurDAG->getTargetConstantPool(ConstantInt::get(
1550                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
1551                                      TLI.getPointerTy());
1552
1553      SDNode *ResNode;
1554      if (Subtarget->isThumb1Only()) {
1555        SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1556        SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1557        SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1558        ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1559                                         Ops, 4);
1560      } else {
1561        SDValue Ops[] = {
1562          CPIdx,
1563          CurDAG->getRegister(0, MVT::i32),
1564          CurDAG->getTargetConstant(0, MVT::i32),
1565          getAL(CurDAG),
1566          CurDAG->getRegister(0, MVT::i32),
1567          CurDAG->getEntryNode()
1568        };
1569        ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1570                                       Ops, 6);
1571      }
1572      ReplaceUses(Op, SDValue(ResNode, 0));
1573      return NULL;
1574    }
1575
1576    // Other cases are autogenerated.
1577    break;
1578  }
1579  case ISD::FrameIndex: {
1580    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1581    int FI = cast<FrameIndexSDNode>(N)->getIndex();
1582    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1583    if (Subtarget->isThumb1Only()) {
1584      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1585                                  CurDAG->getTargetConstant(0, MVT::i32));
1586    } else {
1587      unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1588                      ARM::t2ADDri : ARM::ADDri);
1589      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1590                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1591                        CurDAG->getRegister(0, MVT::i32) };
1592      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1593    }
1594  }
1595  case ARMISD::DYN_ALLOC:
1596    return SelectDYN_ALLOC(Op);
1597  case ISD::SRL:
1598    if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
1599                      Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX))
1600      return I;
1601    break;
1602  case ISD::SRA:
1603    if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
1604                      Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX))
1605      return I;
1606    break;
1607  case ISD::MUL:
1608    if (Subtarget->isThumb1Only())
1609      break;
1610    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1611      unsigned RHSV = C->getZExtValue();
1612      if (!RHSV) break;
1613      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
1614        unsigned ShImm = Log2_32(RHSV-1);
1615        if (ShImm >= 32)
1616          break;
1617        SDValue V = Op.getOperand(0);
1618        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1619        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1620        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1621        if (Subtarget->isThumb()) {
1622          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1623          return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1624        } else {
1625          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1626          return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1627        }
1628      }
1629      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
1630        unsigned ShImm = Log2_32(RHSV+1);
1631        if (ShImm >= 32)
1632          break;
1633        SDValue V = Op.getOperand(0);
1634        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1635        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1636        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1637        if (Subtarget->isThumb()) {
1638          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1639          return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1640        } else {
1641          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1642          return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1643        }
1644      }
1645    }
1646    break;
1647  case ISD::AND: {
1648    // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
1649    // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
1650    // are entirely contributed by c2 and lower 16-bits are entirely contributed
1651    // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
1652    // Select it to: "movt x, ((c1 & 0xffff) >> 16)
1653    EVT VT = Op.getValueType();
1654    if (VT != MVT::i32)
1655      break;
1656    unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
1657      ? ARM::t2MOVTi16
1658      : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
1659    if (!Opc)
1660      break;
1661    SDValue N0 = Op.getOperand(0), N1 = Op.getOperand(1);
1662    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1663    if (!N1C)
1664      break;
1665    if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
1666      SDValue N2 = N0.getOperand(1);
1667      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1668      if (!N2C)
1669        break;
1670      unsigned N1CVal = N1C->getZExtValue();
1671      unsigned N2CVal = N2C->getZExtValue();
1672      if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
1673          (N1CVal & 0xffffU) == 0xffffU &&
1674          (N2CVal & 0xffffU) == 0x0U) {
1675        SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
1676                                                  MVT::i32);
1677        SDValue Ops[] = { N0.getOperand(0), Imm16,
1678                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1679        return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
1680      }
1681    }
1682    break;
1683  }
1684  case ARMISD::VMOVRRD:
1685    return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
1686                                  Op.getOperand(0), getAL(CurDAG),
1687                                  CurDAG->getRegister(0, MVT::i32));
1688  case ISD::UMUL_LOHI: {
1689    if (Subtarget->isThumb1Only())
1690      break;
1691    if (Subtarget->isThumb()) {
1692      SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1693                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1694                        CurDAG->getRegister(0, MVT::i32) };
1695      return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1696    } else {
1697      SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1698                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1699                        CurDAG->getRegister(0, MVT::i32) };
1700      return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1701    }
1702  }
1703  case ISD::SMUL_LOHI: {
1704    if (Subtarget->isThumb1Only())
1705      break;
1706    if (Subtarget->isThumb()) {
1707      SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1708                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1709      return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1710    } else {
1711      SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1712                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1713                        CurDAG->getRegister(0, MVT::i32) };
1714      return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1715    }
1716  }
1717  case ISD::LOAD: {
1718    SDNode *ResNode = 0;
1719    if (Subtarget->isThumb() && Subtarget->hasThumb2())
1720      ResNode = SelectT2IndexedLoad(Op);
1721    else
1722      ResNode = SelectARMIndexedLoad(Op);
1723    if (ResNode)
1724      return ResNode;
1725    // Other cases are autogenerated.
1726    break;
1727  }
1728  case ARMISD::BRCOND: {
1729    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1730    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1731    // Pattern complexity = 6  cost = 1  size = 0
1732
1733    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1734    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1735    // Pattern complexity = 6  cost = 1  size = 0
1736
1737    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1738    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1739    // Pattern complexity = 6  cost = 1  size = 0
1740
1741    unsigned Opc = Subtarget->isThumb() ?
1742      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1743    SDValue Chain = Op.getOperand(0);
1744    SDValue N1 = Op.getOperand(1);
1745    SDValue N2 = Op.getOperand(2);
1746    SDValue N3 = Op.getOperand(3);
1747    SDValue InFlag = Op.getOperand(4);
1748    assert(N1.getOpcode() == ISD::BasicBlock);
1749    assert(N2.getOpcode() == ISD::Constant);
1750    assert(N3.getOpcode() == ISD::Register);
1751
1752    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1753                               cast<ConstantSDNode>(N2)->getZExtValue()),
1754                               MVT::i32);
1755    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1756    SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1757                                             MVT::Flag, Ops, 5);
1758    Chain = SDValue(ResNode, 0);
1759    if (Op.getNode()->getNumValues() == 2) {
1760      InFlag = SDValue(ResNode, 1);
1761      ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1762    }
1763    ReplaceUses(SDValue(Op.getNode(), 0),
1764                SDValue(Chain.getNode(), Chain.getResNo()));
1765    return NULL;
1766  }
1767  case ARMISD::CMOV:
1768    return SelectCMOVOp(Op);
1769  case ARMISD::CNEG: {
1770    EVT VT = Op.getValueType();
1771    SDValue N0 = Op.getOperand(0);
1772    SDValue N1 = Op.getOperand(1);
1773    SDValue N2 = Op.getOperand(2);
1774    SDValue N3 = Op.getOperand(3);
1775    SDValue InFlag = Op.getOperand(4);
1776    assert(N2.getOpcode() == ISD::Constant);
1777    assert(N3.getOpcode() == ISD::Register);
1778
1779    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1780                               cast<ConstantSDNode>(N2)->getZExtValue()),
1781                               MVT::i32);
1782    SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1783    unsigned Opc = 0;
1784    switch (VT.getSimpleVT().SimpleTy) {
1785    default: assert(false && "Illegal conditional move type!");
1786      break;
1787    case MVT::f32:
1788      Opc = ARM::VNEGScc;
1789      break;
1790    case MVT::f64:
1791      Opc = ARM::VNEGDcc;
1792      break;
1793    }
1794    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1795  }
1796
1797  case ARMISD::VZIP: {
1798    unsigned Opc = 0;
1799    EVT VT = N->getValueType(0);
1800    switch (VT.getSimpleVT().SimpleTy) {
1801    default: return NULL;
1802    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
1803    case MVT::v4i16: Opc = ARM::VZIPd16; break;
1804    case MVT::v2f32:
1805    case MVT::v2i32: Opc = ARM::VZIPd32; break;
1806    case MVT::v16i8: Opc = ARM::VZIPq8; break;
1807    case MVT::v8i16: Opc = ARM::VZIPq16; break;
1808    case MVT::v4f32:
1809    case MVT::v4i32: Opc = ARM::VZIPq32; break;
1810    }
1811    SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1812    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1813    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1814    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1815  }
1816  case ARMISD::VUZP: {
1817    unsigned Opc = 0;
1818    EVT VT = N->getValueType(0);
1819    switch (VT.getSimpleVT().SimpleTy) {
1820    default: return NULL;
1821    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
1822    case MVT::v4i16: Opc = ARM::VUZPd16; break;
1823    case MVT::v2f32:
1824    case MVT::v2i32: Opc = ARM::VUZPd32; break;
1825    case MVT::v16i8: Opc = ARM::VUZPq8; break;
1826    case MVT::v8i16: Opc = ARM::VUZPq16; break;
1827    case MVT::v4f32:
1828    case MVT::v4i32: Opc = ARM::VUZPq32; break;
1829    }
1830    SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1831    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1832    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1833    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1834  }
1835  case ARMISD::VTRN: {
1836    unsigned Opc = 0;
1837    EVT VT = N->getValueType(0);
1838    switch (VT.getSimpleVT().SimpleTy) {
1839    default: return NULL;
1840    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
1841    case MVT::v4i16: Opc = ARM::VTRNd16; break;
1842    case MVT::v2f32:
1843    case MVT::v2i32: Opc = ARM::VTRNd32; break;
1844    case MVT::v16i8: Opc = ARM::VTRNq8; break;
1845    case MVT::v8i16: Opc = ARM::VTRNq16; break;
1846    case MVT::v4f32:
1847    case MVT::v4i32: Opc = ARM::VTRNq32; break;
1848    }
1849    SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1850    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1851    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1852    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1853  }
1854
1855  case ISD::INTRINSIC_VOID:
1856  case ISD::INTRINSIC_W_CHAIN: {
1857    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1858    switch (IntNo) {
1859    default:
1860      break;
1861
1862    case Intrinsic::arm_neon_vld2: {
1863      unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
1864                              ARM::VLD2d32, ARM::VLD2d64 };
1865      unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 };
1866      return SelectVLD(Op, 2, DOpcodes, QOpcodes, 0);
1867    }
1868
1869    case Intrinsic::arm_neon_vld3: {
1870      unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
1871                              ARM::VLD3d32, ARM::VLD3d64 };
1872      unsigned QOpcodes0[] = { ARM::VLD3q8a, ARM::VLD3q16a, ARM::VLD3q32a };
1873      unsigned QOpcodes1[] = { ARM::VLD3q8b, ARM::VLD3q16b, ARM::VLD3q32b };
1874      return SelectVLD(Op, 3, DOpcodes, QOpcodes0, QOpcodes1);
1875    }
1876
1877    case Intrinsic::arm_neon_vld4: {
1878      unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
1879                              ARM::VLD4d32, ARM::VLD4d64 };
1880      unsigned QOpcodes0[] = { ARM::VLD4q8a, ARM::VLD4q16a, ARM::VLD4q32a };
1881      unsigned QOpcodes1[] = { ARM::VLD4q8b, ARM::VLD4q16b, ARM::VLD4q32b };
1882      return SelectVLD(Op, 4, DOpcodes, QOpcodes0, QOpcodes1);
1883    }
1884
1885    case Intrinsic::arm_neon_vld2lane: {
1886      unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 };
1887      unsigned QOpcodes0[] = { ARM::VLD2LNq16a, ARM::VLD2LNq32a };
1888      unsigned QOpcodes1[] = { ARM::VLD2LNq16b, ARM::VLD2LNq32b };
1889      return SelectVLDSTLane(Op, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
1890    }
1891
1892    case Intrinsic::arm_neon_vld3lane: {
1893      unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 };
1894      unsigned QOpcodes0[] = { ARM::VLD3LNq16a, ARM::VLD3LNq32a };
1895      unsigned QOpcodes1[] = { ARM::VLD3LNq16b, ARM::VLD3LNq32b };
1896      return SelectVLDSTLane(Op, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
1897    }
1898
1899    case Intrinsic::arm_neon_vld4lane: {
1900      unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 };
1901      unsigned QOpcodes0[] = { ARM::VLD4LNq16a, ARM::VLD4LNq32a };
1902      unsigned QOpcodes1[] = { ARM::VLD4LNq16b, ARM::VLD4LNq32b };
1903      return SelectVLDSTLane(Op, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
1904    }
1905
1906    case Intrinsic::arm_neon_vst2: {
1907      unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
1908                              ARM::VST2d32, ARM::VST2d64 };
1909      unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
1910      return SelectVST(Op, 2, DOpcodes, QOpcodes, 0);
1911    }
1912
1913    case Intrinsic::arm_neon_vst3: {
1914      unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
1915                              ARM::VST3d32, ARM::VST3d64 };
1916      unsigned QOpcodes0[] = { ARM::VST3q8a, ARM::VST3q16a, ARM::VST3q32a };
1917      unsigned QOpcodes1[] = { ARM::VST3q8b, ARM::VST3q16b, ARM::VST3q32b };
1918      return SelectVST(Op, 3, DOpcodes, QOpcodes0, QOpcodes1);
1919    }
1920
1921    case Intrinsic::arm_neon_vst4: {
1922      unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
1923                              ARM::VST4d32, ARM::VST4d64 };
1924      unsigned QOpcodes0[] = { ARM::VST4q8a, ARM::VST4q16a, ARM::VST4q32a };
1925      unsigned QOpcodes1[] = { ARM::VST4q8b, ARM::VST4q16b, ARM::VST4q32b };
1926      return SelectVST(Op, 4, DOpcodes, QOpcodes0, QOpcodes1);
1927    }
1928
1929    case Intrinsic::arm_neon_vst2lane: {
1930      unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 };
1931      unsigned QOpcodes0[] = { ARM::VST2LNq16a, ARM::VST2LNq32a };
1932      unsigned QOpcodes1[] = { ARM::VST2LNq16b, ARM::VST2LNq32b };
1933      return SelectVLDSTLane(Op, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
1934    }
1935
1936    case Intrinsic::arm_neon_vst3lane: {
1937      unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 };
1938      unsigned QOpcodes0[] = { ARM::VST3LNq16a, ARM::VST3LNq32a };
1939      unsigned QOpcodes1[] = { ARM::VST3LNq16b, ARM::VST3LNq32b };
1940      return SelectVLDSTLane(Op, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
1941    }
1942
1943    case Intrinsic::arm_neon_vst4lane: {
1944      unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 };
1945      unsigned QOpcodes0[] = { ARM::VST4LNq16a, ARM::VST4LNq32a };
1946      unsigned QOpcodes1[] = { ARM::VST4LNq16b, ARM::VST4LNq32b };
1947      return SelectVLDSTLane(Op, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
1948    }
1949    }
1950  }
1951  }
1952
1953  return SelectCode(Op);
1954}
1955
1956bool ARMDAGToDAGISel::
1957SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1958                             std::vector<SDValue> &OutOps) {
1959  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1960  // Require the address to be in a register.  That is safe for all ARM
1961  // variants and it is hard to do anything much smarter without knowing
1962  // how the operand is used.
1963  OutOps.push_back(Op);
1964  return false;
1965}
1966
1967/// createARMISelDag - This pass converts a legalized DAG into a
1968/// ARM-specific DAG, ready for instruction scheduling.
1969///
1970FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
1971                                     CodeGenOpt::Level OptLevel) {
1972  return new ARMDAGToDAGISel(TM, OptLevel);
1973}
1974