ARMISelDAGToDAG.cpp revision 226633 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "arm-isel"
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMTargetMachine.h"
18#include "MCTargetDesc/ARMAddressingModes.h"
19#include "llvm/CallingConv.h"
20#include "llvm/Constants.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/SelectionDAG.h"
29#include "llvm/CodeGen/SelectionDAGISel.h"
30#include "llvm/Target/TargetLowering.h"
31#include "llvm/Target/TargetOptions.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37
38using namespace llvm;
39
40static cl::opt<bool>
41DisableShifterOp("disable-shifter-op", cl::Hidden,
42  cl::desc("Disable isel of shifter-op"),
43  cl::init(false));
44
45static cl::opt<bool>
46CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47  cl::desc("Check fp vmla / vmls hazard at isel time"),
48  cl::init(true));
49
50static cl::opt<bool>
51DisableARMIntABS("disable-arm-int-abs", cl::Hidden,
52  cl::desc("Enable / disable ARM integer abs transform"),
53  cl::init(false));
54
55//===--------------------------------------------------------------------===//
56/// ARMDAGToDAGISel - ARM specific code to select ARM machine
57/// instructions for SelectionDAG operations.
58///
59namespace {
60
61enum AddrMode2Type {
62  AM2_BASE, // Simple AM2 (+-imm12)
63  AM2_SHOP  // Shifter-op AM2
64};
65
66class ARMDAGToDAGISel : public SelectionDAGISel {
67  ARMBaseTargetMachine &TM;
68  const ARMBaseInstrInfo *TII;
69
70  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
71  /// make the right decision when generating code for different targets.
72  const ARMSubtarget *Subtarget;
73
74public:
75  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
76                           CodeGenOpt::Level OptLevel)
77    : SelectionDAGISel(tm, OptLevel), TM(tm),
78      TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
79      Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
80  }
81
82  virtual const char *getPassName() const {
83    return "ARM Instruction Selection";
84  }
85
86  /// getI32Imm - Return a target constant of type i32 with the specified
87  /// value.
88  inline SDValue getI32Imm(unsigned Imm) {
89    return CurDAG->getTargetConstant(Imm, MVT::i32);
90  }
91
92  SDNode *Select(SDNode *N);
93
94
95  bool hasNoVMLxHazardUse(SDNode *N) const;
96  bool isShifterOpProfitable(const SDValue &Shift,
97                             ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
98  bool SelectRegShifterOperand(SDValue N, SDValue &A,
99                               SDValue &B, SDValue &C,
100                               bool CheckProfitability = true);
101  bool SelectImmShifterOperand(SDValue N, SDValue &A,
102                               SDValue &B, bool CheckProfitability = true);
103  bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
104                                    SDValue &B, SDValue &C) {
105    // Don't apply the profitability check
106    return SelectRegShifterOperand(N, A, B, C, false);
107  }
108  bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
109                                    SDValue &B) {
110    // Don't apply the profitability check
111    return SelectImmShifterOperand(N, A, B, false);
112  }
113
114  bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
115  bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
116
117  AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
118                                      SDValue &Offset, SDValue &Opc);
119  bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
120                           SDValue &Opc) {
121    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
122  }
123
124  bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
125                           SDValue &Opc) {
126    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
127  }
128
129  bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
130                       SDValue &Opc) {
131    SelectAddrMode2Worker(N, Base, Offset, Opc);
132//    return SelectAddrMode2ShOp(N, Base, Offset, Opc);
133    // This always matches one way or another.
134    return true;
135  }
136
137  bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
138                             SDValue &Offset, SDValue &Opc);
139  bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
140                             SDValue &Offset, SDValue &Opc);
141  bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
142                             SDValue &Offset, SDValue &Opc);
143  bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
144  bool SelectAddrMode3(SDValue N, SDValue &Base,
145                       SDValue &Offset, SDValue &Opc);
146  bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
147                             SDValue &Offset, SDValue &Opc);
148  bool SelectAddrMode5(SDValue N, SDValue &Base,
149                       SDValue &Offset);
150  bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
151  bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
152
153  bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
154
155  // Thumb Addressing Modes:
156  bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
157  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
158                             unsigned Scale);
159  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
160  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
161  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
162  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
163                                SDValue &OffImm);
164  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
165                                 SDValue &OffImm);
166  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
167                                 SDValue &OffImm);
168  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
169                                 SDValue &OffImm);
170  bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
171
172  // Thumb 2 Addressing Modes:
173  bool SelectT2ShifterOperandReg(SDValue N,
174                                 SDValue &BaseReg, SDValue &Opc);
175  bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
176  bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
177                            SDValue &OffImm);
178  bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
179                                 SDValue &OffImm);
180  bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
181                             SDValue &OffReg, SDValue &ShImm);
182
183  inline bool is_so_imm(unsigned Imm) const {
184    return ARM_AM::getSOImmVal(Imm) != -1;
185  }
186
187  inline bool is_so_imm_not(unsigned Imm) const {
188    return ARM_AM::getSOImmVal(~Imm) != -1;
189  }
190
191  inline bool is_t2_so_imm(unsigned Imm) const {
192    return ARM_AM::getT2SOImmVal(Imm) != -1;
193  }
194
195  inline bool is_t2_so_imm_not(unsigned Imm) const {
196    return ARM_AM::getT2SOImmVal(~Imm) != -1;
197  }
198
199  // Include the pieces autogenerated from the target description.
200#include "ARMGenDAGISel.inc"
201
202private:
203  /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
204  /// ARM.
205  SDNode *SelectARMIndexedLoad(SDNode *N);
206  SDNode *SelectT2IndexedLoad(SDNode *N);
207
208  /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
209  /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
210  /// loads of D registers and even subregs and odd subregs of Q registers.
211  /// For NumVecs <= 2, QOpcodes1 is not used.
212  SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
213                    unsigned *DOpcodes,
214                    unsigned *QOpcodes0, unsigned *QOpcodes1);
215
216  /// SelectVST - Select NEON store intrinsics.  NumVecs should
217  /// be 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
218  /// stores of D registers and even subregs and odd subregs of Q registers.
219  /// For NumVecs <= 2, QOpcodes1 is not used.
220  SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
221                    unsigned *DOpcodes,
222                    unsigned *QOpcodes0, unsigned *QOpcodes1);
223
224  /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
225  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
226  /// load/store of D registers and Q registers.
227  SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
228                          bool isUpdating, unsigned NumVecs,
229                          unsigned *DOpcodes, unsigned *QOpcodes);
230
231  /// SelectVLDDup - Select NEON load-duplicate intrinsics.  NumVecs
232  /// should be 2, 3 or 4.  The opcode array specifies the instructions used
233  /// for loading D registers.  (Q registers are not supported.)
234  SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
235                       unsigned *Opcodes);
236
237  /// SelectVTBL - Select NEON VTBL and VTBX intrinsics.  NumVecs should be 2,
238  /// 3 or 4.  These are custom-selected so that a REG_SEQUENCE can be
239  /// generated to force the table registers to be consecutive.
240  SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
241
242  /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
243  SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
244
245  /// SelectCMOVOp - Select CMOV instructions for ARM.
246  SDNode *SelectCMOVOp(SDNode *N);
247  SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
248                              ARMCC::CondCodes CCVal, SDValue CCR,
249                              SDValue InFlag);
250  SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
251                               ARMCC::CondCodes CCVal, SDValue CCR,
252                               SDValue InFlag);
253  SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
254                              ARMCC::CondCodes CCVal, SDValue CCR,
255                              SDValue InFlag);
256  SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
257                               ARMCC::CondCodes CCVal, SDValue CCR,
258                               SDValue InFlag);
259
260  // Select special operations if node forms integer ABS pattern
261  SDNode *SelectABSOp(SDNode *N);
262
263  SDNode *SelectConcatVector(SDNode *N);
264
265  SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
266
267  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
268  /// inline asm expressions.
269  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
270                                            char ConstraintCode,
271                                            std::vector<SDValue> &OutOps);
272
273  // Form pairs of consecutive S, D, or Q registers.
274  SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
275  SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
276  SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
277
278  // Form sequences of 4 consecutive S, D, or Q registers.
279  SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
280  SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
281  SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
282
283  // Get the alignment operand for a NEON VLD or VST instruction.
284  SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
285};
286}
287
288/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
289/// operand. If so Imm will receive the 32-bit value.
290static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
291  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
292    Imm = cast<ConstantSDNode>(N)->getZExtValue();
293    return true;
294  }
295  return false;
296}
297
298// isInt32Immediate - This method tests to see if a constant operand.
299// If so Imm will receive the 32 bit value.
300static bool isInt32Immediate(SDValue N, unsigned &Imm) {
301  return isInt32Immediate(N.getNode(), Imm);
302}
303
304// isOpcWithIntImmediate - This method tests to see if the node is a specific
305// opcode and that it has a immediate integer right operand.
306// If so Imm will receive the 32 bit value.
307static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
308  return N->getOpcode() == Opc &&
309         isInt32Immediate(N->getOperand(1).getNode(), Imm);
310}
311
312/// \brief Check whether a particular node is a constant value representable as
313/// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
314///
315/// \param ScaledConstant [out] - On success, the pre-scaled constant value.
316static bool isScaledConstantInRange(SDValue Node, int Scale,
317                                    int RangeMin, int RangeMax,
318                                    int &ScaledConstant) {
319  assert(Scale > 0 && "Invalid scale!");
320
321  // Check that this is a constant.
322  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
323  if (!C)
324    return false;
325
326  ScaledConstant = (int) C->getZExtValue();
327  if ((ScaledConstant % Scale) != 0)
328    return false;
329
330  ScaledConstant /= Scale;
331  return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
332}
333
334/// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
335/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
336/// least on current ARM implementations) which should be avoidded.
337bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
338  if (OptLevel == CodeGenOpt::None)
339    return true;
340
341  if (!CheckVMLxHazard)
342    return true;
343
344  if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
345    return true;
346
347  if (!N->hasOneUse())
348    return false;
349
350  SDNode *Use = *N->use_begin();
351  if (Use->getOpcode() == ISD::CopyToReg)
352    return true;
353  if (Use->isMachineOpcode()) {
354    const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
355    if (MCID.mayStore())
356      return true;
357    unsigned Opcode = MCID.getOpcode();
358    if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
359      return true;
360    // vmlx feeding into another vmlx. We actually want to unfold
361    // the use later in the MLxExpansion pass. e.g.
362    // vmla
363    // vmla (stall 8 cycles)
364    //
365    // vmul (5 cycles)
366    // vadd (5 cycles)
367    // vmla
368    // This adds up to about 18 - 19 cycles.
369    //
370    // vmla
371    // vmul (stall 4 cycles)
372    // vadd adds up to about 14 cycles.
373    return TII->isFpMLxInstruction(Opcode);
374  }
375
376  return false;
377}
378
379bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
380                                            ARM_AM::ShiftOpc ShOpcVal,
381                                            unsigned ShAmt) {
382  if (!Subtarget->isCortexA9())
383    return true;
384  if (Shift.hasOneUse())
385    return true;
386  // R << 2 is free.
387  return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
388}
389
390bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
391                                              SDValue &BaseReg,
392                                              SDValue &Opc,
393                                              bool CheckProfitability) {
394  if (DisableShifterOp)
395    return false;
396
397  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
398
399  // Don't match base register only case. That is matched to a separate
400  // lower complexity pattern with explicit register operand.
401  if (ShOpcVal == ARM_AM::no_shift) return false;
402
403  BaseReg = N.getOperand(0);
404  unsigned ShImmVal = 0;
405  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
406  if (!RHS) return false;
407  ShImmVal = RHS->getZExtValue() & 31;
408  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
409                                  MVT::i32);
410  return true;
411}
412
413bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
414                                              SDValue &BaseReg,
415                                              SDValue &ShReg,
416                                              SDValue &Opc,
417                                              bool CheckProfitability) {
418  if (DisableShifterOp)
419    return false;
420
421  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
422
423  // Don't match base register only case. That is matched to a separate
424  // lower complexity pattern with explicit register operand.
425  if (ShOpcVal == ARM_AM::no_shift) return false;
426
427  BaseReg = N.getOperand(0);
428  unsigned ShImmVal = 0;
429  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
430  if (RHS) return false;
431
432  ShReg = N.getOperand(1);
433  if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
434    return false;
435  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
436                                  MVT::i32);
437  return true;
438}
439
440
441bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
442                                          SDValue &Base,
443                                          SDValue &OffImm) {
444  // Match simple R + imm12 operands.
445
446  // Base only.
447  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
448      !CurDAG->isBaseWithConstantOffset(N)) {
449    if (N.getOpcode() == ISD::FrameIndex) {
450      // Match frame index.
451      int FI = cast<FrameIndexSDNode>(N)->getIndex();
452      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
453      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
454      return true;
455    }
456
457    if (N.getOpcode() == ARMISD::Wrapper &&
458        !(Subtarget->useMovt() &&
459                     N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
460      Base = N.getOperand(0);
461    } else
462      Base = N;
463    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
464    return true;
465  }
466
467  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
468    int RHSC = (int)RHS->getZExtValue();
469    if (N.getOpcode() == ISD::SUB)
470      RHSC = -RHSC;
471
472    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
473      Base   = N.getOperand(0);
474      if (Base.getOpcode() == ISD::FrameIndex) {
475        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
476        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
477      }
478      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
479      return true;
480    }
481  }
482
483  // Base only.
484  Base = N;
485  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
486  return true;
487}
488
489
490
491bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
492                                      SDValue &Opc) {
493  if (N.getOpcode() == ISD::MUL &&
494      (!Subtarget->isCortexA9() || N.hasOneUse())) {
495    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
496      // X * [3,5,9] -> X + X * [2,4,8] etc.
497      int RHSC = (int)RHS->getZExtValue();
498      if (RHSC & 1) {
499        RHSC = RHSC & ~1;
500        ARM_AM::AddrOpc AddSub = ARM_AM::add;
501        if (RHSC < 0) {
502          AddSub = ARM_AM::sub;
503          RHSC = - RHSC;
504        }
505        if (isPowerOf2_32(RHSC)) {
506          unsigned ShAmt = Log2_32(RHSC);
507          Base = Offset = N.getOperand(0);
508          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
509                                                            ARM_AM::lsl),
510                                          MVT::i32);
511          return true;
512        }
513      }
514    }
515  }
516
517  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
518      // ISD::OR that is equivalent to an ISD::ADD.
519      !CurDAG->isBaseWithConstantOffset(N))
520    return false;
521
522  // Leave simple R +/- imm12 operands for LDRi12
523  if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
524    int RHSC;
525    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
526                                -0x1000+1, 0x1000, RHSC)) // 12 bits.
527      return false;
528  }
529
530  // Otherwise this is R +/- [possibly shifted] R.
531  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
532  ARM_AM::ShiftOpc ShOpcVal =
533    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
534  unsigned ShAmt = 0;
535
536  Base   = N.getOperand(0);
537  Offset = N.getOperand(1);
538
539  if (ShOpcVal != ARM_AM::no_shift) {
540    // Check to see if the RHS of the shift is a constant, if not, we can't fold
541    // it.
542    if (ConstantSDNode *Sh =
543           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
544      ShAmt = Sh->getZExtValue();
545      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
546        Offset = N.getOperand(1).getOperand(0);
547      else {
548        ShAmt = 0;
549        ShOpcVal = ARM_AM::no_shift;
550      }
551    } else {
552      ShOpcVal = ARM_AM::no_shift;
553    }
554  }
555
556  // Try matching (R shl C) + (R).
557  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
558      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
559    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
560    if (ShOpcVal != ARM_AM::no_shift) {
561      // Check to see if the RHS of the shift is a constant, if not, we can't
562      // fold it.
563      if (ConstantSDNode *Sh =
564          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
565        ShAmt = Sh->getZExtValue();
566        if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
567          Offset = N.getOperand(0).getOperand(0);
568          Base = N.getOperand(1);
569        } else {
570          ShAmt = 0;
571          ShOpcVal = ARM_AM::no_shift;
572        }
573      } else {
574        ShOpcVal = ARM_AM::no_shift;
575      }
576    }
577  }
578
579  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
580                                  MVT::i32);
581  return true;
582}
583
584
585
586
587//-----
588
589AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
590                                                     SDValue &Base,
591                                                     SDValue &Offset,
592                                                     SDValue &Opc) {
593  if (N.getOpcode() == ISD::MUL &&
594      (!Subtarget->isCortexA9() || N.hasOneUse())) {
595    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
596      // X * [3,5,9] -> X + X * [2,4,8] etc.
597      int RHSC = (int)RHS->getZExtValue();
598      if (RHSC & 1) {
599        RHSC = RHSC & ~1;
600        ARM_AM::AddrOpc AddSub = ARM_AM::add;
601        if (RHSC < 0) {
602          AddSub = ARM_AM::sub;
603          RHSC = - RHSC;
604        }
605        if (isPowerOf2_32(RHSC)) {
606          unsigned ShAmt = Log2_32(RHSC);
607          Base = Offset = N.getOperand(0);
608          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
609                                                            ARM_AM::lsl),
610                                          MVT::i32);
611          return AM2_SHOP;
612        }
613      }
614    }
615  }
616
617  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
618      // ISD::OR that is equivalent to an ADD.
619      !CurDAG->isBaseWithConstantOffset(N)) {
620    Base = N;
621    if (N.getOpcode() == ISD::FrameIndex) {
622      int FI = cast<FrameIndexSDNode>(N)->getIndex();
623      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
624    } else if (N.getOpcode() == ARMISD::Wrapper &&
625               !(Subtarget->useMovt() &&
626                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
627      Base = N.getOperand(0);
628    }
629    Offset = CurDAG->getRegister(0, MVT::i32);
630    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
631                                                      ARM_AM::no_shift),
632                                    MVT::i32);
633    return AM2_BASE;
634  }
635
636  // Match simple R +/- imm12 operands.
637  if (N.getOpcode() != ISD::SUB) {
638    int RHSC;
639    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
640                                -0x1000+1, 0x1000, RHSC)) { // 12 bits.
641      Base = N.getOperand(0);
642      if (Base.getOpcode() == ISD::FrameIndex) {
643        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
644        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
645      }
646      Offset = CurDAG->getRegister(0, MVT::i32);
647
648      ARM_AM::AddrOpc AddSub = ARM_AM::add;
649      if (RHSC < 0) {
650        AddSub = ARM_AM::sub;
651        RHSC = - RHSC;
652      }
653      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
654                                                        ARM_AM::no_shift),
655                                      MVT::i32);
656      return AM2_BASE;
657    }
658  }
659
660  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
661    // Compute R +/- (R << N) and reuse it.
662    Base = N;
663    Offset = CurDAG->getRegister(0, MVT::i32);
664    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
665                                                      ARM_AM::no_shift),
666                                    MVT::i32);
667    return AM2_BASE;
668  }
669
670  // Otherwise this is R +/- [possibly shifted] R.
671  ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
672  ARM_AM::ShiftOpc ShOpcVal =
673    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
674  unsigned ShAmt = 0;
675
676  Base   = N.getOperand(0);
677  Offset = N.getOperand(1);
678
679  if (ShOpcVal != ARM_AM::no_shift) {
680    // Check to see if the RHS of the shift is a constant, if not, we can't fold
681    // it.
682    if (ConstantSDNode *Sh =
683           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
684      ShAmt = Sh->getZExtValue();
685      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
686        Offset = N.getOperand(1).getOperand(0);
687      else {
688        ShAmt = 0;
689        ShOpcVal = ARM_AM::no_shift;
690      }
691    } else {
692      ShOpcVal = ARM_AM::no_shift;
693    }
694  }
695
696  // Try matching (R shl C) + (R).
697  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
698      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
699    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
700    if (ShOpcVal != ARM_AM::no_shift) {
701      // Check to see if the RHS of the shift is a constant, if not, we can't
702      // fold it.
703      if (ConstantSDNode *Sh =
704          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
705        ShAmt = Sh->getZExtValue();
706        if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
707          Offset = N.getOperand(0).getOperand(0);
708          Base = N.getOperand(1);
709        } else {
710          ShAmt = 0;
711          ShOpcVal = ARM_AM::no_shift;
712        }
713      } else {
714        ShOpcVal = ARM_AM::no_shift;
715      }
716    }
717  }
718
719  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
720                                  MVT::i32);
721  return AM2_SHOP;
722}
723
724bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
725                                            SDValue &Offset, SDValue &Opc) {
726  unsigned Opcode = Op->getOpcode();
727  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
728    ? cast<LoadSDNode>(Op)->getAddressingMode()
729    : cast<StoreSDNode>(Op)->getAddressingMode();
730  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
731    ? ARM_AM::add : ARM_AM::sub;
732  int Val;
733  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
734    return false;
735
736  Offset = N;
737  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
738  unsigned ShAmt = 0;
739  if (ShOpcVal != ARM_AM::no_shift) {
740    // Check to see if the RHS of the shift is a constant, if not, we can't fold
741    // it.
742    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
743      ShAmt = Sh->getZExtValue();
744      if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
745        Offset = N.getOperand(0);
746      else {
747        ShAmt = 0;
748        ShOpcVal = ARM_AM::no_shift;
749      }
750    } else {
751      ShOpcVal = ARM_AM::no_shift;
752    }
753  }
754
755  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
756                                  MVT::i32);
757  return true;
758}
759
760bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
761                                            SDValue &Offset, SDValue &Opc) {
762  unsigned Opcode = Op->getOpcode();
763  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
764    ? cast<LoadSDNode>(Op)->getAddressingMode()
765    : cast<StoreSDNode>(Op)->getAddressingMode();
766  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
767    ? ARM_AM::add : ARM_AM::sub;
768  int Val;
769  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
770    if (AddSub == ARM_AM::sub) Val *= -1;
771    Offset = CurDAG->getRegister(0, MVT::i32);
772    Opc = CurDAG->getTargetConstant(Val, MVT::i32);
773    return true;
774  }
775
776  return false;
777}
778
779
780bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
781                                            SDValue &Offset, SDValue &Opc) {
782  unsigned Opcode = Op->getOpcode();
783  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
784    ? cast<LoadSDNode>(Op)->getAddressingMode()
785    : cast<StoreSDNode>(Op)->getAddressingMode();
786  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
787    ? ARM_AM::add : ARM_AM::sub;
788  int Val;
789  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
790    Offset = CurDAG->getRegister(0, MVT::i32);
791    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
792                                                      ARM_AM::no_shift),
793                                    MVT::i32);
794    return true;
795  }
796
797  return false;
798}
799
800bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
801  Base = N;
802  return true;
803}
804
805bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
806                                      SDValue &Base, SDValue &Offset,
807                                      SDValue &Opc) {
808  if (N.getOpcode() == ISD::SUB) {
809    // X - C  is canonicalize to X + -C, no need to handle it here.
810    Base = N.getOperand(0);
811    Offset = N.getOperand(1);
812    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
813    return true;
814  }
815
816  if (!CurDAG->isBaseWithConstantOffset(N)) {
817    Base = N;
818    if (N.getOpcode() == ISD::FrameIndex) {
819      int FI = cast<FrameIndexSDNode>(N)->getIndex();
820      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
821    }
822    Offset = CurDAG->getRegister(0, MVT::i32);
823    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
824    return true;
825  }
826
827  // If the RHS is +/- imm8, fold into addr mode.
828  int RHSC;
829  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
830                              -256 + 1, 256, RHSC)) { // 8 bits.
831    Base = N.getOperand(0);
832    if (Base.getOpcode() == ISD::FrameIndex) {
833      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
834      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
835    }
836    Offset = CurDAG->getRegister(0, MVT::i32);
837
838    ARM_AM::AddrOpc AddSub = ARM_AM::add;
839    if (RHSC < 0) {
840      AddSub = ARM_AM::sub;
841      RHSC = -RHSC;
842    }
843    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
844    return true;
845  }
846
847  Base = N.getOperand(0);
848  Offset = N.getOperand(1);
849  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
850  return true;
851}
852
853bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
854                                            SDValue &Offset, SDValue &Opc) {
855  unsigned Opcode = Op->getOpcode();
856  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
857    ? cast<LoadSDNode>(Op)->getAddressingMode()
858    : cast<StoreSDNode>(Op)->getAddressingMode();
859  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
860    ? ARM_AM::add : ARM_AM::sub;
861  int Val;
862  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
863    Offset = CurDAG->getRegister(0, MVT::i32);
864    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
865    return true;
866  }
867
868  Offset = N;
869  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
870  return true;
871}
872
873bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
874                                      SDValue &Base, SDValue &Offset) {
875  if (!CurDAG->isBaseWithConstantOffset(N)) {
876    Base = N;
877    if (N.getOpcode() == ISD::FrameIndex) {
878      int FI = cast<FrameIndexSDNode>(N)->getIndex();
879      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
880    } else if (N.getOpcode() == ARMISD::Wrapper &&
881               !(Subtarget->useMovt() &&
882                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
883      Base = N.getOperand(0);
884    }
885    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
886                                       MVT::i32);
887    return true;
888  }
889
890  // If the RHS is +/- imm8, fold into addr mode.
891  int RHSC;
892  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
893                              -256 + 1, 256, RHSC)) {
894    Base = N.getOperand(0);
895    if (Base.getOpcode() == ISD::FrameIndex) {
896      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
897      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
898    }
899
900    ARM_AM::AddrOpc AddSub = ARM_AM::add;
901    if (RHSC < 0) {
902      AddSub = ARM_AM::sub;
903      RHSC = -RHSC;
904    }
905    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
906                                       MVT::i32);
907    return true;
908  }
909
910  Base = N;
911  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
912                                     MVT::i32);
913  return true;
914}
915
916bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
917                                      SDValue &Align) {
918  Addr = N;
919
920  unsigned Alignment = 0;
921  if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
922    // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
923    // The maximum alignment is equal to the memory size being referenced.
924    unsigned LSNAlign = LSN->getAlignment();
925    unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
926    if (LSNAlign > MemSize && MemSize > 1)
927      Alignment = MemSize;
928  } else {
929    // All other uses of addrmode6 are for intrinsics.  For now just record
930    // the raw alignment value; it will be refined later based on the legal
931    // alignment operands for the intrinsic.
932    Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
933  }
934
935  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
936  return true;
937}
938
939bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
940                                            SDValue &Offset) {
941  LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
942  ISD::MemIndexedMode AM = LdSt->getAddressingMode();
943  if (AM != ISD::POST_INC)
944    return false;
945  Offset = N;
946  if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
947    if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
948      Offset = CurDAG->getRegister(0, MVT::i32);
949  }
950  return true;
951}
952
953bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
954                                       SDValue &Offset, SDValue &Label) {
955  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
956    Offset = N.getOperand(0);
957    SDValue N1 = N.getOperand(1);
958    Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
959                                      MVT::i32);
960    return true;
961  }
962
963  return false;
964}
965
966
967//===----------------------------------------------------------------------===//
968//                         Thumb Addressing Modes
969//===----------------------------------------------------------------------===//
970
971bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
972                                            SDValue &Base, SDValue &Offset){
973  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
974    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
975    if (!NC || !NC->isNullValue())
976      return false;
977
978    Base = Offset = N;
979    return true;
980  }
981
982  Base = N.getOperand(0);
983  Offset = N.getOperand(1);
984  return true;
985}
986
987bool
988ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
989                                       SDValue &Offset, unsigned Scale) {
990  if (Scale == 4) {
991    SDValue TmpBase, TmpOffImm;
992    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
993      return false;  // We want to select tLDRspi / tSTRspi instead.
994
995    if (N.getOpcode() == ARMISD::Wrapper &&
996        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
997      return false;  // We want to select tLDRpci instead.
998  }
999
1000  if (!CurDAG->isBaseWithConstantOffset(N))
1001    return false;
1002
1003  // Thumb does not have [sp, r] address mode.
1004  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1005  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1006  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1007      (RHSR && RHSR->getReg() == ARM::SP))
1008    return false;
1009
1010  // FIXME: Why do we explicitly check for a match here and then return false?
1011  // Presumably to allow something else to match, but shouldn't this be
1012  // documented?
1013  int RHSC;
1014  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1015    return false;
1016
1017  Base = N.getOperand(0);
1018  Offset = N.getOperand(1);
1019  return true;
1020}
1021
1022bool
1023ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1024                                          SDValue &Base,
1025                                          SDValue &Offset) {
1026  return SelectThumbAddrModeRI(N, Base, Offset, 1);
1027}
1028
1029bool
1030ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1031                                          SDValue &Base,
1032                                          SDValue &Offset) {
1033  return SelectThumbAddrModeRI(N, Base, Offset, 2);
1034}
1035
1036bool
1037ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1038                                          SDValue &Base,
1039                                          SDValue &Offset) {
1040  return SelectThumbAddrModeRI(N, Base, Offset, 4);
1041}
1042
1043bool
1044ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1045                                          SDValue &Base, SDValue &OffImm) {
1046  if (Scale == 4) {
1047    SDValue TmpBase, TmpOffImm;
1048    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1049      return false;  // We want to select tLDRspi / tSTRspi instead.
1050
1051    if (N.getOpcode() == ARMISD::Wrapper &&
1052        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1053      return false;  // We want to select tLDRpci instead.
1054  }
1055
1056  if (!CurDAG->isBaseWithConstantOffset(N)) {
1057    if (N.getOpcode() == ARMISD::Wrapper &&
1058        !(Subtarget->useMovt() &&
1059          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1060      Base = N.getOperand(0);
1061    } else {
1062      Base = N;
1063    }
1064
1065    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1066    return true;
1067  }
1068
1069  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1070  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1071  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1072      (RHSR && RHSR->getReg() == ARM::SP)) {
1073    ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1074    ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1075    unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1076    unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1077
1078    // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1079    if (LHSC != 0 || RHSC != 0) return false;
1080
1081    Base = N;
1082    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1083    return true;
1084  }
1085
1086  // If the RHS is + imm5 * scale, fold into addr mode.
1087  int RHSC;
1088  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1089    Base = N.getOperand(0);
1090    OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1091    return true;
1092  }
1093
1094  Base = N.getOperand(0);
1095  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1096  return true;
1097}
1098
1099bool
1100ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1101                                           SDValue &OffImm) {
1102  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1103}
1104
1105bool
1106ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1107                                           SDValue &OffImm) {
1108  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1109}
1110
1111bool
1112ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1113                                           SDValue &OffImm) {
1114  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1115}
1116
1117bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1118                                            SDValue &Base, SDValue &OffImm) {
1119  if (N.getOpcode() == ISD::FrameIndex) {
1120    int FI = cast<FrameIndexSDNode>(N)->getIndex();
1121    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1122    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1123    return true;
1124  }
1125
1126  if (!CurDAG->isBaseWithConstantOffset(N))
1127    return false;
1128
1129  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1130  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1131      (LHSR && LHSR->getReg() == ARM::SP)) {
1132    // If the RHS is + imm8 * scale, fold into addr mode.
1133    int RHSC;
1134    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1135      Base = N.getOperand(0);
1136      if (Base.getOpcode() == ISD::FrameIndex) {
1137        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1138        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1139      }
1140      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1141      return true;
1142    }
1143  }
1144
1145  return false;
1146}
1147
1148
1149//===----------------------------------------------------------------------===//
1150//                        Thumb 2 Addressing Modes
1151//===----------------------------------------------------------------------===//
1152
1153
1154bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1155                                                SDValue &Opc) {
1156  if (DisableShifterOp)
1157    return false;
1158
1159  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1160
1161  // Don't match base register only case. That is matched to a separate
1162  // lower complexity pattern with explicit register operand.
1163  if (ShOpcVal == ARM_AM::no_shift) return false;
1164
1165  BaseReg = N.getOperand(0);
1166  unsigned ShImmVal = 0;
1167  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1168    ShImmVal = RHS->getZExtValue() & 31;
1169    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1170    return true;
1171  }
1172
1173  return false;
1174}
1175
1176bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1177                                            SDValue &Base, SDValue &OffImm) {
1178  // Match simple R + imm12 operands.
1179
1180  // Base only.
1181  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1182      !CurDAG->isBaseWithConstantOffset(N)) {
1183    if (N.getOpcode() == ISD::FrameIndex) {
1184      // Match frame index.
1185      int FI = cast<FrameIndexSDNode>(N)->getIndex();
1186      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1187      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1188      return true;
1189    }
1190
1191    if (N.getOpcode() == ARMISD::Wrapper &&
1192               !(Subtarget->useMovt() &&
1193                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1194      Base = N.getOperand(0);
1195      if (Base.getOpcode() == ISD::TargetConstantPool)
1196        return false;  // We want to select t2LDRpci instead.
1197    } else
1198      Base = N;
1199    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1200    return true;
1201  }
1202
1203  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1204    if (SelectT2AddrModeImm8(N, Base, OffImm))
1205      // Let t2LDRi8 handle (R - imm8).
1206      return false;
1207
1208    int RHSC = (int)RHS->getZExtValue();
1209    if (N.getOpcode() == ISD::SUB)
1210      RHSC = -RHSC;
1211
1212    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1213      Base   = N.getOperand(0);
1214      if (Base.getOpcode() == ISD::FrameIndex) {
1215        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1216        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1217      }
1218      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1219      return true;
1220    }
1221  }
1222
1223  // Base only.
1224  Base = N;
1225  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1226  return true;
1227}
1228
1229bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1230                                           SDValue &Base, SDValue &OffImm) {
1231  // Match simple R - imm8 operands.
1232  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1233      !CurDAG->isBaseWithConstantOffset(N))
1234    return false;
1235
1236  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1237    int RHSC = (int)RHS->getSExtValue();
1238    if (N.getOpcode() == ISD::SUB)
1239      RHSC = -RHSC;
1240
1241    if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1242      Base = N.getOperand(0);
1243      if (Base.getOpcode() == ISD::FrameIndex) {
1244        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1245        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1246      }
1247      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1248      return true;
1249    }
1250  }
1251
1252  return false;
1253}
1254
1255bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1256                                                 SDValue &OffImm){
1257  unsigned Opcode = Op->getOpcode();
1258  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1259    ? cast<LoadSDNode>(Op)->getAddressingMode()
1260    : cast<StoreSDNode>(Op)->getAddressingMode();
1261  int RHSC;
1262  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1263    OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1264      ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1265      : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1266    return true;
1267  }
1268
1269  return false;
1270}
1271
1272bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1273                                            SDValue &Base,
1274                                            SDValue &OffReg, SDValue &ShImm) {
1275  // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1276  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1277    return false;
1278
1279  // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1280  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1281    int RHSC = (int)RHS->getZExtValue();
1282    if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1283      return false;
1284    else if (RHSC < 0 && RHSC >= -255) // 8 bits
1285      return false;
1286  }
1287
1288  // Look for (R + R) or (R + (R << [1,2,3])).
1289  unsigned ShAmt = 0;
1290  Base   = N.getOperand(0);
1291  OffReg = N.getOperand(1);
1292
1293  // Swap if it is ((R << c) + R).
1294  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1295  if (ShOpcVal != ARM_AM::lsl) {
1296    ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1297    if (ShOpcVal == ARM_AM::lsl)
1298      std::swap(Base, OffReg);
1299  }
1300
1301  if (ShOpcVal == ARM_AM::lsl) {
1302    // Check to see if the RHS of the shift is a constant, if not, we can't fold
1303    // it.
1304    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1305      ShAmt = Sh->getZExtValue();
1306      if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1307        OffReg = OffReg.getOperand(0);
1308      else {
1309        ShAmt = 0;
1310        ShOpcVal = ARM_AM::no_shift;
1311      }
1312    } else {
1313      ShOpcVal = ARM_AM::no_shift;
1314    }
1315  }
1316
1317  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1318
1319  return true;
1320}
1321
1322//===--------------------------------------------------------------------===//
1323
1324/// getAL - Returns a ARMCC::AL immediate node.
1325static inline SDValue getAL(SelectionDAG *CurDAG) {
1326  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1327}
1328
1329SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1330  LoadSDNode *LD = cast<LoadSDNode>(N);
1331  ISD::MemIndexedMode AM = LD->getAddressingMode();
1332  if (AM == ISD::UNINDEXED)
1333    return NULL;
1334
1335  EVT LoadedVT = LD->getMemoryVT();
1336  SDValue Offset, AMOpc;
1337  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1338  unsigned Opcode = 0;
1339  bool Match = false;
1340  if (LoadedVT == MVT::i32 && isPre &&
1341      SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1342    Opcode = ARM::LDR_PRE_IMM;
1343    Match = true;
1344  } else if (LoadedVT == MVT::i32 && !isPre &&
1345      SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1346    Opcode = ARM::LDR_POST_IMM;
1347    Match = true;
1348  } else if (LoadedVT == MVT::i32 &&
1349      SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1350    Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1351    Match = true;
1352
1353  } else if (LoadedVT == MVT::i16 &&
1354             SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1355    Match = true;
1356    Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1357      ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1358      : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1359  } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1360    if (LD->getExtensionType() == ISD::SEXTLOAD) {
1361      if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1362        Match = true;
1363        Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1364      }
1365    } else {
1366      if (isPre &&
1367          SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1368        Match = true;
1369        Opcode = ARM::LDRB_PRE_IMM;
1370      } else if (!isPre &&
1371                  SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1372        Match = true;
1373        Opcode = ARM::LDRB_POST_IMM;
1374      } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1375        Match = true;
1376        Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1377      }
1378    }
1379  }
1380
1381  if (Match) {
1382    if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1383      SDValue Chain = LD->getChain();
1384      SDValue Base = LD->getBasePtr();
1385      SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1386                       CurDAG->getRegister(0, MVT::i32), Chain };
1387      return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1388                                    MVT::i32, MVT::Other, Ops, 5);
1389    } else {
1390      SDValue Chain = LD->getChain();
1391      SDValue Base = LD->getBasePtr();
1392      SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1393                       CurDAG->getRegister(0, MVT::i32), Chain };
1394      return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1395                                    MVT::i32, MVT::Other, Ops, 6);
1396    }
1397  }
1398
1399  return NULL;
1400}
1401
1402SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1403  LoadSDNode *LD = cast<LoadSDNode>(N);
1404  ISD::MemIndexedMode AM = LD->getAddressingMode();
1405  if (AM == ISD::UNINDEXED)
1406    return NULL;
1407
1408  EVT LoadedVT = LD->getMemoryVT();
1409  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1410  SDValue Offset;
1411  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1412  unsigned Opcode = 0;
1413  bool Match = false;
1414  if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1415    switch (LoadedVT.getSimpleVT().SimpleTy) {
1416    case MVT::i32:
1417      Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1418      break;
1419    case MVT::i16:
1420      if (isSExtLd)
1421        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1422      else
1423        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1424      break;
1425    case MVT::i8:
1426    case MVT::i1:
1427      if (isSExtLd)
1428        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1429      else
1430        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1431      break;
1432    default:
1433      return NULL;
1434    }
1435    Match = true;
1436  }
1437
1438  if (Match) {
1439    SDValue Chain = LD->getChain();
1440    SDValue Base = LD->getBasePtr();
1441    SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1442                     CurDAG->getRegister(0, MVT::i32), Chain };
1443    return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1444                                  MVT::Other, Ops, 5);
1445  }
1446
1447  return NULL;
1448}
1449
1450/// PairSRegs - Form a D register from a pair of S registers.
1451///
1452SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1453  DebugLoc dl = V0.getNode()->getDebugLoc();
1454  SDValue RegClass =
1455    CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1456  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1457  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1458  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1459  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1460}
1461
1462/// PairDRegs - Form a quad register from a pair of D registers.
1463///
1464SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1465  DebugLoc dl = V0.getNode()->getDebugLoc();
1466  SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1467  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1468  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1469  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1470  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1471}
1472
1473/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1474///
1475SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1476  DebugLoc dl = V0.getNode()->getDebugLoc();
1477  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1478  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1479  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1480  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1481  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1482}
1483
1484/// QuadSRegs - Form 4 consecutive S registers.
1485///
1486SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1487                                   SDValue V2, SDValue V3) {
1488  DebugLoc dl = V0.getNode()->getDebugLoc();
1489  SDValue RegClass =
1490    CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1491  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1492  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1493  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1494  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1495  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1496                                    V2, SubReg2, V3, SubReg3 };
1497  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1498}
1499
1500/// QuadDRegs - Form 4 consecutive D registers.
1501///
1502SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1503                                   SDValue V2, SDValue V3) {
1504  DebugLoc dl = V0.getNode()->getDebugLoc();
1505  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1506  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1507  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1508  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1509  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1510  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1511                                    V2, SubReg2, V3, SubReg3 };
1512  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1513}
1514
1515/// QuadQRegs - Form 4 consecutive Q registers.
1516///
1517SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1518                                   SDValue V2, SDValue V3) {
1519  DebugLoc dl = V0.getNode()->getDebugLoc();
1520  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1521  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1522  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1523  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1524  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1525  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1526                                    V2, SubReg2, V3, SubReg3 };
1527  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1528}
1529
1530/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1531/// of a NEON VLD or VST instruction.  The supported values depend on the
1532/// number of registers being loaded.
1533SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1534                                       bool is64BitVector) {
1535  unsigned NumRegs = NumVecs;
1536  if (!is64BitVector && NumVecs < 3)
1537    NumRegs *= 2;
1538
1539  unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1540  if (Alignment >= 32 && NumRegs == 4)
1541    Alignment = 32;
1542  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1543    Alignment = 16;
1544  else if (Alignment >= 8)
1545    Alignment = 8;
1546  else
1547    Alignment = 0;
1548
1549  return CurDAG->getTargetConstant(Alignment, MVT::i32);
1550}
1551
1552SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1553                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1554                                   unsigned *QOpcodes1) {
1555  assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1556  DebugLoc dl = N->getDebugLoc();
1557
1558  SDValue MemAddr, Align;
1559  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1560  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1561    return NULL;
1562
1563  SDValue Chain = N->getOperand(0);
1564  EVT VT = N->getValueType(0);
1565  bool is64BitVector = VT.is64BitVector();
1566  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1567
1568  unsigned OpcodeIndex;
1569  switch (VT.getSimpleVT().SimpleTy) {
1570  default: llvm_unreachable("unhandled vld type");
1571    // Double-register operations:
1572  case MVT::v8i8:  OpcodeIndex = 0; break;
1573  case MVT::v4i16: OpcodeIndex = 1; break;
1574  case MVT::v2f32:
1575  case MVT::v2i32: OpcodeIndex = 2; break;
1576  case MVT::v1i64: OpcodeIndex = 3; break;
1577    // Quad-register operations:
1578  case MVT::v16i8: OpcodeIndex = 0; break;
1579  case MVT::v8i16: OpcodeIndex = 1; break;
1580  case MVT::v4f32:
1581  case MVT::v4i32: OpcodeIndex = 2; break;
1582  case MVT::v2i64: OpcodeIndex = 3;
1583    assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1584    break;
1585  }
1586
1587  EVT ResTy;
1588  if (NumVecs == 1)
1589    ResTy = VT;
1590  else {
1591    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1592    if (!is64BitVector)
1593      ResTyElts *= 2;
1594    ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1595  }
1596  std::vector<EVT> ResTys;
1597  ResTys.push_back(ResTy);
1598  if (isUpdating)
1599    ResTys.push_back(MVT::i32);
1600  ResTys.push_back(MVT::Other);
1601
1602  SDValue Pred = getAL(CurDAG);
1603  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1604  SDNode *VLd;
1605  SmallVector<SDValue, 7> Ops;
1606
1607  // Double registers and VLD1/VLD2 quad registers are directly supported.
1608  if (is64BitVector || NumVecs <= 2) {
1609    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1610                    QOpcodes0[OpcodeIndex]);
1611    Ops.push_back(MemAddr);
1612    Ops.push_back(Align);
1613    if (isUpdating) {
1614      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1615      Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1616    }
1617    Ops.push_back(Pred);
1618    Ops.push_back(Reg0);
1619    Ops.push_back(Chain);
1620    VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1621
1622  } else {
1623    // Otherwise, quad registers are loaded with two separate instructions,
1624    // where one loads the even registers and the other loads the odd registers.
1625    EVT AddrTy = MemAddr.getValueType();
1626
1627    // Load the even subregs.  This is always an updating load, so that it
1628    // provides the address to the second load for the odd subregs.
1629    SDValue ImplDef =
1630      SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1631    const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1632    SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1633                                          ResTy, AddrTy, MVT::Other, OpsA, 7);
1634    Chain = SDValue(VLdA, 2);
1635
1636    // Load the odd subregs.
1637    Ops.push_back(SDValue(VLdA, 1));
1638    Ops.push_back(Align);
1639    if (isUpdating) {
1640      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1641      assert(isa<ConstantSDNode>(Inc.getNode()) &&
1642             "only constant post-increment update allowed for VLD3/4");
1643      (void)Inc;
1644      Ops.push_back(Reg0);
1645    }
1646    Ops.push_back(SDValue(VLdA, 0));
1647    Ops.push_back(Pred);
1648    Ops.push_back(Reg0);
1649    Ops.push_back(Chain);
1650    VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1651                                 Ops.data(), Ops.size());
1652  }
1653
1654  // Transfer memoperands.
1655  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1656  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1657  cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1658
1659  if (NumVecs == 1)
1660    return VLd;
1661
1662  // Extract out the subregisters.
1663  SDValue SuperReg = SDValue(VLd, 0);
1664  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1665         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1666  unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1667  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1668    ReplaceUses(SDValue(N, Vec),
1669                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1670  ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1671  if (isUpdating)
1672    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1673  return NULL;
1674}
1675
1676SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1677                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1678                                   unsigned *QOpcodes1) {
1679  assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1680  DebugLoc dl = N->getDebugLoc();
1681
1682  SDValue MemAddr, Align;
1683  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1684  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1685  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1686    return NULL;
1687
1688  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1689  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1690
1691  SDValue Chain = N->getOperand(0);
1692  EVT VT = N->getOperand(Vec0Idx).getValueType();
1693  bool is64BitVector = VT.is64BitVector();
1694  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1695
1696  unsigned OpcodeIndex;
1697  switch (VT.getSimpleVT().SimpleTy) {
1698  default: llvm_unreachable("unhandled vst type");
1699    // Double-register operations:
1700  case MVT::v8i8:  OpcodeIndex = 0; break;
1701  case MVT::v4i16: OpcodeIndex = 1; break;
1702  case MVT::v2f32:
1703  case MVT::v2i32: OpcodeIndex = 2; break;
1704  case MVT::v1i64: OpcodeIndex = 3; break;
1705    // Quad-register operations:
1706  case MVT::v16i8: OpcodeIndex = 0; break;
1707  case MVT::v8i16: OpcodeIndex = 1; break;
1708  case MVT::v4f32:
1709  case MVT::v4i32: OpcodeIndex = 2; break;
1710  case MVT::v2i64: OpcodeIndex = 3;
1711    assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1712    break;
1713  }
1714
1715  std::vector<EVT> ResTys;
1716  if (isUpdating)
1717    ResTys.push_back(MVT::i32);
1718  ResTys.push_back(MVT::Other);
1719
1720  SDValue Pred = getAL(CurDAG);
1721  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1722  SmallVector<SDValue, 7> Ops;
1723
1724  // Double registers and VST1/VST2 quad registers are directly supported.
1725  if (is64BitVector || NumVecs <= 2) {
1726    SDValue SrcReg;
1727    if (NumVecs == 1) {
1728      SrcReg = N->getOperand(Vec0Idx);
1729    } else if (is64BitVector) {
1730      // Form a REG_SEQUENCE to force register allocation.
1731      SDValue V0 = N->getOperand(Vec0Idx + 0);
1732      SDValue V1 = N->getOperand(Vec0Idx + 1);
1733      if (NumVecs == 2)
1734        SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1735      else {
1736        SDValue V2 = N->getOperand(Vec0Idx + 2);
1737        // If it's a vst3, form a quad D-register and leave the last part as
1738        // an undef.
1739        SDValue V3 = (NumVecs == 3)
1740          ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1741          : N->getOperand(Vec0Idx + 3);
1742        SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1743      }
1744    } else {
1745      // Form a QQ register.
1746      SDValue Q0 = N->getOperand(Vec0Idx);
1747      SDValue Q1 = N->getOperand(Vec0Idx + 1);
1748      SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1749    }
1750
1751    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1752                    QOpcodes0[OpcodeIndex]);
1753    Ops.push_back(MemAddr);
1754    Ops.push_back(Align);
1755    if (isUpdating) {
1756      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1757      Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1758    }
1759    Ops.push_back(SrcReg);
1760    Ops.push_back(Pred);
1761    Ops.push_back(Reg0);
1762    Ops.push_back(Chain);
1763    SDNode *VSt =
1764      CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1765
1766    // Transfer memoperands.
1767    cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1768
1769    return VSt;
1770  }
1771
1772  // Otherwise, quad registers are stored with two separate instructions,
1773  // where one stores the even registers and the other stores the odd registers.
1774
1775  // Form the QQQQ REG_SEQUENCE.
1776  SDValue V0 = N->getOperand(Vec0Idx + 0);
1777  SDValue V1 = N->getOperand(Vec0Idx + 1);
1778  SDValue V2 = N->getOperand(Vec0Idx + 2);
1779  SDValue V3 = (NumVecs == 3)
1780    ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1781    : N->getOperand(Vec0Idx + 3);
1782  SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1783
1784  // Store the even D registers.  This is always an updating store, so that it
1785  // provides the address to the second store for the odd subregs.
1786  const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1787  SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1788                                        MemAddr.getValueType(),
1789                                        MVT::Other, OpsA, 7);
1790  cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
1791  Chain = SDValue(VStA, 1);
1792
1793  // Store the odd D registers.
1794  Ops.push_back(SDValue(VStA, 0));
1795  Ops.push_back(Align);
1796  if (isUpdating) {
1797    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1798    assert(isa<ConstantSDNode>(Inc.getNode()) &&
1799           "only constant post-increment update allowed for VST3/4");
1800    (void)Inc;
1801    Ops.push_back(Reg0);
1802  }
1803  Ops.push_back(RegSeq);
1804  Ops.push_back(Pred);
1805  Ops.push_back(Reg0);
1806  Ops.push_back(Chain);
1807  SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1808                                        Ops.data(), Ops.size());
1809  cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
1810  return VStB;
1811}
1812
1813SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1814                                         bool isUpdating, unsigned NumVecs,
1815                                         unsigned *DOpcodes,
1816                                         unsigned *QOpcodes) {
1817  assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1818  DebugLoc dl = N->getDebugLoc();
1819
1820  SDValue MemAddr, Align;
1821  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1822  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1823  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1824    return NULL;
1825
1826  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1827  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1828
1829  SDValue Chain = N->getOperand(0);
1830  unsigned Lane =
1831    cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1832  EVT VT = N->getOperand(Vec0Idx).getValueType();
1833  bool is64BitVector = VT.is64BitVector();
1834
1835  unsigned Alignment = 0;
1836  if (NumVecs != 3) {
1837    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1838    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1839    if (Alignment > NumBytes)
1840      Alignment = NumBytes;
1841    if (Alignment < 8 && Alignment < NumBytes)
1842      Alignment = 0;
1843    // Alignment must be a power of two; make sure of that.
1844    Alignment = (Alignment & -Alignment);
1845    if (Alignment == 1)
1846      Alignment = 0;
1847  }
1848  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1849
1850  unsigned OpcodeIndex;
1851  switch (VT.getSimpleVT().SimpleTy) {
1852  default: llvm_unreachable("unhandled vld/vst lane type");
1853    // Double-register operations:
1854  case MVT::v8i8:  OpcodeIndex = 0; break;
1855  case MVT::v4i16: OpcodeIndex = 1; break;
1856  case MVT::v2f32:
1857  case MVT::v2i32: OpcodeIndex = 2; break;
1858    // Quad-register operations:
1859  case MVT::v8i16: OpcodeIndex = 0; break;
1860  case MVT::v4f32:
1861  case MVT::v4i32: OpcodeIndex = 1; break;
1862  }
1863
1864  std::vector<EVT> ResTys;
1865  if (IsLoad) {
1866    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1867    if (!is64BitVector)
1868      ResTyElts *= 2;
1869    ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1870                                      MVT::i64, ResTyElts));
1871  }
1872  if (isUpdating)
1873    ResTys.push_back(MVT::i32);
1874  ResTys.push_back(MVT::Other);
1875
1876  SDValue Pred = getAL(CurDAG);
1877  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1878
1879  SmallVector<SDValue, 8> Ops;
1880  Ops.push_back(MemAddr);
1881  Ops.push_back(Align);
1882  if (isUpdating) {
1883    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1884    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1885  }
1886
1887  SDValue SuperReg;
1888  SDValue V0 = N->getOperand(Vec0Idx + 0);
1889  SDValue V1 = N->getOperand(Vec0Idx + 1);
1890  if (NumVecs == 2) {
1891    if (is64BitVector)
1892      SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1893    else
1894      SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1895  } else {
1896    SDValue V2 = N->getOperand(Vec0Idx + 2);
1897    SDValue V3 = (NumVecs == 3)
1898      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1899      : N->getOperand(Vec0Idx + 3);
1900    if (is64BitVector)
1901      SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1902    else
1903      SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1904  }
1905  Ops.push_back(SuperReg);
1906  Ops.push_back(getI32Imm(Lane));
1907  Ops.push_back(Pred);
1908  Ops.push_back(Reg0);
1909  Ops.push_back(Chain);
1910
1911  unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1912                                  QOpcodes[OpcodeIndex]);
1913  SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1914                                         Ops.data(), Ops.size());
1915  cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
1916  if (!IsLoad)
1917    return VLdLn;
1918
1919  // Extract the subregisters.
1920  SuperReg = SDValue(VLdLn, 0);
1921  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1922         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1923  unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1924  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1925    ReplaceUses(SDValue(N, Vec),
1926                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1927  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1928  if (isUpdating)
1929    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1930  return NULL;
1931}
1932
1933SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
1934                                      unsigned NumVecs, unsigned *Opcodes) {
1935  assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1936  DebugLoc dl = N->getDebugLoc();
1937
1938  SDValue MemAddr, Align;
1939  if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
1940    return NULL;
1941
1942  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1943  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1944
1945  SDValue Chain = N->getOperand(0);
1946  EVT VT = N->getValueType(0);
1947
1948  unsigned Alignment = 0;
1949  if (NumVecs != 3) {
1950    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1951    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1952    if (Alignment > NumBytes)
1953      Alignment = NumBytes;
1954    if (Alignment < 8 && Alignment < NumBytes)
1955      Alignment = 0;
1956    // Alignment must be a power of two; make sure of that.
1957    Alignment = (Alignment & -Alignment);
1958    if (Alignment == 1)
1959      Alignment = 0;
1960  }
1961  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1962
1963  unsigned OpcodeIndex;
1964  switch (VT.getSimpleVT().SimpleTy) {
1965  default: llvm_unreachable("unhandled vld-dup type");
1966  case MVT::v8i8:  OpcodeIndex = 0; break;
1967  case MVT::v4i16: OpcodeIndex = 1; break;
1968  case MVT::v2f32:
1969  case MVT::v2i32: OpcodeIndex = 2; break;
1970  }
1971
1972  SDValue Pred = getAL(CurDAG);
1973  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1974  SDValue SuperReg;
1975  unsigned Opc = Opcodes[OpcodeIndex];
1976  SmallVector<SDValue, 6> Ops;
1977  Ops.push_back(MemAddr);
1978  Ops.push_back(Align);
1979  if (isUpdating) {
1980    SDValue Inc = N->getOperand(2);
1981    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1982  }
1983  Ops.push_back(Pred);
1984  Ops.push_back(Reg0);
1985  Ops.push_back(Chain);
1986
1987  unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1988  std::vector<EVT> ResTys;
1989  ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
1990  if (isUpdating)
1991    ResTys.push_back(MVT::i32);
1992  ResTys.push_back(MVT::Other);
1993  SDNode *VLdDup =
1994    CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1995  cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
1996  SuperReg = SDValue(VLdDup, 0);
1997
1998  // Extract the subregisters.
1999  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2000  unsigned SubIdx = ARM::dsub_0;
2001  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2002    ReplaceUses(SDValue(N, Vec),
2003                CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2004  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2005  if (isUpdating)
2006    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2007  return NULL;
2008}
2009
2010SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2011                                    unsigned Opc) {
2012  assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2013  DebugLoc dl = N->getDebugLoc();
2014  EVT VT = N->getValueType(0);
2015  unsigned FirstTblReg = IsExt ? 2 : 1;
2016
2017  // Form a REG_SEQUENCE to force register allocation.
2018  SDValue RegSeq;
2019  SDValue V0 = N->getOperand(FirstTblReg + 0);
2020  SDValue V1 = N->getOperand(FirstTblReg + 1);
2021  if (NumVecs == 2)
2022    RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2023  else {
2024    SDValue V2 = N->getOperand(FirstTblReg + 2);
2025    // If it's a vtbl3, form a quad D-register and leave the last part as
2026    // an undef.
2027    SDValue V3 = (NumVecs == 3)
2028      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2029      : N->getOperand(FirstTblReg + 3);
2030    RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
2031  }
2032
2033  SmallVector<SDValue, 6> Ops;
2034  if (IsExt)
2035    Ops.push_back(N->getOperand(1));
2036  Ops.push_back(RegSeq);
2037  Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2038  Ops.push_back(getAL(CurDAG)); // predicate
2039  Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2040  return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
2041}
2042
2043SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2044                                                     bool isSigned) {
2045  if (!Subtarget->hasV6T2Ops())
2046    return NULL;
2047
2048  unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2049    : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2050
2051
2052  // For unsigned extracts, check for a shift right and mask
2053  unsigned And_imm = 0;
2054  if (N->getOpcode() == ISD::AND) {
2055    if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2056
2057      // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2058      if (And_imm & (And_imm + 1))
2059        return NULL;
2060
2061      unsigned Srl_imm = 0;
2062      if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2063                                Srl_imm)) {
2064        assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2065
2066        // Note: The width operand is encoded as width-1.
2067        unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2068        unsigned LSB = Srl_imm;
2069        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2070        SDValue Ops[] = { N->getOperand(0).getOperand(0),
2071                          CurDAG->getTargetConstant(LSB, MVT::i32),
2072                          CurDAG->getTargetConstant(Width, MVT::i32),
2073          getAL(CurDAG), Reg0 };
2074        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2075      }
2076    }
2077    return NULL;
2078  }
2079
2080  // Otherwise, we're looking for a shift of a shift
2081  unsigned Shl_imm = 0;
2082  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2083    assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2084    unsigned Srl_imm = 0;
2085    if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2086      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2087      // Note: The width operand is encoded as width-1.
2088      unsigned Width = 32 - Srl_imm - 1;
2089      int LSB = Srl_imm - Shl_imm;
2090      if (LSB < 0)
2091        return NULL;
2092      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2093      SDValue Ops[] = { N->getOperand(0).getOperand(0),
2094                        CurDAG->getTargetConstant(LSB, MVT::i32),
2095                        CurDAG->getTargetConstant(Width, MVT::i32),
2096                        getAL(CurDAG), Reg0 };
2097      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2098    }
2099  }
2100  return NULL;
2101}
2102
2103SDNode *ARMDAGToDAGISel::
2104SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2105                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2106  SDValue CPTmp0;
2107  SDValue CPTmp1;
2108  if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
2109    unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
2110    unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
2111    unsigned Opc = 0;
2112    switch (SOShOp) {
2113    case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
2114    case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
2115    case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
2116    case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
2117    default:
2118      llvm_unreachable("Unknown so_reg opcode!");
2119      break;
2120    }
2121    SDValue SOShImm =
2122      CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
2123    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2124    SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2125    return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2126  }
2127  return 0;
2128}
2129
2130SDNode *ARMDAGToDAGISel::
2131SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2132                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2133  SDValue CPTmp0;
2134  SDValue CPTmp1;
2135  SDValue CPTmp2;
2136  if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
2137    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2138    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
2139    return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6);
2140  }
2141
2142  if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2143    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2144    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2145    return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
2146  }
2147  return 0;
2148}
2149
2150SDNode *ARMDAGToDAGISel::
2151SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2152                  ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2153  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2154  if (!T)
2155    return 0;
2156
2157  unsigned Opc = 0;
2158  unsigned TrueImm = T->getZExtValue();
2159  if (is_t2_so_imm(TrueImm)) {
2160    Opc = ARM::t2MOVCCi;
2161  } else if (TrueImm <= 0xffff) {
2162    Opc = ARM::t2MOVCCi16;
2163  } else if (is_t2_so_imm_not(TrueImm)) {
2164    TrueImm = ~TrueImm;
2165    Opc = ARM::t2MVNCCi;
2166  } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2167    // Large immediate.
2168    Opc = ARM::t2MOVCCi32imm;
2169  }
2170
2171  if (Opc) {
2172    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2173    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2174    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2175    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2176  }
2177
2178  return 0;
2179}
2180
2181SDNode *ARMDAGToDAGISel::
2182SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2183                   ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2184  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2185  if (!T)
2186    return 0;
2187
2188  unsigned Opc = 0;
2189  unsigned TrueImm = T->getZExtValue();
2190  bool isSoImm = is_so_imm(TrueImm);
2191  if (isSoImm) {
2192    Opc = ARM::MOVCCi;
2193  } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2194    Opc = ARM::MOVCCi16;
2195  } else if (is_so_imm_not(TrueImm)) {
2196    TrueImm = ~TrueImm;
2197    Opc = ARM::MVNCCi;
2198  } else if (TrueVal.getNode()->hasOneUse() &&
2199             (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2200    // Large immediate.
2201    Opc = ARM::MOVCCi32imm;
2202  }
2203
2204  if (Opc) {
2205    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2206    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2207    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2208    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2209  }
2210
2211  return 0;
2212}
2213
2214SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2215  EVT VT = N->getValueType(0);
2216  SDValue FalseVal = N->getOperand(0);
2217  SDValue TrueVal  = N->getOperand(1);
2218  SDValue CC = N->getOperand(2);
2219  SDValue CCR = N->getOperand(3);
2220  SDValue InFlag = N->getOperand(4);
2221  assert(CC.getOpcode() == ISD::Constant);
2222  assert(CCR.getOpcode() == ISD::Register);
2223  ARMCC::CondCodes CCVal =
2224    (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2225
2226  if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2227    // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2228    // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2229    // Pattern complexity = 18  cost = 1  size = 0
2230    SDValue CPTmp0;
2231    SDValue CPTmp1;
2232    SDValue CPTmp2;
2233    if (Subtarget->isThumb()) {
2234      SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2235                                        CCVal, CCR, InFlag);
2236      if (!Res)
2237        Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2238                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2239      if (Res)
2240        return Res;
2241    } else {
2242      SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2243                                         CCVal, CCR, InFlag);
2244      if (!Res)
2245        Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2246                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2247      if (Res)
2248        return Res;
2249    }
2250
2251    // Pattern: (ARMcmov:i32 GPR:i32:$false,
2252    //             (imm:i32)<<P:Pred_so_imm>>:$true,
2253    //             (imm:i32):$cc)
2254    // Emits: (MOVCCi:i32 GPR:i32:$false,
2255    //           (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2256    // Pattern complexity = 10  cost = 1  size = 0
2257    if (Subtarget->isThumb()) {
2258      SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2259                                        CCVal, CCR, InFlag);
2260      if (!Res)
2261        Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2262                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2263      if (Res)
2264        return Res;
2265    } else {
2266      SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2267                                         CCVal, CCR, InFlag);
2268      if (!Res)
2269        Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2270                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2271      if (Res)
2272        return Res;
2273    }
2274  }
2275
2276  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2277  // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2278  // Pattern complexity = 6  cost = 1  size = 0
2279  //
2280  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2281  // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2282  // Pattern complexity = 6  cost = 11  size = 0
2283  //
2284  // Also VMOVScc and VMOVDcc.
2285  SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2286  SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2287  unsigned Opc = 0;
2288  switch (VT.getSimpleVT().SimpleTy) {
2289  default: assert(false && "Illegal conditional move type!");
2290    break;
2291  case MVT::i32:
2292    Opc = Subtarget->isThumb()
2293      ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2294      : ARM::MOVCCr;
2295    break;
2296  case MVT::f32:
2297    Opc = ARM::VMOVScc;
2298    break;
2299  case MVT::f64:
2300    Opc = ARM::VMOVDcc;
2301    break;
2302  }
2303  return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2304}
2305
2306/// Target-specific DAG combining for ISD::XOR.
2307/// Target-independent combining lowers SELECT_CC nodes of the form
2308/// select_cc setg[ge] X,  0,  X, -X
2309/// select_cc setgt    X, -1,  X, -X
2310/// select_cc setl[te] X,  0, -X,  X
2311/// select_cc setlt    X,  1, -X,  X
2312/// which represent Integer ABS into:
2313/// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2314/// ARM instruction selection detects the latter and matches it to
2315/// ARM::ABS or ARM::t2ABS machine node.
2316SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2317  SDValue XORSrc0 = N->getOperand(0);
2318  SDValue XORSrc1 = N->getOperand(1);
2319  DebugLoc DL = N->getDebugLoc();
2320  EVT VT = N->getValueType(0);
2321
2322  if (DisableARMIntABS)
2323    return NULL;
2324
2325  if (Subtarget->isThumb1Only())
2326    return NULL;
2327
2328  if (XORSrc0.getOpcode() != ISD::ADD ||
2329    XORSrc1.getOpcode() != ISD::SRA)
2330    return NULL;
2331
2332  SDValue ADDSrc0 = XORSrc0.getOperand(0);
2333  SDValue ADDSrc1 = XORSrc0.getOperand(1);
2334  SDValue SRASrc0 = XORSrc1.getOperand(0);
2335  SDValue SRASrc1 = XORSrc1.getOperand(1);
2336  ConstantSDNode *SRAConstant =  dyn_cast<ConstantSDNode>(SRASrc1);
2337  EVT XType = SRASrc0.getValueType();
2338  unsigned Size = XType.getSizeInBits() - 1;
2339
2340  if (ADDSrc1 == XORSrc1  &&
2341      ADDSrc0 == SRASrc0 &&
2342      XType.isInteger() &&
2343      SRAConstant != NULL &&
2344      Size == SRAConstant->getZExtValue()) {
2345
2346    unsigned Opcode = ARM::ABS;
2347    if (Subtarget->isThumb2())
2348      Opcode = ARM::t2ABS;
2349
2350    return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2351  }
2352
2353  return NULL;
2354}
2355
2356SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2357  // The only time a CONCAT_VECTORS operation can have legal types is when
2358  // two 64-bit vectors are concatenated to a 128-bit vector.
2359  EVT VT = N->getValueType(0);
2360  if (!VT.is128BitVector() || N->getNumOperands() != 2)
2361    llvm_unreachable("unexpected CONCAT_VECTORS");
2362  return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2363}
2364
2365SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
2366  SmallVector<SDValue, 6> Ops;
2367  Ops.push_back(Node->getOperand(1)); // Ptr
2368  Ops.push_back(Node->getOperand(2)); // Low part of Val1
2369  Ops.push_back(Node->getOperand(3)); // High part of Val1
2370  if (Opc == ARM::ATOMCMPXCHG6432) {
2371    Ops.push_back(Node->getOperand(4)); // Low part of Val2
2372    Ops.push_back(Node->getOperand(5)); // High part of Val2
2373  }
2374  Ops.push_back(Node->getOperand(0)); // Chain
2375  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2376  MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
2377  SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
2378                                           MVT::i32, MVT::i32, MVT::Other,
2379                                           Ops.data() ,Ops.size());
2380  cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
2381  return ResNode;
2382}
2383
2384SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2385  DebugLoc dl = N->getDebugLoc();
2386
2387  if (N->isMachineOpcode())
2388    return NULL;   // Already selected.
2389
2390  switch (N->getOpcode()) {
2391  default: break;
2392  case ISD::XOR: {
2393    // Select special operations if XOR node forms integer ABS pattern
2394    SDNode *ResNode = SelectABSOp(N);
2395    if (ResNode)
2396      return ResNode;
2397    // Other cases are autogenerated.
2398    break;
2399  }
2400  case ISD::Constant: {
2401    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2402    bool UseCP = true;
2403    if (Subtarget->hasThumb2())
2404      // Thumb2-aware targets have the MOVT instruction, so all immediates can
2405      // be done with MOV + MOVT, at worst.
2406      UseCP = 0;
2407    else {
2408      if (Subtarget->isThumb()) {
2409        UseCP = (Val > 255 &&                          // MOV
2410                 ~Val > 255 &&                         // MOV + MVN
2411                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
2412      } else
2413        UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
2414                 ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
2415                 !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
2416    }
2417
2418    if (UseCP) {
2419      SDValue CPIdx =
2420        CurDAG->getTargetConstantPool(ConstantInt::get(
2421                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
2422                                      TLI.getPointerTy());
2423
2424      SDNode *ResNode;
2425      if (Subtarget->isThumb1Only()) {
2426        SDValue Pred = getAL(CurDAG);
2427        SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2428        SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2429        ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2430                                         Ops, 4);
2431      } else {
2432        SDValue Ops[] = {
2433          CPIdx,
2434          CurDAG->getTargetConstant(0, MVT::i32),
2435          getAL(CurDAG),
2436          CurDAG->getRegister(0, MVT::i32),
2437          CurDAG->getEntryNode()
2438        };
2439        ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2440                                       Ops, 5);
2441      }
2442      ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2443      return NULL;
2444    }
2445
2446    // Other cases are autogenerated.
2447    break;
2448  }
2449  case ISD::FrameIndex: {
2450    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2451    int FI = cast<FrameIndexSDNode>(N)->getIndex();
2452    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2453    if (Subtarget->isThumb1Only()) {
2454      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2455                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2456      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2457    } else {
2458      unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2459                      ARM::t2ADDri : ARM::ADDri);
2460      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2461                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2462                        CurDAG->getRegister(0, MVT::i32) };
2463      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2464    }
2465  }
2466  case ISD::SRL:
2467    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2468      return I;
2469    break;
2470  case ISD::SRA:
2471    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2472      return I;
2473    break;
2474  case ISD::MUL:
2475    if (Subtarget->isThumb1Only())
2476      break;
2477    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2478      unsigned RHSV = C->getZExtValue();
2479      if (!RHSV) break;
2480      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
2481        unsigned ShImm = Log2_32(RHSV-1);
2482        if (ShImm >= 32)
2483          break;
2484        SDValue V = N->getOperand(0);
2485        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2486        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2487        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2488        if (Subtarget->isThumb()) {
2489          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2490          return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2491        } else {
2492          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2493          return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2494        }
2495      }
2496      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
2497        unsigned ShImm = Log2_32(RHSV+1);
2498        if (ShImm >= 32)
2499          break;
2500        SDValue V = N->getOperand(0);
2501        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2502        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2503        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2504        if (Subtarget->isThumb()) {
2505          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2506          return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2507        } else {
2508          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2509          return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2510        }
2511      }
2512    }
2513    break;
2514  case ISD::AND: {
2515    // Check for unsigned bitfield extract
2516    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2517      return I;
2518
2519    // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2520    // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2521    // are entirely contributed by c2 and lower 16-bits are entirely contributed
2522    // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2523    // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2524    EVT VT = N->getValueType(0);
2525    if (VT != MVT::i32)
2526      break;
2527    unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2528      ? ARM::t2MOVTi16
2529      : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2530    if (!Opc)
2531      break;
2532    SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2533    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2534    if (!N1C)
2535      break;
2536    if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2537      SDValue N2 = N0.getOperand(1);
2538      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2539      if (!N2C)
2540        break;
2541      unsigned N1CVal = N1C->getZExtValue();
2542      unsigned N2CVal = N2C->getZExtValue();
2543      if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2544          (N1CVal & 0xffffU) == 0xffffU &&
2545          (N2CVal & 0xffffU) == 0x0U) {
2546        SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2547                                                  MVT::i32);
2548        SDValue Ops[] = { N0.getOperand(0), Imm16,
2549                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2550        return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2551      }
2552    }
2553    break;
2554  }
2555  case ARMISD::VMOVRRD:
2556    return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2557                                  N->getOperand(0), getAL(CurDAG),
2558                                  CurDAG->getRegister(0, MVT::i32));
2559  case ISD::UMUL_LOHI: {
2560    if (Subtarget->isThumb1Only())
2561      break;
2562    if (Subtarget->isThumb()) {
2563      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2564                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2565                        CurDAG->getRegister(0, MVT::i32) };
2566      return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2567    } else {
2568      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2569                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2570                        CurDAG->getRegister(0, MVT::i32) };
2571      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2572                                    ARM::UMULL : ARM::UMULLv5,
2573                                    dl, MVT::i32, MVT::i32, Ops, 5);
2574    }
2575  }
2576  case ISD::SMUL_LOHI: {
2577    if (Subtarget->isThumb1Only())
2578      break;
2579    if (Subtarget->isThumb()) {
2580      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2581                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2582      return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2583    } else {
2584      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2585                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2586                        CurDAG->getRegister(0, MVT::i32) };
2587      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2588                                    ARM::SMULL : ARM::SMULLv5,
2589                                    dl, MVT::i32, MVT::i32, Ops, 5);
2590    }
2591  }
2592  case ISD::LOAD: {
2593    SDNode *ResNode = 0;
2594    if (Subtarget->isThumb() && Subtarget->hasThumb2())
2595      ResNode = SelectT2IndexedLoad(N);
2596    else
2597      ResNode = SelectARMIndexedLoad(N);
2598    if (ResNode)
2599      return ResNode;
2600    // Other cases are autogenerated.
2601    break;
2602  }
2603  case ARMISD::BRCOND: {
2604    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2605    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2606    // Pattern complexity = 6  cost = 1  size = 0
2607
2608    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2609    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2610    // Pattern complexity = 6  cost = 1  size = 0
2611
2612    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2613    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2614    // Pattern complexity = 6  cost = 1  size = 0
2615
2616    unsigned Opc = Subtarget->isThumb() ?
2617      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2618    SDValue Chain = N->getOperand(0);
2619    SDValue N1 = N->getOperand(1);
2620    SDValue N2 = N->getOperand(2);
2621    SDValue N3 = N->getOperand(3);
2622    SDValue InFlag = N->getOperand(4);
2623    assert(N1.getOpcode() == ISD::BasicBlock);
2624    assert(N2.getOpcode() == ISD::Constant);
2625    assert(N3.getOpcode() == ISD::Register);
2626
2627    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2628                               cast<ConstantSDNode>(N2)->getZExtValue()),
2629                               MVT::i32);
2630    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2631    SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2632                                             MVT::Glue, Ops, 5);
2633    Chain = SDValue(ResNode, 0);
2634    if (N->getNumValues() == 2) {
2635      InFlag = SDValue(ResNode, 1);
2636      ReplaceUses(SDValue(N, 1), InFlag);
2637    }
2638    ReplaceUses(SDValue(N, 0),
2639                SDValue(Chain.getNode(), Chain.getResNo()));
2640    return NULL;
2641  }
2642  case ARMISD::CMOV:
2643    return SelectCMOVOp(N);
2644  case ARMISD::VZIP: {
2645    unsigned Opc = 0;
2646    EVT VT = N->getValueType(0);
2647    switch (VT.getSimpleVT().SimpleTy) {
2648    default: return NULL;
2649    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
2650    case MVT::v4i16: Opc = ARM::VZIPd16; break;
2651    case MVT::v2f32:
2652    case MVT::v2i32: Opc = ARM::VZIPd32; break;
2653    case MVT::v16i8: Opc = ARM::VZIPq8; break;
2654    case MVT::v8i16: Opc = ARM::VZIPq16; break;
2655    case MVT::v4f32:
2656    case MVT::v4i32: Opc = ARM::VZIPq32; break;
2657    }
2658    SDValue Pred = getAL(CurDAG);
2659    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2660    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2661    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2662  }
2663  case ARMISD::VUZP: {
2664    unsigned Opc = 0;
2665    EVT VT = N->getValueType(0);
2666    switch (VT.getSimpleVT().SimpleTy) {
2667    default: return NULL;
2668    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
2669    case MVT::v4i16: Opc = ARM::VUZPd16; break;
2670    case MVT::v2f32:
2671    case MVT::v2i32: Opc = ARM::VUZPd32; break;
2672    case MVT::v16i8: Opc = ARM::VUZPq8; break;
2673    case MVT::v8i16: Opc = ARM::VUZPq16; break;
2674    case MVT::v4f32:
2675    case MVT::v4i32: Opc = ARM::VUZPq32; break;
2676    }
2677    SDValue Pred = getAL(CurDAG);
2678    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2679    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2680    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2681  }
2682  case ARMISD::VTRN: {
2683    unsigned Opc = 0;
2684    EVT VT = N->getValueType(0);
2685    switch (VT.getSimpleVT().SimpleTy) {
2686    default: return NULL;
2687    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
2688    case MVT::v4i16: Opc = ARM::VTRNd16; break;
2689    case MVT::v2f32:
2690    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2691    case MVT::v16i8: Opc = ARM::VTRNq8; break;
2692    case MVT::v8i16: Opc = ARM::VTRNq16; break;
2693    case MVT::v4f32:
2694    case MVT::v4i32: Opc = ARM::VTRNq32; break;
2695    }
2696    SDValue Pred = getAL(CurDAG);
2697    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2698    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2699    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2700  }
2701  case ARMISD::BUILD_VECTOR: {
2702    EVT VecVT = N->getValueType(0);
2703    EVT EltVT = VecVT.getVectorElementType();
2704    unsigned NumElts = VecVT.getVectorNumElements();
2705    if (EltVT == MVT::f64) {
2706      assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2707      return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2708    }
2709    assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2710    if (NumElts == 2)
2711      return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2712    assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2713    return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2714                     N->getOperand(2), N->getOperand(3));
2715  }
2716
2717  case ARMISD::VLD2DUP: {
2718    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2719                           ARM::VLD2DUPd32Pseudo };
2720    return SelectVLDDup(N, false, 2, Opcodes);
2721  }
2722
2723  case ARMISD::VLD3DUP: {
2724    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2725                           ARM::VLD3DUPd32Pseudo };
2726    return SelectVLDDup(N, false, 3, Opcodes);
2727  }
2728
2729  case ARMISD::VLD4DUP: {
2730    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2731                           ARM::VLD4DUPd32Pseudo };
2732    return SelectVLDDup(N, false, 4, Opcodes);
2733  }
2734
2735  case ARMISD::VLD2DUP_UPD: {
2736    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd16Pseudo_UPD,
2737                           ARM::VLD2DUPd32Pseudo_UPD };
2738    return SelectVLDDup(N, true, 2, Opcodes);
2739  }
2740
2741  case ARMISD::VLD3DUP_UPD: {
2742    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd16Pseudo_UPD,
2743                           ARM::VLD3DUPd32Pseudo_UPD };
2744    return SelectVLDDup(N, true, 3, Opcodes);
2745  }
2746
2747  case ARMISD::VLD4DUP_UPD: {
2748    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd16Pseudo_UPD,
2749                           ARM::VLD4DUPd32Pseudo_UPD };
2750    return SelectVLDDup(N, true, 4, Opcodes);
2751  }
2752
2753  case ARMISD::VLD1_UPD: {
2754    unsigned DOpcodes[] = { ARM::VLD1d8_UPD, ARM::VLD1d16_UPD,
2755                            ARM::VLD1d32_UPD, ARM::VLD1d64_UPD };
2756    unsigned QOpcodes[] = { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q16Pseudo_UPD,
2757                            ARM::VLD1q32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2758    return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2759  }
2760
2761  case ARMISD::VLD2_UPD: {
2762    unsigned DOpcodes[] = { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d16Pseudo_UPD,
2763                            ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2764    unsigned QOpcodes[] = { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q16Pseudo_UPD,
2765                            ARM::VLD2q32Pseudo_UPD };
2766    return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2767  }
2768
2769  case ARMISD::VLD3_UPD: {
2770    unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2771                            ARM::VLD3d32Pseudo_UPD, ARM::VLD1d64TPseudo_UPD };
2772    unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2773                             ARM::VLD3q16Pseudo_UPD,
2774                             ARM::VLD3q32Pseudo_UPD };
2775    unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2776                             ARM::VLD3q16oddPseudo_UPD,
2777                             ARM::VLD3q32oddPseudo_UPD };
2778    return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2779  }
2780
2781  case ARMISD::VLD4_UPD: {
2782    unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2783                            ARM::VLD4d32Pseudo_UPD, ARM::VLD1d64QPseudo_UPD };
2784    unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2785                             ARM::VLD4q16Pseudo_UPD,
2786                             ARM::VLD4q32Pseudo_UPD };
2787    unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2788                             ARM::VLD4q16oddPseudo_UPD,
2789                             ARM::VLD4q32oddPseudo_UPD };
2790    return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2791  }
2792
2793  case ARMISD::VLD2LN_UPD: {
2794    unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd16Pseudo_UPD,
2795                            ARM::VLD2LNd32Pseudo_UPD };
2796    unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2797                            ARM::VLD2LNq32Pseudo_UPD };
2798    return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2799  }
2800
2801  case ARMISD::VLD3LN_UPD: {
2802    unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd16Pseudo_UPD,
2803                            ARM::VLD3LNd32Pseudo_UPD };
2804    unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2805                            ARM::VLD3LNq32Pseudo_UPD };
2806    return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2807  }
2808
2809  case ARMISD::VLD4LN_UPD: {
2810    unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd16Pseudo_UPD,
2811                            ARM::VLD4LNd32Pseudo_UPD };
2812    unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2813                            ARM::VLD4LNq32Pseudo_UPD };
2814    return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2815  }
2816
2817  case ARMISD::VST1_UPD: {
2818    unsigned DOpcodes[] = { ARM::VST1d8_UPD, ARM::VST1d16_UPD,
2819                            ARM::VST1d32_UPD, ARM::VST1d64_UPD };
2820    unsigned QOpcodes[] = { ARM::VST1q8Pseudo_UPD, ARM::VST1q16Pseudo_UPD,
2821                            ARM::VST1q32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2822    return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2823  }
2824
2825  case ARMISD::VST2_UPD: {
2826    unsigned DOpcodes[] = { ARM::VST2d8Pseudo_UPD, ARM::VST2d16Pseudo_UPD,
2827                            ARM::VST2d32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2828    unsigned QOpcodes[] = { ARM::VST2q8Pseudo_UPD, ARM::VST2q16Pseudo_UPD,
2829                            ARM::VST2q32Pseudo_UPD };
2830    return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2831  }
2832
2833  case ARMISD::VST3_UPD: {
2834    unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
2835                            ARM::VST3d32Pseudo_UPD, ARM::VST1d64TPseudo_UPD };
2836    unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2837                             ARM::VST3q16Pseudo_UPD,
2838                             ARM::VST3q32Pseudo_UPD };
2839    unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2840                             ARM::VST3q16oddPseudo_UPD,
2841                             ARM::VST3q32oddPseudo_UPD };
2842    return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2843  }
2844
2845  case ARMISD::VST4_UPD: {
2846    unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
2847                            ARM::VST4d32Pseudo_UPD, ARM::VST1d64QPseudo_UPD };
2848    unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2849                             ARM::VST4q16Pseudo_UPD,
2850                             ARM::VST4q32Pseudo_UPD };
2851    unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2852                             ARM::VST4q16oddPseudo_UPD,
2853                             ARM::VST4q32oddPseudo_UPD };
2854    return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2855  }
2856
2857  case ARMISD::VST2LN_UPD: {
2858    unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd16Pseudo_UPD,
2859                            ARM::VST2LNd32Pseudo_UPD };
2860    unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2861                            ARM::VST2LNq32Pseudo_UPD };
2862    return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2863  }
2864
2865  case ARMISD::VST3LN_UPD: {
2866    unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd16Pseudo_UPD,
2867                            ARM::VST3LNd32Pseudo_UPD };
2868    unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2869                            ARM::VST3LNq32Pseudo_UPD };
2870    return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2871  }
2872
2873  case ARMISD::VST4LN_UPD: {
2874    unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd16Pseudo_UPD,
2875                            ARM::VST4LNd32Pseudo_UPD };
2876    unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2877                            ARM::VST4LNq32Pseudo_UPD };
2878    return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2879  }
2880
2881  case ISD::INTRINSIC_VOID:
2882  case ISD::INTRINSIC_W_CHAIN: {
2883    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2884    switch (IntNo) {
2885    default:
2886      break;
2887
2888    case Intrinsic::arm_ldrexd: {
2889      SDValue MemAddr = N->getOperand(2);
2890      DebugLoc dl = N->getDebugLoc();
2891      SDValue Chain = N->getOperand(0);
2892
2893      unsigned NewOpc = ARM::LDREXD;
2894      if (Subtarget->isThumb() && Subtarget->hasThumb2())
2895        NewOpc = ARM::t2LDREXD;
2896
2897      // arm_ldrexd returns a i64 value in {i32, i32}
2898      std::vector<EVT> ResTys;
2899      ResTys.push_back(MVT::i32);
2900      ResTys.push_back(MVT::i32);
2901      ResTys.push_back(MVT::Other);
2902
2903      // place arguments in the right order
2904      SmallVector<SDValue, 7> Ops;
2905      Ops.push_back(MemAddr);
2906      Ops.push_back(getAL(CurDAG));
2907      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2908      Ops.push_back(Chain);
2909      SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
2910                                          Ops.size());
2911      // Transfer memoperands.
2912      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2913      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2914      cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
2915
2916      // Until there's support for specifing explicit register constraints
2917      // like the use of even/odd register pair, hardcode ldrexd to always
2918      // use the pair [R0, R1] to hold the load result.
2919      Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R0,
2920                                   SDValue(Ld, 0), SDValue(0,0));
2921      Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R1,
2922                                   SDValue(Ld, 1), Chain.getValue(1));
2923
2924      // Remap uses.
2925      SDValue Glue = Chain.getValue(1);
2926      if (!SDValue(N, 0).use_empty()) {
2927        SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2928                                                ARM::R0, MVT::i32, Glue);
2929        Glue = Result.getValue(2);
2930        ReplaceUses(SDValue(N, 0), Result);
2931      }
2932      if (!SDValue(N, 1).use_empty()) {
2933        SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2934                                                ARM::R1, MVT::i32, Glue);
2935        Glue = Result.getValue(2);
2936        ReplaceUses(SDValue(N, 1), Result);
2937      }
2938
2939      ReplaceUses(SDValue(N, 2), SDValue(Ld, 2));
2940      return NULL;
2941    }
2942
2943    case Intrinsic::arm_strexd: {
2944      DebugLoc dl = N->getDebugLoc();
2945      SDValue Chain = N->getOperand(0);
2946      SDValue Val0 = N->getOperand(2);
2947      SDValue Val1 = N->getOperand(3);
2948      SDValue MemAddr = N->getOperand(4);
2949
2950      // Until there's support for specifing explicit register constraints
2951      // like the use of even/odd register pair, hardcode strexd to always
2952      // use the pair [R2, R3] to hold the i64 (i32, i32) value to be stored.
2953      Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R2, Val0,
2954                                   SDValue(0, 0));
2955      Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R3, Val1, Chain.getValue(1));
2956
2957      SDValue Glue = Chain.getValue(1);
2958      Val0 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2959                                    ARM::R2, MVT::i32, Glue);
2960      Glue = Val0.getValue(1);
2961      Val1 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2962                                    ARM::R3, MVT::i32, Glue);
2963
2964      // Store exclusive double return a i32 value which is the return status
2965      // of the issued store.
2966      std::vector<EVT> ResTys;
2967      ResTys.push_back(MVT::i32);
2968      ResTys.push_back(MVT::Other);
2969
2970      // place arguments in the right order
2971      SmallVector<SDValue, 7> Ops;
2972      Ops.push_back(Val0);
2973      Ops.push_back(Val1);
2974      Ops.push_back(MemAddr);
2975      Ops.push_back(getAL(CurDAG));
2976      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2977      Ops.push_back(Chain);
2978
2979      unsigned NewOpc = ARM::STREXD;
2980      if (Subtarget->isThumb() && Subtarget->hasThumb2())
2981        NewOpc = ARM::t2STREXD;
2982
2983      SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
2984                                          Ops.size());
2985      // Transfer memoperands.
2986      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2987      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2988      cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
2989
2990      return St;
2991    }
2992
2993    case Intrinsic::arm_neon_vld1: {
2994      unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2995                              ARM::VLD1d32, ARM::VLD1d64 };
2996      unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2997                              ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2998      return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
2999    }
3000
3001    case Intrinsic::arm_neon_vld2: {
3002      unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
3003                              ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
3004      unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3005                              ARM::VLD2q32Pseudo };
3006      return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
3007    }
3008
3009    case Intrinsic::arm_neon_vld3: {
3010      unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
3011                              ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
3012      unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3013                               ARM::VLD3q16Pseudo_UPD,
3014                               ARM::VLD3q32Pseudo_UPD };
3015      unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3016                               ARM::VLD3q16oddPseudo,
3017                               ARM::VLD3q32oddPseudo };
3018      return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3019    }
3020
3021    case Intrinsic::arm_neon_vld4: {
3022      unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
3023                              ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
3024      unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3025                               ARM::VLD4q16Pseudo_UPD,
3026                               ARM::VLD4q32Pseudo_UPD };
3027      unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3028                               ARM::VLD4q16oddPseudo,
3029                               ARM::VLD4q32oddPseudo };
3030      return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3031    }
3032
3033    case Intrinsic::arm_neon_vld2lane: {
3034      unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
3035                              ARM::VLD2LNd32Pseudo };
3036      unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
3037      return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3038    }
3039
3040    case Intrinsic::arm_neon_vld3lane: {
3041      unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
3042                              ARM::VLD3LNd32Pseudo };
3043      unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
3044      return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3045    }
3046
3047    case Intrinsic::arm_neon_vld4lane: {
3048      unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
3049                              ARM::VLD4LNd32Pseudo };
3050      unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
3051      return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3052    }
3053
3054    case Intrinsic::arm_neon_vst1: {
3055      unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3056                              ARM::VST1d32, ARM::VST1d64 };
3057      unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
3058                              ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
3059      return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
3060    }
3061
3062    case Intrinsic::arm_neon_vst2: {
3063      unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
3064                              ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
3065      unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3066                              ARM::VST2q32Pseudo };
3067      return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3068    }
3069
3070    case Intrinsic::arm_neon_vst3: {
3071      unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
3072                              ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
3073      unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3074                               ARM::VST3q16Pseudo_UPD,
3075                               ARM::VST3q32Pseudo_UPD };
3076      unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo,
3077                               ARM::VST3q16oddPseudo,
3078                               ARM::VST3q32oddPseudo };
3079      return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3080    }
3081
3082    case Intrinsic::arm_neon_vst4: {
3083      unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
3084                              ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
3085      unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3086                               ARM::VST4q16Pseudo_UPD,
3087                               ARM::VST4q32Pseudo_UPD };
3088      unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo,
3089                               ARM::VST4q16oddPseudo,
3090                               ARM::VST4q32oddPseudo };
3091      return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3092    }
3093
3094    case Intrinsic::arm_neon_vst2lane: {
3095      unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
3096                              ARM::VST2LNd32Pseudo };
3097      unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
3098      return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3099    }
3100
3101    case Intrinsic::arm_neon_vst3lane: {
3102      unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
3103                              ARM::VST3LNd32Pseudo };
3104      unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
3105      return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3106    }
3107
3108    case Intrinsic::arm_neon_vst4lane: {
3109      unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
3110                              ARM::VST4LNd32Pseudo };
3111      unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
3112      return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3113    }
3114    }
3115    break;
3116  }
3117
3118  case ISD::INTRINSIC_WO_CHAIN: {
3119    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3120    switch (IntNo) {
3121    default:
3122      break;
3123
3124    case Intrinsic::arm_neon_vtbl2:
3125      return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
3126    case Intrinsic::arm_neon_vtbl3:
3127      return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3128    case Intrinsic::arm_neon_vtbl4:
3129      return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3130
3131    case Intrinsic::arm_neon_vtbx2:
3132      return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
3133    case Intrinsic::arm_neon_vtbx3:
3134      return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3135    case Intrinsic::arm_neon_vtbx4:
3136      return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3137    }
3138    break;
3139  }
3140
3141  case ARMISD::VTBL1: {
3142    DebugLoc dl = N->getDebugLoc();
3143    EVT VT = N->getValueType(0);
3144    SmallVector<SDValue, 6> Ops;
3145
3146    Ops.push_back(N->getOperand(0));
3147    Ops.push_back(N->getOperand(1));
3148    Ops.push_back(getAL(CurDAG));                    // Predicate
3149    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3150    return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
3151  }
3152  case ARMISD::VTBL2: {
3153    DebugLoc dl = N->getDebugLoc();
3154    EVT VT = N->getValueType(0);
3155
3156    // Form a REG_SEQUENCE to force register allocation.
3157    SDValue V0 = N->getOperand(0);
3158    SDValue V1 = N->getOperand(1);
3159    SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
3160
3161    SmallVector<SDValue, 6> Ops;
3162    Ops.push_back(RegSeq);
3163    Ops.push_back(N->getOperand(2));
3164    Ops.push_back(getAL(CurDAG));                    // Predicate
3165    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3166    return CurDAG->getMachineNode(ARM::VTBL2Pseudo, dl, VT,
3167                                  Ops.data(), Ops.size());
3168  }
3169
3170  case ISD::CONCAT_VECTORS:
3171    return SelectConcatVector(N);
3172
3173  case ARMISD::ATOMOR64_DAG:
3174    return SelectAtomic64(N, ARM::ATOMOR6432);
3175  case ARMISD::ATOMXOR64_DAG:
3176    return SelectAtomic64(N, ARM::ATOMXOR6432);
3177  case ARMISD::ATOMADD64_DAG:
3178    return SelectAtomic64(N, ARM::ATOMADD6432);
3179  case ARMISD::ATOMSUB64_DAG:
3180    return SelectAtomic64(N, ARM::ATOMSUB6432);
3181  case ARMISD::ATOMNAND64_DAG:
3182    return SelectAtomic64(N, ARM::ATOMNAND6432);
3183  case ARMISD::ATOMAND64_DAG:
3184    return SelectAtomic64(N, ARM::ATOMAND6432);
3185  case ARMISD::ATOMSWAP64_DAG:
3186    return SelectAtomic64(N, ARM::ATOMSWAP6432);
3187  case ARMISD::ATOMCMPXCHG64_DAG:
3188    return SelectAtomic64(N, ARM::ATOMCMPXCHG6432);
3189  }
3190
3191  return SelectCode(N);
3192}
3193
3194bool ARMDAGToDAGISel::
3195SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3196                             std::vector<SDValue> &OutOps) {
3197  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3198  // Require the address to be in a register.  That is safe for all ARM
3199  // variants and it is hard to do anything much smarter without knowing
3200  // how the operand is used.
3201  OutOps.push_back(Op);
3202  return false;
3203}
3204
3205/// createARMISelDag - This pass converts a legalized DAG into a
3206/// ARM-specific DAG, ready for instruction scheduling.
3207///
3208FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3209                                     CodeGenOpt::Level OptLevel) {
3210  return new ARMDAGToDAGISel(TM, OptLevel);
3211}
3212