ARMBaseInstrInfo.cpp revision 208599 
1//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMGenInstrInfo.inc"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMRegisterInfo.h"
21#include "llvm/Constants.h"
22#include "llvm/Function.h"
23#include "llvm/GlobalValue.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/CodeGen/LiveVariables.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineJumpTableInfo.h"
30#include "llvm/CodeGen/MachineMemOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37using namespace llvm;
38
39static cl::opt<bool>
40EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
41               cl::desc("Enable ARM 2-addr to 3-addr conv"));
42
43ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
44  : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
45    Subtarget(STI) {
46}
47
48MachineInstr *
49ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
50                                        MachineBasicBlock::iterator &MBBI,
51                                        LiveVariables *LV) const {
52  // FIXME: Thumb2 support.
53
54  if (!EnableARM3Addr)
55    return NULL;
56
57  MachineInstr *MI = MBBI;
58  MachineFunction &MF = *MI->getParent()->getParent();
59  unsigned TSFlags = MI->getDesc().TSFlags;
60  bool isPre = false;
61  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
62  default: return NULL;
63  case ARMII::IndexModePre:
64    isPre = true;
65    break;
66  case ARMII::IndexModePost:
67    break;
68  }
69
70  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
71  // operation.
72  unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
73  if (MemOpc == 0)
74    return NULL;
75
76  MachineInstr *UpdateMI = NULL;
77  MachineInstr *MemMI = NULL;
78  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
79  const TargetInstrDesc &TID = MI->getDesc();
80  unsigned NumOps = TID.getNumOperands();
81  bool isLoad = !TID.mayStore();
82  const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
83  const MachineOperand &Base = MI->getOperand(2);
84  const MachineOperand &Offset = MI->getOperand(NumOps-3);
85  unsigned WBReg = WB.getReg();
86  unsigned BaseReg = Base.getReg();
87  unsigned OffReg = Offset.getReg();
88  unsigned OffImm = MI->getOperand(NumOps-2).getImm();
89  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
90  switch (AddrMode) {
91  default:
92    assert(false && "Unknown indexed op!");
93    return NULL;
94  case ARMII::AddrMode2: {
95    bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
96    unsigned Amt = ARM_AM::getAM2Offset(OffImm);
97    if (OffReg == 0) {
98      if (ARM_AM::getSOImmVal(Amt) == -1)
99        // Can't encode it in a so_imm operand. This transformation will
100        // add more than 1 instruction. Abandon!
101        return NULL;
102      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
103                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
104        .addReg(BaseReg).addImm(Amt)
105        .addImm(Pred).addReg(0).addReg(0);
106    } else if (Amt != 0) {
107      ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
108      unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
109      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
110                         get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
111        .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
112        .addImm(Pred).addReg(0).addReg(0);
113    } else
114      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
115                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
116        .addReg(BaseReg).addReg(OffReg)
117        .addImm(Pred).addReg(0).addReg(0);
118    break;
119  }
120  case ARMII::AddrMode3 : {
121    bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
122    unsigned Amt = ARM_AM::getAM3Offset(OffImm);
123    if (OffReg == 0)
124      // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
125      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
126                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
127        .addReg(BaseReg).addImm(Amt)
128        .addImm(Pred).addReg(0).addReg(0);
129    else
130      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
131                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
132        .addReg(BaseReg).addReg(OffReg)
133        .addImm(Pred).addReg(0).addReg(0);
134    break;
135  }
136  }
137
138  std::vector<MachineInstr*> NewMIs;
139  if (isPre) {
140    if (isLoad)
141      MemMI = BuildMI(MF, MI->getDebugLoc(),
142                      get(MemOpc), MI->getOperand(0).getReg())
143        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
144    else
145      MemMI = BuildMI(MF, MI->getDebugLoc(),
146                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
147        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
148    NewMIs.push_back(MemMI);
149    NewMIs.push_back(UpdateMI);
150  } else {
151    if (isLoad)
152      MemMI = BuildMI(MF, MI->getDebugLoc(),
153                      get(MemOpc), MI->getOperand(0).getReg())
154        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
155    else
156      MemMI = BuildMI(MF, MI->getDebugLoc(),
157                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
158        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
159    if (WB.isDead())
160      UpdateMI->getOperand(0).setIsDead();
161    NewMIs.push_back(UpdateMI);
162    NewMIs.push_back(MemMI);
163  }
164
165  // Transfer LiveVariables states, kill / dead info.
166  if (LV) {
167    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
168      MachineOperand &MO = MI->getOperand(i);
169      if (MO.isReg() && MO.getReg() &&
170          TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
171        unsigned Reg = MO.getReg();
172
173        LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
174        if (MO.isDef()) {
175          MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
176          if (MO.isDead())
177            LV->addVirtualRegisterDead(Reg, NewMI);
178        }
179        if (MO.isUse() && MO.isKill()) {
180          for (unsigned j = 0; j < 2; ++j) {
181            // Look at the two new MI's in reverse order.
182            MachineInstr *NewMI = NewMIs[j];
183            if (!NewMI->readsRegister(Reg))
184              continue;
185            LV->addVirtualRegisterKilled(Reg, NewMI);
186            if (VI.removeKill(MI))
187              VI.Kills.push_back(NewMI);
188            break;
189          }
190        }
191      }
192    }
193  }
194
195  MFI->insert(MBBI, NewMIs[1]);
196  MFI->insert(MBBI, NewMIs[0]);
197  return NewMIs[0];
198}
199
200bool
201ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
202                                            MachineBasicBlock::iterator MI,
203                                            const std::vector<CalleeSavedInfo> &CSI,
204                                            const TargetRegisterInfo *TRI) const {
205  if (CSI.empty())
206    return false;
207
208  DebugLoc DL;
209  if (MI != MBB.end()) DL = MI->getDebugLoc();
210
211  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
212    unsigned Reg = CSI[i].getReg();
213    bool isKill = true;
214
215    // Add the callee-saved register as live-in unless it's LR and
216    // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
217    // then it's already added to the function and entry block live-in sets.
218    if (Reg == ARM::LR) {
219      MachineFunction &MF = *MBB.getParent();
220      if (MF.getFrameInfo()->isReturnAddressTaken() &&
221          MF.getRegInfo().isLiveIn(Reg))
222        isKill = false;
223    }
224
225    if (isKill)
226      MBB.addLiveIn(Reg);
227
228    // Insert the spill to the stack frame. The register is killed at the spill
229    //
230    storeRegToStackSlot(MBB, MI, Reg, isKill,
231                        CSI[i].getFrameIdx(), CSI[i].getRegClass(), TRI);
232  }
233  return true;
234}
235
236// Branch analysis.
237bool
238ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
239                                MachineBasicBlock *&FBB,
240                                SmallVectorImpl<MachineOperand> &Cond,
241                                bool AllowModify) const {
242  // If the block has no terminators, it just falls into the block after it.
243  MachineBasicBlock::iterator I = MBB.end();
244  if (I == MBB.begin())
245    return false;
246  --I;
247  while (I->isDebugValue()) {
248    if (I == MBB.begin())
249      return false;
250    --I;
251  }
252  if (!isUnpredicatedTerminator(I))
253    return false;
254
255  // Get the last instruction in the block.
256  MachineInstr *LastInst = I;
257
258  // If there is only one terminator instruction, process it.
259  unsigned LastOpc = LastInst->getOpcode();
260  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
261    if (isUncondBranchOpcode(LastOpc)) {
262      TBB = LastInst->getOperand(0).getMBB();
263      return false;
264    }
265    if (isCondBranchOpcode(LastOpc)) {
266      // Block ends with fall-through condbranch.
267      TBB = LastInst->getOperand(0).getMBB();
268      Cond.push_back(LastInst->getOperand(1));
269      Cond.push_back(LastInst->getOperand(2));
270      return false;
271    }
272    return true;  // Can't handle indirect branch.
273  }
274
275  // Get the instruction before it if it is a terminator.
276  MachineInstr *SecondLastInst = I;
277
278  // If there are three terminators, we don't know what sort of block this is.
279  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
280    return true;
281
282  // If the block ends with a B and a Bcc, handle it.
283  unsigned SecondLastOpc = SecondLastInst->getOpcode();
284  if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
285    TBB =  SecondLastInst->getOperand(0).getMBB();
286    Cond.push_back(SecondLastInst->getOperand(1));
287    Cond.push_back(SecondLastInst->getOperand(2));
288    FBB = LastInst->getOperand(0).getMBB();
289    return false;
290  }
291
292  // If the block ends with two unconditional branches, handle it.  The second
293  // one is not executed, so remove it.
294  if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
295    TBB = SecondLastInst->getOperand(0).getMBB();
296    I = LastInst;
297    if (AllowModify)
298      I->eraseFromParent();
299    return false;
300  }
301
302  // ...likewise if it ends with a branch table followed by an unconditional
303  // branch. The branch folder can create these, and we must get rid of them for
304  // correctness of Thumb constant islands.
305  if ((isJumpTableBranchOpcode(SecondLastOpc) ||
306       isIndirectBranchOpcode(SecondLastOpc)) &&
307      isUncondBranchOpcode(LastOpc)) {
308    I = LastInst;
309    if (AllowModify)
310      I->eraseFromParent();
311    return true;
312  }
313
314  // Otherwise, can't handle this.
315  return true;
316}
317
318
319unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
320  MachineBasicBlock::iterator I = MBB.end();
321  if (I == MBB.begin()) return 0;
322  --I;
323  while (I->isDebugValue()) {
324    if (I == MBB.begin())
325      return 0;
326    --I;
327  }
328  if (!isUncondBranchOpcode(I->getOpcode()) &&
329      !isCondBranchOpcode(I->getOpcode()))
330    return 0;
331
332  // Remove the branch.
333  I->eraseFromParent();
334
335  I = MBB.end();
336
337  if (I == MBB.begin()) return 1;
338  --I;
339  if (!isCondBranchOpcode(I->getOpcode()))
340    return 1;
341
342  // Remove the branch.
343  I->eraseFromParent();
344  return 2;
345}
346
347unsigned
348ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
349                               MachineBasicBlock *FBB,
350                             const SmallVectorImpl<MachineOperand> &Cond) const {
351  // FIXME this should probably have a DebugLoc argument
352  DebugLoc dl;
353
354  ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
355  int BOpc   = !AFI->isThumbFunction()
356    ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
357  int BccOpc = !AFI->isThumbFunction()
358    ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
359
360  // Shouldn't be a fall through.
361  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
362  assert((Cond.size() == 2 || Cond.size() == 0) &&
363         "ARM branch conditions have two components!");
364
365  if (FBB == 0) {
366    if (Cond.empty()) // Unconditional branch?
367      BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
368    else
369      BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
370        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
371    return 1;
372  }
373
374  // Two-way conditional branch.
375  BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
376    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
377  BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
378  return 2;
379}
380
381bool ARMBaseInstrInfo::
382ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
383  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
384  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
385  return false;
386}
387
388bool ARMBaseInstrInfo::
389PredicateInstruction(MachineInstr *MI,
390                     const SmallVectorImpl<MachineOperand> &Pred) const {
391  unsigned Opc = MI->getOpcode();
392  if (isUncondBranchOpcode(Opc)) {
393    MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
394    MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
395    MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
396    return true;
397  }
398
399  int PIdx = MI->findFirstPredOperandIdx();
400  if (PIdx != -1) {
401    MachineOperand &PMO = MI->getOperand(PIdx);
402    PMO.setImm(Pred[0].getImm());
403    MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
404    return true;
405  }
406  return false;
407}
408
409bool ARMBaseInstrInfo::
410SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
411                  const SmallVectorImpl<MachineOperand> &Pred2) const {
412  if (Pred1.size() > 2 || Pred2.size() > 2)
413    return false;
414
415  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
416  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
417  if (CC1 == CC2)
418    return true;
419
420  switch (CC1) {
421  default:
422    return false;
423  case ARMCC::AL:
424    return true;
425  case ARMCC::HS:
426    return CC2 == ARMCC::HI;
427  case ARMCC::LS:
428    return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
429  case ARMCC::GE:
430    return CC2 == ARMCC::GT;
431  case ARMCC::LE:
432    return CC2 == ARMCC::LT;
433  }
434}
435
436bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
437                                    std::vector<MachineOperand> &Pred) const {
438  // FIXME: This confuses implicit_def with optional CPSR def.
439  const TargetInstrDesc &TID = MI->getDesc();
440  if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
441    return false;
442
443  bool Found = false;
444  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
445    const MachineOperand &MO = MI->getOperand(i);
446    if (MO.isReg() && MO.getReg() == ARM::CPSR) {
447      Pred.push_back(MO);
448      Found = true;
449    }
450  }
451
452  return Found;
453}
454
455/// isPredicable - Return true if the specified instruction can be predicated.
456/// By default, this returns true for every instruction with a
457/// PredicateOperand.
458bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
459  const TargetInstrDesc &TID = MI->getDesc();
460  if (!TID.isPredicable())
461    return false;
462
463  if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
464    ARMFunctionInfo *AFI =
465      MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
466    return AFI->isThumb2Function();
467  }
468  return true;
469}
470
471/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
472DISABLE_INLINE
473static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
474                                unsigned JTI);
475static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
476                                unsigned JTI) {
477  assert(JTI < JT.size());
478  return JT[JTI].MBBs.size();
479}
480
481/// GetInstSize - Return the size of the specified MachineInstr.
482///
483unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
484  const MachineBasicBlock &MBB = *MI->getParent();
485  const MachineFunction *MF = MBB.getParent();
486  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
487
488  // Basic size info comes from the TSFlags field.
489  const TargetInstrDesc &TID = MI->getDesc();
490  unsigned TSFlags = TID.TSFlags;
491
492  unsigned Opc = MI->getOpcode();
493  switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
494  default: {
495    // If this machine instr is an inline asm, measure it.
496    if (MI->getOpcode() == ARM::INLINEASM)
497      return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
498    if (MI->isLabel())
499      return 0;
500    switch (Opc) {
501    default:
502      llvm_unreachable("Unknown or unset size field for instr!");
503    case TargetOpcode::IMPLICIT_DEF:
504    case TargetOpcode::KILL:
505    case TargetOpcode::DBG_LABEL:
506    case TargetOpcode::EH_LABEL:
507    case TargetOpcode::DBG_VALUE:
508      return 0;
509    }
510    break;
511  }
512  case ARMII::Size8Bytes: return 8;          // ARM instruction x 2.
513  case ARMII::Size4Bytes: return 4;          // ARM / Thumb2 instruction.
514  case ARMII::Size2Bytes: return 2;          // Thumb1 instruction.
515  case ARMII::SizeSpecial: {
516    switch (Opc) {
517    case ARM::CONSTPOOL_ENTRY:
518      // If this machine instr is a constant pool entry, its size is recorded as
519      // operand #2.
520      return MI->getOperand(2).getImm();
521    case ARM::Int_eh_sjlj_longjmp:
522      return 16;
523    case ARM::tInt_eh_sjlj_longjmp:
524      return 10;
525    case ARM::Int_eh_sjlj_setjmp:
526    case ARM::Int_eh_sjlj_setjmp_nofp:
527      return 24;
528    case ARM::tInt_eh_sjlj_setjmp:
529    case ARM::t2Int_eh_sjlj_setjmp:
530    case ARM::t2Int_eh_sjlj_setjmp_nofp:
531      return 14;
532    case ARM::BR_JTr:
533    case ARM::BR_JTm:
534    case ARM::BR_JTadd:
535    case ARM::tBR_JTr:
536    case ARM::t2BR_JT:
537    case ARM::t2TBB:
538    case ARM::t2TBH: {
539      // These are jumptable branches, i.e. a branch followed by an inlined
540      // jumptable. The size is 4 + 4 * number of entries. For TBB, each
541      // entry is one byte; TBH two byte each.
542      unsigned EntrySize = (Opc == ARM::t2TBB)
543        ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
544      unsigned NumOps = TID.getNumOperands();
545      MachineOperand JTOP =
546        MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
547      unsigned JTI = JTOP.getIndex();
548      const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
549      assert(MJTI != 0);
550      const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
551      assert(JTI < JT.size());
552      // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
553      // 4 aligned. The assembler / linker may add 2 byte padding just before
554      // the JT entries.  The size does not include this padding; the
555      // constant islands pass does separate bookkeeping for it.
556      // FIXME: If we know the size of the function is less than (1 << 16) *2
557      // bytes, we can use 16-bit entries instead. Then there won't be an
558      // alignment issue.
559      unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
560      unsigned NumEntries = getNumJTEntries(JT, JTI);
561      if (Opc == ARM::t2TBB && (NumEntries & 1))
562        // Make sure the instruction that follows TBB is 2-byte aligned.
563        // FIXME: Constant island pass should insert an "ALIGN" instruction
564        // instead.
565        ++NumEntries;
566      return NumEntries * EntrySize + InstSize;
567    }
568    default:
569      // Otherwise, pseudo-instruction sizes are zero.
570      return 0;
571    }
572  }
573  }
574  return 0; // Not reached
575}
576
577/// Return true if the instruction is a register to register move and
578/// leave the source and dest operands in the passed parameters.
579///
580bool
581ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
582                              unsigned &SrcReg, unsigned &DstReg,
583                              unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
584  switch (MI.getOpcode()) {
585  default: break;
586  case ARM::VMOVS:
587  case ARM::VMOVD:
588  case ARM::VMOVDneon:
589  case ARM::VMOVQ:
590  case ARM::VMOVQQ : {
591    SrcReg = MI.getOperand(1).getReg();
592    DstReg = MI.getOperand(0).getReg();
593    SrcSubIdx = MI.getOperand(1).getSubReg();
594    DstSubIdx = MI.getOperand(0).getSubReg();
595    return true;
596  }
597  case ARM::MOVr:
598  case ARM::tMOVr:
599  case ARM::tMOVgpr2tgpr:
600  case ARM::tMOVtgpr2gpr:
601  case ARM::tMOVgpr2gpr:
602  case ARM::t2MOVr: {
603    assert(MI.getDesc().getNumOperands() >= 2 &&
604           MI.getOperand(0).isReg() &&
605           MI.getOperand(1).isReg() &&
606           "Invalid ARM MOV instruction");
607    SrcReg = MI.getOperand(1).getReg();
608    DstReg = MI.getOperand(0).getReg();
609    SrcSubIdx = MI.getOperand(1).getSubReg();
610    DstSubIdx = MI.getOperand(0).getSubReg();
611    return true;
612  }
613  }
614
615  return false;
616}
617
618unsigned
619ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
620                                      int &FrameIndex) const {
621  switch (MI->getOpcode()) {
622  default: break;
623  case ARM::LDR:
624  case ARM::t2LDRs:  // FIXME: don't use t2LDRs to access frame.
625    if (MI->getOperand(1).isFI() &&
626        MI->getOperand(2).isReg() &&
627        MI->getOperand(3).isImm() &&
628        MI->getOperand(2).getReg() == 0 &&
629        MI->getOperand(3).getImm() == 0) {
630      FrameIndex = MI->getOperand(1).getIndex();
631      return MI->getOperand(0).getReg();
632    }
633    break;
634  case ARM::t2LDRi12:
635  case ARM::tRestore:
636    if (MI->getOperand(1).isFI() &&
637        MI->getOperand(2).isImm() &&
638        MI->getOperand(2).getImm() == 0) {
639      FrameIndex = MI->getOperand(1).getIndex();
640      return MI->getOperand(0).getReg();
641    }
642    break;
643  case ARM::VLDRD:
644  case ARM::VLDRS:
645    if (MI->getOperand(1).isFI() &&
646        MI->getOperand(2).isImm() &&
647        MI->getOperand(2).getImm() == 0) {
648      FrameIndex = MI->getOperand(1).getIndex();
649      return MI->getOperand(0).getReg();
650    }
651    break;
652  }
653
654  return 0;
655}
656
657unsigned
658ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
659                                     int &FrameIndex) const {
660  switch (MI->getOpcode()) {
661  default: break;
662  case ARM::STR:
663  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
664    if (MI->getOperand(1).isFI() &&
665        MI->getOperand(2).isReg() &&
666        MI->getOperand(3).isImm() &&
667        MI->getOperand(2).getReg() == 0 &&
668        MI->getOperand(3).getImm() == 0) {
669      FrameIndex = MI->getOperand(1).getIndex();
670      return MI->getOperand(0).getReg();
671    }
672    break;
673  case ARM::t2STRi12:
674  case ARM::tSpill:
675    if (MI->getOperand(1).isFI() &&
676        MI->getOperand(2).isImm() &&
677        MI->getOperand(2).getImm() == 0) {
678      FrameIndex = MI->getOperand(1).getIndex();
679      return MI->getOperand(0).getReg();
680    }
681    break;
682  case ARM::VSTRD:
683  case ARM::VSTRS:
684    if (MI->getOperand(1).isFI() &&
685        MI->getOperand(2).isImm() &&
686        MI->getOperand(2).getImm() == 0) {
687      FrameIndex = MI->getOperand(1).getIndex();
688      return MI->getOperand(0).getReg();
689    }
690    break;
691  }
692
693  return 0;
694}
695
696bool
697ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
698                               MachineBasicBlock::iterator I,
699                               unsigned DestReg, unsigned SrcReg,
700                               const TargetRegisterClass *DestRC,
701                               const TargetRegisterClass *SrcRC,
702                               DebugLoc DL) const {
703  // tGPR is used sometimes in ARM instructions that need to avoid using
704  // certain registers.  Just treat it as GPR here.
705  if (DestRC == ARM::tGPRRegisterClass)
706    DestRC = ARM::GPRRegisterClass;
707  if (SrcRC == ARM::tGPRRegisterClass)
708    SrcRC = ARM::GPRRegisterClass;
709
710  // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
711  if (DestRC == ARM::DPR_8RegisterClass)
712    DestRC = ARM::DPR_VFP2RegisterClass;
713  if (SrcRC == ARM::DPR_8RegisterClass)
714    SrcRC = ARM::DPR_VFP2RegisterClass;
715
716  // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
717  if (DestRC == ARM::QPR_VFP2RegisterClass ||
718      DestRC == ARM::QPR_8RegisterClass)
719    DestRC = ARM::QPRRegisterClass;
720  if (SrcRC == ARM::QPR_VFP2RegisterClass ||
721      SrcRC == ARM::QPR_8RegisterClass)
722    SrcRC = ARM::QPRRegisterClass;
723
724  // Allow QQPR / QQPR_VFP2 cross-class copies.
725  if (DestRC == ARM::QQPR_VFP2RegisterClass)
726    DestRC = ARM::QQPRRegisterClass;
727  if (SrcRC == ARM::QQPR_VFP2RegisterClass)
728    SrcRC = ARM::QQPRRegisterClass;
729
730  // Disallow copies of unequal sizes.
731  if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize())
732    return false;
733
734  if (DestRC == ARM::GPRRegisterClass) {
735    if (SrcRC == ARM::SPRRegisterClass)
736      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg)
737                     .addReg(SrcReg));
738    else
739      AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
740                                          DestReg).addReg(SrcReg)));
741  } else {
742    unsigned Opc;
743
744    if (DestRC == ARM::SPRRegisterClass)
745      Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
746    else if (DestRC == ARM::DPRRegisterClass)
747      Opc = ARM::VMOVD;
748    else if (DestRC == ARM::DPR_VFP2RegisterClass ||
749             SrcRC == ARM::DPR_VFP2RegisterClass)
750      // Always use neon reg-reg move if source or dest is NEON-only regclass.
751      Opc = ARM::VMOVDneon;
752    else if (DestRC == ARM::QPRRegisterClass)
753      Opc = ARM::VMOVQ;
754    else if (DestRC == ARM::QQPRRegisterClass)
755      Opc = ARM::VMOVQQ;
756    else if (DestRC == ARM::QQQQPRRegisterClass)
757      Opc = ARM::VMOVQQQQ;
758    else
759      return false;
760
761    AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg));
762  }
763
764  return true;
765}
766
767static const
768MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
769                             unsigned Reg, unsigned SubIdx, unsigned State,
770                             const TargetRegisterInfo *TRI) {
771  if (!SubIdx)
772    return MIB.addReg(Reg, State);
773
774  if (TargetRegisterInfo::isPhysicalRegister(Reg))
775    return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
776  return MIB.addReg(Reg, State, SubIdx);
777}
778
779void ARMBaseInstrInfo::
780storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
781                    unsigned SrcReg, bool isKill, int FI,
782                    const TargetRegisterClass *RC,
783                    const TargetRegisterInfo *TRI) const {
784  DebugLoc DL;
785  if (I != MBB.end()) DL = I->getDebugLoc();
786  MachineFunction &MF = *MBB.getParent();
787  MachineFrameInfo &MFI = *MF.getFrameInfo();
788  unsigned Align = MFI.getObjectAlignment(FI);
789
790  MachineMemOperand *MMO =
791    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
792                            MachineMemOperand::MOStore, 0,
793                            MFI.getObjectSize(FI),
794                            Align);
795
796  // tGPR is used sometimes in ARM instructions that need to avoid using
797  // certain registers.  Just treat it as GPR here.
798  if (RC == ARM::tGPRRegisterClass)
799    RC = ARM::GPRRegisterClass;
800
801  if (RC == ARM::GPRRegisterClass) {
802    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
803                   .addReg(SrcReg, getKillRegState(isKill))
804                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
805  } else if (RC == ARM::SPRRegisterClass) {
806    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
807                   .addReg(SrcReg, getKillRegState(isKill))
808                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
809  } else if (RC == ARM::DPRRegisterClass ||
810             RC == ARM::DPR_VFP2RegisterClass ||
811             RC == ARM::DPR_8RegisterClass) {
812    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
813                   .addReg(SrcReg, getKillRegState(isKill))
814                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
815  } else if (RC == ARM::QPRRegisterClass ||
816             RC == ARM::QPR_VFP2RegisterClass ||
817             RC == ARM::QPR_8RegisterClass) {
818    // FIXME: Neon instructions should support predicates
819    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
820      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
821                     .addFrameIndex(FI).addImm(128)
822                     .addReg(SrcReg, getKillRegState(isKill))
823                     .addMemOperand(MMO));
824    } else {
825      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
826                     .addReg(SrcReg, getKillRegState(isKill))
827                     .addFrameIndex(FI)
828                     .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
829                     .addMemOperand(MMO));
830    }
831  } else if (RC == ARM::QQPRRegisterClass || RC == ARM::QQPR_VFP2RegisterClass){
832    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
833      // FIXME: It's possible to only store part of the QQ register if the
834      // spilled def has a sub-register index.
835      MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
836        .addFrameIndex(FI).addImm(128);
837      MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
838      MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
839      MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
840      MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
841      AddDefaultPred(MIB.addMemOperand(MMO));
842    } else {
843      MachineInstrBuilder MIB =
844        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
845                       .addFrameIndex(FI)
846                       .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
847        .addMemOperand(MMO);
848      MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
849      MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
850      MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
851            AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
852    }
853  } else {
854    assert(RC == ARM::QQQQPRRegisterClass && "Unknown regclass!");
855    MachineInstrBuilder MIB =
856      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
857                     .addFrameIndex(FI)
858                     .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
859      .addMemOperand(MMO);
860    MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
861    MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
862    MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
863    MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
864    MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
865    MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
866    MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
867          AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
868  }
869}
870
871void ARMBaseInstrInfo::
872loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
873                     unsigned DestReg, int FI,
874                     const TargetRegisterClass *RC,
875                     const TargetRegisterInfo *TRI) const {
876  DebugLoc DL;
877  if (I != MBB.end()) DL = I->getDebugLoc();
878  MachineFunction &MF = *MBB.getParent();
879  MachineFrameInfo &MFI = *MF.getFrameInfo();
880  unsigned Align = MFI.getObjectAlignment(FI);
881  MachineMemOperand *MMO =
882    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
883                            MachineMemOperand::MOLoad, 0,
884                            MFI.getObjectSize(FI),
885                            Align);
886
887  // tGPR is used sometimes in ARM instructions that need to avoid using
888  // certain registers.  Just treat it as GPR here.
889  if (RC == ARM::tGPRRegisterClass)
890    RC = ARM::GPRRegisterClass;
891
892  if (RC == ARM::GPRRegisterClass) {
893    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
894                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
895  } else if (RC == ARM::SPRRegisterClass) {
896    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
897                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
898  } else if (RC == ARM::DPRRegisterClass ||
899             RC == ARM::DPR_VFP2RegisterClass ||
900             RC == ARM::DPR_8RegisterClass) {
901    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
902                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
903  } else if (RC == ARM::QPRRegisterClass ||
904             RC == ARM::QPR_VFP2RegisterClass ||
905             RC == ARM::QPR_8RegisterClass) {
906    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
907      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
908                     .addFrameIndex(FI).addImm(128)
909                     .addMemOperand(MMO));
910    } else {
911      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
912                     .addFrameIndex(FI)
913                     .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
914                     .addMemOperand(MMO));
915    }
916  } else if (RC == ARM::QQPRRegisterClass || RC == ARM::QQPR_VFP2RegisterClass){
917    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
918      MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32));
919      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
920      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
921      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
922      MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
923      AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
924    } else {
925      MachineInstrBuilder MIB =
926        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
927                       .addFrameIndex(FI)
928                       .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
929        .addMemOperand(MMO);
930      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
931      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
932      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
933            AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
934    }
935  } else {
936    assert(RC == ARM::QQQQPRRegisterClass && "Unknown regclass!");
937      MachineInstrBuilder MIB =
938        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
939                       .addFrameIndex(FI)
940                       .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
941        .addMemOperand(MMO);
942      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
943      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
944      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
945      MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
946      MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
947      MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
948      MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
949            AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
950  }
951}
952
953MachineInstr*
954ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
955                                           int FrameIx, uint64_t Offset,
956                                           const MDNode *MDPtr,
957                                           DebugLoc DL) const {
958  MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
959    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
960  return &*MIB;
961}
962
963MachineInstr *ARMBaseInstrInfo::
964foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
965                      const SmallVectorImpl<unsigned> &Ops, int FI) const {
966  if (Ops.size() != 1) return NULL;
967
968  unsigned OpNum = Ops[0];
969  unsigned Opc = MI->getOpcode();
970  MachineInstr *NewMI = NULL;
971  if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
972    // If it is updating CPSR, then it cannot be folded.
973    if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
974      return NULL;
975    unsigned Pred = MI->getOperand(2).getImm();
976    unsigned PredReg = MI->getOperand(3).getReg();
977    if (OpNum == 0) { // move -> store
978      unsigned SrcReg = MI->getOperand(1).getReg();
979      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
980      bool isKill = MI->getOperand(1).isKill();
981      bool isUndef = MI->getOperand(1).isUndef();
982      if (Opc == ARM::MOVr)
983        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
984          .addReg(SrcReg,
985                  getKillRegState(isKill) | getUndefRegState(isUndef),
986                  SrcSubReg)
987          .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
988      else // ARM::t2MOVr
989        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
990          .addReg(SrcReg,
991                  getKillRegState(isKill) | getUndefRegState(isUndef),
992                  SrcSubReg)
993          .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
994    } else {          // move -> load
995      unsigned DstReg = MI->getOperand(0).getReg();
996      unsigned DstSubReg = MI->getOperand(0).getSubReg();
997      bool isDead = MI->getOperand(0).isDead();
998      bool isUndef = MI->getOperand(0).isUndef();
999      if (Opc == ARM::MOVr)
1000        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
1001          .addReg(DstReg,
1002                  RegState::Define |
1003                  getDeadRegState(isDead) |
1004                  getUndefRegState(isUndef), DstSubReg)
1005          .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1006      else // ARM::t2MOVr
1007        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
1008          .addReg(DstReg,
1009                  RegState::Define |
1010                  getDeadRegState(isDead) |
1011                  getUndefRegState(isUndef), DstSubReg)
1012          .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1013    }
1014  } else if (Opc == ARM::tMOVgpr2gpr ||
1015             Opc == ARM::tMOVtgpr2gpr ||
1016             Opc == ARM::tMOVgpr2tgpr) {
1017    if (OpNum == 0) { // move -> store
1018      unsigned SrcReg = MI->getOperand(1).getReg();
1019      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1020      bool isKill = MI->getOperand(1).isKill();
1021      bool isUndef = MI->getOperand(1).isUndef();
1022      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
1023        .addReg(SrcReg,
1024                getKillRegState(isKill) | getUndefRegState(isUndef),
1025                SrcSubReg)
1026        .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
1027    } else {          // move -> load
1028      unsigned DstReg = MI->getOperand(0).getReg();
1029      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1030      bool isDead = MI->getOperand(0).isDead();
1031      bool isUndef = MI->getOperand(0).isUndef();
1032      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
1033        .addReg(DstReg,
1034                RegState::Define |
1035                getDeadRegState(isDead) |
1036                getUndefRegState(isUndef),
1037                DstSubReg)
1038        .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
1039    }
1040  } else if (Opc == ARM::VMOVS) {
1041    unsigned Pred = MI->getOperand(2).getImm();
1042    unsigned PredReg = MI->getOperand(3).getReg();
1043    if (OpNum == 0) { // move -> store
1044      unsigned SrcReg = MI->getOperand(1).getReg();
1045      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1046      bool isKill = MI->getOperand(1).isKill();
1047      bool isUndef = MI->getOperand(1).isUndef();
1048      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
1049        .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
1050                SrcSubReg)
1051        .addFrameIndex(FI)
1052        .addImm(0).addImm(Pred).addReg(PredReg);
1053    } else {          // move -> load
1054      unsigned DstReg = MI->getOperand(0).getReg();
1055      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1056      bool isDead = MI->getOperand(0).isDead();
1057      bool isUndef = MI->getOperand(0).isUndef();
1058      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
1059        .addReg(DstReg,
1060                RegState::Define |
1061                getDeadRegState(isDead) |
1062                getUndefRegState(isUndef),
1063                DstSubReg)
1064        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1065    }
1066  } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVDneon) {
1067    unsigned Pred = MI->getOperand(2).getImm();
1068    unsigned PredReg = MI->getOperand(3).getReg();
1069    if (OpNum == 0) { // move -> store
1070      unsigned SrcReg = MI->getOperand(1).getReg();
1071      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1072      bool isKill = MI->getOperand(1).isKill();
1073      bool isUndef = MI->getOperand(1).isUndef();
1074      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
1075        .addReg(SrcReg,
1076                getKillRegState(isKill) | getUndefRegState(isUndef),
1077                SrcSubReg)
1078        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1079    } else {          // move -> load
1080      unsigned DstReg = MI->getOperand(0).getReg();
1081      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1082      bool isDead = MI->getOperand(0).isDead();
1083      bool isUndef = MI->getOperand(0).isUndef();
1084      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
1085        .addReg(DstReg,
1086                RegState::Define |
1087                getDeadRegState(isDead) |
1088                getUndefRegState(isUndef),
1089                DstSubReg)
1090        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1091    }
1092  }  else if (Opc == ARM::VMOVQ) {
1093    MachineFrameInfo &MFI = *MF.getFrameInfo();
1094    unsigned Pred = MI->getOperand(2).getImm();
1095    unsigned PredReg = MI->getOperand(3).getReg();
1096    if (OpNum == 0) { // move -> store
1097      unsigned SrcReg = MI->getOperand(1).getReg();
1098      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1099      bool isKill = MI->getOperand(1).isKill();
1100      bool isUndef = MI->getOperand(1).isUndef();
1101      if (MFI.getObjectAlignment(FI) >= 16 &&
1102          getRegisterInfo().canRealignStack(MF)) {
1103        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VST1q))
1104          .addFrameIndex(FI).addImm(128)
1105          .addReg(SrcReg,
1106                  getKillRegState(isKill) | getUndefRegState(isUndef),
1107                  SrcSubReg)
1108          .addImm(Pred).addReg(PredReg);
1109      } else {
1110        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTMQ))
1111          .addReg(SrcReg,
1112                  getKillRegState(isKill) | getUndefRegState(isUndef),
1113                  SrcSubReg)
1114          .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1115          .addImm(Pred).addReg(PredReg);
1116      }
1117    } else {          // move -> load
1118      unsigned DstReg = MI->getOperand(0).getReg();
1119      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1120      bool isDead = MI->getOperand(0).isDead();
1121      bool isUndef = MI->getOperand(0).isUndef();
1122      if (MFI.getObjectAlignment(FI) >= 16 &&
1123          getRegisterInfo().canRealignStack(MF)) {
1124        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLD1q))
1125          .addReg(DstReg,
1126                  RegState::Define |
1127                  getDeadRegState(isDead) |
1128                  getUndefRegState(isUndef),
1129                  DstSubReg)
1130          .addFrameIndex(FI).addImm(128).addImm(Pred).addReg(PredReg);
1131      } else {
1132        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDMQ))
1133          .addReg(DstReg,
1134                  RegState::Define |
1135                  getDeadRegState(isDead) |
1136                  getUndefRegState(isUndef),
1137                  DstSubReg)
1138          .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1139          .addImm(Pred).addReg(PredReg);
1140      }
1141    }
1142  }
1143
1144  return NewMI;
1145}
1146
1147MachineInstr*
1148ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
1149                                        MachineInstr* MI,
1150                                        const SmallVectorImpl<unsigned> &Ops,
1151                                        MachineInstr* LoadMI) const {
1152  // FIXME
1153  return 0;
1154}
1155
1156bool
1157ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
1158                                   const SmallVectorImpl<unsigned> &Ops) const {
1159  if (Ops.size() != 1) return false;
1160
1161  unsigned Opc = MI->getOpcode();
1162  if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
1163    // If it is updating CPSR, then it cannot be folded.
1164    return MI->getOperand(4).getReg() != ARM::CPSR ||
1165      MI->getOperand(4).isDead();
1166  } else if (Opc == ARM::tMOVgpr2gpr ||
1167             Opc == ARM::tMOVtgpr2gpr ||
1168             Opc == ARM::tMOVgpr2tgpr) {
1169    return true;
1170  } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD ||
1171             Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
1172    return true;
1173  }
1174
1175  // FIXME: VMOVQQ and VMOVQQQQ?
1176
1177  return false;
1178}
1179
1180/// Create a copy of a const pool value. Update CPI to the new index and return
1181/// the label UID.
1182static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1183  MachineConstantPool *MCP = MF.getConstantPool();
1184  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1185
1186  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1187  assert(MCPE.isMachineConstantPoolEntry() &&
1188         "Expecting a machine constantpool entry!");
1189  ARMConstantPoolValue *ACPV =
1190    static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1191
1192  unsigned PCLabelId = AFI->createConstPoolEntryUId();
1193  ARMConstantPoolValue *NewCPV = 0;
1194  if (ACPV->isGlobalValue())
1195    NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
1196                                      ARMCP::CPValue, 4);
1197  else if (ACPV->isExtSymbol())
1198    NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
1199                                      ACPV->getSymbol(), PCLabelId, 4);
1200  else if (ACPV->isBlockAddress())
1201    NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
1202                                      ARMCP::CPBlockAddress, 4);
1203  else
1204    llvm_unreachable("Unexpected ARM constantpool value type!!");
1205  CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1206  return PCLabelId;
1207}
1208
1209void ARMBaseInstrInfo::
1210reMaterialize(MachineBasicBlock &MBB,
1211              MachineBasicBlock::iterator I,
1212              unsigned DestReg, unsigned SubIdx,
1213              const MachineInstr *Orig,
1214              const TargetRegisterInfo *TRI) const {
1215  if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
1216    DestReg = TRI->getSubReg(DestReg, SubIdx);
1217    SubIdx = 0;
1218  }
1219
1220  unsigned Opcode = Orig->getOpcode();
1221  switch (Opcode) {
1222  default: {
1223    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1224    MI->getOperand(0).setReg(DestReg);
1225    MBB.insert(I, MI);
1226    break;
1227  }
1228  case ARM::tLDRpci_pic:
1229  case ARM::t2LDRpci_pic: {
1230    MachineFunction &MF = *MBB.getParent();
1231    unsigned CPI = Orig->getOperand(1).getIndex();
1232    unsigned PCLabelId = duplicateCPV(MF, CPI);
1233    MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1234                                      DestReg)
1235      .addConstantPoolIndex(CPI).addImm(PCLabelId);
1236    (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1237    break;
1238  }
1239  }
1240
1241  MachineInstr *NewMI = prior(I);
1242  NewMI->getOperand(0).setSubReg(SubIdx);
1243}
1244
1245MachineInstr *
1246ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1247  MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1248  switch(Orig->getOpcode()) {
1249  case ARM::tLDRpci_pic:
1250  case ARM::t2LDRpci_pic: {
1251    unsigned CPI = Orig->getOperand(1).getIndex();
1252    unsigned PCLabelId = duplicateCPV(MF, CPI);
1253    Orig->getOperand(1).setIndex(CPI);
1254    Orig->getOperand(2).setImm(PCLabelId);
1255    break;
1256  }
1257  }
1258  return MI;
1259}
1260
1261bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1262                                        const MachineInstr *MI1) const {
1263  int Opcode = MI0->getOpcode();
1264  if (Opcode == ARM::t2LDRpci ||
1265      Opcode == ARM::t2LDRpci_pic ||
1266      Opcode == ARM::tLDRpci ||
1267      Opcode == ARM::tLDRpci_pic) {
1268    if (MI1->getOpcode() != Opcode)
1269      return false;
1270    if (MI0->getNumOperands() != MI1->getNumOperands())
1271      return false;
1272
1273    const MachineOperand &MO0 = MI0->getOperand(1);
1274    const MachineOperand &MO1 = MI1->getOperand(1);
1275    if (MO0.getOffset() != MO1.getOffset())
1276      return false;
1277
1278    const MachineFunction *MF = MI0->getParent()->getParent();
1279    const MachineConstantPool *MCP = MF->getConstantPool();
1280    int CPI0 = MO0.getIndex();
1281    int CPI1 = MO1.getIndex();
1282    const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1283    const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1284    ARMConstantPoolValue *ACPV0 =
1285      static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1286    ARMConstantPoolValue *ACPV1 =
1287      static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1288    return ACPV0->hasSameValue(ACPV1);
1289  }
1290
1291  return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1292}
1293
1294/// getInstrPredicate - If instruction is predicated, returns its predicate
1295/// condition, otherwise returns AL. It also returns the condition code
1296/// register by reference.
1297ARMCC::CondCodes
1298llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1299  int PIdx = MI->findFirstPredOperandIdx();
1300  if (PIdx == -1) {
1301    PredReg = 0;
1302    return ARMCC::AL;
1303  }
1304
1305  PredReg = MI->getOperand(PIdx+1).getReg();
1306  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1307}
1308
1309
1310int llvm::getMatchingCondBranchOpcode(int Opc) {
1311  if (Opc == ARM::B)
1312    return ARM::Bcc;
1313  else if (Opc == ARM::tB)
1314    return ARM::tBcc;
1315  else if (Opc == ARM::t2B)
1316      return ARM::t2Bcc;
1317
1318  llvm_unreachable("Unknown unconditional branch opcode!");
1319  return 0;
1320}
1321
1322
1323void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1324                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1325                               unsigned DestReg, unsigned BaseReg, int NumBytes,
1326                               ARMCC::CondCodes Pred, unsigned PredReg,
1327                               const ARMBaseInstrInfo &TII) {
1328  bool isSub = NumBytes < 0;
1329  if (isSub) NumBytes = -NumBytes;
1330
1331  while (NumBytes) {
1332    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1333    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1334    assert(ThisVal && "Didn't extract field correctly");
1335
1336    // We will handle these bits from offset, clear them.
1337    NumBytes &= ~ThisVal;
1338
1339    assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1340
1341    // Build the new ADD / SUB.
1342    unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1343    BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1344      .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1345      .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1346    BaseReg = DestReg;
1347  }
1348}
1349
1350bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1351                                unsigned FrameReg, int &Offset,
1352                                const ARMBaseInstrInfo &TII) {
1353  unsigned Opcode = MI.getOpcode();
1354  const TargetInstrDesc &Desc = MI.getDesc();
1355  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1356  bool isSub = false;
1357
1358  // Memory operands in inline assembly always use AddrMode2.
1359  if (Opcode == ARM::INLINEASM)
1360    AddrMode = ARMII::AddrMode2;
1361
1362  if (Opcode == ARM::ADDri) {
1363    Offset += MI.getOperand(FrameRegIdx+1).getImm();
1364    if (Offset == 0) {
1365      // Turn it into a move.
1366      MI.setDesc(TII.get(ARM::MOVr));
1367      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1368      MI.RemoveOperand(FrameRegIdx+1);
1369      Offset = 0;
1370      return true;
1371    } else if (Offset < 0) {
1372      Offset = -Offset;
1373      isSub = true;
1374      MI.setDesc(TII.get(ARM::SUBri));
1375    }
1376
1377    // Common case: small offset, fits into instruction.
1378    if (ARM_AM::getSOImmVal(Offset) != -1) {
1379      // Replace the FrameIndex with sp / fp
1380      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1381      MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1382      Offset = 0;
1383      return true;
1384    }
1385
1386    // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1387    // as possible.
1388    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1389    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1390
1391    // We will handle these bits from offset, clear them.
1392    Offset &= ~ThisImmVal;
1393
1394    // Get the properly encoded SOImmVal field.
1395    assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1396           "Bit extraction didn't work?");
1397    MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1398 } else {
1399    unsigned ImmIdx = 0;
1400    int InstrOffs = 0;
1401    unsigned NumBits = 0;
1402    unsigned Scale = 1;
1403    switch (AddrMode) {
1404    case ARMII::AddrMode2: {
1405      ImmIdx = FrameRegIdx+2;
1406      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1407      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1408        InstrOffs *= -1;
1409      NumBits = 12;
1410      break;
1411    }
1412    case ARMII::AddrMode3: {
1413      ImmIdx = FrameRegIdx+2;
1414      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1415      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1416        InstrOffs *= -1;
1417      NumBits = 8;
1418      break;
1419    }
1420    case ARMII::AddrMode4:
1421    case ARMII::AddrMode6:
1422      // Can't fold any offset even if it's zero.
1423      return false;
1424    case ARMII::AddrMode5: {
1425      ImmIdx = FrameRegIdx+1;
1426      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1427      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1428        InstrOffs *= -1;
1429      NumBits = 8;
1430      Scale = 4;
1431      break;
1432    }
1433    default:
1434      llvm_unreachable("Unsupported addressing mode!");
1435      break;
1436    }
1437
1438    Offset += InstrOffs * Scale;
1439    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1440    if (Offset < 0) {
1441      Offset = -Offset;
1442      isSub = true;
1443    }
1444
1445    // Attempt to fold address comp. if opcode has offset bits
1446    if (NumBits > 0) {
1447      // Common case: small offset, fits into instruction.
1448      MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1449      int ImmedOffset = Offset / Scale;
1450      unsigned Mask = (1 << NumBits) - 1;
1451      if ((unsigned)Offset <= Mask * Scale) {
1452        // Replace the FrameIndex with sp
1453        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1454        if (isSub)
1455          ImmedOffset |= 1 << NumBits;
1456        ImmOp.ChangeToImmediate(ImmedOffset);
1457        Offset = 0;
1458        return true;
1459      }
1460
1461      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1462      ImmedOffset = ImmedOffset & Mask;
1463      if (isSub)
1464        ImmedOffset |= 1 << NumBits;
1465      ImmOp.ChangeToImmediate(ImmedOffset);
1466      Offset &= ~(Mask*Scale);
1467    }
1468  }
1469
1470  Offset = (isSub) ? -Offset : Offset;
1471  return Offset == 0;
1472}
1473