ARM.h revision 212904 
1//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the entry points for global functions defined in the LLVM
11// ARM back-end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef TARGET_ARM_H
16#define TARGET_ARM_H
17
18#include "llvm/Support/ErrorHandling.h"
19#include "llvm/Target/TargetMachine.h"
20#include <cassert>
21
22namespace llvm {
23
24class ARMBaseTargetMachine;
25class FunctionPass;
26class JITCodeEmitter;
27class formatted_raw_ostream;
28
29// Enums corresponding to ARM condition codes
30namespace ARMCC {
31  // The CondCodes constants map directly to the 4-bit encoding of the
32  // condition field for predicated instructions.
33  enum CondCodes { // Meaning (integer)          Meaning (floating-point)
34    EQ,            // Equal                      Equal
35    NE,            // Not equal                  Not equal, or unordered
36    HS,            // Carry set                  >, ==, or unordered
37    LO,            // Carry clear                Less than
38    MI,            // Minus, negative            Less than
39    PL,            // Plus, positive or zero     >, ==, or unordered
40    VS,            // Overflow                   Unordered
41    VC,            // No overflow                Not unordered
42    HI,            // Unsigned higher            Greater than, or unordered
43    LS,            // Unsigned lower or same     Less than or equal
44    GE,            // Greater than or equal      Greater than or equal
45    LT,            // Less than                  Less than, or unordered
46    GT,            // Greater than               Greater than
47    LE,            // Less than or equal         <, ==, or unordered
48    AL             // Always (unconditional)     Always (unconditional)
49  };
50
51  inline static CondCodes getOppositeCondition(CondCodes CC) {
52    switch (CC) {
53    default: llvm_unreachable("Unknown condition code");
54    case EQ: return NE;
55    case NE: return EQ;
56    case HS: return LO;
57    case LO: return HS;
58    case MI: return PL;
59    case PL: return MI;
60    case VS: return VC;
61    case VC: return VS;
62    case HI: return LS;
63    case LS: return HI;
64    case GE: return LT;
65    case LT: return GE;
66    case GT: return LE;
67    case LE: return GT;
68    }
69  }
70} // namespace ARMCC
71
72inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
73  switch (CC) {
74  default: llvm_unreachable("Unknown condition code");
75  case ARMCC::EQ:  return "eq";
76  case ARMCC::NE:  return "ne";
77  case ARMCC::HS:  return "hs";
78  case ARMCC::LO:  return "lo";
79  case ARMCC::MI:  return "mi";
80  case ARMCC::PL:  return "pl";
81  case ARMCC::VS:  return "vs";
82  case ARMCC::VC:  return "vc";
83  case ARMCC::HI:  return "hi";
84  case ARMCC::LS:  return "ls";
85  case ARMCC::GE:  return "ge";
86  case ARMCC::LT:  return "lt";
87  case ARMCC::GT:  return "gt";
88  case ARMCC::LE:  return "le";
89  case ARMCC::AL:  return "al";
90  }
91}
92
93namespace ARM_MB {
94  // The Memory Barrier Option constants map directly to the 4-bit encoding of
95  // the option field for memory barrier operations.
96  enum MemBOpt {
97    ST    = 14,
98    ISH   = 11,
99    ISHST = 10,
100    NSH   = 7,
101    NSHST = 6,
102    OSH   = 3,
103    OSHST = 2
104  };
105
106  inline static const char *MemBOptToString(unsigned val) {
107    switch (val) {
108    default: llvm_unreachable("Unknown memory opetion");
109    case ST:    return "st";
110    case ISH:   return "ish";
111    case ISHST: return "ishst";
112    case NSH:   return "nsh";
113    case NSHST: return "nshst";
114    case OSH:   return "osh";
115    case OSHST: return "oshst";
116    }
117  }
118} // namespace ARM_MB
119
120FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
121                               CodeGenOpt::Level OptLevel);
122
123FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
124                                          JITCodeEmitter &JCE);
125
126FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
127FunctionPass *createARMExpandPseudoPass();
128FunctionPass *createARMGlobalMergePass(const TargetLowering* tli);
129FunctionPass *createARMConstantIslandPass();
130FunctionPass *createNEONPreAllocPass();
131FunctionPass *createNEONMoveFixPass();
132FunctionPass *createThumb2ITBlockPass();
133FunctionPass *createThumb2SizeReductionPass();
134
135extern Target TheARMTarget, TheThumbTarget;
136
137} // end namespace llvm;
138
139// Defines symbolic names for ARM registers.  This defines a mapping from
140// register name to register number.
141//
142#include "ARMGenRegisterNames.inc"
143
144// Defines symbolic names for the ARM instructions.
145//
146#include "ARMGenInstrNames.inc"
147
148
149#endif
150