ARM.h revision 195340 
1//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the entry points for global functions defined in the LLVM
11// ARM back-end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef TARGET_ARM_H
16#define TARGET_ARM_H
17
18#include "llvm/Target/TargetMachine.h"
19#include <cassert>
20
21namespace llvm {
22
23class ARMBaseTargetMachine;
24class FunctionPass;
25class MachineCodeEmitter;
26class JITCodeEmitter;
27class raw_ostream;
28
29// Enums corresponding to ARM condition codes
30namespace ARMCC {
31  // The CondCodes constants map directly to the 4-bit encoding of the
32  // condition field for predicated instructions.
33  enum CondCodes {
34    EQ,
35    NE,
36    HS,
37    LO,
38    MI,
39    PL,
40    VS,
41    VC,
42    HI,
43    LS,
44    GE,
45    LT,
46    GT,
47    LE,
48    AL
49  };
50
51  inline static CondCodes getOppositeCondition(CondCodes CC){
52    switch (CC) {
53    default: assert(0 && "Unknown condition code");
54    case EQ: return NE;
55    case NE: return EQ;
56    case HS: return LO;
57    case LO: return HS;
58    case MI: return PL;
59    case PL: return MI;
60    case VS: return VC;
61    case VC: return VS;
62    case HI: return LS;
63    case LS: return HI;
64    case GE: return LT;
65    case LT: return GE;
66    case GT: return LE;
67    case LE: return GT;
68    }
69  }
70}
71
72inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
73  switch (CC) {
74  default: assert(0 && "Unknown condition code");
75  case ARMCC::EQ:  return "eq";
76  case ARMCC::NE:  return "ne";
77  case ARMCC::HS:  return "hs";
78  case ARMCC::LO:  return "lo";
79  case ARMCC::MI:  return "mi";
80  case ARMCC::PL:  return "pl";
81  case ARMCC::VS:  return "vs";
82  case ARMCC::VC:  return "vc";
83  case ARMCC::HI:  return "hi";
84  case ARMCC::LS:  return "ls";
85  case ARMCC::GE:  return "ge";
86  case ARMCC::LT:  return "lt";
87  case ARMCC::GT:  return "gt";
88  case ARMCC::LE:  return "le";
89  case ARMCC::AL:  return "al";
90  }
91}
92
93FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM);
94FunctionPass *createARMCodePrinterPass(raw_ostream &O,
95                                       ARMBaseTargetMachine &TM,
96                                       bool Verbose);
97FunctionPass *createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
98                                       MachineCodeEmitter &MCE);
99
100FunctionPass *createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
101                                       MachineCodeEmitter &MCE);
102FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
103                                          JITCodeEmitter &JCE);
104
105FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
106FunctionPass *createARMConstantIslandPass();
107
108} // end namespace llvm;
109
110// Defines symbolic names for ARM registers.  This defines a mapping from
111// register name to register number.
112//
113#include "ARMGenRegisterNames.inc"
114
115// Defines symbolic names for the ARM instructions.
116//
117#include "ARMGenInstrNames.inc"
118
119
120#endif
121