SIDefines.h revision 302408
1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8/// \file 9//===----------------------------------------------------------------------===// 10 11#include "llvm/MC/MCInstrDesc.h" 12 13#ifndef LLVM_LIB_TARGET_R600_SIDEFINES_H 14#define LLVM_LIB_TARGET_R600_SIDEFINES_H 15 16namespace SIInstrFlags { 17// This needs to be kept in sync with the field bits in InstSI. 18enum { 19 SALU = 1 << 3, 20 VALU = 1 << 4, 21 22 SOP1 = 1 << 5, 23 SOP2 = 1 << 6, 24 SOPC = 1 << 7, 25 SOPK = 1 << 8, 26 SOPP = 1 << 9, 27 28 VOP1 = 1 << 10, 29 VOP2 = 1 << 11, 30 VOP3 = 1 << 12, 31 VOPC = 1 << 13, 32 33 MUBUF = 1 << 14, 34 MTBUF = 1 << 15, 35 SMRD = 1 << 16, 36 DS = 1 << 17, 37 MIMG = 1 << 18, 38 FLAT = 1 << 19, 39 WQM = 1 << 20, 40 VGPRSpill = 1 << 21, 41 VOPAsmPrefer32Bit = 1 << 22 42}; 43} 44 45namespace llvm { 46namespace AMDGPU { 47 enum OperandType { 48 /// Operand with register or 32-bit immediate 49 OPERAND_REG_IMM32 = llvm::MCOI::OPERAND_FIRST_TARGET, 50 /// Operand with register or inline constant 51 OPERAND_REG_INLINE_C 52 }; 53} 54} 55 56namespace SIInstrFlags { 57 enum Flags { 58 // First 4 bits are the instruction encoding 59 VM_CNT = 1 << 0, 60 EXP_CNT = 1 << 1, 61 LGKM_CNT = 1 << 2 62 }; 63 64 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 65 // The result is true if any of these tests are true. 66 enum ClassFlags { 67 S_NAN = 1 << 0, // Signaling NaN 68 Q_NAN = 1 << 1, // Quiet NaN 69 N_INFINITY = 1 << 2, // Negative infinity 70 N_NORMAL = 1 << 3, // Negative normal 71 N_SUBNORMAL = 1 << 4, // Negative subnormal 72 N_ZERO = 1 << 5, // Negative zero 73 P_ZERO = 1 << 6, // Positive zero 74 P_SUBNORMAL = 1 << 7, // Positive subnormal 75 P_NORMAL = 1 << 8, // Positive normal 76 P_INFINITY = 1 << 9 // Positive infinity 77 }; 78} 79 80namespace SISrcMods { 81 enum { 82 NEG = 1 << 0, 83 ABS = 1 << 1 84 }; 85} 86 87namespace SIOutMods { 88 enum { 89 NONE = 0, 90 MUL2 = 1, 91 MUL4 = 2, 92 DIV2 = 3 93 }; 94} 95 96#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 97#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 98#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 99#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 100#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 101#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 102#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 103#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 104 105#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 106#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 107#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 108#define C_00B84C_SCRATCH_EN 0xFFFFFFFE 109#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 110#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 111#define C_00B84C_USER_SGPR 0xFFFFFFC1 112#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 113#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 114#define C_00B84C_TGID_X_EN 0xFFFFFF7F 115#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 116#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 117#define C_00B84C_TGID_Y_EN 0xFFFFFEFF 118#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 119#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 120#define C_00B84C_TGID_Z_EN 0xFFFFFDFF 121#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 122#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 123#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 124#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 125#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 126#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 127/* CIK */ 128#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 129#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 130#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 131/* */ 132#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 133#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 134#define C_00B84C_LDS_SIZE 0xFF007FFF 135#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 136#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 137#define C_00B84C_EXCP_EN 138 139#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 140#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 141 142#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 143#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 144#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 145#define C_00B848_VGPRS 0xFFFFFFC0 146#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 147#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 148#define C_00B848_SGPRS 0xFFFFFC3F 149#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 150#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 151#define C_00B848_PRIORITY 0xFFFFF3FF 152#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 153#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 154#define C_00B848_FLOAT_MODE 0xFFF00FFF 155#define S_00B848_PRIV(x) (((x) & 0x1) << 20) 156#define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 157#define C_00B848_PRIV 0xFFEFFFFF 158#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 159#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 160#define C_00B848_DX10_CLAMP 0xFFDFFFFF 161#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 162#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 163#define C_00B848_DEBUG_MODE 0xFFBFFFFF 164#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 165#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 166#define C_00B848_IEEE_MODE 0xFF7FFFFF 167 168 169// Helpers for setting FLOAT_MODE 170#define FP_ROUND_ROUND_TO_NEAREST 0 171#define FP_ROUND_ROUND_TO_INF 1 172#define FP_ROUND_ROUND_TO_NEGINF 2 173#define FP_ROUND_ROUND_TO_ZERO 3 174 175// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 176// precision. 177#define FP_ROUND_MODE_SP(x) ((x) & 0x3) 178#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 179 180#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 181#define FP_DENORM_FLUSH_OUT 1 182#define FP_DENORM_FLUSH_IN 2 183#define FP_DENORM_FLUSH_NONE 3 184 185 186// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 187// precision. 188#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 189#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 190 191#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 192#define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 193 194#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 195#define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 196 197 198#endif 199