1284677Sdim//===-- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI -------*- C++ -*-===// 2284677Sdim// 3284677Sdim// The LLVM Compiler Infrastructure 4284677Sdim// 5284677Sdim// This file is distributed under the University of Illinois Open Source 6284677Sdim// License. See LICENSE.TXT for details. 7284677Sdim// 8284677Sdim//===----------------------------------------------------------------------===// 9284677Sdim/// \file 10284677Sdim/// This file a TargetTransformInfo::Concept conforming object specific to the 11284677Sdim/// AMDGPU target machine. It uses the target's detailed information to 12284677Sdim/// provide more precise answers to certain TTI queries, while letting the 13284677Sdim/// target independent and default TTI implementations handle the rest. 14284677Sdim/// 15284677Sdim//===----------------------------------------------------------------------===// 16284677Sdim 17284677Sdim#ifndef LLVM_LIB_TARGET_R600_AMDGPUTARGETTRANSFORMINFO_H 18284677Sdim#define LLVM_LIB_TARGET_R600_AMDGPUTARGETTRANSFORMINFO_H 19284677Sdim 20284677Sdim#include "AMDGPU.h" 21284677Sdim#include "AMDGPUTargetMachine.h" 22284677Sdim#include "llvm/Analysis/TargetTransformInfo.h" 23284677Sdim#include "llvm/CodeGen/BasicTTIImpl.h" 24284677Sdim#include "llvm/Target/TargetLowering.h" 25284677Sdim 26284677Sdimnamespace llvm { 27284677Sdim 28284677Sdimclass AMDGPUTTIImpl : public BasicTTIImplBase<AMDGPUTTIImpl> { 29284677Sdim typedef BasicTTIImplBase<AMDGPUTTIImpl> BaseT; 30284677Sdim typedef TargetTransformInfo TTI; 31284677Sdim friend BaseT; 32284677Sdim 33284677Sdim const AMDGPUSubtarget *ST; 34284677Sdim const AMDGPUTargetLowering *TLI; 35284677Sdim 36284677Sdim const AMDGPUSubtarget *getST() const { return ST; } 37284677Sdim const AMDGPUTargetLowering *getTLI() const { return TLI; } 38284677Sdim 39284677Sdimpublic: 40286684Sdim explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const DataLayout &DL) 41286684Sdim : BaseT(TM, DL), ST(TM->getSubtargetImpl()), 42286684Sdim TLI(ST->getTargetLowering()) {} 43284677Sdim 44284677Sdim // Provide value semantics. MSVC requires that we spell all of these out. 45284677Sdim AMDGPUTTIImpl(const AMDGPUTTIImpl &Arg) 46284677Sdim : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} 47284677Sdim AMDGPUTTIImpl(AMDGPUTTIImpl &&Arg) 48284677Sdim : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)), 49284677Sdim TLI(std::move(Arg.TLI)) {} 50284677Sdim 51284677Sdim bool hasBranchDivergence() { return true; } 52284677Sdim 53284677Sdim void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP); 54284677Sdim 55284677Sdim TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) { 56284677Sdim assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 57284677Sdim return ST->hasBCNT(TyWidth) ? TTI::PSK_FastHardware : TTI::PSK_Software; 58284677Sdim } 59284677Sdim 60284677Sdim unsigned getNumberOfRegisters(bool Vector); 61284677Sdim unsigned getRegisterBitWidth(bool Vector); 62284677Sdim unsigned getMaxInterleaveFactor(unsigned VF); 63296417Sdim 64296417Sdim unsigned getCFInstrCost(unsigned Opcode); 65296417Sdim 66296417Sdim int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index); 67296417Sdim bool isSourceOfDivergence(const Value *V) const; 68284677Sdim}; 69284677Sdim 70284677Sdim} // end namespace llvm 71284677Sdim 72284677Sdim#endif 73