AMDGPUISelLowering.h revision 303975
165532Snectar//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===// 265532Snectar// 365532Snectar// The LLVM Compiler Infrastructure 465532Snectar// 565532Snectar// This file is distributed under the University of Illinois Open Source 665532Snectar// License. See LICENSE.TXT for details. 765532Snectar// 865532Snectar//===----------------------------------------------------------------------===// 965532Snectar// 1065532Snectar/// \file 1165532Snectar/// \brief Interface definition of the TargetLowering class that is common 1265532Snectar/// to all AMD GPUs. 1365532Snectar// 1465532Snectar//===----------------------------------------------------------------------===// 1565532Snectar 1665532Snectar#ifndef LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H 1765532Snectar#define LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H 1865532Snectar 1965532Snectar#include "llvm/Target/TargetLowering.h" 2065532Snectar 2165532Snectarnamespace llvm { 2265532Snectar 2365532Snectarclass AMDGPUMachineFunction; 2465532Snectarclass AMDGPUSubtarget; 2565532Snectarclass MachineRegisterInfo; 2665532Snectar 2765532Snectarclass AMDGPUTargetLowering : public TargetLowering { 2865532Snectarprotected: 2965532Snectar const AMDGPUSubtarget *Subtarget; 3065532Snectar 3165532Snectarprivate: 3265532Snectar SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV, 3365532Snectar const SDValue &InitPtr, 3465532Snectar SDValue Chain, 3565532Snectar SelectionDAG &DAG) const; 3665532Snectar SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const; 3765532Snectar SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 3865532Snectar SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 3965532Snectar SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 4065532Snectar /// \brief Lower vector stores by merging the vector elements into an integer 4165532Snectar /// of the same bitwidth. 4265532Snectar SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const; 4365532Snectar /// \brief Split a vector store into multiple scalar stores. 4465532Snectar /// \returns The resulting chain. 4565532Snectar 4665532Snectar SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const; 4765532Snectar SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const; 4892986Sobrien SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const; 4965532Snectar SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const; 5092986Sobrien SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const; 5192986Sobrien 5292986Sobrien SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const; 5365532Snectar SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const; 5465532Snectar SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const; 5565532Snectar SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const; 5665532Snectar 5765532Snectar SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const; 5865532Snectar 5965532Snectar SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const; 6065532Snectar SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const; 6165532Snectar SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 6265532Snectar SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 6365532Snectar 6465532Snectar SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const; 6565532Snectar SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 6666451Snectar SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 6765532Snectar 6865532Snectar SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 6965532Snectar 7065532Snectar SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const; 7165532Snectar SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const; 7265532Snectar SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const; 7365532Snectar SDValue performCtlzCombine(SDLoc SL, SDValue Cond, SDValue LHS, SDValue RHS, 7465532Snectar DAGCombinerInfo &DCI) const; 7565532Snectar SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const; 7692905Sobrien 7792905Sobrienprotected: 7892905Sobrien static EVT getEquivalentMemType(LLVMContext &Context, EVT VT); 7992905Sobrien static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT); 8065532Snectar 8165532Snectar virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 8265532Snectar SelectionDAG &DAG) const; 8365532Snectar 8465532Snectar /// \brief Split a vector load into a scalar load of each component. 8565532Snectar SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const; 8665532Snectar 8765532Snectar /// \brief Split a vector load into 2 loads of half the vector. 8865532Snectar SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const; 8965532Snectar 9065532Snectar /// \brief Split a vector store into a scalar store of each component. 9165532Snectar SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const; 9265532Snectar 9365532Snectar /// \brief Split a vector store into 2 stores of half the vector. 9465532Snectar SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const; 9565532Snectar 9666485Snectar SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 9766451Snectar SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 9866451Snectar SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 9966451Snectar SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 10065532Snectar SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const; 10165532Snectar void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, 10265532Snectar SmallVectorImpl<SDValue> &Results) const; 10365532Snectar bool isHWTrueValue(SDValue Op) const; 10465532Snectar bool isHWFalseValue(SDValue Op) const; 10565532Snectar 10665532Snectar /// The SelectionDAGBuilder will automatically promote function arguments 10766485Snectar /// with illegal types. However, this does not work for the AMDGPU targets 10866451Snectar /// since the function arguments are stored in memory as these illegal types. 10966451Snectar /// In order to handle this properly we need to get the origianl types sizes 11066451Snectar /// from the LLVM IR Function and fixup the ISD:InputArg values before 11165532Snectar /// passing them to AnalyzeFormalArguments() 11265532Snectar void getOriginalFunctionArgs(SelectionDAG &DAG, 11365532Snectar const Function *F, 11465532Snectar const SmallVectorImpl<ISD::InputArg> &Ins, 11565532Snectar SmallVectorImpl<ISD::InputArg> &OrigIns) const; 11665532Snectar void AnalyzeFormalArguments(CCState &State, 11765532Snectar const SmallVectorImpl<ISD::InputArg> &Ins) const; 11865532Snectar void AnalyzeReturn(CCState &State, 11965532Snectar const SmallVectorImpl<ISD::OutputArg> &Outs) const; 12065532Snectar 12165532Snectarpublic: 12265532Snectar AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI); 12365532Snectar 12465532Snectar bool isFAbsFree(EVT VT) const override; 12565532Snectar bool isFNegFree(EVT VT) const override; 12665532Snectar bool isTruncateFree(EVT Src, EVT Dest) const override; 12765532Snectar bool isTruncateFree(Type *Src, Type *Dest) const override; 12865532Snectar 12965532Snectar bool isZExtFree(Type *Src, Type *Dest) const override; 13065532Snectar bool isZExtFree(EVT Src, EVT Dest) const override; 13165532Snectar bool isZExtFree(SDValue Val, EVT VT2) const override; 13265532Snectar 13365532Snectar bool isNarrowingProfitable(EVT VT1, EVT VT2) const override; 13465532Snectar 13565532Snectar MVT getVectorIdxTy(const DataLayout &) const override; 13665532Snectar bool isSelectSupported(SelectSupportKind) const override; 13765532Snectar 13865532Snectar bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 13965532Snectar bool ShouldShrinkFPConstant(EVT VT) const override; 14065532Snectar bool shouldReduceLoadWidth(SDNode *Load, 14165532Snectar ISD::LoadExtType ExtType, 14265532Snectar EVT ExtVT) const override; 14365532Snectar 14465532Snectar bool isLoadBitCastBeneficial(EVT, EVT) const override; 14565532Snectar 14665532Snectar bool storeOfVectorConstantIsCheap(EVT MemVT, 14765532Snectar unsigned NumElem, 14865532Snectar unsigned AS) const override; 14965532Snectar bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override; 15065532Snectar bool isCheapToSpeculateCttz() const override; 15165532Snectar bool isCheapToSpeculateCtlz() const override; 15265532Snectar 15365532Snectar SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, 15465532Snectar bool isVarArg, 15565532Snectar const SmallVectorImpl<ISD::OutputArg> &Outs, 15665532Snectar const SmallVectorImpl<SDValue> &OutVals, 15765532Snectar SDLoc DL, SelectionDAG &DAG) const override; 15865532Snectar SDValue LowerCall(CallLoweringInfo &CLI, 15965532Snectar SmallVectorImpl<SDValue> &InVals) const override; 16065532Snectar 16165532Snectar SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, 16265532Snectar SelectionDAG &DAG) const; 16365532Snectar 16465532Snectar SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 16565532Snectar SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 166114443Snectar void ReplaceNodeResults(SDNode * N, 16771929Snectar SmallVectorImpl<SDValue> &Results, 16871929Snectar SelectionDAG &DAG) const override; 16971929Snectar 17065532Snectar SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const; 17165532Snectar SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; 17265532Snectar SDValue CombineFMinMaxLegacy(SDLoc DL, 17365532Snectar EVT VT, 17465532Snectar SDValue LHS, 17565532Snectar SDValue RHS, 17665532Snectar SDValue True, 17765532Snectar SDValue False, 17865532Snectar SDValue CC, 17965532Snectar DAGCombinerInfo &DCI) const; 18065532Snectar 18165532Snectar const char* getTargetNodeName(unsigned Opcode) const override; 18265532Snectar 18365532Snectar SDValue getRsqrtEstimate(SDValue Operand, 18465532Snectar DAGCombinerInfo &DCI, 18565532Snectar unsigned &RefinementSteps, 18665532Snectar bool &UseOneConstNR) const override; 18765532Snectar SDValue getRecipEstimate(SDValue Operand, 18865532Snectar DAGCombinerInfo &DCI, 18965532Snectar unsigned &RefinementSteps) const override; 19065532Snectar 19165532Snectar virtual SDNode *PostISelFolding(MachineSDNode *N, 19265532Snectar SelectionDAG &DAG) const { 19365532Snectar return N; 19465532Snectar } 19565532Snectar 19665532Snectar /// \brief Determine which of the bits specified in \p Mask are known to be 19765532Snectar /// either zero or one and return them in the \p KnownZero and \p KnownOne 19865532Snectar /// bitsets. 19965532Snectar void computeKnownBitsForTargetNode(const SDValue Op, 20065532Snectar APInt &KnownZero, 20165532Snectar APInt &KnownOne, 20265532Snectar const SelectionDAG &DAG, 20365532Snectar unsigned Depth = 0) const override; 20465532Snectar 20565532Snectar unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, 20665532Snectar unsigned Depth = 0) const override; 20765532Snectar 20865532Snectar /// \brief Helper function that adds Reg to the LiveIn list of the DAG's 20965532Snectar /// MachineFunction. 21065532Snectar /// 21165532Snectar /// \returns a RegisterSDNode representing Reg. 21265532Snectar virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, 21365532Snectar const TargetRegisterClass *RC, 21465532Snectar unsigned Reg, EVT VT) const; 21565532Snectar 21665532Snectar enum ImplicitParameter { 21765532Snectar GRID_DIM, 21865532Snectar GRID_OFFSET 21965532Snectar }; 22065532Snectar 22165532Snectar /// \brief Helper function that returns the byte offset of the given 22265532Snectar /// type of implicit parameter. 22365532Snectar uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, 22465532Snectar const ImplicitParameter Param) const; 22565532Snectar}; 22665532Snectar 22765532Snectarnamespace AMDGPUISD { 22865532Snectar 22965532Snectarenum NodeType : unsigned { 23065532Snectar // AMDIL ISD Opcodes 23165532Snectar FIRST_NUMBER = ISD::BUILTIN_OP_END, 23265532Snectar CALL, // Function call based on a single integer 23365532Snectar UMUL, // 32bit unsigned multiplication 23465532Snectar RET_FLAG, 23565532Snectar BRANCH_COND, 23665532Snectar // End AMDIL ISD Opcodes 23765532Snectar DWORDADDR, 23865532Snectar FRACT, 23965532Snectar CLAMP, 24065532Snectar 24165532Snectar // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi. 24265532Snectar // Denormals handled on some parts. 24365532Snectar COS_HW, 24465532Snectar SIN_HW, 24565532Snectar FMAX_LEGACY, 24665532Snectar FMIN_LEGACY, 24765532Snectar FMAX3, 24865532Snectar SMAX3, 24965532Snectar UMAX3, 25065532Snectar FMIN3, 25165532Snectar SMIN3, 25265532Snectar UMIN3, 25365532Snectar URECIP, 25465532Snectar DIV_SCALE, 25565532Snectar DIV_FMAS, 25665532Snectar DIV_FIXUP, 25765532Snectar TRIG_PREOP, // 1 ULP max error for f64 25865532Snectar 25965532Snectar // RCP, RSQ - For f32, 1 ULP max error, no denormal handling. 26065532Snectar // For f64, max error 2^29 ULP, handles denormals. 26165532Snectar RCP, 26265532Snectar RSQ, 26365532Snectar RSQ_LEGACY, 26465532Snectar RSQ_CLAMPED, 26565532Snectar LDEXP, 26665532Snectar FP_CLASS, 26765532Snectar DOT4, 26865532Snectar CARRY, 26965532Snectar BORROW, 27065532Snectar BFE_U32, // Extract range of bits with zero extension to 32-bits. 27165532Snectar BFE_I32, // Extract range of bits with sign extension to 32-bits. 27265532Snectar BFI, // (src0 & src1) | (~src0 & src2) 27365532Snectar BFM, // Insert a range of bits into a 32-bit word. 27465532Snectar FFBH_U32, // ctlz with -1 if input is zero. 27565532Snectar MUL_U24, 27665532Snectar MUL_I24, 27765532Snectar MAD_U24, 27865532Snectar MAD_I24, 27965532Snectar TEXTURE_FETCH, 28065532Snectar EXPORT, 28165532Snectar CONST_ADDRESS, 28265532Snectar REGISTER_LOAD, 28365532Snectar REGISTER_STORE, 28465532Snectar LOAD_INPUT, 28565532Snectar SAMPLE, 28665532Snectar SAMPLEB, 28765532Snectar SAMPLED, 28865532Snectar SAMPLEL, 289254700Sjilles 29065532Snectar // These cvt_f32_ubyte* nodes need to remain consecutive and in order. 29165532Snectar CVT_F32_UBYTE0, 29265532Snectar CVT_F32_UBYTE1, 29365532Snectar CVT_F32_UBYTE2, 29465532Snectar CVT_F32_UBYTE3, 29565532Snectar /// This node is for VLIW targets and it is used to represent a vector 29665532Snectar /// that is stored in consecutive registers with the same channel. 29765532Snectar /// For example: 29865532Snectar /// |X |Y|Z|W| 29965532Snectar /// T0|v.x| | | | 30065532Snectar /// T1|v.y| | | | 30165532Snectar /// T2|v.z| | | | 30265532Snectar /// T3|v.w| | | | 30365532Snectar BUILD_VERTICAL_VECTOR, 30465532Snectar /// Pointer to the start of the shader's constant data. 30565532Snectar CONST_DATA_PTR, 30665532Snectar SENDMSG, 30765532Snectar INTERP_MOV, 30865532Snectar INTERP_P1, 30965532Snectar INTERP_P2, 31065532Snectar FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE, 31165532Snectar STORE_MSKOR, 31265532Snectar LOAD_CONSTANT, 31365532Snectar TBUFFER_STORE_FORMAT, 31465532Snectar LAST_AMDGPU_ISD_NUMBER 31565532Snectar}; 31665532Snectar 31765532Snectar 31865532Snectar} // End namespace AMDGPUISD 31965532Snectar 32065532Snectar} // End namespace llvm 32165532Snectar 32265532Snectar#endif 32365532Snectar