AMDGPUISelLowering.h revision 296417 
1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition of the TargetLowering class that is common
12/// to all AMD GPUs.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
17#define LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
18
19#include "llvm/Target/TargetLowering.h"
20
21namespace llvm {
22
23class AMDGPUMachineFunction;
24class AMDGPUSubtarget;
25class MachineRegisterInfo;
26
27class AMDGPUTargetLowering : public TargetLowering {
28protected:
29  const AMDGPUSubtarget *Subtarget;
30
31private:
32  SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33                                   const SDValue &InitPtr,
34                                   SDValue Chain,
35                                   SelectionDAG &DAG) const;
36  SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40  /// \brief Lower vector stores by merging the vector elements into an integer
41  /// of the same bitwidth.
42  SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
43  /// \brief Split a vector store into multiple scalar stores.
44  /// \returns The resulting chain.
45
46  SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
47  SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
48  SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
49  SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
50  SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
51
52  SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
53  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
54  SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
55  SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
56
57  SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
58
59  SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
60  SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
61  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
62  SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
63
64  SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
65  SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
66  SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
67
68  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
69
70  SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
71  SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
72  SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
73  SDValue performCtlzCombine(SDLoc SL, SDValue Cond, SDValue LHS, SDValue RHS,
74                             DAGCombinerInfo &DCI) const;
75  SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
76
77protected:
78  static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
79  static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
80
81  virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
82                                     SelectionDAG &DAG) const;
83
84  /// \brief Split a vector load into a scalar load of each component.
85  SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const;
86
87  /// \brief Split a vector load into 2 loads of half the vector.
88  SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
89
90  /// \brief Split a vector store into a scalar store of each component.
91  SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const;
92
93  /// \brief Split a vector store into 2 stores of half the vector.
94  SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
95
96  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
97  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
98  SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
99  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
100  SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
101  void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
102                                    SmallVectorImpl<SDValue> &Results) const;
103  bool isHWTrueValue(SDValue Op) const;
104  bool isHWFalseValue(SDValue Op) const;
105
106  /// The SelectionDAGBuilder will automatically promote function arguments
107  /// with illegal types.  However, this does not work for the AMDGPU targets
108  /// since the function arguments are stored in memory as these illegal types.
109  /// In order to handle this properly we need to get the origianl types sizes
110  /// from the LLVM IR Function and fixup the ISD:InputArg values before
111  /// passing them to AnalyzeFormalArguments()
112  void getOriginalFunctionArgs(SelectionDAG &DAG,
113                               const Function *F,
114                               const SmallVectorImpl<ISD::InputArg> &Ins,
115                               SmallVectorImpl<ISD::InputArg> &OrigIns) const;
116  void AnalyzeFormalArguments(CCState &State,
117                              const SmallVectorImpl<ISD::InputArg> &Ins) const;
118  void AnalyzeReturn(CCState &State,
119                     const SmallVectorImpl<ISD::OutputArg> &Outs) const;
120
121public:
122  AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI);
123
124  bool isFAbsFree(EVT VT) const override;
125  bool isFNegFree(EVT VT) const override;
126  bool isTruncateFree(EVT Src, EVT Dest) const override;
127  bool isTruncateFree(Type *Src, Type *Dest) const override;
128
129  bool isZExtFree(Type *Src, Type *Dest) const override;
130  bool isZExtFree(EVT Src, EVT Dest) const override;
131  bool isZExtFree(SDValue Val, EVT VT2) const override;
132
133  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
134
135  MVT getVectorIdxTy(const DataLayout &) const override;
136  bool isSelectSupported(SelectSupportKind) const override;
137
138  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
139  bool ShouldShrinkFPConstant(EVT VT) const override;
140  bool shouldReduceLoadWidth(SDNode *Load,
141                             ISD::LoadExtType ExtType,
142                             EVT ExtVT) const override;
143
144  bool isLoadBitCastBeneficial(EVT, EVT) const override;
145
146  bool storeOfVectorConstantIsCheap(EVT MemVT,
147                                    unsigned NumElem,
148                                    unsigned AS) const override;
149  bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
150  bool isCheapToSpeculateCttz() const override;
151  bool isCheapToSpeculateCtlz() const override;
152
153  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
154                      bool isVarArg,
155                      const SmallVectorImpl<ISD::OutputArg> &Outs,
156                      const SmallVectorImpl<SDValue> &OutVals,
157                      SDLoc DL, SelectionDAG &DAG) const override;
158  SDValue LowerCall(CallLoweringInfo &CLI,
159                    SmallVectorImpl<SDValue> &InVals) const override;
160
161  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
162                                  SelectionDAG &DAG) const;
163
164  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
165  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
166  void ReplaceNodeResults(SDNode * N,
167                          SmallVectorImpl<SDValue> &Results,
168                          SelectionDAG &DAG) const override;
169
170  SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
171  SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
172  SDValue CombineFMinMaxLegacy(SDLoc DL,
173                               EVT VT,
174                               SDValue LHS,
175                               SDValue RHS,
176                               SDValue True,
177                               SDValue False,
178                               SDValue CC,
179                               DAGCombinerInfo &DCI) const;
180
181  const char* getTargetNodeName(unsigned Opcode) const override;
182
183  SDValue getRsqrtEstimate(SDValue Operand,
184                           DAGCombinerInfo &DCI,
185                           unsigned &RefinementSteps,
186                           bool &UseOneConstNR) const override;
187  SDValue getRecipEstimate(SDValue Operand,
188                           DAGCombinerInfo &DCI,
189                           unsigned &RefinementSteps) const override;
190
191  virtual SDNode *PostISelFolding(MachineSDNode *N,
192                                  SelectionDAG &DAG) const {
193    return N;
194  }
195
196  /// \brief Determine which of the bits specified in \p Mask are known to be
197  /// either zero or one and return them in the \p KnownZero and \p KnownOne
198  /// bitsets.
199  void computeKnownBitsForTargetNode(const SDValue Op,
200                                     APInt &KnownZero,
201                                     APInt &KnownOne,
202                                     const SelectionDAG &DAG,
203                                     unsigned Depth = 0) const override;
204
205  unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
206                                           unsigned Depth = 0) const override;
207
208  /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
209  /// MachineFunction.
210  ///
211  /// \returns a RegisterSDNode representing Reg.
212  virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
213                                       const TargetRegisterClass *RC,
214                                       unsigned Reg, EVT VT) const;
215
216  enum ImplicitParameter {
217    GRID_DIM,
218    GRID_OFFSET
219  };
220
221  /// \brief Helper function that returns the byte offset of the given
222  /// type of implicit parameter.
223  uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
224                                      const ImplicitParameter Param) const;
225};
226
227namespace AMDGPUISD {
228
229enum NodeType : unsigned {
230  // AMDIL ISD Opcodes
231  FIRST_NUMBER = ISD::BUILTIN_OP_END,
232  CALL,        // Function call based on a single integer
233  UMUL,        // 32bit unsigned multiplication
234  RET_FLAG,
235  BRANCH_COND,
236  // End AMDIL ISD Opcodes
237  DWORDADDR,
238  FRACT,
239  CLAMP,
240
241  // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
242  // Denormals handled on some parts.
243  COS_HW,
244  SIN_HW,
245  FMAX_LEGACY,
246  FMIN_LEGACY,
247  FMAX3,
248  SMAX3,
249  UMAX3,
250  FMIN3,
251  SMIN3,
252  UMIN3,
253  URECIP,
254  DIV_SCALE,
255  DIV_FMAS,
256  DIV_FIXUP,
257  TRIG_PREOP, // 1 ULP max error for f64
258
259  // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
260  //            For f64, max error 2^29 ULP, handles denormals.
261  RCP,
262  RSQ,
263  RSQ_LEGACY,
264  RSQ_CLAMPED,
265  LDEXP,
266  FP_CLASS,
267  DOT4,
268  CARRY,
269  BORROW,
270  BFE_U32, // Extract range of bits with zero extension to 32-bits.
271  BFE_I32, // Extract range of bits with sign extension to 32-bits.
272  BFI, // (src0 & src1) | (~src0 & src2)
273  BFM, // Insert a range of bits into a 32-bit word.
274  FFBH_U32, // ctlz with -1 if input is zero.
275  MUL_U24,
276  MUL_I24,
277  MAD_U24,
278  MAD_I24,
279  TEXTURE_FETCH,
280  EXPORT,
281  CONST_ADDRESS,
282  REGISTER_LOAD,
283  REGISTER_STORE,
284  LOAD_INPUT,
285  SAMPLE,
286  SAMPLEB,
287  SAMPLED,
288  SAMPLEL,
289
290  // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
291  CVT_F32_UBYTE0,
292  CVT_F32_UBYTE1,
293  CVT_F32_UBYTE2,
294  CVT_F32_UBYTE3,
295  /// This node is for VLIW targets and it is used to represent a vector
296  /// that is stored in consecutive registers with the same channel.
297  /// For example:
298  ///   |X  |Y|Z|W|
299  /// T0|v.x| | | |
300  /// T1|v.y| | | |
301  /// T2|v.z| | | |
302  /// T3|v.w| | | |
303  BUILD_VERTICAL_VECTOR,
304  /// Pointer to the start of the shader's constant data.
305  CONST_DATA_PTR,
306  SENDMSG,
307  INTERP_MOV,
308  INTERP_P1,
309  INTERP_P2,
310  FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
311  STORE_MSKOR,
312  LOAD_CONSTANT,
313  TBUFFER_STORE_FORMAT,
314  LAST_AMDGPU_ISD_NUMBER
315};
316
317
318} // End namespace AMDGPUISD
319
320} // End namespace llvm
321
322#endif
323