AMDGPUISelLowering.h revision 286684 
1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition of the TargetLowering class that is common
12/// to all AMD GPUs.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
17#define LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
18
19#include "llvm/Target/TargetLowering.h"
20
21namespace llvm {
22
23class AMDGPUMachineFunction;
24class AMDGPUSubtarget;
25class MachineRegisterInfo;
26
27class AMDGPUTargetLowering : public TargetLowering {
28protected:
29  const AMDGPUSubtarget *Subtarget;
30
31private:
32  SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33                                   const SDValue &InitPtr,
34                                   SDValue Chain,
35                                   SelectionDAG &DAG) const;
36  SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40  /// \brief Lower vector stores by merging the vector elements into an integer
41  /// of the same bitwidth.
42  SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
43  /// \brief Split a vector store into multiple scalar stores.
44  /// \returns The resulting chain.
45
46  SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
47  SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
48  SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
49  SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
50  SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
51
52  SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
53  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
54  SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
55  SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
56
57  SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
59  SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
60
61  SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
62  SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
63  SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
64
65  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
66
67  SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
68  SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
69  SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
70
71protected:
72  static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
73  static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
74
75  virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
76                                     SelectionDAG &DAG) const;
77
78  /// \brief Split a vector load into a scalar load of each component.
79  SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const;
80
81  /// \brief Split a vector load into 2 loads of half the vector.
82  SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
83
84  /// \brief Split a vector store into a scalar store of each component.
85  SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const;
86
87  /// \brief Split a vector store into 2 stores of half the vector.
88  SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
89
90  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
91  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
92  SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
93  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
94  SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
95  void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
96                                    SmallVectorImpl<SDValue> &Results) const;
97  bool isHWTrueValue(SDValue Op) const;
98  bool isHWFalseValue(SDValue Op) const;
99
100  /// The SelectionDAGBuilder will automatically promote function arguments
101  /// with illegal types.  However, this does not work for the AMDGPU targets
102  /// since the function arguments are stored in memory as these illegal types.
103  /// In order to handle this properly we need to get the origianl types sizes
104  /// from the LLVM IR Function and fixup the ISD:InputArg values before
105  /// passing them to AnalyzeFormalArguments()
106  void getOriginalFunctionArgs(SelectionDAG &DAG,
107                               const Function *F,
108                               const SmallVectorImpl<ISD::InputArg> &Ins,
109                               SmallVectorImpl<ISD::InputArg> &OrigIns) const;
110  void AnalyzeFormalArguments(CCState &State,
111                              const SmallVectorImpl<ISD::InputArg> &Ins) const;
112
113public:
114  AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI);
115
116  bool isFAbsFree(EVT VT) const override;
117  bool isFNegFree(EVT VT) const override;
118  bool isTruncateFree(EVT Src, EVT Dest) const override;
119  bool isTruncateFree(Type *Src, Type *Dest) const override;
120
121  bool isZExtFree(Type *Src, Type *Dest) const override;
122  bool isZExtFree(EVT Src, EVT Dest) const override;
123  bool isZExtFree(SDValue Val, EVT VT2) const override;
124
125  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
126
127  MVT getVectorIdxTy(const DataLayout &) const override;
128  bool isSelectSupported(SelectSupportKind) const override;
129
130  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
131  bool ShouldShrinkFPConstant(EVT VT) const override;
132  bool shouldReduceLoadWidth(SDNode *Load,
133                             ISD::LoadExtType ExtType,
134                             EVT ExtVT) const override;
135
136  bool isLoadBitCastBeneficial(EVT, EVT) const override;
137
138  bool storeOfVectorConstantIsCheap(EVT MemVT,
139                                    unsigned NumElem,
140                                    unsigned AS) const override;
141  bool isCheapToSpeculateCttz() const override;
142  bool isCheapToSpeculateCtlz() const override;
143
144  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
145                      bool isVarArg,
146                      const SmallVectorImpl<ISD::OutputArg> &Outs,
147                      const SmallVectorImpl<SDValue> &OutVals,
148                      SDLoc DL, SelectionDAG &DAG) const override;
149  SDValue LowerCall(CallLoweringInfo &CLI,
150                    SmallVectorImpl<SDValue> &InVals) const override;
151
152  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
153  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
154  void ReplaceNodeResults(SDNode * N,
155                          SmallVectorImpl<SDValue> &Results,
156                          SelectionDAG &DAG) const override;
157
158  SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
159  SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
160  SDValue CombineFMinMaxLegacy(SDLoc DL,
161                               EVT VT,
162                               SDValue LHS,
163                               SDValue RHS,
164                               SDValue True,
165                               SDValue False,
166                               SDValue CC,
167                               DAGCombinerInfo &DCI) const;
168  SDValue CombineIMinMax(SDLoc DL,
169                         EVT VT,
170                         SDValue LHS,
171                         SDValue RHS,
172                         SDValue True,
173                         SDValue False,
174                         SDValue CC,
175                         SelectionDAG &DAG) const;
176
177  const char* getTargetNodeName(unsigned Opcode) const override;
178
179  SDValue getRsqrtEstimate(SDValue Operand,
180                           DAGCombinerInfo &DCI,
181                           unsigned &RefinementSteps,
182                           bool &UseOneConstNR) const override;
183  SDValue getRecipEstimate(SDValue Operand,
184                           DAGCombinerInfo &DCI,
185                           unsigned &RefinementSteps) const override;
186
187  virtual SDNode *PostISelFolding(MachineSDNode *N,
188                                  SelectionDAG &DAG) const {
189    return N;
190  }
191
192  /// \brief Determine which of the bits specified in \p Mask are known to be
193  /// either zero or one and return them in the \p KnownZero and \p KnownOne
194  /// bitsets.
195  void computeKnownBitsForTargetNode(const SDValue Op,
196                                     APInt &KnownZero,
197                                     APInt &KnownOne,
198                                     const SelectionDAG &DAG,
199                                     unsigned Depth = 0) const override;
200
201  unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
202                                           unsigned Depth = 0) const override;
203
204  /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
205  /// MachineFunction.
206  ///
207  /// \returns a RegisterSDNode representing Reg.
208  virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
209                                       const TargetRegisterClass *RC,
210                                       unsigned Reg, EVT VT) const;
211
212  enum ImplicitParameter {
213    GRID_DIM,
214    GRID_OFFSET
215  };
216
217  /// \brief Helper function that returns the byte offset of the given
218  /// type of implicit parameter.
219  unsigned getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
220                                      const ImplicitParameter Param) const;
221};
222
223namespace AMDGPUISD {
224
225enum NodeType : unsigned {
226  // AMDIL ISD Opcodes
227  FIRST_NUMBER = ISD::BUILTIN_OP_END,
228  CALL,        // Function call based on a single integer
229  UMUL,        // 32bit unsigned multiplication
230  RET_FLAG,
231  BRANCH_COND,
232  // End AMDIL ISD Opcodes
233  DWORDADDR,
234  FRACT,
235  CLAMP,
236
237  // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
238  // Denormals handled on some parts.
239  COS_HW,
240  SIN_HW,
241  FMAX_LEGACY,
242  FMIN_LEGACY,
243  FMAX3,
244  SMAX3,
245  UMAX3,
246  FMIN3,
247  SMIN3,
248  UMIN3,
249  URECIP,
250  DIV_SCALE,
251  DIV_FMAS,
252  DIV_FIXUP,
253  TRIG_PREOP, // 1 ULP max error for f64
254
255  // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
256  //            For f64, max error 2^29 ULP, handles denormals.
257  RCP,
258  RSQ,
259  RSQ_LEGACY,
260  RSQ_CLAMPED,
261  LDEXP,
262  FP_CLASS,
263  DOT4,
264  CARRY,
265  BORROW,
266  BFE_U32, // Extract range of bits with zero extension to 32-bits.
267  BFE_I32, // Extract range of bits with sign extension to 32-bits.
268  BFI, // (src0 & src1) | (~src0 & src2)
269  BFM, // Insert a range of bits into a 32-bit word.
270  BREV, // Reverse bits.
271  MUL_U24,
272  MUL_I24,
273  MAD_U24,
274  MAD_I24,
275  TEXTURE_FETCH,
276  EXPORT,
277  CONST_ADDRESS,
278  REGISTER_LOAD,
279  REGISTER_STORE,
280  LOAD_INPUT,
281  SAMPLE,
282  SAMPLEB,
283  SAMPLED,
284  SAMPLEL,
285
286  // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
287  CVT_F32_UBYTE0,
288  CVT_F32_UBYTE1,
289  CVT_F32_UBYTE2,
290  CVT_F32_UBYTE3,
291  /// This node is for VLIW targets and it is used to represent a vector
292  /// that is stored in consecutive registers with the same channel.
293  /// For example:
294  ///   |X  |Y|Z|W|
295  /// T0|v.x| | | |
296  /// T1|v.y| | | |
297  /// T2|v.z| | | |
298  /// T3|v.w| | | |
299  BUILD_VERTICAL_VECTOR,
300  /// Pointer to the start of the shader's constant data.
301  CONST_DATA_PTR,
302  SENDMSG,
303  INTERP_MOV,
304  INTERP_P1,
305  INTERP_P2,
306  FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
307  STORE_MSKOR,
308  LOAD_CONSTANT,
309  TBUFFER_STORE_FORMAT,
310  LAST_AMDGPU_ISD_NUMBER
311};
312
313
314} // End namespace AMDGPUISD
315
316} // End namespace llvm
317
318#endif
319