AMDGPUISelLowering.h revision 284677 
1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition of the TargetLowering class that is common
12/// to all AMD GPUs.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
17#define LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
18
19#include "llvm/Target/TargetLowering.h"
20
21namespace llvm {
22
23class AMDGPUMachineFunction;
24class AMDGPUSubtarget;
25class MachineRegisterInfo;
26
27class AMDGPUTargetLowering : public TargetLowering {
28protected:
29  const AMDGPUSubtarget *Subtarget;
30
31private:
32  SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33                                   const SDValue &InitPtr,
34                                   SDValue Chain,
35                                   SelectionDAG &DAG) const;
36  SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40  /// \brief Lower vector stores by merging the vector elements into an integer
41  /// of the same bitwidth.
42  SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
43  /// \brief Split a vector store into multiple scalar stores.
44  /// \returns The resulting chain.
45
46  SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
47  SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
48  SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
49  SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
50  SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
51
52  SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
53  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
54  SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
55  SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
56
57  SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
59  SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
60
61  SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
62  SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
63  SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
64
65  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
66
67  SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
68  SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
69
70protected:
71  static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
72  static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
73
74  virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
75                                     SelectionDAG &DAG) const;
76
77  /// \brief Split a vector load into a scalar load of each component.
78  SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const;
79
80  /// \brief Split a vector load into 2 loads of half the vector.
81  SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
82
83  /// \brief Split a vector store into a scalar store of each component.
84  SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const;
85
86  /// \brief Split a vector store into 2 stores of half the vector.
87  SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
88
89  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
90  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
91  SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
92  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
93  SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
94  void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
95                                    SmallVectorImpl<SDValue> &Results) const;
96  bool isHWTrueValue(SDValue Op) const;
97  bool isHWFalseValue(SDValue Op) const;
98
99  /// The SelectionDAGBuilder will automatically promote function arguments
100  /// with illegal types.  However, this does not work for the AMDGPU targets
101  /// since the function arguments are stored in memory as these illegal types.
102  /// In order to handle this properly we need to get the origianl types sizes
103  /// from the LLVM IR Function and fixup the ISD:InputArg values before
104  /// passing them to AnalyzeFormalArguments()
105  void getOriginalFunctionArgs(SelectionDAG &DAG,
106                               const Function *F,
107                               const SmallVectorImpl<ISD::InputArg> &Ins,
108                               SmallVectorImpl<ISD::InputArg> &OrigIns) const;
109  void AnalyzeFormalArguments(CCState &State,
110                              const SmallVectorImpl<ISD::InputArg> &Ins) const;
111
112public:
113  AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI);
114
115  bool isFAbsFree(EVT VT) const override;
116  bool isFNegFree(EVT VT) const override;
117  bool isTruncateFree(EVT Src, EVT Dest) const override;
118  bool isTruncateFree(Type *Src, Type *Dest) const override;
119
120  bool isZExtFree(Type *Src, Type *Dest) const override;
121  bool isZExtFree(EVT Src, EVT Dest) const override;
122  bool isZExtFree(SDValue Val, EVT VT2) const override;
123
124  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
125
126  MVT getVectorIdxTy() const override;
127  bool isSelectSupported(SelectSupportKind) const override;
128
129  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
130  bool ShouldShrinkFPConstant(EVT VT) const override;
131  bool shouldReduceLoadWidth(SDNode *Load,
132                             ISD::LoadExtType ExtType,
133                             EVT ExtVT) const override;
134
135  bool isLoadBitCastBeneficial(EVT, EVT) const override;
136
137  bool storeOfVectorConstantIsCheap(EVT MemVT,
138                                    unsigned NumElem,
139                                    unsigned AS) const override;
140  bool isCheapToSpeculateCttz() const override;
141  bool isCheapToSpeculateCtlz() const override;
142
143  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
144                      bool isVarArg,
145                      const SmallVectorImpl<ISD::OutputArg> &Outs,
146                      const SmallVectorImpl<SDValue> &OutVals,
147                      SDLoc DL, SelectionDAG &DAG) const override;
148  SDValue LowerCall(CallLoweringInfo &CLI,
149                    SmallVectorImpl<SDValue> &InVals) const override;
150
151  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
152  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
153  void ReplaceNodeResults(SDNode * N,
154                          SmallVectorImpl<SDValue> &Results,
155                          SelectionDAG &DAG) const override;
156
157  SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
158  SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
159  SDValue CombineFMinMaxLegacy(SDLoc DL,
160                               EVT VT,
161                               SDValue LHS,
162                               SDValue RHS,
163                               SDValue True,
164                               SDValue False,
165                               SDValue CC,
166                               DAGCombinerInfo &DCI) const;
167  SDValue CombineIMinMax(SDLoc DL,
168                         EVT VT,
169                         SDValue LHS,
170                         SDValue RHS,
171                         SDValue True,
172                         SDValue False,
173                         SDValue CC,
174                         SelectionDAG &DAG) const;
175
176  const char* getTargetNodeName(unsigned Opcode) const override;
177
178  SDValue getRsqrtEstimate(SDValue Operand,
179                           DAGCombinerInfo &DCI,
180                           unsigned &RefinementSteps,
181                           bool &UseOneConstNR) const override;
182  SDValue getRecipEstimate(SDValue Operand,
183                           DAGCombinerInfo &DCI,
184                           unsigned &RefinementSteps) const override;
185
186  virtual SDNode *PostISelFolding(MachineSDNode *N,
187                                  SelectionDAG &DAG) const {
188    return N;
189  }
190
191  /// \brief Determine which of the bits specified in \p Mask are known to be
192  /// either zero or one and return them in the \p KnownZero and \p KnownOne
193  /// bitsets.
194  void computeKnownBitsForTargetNode(const SDValue Op,
195                                     APInt &KnownZero,
196                                     APInt &KnownOne,
197                                     const SelectionDAG &DAG,
198                                     unsigned Depth = 0) const override;
199
200  unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
201                                           unsigned Depth = 0) const override;
202
203  /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
204  /// MachineFunction.
205  ///
206  /// \returns a RegisterSDNode representing Reg.
207  virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
208                                       const TargetRegisterClass *RC,
209                                       unsigned Reg, EVT VT) const;
210};
211
212namespace AMDGPUISD {
213
214enum NodeType : unsigned {
215  // AMDIL ISD Opcodes
216  FIRST_NUMBER = ISD::BUILTIN_OP_END,
217  CALL,        // Function call based on a single integer
218  UMUL,        // 32bit unsigned multiplication
219  RET_FLAG,
220  BRANCH_COND,
221  // End AMDIL ISD Opcodes
222  DWORDADDR,
223  FRACT,
224  CLAMP,
225
226  // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
227  // Denormals handled on some parts.
228  COS_HW,
229  SIN_HW,
230  FMAX_LEGACY,
231  FMIN_LEGACY,
232  FMAX3,
233  SMAX3,
234  UMAX3,
235  FMIN3,
236  SMIN3,
237  UMIN3,
238  URECIP,
239  DIV_SCALE,
240  DIV_FMAS,
241  DIV_FIXUP,
242  TRIG_PREOP, // 1 ULP max error for f64
243
244  // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
245  //            For f64, max error 2^29 ULP, handles denormals.
246  RCP,
247  RSQ,
248  RSQ_LEGACY,
249  RSQ_CLAMPED,
250  LDEXP,
251  FP_CLASS,
252  DOT4,
253  CARRY,
254  BORROW,
255  BFE_U32, // Extract range of bits with zero extension to 32-bits.
256  BFE_I32, // Extract range of bits with sign extension to 32-bits.
257  BFI, // (src0 & src1) | (~src0 & src2)
258  BFM, // Insert a range of bits into a 32-bit word.
259  BREV, // Reverse bits.
260  MUL_U24,
261  MUL_I24,
262  MAD_U24,
263  MAD_I24,
264  TEXTURE_FETCH,
265  EXPORT,
266  CONST_ADDRESS,
267  REGISTER_LOAD,
268  REGISTER_STORE,
269  LOAD_INPUT,
270  SAMPLE,
271  SAMPLEB,
272  SAMPLED,
273  SAMPLEL,
274
275  // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
276  CVT_F32_UBYTE0,
277  CVT_F32_UBYTE1,
278  CVT_F32_UBYTE2,
279  CVT_F32_UBYTE3,
280  /// This node is for VLIW targets and it is used to represent a vector
281  /// that is stored in consecutive registers with the same channel.
282  /// For example:
283  ///   |X  |Y|Z|W|
284  /// T0|v.x| | | |
285  /// T1|v.y| | | |
286  /// T2|v.z| | | |
287  /// T3|v.w| | | |
288  BUILD_VERTICAL_VECTOR,
289  /// Pointer to the start of the shader's constant data.
290  CONST_DATA_PTR,
291  SENDMSG,
292  INTERP_MOV,
293  INTERP_P1,
294  INTERP_P2,
295  FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
296  STORE_MSKOR,
297  LOAD_CONSTANT,
298  TBUFFER_STORE_FORMAT,
299  LAST_AMDGPU_ISD_NUMBER
300};
301
302
303} // End namespace AMDGPUISD
304
305} // End namespace llvm
306
307#endif
308