AArch64BaseInfo.cpp revision 288943 
1//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides basic encoding and assembly information for AArch64.
11//
12//===----------------------------------------------------------------------===//
13#include "AArch64BaseInfo.h"
14#include "llvm/ADT/APFloat.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/ADT/StringExtras.h"
17#include "llvm/Support/Regex.h"
18
19using namespace llvm;
20
21StringRef AArch64NamedImmMapper::toString(uint32_t Value,
22          const FeatureBitset& FeatureBits, bool &Valid) const {
23  for (unsigned i = 0; i < NumMappings; ++i) {
24    if (Mappings[i].isValueEqual(Value, FeatureBits)) {
25      Valid = true;
26      return Mappings[i].Name;
27    }
28  }
29
30  Valid = false;
31  return StringRef();
32}
33
34uint32_t AArch64NamedImmMapper::fromString(StringRef Name,
35         const FeatureBitset& FeatureBits, bool &Valid) const {
36  std::string LowerCaseName = Name.lower();
37  for (unsigned i = 0; i < NumMappings; ++i) {
38    if (Mappings[i].isNameEqual(LowerCaseName, FeatureBits)) {
39      Valid = true;
40      return Mappings[i].Value;
41    }
42  }
43
44  Valid = false;
45  return -1;
46}
47
48bool AArch64NamedImmMapper::validImm(uint32_t Value) const {
49  return Value < TooBigImm;
50}
51
52const AArch64NamedImmMapper::Mapping AArch64AT::ATMapper::ATMappings[] = {
53  {"s1e1r", S1E1R, {}},
54  {"s1e2r", S1E2R, {}},
55  {"s1e3r", S1E3R, {}},
56  {"s1e1w", S1E1W, {}},
57  {"s1e2w", S1E2W, {}},
58  {"s1e3w", S1E3W, {}},
59  {"s1e0r", S1E0R, {}},
60  {"s1e0w", S1E0W, {}},
61  {"s12e1r", S12E1R, {}},
62  {"s12e1w", S12E1W, {}},
63  {"s12e0r", S12E0R, {}},
64  {"s12e0w", S12E0W, {}},
65};
66
67AArch64AT::ATMapper::ATMapper()
68  : AArch64NamedImmMapper(ATMappings, 0) {}
69
70const AArch64NamedImmMapper::Mapping AArch64DB::DBarrierMapper::DBarrierMappings[] = {
71  {"oshld", OSHLD, {}},
72  {"oshst", OSHST, {}},
73  {"osh", OSH, {}},
74  {"nshld", NSHLD, {}},
75  {"nshst", NSHST, {}},
76  {"nsh", NSH, {}},
77  {"ishld", ISHLD, {}},
78  {"ishst", ISHST, {}},
79  {"ish", ISH, {}},
80  {"ld", LD, {}},
81  {"st", ST, {}},
82  {"sy", SY, {}}
83};
84
85AArch64DB::DBarrierMapper::DBarrierMapper()
86  : AArch64NamedImmMapper(DBarrierMappings, 16u) {}
87
88const AArch64NamedImmMapper::Mapping AArch64DC::DCMapper::DCMappings[] = {
89  {"zva", ZVA, {}},
90  {"ivac", IVAC, {}},
91  {"isw", ISW, {}},
92  {"cvac", CVAC, {}},
93  {"csw", CSW, {}},
94  {"cvau", CVAU, {}},
95  {"civac", CIVAC, {}},
96  {"cisw", CISW, {}}
97};
98
99AArch64DC::DCMapper::DCMapper()
100  : AArch64NamedImmMapper(DCMappings, 0) {}
101
102const AArch64NamedImmMapper::Mapping AArch64IC::ICMapper::ICMappings[] = {
103  {"ialluis",  IALLUIS, {}},
104  {"iallu", IALLU, {}},
105  {"ivau", IVAU, {}}
106};
107
108AArch64IC::ICMapper::ICMapper()
109  : AArch64NamedImmMapper(ICMappings, 0) {}
110
111const AArch64NamedImmMapper::Mapping AArch64ISB::ISBMapper::ISBMappings[] = {
112  {"sy",  SY, {}},
113};
114
115AArch64ISB::ISBMapper::ISBMapper()
116  : AArch64NamedImmMapper(ISBMappings, 16) {}
117
118const AArch64NamedImmMapper::Mapping AArch64PRFM::PRFMMapper::PRFMMappings[] = {
119  {"pldl1keep", PLDL1KEEP, {}},
120  {"pldl1strm", PLDL1STRM, {}},
121  {"pldl2keep", PLDL2KEEP, {}},
122  {"pldl2strm", PLDL2STRM, {}},
123  {"pldl3keep", PLDL3KEEP, {}},
124  {"pldl3strm", PLDL3STRM, {}},
125  {"plil1keep", PLIL1KEEP, {}},
126  {"plil1strm", PLIL1STRM, {}},
127  {"plil2keep", PLIL2KEEP, {}},
128  {"plil2strm", PLIL2STRM, {}},
129  {"plil3keep", PLIL3KEEP, {}},
130  {"plil3strm", PLIL3STRM, {}},
131  {"pstl1keep", PSTL1KEEP, {}},
132  {"pstl1strm", PSTL1STRM, {}},
133  {"pstl2keep", PSTL2KEEP, {}},
134  {"pstl2strm", PSTL2STRM, {}},
135  {"pstl3keep", PSTL3KEEP, {}},
136  {"pstl3strm", PSTL3STRM, {}}
137};
138
139AArch64PRFM::PRFMMapper::PRFMMapper()
140  : AArch64NamedImmMapper(PRFMMappings, 32) {}
141
142const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStateMappings[] = {
143  {"spsel", SPSel, {}},
144  {"daifset", DAIFSet, {}},
145  {"daifclr", DAIFClr, {}},
146
147  // v8.1a "Privileged Access Never" extension-specific PStates
148  {"pan", PAN, {AArch64::HasV8_1aOps}},
149};
150
151AArch64PState::PStateMapper::PStateMapper()
152  : AArch64NamedImmMapper(PStateMappings, 0) {}
153
154const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
155  {"mdccsr_el0", MDCCSR_EL0, {}},
156  {"dbgdtrrx_el0", DBGDTRRX_EL0, {}},
157  {"mdrar_el1", MDRAR_EL1, {}},
158  {"oslsr_el1", OSLSR_EL1, {}},
159  {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1, {}},
160  {"pmceid0_el0", PMCEID0_EL0, {}},
161  {"pmceid1_el0", PMCEID1_EL0, {}},
162  {"midr_el1", MIDR_EL1, {}},
163  {"ccsidr_el1", CCSIDR_EL1, {}},
164  {"clidr_el1", CLIDR_EL1, {}},
165  {"ctr_el0", CTR_EL0, {}},
166  {"mpidr_el1", MPIDR_EL1, {}},
167  {"revidr_el1", REVIDR_EL1, {}},
168  {"aidr_el1", AIDR_EL1, {}},
169  {"dczid_el0", DCZID_EL0, {}},
170  {"id_pfr0_el1", ID_PFR0_EL1, {}},
171  {"id_pfr1_el1", ID_PFR1_EL1, {}},
172  {"id_dfr0_el1", ID_DFR0_EL1, {}},
173  {"id_afr0_el1", ID_AFR0_EL1, {}},
174  {"id_mmfr0_el1", ID_MMFR0_EL1, {}},
175  {"id_mmfr1_el1", ID_MMFR1_EL1, {}},
176  {"id_mmfr2_el1", ID_MMFR2_EL1, {}},
177  {"id_mmfr3_el1", ID_MMFR3_EL1, {}},
178  {"id_mmfr4_el1", ID_MMFR4_EL1, {}},
179  {"id_isar0_el1", ID_ISAR0_EL1, {}},
180  {"id_isar1_el1", ID_ISAR1_EL1, {}},
181  {"id_isar2_el1", ID_ISAR2_EL1, {}},
182  {"id_isar3_el1", ID_ISAR3_EL1, {}},
183  {"id_isar4_el1", ID_ISAR4_EL1, {}},
184  {"id_isar5_el1", ID_ISAR5_EL1, {}},
185  {"id_aa64pfr0_el1", ID_A64PFR0_EL1, {}},
186  {"id_aa64pfr1_el1", ID_A64PFR1_EL1, {}},
187  {"id_aa64dfr0_el1", ID_A64DFR0_EL1, {}},
188  {"id_aa64dfr1_el1", ID_A64DFR1_EL1, {}},
189  {"id_aa64afr0_el1", ID_A64AFR0_EL1, {}},
190  {"id_aa64afr1_el1", ID_A64AFR1_EL1, {}},
191  {"id_aa64isar0_el1", ID_A64ISAR0_EL1, {}},
192  {"id_aa64isar1_el1", ID_A64ISAR1_EL1, {}},
193  {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, {}},
194  {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, {}},
195  {"mvfr0_el1", MVFR0_EL1, {}},
196  {"mvfr1_el1", MVFR1_EL1, {}},
197  {"mvfr2_el1", MVFR2_EL1, {}},
198  {"rvbar_el1", RVBAR_EL1, {}},
199  {"rvbar_el2", RVBAR_EL2, {}},
200  {"rvbar_el3", RVBAR_EL3, {}},
201  {"isr_el1", ISR_EL1, {}},
202  {"cntpct_el0", CNTPCT_EL0, {}},
203  {"cntvct_el0", CNTVCT_EL0, {}},
204
205  // Trace registers
206  {"trcstatr", TRCSTATR, {}},
207  {"trcidr8", TRCIDR8, {}},
208  {"trcidr9", TRCIDR9, {}},
209  {"trcidr10", TRCIDR10, {}},
210  {"trcidr11", TRCIDR11, {}},
211  {"trcidr12", TRCIDR12, {}},
212  {"trcidr13", TRCIDR13, {}},
213  {"trcidr0", TRCIDR0, {}},
214  {"trcidr1", TRCIDR1, {}},
215  {"trcidr2", TRCIDR2, {}},
216  {"trcidr3", TRCIDR3, {}},
217  {"trcidr4", TRCIDR4, {}},
218  {"trcidr5", TRCIDR5, {}},
219  {"trcidr6", TRCIDR6, {}},
220  {"trcidr7", TRCIDR7, {}},
221  {"trcoslsr", TRCOSLSR, {}},
222  {"trcpdsr", TRCPDSR, {}},
223  {"trcdevaff0", TRCDEVAFF0, {}},
224  {"trcdevaff1", TRCDEVAFF1, {}},
225  {"trclsr", TRCLSR, {}},
226  {"trcauthstatus", TRCAUTHSTATUS, {}},
227  {"trcdevarch", TRCDEVARCH, {}},
228  {"trcdevid", TRCDEVID, {}},
229  {"trcdevtype", TRCDEVTYPE, {}},
230  {"trcpidr4", TRCPIDR4, {}},
231  {"trcpidr5", TRCPIDR5, {}},
232  {"trcpidr6", TRCPIDR6, {}},
233  {"trcpidr7", TRCPIDR7, {}},
234  {"trcpidr0", TRCPIDR0, {}},
235  {"trcpidr1", TRCPIDR1, {}},
236  {"trcpidr2", TRCPIDR2, {}},
237  {"trcpidr3", TRCPIDR3, {}},
238  {"trccidr0", TRCCIDR0, {}},
239  {"trccidr1", TRCCIDR1, {}},
240  {"trccidr2", TRCCIDR2, {}},
241  {"trccidr3", TRCCIDR3, {}},
242
243  // GICv3 registers
244  {"icc_iar1_el1", ICC_IAR1_EL1, {}},
245  {"icc_iar0_el1", ICC_IAR0_EL1, {}},
246  {"icc_hppir1_el1", ICC_HPPIR1_EL1, {}},
247  {"icc_hppir0_el1", ICC_HPPIR0_EL1, {}},
248  {"icc_rpr_el1", ICC_RPR_EL1, {}},
249  {"ich_vtr_el2", ICH_VTR_EL2, {}},
250  {"ich_eisr_el2", ICH_EISR_EL2, {}},
251  {"ich_elsr_el2", ICH_ELSR_EL2, {}},
252
253  // v8.1a "Limited Ordering Regions" extension-specific system registers
254  {"lorid_el1", LORID_EL1, {AArch64::HasV8_1aOps}},
255};
256
257AArch64SysReg::MRSMapper::MRSMapper() {
258    InstMappings = &MRSMappings[0];
259    NumInstMappings = llvm::array_lengthof(MRSMappings);
260}
261
262const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRMappings[] = {
263  {"dbgdtrtx_el0", DBGDTRTX_EL0, {}},
264  {"oslar_el1", OSLAR_EL1, {}},
265  {"pmswinc_el0", PMSWINC_EL0, {}},
266
267  // Trace registers
268  {"trcoslar", TRCOSLAR, {}},
269  {"trclar", TRCLAR, {}},
270
271  // GICv3 registers
272  {"icc_eoir1_el1", ICC_EOIR1_EL1, {}},
273  {"icc_eoir0_el1", ICC_EOIR0_EL1, {}},
274  {"icc_dir_el1", ICC_DIR_EL1, {}},
275  {"icc_sgi1r_el1", ICC_SGI1R_EL1, {}},
276  {"icc_asgi1r_el1", ICC_ASGI1R_EL1, {}},
277  {"icc_sgi0r_el1", ICC_SGI0R_EL1, {}},
278
279  // v8.1a "Privileged Access Never" extension-specific system registers
280  {"pan", PAN, {AArch64::HasV8_1aOps}},
281};
282
283AArch64SysReg::MSRMapper::MSRMapper() {
284    InstMappings = &MSRMappings[0];
285    NumInstMappings = llvm::array_lengthof(MSRMappings);
286}
287
288
289const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = {
290  {"osdtrrx_el1", OSDTRRX_EL1, {}},
291  {"osdtrtx_el1",  OSDTRTX_EL1, {}},
292  {"teecr32_el1", TEECR32_EL1, {}},
293  {"mdccint_el1", MDCCINT_EL1, {}},
294  {"mdscr_el1", MDSCR_EL1, {}},
295  {"dbgdtr_el0", DBGDTR_EL0, {}},
296  {"oseccr_el1", OSECCR_EL1, {}},
297  {"dbgvcr32_el2", DBGVCR32_EL2, {}},
298  {"dbgbvr0_el1", DBGBVR0_EL1, {}},
299  {"dbgbvr1_el1", DBGBVR1_EL1, {}},
300  {"dbgbvr2_el1", DBGBVR2_EL1, {}},
301  {"dbgbvr3_el1", DBGBVR3_EL1, {}},
302  {"dbgbvr4_el1", DBGBVR4_EL1, {}},
303  {"dbgbvr5_el1", DBGBVR5_EL1, {}},
304  {"dbgbvr6_el1", DBGBVR6_EL1, {}},
305  {"dbgbvr7_el1", DBGBVR7_EL1, {}},
306  {"dbgbvr8_el1", DBGBVR8_EL1, {}},
307  {"dbgbvr9_el1", DBGBVR9_EL1, {}},
308  {"dbgbvr10_el1", DBGBVR10_EL1, {}},
309  {"dbgbvr11_el1", DBGBVR11_EL1, {}},
310  {"dbgbvr12_el1", DBGBVR12_EL1, {}},
311  {"dbgbvr13_el1", DBGBVR13_EL1, {}},
312  {"dbgbvr14_el1", DBGBVR14_EL1, {}},
313  {"dbgbvr15_el1", DBGBVR15_EL1, {}},
314  {"dbgbcr0_el1", DBGBCR0_EL1, {}},
315  {"dbgbcr1_el1", DBGBCR1_EL1, {}},
316  {"dbgbcr2_el1", DBGBCR2_EL1, {}},
317  {"dbgbcr3_el1", DBGBCR3_EL1, {}},
318  {"dbgbcr4_el1", DBGBCR4_EL1, {}},
319  {"dbgbcr5_el1", DBGBCR5_EL1, {}},
320  {"dbgbcr6_el1", DBGBCR6_EL1, {}},
321  {"dbgbcr7_el1", DBGBCR7_EL1, {}},
322  {"dbgbcr8_el1", DBGBCR8_EL1, {}},
323  {"dbgbcr9_el1", DBGBCR9_EL1, {}},
324  {"dbgbcr10_el1", DBGBCR10_EL1, {}},
325  {"dbgbcr11_el1", DBGBCR11_EL1, {}},
326  {"dbgbcr12_el1", DBGBCR12_EL1, {}},
327  {"dbgbcr13_el1", DBGBCR13_EL1, {}},
328  {"dbgbcr14_el1", DBGBCR14_EL1, {}},
329  {"dbgbcr15_el1", DBGBCR15_EL1, {}},
330  {"dbgwvr0_el1", DBGWVR0_EL1, {}},
331  {"dbgwvr1_el1", DBGWVR1_EL1, {}},
332  {"dbgwvr2_el1", DBGWVR2_EL1, {}},
333  {"dbgwvr3_el1", DBGWVR3_EL1, {}},
334  {"dbgwvr4_el1", DBGWVR4_EL1, {}},
335  {"dbgwvr5_el1", DBGWVR5_EL1, {}},
336  {"dbgwvr6_el1", DBGWVR6_EL1, {}},
337  {"dbgwvr7_el1", DBGWVR7_EL1, {}},
338  {"dbgwvr8_el1", DBGWVR8_EL1, {}},
339  {"dbgwvr9_el1", DBGWVR9_EL1, {}},
340  {"dbgwvr10_el1", DBGWVR10_EL1, {}},
341  {"dbgwvr11_el1", DBGWVR11_EL1, {}},
342  {"dbgwvr12_el1", DBGWVR12_EL1, {}},
343  {"dbgwvr13_el1", DBGWVR13_EL1, {}},
344  {"dbgwvr14_el1", DBGWVR14_EL1, {}},
345  {"dbgwvr15_el1", DBGWVR15_EL1, {}},
346  {"dbgwcr0_el1", DBGWCR0_EL1, {}},
347  {"dbgwcr1_el1", DBGWCR1_EL1, {}},
348  {"dbgwcr2_el1", DBGWCR2_EL1, {}},
349  {"dbgwcr3_el1", DBGWCR3_EL1, {}},
350  {"dbgwcr4_el1", DBGWCR4_EL1, {}},
351  {"dbgwcr5_el1", DBGWCR5_EL1, {}},
352  {"dbgwcr6_el1", DBGWCR6_EL1, {}},
353  {"dbgwcr7_el1", DBGWCR7_EL1, {}},
354  {"dbgwcr8_el1", DBGWCR8_EL1, {}},
355  {"dbgwcr9_el1", DBGWCR9_EL1, {}},
356  {"dbgwcr10_el1", DBGWCR10_EL1, {}},
357  {"dbgwcr11_el1", DBGWCR11_EL1, {}},
358  {"dbgwcr12_el1", DBGWCR12_EL1, {}},
359  {"dbgwcr13_el1", DBGWCR13_EL1, {}},
360  {"dbgwcr14_el1", DBGWCR14_EL1, {}},
361  {"dbgwcr15_el1", DBGWCR15_EL1, {}},
362  {"teehbr32_el1", TEEHBR32_EL1, {}},
363  {"osdlr_el1", OSDLR_EL1, {}},
364  {"dbgprcr_el1", DBGPRCR_EL1, {}},
365  {"dbgclaimset_el1", DBGCLAIMSET_EL1, {}},
366  {"dbgclaimclr_el1", DBGCLAIMCLR_EL1, {}},
367  {"csselr_el1", CSSELR_EL1, {}},
368  {"vpidr_el2", VPIDR_EL2, {}},
369  {"vmpidr_el2", VMPIDR_EL2, {}},
370  {"sctlr_el1", SCTLR_EL1, {}},
371  {"sctlr_el2", SCTLR_EL2, {}},
372  {"sctlr_el3", SCTLR_EL3, {}},
373  {"actlr_el1", ACTLR_EL1, {}},
374  {"actlr_el2", ACTLR_EL2, {}},
375  {"actlr_el3", ACTLR_EL3, {}},
376  {"cpacr_el1", CPACR_EL1, {}},
377  {"hcr_el2", HCR_EL2, {}},
378  {"scr_el3", SCR_EL3, {}},
379  {"mdcr_el2", MDCR_EL2, {}},
380  {"sder32_el3", SDER32_EL3, {}},
381  {"cptr_el2", CPTR_EL2, {}},
382  {"cptr_el3", CPTR_EL3, {}},
383  {"hstr_el2", HSTR_EL2, {}},
384  {"hacr_el2", HACR_EL2, {}},
385  {"mdcr_el3", MDCR_EL3, {}},
386  {"ttbr0_el1", TTBR0_EL1, {}},
387  {"ttbr0_el2", TTBR0_EL2, {}},
388  {"ttbr0_el3", TTBR0_EL3, {}},
389  {"ttbr1_el1", TTBR1_EL1, {}},
390  {"tcr_el1", TCR_EL1, {}},
391  {"tcr_el2", TCR_EL2, {}},
392  {"tcr_el3", TCR_EL3, {}},
393  {"vttbr_el2", VTTBR_EL2, {}},
394  {"vtcr_el2", VTCR_EL2, {}},
395  {"dacr32_el2", DACR32_EL2, {}},
396  {"spsr_el1", SPSR_EL1, {}},
397  {"spsr_el2", SPSR_EL2, {}},
398  {"spsr_el3", SPSR_EL3, {}},
399  {"elr_el1", ELR_EL1, {}},
400  {"elr_el2", ELR_EL2, {}},
401  {"elr_el3", ELR_EL3, {}},
402  {"sp_el0", SP_EL0, {}},
403  {"sp_el1", SP_EL1, {}},
404  {"sp_el2", SP_EL2, {}},
405  {"spsel", SPSel, {}},
406  {"nzcv", NZCV, {}},
407  {"daif", DAIF, {}},
408  {"currentel", CurrentEL, {}},
409  {"spsr_irq", SPSR_irq, {}},
410  {"spsr_abt", SPSR_abt, {}},
411  {"spsr_und", SPSR_und, {}},
412  {"spsr_fiq", SPSR_fiq, {}},
413  {"fpcr", FPCR, {}},
414  {"fpsr", FPSR, {}},
415  {"dspsr_el0", DSPSR_EL0, {}},
416  {"dlr_el0", DLR_EL0, {}},
417  {"ifsr32_el2", IFSR32_EL2, {}},
418  {"afsr0_el1", AFSR0_EL1, {}},
419  {"afsr0_el2", AFSR0_EL2, {}},
420  {"afsr0_el3", AFSR0_EL3, {}},
421  {"afsr1_el1", AFSR1_EL1, {}},
422  {"afsr1_el2", AFSR1_EL2, {}},
423  {"afsr1_el3", AFSR1_EL3, {}},
424  {"esr_el1", ESR_EL1, {}},
425  {"esr_el2", ESR_EL2, {}},
426  {"esr_el3", ESR_EL3, {}},
427  {"fpexc32_el2", FPEXC32_EL2, {}},
428  {"far_el1", FAR_EL1, {}},
429  {"far_el2", FAR_EL2, {}},
430  {"far_el3", FAR_EL3, {}},
431  {"hpfar_el2", HPFAR_EL2, {}},
432  {"par_el1", PAR_EL1, {}},
433  {"pmcr_el0", PMCR_EL0, {}},
434  {"pmcntenset_el0", PMCNTENSET_EL0, {}},
435  {"pmcntenclr_el0", PMCNTENCLR_EL0, {}},
436  {"pmovsclr_el0", PMOVSCLR_EL0, {}},
437  {"pmselr_el0", PMSELR_EL0, {}},
438  {"pmccntr_el0", PMCCNTR_EL0, {}},
439  {"pmxevtyper_el0", PMXEVTYPER_EL0, {}},
440  {"pmxevcntr_el0", PMXEVCNTR_EL0, {}},
441  {"pmuserenr_el0", PMUSERENR_EL0, {}},
442  {"pmintenset_el1", PMINTENSET_EL1, {}},
443  {"pmintenclr_el1", PMINTENCLR_EL1, {}},
444  {"pmovsset_el0", PMOVSSET_EL0, {}},
445  {"mair_el1", MAIR_EL1, {}},
446  {"mair_el2", MAIR_EL2, {}},
447  {"mair_el3", MAIR_EL3, {}},
448  {"amair_el1", AMAIR_EL1, {}},
449  {"amair_el2", AMAIR_EL2, {}},
450  {"amair_el3", AMAIR_EL3, {}},
451  {"vbar_el1", VBAR_EL1, {}},
452  {"vbar_el2", VBAR_EL2, {}},
453  {"vbar_el3", VBAR_EL3, {}},
454  {"rmr_el1", RMR_EL1, {}},
455  {"rmr_el2", RMR_EL2, {}},
456  {"rmr_el3", RMR_EL3, {}},
457  {"contextidr_el1", CONTEXTIDR_EL1, {}},
458  {"tpidr_el0", TPIDR_EL0, {}},
459  {"tpidr_el2", TPIDR_EL2, {}},
460  {"tpidr_el3", TPIDR_EL3, {}},
461  {"tpidrro_el0", TPIDRRO_EL0, {}},
462  {"tpidr_el1", TPIDR_EL1, {}},
463  {"cntfrq_el0", CNTFRQ_EL0, {}},
464  {"cntvoff_el2", CNTVOFF_EL2, {}},
465  {"cntkctl_el1", CNTKCTL_EL1, {}},
466  {"cnthctl_el2", CNTHCTL_EL2, {}},
467  {"cntp_tval_el0", CNTP_TVAL_EL0, {}},
468  {"cnthp_tval_el2", CNTHP_TVAL_EL2, {}},
469  {"cntps_tval_el1", CNTPS_TVAL_EL1, {}},
470  {"cntp_ctl_el0", CNTP_CTL_EL0, {}},
471  {"cnthp_ctl_el2", CNTHP_CTL_EL2, {}},
472  {"cntps_ctl_el1", CNTPS_CTL_EL1, {}},
473  {"cntp_cval_el0", CNTP_CVAL_EL0, {}},
474  {"cnthp_cval_el2", CNTHP_CVAL_EL2, {}},
475  {"cntps_cval_el1", CNTPS_CVAL_EL1, {}},
476  {"cntv_tval_el0", CNTV_TVAL_EL0, {}},
477  {"cntv_ctl_el0", CNTV_CTL_EL0, {}},
478  {"cntv_cval_el0", CNTV_CVAL_EL0, {}},
479  {"pmevcntr0_el0", PMEVCNTR0_EL0, {}},
480  {"pmevcntr1_el0", PMEVCNTR1_EL0, {}},
481  {"pmevcntr2_el0", PMEVCNTR2_EL0, {}},
482  {"pmevcntr3_el0", PMEVCNTR3_EL0, {}},
483  {"pmevcntr4_el0", PMEVCNTR4_EL0, {}},
484  {"pmevcntr5_el0", PMEVCNTR5_EL0, {}},
485  {"pmevcntr6_el0", PMEVCNTR6_EL0, {}},
486  {"pmevcntr7_el0", PMEVCNTR7_EL0, {}},
487  {"pmevcntr8_el0", PMEVCNTR8_EL0, {}},
488  {"pmevcntr9_el0", PMEVCNTR9_EL0, {}},
489  {"pmevcntr10_el0", PMEVCNTR10_EL0, {}},
490  {"pmevcntr11_el0", PMEVCNTR11_EL0, {}},
491  {"pmevcntr12_el0", PMEVCNTR12_EL0, {}},
492  {"pmevcntr13_el0", PMEVCNTR13_EL0, {}},
493  {"pmevcntr14_el0", PMEVCNTR14_EL0, {}},
494  {"pmevcntr15_el0", PMEVCNTR15_EL0, {}},
495  {"pmevcntr16_el0", PMEVCNTR16_EL0, {}},
496  {"pmevcntr17_el0", PMEVCNTR17_EL0, {}},
497  {"pmevcntr18_el0", PMEVCNTR18_EL0, {}},
498  {"pmevcntr19_el0", PMEVCNTR19_EL0, {}},
499  {"pmevcntr20_el0", PMEVCNTR20_EL0, {}},
500  {"pmevcntr21_el0", PMEVCNTR21_EL0, {}},
501  {"pmevcntr22_el0", PMEVCNTR22_EL0, {}},
502  {"pmevcntr23_el0", PMEVCNTR23_EL0, {}},
503  {"pmevcntr24_el0", PMEVCNTR24_EL0, {}},
504  {"pmevcntr25_el0", PMEVCNTR25_EL0, {}},
505  {"pmevcntr26_el0", PMEVCNTR26_EL0, {}},
506  {"pmevcntr27_el0", PMEVCNTR27_EL0, {}},
507  {"pmevcntr28_el0", PMEVCNTR28_EL0, {}},
508  {"pmevcntr29_el0", PMEVCNTR29_EL0, {}},
509  {"pmevcntr30_el0", PMEVCNTR30_EL0, {}},
510  {"pmccfiltr_el0", PMCCFILTR_EL0, {}},
511  {"pmevtyper0_el0", PMEVTYPER0_EL0, {}},
512  {"pmevtyper1_el0", PMEVTYPER1_EL0, {}},
513  {"pmevtyper2_el0", PMEVTYPER2_EL0, {}},
514  {"pmevtyper3_el0", PMEVTYPER3_EL0, {}},
515  {"pmevtyper4_el0", PMEVTYPER4_EL0, {}},
516  {"pmevtyper5_el0", PMEVTYPER5_EL0, {}},
517  {"pmevtyper6_el0", PMEVTYPER6_EL0, {}},
518  {"pmevtyper7_el0", PMEVTYPER7_EL0, {}},
519  {"pmevtyper8_el0", PMEVTYPER8_EL0, {}},
520  {"pmevtyper9_el0", PMEVTYPER9_EL0, {}},
521  {"pmevtyper10_el0", PMEVTYPER10_EL0, {}},
522  {"pmevtyper11_el0", PMEVTYPER11_EL0, {}},
523  {"pmevtyper12_el0", PMEVTYPER12_EL0, {}},
524  {"pmevtyper13_el0", PMEVTYPER13_EL0, {}},
525  {"pmevtyper14_el0", PMEVTYPER14_EL0, {}},
526  {"pmevtyper15_el0", PMEVTYPER15_EL0, {}},
527  {"pmevtyper16_el0", PMEVTYPER16_EL0, {}},
528  {"pmevtyper17_el0", PMEVTYPER17_EL0, {}},
529  {"pmevtyper18_el0", PMEVTYPER18_EL0, {}},
530  {"pmevtyper19_el0", PMEVTYPER19_EL0, {}},
531  {"pmevtyper20_el0", PMEVTYPER20_EL0, {}},
532  {"pmevtyper21_el0", PMEVTYPER21_EL0, {}},
533  {"pmevtyper22_el0", PMEVTYPER22_EL0, {}},
534  {"pmevtyper23_el0", PMEVTYPER23_EL0, {}},
535  {"pmevtyper24_el0", PMEVTYPER24_EL0, {}},
536  {"pmevtyper25_el0", PMEVTYPER25_EL0, {}},
537  {"pmevtyper26_el0", PMEVTYPER26_EL0, {}},
538  {"pmevtyper27_el0", PMEVTYPER27_EL0, {}},
539  {"pmevtyper28_el0", PMEVTYPER28_EL0, {}},
540  {"pmevtyper29_el0", PMEVTYPER29_EL0, {}},
541  {"pmevtyper30_el0", PMEVTYPER30_EL0, {}},
542
543  // Trace registers
544  {"trcprgctlr", TRCPRGCTLR, {}},
545  {"trcprocselr", TRCPROCSELR, {}},
546  {"trcconfigr", TRCCONFIGR, {}},
547  {"trcauxctlr", TRCAUXCTLR, {}},
548  {"trceventctl0r", TRCEVENTCTL0R, {}},
549  {"trceventctl1r", TRCEVENTCTL1R, {}},
550  {"trcstallctlr", TRCSTALLCTLR, {}},
551  {"trctsctlr", TRCTSCTLR, {}},
552  {"trcsyncpr", TRCSYNCPR, {}},
553  {"trcccctlr", TRCCCCTLR, {}},
554  {"trcbbctlr", TRCBBCTLR, {}},
555  {"trctraceidr", TRCTRACEIDR, {}},
556  {"trcqctlr", TRCQCTLR, {}},
557  {"trcvictlr", TRCVICTLR, {}},
558  {"trcviiectlr", TRCVIIECTLR, {}},
559  {"trcvissctlr", TRCVISSCTLR, {}},
560  {"trcvipcssctlr", TRCVIPCSSCTLR, {}},
561  {"trcvdctlr", TRCVDCTLR, {}},
562  {"trcvdsacctlr", TRCVDSACCTLR, {}},
563  {"trcvdarcctlr", TRCVDARCCTLR, {}},
564  {"trcseqevr0", TRCSEQEVR0, {}},
565  {"trcseqevr1", TRCSEQEVR1, {}},
566  {"trcseqevr2", TRCSEQEVR2, {}},
567  {"trcseqrstevr", TRCSEQRSTEVR, {}},
568  {"trcseqstr", TRCSEQSTR, {}},
569  {"trcextinselr", TRCEXTINSELR, {}},
570  {"trccntrldvr0", TRCCNTRLDVR0, {}},
571  {"trccntrldvr1", TRCCNTRLDVR1, {}},
572  {"trccntrldvr2", TRCCNTRLDVR2, {}},
573  {"trccntrldvr3", TRCCNTRLDVR3, {}},
574  {"trccntctlr0", TRCCNTCTLR0, {}},
575  {"trccntctlr1", TRCCNTCTLR1, {}},
576  {"trccntctlr2", TRCCNTCTLR2, {}},
577  {"trccntctlr3", TRCCNTCTLR3, {}},
578  {"trccntvr0", TRCCNTVR0, {}},
579  {"trccntvr1", TRCCNTVR1, {}},
580  {"trccntvr2", TRCCNTVR2, {}},
581  {"trccntvr3", TRCCNTVR3, {}},
582  {"trcimspec0", TRCIMSPEC0, {}},
583  {"trcimspec1", TRCIMSPEC1, {}},
584  {"trcimspec2", TRCIMSPEC2, {}},
585  {"trcimspec3", TRCIMSPEC3, {}},
586  {"trcimspec4", TRCIMSPEC4, {}},
587  {"trcimspec5", TRCIMSPEC5, {}},
588  {"trcimspec6", TRCIMSPEC6, {}},
589  {"trcimspec7", TRCIMSPEC7, {}},
590  {"trcrsctlr2", TRCRSCTLR2, {}},
591  {"trcrsctlr3", TRCRSCTLR3, {}},
592  {"trcrsctlr4", TRCRSCTLR4, {}},
593  {"trcrsctlr5", TRCRSCTLR5, {}},
594  {"trcrsctlr6", TRCRSCTLR6, {}},
595  {"trcrsctlr7", TRCRSCTLR7, {}},
596  {"trcrsctlr8", TRCRSCTLR8, {}},
597  {"trcrsctlr9", TRCRSCTLR9, {}},
598  {"trcrsctlr10", TRCRSCTLR10, {}},
599  {"trcrsctlr11", TRCRSCTLR11, {}},
600  {"trcrsctlr12", TRCRSCTLR12, {}},
601  {"trcrsctlr13", TRCRSCTLR13, {}},
602  {"trcrsctlr14", TRCRSCTLR14, {}},
603  {"trcrsctlr15", TRCRSCTLR15, {}},
604  {"trcrsctlr16", TRCRSCTLR16, {}},
605  {"trcrsctlr17", TRCRSCTLR17, {}},
606  {"trcrsctlr18", TRCRSCTLR18, {}},
607  {"trcrsctlr19", TRCRSCTLR19, {}},
608  {"trcrsctlr20", TRCRSCTLR20, {}},
609  {"trcrsctlr21", TRCRSCTLR21, {}},
610  {"trcrsctlr22", TRCRSCTLR22, {}},
611  {"trcrsctlr23", TRCRSCTLR23, {}},
612  {"trcrsctlr24", TRCRSCTLR24, {}},
613  {"trcrsctlr25", TRCRSCTLR25, {}},
614  {"trcrsctlr26", TRCRSCTLR26, {}},
615  {"trcrsctlr27", TRCRSCTLR27, {}},
616  {"trcrsctlr28", TRCRSCTLR28, {}},
617  {"trcrsctlr29", TRCRSCTLR29, {}},
618  {"trcrsctlr30", TRCRSCTLR30, {}},
619  {"trcrsctlr31", TRCRSCTLR31, {}},
620  {"trcssccr0", TRCSSCCR0, {}},
621  {"trcssccr1", TRCSSCCR1, {}},
622  {"trcssccr2", TRCSSCCR2, {}},
623  {"trcssccr3", TRCSSCCR3, {}},
624  {"trcssccr4", TRCSSCCR4, {}},
625  {"trcssccr5", TRCSSCCR5, {}},
626  {"trcssccr6", TRCSSCCR6, {}},
627  {"trcssccr7", TRCSSCCR7, {}},
628  {"trcsscsr0", TRCSSCSR0, {}},
629  {"trcsscsr1", TRCSSCSR1, {}},
630  {"trcsscsr2", TRCSSCSR2, {}},
631  {"trcsscsr3", TRCSSCSR3, {}},
632  {"trcsscsr4", TRCSSCSR4, {}},
633  {"trcsscsr5", TRCSSCSR5, {}},
634  {"trcsscsr6", TRCSSCSR6, {}},
635  {"trcsscsr7", TRCSSCSR7, {}},
636  {"trcsspcicr0", TRCSSPCICR0, {}},
637  {"trcsspcicr1", TRCSSPCICR1, {}},
638  {"trcsspcicr2", TRCSSPCICR2, {}},
639  {"trcsspcicr3", TRCSSPCICR3, {}},
640  {"trcsspcicr4", TRCSSPCICR4, {}},
641  {"trcsspcicr5", TRCSSPCICR5, {}},
642  {"trcsspcicr6", TRCSSPCICR6, {}},
643  {"trcsspcicr7", TRCSSPCICR7, {}},
644  {"trcpdcr", TRCPDCR, {}},
645  {"trcacvr0", TRCACVR0, {}},
646  {"trcacvr1", TRCACVR1, {}},
647  {"trcacvr2", TRCACVR2, {}},
648  {"trcacvr3", TRCACVR3, {}},
649  {"trcacvr4", TRCACVR4, {}},
650  {"trcacvr5", TRCACVR5, {}},
651  {"trcacvr6", TRCACVR6, {}},
652  {"trcacvr7", TRCACVR7, {}},
653  {"trcacvr8", TRCACVR8, {}},
654  {"trcacvr9", TRCACVR9, {}},
655  {"trcacvr10", TRCACVR10, {}},
656  {"trcacvr11", TRCACVR11, {}},
657  {"trcacvr12", TRCACVR12, {}},
658  {"trcacvr13", TRCACVR13, {}},
659  {"trcacvr14", TRCACVR14, {}},
660  {"trcacvr15", TRCACVR15, {}},
661  {"trcacatr0", TRCACATR0, {}},
662  {"trcacatr1", TRCACATR1, {}},
663  {"trcacatr2", TRCACATR2, {}},
664  {"trcacatr3", TRCACATR3, {}},
665  {"trcacatr4", TRCACATR4, {}},
666  {"trcacatr5", TRCACATR5, {}},
667  {"trcacatr6", TRCACATR6, {}},
668  {"trcacatr7", TRCACATR7, {}},
669  {"trcacatr8", TRCACATR8, {}},
670  {"trcacatr9", TRCACATR9, {}},
671  {"trcacatr10", TRCACATR10, {}},
672  {"trcacatr11", TRCACATR11, {}},
673  {"trcacatr12", TRCACATR12, {}},
674  {"trcacatr13", TRCACATR13, {}},
675  {"trcacatr14", TRCACATR14, {}},
676  {"trcacatr15", TRCACATR15, {}},
677  {"trcdvcvr0", TRCDVCVR0, {}},
678  {"trcdvcvr1", TRCDVCVR1, {}},
679  {"trcdvcvr2", TRCDVCVR2, {}},
680  {"trcdvcvr3", TRCDVCVR3, {}},
681  {"trcdvcvr4", TRCDVCVR4, {}},
682  {"trcdvcvr5", TRCDVCVR5, {}},
683  {"trcdvcvr6", TRCDVCVR6, {}},
684  {"trcdvcvr7", TRCDVCVR7, {}},
685  {"trcdvcmr0", TRCDVCMR0, {}},
686  {"trcdvcmr1", TRCDVCMR1, {}},
687  {"trcdvcmr2", TRCDVCMR2, {}},
688  {"trcdvcmr3", TRCDVCMR3, {}},
689  {"trcdvcmr4", TRCDVCMR4, {}},
690  {"trcdvcmr5", TRCDVCMR5, {}},
691  {"trcdvcmr6", TRCDVCMR6, {}},
692  {"trcdvcmr7", TRCDVCMR7, {}},
693  {"trccidcvr0", TRCCIDCVR0, {}},
694  {"trccidcvr1", TRCCIDCVR1, {}},
695  {"trccidcvr2", TRCCIDCVR2, {}},
696  {"trccidcvr3", TRCCIDCVR3, {}},
697  {"trccidcvr4", TRCCIDCVR4, {}},
698  {"trccidcvr5", TRCCIDCVR5, {}},
699  {"trccidcvr6", TRCCIDCVR6, {}},
700  {"trccidcvr7", TRCCIDCVR7, {}},
701  {"trcvmidcvr0", TRCVMIDCVR0, {}},
702  {"trcvmidcvr1", TRCVMIDCVR1, {}},
703  {"trcvmidcvr2", TRCVMIDCVR2, {}},
704  {"trcvmidcvr3", TRCVMIDCVR3, {}},
705  {"trcvmidcvr4", TRCVMIDCVR4, {}},
706  {"trcvmidcvr5", TRCVMIDCVR5, {}},
707  {"trcvmidcvr6", TRCVMIDCVR6, {}},
708  {"trcvmidcvr7", TRCVMIDCVR7, {}},
709  {"trccidcctlr0", TRCCIDCCTLR0, {}},
710  {"trccidcctlr1", TRCCIDCCTLR1, {}},
711  {"trcvmidcctlr0", TRCVMIDCCTLR0, {}},
712  {"trcvmidcctlr1", TRCVMIDCCTLR1, {}},
713  {"trcitctrl", TRCITCTRL, {}},
714  {"trcclaimset", TRCCLAIMSET, {}},
715  {"trcclaimclr", TRCCLAIMCLR, {}},
716
717  // GICv3 registers
718  {"icc_bpr1_el1", ICC_BPR1_EL1, {}},
719  {"icc_bpr0_el1", ICC_BPR0_EL1, {}},
720  {"icc_pmr_el1", ICC_PMR_EL1, {}},
721  {"icc_ctlr_el1", ICC_CTLR_EL1, {}},
722  {"icc_ctlr_el3", ICC_CTLR_EL3, {}},
723  {"icc_sre_el1", ICC_SRE_EL1, {}},
724  {"icc_sre_el2", ICC_SRE_EL2, {}},
725  {"icc_sre_el3", ICC_SRE_EL3, {}},
726  {"icc_igrpen0_el1", ICC_IGRPEN0_EL1, {}},
727  {"icc_igrpen1_el1", ICC_IGRPEN1_EL1, {}},
728  {"icc_igrpen1_el3", ICC_IGRPEN1_EL3, {}},
729  {"icc_seien_el1", ICC_SEIEN_EL1, {}},
730  {"icc_ap0r0_el1", ICC_AP0R0_EL1, {}},
731  {"icc_ap0r1_el1", ICC_AP0R1_EL1, {}},
732  {"icc_ap0r2_el1", ICC_AP0R2_EL1, {}},
733  {"icc_ap0r3_el1", ICC_AP0R3_EL1, {}},
734  {"icc_ap1r0_el1", ICC_AP1R0_EL1, {}},
735  {"icc_ap1r1_el1", ICC_AP1R1_EL1, {}},
736  {"icc_ap1r2_el1", ICC_AP1R2_EL1, {}},
737  {"icc_ap1r3_el1", ICC_AP1R3_EL1, {}},
738  {"ich_ap0r0_el2", ICH_AP0R0_EL2, {}},
739  {"ich_ap0r1_el2", ICH_AP0R1_EL2, {}},
740  {"ich_ap0r2_el2", ICH_AP0R2_EL2, {}},
741  {"ich_ap0r3_el2", ICH_AP0R3_EL2, {}},
742  {"ich_ap1r0_el2", ICH_AP1R0_EL2, {}},
743  {"ich_ap1r1_el2", ICH_AP1R1_EL2, {}},
744  {"ich_ap1r2_el2", ICH_AP1R2_EL2, {}},
745  {"ich_ap1r3_el2", ICH_AP1R3_EL2, {}},
746  {"ich_hcr_el2", ICH_HCR_EL2, {}},
747  {"ich_misr_el2", ICH_MISR_EL2, {}},
748  {"ich_vmcr_el2", ICH_VMCR_EL2, {}},
749  {"ich_vseir_el2", ICH_VSEIR_EL2, {}},
750  {"ich_lr0_el2", ICH_LR0_EL2, {}},
751  {"ich_lr1_el2", ICH_LR1_EL2, {}},
752  {"ich_lr2_el2", ICH_LR2_EL2, {}},
753  {"ich_lr3_el2", ICH_LR3_EL2, {}},
754  {"ich_lr4_el2", ICH_LR4_EL2, {}},
755  {"ich_lr5_el2", ICH_LR5_EL2, {}},
756  {"ich_lr6_el2", ICH_LR6_EL2, {}},
757  {"ich_lr7_el2", ICH_LR7_EL2, {}},
758  {"ich_lr8_el2", ICH_LR8_EL2, {}},
759  {"ich_lr9_el2", ICH_LR9_EL2, {}},
760  {"ich_lr10_el2", ICH_LR10_EL2, {}},
761  {"ich_lr11_el2", ICH_LR11_EL2, {}},
762  {"ich_lr12_el2", ICH_LR12_EL2, {}},
763  {"ich_lr13_el2", ICH_LR13_EL2, {}},
764  {"ich_lr14_el2", ICH_LR14_EL2, {}},
765  {"ich_lr15_el2", ICH_LR15_EL2, {}},
766
767  // Cyclone registers
768  {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3, {AArch64::ProcCyclone}},
769
770  // v8.1a "Privileged Access Never" extension-specific system registers
771  {"pan", PAN, {AArch64::HasV8_1aOps}},
772
773  // v8.1a "Limited Ordering Regions" extension-specific system registers
774  {"lorsa_el1", LORSA_EL1, {AArch64::HasV8_1aOps}},
775  {"lorea_el1", LOREA_EL1, {AArch64::HasV8_1aOps}},
776  {"lorn_el1", LORN_EL1, {AArch64::HasV8_1aOps}},
777  {"lorc_el1", LORC_EL1, {AArch64::HasV8_1aOps}},
778
779  // v8.1a "Virtualization host extensions" system registers
780  {"ttbr1_el2", TTBR1_EL2, {AArch64::HasV8_1aOps}},
781  {"contextidr_el2", CONTEXTIDR_EL2, {AArch64::HasV8_1aOps}},
782  {"cnthv_tval_el2", CNTHV_TVAL_EL2, {AArch64::HasV8_1aOps}},
783  {"cnthv_cval_el2", CNTHV_CVAL_EL2, {AArch64::HasV8_1aOps}},
784  {"cnthv_ctl_el2", CNTHV_CTL_EL2, {AArch64::HasV8_1aOps}},
785  {"sctlr_el12", SCTLR_EL12, {AArch64::HasV8_1aOps}},
786  {"cpacr_el12", CPACR_EL12, {AArch64::HasV8_1aOps}},
787  {"ttbr0_el12", TTBR0_EL12, {AArch64::HasV8_1aOps}},
788  {"ttbr1_el12", TTBR1_EL12, {AArch64::HasV8_1aOps}},
789  {"tcr_el12", TCR_EL12, {AArch64::HasV8_1aOps}},
790  {"afsr0_el12", AFSR0_EL12, {AArch64::HasV8_1aOps}},
791  {"afsr1_el12", AFSR1_EL12, {AArch64::HasV8_1aOps}},
792  {"esr_el12", ESR_EL12, {AArch64::HasV8_1aOps}},
793  {"far_el12", FAR_EL12, {AArch64::HasV8_1aOps}},
794  {"mair_el12", MAIR_EL12, {AArch64::HasV8_1aOps}},
795  {"amair_el12", AMAIR_EL12, {AArch64::HasV8_1aOps}},
796  {"vbar_el12", VBAR_EL12, {AArch64::HasV8_1aOps}},
797  {"contextidr_el12", CONTEXTIDR_EL12, {AArch64::HasV8_1aOps}},
798  {"cntkctl_el12", CNTKCTL_EL12, {AArch64::HasV8_1aOps}},
799  {"cntp_tval_el02", CNTP_TVAL_EL02, {AArch64::HasV8_1aOps}},
800  {"cntp_ctl_el02", CNTP_CTL_EL02, {AArch64::HasV8_1aOps}},
801  {"cntp_cval_el02", CNTP_CVAL_EL02, {AArch64::HasV8_1aOps}},
802  {"cntv_tval_el02", CNTV_TVAL_EL02, {AArch64::HasV8_1aOps}},
803  {"cntv_ctl_el02", CNTV_CTL_EL02, {AArch64::HasV8_1aOps}},
804  {"cntv_cval_el02", CNTV_CVAL_EL02, {AArch64::HasV8_1aOps}},
805  {"spsr_el12", SPSR_EL12, {AArch64::HasV8_1aOps}},
806  {"elr_el12", ELR_EL12, {AArch64::HasV8_1aOps}},
807};
808
809uint32_t
810AArch64SysReg::SysRegMapper::fromString(StringRef Name,
811    const FeatureBitset& FeatureBits, bool &Valid) const {
812  std::string NameLower = Name.lower();
813
814  // First search the registers shared by all
815  for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
816    if (SysRegMappings[i].isNameEqual(NameLower, FeatureBits)) {
817      Valid = true;
818      return SysRegMappings[i].Value;
819    }
820  }
821
822  // Now try the instruction-specific registers (either read-only or
823  // write-only).
824  for (unsigned i = 0; i < NumInstMappings; ++i) {
825    if (InstMappings[i].isNameEqual(NameLower, FeatureBits)) {
826      Valid = true;
827      return InstMappings[i].Value;
828    }
829  }
830
831  // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
832  Regex GenericRegPattern("^s([0-3])_([0-7])_c([0-9]|1[0-5])_c([0-9]|1[0-5])_([0-7])$");
833
834  SmallVector<StringRef, 5> Ops;
835  if (!GenericRegPattern.match(NameLower, &Ops)) {
836    Valid = false;
837    return -1;
838  }
839
840  uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
841  uint32_t Bits;
842  Ops[1].getAsInteger(10, Op0);
843  Ops[2].getAsInteger(10, Op1);
844  Ops[3].getAsInteger(10, CRn);
845  Ops[4].getAsInteger(10, CRm);
846  Ops[5].getAsInteger(10, Op2);
847  Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
848
849  Valid = true;
850  return Bits;
851}
852
853std::string
854AArch64SysReg::SysRegMapper::toString(uint32_t Bits,
855                                      const FeatureBitset& FeatureBits) const {
856  // First search the registers shared by all
857  for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
858    if (SysRegMappings[i].isValueEqual(Bits, FeatureBits)) {
859      return SysRegMappings[i].Name;
860    }
861  }
862
863  // Now try the instruction-specific registers (either read-only or
864  // write-only).
865  for (unsigned i = 0; i < NumInstMappings; ++i) {
866    if (InstMappings[i].isValueEqual(Bits, FeatureBits)) {
867      return InstMappings[i].Name;
868    }
869  }
870
871  assert(Bits < 0x10000);
872  uint32_t Op0 = (Bits >> 14) & 0x3;
873  uint32_t Op1 = (Bits >> 11) & 0x7;
874  uint32_t CRn = (Bits >> 7) & 0xf;
875  uint32_t CRm = (Bits >> 3) & 0xf;
876  uint32_t Op2 = Bits & 0x7;
877
878  return "s" + utostr(Op0)+ "_" + utostr(Op1) + "_c" + utostr(CRn)
879               + "_c" + utostr(CRm) + "_" + utostr(Op2);
880}
881
882const AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIMappings[] = {
883  {"ipas2e1is", IPAS2E1IS, {}},
884  {"ipas2le1is", IPAS2LE1IS, {}},
885  {"vmalle1is", VMALLE1IS, {}},
886  {"alle2is", ALLE2IS, {}},
887  {"alle3is", ALLE3IS, {}},
888  {"vae1is", VAE1IS, {}},
889  {"vae2is", VAE2IS, {}},
890  {"vae3is", VAE3IS, {}},
891  {"aside1is", ASIDE1IS, {}},
892  {"vaae1is", VAAE1IS, {}},
893  {"alle1is", ALLE1IS, {}},
894  {"vale1is", VALE1IS, {}},
895  {"vale2is", VALE2IS, {}},
896  {"vale3is", VALE3IS, {}},
897  {"vmalls12e1is", VMALLS12E1IS, {}},
898  {"vaale1is", VAALE1IS, {}},
899  {"ipas2e1", IPAS2E1, {}},
900  {"ipas2le1", IPAS2LE1, {}},
901  {"vmalle1", VMALLE1, {}},
902  {"alle2", ALLE2, {}},
903  {"alle3", ALLE3, {}},
904  {"vae1", VAE1, {}},
905  {"vae2", VAE2, {}},
906  {"vae3", VAE3, {}},
907  {"aside1", ASIDE1, {}},
908  {"vaae1", VAAE1, {}},
909  {"alle1", ALLE1, {}},
910  {"vale1", VALE1, {}},
911  {"vale2", VALE2, {}},
912  {"vale3", VALE3, {}},
913  {"vmalls12e1", VMALLS12E1, {}},
914  {"vaale1", VAALE1, {}}
915};
916
917AArch64TLBI::TLBIMapper::TLBIMapper()
918  : AArch64NamedImmMapper(TLBIMappings, 0) {}
919