1249259Sdim//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim// This file provides basic encoding and assembly information for AArch64. 11249259Sdim// 12249259Sdim//===----------------------------------------------------------------------===// 13249259Sdim#include "AArch64BaseInfo.h" 14249259Sdim#include "llvm/ADT/APFloat.h" 15249259Sdim#include "llvm/ADT/SmallVector.h" 16249259Sdim#include "llvm/ADT/StringExtras.h" 17249259Sdim#include "llvm/Support/Regex.h" 18249259Sdim 19249259Sdimusing namespace llvm; 20249259Sdim 21288943SdimStringRef AArch64NamedImmMapper::toString(uint32_t Value, 22288943Sdim const FeatureBitset& FeatureBits, bool &Valid) const { 23288943Sdim for (unsigned i = 0; i < NumMappings; ++i) { 24288943Sdim if (Mappings[i].isValueEqual(Value, FeatureBits)) { 25249259Sdim Valid = true; 26288943Sdim return Mappings[i].Name; 27249259Sdim } 28249259Sdim } 29249259Sdim 30249259Sdim Valid = false; 31249259Sdim return StringRef(); 32249259Sdim} 33249259Sdim 34288943Sdimuint32_t AArch64NamedImmMapper::fromString(StringRef Name, 35288943Sdim const FeatureBitset& FeatureBits, bool &Valid) const { 36249259Sdim std::string LowerCaseName = Name.lower(); 37288943Sdim for (unsigned i = 0; i < NumMappings; ++i) { 38288943Sdim if (Mappings[i].isNameEqual(LowerCaseName, FeatureBits)) { 39249259Sdim Valid = true; 40288943Sdim return Mappings[i].Value; 41249259Sdim } 42249259Sdim } 43249259Sdim 44249259Sdim Valid = false; 45249259Sdim return -1; 46249259Sdim} 47249259Sdim 48276479Sdimbool AArch64NamedImmMapper::validImm(uint32_t Value) const { 49249259Sdim return Value < TooBigImm; 50249259Sdim} 51249259Sdim 52288943Sdimconst AArch64NamedImmMapper::Mapping AArch64AT::ATMapper::ATMappings[] = { 53288943Sdim {"s1e1r", S1E1R, {}}, 54288943Sdim {"s1e2r", S1E2R, {}}, 55288943Sdim {"s1e3r", S1E3R, {}}, 56288943Sdim {"s1e1w", S1E1W, {}}, 57288943Sdim {"s1e2w", S1E2W, {}}, 58288943Sdim {"s1e3w", S1E3W, {}}, 59288943Sdim {"s1e0r", S1E0R, {}}, 60288943Sdim {"s1e0w", S1E0W, {}}, 61288943Sdim {"s12e1r", S12E1R, {}}, 62288943Sdim {"s12e1w", S12E1W, {}}, 63288943Sdim {"s12e0r", S12E0R, {}}, 64288943Sdim {"s12e0w", S12E0W, {}}, 65249259Sdim}; 66249259Sdim 67276479SdimAArch64AT::ATMapper::ATMapper() 68288943Sdim : AArch64NamedImmMapper(ATMappings, 0) {} 69249259Sdim 70288943Sdimconst AArch64NamedImmMapper::Mapping AArch64DB::DBarrierMapper::DBarrierMappings[] = { 71288943Sdim {"oshld", OSHLD, {}}, 72288943Sdim {"oshst", OSHST, {}}, 73288943Sdim {"osh", OSH, {}}, 74288943Sdim {"nshld", NSHLD, {}}, 75288943Sdim {"nshst", NSHST, {}}, 76288943Sdim {"nsh", NSH, {}}, 77288943Sdim {"ishld", ISHLD, {}}, 78288943Sdim {"ishst", ISHST, {}}, 79288943Sdim {"ish", ISH, {}}, 80288943Sdim {"ld", LD, {}}, 81288943Sdim {"st", ST, {}}, 82288943Sdim {"sy", SY, {}} 83249259Sdim}; 84249259Sdim 85276479SdimAArch64DB::DBarrierMapper::DBarrierMapper() 86288943Sdim : AArch64NamedImmMapper(DBarrierMappings, 16u) {} 87249259Sdim 88288943Sdimconst AArch64NamedImmMapper::Mapping AArch64DC::DCMapper::DCMappings[] = { 89288943Sdim {"zva", ZVA, {}}, 90288943Sdim {"ivac", IVAC, {}}, 91288943Sdim {"isw", ISW, {}}, 92288943Sdim {"cvac", CVAC, {}}, 93288943Sdim {"csw", CSW, {}}, 94288943Sdim {"cvau", CVAU, {}}, 95288943Sdim {"civac", CIVAC, {}}, 96288943Sdim {"cisw", CISW, {}} 97249259Sdim}; 98249259Sdim 99276479SdimAArch64DC::DCMapper::DCMapper() 100288943Sdim : AArch64NamedImmMapper(DCMappings, 0) {} 101249259Sdim 102288943Sdimconst AArch64NamedImmMapper::Mapping AArch64IC::ICMapper::ICMappings[] = { 103288943Sdim {"ialluis", IALLUIS, {}}, 104288943Sdim {"iallu", IALLU, {}}, 105288943Sdim {"ivau", IVAU, {}} 106249259Sdim}; 107249259Sdim 108276479SdimAArch64IC::ICMapper::ICMapper() 109288943Sdim : AArch64NamedImmMapper(ICMappings, 0) {} 110249259Sdim 111288943Sdimconst AArch64NamedImmMapper::Mapping AArch64ISB::ISBMapper::ISBMappings[] = { 112288943Sdim {"sy", SY, {}}, 113249259Sdim}; 114249259Sdim 115276479SdimAArch64ISB::ISBMapper::ISBMapper() 116288943Sdim : AArch64NamedImmMapper(ISBMappings, 16) {} 117249259Sdim 118288943Sdimconst AArch64NamedImmMapper::Mapping AArch64PRFM::PRFMMapper::PRFMMappings[] = { 119288943Sdim {"pldl1keep", PLDL1KEEP, {}}, 120288943Sdim {"pldl1strm", PLDL1STRM, {}}, 121288943Sdim {"pldl2keep", PLDL2KEEP, {}}, 122288943Sdim {"pldl2strm", PLDL2STRM, {}}, 123288943Sdim {"pldl3keep", PLDL3KEEP, {}}, 124288943Sdim {"pldl3strm", PLDL3STRM, {}}, 125288943Sdim {"plil1keep", PLIL1KEEP, {}}, 126288943Sdim {"plil1strm", PLIL1STRM, {}}, 127288943Sdim {"plil2keep", PLIL2KEEP, {}}, 128288943Sdim {"plil2strm", PLIL2STRM, {}}, 129288943Sdim {"plil3keep", PLIL3KEEP, {}}, 130288943Sdim {"plil3strm", PLIL3STRM, {}}, 131288943Sdim {"pstl1keep", PSTL1KEEP, {}}, 132288943Sdim {"pstl1strm", PSTL1STRM, {}}, 133288943Sdim {"pstl2keep", PSTL2KEEP, {}}, 134288943Sdim {"pstl2strm", PSTL2STRM, {}}, 135288943Sdim {"pstl3keep", PSTL3KEEP, {}}, 136288943Sdim {"pstl3strm", PSTL3STRM, {}} 137249259Sdim}; 138249259Sdim 139276479SdimAArch64PRFM::PRFMMapper::PRFMMapper() 140288943Sdim : AArch64NamedImmMapper(PRFMMappings, 32) {} 141249259Sdim 142288943Sdimconst AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStateMappings[] = { 143288943Sdim {"spsel", SPSel, {}}, 144288943Sdim {"daifset", DAIFSet, {}}, 145288943Sdim {"daifclr", DAIFClr, {}}, 146288943Sdim 147288943Sdim // v8.1a "Privileged Access Never" extension-specific PStates 148288943Sdim {"pan", PAN, {AArch64::HasV8_1aOps}}, 149296417Sdim 150296417Sdim // v8.2a 151296417Sdim {"uao", UAO, {AArch64::HasV8_2aOps}}, 152249259Sdim}; 153249259Sdim 154276479SdimAArch64PState::PStateMapper::PStateMapper() 155288943Sdim : AArch64NamedImmMapper(PStateMappings, 0) {} 156249259Sdim 157296417Sdimconst AArch64NamedImmMapper::Mapping AArch64PSBHint::PSBHintMapper::PSBHintMappings[] = { 158296417Sdim // v8.2a "Statistical Profiling" extension-specific PSB operand 159296417Sdim {"csync", CSync, {AArch64::FeatureSPE}}, 160296417Sdim}; 161296417Sdim 162296417SdimAArch64PSBHint::PSBHintMapper::PSBHintMapper() 163296417Sdim : AArch64NamedImmMapper(PSBHintMappings, 0) {} 164296417Sdim 165288943Sdimconst AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = { 166288943Sdim {"mdccsr_el0", MDCCSR_EL0, {}}, 167288943Sdim {"dbgdtrrx_el0", DBGDTRRX_EL0, {}}, 168288943Sdim {"mdrar_el1", MDRAR_EL1, {}}, 169288943Sdim {"oslsr_el1", OSLSR_EL1, {}}, 170288943Sdim {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1, {}}, 171288943Sdim {"pmceid0_el0", PMCEID0_EL0, {}}, 172288943Sdim {"pmceid1_el0", PMCEID1_EL0, {}}, 173288943Sdim {"midr_el1", MIDR_EL1, {}}, 174288943Sdim {"ccsidr_el1", CCSIDR_EL1, {}}, 175288943Sdim {"clidr_el1", CLIDR_EL1, {}}, 176288943Sdim {"ctr_el0", CTR_EL0, {}}, 177288943Sdim {"mpidr_el1", MPIDR_EL1, {}}, 178288943Sdim {"revidr_el1", REVIDR_EL1, {}}, 179288943Sdim {"aidr_el1", AIDR_EL1, {}}, 180288943Sdim {"dczid_el0", DCZID_EL0, {}}, 181288943Sdim {"id_pfr0_el1", ID_PFR0_EL1, {}}, 182288943Sdim {"id_pfr1_el1", ID_PFR1_EL1, {}}, 183288943Sdim {"id_dfr0_el1", ID_DFR0_EL1, {}}, 184288943Sdim {"id_afr0_el1", ID_AFR0_EL1, {}}, 185288943Sdim {"id_mmfr0_el1", ID_MMFR0_EL1, {}}, 186288943Sdim {"id_mmfr1_el1", ID_MMFR1_EL1, {}}, 187288943Sdim {"id_mmfr2_el1", ID_MMFR2_EL1, {}}, 188288943Sdim {"id_mmfr3_el1", ID_MMFR3_EL1, {}}, 189288943Sdim {"id_mmfr4_el1", ID_MMFR4_EL1, {}}, 190288943Sdim {"id_isar0_el1", ID_ISAR0_EL1, {}}, 191288943Sdim {"id_isar1_el1", ID_ISAR1_EL1, {}}, 192288943Sdim {"id_isar2_el1", ID_ISAR2_EL1, {}}, 193288943Sdim {"id_isar3_el1", ID_ISAR3_EL1, {}}, 194288943Sdim {"id_isar4_el1", ID_ISAR4_EL1, {}}, 195288943Sdim {"id_isar5_el1", ID_ISAR5_EL1, {}}, 196288943Sdim {"id_aa64pfr0_el1", ID_A64PFR0_EL1, {}}, 197288943Sdim {"id_aa64pfr1_el1", ID_A64PFR1_EL1, {}}, 198288943Sdim {"id_aa64dfr0_el1", ID_A64DFR0_EL1, {}}, 199288943Sdim {"id_aa64dfr1_el1", ID_A64DFR1_EL1, {}}, 200288943Sdim {"id_aa64afr0_el1", ID_A64AFR0_EL1, {}}, 201288943Sdim {"id_aa64afr1_el1", ID_A64AFR1_EL1, {}}, 202288943Sdim {"id_aa64isar0_el1", ID_A64ISAR0_EL1, {}}, 203288943Sdim {"id_aa64isar1_el1", ID_A64ISAR1_EL1, {}}, 204288943Sdim {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, {}}, 205288943Sdim {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, {}}, 206296417Sdim {"id_aa64mmfr2_el1", ID_A64MMFR2_EL1, {AArch64::HasV8_2aOps}}, 207288943Sdim {"mvfr0_el1", MVFR0_EL1, {}}, 208288943Sdim {"mvfr1_el1", MVFR1_EL1, {}}, 209288943Sdim {"mvfr2_el1", MVFR2_EL1, {}}, 210288943Sdim {"rvbar_el1", RVBAR_EL1, {}}, 211288943Sdim {"rvbar_el2", RVBAR_EL2, {}}, 212288943Sdim {"rvbar_el3", RVBAR_EL3, {}}, 213288943Sdim {"isr_el1", ISR_EL1, {}}, 214288943Sdim {"cntpct_el0", CNTPCT_EL0, {}}, 215288943Sdim {"cntvct_el0", CNTVCT_EL0, {}}, 216249259Sdim 217249259Sdim // Trace registers 218288943Sdim {"trcstatr", TRCSTATR, {}}, 219288943Sdim {"trcidr8", TRCIDR8, {}}, 220288943Sdim {"trcidr9", TRCIDR9, {}}, 221288943Sdim {"trcidr10", TRCIDR10, {}}, 222288943Sdim {"trcidr11", TRCIDR11, {}}, 223288943Sdim {"trcidr12", TRCIDR12, {}}, 224288943Sdim {"trcidr13", TRCIDR13, {}}, 225288943Sdim {"trcidr0", TRCIDR0, {}}, 226288943Sdim {"trcidr1", TRCIDR1, {}}, 227288943Sdim {"trcidr2", TRCIDR2, {}}, 228288943Sdim {"trcidr3", TRCIDR3, {}}, 229288943Sdim {"trcidr4", TRCIDR4, {}}, 230288943Sdim {"trcidr5", TRCIDR5, {}}, 231288943Sdim {"trcidr6", TRCIDR6, {}}, 232288943Sdim {"trcidr7", TRCIDR7, {}}, 233288943Sdim {"trcoslsr", TRCOSLSR, {}}, 234288943Sdim {"trcpdsr", TRCPDSR, {}}, 235288943Sdim {"trcdevaff0", TRCDEVAFF0, {}}, 236288943Sdim {"trcdevaff1", TRCDEVAFF1, {}}, 237288943Sdim {"trclsr", TRCLSR, {}}, 238288943Sdim {"trcauthstatus", TRCAUTHSTATUS, {}}, 239288943Sdim {"trcdevarch", TRCDEVARCH, {}}, 240288943Sdim {"trcdevid", TRCDEVID, {}}, 241288943Sdim {"trcdevtype", TRCDEVTYPE, {}}, 242288943Sdim {"trcpidr4", TRCPIDR4, {}}, 243288943Sdim {"trcpidr5", TRCPIDR5, {}}, 244288943Sdim {"trcpidr6", TRCPIDR6, {}}, 245288943Sdim {"trcpidr7", TRCPIDR7, {}}, 246288943Sdim {"trcpidr0", TRCPIDR0, {}}, 247288943Sdim {"trcpidr1", TRCPIDR1, {}}, 248288943Sdim {"trcpidr2", TRCPIDR2, {}}, 249288943Sdim {"trcpidr3", TRCPIDR3, {}}, 250288943Sdim {"trccidr0", TRCCIDR0, {}}, 251288943Sdim {"trccidr1", TRCCIDR1, {}}, 252288943Sdim {"trccidr2", TRCCIDR2, {}}, 253288943Sdim {"trccidr3", TRCCIDR3, {}}, 254249259Sdim 255249259Sdim // GICv3 registers 256288943Sdim {"icc_iar1_el1", ICC_IAR1_EL1, {}}, 257288943Sdim {"icc_iar0_el1", ICC_IAR0_EL1, {}}, 258288943Sdim {"icc_hppir1_el1", ICC_HPPIR1_EL1, {}}, 259288943Sdim {"icc_hppir0_el1", ICC_HPPIR0_EL1, {}}, 260288943Sdim {"icc_rpr_el1", ICC_RPR_EL1, {}}, 261288943Sdim {"ich_vtr_el2", ICH_VTR_EL2, {}}, 262288943Sdim {"ich_eisr_el2", ICH_EISR_EL2, {}}, 263288943Sdim {"ich_elsr_el2", ICH_ELSR_EL2, {}}, 264288943Sdim 265288943Sdim // v8.1a "Limited Ordering Regions" extension-specific system registers 266288943Sdim {"lorid_el1", LORID_EL1, {AArch64::HasV8_1aOps}}, 267249259Sdim}; 268249259Sdim 269288943SdimAArch64SysReg::MRSMapper::MRSMapper() { 270288943Sdim InstMappings = &MRSMappings[0]; 271288943Sdim NumInstMappings = llvm::array_lengthof(MRSMappings); 272249259Sdim} 273249259Sdim 274288943Sdimconst AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRMappings[] = { 275288943Sdim {"dbgdtrtx_el0", DBGDTRTX_EL0, {}}, 276288943Sdim {"oslar_el1", OSLAR_EL1, {}}, 277288943Sdim {"pmswinc_el0", PMSWINC_EL0, {}}, 278249259Sdim 279249259Sdim // Trace registers 280288943Sdim {"trcoslar", TRCOSLAR, {}}, 281288943Sdim {"trclar", TRCLAR, {}}, 282249259Sdim 283249259Sdim // GICv3 registers 284288943Sdim {"icc_eoir1_el1", ICC_EOIR1_EL1, {}}, 285288943Sdim {"icc_eoir0_el1", ICC_EOIR0_EL1, {}}, 286288943Sdim {"icc_dir_el1", ICC_DIR_EL1, {}}, 287288943Sdim {"icc_sgi1r_el1", ICC_SGI1R_EL1, {}}, 288288943Sdim {"icc_asgi1r_el1", ICC_ASGI1R_EL1, {}}, 289288943Sdim {"icc_sgi0r_el1", ICC_SGI0R_EL1, {}}, 290249259Sdim}; 291249259Sdim 292288943SdimAArch64SysReg::MSRMapper::MSRMapper() { 293288943Sdim InstMappings = &MSRMappings[0]; 294288943Sdim NumInstMappings = llvm::array_lengthof(MSRMappings); 295249259Sdim} 296249259Sdim 297249259Sdim 298288943Sdimconst AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = { 299288943Sdim {"osdtrrx_el1", OSDTRRX_EL1, {}}, 300288943Sdim {"osdtrtx_el1", OSDTRTX_EL1, {}}, 301288943Sdim {"teecr32_el1", TEECR32_EL1, {}}, 302288943Sdim {"mdccint_el1", MDCCINT_EL1, {}}, 303288943Sdim {"mdscr_el1", MDSCR_EL1, {}}, 304288943Sdim {"dbgdtr_el0", DBGDTR_EL0, {}}, 305288943Sdim {"oseccr_el1", OSECCR_EL1, {}}, 306288943Sdim {"dbgvcr32_el2", DBGVCR32_EL2, {}}, 307288943Sdim {"dbgbvr0_el1", DBGBVR0_EL1, {}}, 308288943Sdim {"dbgbvr1_el1", DBGBVR1_EL1, {}}, 309288943Sdim {"dbgbvr2_el1", DBGBVR2_EL1, {}}, 310288943Sdim {"dbgbvr3_el1", DBGBVR3_EL1, {}}, 311288943Sdim {"dbgbvr4_el1", DBGBVR4_EL1, {}}, 312288943Sdim {"dbgbvr5_el1", DBGBVR5_EL1, {}}, 313288943Sdim {"dbgbvr6_el1", DBGBVR6_EL1, {}}, 314288943Sdim {"dbgbvr7_el1", DBGBVR7_EL1, {}}, 315288943Sdim {"dbgbvr8_el1", DBGBVR8_EL1, {}}, 316288943Sdim {"dbgbvr9_el1", DBGBVR9_EL1, {}}, 317288943Sdim {"dbgbvr10_el1", DBGBVR10_EL1, {}}, 318288943Sdim {"dbgbvr11_el1", DBGBVR11_EL1, {}}, 319288943Sdim {"dbgbvr12_el1", DBGBVR12_EL1, {}}, 320288943Sdim {"dbgbvr13_el1", DBGBVR13_EL1, {}}, 321288943Sdim {"dbgbvr14_el1", DBGBVR14_EL1, {}}, 322288943Sdim {"dbgbvr15_el1", DBGBVR15_EL1, {}}, 323288943Sdim {"dbgbcr0_el1", DBGBCR0_EL1, {}}, 324288943Sdim {"dbgbcr1_el1", DBGBCR1_EL1, {}}, 325288943Sdim {"dbgbcr2_el1", DBGBCR2_EL1, {}}, 326288943Sdim {"dbgbcr3_el1", DBGBCR3_EL1, {}}, 327288943Sdim {"dbgbcr4_el1", DBGBCR4_EL1, {}}, 328288943Sdim {"dbgbcr5_el1", DBGBCR5_EL1, {}}, 329288943Sdim {"dbgbcr6_el1", DBGBCR6_EL1, {}}, 330288943Sdim {"dbgbcr7_el1", DBGBCR7_EL1, {}}, 331288943Sdim {"dbgbcr8_el1", DBGBCR8_EL1, {}}, 332288943Sdim {"dbgbcr9_el1", DBGBCR9_EL1, {}}, 333288943Sdim {"dbgbcr10_el1", DBGBCR10_EL1, {}}, 334288943Sdim {"dbgbcr11_el1", DBGBCR11_EL1, {}}, 335288943Sdim {"dbgbcr12_el1", DBGBCR12_EL1, {}}, 336288943Sdim {"dbgbcr13_el1", DBGBCR13_EL1, {}}, 337288943Sdim {"dbgbcr14_el1", DBGBCR14_EL1, {}}, 338288943Sdim {"dbgbcr15_el1", DBGBCR15_EL1, {}}, 339288943Sdim {"dbgwvr0_el1", DBGWVR0_EL1, {}}, 340288943Sdim {"dbgwvr1_el1", DBGWVR1_EL1, {}}, 341288943Sdim {"dbgwvr2_el1", DBGWVR2_EL1, {}}, 342288943Sdim {"dbgwvr3_el1", DBGWVR3_EL1, {}}, 343288943Sdim {"dbgwvr4_el1", DBGWVR4_EL1, {}}, 344288943Sdim {"dbgwvr5_el1", DBGWVR5_EL1, {}}, 345288943Sdim {"dbgwvr6_el1", DBGWVR6_EL1, {}}, 346288943Sdim {"dbgwvr7_el1", DBGWVR7_EL1, {}}, 347288943Sdim {"dbgwvr8_el1", DBGWVR8_EL1, {}}, 348288943Sdim {"dbgwvr9_el1", DBGWVR9_EL1, {}}, 349288943Sdim {"dbgwvr10_el1", DBGWVR10_EL1, {}}, 350288943Sdim {"dbgwvr11_el1", DBGWVR11_EL1, {}}, 351288943Sdim {"dbgwvr12_el1", DBGWVR12_EL1, {}}, 352288943Sdim {"dbgwvr13_el1", DBGWVR13_EL1, {}}, 353288943Sdim {"dbgwvr14_el1", DBGWVR14_EL1, {}}, 354288943Sdim {"dbgwvr15_el1", DBGWVR15_EL1, {}}, 355288943Sdim {"dbgwcr0_el1", DBGWCR0_EL1, {}}, 356288943Sdim {"dbgwcr1_el1", DBGWCR1_EL1, {}}, 357288943Sdim {"dbgwcr2_el1", DBGWCR2_EL1, {}}, 358288943Sdim {"dbgwcr3_el1", DBGWCR3_EL1, {}}, 359288943Sdim {"dbgwcr4_el1", DBGWCR4_EL1, {}}, 360288943Sdim {"dbgwcr5_el1", DBGWCR5_EL1, {}}, 361288943Sdim {"dbgwcr6_el1", DBGWCR6_EL1, {}}, 362288943Sdim {"dbgwcr7_el1", DBGWCR7_EL1, {}}, 363288943Sdim {"dbgwcr8_el1", DBGWCR8_EL1, {}}, 364288943Sdim {"dbgwcr9_el1", DBGWCR9_EL1, {}}, 365288943Sdim {"dbgwcr10_el1", DBGWCR10_EL1, {}}, 366288943Sdim {"dbgwcr11_el1", DBGWCR11_EL1, {}}, 367288943Sdim {"dbgwcr12_el1", DBGWCR12_EL1, {}}, 368288943Sdim {"dbgwcr13_el1", DBGWCR13_EL1, {}}, 369288943Sdim {"dbgwcr14_el1", DBGWCR14_EL1, {}}, 370288943Sdim {"dbgwcr15_el1", DBGWCR15_EL1, {}}, 371288943Sdim {"teehbr32_el1", TEEHBR32_EL1, {}}, 372288943Sdim {"osdlr_el1", OSDLR_EL1, {}}, 373288943Sdim {"dbgprcr_el1", DBGPRCR_EL1, {}}, 374288943Sdim {"dbgclaimset_el1", DBGCLAIMSET_EL1, {}}, 375288943Sdim {"dbgclaimclr_el1", DBGCLAIMCLR_EL1, {}}, 376288943Sdim {"csselr_el1", CSSELR_EL1, {}}, 377288943Sdim {"vpidr_el2", VPIDR_EL2, {}}, 378288943Sdim {"vmpidr_el2", VMPIDR_EL2, {}}, 379288943Sdim {"sctlr_el1", SCTLR_EL1, {}}, 380288943Sdim {"sctlr_el2", SCTLR_EL2, {}}, 381288943Sdim {"sctlr_el3", SCTLR_EL3, {}}, 382288943Sdim {"actlr_el1", ACTLR_EL1, {}}, 383288943Sdim {"actlr_el2", ACTLR_EL2, {}}, 384288943Sdim {"actlr_el3", ACTLR_EL3, {}}, 385288943Sdim {"cpacr_el1", CPACR_EL1, {}}, 386288943Sdim {"hcr_el2", HCR_EL2, {}}, 387288943Sdim {"scr_el3", SCR_EL3, {}}, 388288943Sdim {"mdcr_el2", MDCR_EL2, {}}, 389288943Sdim {"sder32_el3", SDER32_EL3, {}}, 390288943Sdim {"cptr_el2", CPTR_EL2, {}}, 391288943Sdim {"cptr_el3", CPTR_EL3, {}}, 392288943Sdim {"hstr_el2", HSTR_EL2, {}}, 393288943Sdim {"hacr_el2", HACR_EL2, {}}, 394288943Sdim {"mdcr_el3", MDCR_EL3, {}}, 395288943Sdim {"ttbr0_el1", TTBR0_EL1, {}}, 396288943Sdim {"ttbr0_el2", TTBR0_EL2, {}}, 397288943Sdim {"ttbr0_el3", TTBR0_EL3, {}}, 398288943Sdim {"ttbr1_el1", TTBR1_EL1, {}}, 399288943Sdim {"tcr_el1", TCR_EL1, {}}, 400288943Sdim {"tcr_el2", TCR_EL2, {}}, 401288943Sdim {"tcr_el3", TCR_EL3, {}}, 402288943Sdim {"vttbr_el2", VTTBR_EL2, {}}, 403288943Sdim {"vtcr_el2", VTCR_EL2, {}}, 404288943Sdim {"dacr32_el2", DACR32_EL2, {}}, 405288943Sdim {"spsr_el1", SPSR_EL1, {}}, 406288943Sdim {"spsr_el2", SPSR_EL2, {}}, 407288943Sdim {"spsr_el3", SPSR_EL3, {}}, 408288943Sdim {"elr_el1", ELR_EL1, {}}, 409288943Sdim {"elr_el2", ELR_EL2, {}}, 410288943Sdim {"elr_el3", ELR_EL3, {}}, 411288943Sdim {"sp_el0", SP_EL0, {}}, 412288943Sdim {"sp_el1", SP_EL1, {}}, 413288943Sdim {"sp_el2", SP_EL2, {}}, 414288943Sdim {"spsel", SPSel, {}}, 415288943Sdim {"nzcv", NZCV, {}}, 416288943Sdim {"daif", DAIF, {}}, 417288943Sdim {"currentel", CurrentEL, {}}, 418288943Sdim {"spsr_irq", SPSR_irq, {}}, 419288943Sdim {"spsr_abt", SPSR_abt, {}}, 420288943Sdim {"spsr_und", SPSR_und, {}}, 421288943Sdim {"spsr_fiq", SPSR_fiq, {}}, 422288943Sdim {"fpcr", FPCR, {}}, 423288943Sdim {"fpsr", FPSR, {}}, 424288943Sdim {"dspsr_el0", DSPSR_EL0, {}}, 425288943Sdim {"dlr_el0", DLR_EL0, {}}, 426288943Sdim {"ifsr32_el2", IFSR32_EL2, {}}, 427288943Sdim {"afsr0_el1", AFSR0_EL1, {}}, 428288943Sdim {"afsr0_el2", AFSR0_EL2, {}}, 429288943Sdim {"afsr0_el3", AFSR0_EL3, {}}, 430288943Sdim {"afsr1_el1", AFSR1_EL1, {}}, 431288943Sdim {"afsr1_el2", AFSR1_EL2, {}}, 432288943Sdim {"afsr1_el3", AFSR1_EL3, {}}, 433288943Sdim {"esr_el1", ESR_EL1, {}}, 434288943Sdim {"esr_el2", ESR_EL2, {}}, 435288943Sdim {"esr_el3", ESR_EL3, {}}, 436288943Sdim {"fpexc32_el2", FPEXC32_EL2, {}}, 437288943Sdim {"far_el1", FAR_EL1, {}}, 438288943Sdim {"far_el2", FAR_EL2, {}}, 439288943Sdim {"far_el3", FAR_EL3, {}}, 440288943Sdim {"hpfar_el2", HPFAR_EL2, {}}, 441288943Sdim {"par_el1", PAR_EL1, {}}, 442288943Sdim {"pmcr_el0", PMCR_EL0, {}}, 443288943Sdim {"pmcntenset_el0", PMCNTENSET_EL0, {}}, 444288943Sdim {"pmcntenclr_el0", PMCNTENCLR_EL0, {}}, 445288943Sdim {"pmovsclr_el0", PMOVSCLR_EL0, {}}, 446288943Sdim {"pmselr_el0", PMSELR_EL0, {}}, 447288943Sdim {"pmccntr_el0", PMCCNTR_EL0, {}}, 448288943Sdim {"pmxevtyper_el0", PMXEVTYPER_EL0, {}}, 449288943Sdim {"pmxevcntr_el0", PMXEVCNTR_EL0, {}}, 450288943Sdim {"pmuserenr_el0", PMUSERENR_EL0, {}}, 451288943Sdim {"pmintenset_el1", PMINTENSET_EL1, {}}, 452288943Sdim {"pmintenclr_el1", PMINTENCLR_EL1, {}}, 453288943Sdim {"pmovsset_el0", PMOVSSET_EL0, {}}, 454288943Sdim {"mair_el1", MAIR_EL1, {}}, 455288943Sdim {"mair_el2", MAIR_EL2, {}}, 456288943Sdim {"mair_el3", MAIR_EL3, {}}, 457288943Sdim {"amair_el1", AMAIR_EL1, {}}, 458288943Sdim {"amair_el2", AMAIR_EL2, {}}, 459288943Sdim {"amair_el3", AMAIR_EL3, {}}, 460288943Sdim {"vbar_el1", VBAR_EL1, {}}, 461288943Sdim {"vbar_el2", VBAR_EL2, {}}, 462288943Sdim {"vbar_el3", VBAR_EL3, {}}, 463288943Sdim {"rmr_el1", RMR_EL1, {}}, 464288943Sdim {"rmr_el2", RMR_EL2, {}}, 465288943Sdim {"rmr_el3", RMR_EL3, {}}, 466288943Sdim {"contextidr_el1", CONTEXTIDR_EL1, {}}, 467288943Sdim {"tpidr_el0", TPIDR_EL0, {}}, 468288943Sdim {"tpidr_el2", TPIDR_EL2, {}}, 469288943Sdim {"tpidr_el3", TPIDR_EL3, {}}, 470288943Sdim {"tpidrro_el0", TPIDRRO_EL0, {}}, 471288943Sdim {"tpidr_el1", TPIDR_EL1, {}}, 472288943Sdim {"cntfrq_el0", CNTFRQ_EL0, {}}, 473288943Sdim {"cntvoff_el2", CNTVOFF_EL2, {}}, 474288943Sdim {"cntkctl_el1", CNTKCTL_EL1, {}}, 475288943Sdim {"cnthctl_el2", CNTHCTL_EL2, {}}, 476288943Sdim {"cntp_tval_el0", CNTP_TVAL_EL0, {}}, 477288943Sdim {"cnthp_tval_el2", CNTHP_TVAL_EL2, {}}, 478288943Sdim {"cntps_tval_el1", CNTPS_TVAL_EL1, {}}, 479288943Sdim {"cntp_ctl_el0", CNTP_CTL_EL0, {}}, 480288943Sdim {"cnthp_ctl_el2", CNTHP_CTL_EL2, {}}, 481288943Sdim {"cntps_ctl_el1", CNTPS_CTL_EL1, {}}, 482288943Sdim {"cntp_cval_el0", CNTP_CVAL_EL0, {}}, 483288943Sdim {"cnthp_cval_el2", CNTHP_CVAL_EL2, {}}, 484288943Sdim {"cntps_cval_el1", CNTPS_CVAL_EL1, {}}, 485288943Sdim {"cntv_tval_el0", CNTV_TVAL_EL0, {}}, 486288943Sdim {"cntv_ctl_el0", CNTV_CTL_EL0, {}}, 487288943Sdim {"cntv_cval_el0", CNTV_CVAL_EL0, {}}, 488288943Sdim {"pmevcntr0_el0", PMEVCNTR0_EL0, {}}, 489288943Sdim {"pmevcntr1_el0", PMEVCNTR1_EL0, {}}, 490288943Sdim {"pmevcntr2_el0", PMEVCNTR2_EL0, {}}, 491288943Sdim {"pmevcntr3_el0", PMEVCNTR3_EL0, {}}, 492288943Sdim {"pmevcntr4_el0", PMEVCNTR4_EL0, {}}, 493288943Sdim {"pmevcntr5_el0", PMEVCNTR5_EL0, {}}, 494288943Sdim {"pmevcntr6_el0", PMEVCNTR6_EL0, {}}, 495288943Sdim {"pmevcntr7_el0", PMEVCNTR7_EL0, {}}, 496288943Sdim {"pmevcntr8_el0", PMEVCNTR8_EL0, {}}, 497288943Sdim {"pmevcntr9_el0", PMEVCNTR9_EL0, {}}, 498288943Sdim {"pmevcntr10_el0", PMEVCNTR10_EL0, {}}, 499288943Sdim {"pmevcntr11_el0", PMEVCNTR11_EL0, {}}, 500288943Sdim {"pmevcntr12_el0", PMEVCNTR12_EL0, {}}, 501288943Sdim {"pmevcntr13_el0", PMEVCNTR13_EL0, {}}, 502288943Sdim {"pmevcntr14_el0", PMEVCNTR14_EL0, {}}, 503288943Sdim {"pmevcntr15_el0", PMEVCNTR15_EL0, {}}, 504288943Sdim {"pmevcntr16_el0", PMEVCNTR16_EL0, {}}, 505288943Sdim {"pmevcntr17_el0", PMEVCNTR17_EL0, {}}, 506288943Sdim {"pmevcntr18_el0", PMEVCNTR18_EL0, {}}, 507288943Sdim {"pmevcntr19_el0", PMEVCNTR19_EL0, {}}, 508288943Sdim {"pmevcntr20_el0", PMEVCNTR20_EL0, {}}, 509288943Sdim {"pmevcntr21_el0", PMEVCNTR21_EL0, {}}, 510288943Sdim {"pmevcntr22_el0", PMEVCNTR22_EL0, {}}, 511288943Sdim {"pmevcntr23_el0", PMEVCNTR23_EL0, {}}, 512288943Sdim {"pmevcntr24_el0", PMEVCNTR24_EL0, {}}, 513288943Sdim {"pmevcntr25_el0", PMEVCNTR25_EL0, {}}, 514288943Sdim {"pmevcntr26_el0", PMEVCNTR26_EL0, {}}, 515288943Sdim {"pmevcntr27_el0", PMEVCNTR27_EL0, {}}, 516288943Sdim {"pmevcntr28_el0", PMEVCNTR28_EL0, {}}, 517288943Sdim {"pmevcntr29_el0", PMEVCNTR29_EL0, {}}, 518288943Sdim {"pmevcntr30_el0", PMEVCNTR30_EL0, {}}, 519288943Sdim {"pmccfiltr_el0", PMCCFILTR_EL0, {}}, 520288943Sdim {"pmevtyper0_el0", PMEVTYPER0_EL0, {}}, 521288943Sdim {"pmevtyper1_el0", PMEVTYPER1_EL0, {}}, 522288943Sdim {"pmevtyper2_el0", PMEVTYPER2_EL0, {}}, 523288943Sdim {"pmevtyper3_el0", PMEVTYPER3_EL0, {}}, 524288943Sdim {"pmevtyper4_el0", PMEVTYPER4_EL0, {}}, 525288943Sdim {"pmevtyper5_el0", PMEVTYPER5_EL0, {}}, 526288943Sdim {"pmevtyper6_el0", PMEVTYPER6_EL0, {}}, 527288943Sdim {"pmevtyper7_el0", PMEVTYPER7_EL0, {}}, 528288943Sdim {"pmevtyper8_el0", PMEVTYPER8_EL0, {}}, 529288943Sdim {"pmevtyper9_el0", PMEVTYPER9_EL0, {}}, 530288943Sdim {"pmevtyper10_el0", PMEVTYPER10_EL0, {}}, 531288943Sdim {"pmevtyper11_el0", PMEVTYPER11_EL0, {}}, 532288943Sdim {"pmevtyper12_el0", PMEVTYPER12_EL0, {}}, 533288943Sdim {"pmevtyper13_el0", PMEVTYPER13_EL0, {}}, 534288943Sdim {"pmevtyper14_el0", PMEVTYPER14_EL0, {}}, 535288943Sdim {"pmevtyper15_el0", PMEVTYPER15_EL0, {}}, 536288943Sdim {"pmevtyper16_el0", PMEVTYPER16_EL0, {}}, 537288943Sdim {"pmevtyper17_el0", PMEVTYPER17_EL0, {}}, 538288943Sdim {"pmevtyper18_el0", PMEVTYPER18_EL0, {}}, 539288943Sdim {"pmevtyper19_el0", PMEVTYPER19_EL0, {}}, 540288943Sdim {"pmevtyper20_el0", PMEVTYPER20_EL0, {}}, 541288943Sdim {"pmevtyper21_el0", PMEVTYPER21_EL0, {}}, 542288943Sdim {"pmevtyper22_el0", PMEVTYPER22_EL0, {}}, 543288943Sdim {"pmevtyper23_el0", PMEVTYPER23_EL0, {}}, 544288943Sdim {"pmevtyper24_el0", PMEVTYPER24_EL0, {}}, 545288943Sdim {"pmevtyper25_el0", PMEVTYPER25_EL0, {}}, 546288943Sdim {"pmevtyper26_el0", PMEVTYPER26_EL0, {}}, 547288943Sdim {"pmevtyper27_el0", PMEVTYPER27_EL0, {}}, 548288943Sdim {"pmevtyper28_el0", PMEVTYPER28_EL0, {}}, 549288943Sdim {"pmevtyper29_el0", PMEVTYPER29_EL0, {}}, 550288943Sdim {"pmevtyper30_el0", PMEVTYPER30_EL0, {}}, 551249259Sdim 552249259Sdim // Trace registers 553288943Sdim {"trcprgctlr", TRCPRGCTLR, {}}, 554288943Sdim {"trcprocselr", TRCPROCSELR, {}}, 555288943Sdim {"trcconfigr", TRCCONFIGR, {}}, 556288943Sdim {"trcauxctlr", TRCAUXCTLR, {}}, 557288943Sdim {"trceventctl0r", TRCEVENTCTL0R, {}}, 558288943Sdim {"trceventctl1r", TRCEVENTCTL1R, {}}, 559288943Sdim {"trcstallctlr", TRCSTALLCTLR, {}}, 560288943Sdim {"trctsctlr", TRCTSCTLR, {}}, 561288943Sdim {"trcsyncpr", TRCSYNCPR, {}}, 562288943Sdim {"trcccctlr", TRCCCCTLR, {}}, 563288943Sdim {"trcbbctlr", TRCBBCTLR, {}}, 564288943Sdim {"trctraceidr", TRCTRACEIDR, {}}, 565288943Sdim {"trcqctlr", TRCQCTLR, {}}, 566288943Sdim {"trcvictlr", TRCVICTLR, {}}, 567288943Sdim {"trcviiectlr", TRCVIIECTLR, {}}, 568288943Sdim {"trcvissctlr", TRCVISSCTLR, {}}, 569288943Sdim {"trcvipcssctlr", TRCVIPCSSCTLR, {}}, 570288943Sdim {"trcvdctlr", TRCVDCTLR, {}}, 571288943Sdim {"trcvdsacctlr", TRCVDSACCTLR, {}}, 572288943Sdim {"trcvdarcctlr", TRCVDARCCTLR, {}}, 573288943Sdim {"trcseqevr0", TRCSEQEVR0, {}}, 574288943Sdim {"trcseqevr1", TRCSEQEVR1, {}}, 575288943Sdim {"trcseqevr2", TRCSEQEVR2, {}}, 576288943Sdim {"trcseqrstevr", TRCSEQRSTEVR, {}}, 577288943Sdim {"trcseqstr", TRCSEQSTR, {}}, 578288943Sdim {"trcextinselr", TRCEXTINSELR, {}}, 579288943Sdim {"trccntrldvr0", TRCCNTRLDVR0, {}}, 580288943Sdim {"trccntrldvr1", TRCCNTRLDVR1, {}}, 581288943Sdim {"trccntrldvr2", TRCCNTRLDVR2, {}}, 582288943Sdim {"trccntrldvr3", TRCCNTRLDVR3, {}}, 583288943Sdim {"trccntctlr0", TRCCNTCTLR0, {}}, 584288943Sdim {"trccntctlr1", TRCCNTCTLR1, {}}, 585288943Sdim {"trccntctlr2", TRCCNTCTLR2, {}}, 586288943Sdim {"trccntctlr3", TRCCNTCTLR3, {}}, 587288943Sdim {"trccntvr0", TRCCNTVR0, {}}, 588288943Sdim {"trccntvr1", TRCCNTVR1, {}}, 589288943Sdim {"trccntvr2", TRCCNTVR2, {}}, 590288943Sdim {"trccntvr3", TRCCNTVR3, {}}, 591288943Sdim {"trcimspec0", TRCIMSPEC0, {}}, 592288943Sdim {"trcimspec1", TRCIMSPEC1, {}}, 593288943Sdim {"trcimspec2", TRCIMSPEC2, {}}, 594288943Sdim {"trcimspec3", TRCIMSPEC3, {}}, 595288943Sdim {"trcimspec4", TRCIMSPEC4, {}}, 596288943Sdim {"trcimspec5", TRCIMSPEC5, {}}, 597288943Sdim {"trcimspec6", TRCIMSPEC6, {}}, 598288943Sdim {"trcimspec7", TRCIMSPEC7, {}}, 599288943Sdim {"trcrsctlr2", TRCRSCTLR2, {}}, 600288943Sdim {"trcrsctlr3", TRCRSCTLR3, {}}, 601288943Sdim {"trcrsctlr4", TRCRSCTLR4, {}}, 602288943Sdim {"trcrsctlr5", TRCRSCTLR5, {}}, 603288943Sdim {"trcrsctlr6", TRCRSCTLR6, {}}, 604288943Sdim {"trcrsctlr7", TRCRSCTLR7, {}}, 605288943Sdim {"trcrsctlr8", TRCRSCTLR8, {}}, 606288943Sdim {"trcrsctlr9", TRCRSCTLR9, {}}, 607288943Sdim {"trcrsctlr10", TRCRSCTLR10, {}}, 608288943Sdim {"trcrsctlr11", TRCRSCTLR11, {}}, 609288943Sdim {"trcrsctlr12", TRCRSCTLR12, {}}, 610288943Sdim {"trcrsctlr13", TRCRSCTLR13, {}}, 611288943Sdim {"trcrsctlr14", TRCRSCTLR14, {}}, 612288943Sdim {"trcrsctlr15", TRCRSCTLR15, {}}, 613288943Sdim {"trcrsctlr16", TRCRSCTLR16, {}}, 614288943Sdim {"trcrsctlr17", TRCRSCTLR17, {}}, 615288943Sdim {"trcrsctlr18", TRCRSCTLR18, {}}, 616288943Sdim {"trcrsctlr19", TRCRSCTLR19, {}}, 617288943Sdim {"trcrsctlr20", TRCRSCTLR20, {}}, 618288943Sdim {"trcrsctlr21", TRCRSCTLR21, {}}, 619288943Sdim {"trcrsctlr22", TRCRSCTLR22, {}}, 620288943Sdim {"trcrsctlr23", TRCRSCTLR23, {}}, 621288943Sdim {"trcrsctlr24", TRCRSCTLR24, {}}, 622288943Sdim {"trcrsctlr25", TRCRSCTLR25, {}}, 623288943Sdim {"trcrsctlr26", TRCRSCTLR26, {}}, 624288943Sdim {"trcrsctlr27", TRCRSCTLR27, {}}, 625288943Sdim {"trcrsctlr28", TRCRSCTLR28, {}}, 626288943Sdim {"trcrsctlr29", TRCRSCTLR29, {}}, 627288943Sdim {"trcrsctlr30", TRCRSCTLR30, {}}, 628288943Sdim {"trcrsctlr31", TRCRSCTLR31, {}}, 629288943Sdim {"trcssccr0", TRCSSCCR0, {}}, 630288943Sdim {"trcssccr1", TRCSSCCR1, {}}, 631288943Sdim {"trcssccr2", TRCSSCCR2, {}}, 632288943Sdim {"trcssccr3", TRCSSCCR3, {}}, 633288943Sdim {"trcssccr4", TRCSSCCR4, {}}, 634288943Sdim {"trcssccr5", TRCSSCCR5, {}}, 635288943Sdim {"trcssccr6", TRCSSCCR6, {}}, 636288943Sdim {"trcssccr7", TRCSSCCR7, {}}, 637288943Sdim {"trcsscsr0", TRCSSCSR0, {}}, 638288943Sdim {"trcsscsr1", TRCSSCSR1, {}}, 639288943Sdim {"trcsscsr2", TRCSSCSR2, {}}, 640288943Sdim {"trcsscsr3", TRCSSCSR3, {}}, 641288943Sdim {"trcsscsr4", TRCSSCSR4, {}}, 642288943Sdim {"trcsscsr5", TRCSSCSR5, {}}, 643288943Sdim {"trcsscsr6", TRCSSCSR6, {}}, 644288943Sdim {"trcsscsr7", TRCSSCSR7, {}}, 645288943Sdim {"trcsspcicr0", TRCSSPCICR0, {}}, 646288943Sdim {"trcsspcicr1", TRCSSPCICR1, {}}, 647288943Sdim {"trcsspcicr2", TRCSSPCICR2, {}}, 648288943Sdim {"trcsspcicr3", TRCSSPCICR3, {}}, 649288943Sdim {"trcsspcicr4", TRCSSPCICR4, {}}, 650288943Sdim {"trcsspcicr5", TRCSSPCICR5, {}}, 651288943Sdim {"trcsspcicr6", TRCSSPCICR6, {}}, 652288943Sdim {"trcsspcicr7", TRCSSPCICR7, {}}, 653288943Sdim {"trcpdcr", TRCPDCR, {}}, 654288943Sdim {"trcacvr0", TRCACVR0, {}}, 655288943Sdim {"trcacvr1", TRCACVR1, {}}, 656288943Sdim {"trcacvr2", TRCACVR2, {}}, 657288943Sdim {"trcacvr3", TRCACVR3, {}}, 658288943Sdim {"trcacvr4", TRCACVR4, {}}, 659288943Sdim {"trcacvr5", TRCACVR5, {}}, 660288943Sdim {"trcacvr6", TRCACVR6, {}}, 661288943Sdim {"trcacvr7", TRCACVR7, {}}, 662288943Sdim {"trcacvr8", TRCACVR8, {}}, 663288943Sdim {"trcacvr9", TRCACVR9, {}}, 664288943Sdim {"trcacvr10", TRCACVR10, {}}, 665288943Sdim {"trcacvr11", TRCACVR11, {}}, 666288943Sdim {"trcacvr12", TRCACVR12, {}}, 667288943Sdim {"trcacvr13", TRCACVR13, {}}, 668288943Sdim {"trcacvr14", TRCACVR14, {}}, 669288943Sdim {"trcacvr15", TRCACVR15, {}}, 670288943Sdim {"trcacatr0", TRCACATR0, {}}, 671288943Sdim {"trcacatr1", TRCACATR1, {}}, 672288943Sdim {"trcacatr2", TRCACATR2, {}}, 673288943Sdim {"trcacatr3", TRCACATR3, {}}, 674288943Sdim {"trcacatr4", TRCACATR4, {}}, 675288943Sdim {"trcacatr5", TRCACATR5, {}}, 676288943Sdim {"trcacatr6", TRCACATR6, {}}, 677288943Sdim {"trcacatr7", TRCACATR7, {}}, 678288943Sdim {"trcacatr8", TRCACATR8, {}}, 679288943Sdim {"trcacatr9", TRCACATR9, {}}, 680288943Sdim {"trcacatr10", TRCACATR10, {}}, 681288943Sdim {"trcacatr11", TRCACATR11, {}}, 682288943Sdim {"trcacatr12", TRCACATR12, {}}, 683288943Sdim {"trcacatr13", TRCACATR13, {}}, 684288943Sdim {"trcacatr14", TRCACATR14, {}}, 685288943Sdim {"trcacatr15", TRCACATR15, {}}, 686288943Sdim {"trcdvcvr0", TRCDVCVR0, {}}, 687288943Sdim {"trcdvcvr1", TRCDVCVR1, {}}, 688288943Sdim {"trcdvcvr2", TRCDVCVR2, {}}, 689288943Sdim {"trcdvcvr3", TRCDVCVR3, {}}, 690288943Sdim {"trcdvcvr4", TRCDVCVR4, {}}, 691288943Sdim {"trcdvcvr5", TRCDVCVR5, {}}, 692288943Sdim {"trcdvcvr6", TRCDVCVR6, {}}, 693288943Sdim {"trcdvcvr7", TRCDVCVR7, {}}, 694288943Sdim {"trcdvcmr0", TRCDVCMR0, {}}, 695288943Sdim {"trcdvcmr1", TRCDVCMR1, {}}, 696288943Sdim {"trcdvcmr2", TRCDVCMR2, {}}, 697288943Sdim {"trcdvcmr3", TRCDVCMR3, {}}, 698288943Sdim {"trcdvcmr4", TRCDVCMR4, {}}, 699288943Sdim {"trcdvcmr5", TRCDVCMR5, {}}, 700288943Sdim {"trcdvcmr6", TRCDVCMR6, {}}, 701288943Sdim {"trcdvcmr7", TRCDVCMR7, {}}, 702288943Sdim {"trccidcvr0", TRCCIDCVR0, {}}, 703288943Sdim {"trccidcvr1", TRCCIDCVR1, {}}, 704288943Sdim {"trccidcvr2", TRCCIDCVR2, {}}, 705288943Sdim {"trccidcvr3", TRCCIDCVR3, {}}, 706288943Sdim {"trccidcvr4", TRCCIDCVR4, {}}, 707288943Sdim {"trccidcvr5", TRCCIDCVR5, {}}, 708288943Sdim {"trccidcvr6", TRCCIDCVR6, {}}, 709288943Sdim {"trccidcvr7", TRCCIDCVR7, {}}, 710288943Sdim {"trcvmidcvr0", TRCVMIDCVR0, {}}, 711288943Sdim {"trcvmidcvr1", TRCVMIDCVR1, {}}, 712288943Sdim {"trcvmidcvr2", TRCVMIDCVR2, {}}, 713288943Sdim {"trcvmidcvr3", TRCVMIDCVR3, {}}, 714288943Sdim {"trcvmidcvr4", TRCVMIDCVR4, {}}, 715288943Sdim {"trcvmidcvr5", TRCVMIDCVR5, {}}, 716288943Sdim {"trcvmidcvr6", TRCVMIDCVR6, {}}, 717288943Sdim {"trcvmidcvr7", TRCVMIDCVR7, {}}, 718288943Sdim {"trccidcctlr0", TRCCIDCCTLR0, {}}, 719288943Sdim {"trccidcctlr1", TRCCIDCCTLR1, {}}, 720288943Sdim {"trcvmidcctlr0", TRCVMIDCCTLR0, {}}, 721288943Sdim {"trcvmidcctlr1", TRCVMIDCCTLR1, {}}, 722288943Sdim {"trcitctrl", TRCITCTRL, {}}, 723288943Sdim {"trcclaimset", TRCCLAIMSET, {}}, 724288943Sdim {"trcclaimclr", TRCCLAIMCLR, {}}, 725249259Sdim 726249259Sdim // GICv3 registers 727288943Sdim {"icc_bpr1_el1", ICC_BPR1_EL1, {}}, 728288943Sdim {"icc_bpr0_el1", ICC_BPR0_EL1, {}}, 729288943Sdim {"icc_pmr_el1", ICC_PMR_EL1, {}}, 730288943Sdim {"icc_ctlr_el1", ICC_CTLR_EL1, {}}, 731288943Sdim {"icc_ctlr_el3", ICC_CTLR_EL3, {}}, 732288943Sdim {"icc_sre_el1", ICC_SRE_EL1, {}}, 733288943Sdim {"icc_sre_el2", ICC_SRE_EL2, {}}, 734288943Sdim {"icc_sre_el3", ICC_SRE_EL3, {}}, 735288943Sdim {"icc_igrpen0_el1", ICC_IGRPEN0_EL1, {}}, 736288943Sdim {"icc_igrpen1_el1", ICC_IGRPEN1_EL1, {}}, 737288943Sdim {"icc_igrpen1_el3", ICC_IGRPEN1_EL3, {}}, 738288943Sdim {"icc_seien_el1", ICC_SEIEN_EL1, {}}, 739288943Sdim {"icc_ap0r0_el1", ICC_AP0R0_EL1, {}}, 740288943Sdim {"icc_ap0r1_el1", ICC_AP0R1_EL1, {}}, 741288943Sdim {"icc_ap0r2_el1", ICC_AP0R2_EL1, {}}, 742288943Sdim {"icc_ap0r3_el1", ICC_AP0R3_EL1, {}}, 743288943Sdim {"icc_ap1r0_el1", ICC_AP1R0_EL1, {}}, 744288943Sdim {"icc_ap1r1_el1", ICC_AP1R1_EL1, {}}, 745288943Sdim {"icc_ap1r2_el1", ICC_AP1R2_EL1, {}}, 746288943Sdim {"icc_ap1r3_el1", ICC_AP1R3_EL1, {}}, 747288943Sdim {"ich_ap0r0_el2", ICH_AP0R0_EL2, {}}, 748288943Sdim {"ich_ap0r1_el2", ICH_AP0R1_EL2, {}}, 749288943Sdim {"ich_ap0r2_el2", ICH_AP0R2_EL2, {}}, 750288943Sdim {"ich_ap0r3_el2", ICH_AP0R3_EL2, {}}, 751288943Sdim {"ich_ap1r0_el2", ICH_AP1R0_EL2, {}}, 752288943Sdim {"ich_ap1r1_el2", ICH_AP1R1_EL2, {}}, 753288943Sdim {"ich_ap1r2_el2", ICH_AP1R2_EL2, {}}, 754288943Sdim {"ich_ap1r3_el2", ICH_AP1R3_EL2, {}}, 755288943Sdim {"ich_hcr_el2", ICH_HCR_EL2, {}}, 756288943Sdim {"ich_misr_el2", ICH_MISR_EL2, {}}, 757288943Sdim {"ich_vmcr_el2", ICH_VMCR_EL2, {}}, 758288943Sdim {"ich_vseir_el2", ICH_VSEIR_EL2, {}}, 759288943Sdim {"ich_lr0_el2", ICH_LR0_EL2, {}}, 760288943Sdim {"ich_lr1_el2", ICH_LR1_EL2, {}}, 761288943Sdim {"ich_lr2_el2", ICH_LR2_EL2, {}}, 762288943Sdim {"ich_lr3_el2", ICH_LR3_EL2, {}}, 763288943Sdim {"ich_lr4_el2", ICH_LR4_EL2, {}}, 764288943Sdim {"ich_lr5_el2", ICH_LR5_EL2, {}}, 765288943Sdim {"ich_lr6_el2", ICH_LR6_EL2, {}}, 766288943Sdim {"ich_lr7_el2", ICH_LR7_EL2, {}}, 767288943Sdim {"ich_lr8_el2", ICH_LR8_EL2, {}}, 768288943Sdim {"ich_lr9_el2", ICH_LR9_EL2, {}}, 769288943Sdim {"ich_lr10_el2", ICH_LR10_EL2, {}}, 770288943Sdim {"ich_lr11_el2", ICH_LR11_EL2, {}}, 771288943Sdim {"ich_lr12_el2", ICH_LR12_EL2, {}}, 772288943Sdim {"ich_lr13_el2", ICH_LR13_EL2, {}}, 773288943Sdim {"ich_lr14_el2", ICH_LR14_EL2, {}}, 774288943Sdim {"ich_lr15_el2", ICH_LR15_EL2, {}}, 775249259Sdim 776288943Sdim // Cyclone registers 777288943Sdim {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3, {AArch64::ProcCyclone}}, 778288943Sdim 779288943Sdim // v8.1a "Privileged Access Never" extension-specific system registers 780288943Sdim {"pan", PAN, {AArch64::HasV8_1aOps}}, 781288943Sdim 782288943Sdim // v8.1a "Limited Ordering Regions" extension-specific system registers 783288943Sdim {"lorsa_el1", LORSA_EL1, {AArch64::HasV8_1aOps}}, 784288943Sdim {"lorea_el1", LOREA_EL1, {AArch64::HasV8_1aOps}}, 785288943Sdim {"lorn_el1", LORN_EL1, {AArch64::HasV8_1aOps}}, 786288943Sdim {"lorc_el1", LORC_EL1, {AArch64::HasV8_1aOps}}, 787288943Sdim 788288943Sdim // v8.1a "Virtualization host extensions" system registers 789288943Sdim {"ttbr1_el2", TTBR1_EL2, {AArch64::HasV8_1aOps}}, 790288943Sdim {"contextidr_el2", CONTEXTIDR_EL2, {AArch64::HasV8_1aOps}}, 791288943Sdim {"cnthv_tval_el2", CNTHV_TVAL_EL2, {AArch64::HasV8_1aOps}}, 792288943Sdim {"cnthv_cval_el2", CNTHV_CVAL_EL2, {AArch64::HasV8_1aOps}}, 793288943Sdim {"cnthv_ctl_el2", CNTHV_CTL_EL2, {AArch64::HasV8_1aOps}}, 794288943Sdim {"sctlr_el12", SCTLR_EL12, {AArch64::HasV8_1aOps}}, 795288943Sdim {"cpacr_el12", CPACR_EL12, {AArch64::HasV8_1aOps}}, 796288943Sdim {"ttbr0_el12", TTBR0_EL12, {AArch64::HasV8_1aOps}}, 797288943Sdim {"ttbr1_el12", TTBR1_EL12, {AArch64::HasV8_1aOps}}, 798288943Sdim {"tcr_el12", TCR_EL12, {AArch64::HasV8_1aOps}}, 799288943Sdim {"afsr0_el12", AFSR0_EL12, {AArch64::HasV8_1aOps}}, 800288943Sdim {"afsr1_el12", AFSR1_EL12, {AArch64::HasV8_1aOps}}, 801288943Sdim {"esr_el12", ESR_EL12, {AArch64::HasV8_1aOps}}, 802288943Sdim {"far_el12", FAR_EL12, {AArch64::HasV8_1aOps}}, 803288943Sdim {"mair_el12", MAIR_EL12, {AArch64::HasV8_1aOps}}, 804288943Sdim {"amair_el12", AMAIR_EL12, {AArch64::HasV8_1aOps}}, 805288943Sdim {"vbar_el12", VBAR_EL12, {AArch64::HasV8_1aOps}}, 806288943Sdim {"contextidr_el12", CONTEXTIDR_EL12, {AArch64::HasV8_1aOps}}, 807288943Sdim {"cntkctl_el12", CNTKCTL_EL12, {AArch64::HasV8_1aOps}}, 808288943Sdim {"cntp_tval_el02", CNTP_TVAL_EL02, {AArch64::HasV8_1aOps}}, 809288943Sdim {"cntp_ctl_el02", CNTP_CTL_EL02, {AArch64::HasV8_1aOps}}, 810288943Sdim {"cntp_cval_el02", CNTP_CVAL_EL02, {AArch64::HasV8_1aOps}}, 811288943Sdim {"cntv_tval_el02", CNTV_TVAL_EL02, {AArch64::HasV8_1aOps}}, 812288943Sdim {"cntv_ctl_el02", CNTV_CTL_EL02, {AArch64::HasV8_1aOps}}, 813288943Sdim {"cntv_cval_el02", CNTV_CVAL_EL02, {AArch64::HasV8_1aOps}}, 814288943Sdim {"spsr_el12", SPSR_EL12, {AArch64::HasV8_1aOps}}, 815288943Sdim {"elr_el12", ELR_EL12, {AArch64::HasV8_1aOps}}, 816296417Sdim 817296417Sdim // v8.2a registers 818296417Sdim {"uao", UAO, {AArch64::HasV8_2aOps}}, 819296417Sdim 820296417Sdim // v8.2a "Statistical Profiling extension" registers 821296417Sdim {"pmblimitr_el1", PMBLIMITR_EL1, {AArch64::FeatureSPE}}, 822296417Sdim {"pmbptr_el1", PMBPTR_EL1, {AArch64::FeatureSPE}}, 823296417Sdim {"pmbsr_el1", PMBSR_EL1, {AArch64::FeatureSPE}}, 824296417Sdim {"pmbidr_el1", PMBIDR_EL1, {AArch64::FeatureSPE}}, 825296417Sdim {"pmscr_el2", PMSCR_EL2, {AArch64::FeatureSPE}}, 826296417Sdim {"pmscr_el12", PMSCR_EL12, {AArch64::FeatureSPE}}, 827296417Sdim {"pmscr_el1", PMSCR_EL1, {AArch64::FeatureSPE}}, 828296417Sdim {"pmsicr_el1", PMSICR_EL1, {AArch64::FeatureSPE}}, 829296417Sdim {"pmsirr_el1", PMSIRR_EL1, {AArch64::FeatureSPE}}, 830296417Sdim {"pmsfcr_el1", PMSFCR_EL1, {AArch64::FeatureSPE}}, 831296417Sdim {"pmsevfr_el1", PMSEVFR_EL1, {AArch64::FeatureSPE}}, 832296417Sdim {"pmslatfr_el1", PMSLATFR_EL1, {AArch64::FeatureSPE}}, 833296417Sdim {"pmsidr_el1", PMSIDR_EL1, {AArch64::FeatureSPE}}, 834276479Sdim}; 835276479Sdim 836249259Sdimuint32_t 837296417SdimAArch64SysReg::SysRegMapper::fromString(StringRef Name, 838288943Sdim const FeatureBitset& FeatureBits, bool &Valid) const { 839276479Sdim std::string NameLower = Name.lower(); 840276479Sdim 841249259Sdim // First search the registers shared by all 842288943Sdim for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) { 843288943Sdim if (SysRegMappings[i].isNameEqual(NameLower, FeatureBits)) { 844249259Sdim Valid = true; 845288943Sdim return SysRegMappings[i].Value; 846249259Sdim } 847249259Sdim } 848249259Sdim 849249259Sdim // Now try the instruction-specific registers (either read-only or 850249259Sdim // write-only). 851288943Sdim for (unsigned i = 0; i < NumInstMappings; ++i) { 852288943Sdim if (InstMappings[i].isNameEqual(NameLower, FeatureBits)) { 853249259Sdim Valid = true; 854288943Sdim return InstMappings[i].Value; 855249259Sdim } 856249259Sdim } 857249259Sdim 858280031Sdim // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name 859280031Sdim Regex GenericRegPattern("^s([0-3])_([0-7])_c([0-9]|1[0-5])_c([0-9]|1[0-5])_([0-7])$"); 860249259Sdim 861280031Sdim SmallVector<StringRef, 5> Ops; 862249259Sdim if (!GenericRegPattern.match(NameLower, &Ops)) { 863249259Sdim Valid = false; 864249259Sdim return -1; 865249259Sdim } 866249259Sdim 867280031Sdim uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; 868249259Sdim uint32_t Bits; 869280031Sdim Ops[1].getAsInteger(10, Op0); 870280031Sdim Ops[2].getAsInteger(10, Op1); 871280031Sdim Ops[3].getAsInteger(10, CRn); 872280031Sdim Ops[4].getAsInteger(10, CRm); 873280031Sdim Ops[5].getAsInteger(10, Op2); 874249259Sdim Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 875249259Sdim 876249259Sdim Valid = true; 877249259Sdim return Bits; 878249259Sdim} 879249259Sdim 880249259Sdimstd::string 881296417SdimAArch64SysReg::SysRegMapper::toString(uint32_t Bits, 882288943Sdim const FeatureBitset& FeatureBits) const { 883276479Sdim // First search the registers shared by all 884288943Sdim for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) { 885288943Sdim if (SysRegMappings[i].isValueEqual(Bits, FeatureBits)) { 886288943Sdim return SysRegMappings[i].Name; 887249259Sdim } 888249259Sdim } 889249259Sdim 890276479Sdim // Now try the instruction-specific registers (either read-only or 891276479Sdim // write-only). 892288943Sdim for (unsigned i = 0; i < NumInstMappings; ++i) { 893288943Sdim if (InstMappings[i].isValueEqual(Bits, FeatureBits)) { 894288943Sdim return InstMappings[i].Name; 895249259Sdim } 896249259Sdim } 897249259Sdim 898280031Sdim assert(Bits < 0x10000); 899249259Sdim uint32_t Op0 = (Bits >> 14) & 0x3; 900249259Sdim uint32_t Op1 = (Bits >> 11) & 0x7; 901249259Sdim uint32_t CRn = (Bits >> 7) & 0xf; 902249259Sdim uint32_t CRm = (Bits >> 3) & 0xf; 903249259Sdim uint32_t Op2 = Bits & 0x7; 904249259Sdim 905280031Sdim return "s" + utostr(Op0)+ "_" + utostr(Op1) + "_c" + utostr(CRn) 906249259Sdim + "_c" + utostr(CRm) + "_" + utostr(Op2); 907249259Sdim} 908249259Sdim 909288943Sdimconst AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIMappings[] = { 910288943Sdim {"ipas2e1is", IPAS2E1IS, {}}, 911288943Sdim {"ipas2le1is", IPAS2LE1IS, {}}, 912288943Sdim {"vmalle1is", VMALLE1IS, {}}, 913288943Sdim {"alle2is", ALLE2IS, {}}, 914288943Sdim {"alle3is", ALLE3IS, {}}, 915288943Sdim {"vae1is", VAE1IS, {}}, 916288943Sdim {"vae2is", VAE2IS, {}}, 917288943Sdim {"vae3is", VAE3IS, {}}, 918288943Sdim {"aside1is", ASIDE1IS, {}}, 919288943Sdim {"vaae1is", VAAE1IS, {}}, 920288943Sdim {"alle1is", ALLE1IS, {}}, 921288943Sdim {"vale1is", VALE1IS, {}}, 922288943Sdim {"vale2is", VALE2IS, {}}, 923288943Sdim {"vale3is", VALE3IS, {}}, 924288943Sdim {"vmalls12e1is", VMALLS12E1IS, {}}, 925288943Sdim {"vaale1is", VAALE1IS, {}}, 926288943Sdim {"ipas2e1", IPAS2E1, {}}, 927288943Sdim {"ipas2le1", IPAS2LE1, {}}, 928288943Sdim {"vmalle1", VMALLE1, {}}, 929288943Sdim {"alle2", ALLE2, {}}, 930288943Sdim {"alle3", ALLE3, {}}, 931288943Sdim {"vae1", VAE1, {}}, 932288943Sdim {"vae2", VAE2, {}}, 933288943Sdim {"vae3", VAE3, {}}, 934288943Sdim {"aside1", ASIDE1, {}}, 935288943Sdim {"vaae1", VAAE1, {}}, 936288943Sdim {"alle1", ALLE1, {}}, 937288943Sdim {"vale1", VALE1, {}}, 938288943Sdim {"vale2", VALE2, {}}, 939288943Sdim {"vale3", VALE3, {}}, 940288943Sdim {"vmalls12e1", VMALLS12E1, {}}, 941288943Sdim {"vaale1", VAALE1, {}} 942249259Sdim}; 943249259Sdim 944276479SdimAArch64TLBI::TLBIMapper::TLBIMapper() 945288943Sdim : AArch64NamedImmMapper(TLBIMappings, 0) {} 946