AArch64Subtarget.cpp revision 296417 
1//===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the AArch64 specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AArch64InstrInfo.h"
15#include "AArch64PBQPRegAlloc.h"
16#include "AArch64Subtarget.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/CodeGen/MachineScheduler.h"
19#include "llvm/IR/GlobalValue.h"
20#include "llvm/Support/TargetRegistry.h"
21
22using namespace llvm;
23
24#define DEBUG_TYPE "aarch64-subtarget"
25
26#define GET_SUBTARGETINFO_CTOR
27#define GET_SUBTARGETINFO_TARGET_DESC
28#include "AArch64GenSubtargetInfo.inc"
29
30static cl::opt<bool>
31EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
32                     "converter pass"), cl::init(true), cl::Hidden);
33
34// If OS supports TBI, use this flag to enable it.
35static cl::opt<bool>
36UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
37                         "an address is ignored"), cl::init(false), cl::Hidden);
38
39AArch64Subtarget &
40AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
41  // Determine default and user-specified characteristics
42
43  if (CPUString.empty())
44    CPUString = "generic";
45
46  ParseSubtargetFeatures(CPUString, FS);
47  return *this;
48}
49
50AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
51                                   const std::string &FS,
52                                   const TargetMachine &TM, bool LittleEndian)
53    : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
54      HasV8_1aOps(false), HasV8_2aOps(false), HasFPARMv8(false), HasNEON(false),
55      HasCrypto(false), HasCRC(false), HasPerfMon(false), HasFullFP16(false),
56      HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
57      StrictAlign(false), ReserveX18(TT.isOSDarwin()), IsLittle(LittleEndian),
58      CPUString(CPU), TargetTriple(TT), FrameLowering(),
59      InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
60      TLInfo(TM, *this) {}
61
62/// ClassifyGlobalReference - Find the target operand flags that describe
63/// how a global value should be referenced for the current subtarget.
64unsigned char
65AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
66                                        const TargetMachine &TM) const {
67  bool isDef = GV->isStrongDefinitionForLinker();
68
69  // MachO large model always goes via a GOT, simply to get a single 8-byte
70  // absolute relocation on all global addresses.
71  if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
72    return AArch64II::MO_GOT;
73
74  // The small code mode's direct accesses use ADRP, which cannot necessarily
75  // produce the value 0 (if the code is above 4GB).
76  if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage()) {
77    // In PIC mode use the GOT, but in absolute mode use a constant pool load.
78    if (TM.getRelocationModel() == Reloc::Static)
79        return AArch64II::MO_CONSTPOOL;
80    else
81        return AArch64II::MO_GOT;
82  }
83
84  // If symbol visibility is hidden, the extra load is not needed if
85  // the symbol is definitely defined in the current translation unit.
86
87  // The handling of non-hidden symbols in PIC mode is rather target-dependent:
88  //   + On MachO, if the symbol is defined in this module the GOT can be
89  //     skipped.
90  //   + On ELF, the R_AARCH64_COPY relocation means that even symbols actually
91  //     defined could end up in unexpected places. Use a GOT.
92  if (TM.getRelocationModel() != Reloc::Static && GV->hasDefaultVisibility()) {
93    if (isTargetMachO())
94      return isDef ? AArch64II::MO_NO_FLAG : AArch64II::MO_GOT;
95    else
96      // No need to go through the GOT for local symbols on ELF.
97      return GV->hasLocalLinkage() ? AArch64II::MO_NO_FLAG : AArch64II::MO_GOT;
98  }
99
100  return AArch64II::MO_NO_FLAG;
101}
102
103/// This function returns the name of a function which has an interface
104/// like the non-standard bzero function, if such a function exists on
105/// the current subtarget and it is considered prefereable over
106/// memset with zero passed as the second argument. Otherwise it
107/// returns null.
108const char *AArch64Subtarget::getBZeroEntry() const {
109  // Prefer bzero on Darwin only.
110  if(isTargetDarwin())
111    return "bzero";
112
113  return nullptr;
114}
115
116void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
117                                         MachineInstr *begin, MachineInstr *end,
118                                         unsigned NumRegionInstrs) const {
119  // LNT run (at least on Cyclone) showed reasonably significant gains for
120  // bi-directional scheduling. 253.perlbmk.
121  Policy.OnlyTopDown = false;
122  Policy.OnlyBottomUp = false;
123  // Enabling or Disabling the latency heuristic is a close call: It seems to
124  // help nearly no benchmark on out-of-order architectures, on the other hand
125  // it regresses register pressure on a few benchmarking.
126  if (isCyclone())
127    Policy.DisableLatencyHeuristic = true;
128}
129
130bool AArch64Subtarget::enableEarlyIfConversion() const {
131  return EnableEarlyIfConvert;
132}
133
134bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
135  if (!UseAddressTopByteIgnored)
136    return false;
137
138  if (TargetTriple.isiOS()) {
139    unsigned Major, Minor, Micro;
140    TargetTriple.getiOSVersion(Major, Minor, Micro);
141    return Major >= 8;
142  }
143
144  return false;
145}
146
147std::unique_ptr<PBQPRAConstraint>
148AArch64Subtarget::getCustomPBQPConstraints() const {
149  if (!isCortexA57())
150    return nullptr;
151
152  return llvm::make_unique<A57ChainingConstraint>();
153}
154