AArch64RegisterInfo.h revision 280031
1276479Sdim//==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
2249259Sdim//
3249259Sdim//                     The LLVM Compiler Infrastructure
4249259Sdim//
5249259Sdim// This file is distributed under the University of Illinois Open Source
6249259Sdim// License. See LICENSE.TXT for details.
7249259Sdim//
8249259Sdim//===----------------------------------------------------------------------===//
9249259Sdim//
10276479Sdim// This file contains the AArch64 implementation of the MRegisterInfo class.
11249259Sdim//
12249259Sdim//===----------------------------------------------------------------------===//
13249259Sdim
14280031Sdim#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
15280031Sdim#define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
16249259Sdim
17249259Sdim#define GET_REGINFO_HEADER
18249259Sdim#include "AArch64GenRegisterInfo.inc"
19249259Sdim
20249259Sdimnamespace llvm {
21249259Sdim
22249259Sdimclass AArch64InstrInfo;
23249259Sdimclass AArch64Subtarget;
24276479Sdimclass MachineFunction;
25276479Sdimclass RegScavenger;
26276479Sdimclass TargetRegisterClass;
27249259Sdim
28249259Sdimstruct AArch64RegisterInfo : public AArch64GenRegisterInfo {
29276479Sdimprivate:
30276479Sdim  const AArch64InstrInfo *TII;
31276479Sdim  const AArch64Subtarget *STI;
32249259Sdim
33276479Sdimpublic:
34276479Sdim  AArch64RegisterInfo(const AArch64InstrInfo *tii, const AArch64Subtarget *sti);
35249259Sdim
36276479Sdim  bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
37249259Sdim
38276479Sdim  /// Code Generation virtual methods...
39276479Sdim  const MCPhysReg *
40276479Sdim  getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
41276479Sdim  const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
42249259Sdim
43276479Sdim  unsigned getCSRFirstUseCost() const override {
44276479Sdim    // The cost will be compared against BlockFrequency where entry has the
45276479Sdim    // value of 1 << 14. A value of 5 will choose to spill or split really
46276479Sdim    // cold path instead of using a callee-saved register.
47276479Sdim    return 5;
48276479Sdim  }
49249259Sdim
50276479Sdim  // Calls involved in thread-local variable lookup save more registers than
51276479Sdim  // normal calls, so they need a different mask to represent this.
52276479Sdim  const uint32_t *getTLSCallPreservedMask() const;
53276479Sdim
54276479Sdim  /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
55276479Sdim  /// case that 'returned' is on an i64 first argument if the calling convention
56276479Sdim  /// is one that can (partially) model this attribute with a preserved mask
57276479Sdim  /// (i.e. it is a calling convention that uses the same register for the first
58276479Sdim  /// i64 argument and an i64 return value)
59276479Sdim  ///
60276479Sdim  /// Should return NULL in the case that the calling convention does not have
61276479Sdim  /// this property
62276479Sdim  const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
63276479Sdim
64276479Sdim  BitVector getReservedRegs(const MachineFunction &MF) const override;
65249259Sdim  const TargetRegisterClass *
66276479Sdim  getPointerRegClass(const MachineFunction &MF,
67276479Sdim                     unsigned Kind = 0) const override;
68276479Sdim  const TargetRegisterClass *
69276479Sdim  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
70249259Sdim
71276479Sdim  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
72276479Sdim  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
73276479Sdim  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
74249259Sdim
75276479Sdim  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
76276479Sdim  bool isFrameOffsetLegal(const MachineInstr *MI,
77276479Sdim                          int64_t Offset) const override;
78276479Sdim  void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
79276479Sdim                                    int FrameIdx,
80276479Sdim                                    int64_t Offset) const override;
81276479Sdim  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
82276479Sdim                         int64_t Offset) const override;
83276479Sdim  void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
84276479Sdim                           unsigned FIOperandNum,
85276479Sdim                           RegScavenger *RS = nullptr) const override;
86276479Sdim  bool cannotEliminateFrame(const MachineFunction &MF) const;
87249259Sdim
88276479Sdim  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
89276479Sdim  bool hasBasePointer(const MachineFunction &MF) const;
90276479Sdim  unsigned getBaseRegister() const;
91249259Sdim
92276479Sdim  // Debug information queries.
93276479Sdim  unsigned getFrameRegister(const MachineFunction &MF) const override;
94249259Sdim
95276479Sdim  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
96276479Sdim                               MachineFunction &MF) const override;
97249259Sdim};
98249259Sdim
99249259Sdim} // end namespace llvm
100249259Sdim
101280031Sdim#endif
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