TargetParser.cpp revision 283625 
1//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements a target parser to recognise hardware features such as
11// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
12//
13//===----------------------------------------------------------------------===//
14
15#include "llvm/Support/ARMBuildAttributes.h"
16#include "llvm/Support/TargetParser.h"
17#include "llvm/ADT/StringExtras.h"
18#include "llvm/ADT/StringSwitch.h"
19#include <cctype>
20
21using namespace llvm;
22
23namespace {
24
25// List of canonical FPU names (use getFPUSynonym)
26// FIXME: TableGen this.
27struct {
28  const char * Name;
29  ARM::FPUKind ID;
30} FPUNames[] = {
31  { "invalid",              ARM::FK_INVALID },
32  { "vfp",                  ARM::FK_VFP },
33  { "vfpv2",                ARM::FK_VFPV2 },
34  { "vfpv3",                ARM::FK_VFPV3 },
35  { "vfpv3-d16",            ARM::FK_VFPV3_D16 },
36  { "vfpv4",                ARM::FK_VFPV4 },
37  { "vfpv4-d16",            ARM::FK_VFPV4_D16 },
38  { "fpv5-d16",             ARM::FK_FPV5_D16 },
39  { "fp-armv8",             ARM::FK_FP_ARMV8 },
40  { "neon",                 ARM::FK_NEON },
41  { "neon-vfpv4",           ARM::FK_NEON_VFPV4 },
42  { "neon-fp-armv8",        ARM::FK_NEON_FP_ARMV8 },
43  { "crypto-neon-fp-armv8", ARM::FK_CRYPTO_NEON_FP_ARMV8 },
44  { "softvfp",              ARM::FK_SOFTVFP }
45};
46// List of canonical arch names (use getArchSynonym)
47// FIXME: TableGen this.
48struct {
49  const char *Name;
50  ARM::ArchKind ID;
51  const char *DefaultCPU;
52  ARMBuildAttrs::CPUArch DefaultArch;
53} ARCHNames[] = {
54  { "invalid",   ARM::AK_INVALID,  nullptr,   ARMBuildAttrs::CPUArch::Pre_v4 },
55  { "armv2",     ARM::AK_ARMV2,    "2",       ARMBuildAttrs::CPUArch::v4 },
56  { "armv2a",    ARM::AK_ARMV2A,   "2A",      ARMBuildAttrs::CPUArch::v4 },
57  { "armv3",     ARM::AK_ARMV3,    "3",       ARMBuildAttrs::CPUArch::v4 },
58  { "armv3m",    ARM::AK_ARMV3M,   "3M",      ARMBuildAttrs::CPUArch::v4 },
59  { "armv4",     ARM::AK_ARMV4,    "4",       ARMBuildAttrs::CPUArch::v4 },
60  { "armv4t",    ARM::AK_ARMV4T,   "4T",      ARMBuildAttrs::CPUArch::v4T },
61  { "armv5",     ARM::AK_ARMV5,    "5",       ARMBuildAttrs::CPUArch::v5T },
62  { "armv5t",    ARM::AK_ARMV5T,   "5T",      ARMBuildAttrs::CPUArch::v5T },
63  { "armv5te",   ARM::AK_ARMV5TE,  "5TE",     ARMBuildAttrs::CPUArch::v5TE },
64  { "armv6",     ARM::AK_ARMV6,    "6",       ARMBuildAttrs::CPUArch::v6 },
65  { "armv6j",    ARM::AK_ARMV6J,   "6J",      ARMBuildAttrs::CPUArch::v6 },
66  { "armv6k",    ARM::AK_ARMV6K,   "6K",      ARMBuildAttrs::CPUArch::v6K },
67  { "armv6t2",   ARM::AK_ARMV6T2,  "6T2",     ARMBuildAttrs::CPUArch::v6T2 },
68  { "armv6z",    ARM::AK_ARMV6Z,   "6Z",      ARMBuildAttrs::CPUArch::v6KZ },
69  { "armv6zk",   ARM::AK_ARMV6ZK,  "6ZK",     ARMBuildAttrs::CPUArch::v6KZ },
70  { "armv6-m",   ARM::AK_ARMV6M,   "6-M",     ARMBuildAttrs::CPUArch::v6_M },
71  { "armv7",     ARM::AK_ARMV7,    "7",       ARMBuildAttrs::CPUArch::v7 },
72  { "armv7-a",   ARM::AK_ARMV7A,   "7-A",     ARMBuildAttrs::CPUArch::v7 },
73  { "armv7-r",   ARM::AK_ARMV7R,   "7-R",     ARMBuildAttrs::CPUArch::v7 },
74  { "armv7-m",   ARM::AK_ARMV7M,   "7-M",     ARMBuildAttrs::CPUArch::v7 },
75  { "armv8-a",   ARM::AK_ARMV8A,   "8-A",     ARMBuildAttrs::CPUArch::v8 },
76  { "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A",   ARMBuildAttrs::CPUArch::v8 },
77  // Non-standard Arch names.
78  { "iwmmxt",    ARM::AK_IWMMXT,   "iwmmxt",  ARMBuildAttrs::CPUArch::v5TE },
79  { "iwmmxt2",   ARM::AK_IWMMXT2,  "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE },
80  { "xscale",    ARM::AK_XSCALE,   "xscale",  ARMBuildAttrs::CPUArch::v5TE },
81  { "armv5e",    ARM::AK_ARMV5E,   "5E",      ARMBuildAttrs::CPUArch::v5TE },
82  { "armv5tej",  ARM::AK_ARMV5TEJ, "5TE",     ARMBuildAttrs::CPUArch::v5TE },
83  { "armv6sm",   ARM::AK_ARMV6SM,  "6-M",     ARMBuildAttrs::CPUArch::v6_M },
84  { "armv6hl",   ARM::AK_ARMV6HL,  "6-M",     ARMBuildAttrs::CPUArch::v6_M },
85  { "armv7e-m",  ARM::AK_ARMV7EM,  "7E-M",    ARMBuildAttrs::CPUArch::v7E_M },
86  { "armv7l",    ARM::AK_ARMV7L,   "7-L",     ARMBuildAttrs::CPUArch::v7 },
87  { "armv7hl",   ARM::AK_ARMV7HL,  "7H-L",    ARMBuildAttrs::CPUArch::v7 },
88  { "armv7s",    ARM::AK_ARMV7S,   "7-S",     ARMBuildAttrs::CPUArch::v7 }
89};
90// List of canonical ARCH names (use getARCHSynonym)
91// FIXME: TableGen this.
92struct {
93  const char *Name;
94  ARM::ArchExtKind ID;
95} ARCHExtNames[] = {
96  { "invalid",  ARM::AEK_INVALID },
97  { "crc",      ARM::AEK_CRC },
98  { "crypto",   ARM::AEK_CRYPTO },
99  { "fp",       ARM::AEK_FP },
100  { "idiv",     ARM::AEK_HWDIV },
101  { "mp",       ARM::AEK_MP },
102  { "sec",      ARM::AEK_SEC },
103  { "virt",     ARM::AEK_VIRT }
104};
105// List of CPU names and their arches.
106// The same CPU can have multiple arches and can be default on multiple arches.
107// When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
108// FIXME: TableGen this.
109struct {
110  const char *Name;
111  ARM::ArchKind ArchID;
112  bool Default;
113} CPUNames[] = {
114  { "arm2",          ARM::AK_ARMV2,    true },
115  { "arm6",          ARM::AK_ARMV3,    true },
116  { "arm7m",         ARM::AK_ARMV3M,   true },
117  { "strongarm",     ARM::AK_ARMV4,    true },
118  { "arm7tdmi",      ARM::AK_ARMV4T,   true },
119  { "arm7tdmi-s",    ARM::AK_ARMV4T,   false },
120  { "arm710t",       ARM::AK_ARMV4T,   false },
121  { "arm720t",       ARM::AK_ARMV4T,   false },
122  { "arm9",          ARM::AK_ARMV4T,   false },
123  { "arm9tdmi",      ARM::AK_ARMV4T,   false },
124  { "arm920",        ARM::AK_ARMV4T,   false },
125  { "arm920t",       ARM::AK_ARMV4T,   false },
126  { "arm922t",       ARM::AK_ARMV4T,   false },
127  { "arm9312",       ARM::AK_ARMV4T,   false },
128  { "arm940t",       ARM::AK_ARMV4T,   false },
129  { "ep9312",        ARM::AK_ARMV4T,   false },
130  { "arm10tdmi",     ARM::AK_ARMV5,    true },
131  { "arm10tdmi",     ARM::AK_ARMV5T,   true },
132  { "arm1020t",      ARM::AK_ARMV5T,   false },
133  { "xscale",        ARM::AK_XSCALE,   true },
134  { "xscale",        ARM::AK_ARMV5TE,  false },
135  { "arm9e",         ARM::AK_ARMV5TE,  false },
136  { "arm926ej-s",    ARM::AK_ARMV5TE,  false },
137  { "arm946ej-s",    ARM::AK_ARMV5TE,  false },
138  { "arm966e-s",     ARM::AK_ARMV5TE,  false },
139  { "arm968e-s",     ARM::AK_ARMV5TE,  false },
140  { "arm1020e",      ARM::AK_ARMV5TE,  false },
141  { "arm1022e",      ARM::AK_ARMV5TE,  true },
142  { "iwmmxt",        ARM::AK_ARMV5TE,  false },
143  { "iwmmxt",        ARM::AK_IWMMXT,   true },
144  { "arm1136jf-s",   ARM::AK_ARMV6,    true },
145  { "arm1136j-s",    ARM::AK_ARMV6J,   true },
146  { "arm1136jz-s",   ARM::AK_ARMV6J,   false },
147  { "arm1176j-s",    ARM::AK_ARMV6K,   false },
148  { "mpcore",        ARM::AK_ARMV6K,   false },
149  { "mpcorenovfp",   ARM::AK_ARMV6K,   false },
150  { "arm1176jzf-s",  ARM::AK_ARMV6K,   true },
151  { "arm1176jzf-s",  ARM::AK_ARMV6Z,   true },
152  { "arm1176jzf-s",  ARM::AK_ARMV6ZK,  true },
153  { "arm1156t2-s",   ARM::AK_ARMV6T2,  true },
154  { "arm1156t2f-s",  ARM::AK_ARMV6T2,  false },
155  { "cortex-m0",     ARM::AK_ARMV6M,   true },
156  { "cortex-m0plus", ARM::AK_ARMV6M,   false },
157  { "cortex-m1",     ARM::AK_ARMV6M,   false },
158  { "sc000",         ARM::AK_ARMV6M,   false },
159  { "cortex-a8",     ARM::AK_ARMV7,    true },
160  { "cortex-a5",     ARM::AK_ARMV7A,   false },
161  { "cortex-a7",     ARM::AK_ARMV7A,   false },
162  { "cortex-a8",     ARM::AK_ARMV7A,   true },
163  { "cortex-a9",     ARM::AK_ARMV7A,   false },
164  { "cortex-a12",    ARM::AK_ARMV7A,   false },
165  { "cortex-a15",    ARM::AK_ARMV7A,   false },
166  { "cortex-a17",    ARM::AK_ARMV7A,   false },
167  { "krait",         ARM::AK_ARMV7A,   false },
168  { "cortex-r4",     ARM::AK_ARMV7R,   true },
169  { "cortex-r4f",    ARM::AK_ARMV7R,   false },
170  { "cortex-r5",     ARM::AK_ARMV7R,   false },
171  { "cortex-r7",     ARM::AK_ARMV7R,   false },
172  { "sc300",         ARM::AK_ARMV7M,   false },
173  { "cortex-m3",     ARM::AK_ARMV7M,   true },
174  { "cortex-m4",     ARM::AK_ARMV7M,   false },
175  { "cortex-m7",     ARM::AK_ARMV7M,   false },
176  { "cortex-a53",    ARM::AK_ARMV8A,   true },
177  { "cortex-a57",    ARM::AK_ARMV8A,   false },
178  { "cortex-a72",    ARM::AK_ARMV8A,   false },
179  { "cyclone",       ARM::AK_ARMV8A,   false },
180  { "generic",       ARM::AK_ARMV8_1A, true },
181  // Non-standard Arch names.
182  { "arm1022e",      ARM::AK_ARMV5E,   true },
183  { "arm926ej-s",    ARM::AK_ARMV5TEJ, true },
184  { "cortex-m0",     ARM::AK_ARMV6SM,  true },
185  { "arm1176jzf-s",  ARM::AK_ARMV6HL,  true },
186  { "cortex-a8",     ARM::AK_ARMV7L,   true },
187  { "cortex-a8",     ARM::AK_ARMV7HL,  true },
188  { "cortex-m4",     ARM::AK_ARMV7EM,  true },
189  { "swift",         ARM::AK_ARMV7S,   true },
190  // Invalid CPU
191  { "invalid",       ARM::AK_INVALID,  true }
192};
193
194} // namespace
195
196namespace llvm {
197
198// ======================================================= //
199// Information by ID
200// ======================================================= //
201
202const char *ARMTargetParser::getFPUName(unsigned FPUKind) {
203  if (FPUKind >= ARM::FK_LAST)
204    return nullptr;
205  return FPUNames[FPUKind].Name;
206}
207
208const char *ARMTargetParser::getArchName(unsigned ArchKind) {
209  if (ArchKind >= ARM::AK_LAST)
210    return nullptr;
211  return ARCHNames[ArchKind].Name;
212}
213
214const char *ARMTargetParser::getArchDefaultCPUName(unsigned ArchKind) {
215  if (ArchKind >= ARM::AK_LAST)
216    return nullptr;
217  return ARCHNames[ArchKind].DefaultCPU;
218}
219
220unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ArchKind) {
221  if (ArchKind >= ARM::AK_LAST)
222    return ARMBuildAttrs::CPUArch::Pre_v4;
223  return ARCHNames[ArchKind].DefaultArch;
224}
225
226const char *ARMTargetParser::getArchExtName(unsigned ArchExtKind) {
227  if (ArchExtKind >= ARM::AEK_LAST)
228    return nullptr;
229  return ARCHExtNames[ArchExtKind].Name;
230}
231
232const char *ARMTargetParser::getDefaultCPU(StringRef Arch) {
233  unsigned AK = parseArch(Arch);
234  if (AK == ARM::AK_INVALID)
235    return nullptr;
236
237  // Look for multiple AKs to find the default for pair AK+Name.
238  for (const auto CPU : CPUNames) {
239    if (CPU.ArchID == AK && CPU.Default)
240      return CPU.Name;
241  }
242  return nullptr;
243}
244
245// ======================================================= //
246// Parsers
247// ======================================================= //
248
249StringRef ARMTargetParser::getFPUSynonym(StringRef FPU) {
250  return StringSwitch<StringRef>(FPU)
251    .Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
252    .Case("vfp2", "vfpv2")
253    .Case("vfp3", "vfpv3")
254    .Case("vfp4", "vfpv4")
255    .Case("vfp3-d16", "vfpv3-d16")
256    .Case("vfp4-d16", "vfpv4-d16")
257    // FIXME: sp-16 is NOT the same as d16
258    .Cases("fp4-sp-d16", "fpv4-sp-d16", "vfpv4-d16")
259    .Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
260    .Cases("fp5-sp-d16", "fpv5-sp-d16", "fpv5-d16")
261    .Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
262    // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
263    .Case("neon-vfpv3", "neon")
264    .Default(FPU);
265}
266
267StringRef ARMTargetParser::getArchSynonym(StringRef Arch) {
268  return StringSwitch<StringRef>(Arch)
269    .Cases("armv6m",   "v6m",   "armv6-m")
270    .Cases("armv7a",   "v7a",   "armv7-a")
271    .Cases("armv7r",   "v7r",   "armv7-r")
272    .Cases("armv7m",   "v7m",   "armv7-m")
273    .Cases("armv7em",  "v7em",  "armv7e-m")
274    .Cases("armv8",    "v8",    "armv8-a")
275    .Cases("armv8a",   "v8a",   "armv8-a")
276    .Cases("armv8.1a", "v8.1a", "armv8.1-a")
277    .Cases("aarch64",  "arm64", "armv8-a")
278    .Default(Arch);
279}
280
281// MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but
282// (iwmmxt|xscale)(eb)? is also permitted. If the former, return
283// "v.+", if the latter, return unmodified string, minus 'eb'.
284// If invalid, return empty string.
285StringRef ARMTargetParser::getCanonicalArchName(StringRef Arch) {
286  size_t offset = StringRef::npos;
287  StringRef A = Arch;
288  StringRef Error = "";
289
290  // Begins with "arm" / "thumb", move past it.
291  if (A.startswith("arm64"))
292    offset = 5;
293  else if (A.startswith("arm"))
294    offset = 3;
295  else if (A.startswith("thumb"))
296    offset = 5;
297  else if (A.startswith("aarch64")) {
298    offset = 7;
299    // AArch64 uses "_be", not "eb" suffix.
300    if (A.find("eb") != StringRef::npos)
301      return Error;
302    if (A.substr(offset,3) == "_be")
303      offset += 3;
304  }
305
306  // Ex. "armebv7", move past the "eb".
307  if (offset != StringRef::npos && A.substr(offset, 2) == "eb")
308    offset += 2;
309  // Or, if it ends with eb ("armv7eb"), chop it off.
310  else if (A.endswith("eb"))
311    A = A.substr(0, A.size() - 2);
312  // Trim the head
313  if (offset != StringRef::npos)
314    A = A.substr(offset);
315
316  // Empty string means offset reached the end, which means it's valid.
317  if (A.empty())
318    return Arch;
319
320  // Only match non-marketing names
321  if (offset != StringRef::npos) {
322  // Must start with 'vN'.
323    if (A[0] != 'v' || !std::isdigit(A[1]))
324      return Error;
325    // Can't have an extra 'eb'.
326    if (A.find("eb") != StringRef::npos)
327      return Error;
328  }
329
330  // Arch will either be a 'v' name (v7a) or a marketing name (xscale).
331  return A;
332}
333
334unsigned ARMTargetParser::parseFPU(StringRef FPU) {
335  StringRef Syn = getFPUSynonym(FPU);
336  for (const auto F : FPUNames) {
337    if (Syn == F.Name)
338      return F.ID;
339  }
340  return ARM::FK_INVALID;
341}
342
343// Allows partial match, ex. "v7a" matches "armv7a".
344unsigned ARMTargetParser::parseArch(StringRef Arch) {
345  StringRef Syn = getArchSynonym(Arch);
346  for (const auto A : ARCHNames) {
347    if (StringRef(A.Name).endswith(Syn))
348      return A.ID;
349  }
350  return ARM::AK_INVALID;
351}
352
353unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) {
354  for (const auto A : ARCHExtNames) {
355    if (ArchExt == A.Name)
356      return A.ID;
357  }
358  return ARM::AEK_INVALID;
359}
360
361unsigned ARMTargetParser::parseCPUArch(StringRef CPU) {
362  for (const auto C : CPUNames) {
363    if (CPU == C.Name)
364      return C.ArchID;
365  }
366  return ARM::AK_INVALID;
367}
368
369// ARM, Thumb, AArch64
370unsigned ARMTargetParser::parseArchISA(StringRef Arch) {
371  return StringSwitch<unsigned>(Arch)
372      .StartsWith("aarch64", ARM::IK_AARCH64)
373      .StartsWith("arm64",   ARM::IK_AARCH64)
374      .StartsWith("thumb",   ARM::IK_THUMB)
375      .StartsWith("arm",     ARM::IK_ARM)
376      .Default(ARM::EK_INVALID);
377}
378
379// Little/Big endian
380unsigned ARMTargetParser::parseArchEndian(StringRef Arch) {
381  if (Arch.startswith("armeb") ||
382      Arch.startswith("thumbeb") ||
383      Arch.startswith("aarch64_be"))
384    return ARM::EK_BIG;
385
386  if (Arch.startswith("arm") || Arch.startswith("thumb")) {
387    if (Arch.endswith("eb"))
388      return ARM::EK_BIG;
389    else
390      return ARM::EK_LITTLE;
391  }
392
393  if (Arch.startswith("aarch64"))
394    return ARM::EK_LITTLE;
395
396  return ARM::EK_INVALID;
397}
398
399// Profile A/R/M
400unsigned ARMTargetParser::parseArchProfile(StringRef Arch) {
401  Arch = getCanonicalArchName(Arch);
402  switch(parseArch(Arch)) {
403  case ARM::AK_ARMV6M:
404  case ARM::AK_ARMV7M:
405  case ARM::AK_ARMV6SM:
406  case ARM::AK_ARMV7EM:
407    return ARM::PK_M;
408  case ARM::AK_ARMV7R:
409    return ARM::PK_R;
410  case ARM::AK_ARMV7:
411  case ARM::AK_ARMV7A:
412  case ARM::AK_ARMV8A:
413  case ARM::AK_ARMV8_1A:
414    return ARM::PK_A;
415  }
416  return ARM::PK_INVALID;
417}
418
419// Version number (ex. v7 = 7).
420unsigned ARMTargetParser::parseArchVersion(StringRef Arch) {
421  Arch = getCanonicalArchName(Arch);
422  switch(parseArch(Arch)) {
423  case ARM::AK_ARMV2:
424  case ARM::AK_ARMV2A:
425    return 2;
426  case ARM::AK_ARMV3:
427  case ARM::AK_ARMV3M:
428    return 3;
429  case ARM::AK_ARMV4:
430  case ARM::AK_ARMV4T:
431    return 4;
432  case ARM::AK_ARMV5:
433  case ARM::AK_ARMV5T:
434  case ARM::AK_ARMV5TE:
435  case ARM::AK_IWMMXT:
436  case ARM::AK_IWMMXT2:
437  case ARM::AK_XSCALE:
438  case ARM::AK_ARMV5E:
439  case ARM::AK_ARMV5TEJ:
440    return 5;
441  case ARM::AK_ARMV6:
442  case ARM::AK_ARMV6J:
443  case ARM::AK_ARMV6K:
444  case ARM::AK_ARMV6T2:
445  case ARM::AK_ARMV6Z:
446  case ARM::AK_ARMV6ZK:
447  case ARM::AK_ARMV6M:
448  case ARM::AK_ARMV6SM:
449  case ARM::AK_ARMV6HL:
450    return 6;
451  case ARM::AK_ARMV7:
452  case ARM::AK_ARMV7A:
453  case ARM::AK_ARMV7R:
454  case ARM::AK_ARMV7M:
455  case ARM::AK_ARMV7L:
456  case ARM::AK_ARMV7HL:
457  case ARM::AK_ARMV7S:
458  case ARM::AK_ARMV7EM:
459    return 7;
460  case ARM::AK_ARMV8A:
461  case ARM::AK_ARMV8_1A:
462    return 8;
463  }
464  return 0;
465}
466
467} // namespace llvm
468