TargetLoweringBase.cpp revision 280031
1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLoweringBase class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/ADT/STLExtras.h" 17#include "llvm/ADT/Triple.h" 18#include "llvm/CodeGen/Analysis.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineJumpTableInfo.h" 23#include "llvm/CodeGen/StackMaps.h" 24#include "llvm/IR/DataLayout.h" 25#include "llvm/IR/DerivedTypes.h" 26#include "llvm/IR/GlobalVariable.h" 27#include "llvm/IR/Mangler.h" 28#include "llvm/MC/MCAsmInfo.h" 29#include "llvm/MC/MCContext.h" 30#include "llvm/MC/MCExpr.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Target/TargetLoweringObjectFile.h" 35#include "llvm/Target/TargetMachine.h" 36#include "llvm/Target/TargetRegisterInfo.h" 37#include "llvm/Target/TargetSubtargetInfo.h" 38#include <cctype> 39using namespace llvm; 40 41/// InitLibcallNames - Set default libcall names. 42/// 43static void InitLibcallNames(const char **Names, const Triple &TT) { 44 Names[RTLIB::SHL_I16] = "__ashlhi3"; 45 Names[RTLIB::SHL_I32] = "__ashlsi3"; 46 Names[RTLIB::SHL_I64] = "__ashldi3"; 47 Names[RTLIB::SHL_I128] = "__ashlti3"; 48 Names[RTLIB::SRL_I16] = "__lshrhi3"; 49 Names[RTLIB::SRL_I32] = "__lshrsi3"; 50 Names[RTLIB::SRL_I64] = "__lshrdi3"; 51 Names[RTLIB::SRL_I128] = "__lshrti3"; 52 Names[RTLIB::SRA_I16] = "__ashrhi3"; 53 Names[RTLIB::SRA_I32] = "__ashrsi3"; 54 Names[RTLIB::SRA_I64] = "__ashrdi3"; 55 Names[RTLIB::SRA_I128] = "__ashrti3"; 56 Names[RTLIB::MUL_I8] = "__mulqi3"; 57 Names[RTLIB::MUL_I16] = "__mulhi3"; 58 Names[RTLIB::MUL_I32] = "__mulsi3"; 59 Names[RTLIB::MUL_I64] = "__muldi3"; 60 Names[RTLIB::MUL_I128] = "__multi3"; 61 Names[RTLIB::MULO_I32] = "__mulosi4"; 62 Names[RTLIB::MULO_I64] = "__mulodi4"; 63 Names[RTLIB::MULO_I128] = "__muloti4"; 64 Names[RTLIB::SDIV_I8] = "__divqi3"; 65 Names[RTLIB::SDIV_I16] = "__divhi3"; 66 Names[RTLIB::SDIV_I32] = "__divsi3"; 67 Names[RTLIB::SDIV_I64] = "__divdi3"; 68 Names[RTLIB::SDIV_I128] = "__divti3"; 69 Names[RTLIB::UDIV_I8] = "__udivqi3"; 70 Names[RTLIB::UDIV_I16] = "__udivhi3"; 71 Names[RTLIB::UDIV_I32] = "__udivsi3"; 72 Names[RTLIB::UDIV_I64] = "__udivdi3"; 73 Names[RTLIB::UDIV_I128] = "__udivti3"; 74 Names[RTLIB::SREM_I8] = "__modqi3"; 75 Names[RTLIB::SREM_I16] = "__modhi3"; 76 Names[RTLIB::SREM_I32] = "__modsi3"; 77 Names[RTLIB::SREM_I64] = "__moddi3"; 78 Names[RTLIB::SREM_I128] = "__modti3"; 79 Names[RTLIB::UREM_I8] = "__umodqi3"; 80 Names[RTLIB::UREM_I16] = "__umodhi3"; 81 Names[RTLIB::UREM_I32] = "__umodsi3"; 82 Names[RTLIB::UREM_I64] = "__umoddi3"; 83 Names[RTLIB::UREM_I128] = "__umodti3"; 84 85 // These are generally not available. 86 Names[RTLIB::SDIVREM_I8] = nullptr; 87 Names[RTLIB::SDIVREM_I16] = nullptr; 88 Names[RTLIB::SDIVREM_I32] = nullptr; 89 Names[RTLIB::SDIVREM_I64] = nullptr; 90 Names[RTLIB::SDIVREM_I128] = nullptr; 91 Names[RTLIB::UDIVREM_I8] = nullptr; 92 Names[RTLIB::UDIVREM_I16] = nullptr; 93 Names[RTLIB::UDIVREM_I32] = nullptr; 94 Names[RTLIB::UDIVREM_I64] = nullptr; 95 Names[RTLIB::UDIVREM_I128] = nullptr; 96 97 Names[RTLIB::NEG_I32] = "__negsi2"; 98 Names[RTLIB::NEG_I64] = "__negdi2"; 99 Names[RTLIB::ADD_F32] = "__addsf3"; 100 Names[RTLIB::ADD_F64] = "__adddf3"; 101 Names[RTLIB::ADD_F80] = "__addxf3"; 102 Names[RTLIB::ADD_F128] = "__addtf3"; 103 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 104 Names[RTLIB::SUB_F32] = "__subsf3"; 105 Names[RTLIB::SUB_F64] = "__subdf3"; 106 Names[RTLIB::SUB_F80] = "__subxf3"; 107 Names[RTLIB::SUB_F128] = "__subtf3"; 108 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 109 Names[RTLIB::MUL_F32] = "__mulsf3"; 110 Names[RTLIB::MUL_F64] = "__muldf3"; 111 Names[RTLIB::MUL_F80] = "__mulxf3"; 112 Names[RTLIB::MUL_F128] = "__multf3"; 113 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 114 Names[RTLIB::DIV_F32] = "__divsf3"; 115 Names[RTLIB::DIV_F64] = "__divdf3"; 116 Names[RTLIB::DIV_F80] = "__divxf3"; 117 Names[RTLIB::DIV_F128] = "__divtf3"; 118 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 119 Names[RTLIB::REM_F32] = "fmodf"; 120 Names[RTLIB::REM_F64] = "fmod"; 121 Names[RTLIB::REM_F80] = "fmodl"; 122 Names[RTLIB::REM_F128] = "fmodl"; 123 Names[RTLIB::REM_PPCF128] = "fmodl"; 124 Names[RTLIB::FMA_F32] = "fmaf"; 125 Names[RTLIB::FMA_F64] = "fma"; 126 Names[RTLIB::FMA_F80] = "fmal"; 127 Names[RTLIB::FMA_F128] = "fmal"; 128 Names[RTLIB::FMA_PPCF128] = "fmal"; 129 Names[RTLIB::POWI_F32] = "__powisf2"; 130 Names[RTLIB::POWI_F64] = "__powidf2"; 131 Names[RTLIB::POWI_F80] = "__powixf2"; 132 Names[RTLIB::POWI_F128] = "__powitf2"; 133 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 134 Names[RTLIB::SQRT_F32] = "sqrtf"; 135 Names[RTLIB::SQRT_F64] = "sqrt"; 136 Names[RTLIB::SQRT_F80] = "sqrtl"; 137 Names[RTLIB::SQRT_F128] = "sqrtl"; 138 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 139 Names[RTLIB::LOG_F32] = "logf"; 140 Names[RTLIB::LOG_F64] = "log"; 141 Names[RTLIB::LOG_F80] = "logl"; 142 Names[RTLIB::LOG_F128] = "logl"; 143 Names[RTLIB::LOG_PPCF128] = "logl"; 144 Names[RTLIB::LOG2_F32] = "log2f"; 145 Names[RTLIB::LOG2_F64] = "log2"; 146 Names[RTLIB::LOG2_F80] = "log2l"; 147 Names[RTLIB::LOG2_F128] = "log2l"; 148 Names[RTLIB::LOG2_PPCF128] = "log2l"; 149 Names[RTLIB::LOG10_F32] = "log10f"; 150 Names[RTLIB::LOG10_F64] = "log10"; 151 Names[RTLIB::LOG10_F80] = "log10l"; 152 Names[RTLIB::LOG10_F128] = "log10l"; 153 Names[RTLIB::LOG10_PPCF128] = "log10l"; 154 Names[RTLIB::EXP_F32] = "expf"; 155 Names[RTLIB::EXP_F64] = "exp"; 156 Names[RTLIB::EXP_F80] = "expl"; 157 Names[RTLIB::EXP_F128] = "expl"; 158 Names[RTLIB::EXP_PPCF128] = "expl"; 159 Names[RTLIB::EXP2_F32] = "exp2f"; 160 Names[RTLIB::EXP2_F64] = "exp2"; 161 Names[RTLIB::EXP2_F80] = "exp2l"; 162 Names[RTLIB::EXP2_F128] = "exp2l"; 163 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 164 Names[RTLIB::SIN_F32] = "sinf"; 165 Names[RTLIB::SIN_F64] = "sin"; 166 Names[RTLIB::SIN_F80] = "sinl"; 167 Names[RTLIB::SIN_F128] = "sinl"; 168 Names[RTLIB::SIN_PPCF128] = "sinl"; 169 Names[RTLIB::COS_F32] = "cosf"; 170 Names[RTLIB::COS_F64] = "cos"; 171 Names[RTLIB::COS_F80] = "cosl"; 172 Names[RTLIB::COS_F128] = "cosl"; 173 Names[RTLIB::COS_PPCF128] = "cosl"; 174 Names[RTLIB::POW_F32] = "powf"; 175 Names[RTLIB::POW_F64] = "pow"; 176 Names[RTLIB::POW_F80] = "powl"; 177 Names[RTLIB::POW_F128] = "powl"; 178 Names[RTLIB::POW_PPCF128] = "powl"; 179 Names[RTLIB::CEIL_F32] = "ceilf"; 180 Names[RTLIB::CEIL_F64] = "ceil"; 181 Names[RTLIB::CEIL_F80] = "ceill"; 182 Names[RTLIB::CEIL_F128] = "ceill"; 183 Names[RTLIB::CEIL_PPCF128] = "ceill"; 184 Names[RTLIB::TRUNC_F32] = "truncf"; 185 Names[RTLIB::TRUNC_F64] = "trunc"; 186 Names[RTLIB::TRUNC_F80] = "truncl"; 187 Names[RTLIB::TRUNC_F128] = "truncl"; 188 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 189 Names[RTLIB::RINT_F32] = "rintf"; 190 Names[RTLIB::RINT_F64] = "rint"; 191 Names[RTLIB::RINT_F80] = "rintl"; 192 Names[RTLIB::RINT_F128] = "rintl"; 193 Names[RTLIB::RINT_PPCF128] = "rintl"; 194 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 195 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 196 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 197 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 198 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 199 Names[RTLIB::ROUND_F32] = "roundf"; 200 Names[RTLIB::ROUND_F64] = "round"; 201 Names[RTLIB::ROUND_F80] = "roundl"; 202 Names[RTLIB::ROUND_F128] = "roundl"; 203 Names[RTLIB::ROUND_PPCF128] = "roundl"; 204 Names[RTLIB::FLOOR_F32] = "floorf"; 205 Names[RTLIB::FLOOR_F64] = "floor"; 206 Names[RTLIB::FLOOR_F80] = "floorl"; 207 Names[RTLIB::FLOOR_F128] = "floorl"; 208 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 209 Names[RTLIB::FMIN_F32] = "fminf"; 210 Names[RTLIB::FMIN_F64] = "fmin"; 211 Names[RTLIB::FMIN_F80] = "fminl"; 212 Names[RTLIB::FMIN_F128] = "fminl"; 213 Names[RTLIB::FMIN_PPCF128] = "fminl"; 214 Names[RTLIB::FMAX_F32] = "fmaxf"; 215 Names[RTLIB::FMAX_F64] = "fmax"; 216 Names[RTLIB::FMAX_F80] = "fmaxl"; 217 Names[RTLIB::FMAX_F128] = "fmaxl"; 218 Names[RTLIB::FMAX_PPCF128] = "fmaxl"; 219 Names[RTLIB::ROUND_F32] = "roundf"; 220 Names[RTLIB::ROUND_F64] = "round"; 221 Names[RTLIB::ROUND_F80] = "roundl"; 222 Names[RTLIB::ROUND_F128] = "roundl"; 223 Names[RTLIB::ROUND_PPCF128] = "roundl"; 224 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 225 Names[RTLIB::COPYSIGN_F64] = "copysign"; 226 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 227 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 228 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 229 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 230 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 231 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 232 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 233 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 234 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2"; 235 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2"; 236 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2"; 237 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2"; 238 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 239 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 240 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 241 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 242 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 243 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 244 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 245 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 246 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 247 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 248 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 249 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 250 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 251 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 252 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 253 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 254 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 255 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 256 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 257 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 258 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 259 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 260 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 261 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 262 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 263 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 264 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 265 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 266 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 267 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 268 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 269 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 270 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 271 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 272 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 273 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 274 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 275 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 276 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 277 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 278 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 279 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 280 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 281 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 282 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 283 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 284 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 285 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 286 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 287 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 288 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 289 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 290 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 291 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 292 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 293 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 294 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 295 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 296 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 297 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 298 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 299 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 300 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 301 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 302 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 303 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 304 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 305 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 306 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 307 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 308 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 309 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 310 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 311 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 312 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 313 Names[RTLIB::OEQ_F32] = "__eqsf2"; 314 Names[RTLIB::OEQ_F64] = "__eqdf2"; 315 Names[RTLIB::OEQ_F128] = "__eqtf2"; 316 Names[RTLIB::UNE_F32] = "__nesf2"; 317 Names[RTLIB::UNE_F64] = "__nedf2"; 318 Names[RTLIB::UNE_F128] = "__netf2"; 319 Names[RTLIB::OGE_F32] = "__gesf2"; 320 Names[RTLIB::OGE_F64] = "__gedf2"; 321 Names[RTLIB::OGE_F128] = "__getf2"; 322 Names[RTLIB::OLT_F32] = "__ltsf2"; 323 Names[RTLIB::OLT_F64] = "__ltdf2"; 324 Names[RTLIB::OLT_F128] = "__lttf2"; 325 Names[RTLIB::OLE_F32] = "__lesf2"; 326 Names[RTLIB::OLE_F64] = "__ledf2"; 327 Names[RTLIB::OLE_F128] = "__letf2"; 328 Names[RTLIB::OGT_F32] = "__gtsf2"; 329 Names[RTLIB::OGT_F64] = "__gtdf2"; 330 Names[RTLIB::OGT_F128] = "__gttf2"; 331 Names[RTLIB::UO_F32] = "__unordsf2"; 332 Names[RTLIB::UO_F64] = "__unorddf2"; 333 Names[RTLIB::UO_F128] = "__unordtf2"; 334 Names[RTLIB::O_F32] = "__unordsf2"; 335 Names[RTLIB::O_F64] = "__unorddf2"; 336 Names[RTLIB::O_F128] = "__unordtf2"; 337 Names[RTLIB::MEMCPY] = "memcpy"; 338 Names[RTLIB::MEMMOVE] = "memmove"; 339 Names[RTLIB::MEMSET] = "memset"; 340 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 341 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 342 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 343 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 344 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 345 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 346 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 347 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 348 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 349 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 350 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 351 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 352 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 353 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 354 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 355 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 356 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 357 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 358 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 359 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 360 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 361 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 362 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 363 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 364 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 365 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 366 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 367 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 368 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 369 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 370 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 371 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 372 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 373 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 374 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 375 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 376 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 377 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 378 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 379 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 380 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 381 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 382 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 383 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 384 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 385 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 386 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 387 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 388 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 389 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 390 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 391 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 392 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 393 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 394 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 395 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 396 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 397 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 398 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 399 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 400 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 401 402 if (TT.getEnvironment() == Triple::GNU) { 403 Names[RTLIB::SINCOS_F32] = "sincosf"; 404 Names[RTLIB::SINCOS_F64] = "sincos"; 405 Names[RTLIB::SINCOS_F80] = "sincosl"; 406 Names[RTLIB::SINCOS_F128] = "sincosl"; 407 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 408 } else { 409 // These are generally not available. 410 Names[RTLIB::SINCOS_F32] = nullptr; 411 Names[RTLIB::SINCOS_F64] = nullptr; 412 Names[RTLIB::SINCOS_F80] = nullptr; 413 Names[RTLIB::SINCOS_F128] = nullptr; 414 Names[RTLIB::SINCOS_PPCF128] = nullptr; 415 } 416 417 if (!TT.isOSOpenBSD()) { 418 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 419 } else { 420 // These are generally not available. 421 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr; 422 } 423} 424 425/// InitLibcallCallingConvs - Set default libcall CallingConvs. 426/// 427static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 428 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 429 CCs[i] = CallingConv::C; 430 } 431} 432 433/// getFPEXT - Return the FPEXT_*_* value for the given types, or 434/// UNKNOWN_LIBCALL if there is none. 435RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 436 if (OpVT == MVT::f16) { 437 if (RetVT == MVT::f32) 438 return FPEXT_F16_F32; 439 } else if (OpVT == MVT::f32) { 440 if (RetVT == MVT::f64) 441 return FPEXT_F32_F64; 442 if (RetVT == MVT::f128) 443 return FPEXT_F32_F128; 444 } else if (OpVT == MVT::f64) { 445 if (RetVT == MVT::f128) 446 return FPEXT_F64_F128; 447 } 448 449 return UNKNOWN_LIBCALL; 450} 451 452/// getFPROUND - Return the FPROUND_*_* value for the given types, or 453/// UNKNOWN_LIBCALL if there is none. 454RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 455 if (RetVT == MVT::f16) { 456 if (OpVT == MVT::f32) 457 return FPROUND_F32_F16; 458 if (OpVT == MVT::f64) 459 return FPROUND_F64_F16; 460 if (OpVT == MVT::f80) 461 return FPROUND_F80_F16; 462 if (OpVT == MVT::f128) 463 return FPROUND_F128_F16; 464 if (OpVT == MVT::ppcf128) 465 return FPROUND_PPCF128_F16; 466 } else if (RetVT == MVT::f32) { 467 if (OpVT == MVT::f64) 468 return FPROUND_F64_F32; 469 if (OpVT == MVT::f80) 470 return FPROUND_F80_F32; 471 if (OpVT == MVT::f128) 472 return FPROUND_F128_F32; 473 if (OpVT == MVT::ppcf128) 474 return FPROUND_PPCF128_F32; 475 } else if (RetVT == MVT::f64) { 476 if (OpVT == MVT::f80) 477 return FPROUND_F80_F64; 478 if (OpVT == MVT::f128) 479 return FPROUND_F128_F64; 480 if (OpVT == MVT::ppcf128) 481 return FPROUND_PPCF128_F64; 482 } 483 484 return UNKNOWN_LIBCALL; 485} 486 487/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 488/// UNKNOWN_LIBCALL if there is none. 489RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 490 if (OpVT == MVT::f32) { 491 if (RetVT == MVT::i8) 492 return FPTOSINT_F32_I8; 493 if (RetVT == MVT::i16) 494 return FPTOSINT_F32_I16; 495 if (RetVT == MVT::i32) 496 return FPTOSINT_F32_I32; 497 if (RetVT == MVT::i64) 498 return FPTOSINT_F32_I64; 499 if (RetVT == MVT::i128) 500 return FPTOSINT_F32_I128; 501 } else if (OpVT == MVT::f64) { 502 if (RetVT == MVT::i8) 503 return FPTOSINT_F64_I8; 504 if (RetVT == MVT::i16) 505 return FPTOSINT_F64_I16; 506 if (RetVT == MVT::i32) 507 return FPTOSINT_F64_I32; 508 if (RetVT == MVT::i64) 509 return FPTOSINT_F64_I64; 510 if (RetVT == MVT::i128) 511 return FPTOSINT_F64_I128; 512 } else if (OpVT == MVT::f80) { 513 if (RetVT == MVT::i32) 514 return FPTOSINT_F80_I32; 515 if (RetVT == MVT::i64) 516 return FPTOSINT_F80_I64; 517 if (RetVT == MVT::i128) 518 return FPTOSINT_F80_I128; 519 } else if (OpVT == MVT::f128) { 520 if (RetVT == MVT::i32) 521 return FPTOSINT_F128_I32; 522 if (RetVT == MVT::i64) 523 return FPTOSINT_F128_I64; 524 if (RetVT == MVT::i128) 525 return FPTOSINT_F128_I128; 526 } else if (OpVT == MVT::ppcf128) { 527 if (RetVT == MVT::i32) 528 return FPTOSINT_PPCF128_I32; 529 if (RetVT == MVT::i64) 530 return FPTOSINT_PPCF128_I64; 531 if (RetVT == MVT::i128) 532 return FPTOSINT_PPCF128_I128; 533 } 534 return UNKNOWN_LIBCALL; 535} 536 537/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 538/// UNKNOWN_LIBCALL if there is none. 539RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 540 if (OpVT == MVT::f32) { 541 if (RetVT == MVT::i8) 542 return FPTOUINT_F32_I8; 543 if (RetVT == MVT::i16) 544 return FPTOUINT_F32_I16; 545 if (RetVT == MVT::i32) 546 return FPTOUINT_F32_I32; 547 if (RetVT == MVT::i64) 548 return FPTOUINT_F32_I64; 549 if (RetVT == MVT::i128) 550 return FPTOUINT_F32_I128; 551 } else if (OpVT == MVT::f64) { 552 if (RetVT == MVT::i8) 553 return FPTOUINT_F64_I8; 554 if (RetVT == MVT::i16) 555 return FPTOUINT_F64_I16; 556 if (RetVT == MVT::i32) 557 return FPTOUINT_F64_I32; 558 if (RetVT == MVT::i64) 559 return FPTOUINT_F64_I64; 560 if (RetVT == MVT::i128) 561 return FPTOUINT_F64_I128; 562 } else if (OpVT == MVT::f80) { 563 if (RetVT == MVT::i32) 564 return FPTOUINT_F80_I32; 565 if (RetVT == MVT::i64) 566 return FPTOUINT_F80_I64; 567 if (RetVT == MVT::i128) 568 return FPTOUINT_F80_I128; 569 } else if (OpVT == MVT::f128) { 570 if (RetVT == MVT::i32) 571 return FPTOUINT_F128_I32; 572 if (RetVT == MVT::i64) 573 return FPTOUINT_F128_I64; 574 if (RetVT == MVT::i128) 575 return FPTOUINT_F128_I128; 576 } else if (OpVT == MVT::ppcf128) { 577 if (RetVT == MVT::i32) 578 return FPTOUINT_PPCF128_I32; 579 if (RetVT == MVT::i64) 580 return FPTOUINT_PPCF128_I64; 581 if (RetVT == MVT::i128) 582 return FPTOUINT_PPCF128_I128; 583 } 584 return UNKNOWN_LIBCALL; 585} 586 587/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 588/// UNKNOWN_LIBCALL if there is none. 589RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 590 if (OpVT == MVT::i32) { 591 if (RetVT == MVT::f32) 592 return SINTTOFP_I32_F32; 593 if (RetVT == MVT::f64) 594 return SINTTOFP_I32_F64; 595 if (RetVT == MVT::f80) 596 return SINTTOFP_I32_F80; 597 if (RetVT == MVT::f128) 598 return SINTTOFP_I32_F128; 599 if (RetVT == MVT::ppcf128) 600 return SINTTOFP_I32_PPCF128; 601 } else if (OpVT == MVT::i64) { 602 if (RetVT == MVT::f32) 603 return SINTTOFP_I64_F32; 604 if (RetVT == MVT::f64) 605 return SINTTOFP_I64_F64; 606 if (RetVT == MVT::f80) 607 return SINTTOFP_I64_F80; 608 if (RetVT == MVT::f128) 609 return SINTTOFP_I64_F128; 610 if (RetVT == MVT::ppcf128) 611 return SINTTOFP_I64_PPCF128; 612 } else if (OpVT == MVT::i128) { 613 if (RetVT == MVT::f32) 614 return SINTTOFP_I128_F32; 615 if (RetVT == MVT::f64) 616 return SINTTOFP_I128_F64; 617 if (RetVT == MVT::f80) 618 return SINTTOFP_I128_F80; 619 if (RetVT == MVT::f128) 620 return SINTTOFP_I128_F128; 621 if (RetVT == MVT::ppcf128) 622 return SINTTOFP_I128_PPCF128; 623 } 624 return UNKNOWN_LIBCALL; 625} 626 627/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 628/// UNKNOWN_LIBCALL if there is none. 629RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 630 if (OpVT == MVT::i32) { 631 if (RetVT == MVT::f32) 632 return UINTTOFP_I32_F32; 633 if (RetVT == MVT::f64) 634 return UINTTOFP_I32_F64; 635 if (RetVT == MVT::f80) 636 return UINTTOFP_I32_F80; 637 if (RetVT == MVT::f128) 638 return UINTTOFP_I32_F128; 639 if (RetVT == MVT::ppcf128) 640 return UINTTOFP_I32_PPCF128; 641 } else if (OpVT == MVT::i64) { 642 if (RetVT == MVT::f32) 643 return UINTTOFP_I64_F32; 644 if (RetVT == MVT::f64) 645 return UINTTOFP_I64_F64; 646 if (RetVT == MVT::f80) 647 return UINTTOFP_I64_F80; 648 if (RetVT == MVT::f128) 649 return UINTTOFP_I64_F128; 650 if (RetVT == MVT::ppcf128) 651 return UINTTOFP_I64_PPCF128; 652 } else if (OpVT == MVT::i128) { 653 if (RetVT == MVT::f32) 654 return UINTTOFP_I128_F32; 655 if (RetVT == MVT::f64) 656 return UINTTOFP_I128_F64; 657 if (RetVT == MVT::f80) 658 return UINTTOFP_I128_F80; 659 if (RetVT == MVT::f128) 660 return UINTTOFP_I128_F128; 661 if (RetVT == MVT::ppcf128) 662 return UINTTOFP_I128_PPCF128; 663 } 664 return UNKNOWN_LIBCALL; 665} 666 667/// InitCmpLibcallCCs - Set default comparison libcall CC. 668/// 669static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 670 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 671 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 672 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 673 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 674 CCs[RTLIB::UNE_F32] = ISD::SETNE; 675 CCs[RTLIB::UNE_F64] = ISD::SETNE; 676 CCs[RTLIB::UNE_F128] = ISD::SETNE; 677 CCs[RTLIB::OGE_F32] = ISD::SETGE; 678 CCs[RTLIB::OGE_F64] = ISD::SETGE; 679 CCs[RTLIB::OGE_F128] = ISD::SETGE; 680 CCs[RTLIB::OLT_F32] = ISD::SETLT; 681 CCs[RTLIB::OLT_F64] = ISD::SETLT; 682 CCs[RTLIB::OLT_F128] = ISD::SETLT; 683 CCs[RTLIB::OLE_F32] = ISD::SETLE; 684 CCs[RTLIB::OLE_F64] = ISD::SETLE; 685 CCs[RTLIB::OLE_F128] = ISD::SETLE; 686 CCs[RTLIB::OGT_F32] = ISD::SETGT; 687 CCs[RTLIB::OGT_F64] = ISD::SETGT; 688 CCs[RTLIB::OGT_F128] = ISD::SETGT; 689 CCs[RTLIB::UO_F32] = ISD::SETNE; 690 CCs[RTLIB::UO_F64] = ISD::SETNE; 691 CCs[RTLIB::UO_F128] = ISD::SETNE; 692 CCs[RTLIB::O_F32] = ISD::SETEQ; 693 CCs[RTLIB::O_F64] = ISD::SETEQ; 694 CCs[RTLIB::O_F128] = ISD::SETEQ; 695} 696 697/// NOTE: The TargetMachine owns TLOF. 698TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) 699 : TM(tm), DL(TM.getSubtargetImpl()->getDataLayout()) { 700 initActions(); 701 702 // Perform these initializations only once. 703 IsLittleEndian = DL->isLittleEndian(); 704 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 705 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 706 = MaxStoresPerMemmoveOptSize = 4; 707 UseUnderscoreSetJmp = false; 708 UseUnderscoreLongJmp = false; 709 SelectIsExpensive = false; 710 HasMultipleConditionRegisters = false; 711 HasExtractBitsInsn = false; 712 IntDivIsCheap = false; 713 FsqrtIsCheap = false; 714 Pow2SDivIsCheap = false; 715 JumpIsExpensive = false; 716 PredictableSelectIsExpensive = false; 717 MaskAndBranchFoldingIsLegal = false; 718 EnableExtLdPromotion = false; 719 HasFloatingPointExceptions = true; 720 StackPointerRegisterToSaveRestore = 0; 721 ExceptionPointerRegister = 0; 722 ExceptionSelectorRegister = 0; 723 BooleanContents = UndefinedBooleanContent; 724 BooleanFloatContents = UndefinedBooleanContent; 725 BooleanVectorContents = UndefinedBooleanContent; 726 SchedPreferenceInfo = Sched::ILP; 727 JumpBufSize = 0; 728 JumpBufAlignment = 0; 729 MinFunctionAlignment = 0; 730 PrefFunctionAlignment = 0; 731 PrefLoopAlignment = 0; 732 MinStackArgumentAlignment = 1; 733 InsertFencesForAtomic = false; 734 MinimumJumpTableEntries = 4; 735 736 InitLibcallNames(LibcallRoutineNames, Triple(TM.getTargetTriple())); 737 InitCmpLibcallCCs(CmpLibcallCCs); 738 InitLibcallCallingConvs(LibcallCallingConvs); 739} 740 741void TargetLoweringBase::initActions() { 742 // All operations default to being supported. 743 memset(OpActions, 0, sizeof(OpActions)); 744 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 745 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 746 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 747 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 748 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 749 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 750 751 // Set default actions for various operations. 752 for (MVT VT : MVT::all_valuetypes()) { 753 // Default all indexed load / store to expand. 754 for (unsigned IM = (unsigned)ISD::PRE_INC; 755 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 756 setIndexedLoadAction(IM, VT, Expand); 757 setIndexedStoreAction(IM, VT, Expand); 758 } 759 760 // Most backends expect to see the node which just returns the value loaded. 761 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 762 763 // These operations default to expand. 764 setOperationAction(ISD::FGETSIGN, VT, Expand); 765 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 766 setOperationAction(ISD::FMINNUM, VT, Expand); 767 setOperationAction(ISD::FMAXNUM, VT, Expand); 768 769 // These library functions default to expand. 770 setOperationAction(ISD::FROUND, VT, Expand); 771 772 // These operations default to expand for vector types. 773 if (VT.isVector()) { 774 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 775 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 776 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 777 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 778 } 779 } 780 781 // Most targets ignore the @llvm.prefetch intrinsic. 782 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 783 784 // ConstantFP nodes default to expand. Targets can either change this to 785 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 786 // to optimize expansions for certain constants. 787 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 788 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 789 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 790 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 791 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 792 793 // These library functions default to expand. 794 setOperationAction(ISD::FLOG , MVT::f16, Expand); 795 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 796 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 797 setOperationAction(ISD::FEXP , MVT::f16, Expand); 798 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 799 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 800 setOperationAction(ISD::FMINNUM, MVT::f16, Expand); 801 setOperationAction(ISD::FMAXNUM, MVT::f16, Expand); 802 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 803 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 804 setOperationAction(ISD::FRINT, MVT::f16, Expand); 805 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 806 setOperationAction(ISD::FROUND, MVT::f16, Expand); 807 setOperationAction(ISD::FLOG , MVT::f32, Expand); 808 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 809 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 810 setOperationAction(ISD::FEXP , MVT::f32, Expand); 811 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 812 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 813 setOperationAction(ISD::FMINNUM, MVT::f32, Expand); 814 setOperationAction(ISD::FMAXNUM, MVT::f32, Expand); 815 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 816 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 817 setOperationAction(ISD::FRINT, MVT::f32, Expand); 818 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 819 setOperationAction(ISD::FROUND, MVT::f32, Expand); 820 setOperationAction(ISD::FLOG , MVT::f64, Expand); 821 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 822 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 823 setOperationAction(ISD::FEXP , MVT::f64, Expand); 824 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 825 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 826 setOperationAction(ISD::FMINNUM, MVT::f64, Expand); 827 setOperationAction(ISD::FMAXNUM, MVT::f64, Expand); 828 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 829 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 830 setOperationAction(ISD::FRINT, MVT::f64, Expand); 831 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 832 setOperationAction(ISD::FROUND, MVT::f64, Expand); 833 setOperationAction(ISD::FLOG , MVT::f128, Expand); 834 setOperationAction(ISD::FLOG2, MVT::f128, Expand); 835 setOperationAction(ISD::FLOG10, MVT::f128, Expand); 836 setOperationAction(ISD::FEXP , MVT::f128, Expand); 837 setOperationAction(ISD::FEXP2, MVT::f128, Expand); 838 setOperationAction(ISD::FFLOOR, MVT::f128, Expand); 839 setOperationAction(ISD::FMINNUM, MVT::f128, Expand); 840 setOperationAction(ISD::FMAXNUM, MVT::f128, Expand); 841 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand); 842 setOperationAction(ISD::FCEIL, MVT::f128, Expand); 843 setOperationAction(ISD::FRINT, MVT::f128, Expand); 844 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); 845 setOperationAction(ISD::FROUND, MVT::f128, Expand); 846 847 // Default ISD::TRAP to expand (which turns it into abort). 848 setOperationAction(ISD::TRAP, MVT::Other, Expand); 849 850 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 851 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 852 // 853 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 854} 855 856MVT TargetLoweringBase::getPointerTy(uint32_t AS) const { 857 return MVT::getIntegerVT(getPointerSizeInBits(AS)); 858} 859 860unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const { 861 return DL->getPointerSizeInBits(AS); 862} 863 864unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const { 865 assert(Ty->isPointerTy()); 866 return getPointerSizeInBits(Ty->getPointerAddressSpace()); 867} 868 869MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const { 870 return MVT::getIntegerVT(8*DL->getPointerSize(0)); 871} 872 873EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const { 874 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 875 if (LHSTy.isVector()) 876 return LHSTy; 877 return getScalarShiftAmountTy(LHSTy); 878} 879 880/// canOpTrap - Returns true if the operation can trap for the value type. 881/// VT must be a legal type. 882bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 883 assert(isTypeLegal(VT)); 884 switch (Op) { 885 default: 886 return false; 887 case ISD::FDIV: 888 case ISD::FREM: 889 case ISD::SDIV: 890 case ISD::UDIV: 891 case ISD::SREM: 892 case ISD::UREM: 893 return true; 894 } 895} 896 897 898static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 899 unsigned &NumIntermediates, 900 MVT &RegisterVT, 901 TargetLoweringBase *TLI) { 902 // Figure out the right, legal destination reg to copy into. 903 unsigned NumElts = VT.getVectorNumElements(); 904 MVT EltTy = VT.getVectorElementType(); 905 906 unsigned NumVectorRegs = 1; 907 908 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 909 // could break down into LHS/RHS like LegalizeDAG does. 910 if (!isPowerOf2_32(NumElts)) { 911 NumVectorRegs = NumElts; 912 NumElts = 1; 913 } 914 915 // Divide the input until we get to a supported size. This will always 916 // end with a scalar if the target doesn't support vectors. 917 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 918 NumElts >>= 1; 919 NumVectorRegs <<= 1; 920 } 921 922 NumIntermediates = NumVectorRegs; 923 924 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 925 if (!TLI->isTypeLegal(NewVT)) 926 NewVT = EltTy; 927 IntermediateVT = NewVT; 928 929 unsigned NewVTSize = NewVT.getSizeInBits(); 930 931 // Convert sizes such as i33 to i64. 932 if (!isPowerOf2_32(NewVTSize)) 933 NewVTSize = NextPowerOf2(NewVTSize); 934 935 MVT DestVT = TLI->getRegisterType(NewVT); 936 RegisterVT = DestVT; 937 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 938 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 939 940 // Otherwise, promotion or legal types use the same number of registers as 941 // the vector decimated to the appropriate level. 942 return NumVectorRegs; 943} 944 945/// isLegalRC - Return true if the value types that can be represented by the 946/// specified register class are all legal. 947bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 948 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 949 I != E; ++I) { 950 if (isTypeLegal(*I)) 951 return true; 952 } 953 return false; 954} 955 956/// Replace/modify any TargetFrameIndex operands with a targte-dependent 957/// sequence of memory operands that is recognized by PrologEpilogInserter. 958MachineBasicBlock* 959TargetLoweringBase::emitPatchPoint(MachineInstr *MI, 960 MachineBasicBlock *MBB) const { 961 MachineFunction &MF = *MI->getParent()->getParent(); 962 963 // MI changes inside this loop as we grow operands. 964 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 965 MachineOperand &MO = MI->getOperand(OperIdx); 966 if (!MO.isFI()) 967 continue; 968 969 // foldMemoryOperand builds a new MI after replacing a single FI operand 970 // with the canonical set of five x86 addressing-mode operands. 971 int FI = MO.getIndex(); 972 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 973 974 // Copy operands before the frame-index. 975 for (unsigned i = 0; i < OperIdx; ++i) 976 MIB.addOperand(MI->getOperand(i)); 977 // Add frame index operands: direct-mem-ref tag, #FI, offset. 978 MIB.addImm(StackMaps::DirectMemRefOp); 979 MIB.addOperand(MI->getOperand(OperIdx)); 980 MIB.addImm(0); 981 // Copy the operands after the frame index. 982 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 983 MIB.addOperand(MI->getOperand(i)); 984 985 // Inherit previous memory operands. 986 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 987 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 988 989 // Add a new memory operand for this FI. 990 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 991 assert(MFI.getObjectOffset(FI) != -1); 992 993 unsigned Flags = MachineMemOperand::MOLoad; 994 if (MI->getOpcode() == TargetOpcode::STATEPOINT) { 995 Flags |= MachineMemOperand::MOStore; 996 Flags |= MachineMemOperand::MOVolatile; 997 } 998 MachineMemOperand *MMO = MF.getMachineMemOperand( 999 MachinePointerInfo::getFixedStack(FI), Flags, 1000 TM.getSubtargetImpl()->getDataLayout()->getPointerSize(), 1001 MFI.getObjectAlignment(FI)); 1002 MIB->addMemOperand(MF, MMO); 1003 1004 // Replace the instruction and update the operand index. 1005 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1006 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 1007 MI->eraseFromParent(); 1008 MI = MIB; 1009 } 1010 return MBB; 1011} 1012 1013/// findRepresentativeClass - Return the largest legal super-reg register class 1014/// of the register class for the specified type and its associated "cost". 1015std::pair<const TargetRegisterClass*, uint8_t> 1016TargetLoweringBase::findRepresentativeClass(MVT VT) const { 1017 const TargetRegisterInfo *TRI = 1018 getTargetMachine().getSubtargetImpl()->getRegisterInfo(); 1019 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1020 if (!RC) 1021 return std::make_pair(RC, 0); 1022 1023 // Compute the set of all super-register classes. 1024 BitVector SuperRegRC(TRI->getNumRegClasses()); 1025 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1026 SuperRegRC.setBitsInMask(RCI.getMask()); 1027 1028 // Find the first legal register class with the largest spill size. 1029 const TargetRegisterClass *BestRC = RC; 1030 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 1031 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1032 // We want the largest possible spill size. 1033 if (SuperRC->getSize() <= BestRC->getSize()) 1034 continue; 1035 if (!isLegalRC(SuperRC)) 1036 continue; 1037 BestRC = SuperRC; 1038 } 1039 return std::make_pair(BestRC, 1); 1040} 1041 1042/// computeRegisterProperties - Once all of the register classes are added, 1043/// this allows us to compute derived properties we expose. 1044void TargetLoweringBase::computeRegisterProperties() { 1045 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1046 "Too many value types for ValueTypeActions to hold!"); 1047 1048 // Everything defaults to needing one register. 1049 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1050 NumRegistersForVT[i] = 1; 1051 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1052 } 1053 // ...except isVoid, which doesn't need any registers. 1054 NumRegistersForVT[MVT::isVoid] = 0; 1055 1056 // Find the largest integer register class. 1057 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1058 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1059 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1060 1061 // Every integer value type larger than this largest register takes twice as 1062 // many registers to represent as the previous ValueType. 1063 for (unsigned ExpandedReg = LargestIntReg + 1; 1064 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1065 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1066 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1067 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1068 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1069 TypeExpandInteger); 1070 } 1071 1072 // Inspect all of the ValueType's smaller than the largest integer 1073 // register to see which ones need promotion. 1074 unsigned LegalIntReg = LargestIntReg; 1075 for (unsigned IntReg = LargestIntReg - 1; 1076 IntReg >= (unsigned)MVT::i1; --IntReg) { 1077 MVT IVT = (MVT::SimpleValueType)IntReg; 1078 if (isTypeLegal(IVT)) { 1079 LegalIntReg = IntReg; 1080 } else { 1081 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1082 (const MVT::SimpleValueType)LegalIntReg; 1083 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1084 } 1085 } 1086 1087 // ppcf128 type is really two f64's. 1088 if (!isTypeLegal(MVT::ppcf128)) { 1089 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1090 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1091 TransformToType[MVT::ppcf128] = MVT::f64; 1092 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1093 } 1094 1095 // Decide how to handle f128. If the target does not have native f128 support, 1096 // expand it to i128 and we will be generating soft float library calls. 1097 if (!isTypeLegal(MVT::f128)) { 1098 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1099 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1100 TransformToType[MVT::f128] = MVT::i128; 1101 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1102 } 1103 1104 // Decide how to handle f64. If the target does not have native f64 support, 1105 // expand it to i64 and we will be generating soft float library calls. 1106 if (!isTypeLegal(MVT::f64)) { 1107 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1108 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1109 TransformToType[MVT::f64] = MVT::i64; 1110 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1111 } 1112 1113 // Decide how to handle f32. If the target does not have native support for 1114 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 1115 if (!isTypeLegal(MVT::f32)) { 1116 if (isTypeLegal(MVT::f64)) { 1117 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 1118 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 1119 TransformToType[MVT::f32] = MVT::f64; 1120 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 1121 } else { 1122 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1123 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1124 TransformToType[MVT::f32] = MVT::i32; 1125 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1126 } 1127 } 1128 1129 if (!isTypeLegal(MVT::f16)) { 1130 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16]; 1131 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16]; 1132 TransformToType[MVT::f16] = MVT::i16; 1133 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftenFloat); 1134 } 1135 1136 // Loop over all of the vector value types to see which need transformations. 1137 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1138 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1139 MVT VT = (MVT::SimpleValueType) i; 1140 if (isTypeLegal(VT)) 1141 continue; 1142 1143 MVT EltVT = VT.getVectorElementType(); 1144 unsigned NElts = VT.getVectorNumElements(); 1145 bool IsLegalWiderType = false; 1146 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1147 switch (PreferredAction) { 1148 case TypePromoteInteger: { 1149 // Try to promote the elements of integer vectors. If no legal 1150 // promotion was found, fall through to the widen-vector method. 1151 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1152 MVT SVT = (MVT::SimpleValueType) nVT; 1153 // Promote vectors of integers to vectors with the same number 1154 // of elements, with a wider element type. 1155 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 1156 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT) 1157 && SVT.getScalarType().isInteger()) { 1158 TransformToType[i] = SVT; 1159 RegisterTypeForVT[i] = SVT; 1160 NumRegistersForVT[i] = 1; 1161 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1162 IsLegalWiderType = true; 1163 break; 1164 } 1165 } 1166 if (IsLegalWiderType) 1167 break; 1168 } 1169 case TypeWidenVector: { 1170 // Try to widen the vector. 1171 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1172 MVT SVT = (MVT::SimpleValueType) nVT; 1173 if (SVT.getVectorElementType() == EltVT 1174 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1175 TransformToType[i] = SVT; 1176 RegisterTypeForVT[i] = SVT; 1177 NumRegistersForVT[i] = 1; 1178 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1179 IsLegalWiderType = true; 1180 break; 1181 } 1182 } 1183 if (IsLegalWiderType) 1184 break; 1185 } 1186 case TypeSplitVector: 1187 case TypeScalarizeVector: { 1188 MVT IntermediateVT; 1189 MVT RegisterVT; 1190 unsigned NumIntermediates; 1191 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1192 NumIntermediates, RegisterVT, this); 1193 RegisterTypeForVT[i] = RegisterVT; 1194 1195 MVT NVT = VT.getPow2VectorType(); 1196 if (NVT == VT) { 1197 // Type is already a power of 2. The default action is to split. 1198 TransformToType[i] = MVT::Other; 1199 if (PreferredAction == TypeScalarizeVector) 1200 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1201 else if (PreferredAction == TypeSplitVector) 1202 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1203 else 1204 // Set type action according to the number of elements. 1205 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector 1206 : TypeSplitVector); 1207 } else { 1208 TransformToType[i] = NVT; 1209 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1210 } 1211 break; 1212 } 1213 default: 1214 llvm_unreachable("Unknown vector legalization action!"); 1215 } 1216 } 1217 1218 // Determine the 'representative' register class for each value type. 1219 // An representative register class is the largest (meaning one which is 1220 // not a sub-register class / subreg register class) legal register class for 1221 // a group of value types. For example, on i386, i8, i16, and i32 1222 // representative would be GR32; while on x86_64 it's GR64. 1223 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1224 const TargetRegisterClass* RRC; 1225 uint8_t Cost; 1226 std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 1227 RepRegClassForVT[i] = RRC; 1228 RepRegClassCostForVT[i] = Cost; 1229 } 1230} 1231 1232EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const { 1233 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1234 return getPointerTy(0).SimpleTy; 1235} 1236 1237MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1238 return MVT::i32; // return the default value 1239} 1240 1241/// getVectorTypeBreakdown - Vector types are broken down into some number of 1242/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1243/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1244/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1245/// 1246/// This method returns the number of registers needed, and the VT for each 1247/// register. It also returns the VT and quantity of the intermediate values 1248/// before they are promoted/expanded. 1249/// 1250unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1251 EVT &IntermediateVT, 1252 unsigned &NumIntermediates, 1253 MVT &RegisterVT) const { 1254 unsigned NumElts = VT.getVectorNumElements(); 1255 1256 // If there is a wider vector type with the same element type as this one, 1257 // or a promoted vector type that has the same number of elements which 1258 // are wider, then we should convert to that legal vector type. 1259 // This handles things like <2 x float> -> <4 x float> and 1260 // <4 x i1> -> <4 x i32>. 1261 LegalizeTypeAction TA = getTypeAction(Context, VT); 1262 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1263 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1264 if (isTypeLegal(RegisterEVT)) { 1265 IntermediateVT = RegisterEVT; 1266 RegisterVT = RegisterEVT.getSimpleVT(); 1267 NumIntermediates = 1; 1268 return 1; 1269 } 1270 } 1271 1272 // Figure out the right, legal destination reg to copy into. 1273 EVT EltTy = VT.getVectorElementType(); 1274 1275 unsigned NumVectorRegs = 1; 1276 1277 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1278 // could break down into LHS/RHS like LegalizeDAG does. 1279 if (!isPowerOf2_32(NumElts)) { 1280 NumVectorRegs = NumElts; 1281 NumElts = 1; 1282 } 1283 1284 // Divide the input until we get to a supported size. This will always 1285 // end with a scalar if the target doesn't support vectors. 1286 while (NumElts > 1 && !isTypeLegal( 1287 EVT::getVectorVT(Context, EltTy, NumElts))) { 1288 NumElts >>= 1; 1289 NumVectorRegs <<= 1; 1290 } 1291 1292 NumIntermediates = NumVectorRegs; 1293 1294 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1295 if (!isTypeLegal(NewVT)) 1296 NewVT = EltTy; 1297 IntermediateVT = NewVT; 1298 1299 MVT DestVT = getRegisterType(Context, NewVT); 1300 RegisterVT = DestVT; 1301 unsigned NewVTSize = NewVT.getSizeInBits(); 1302 1303 // Convert sizes such as i33 to i64. 1304 if (!isPowerOf2_32(NewVTSize)) 1305 NewVTSize = NextPowerOf2(NewVTSize); 1306 1307 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1308 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1309 1310 // Otherwise, promotion or legal types use the same number of registers as 1311 // the vector decimated to the appropriate level. 1312 return NumVectorRegs; 1313} 1314 1315/// Get the EVTs and ArgFlags collections that represent the legalized return 1316/// type of the given function. This does not require a DAG or a return value, 1317/// and is suitable for use before any DAGs for the function are constructed. 1318/// TODO: Move this out of TargetLowering.cpp. 1319void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr, 1320 SmallVectorImpl<ISD::OutputArg> &Outs, 1321 const TargetLowering &TLI) { 1322 SmallVector<EVT, 4> ValueVTs; 1323 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1324 unsigned NumValues = ValueVTs.size(); 1325 if (NumValues == 0) return; 1326 1327 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1328 EVT VT = ValueVTs[j]; 1329 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1330 1331 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1332 ExtendKind = ISD::SIGN_EXTEND; 1333 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1334 ExtendKind = ISD::ZERO_EXTEND; 1335 1336 // FIXME: C calling convention requires the return type to be promoted to 1337 // at least 32-bit. But this is not necessary for non-C calling 1338 // conventions. The frontend should mark functions whose return values 1339 // require promoting with signext or zeroext attributes. 1340 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1341 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1342 if (VT.bitsLT(MinVT)) 1343 VT = MinVT; 1344 } 1345 1346 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1347 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1348 1349 // 'inreg' on function refers to return value 1350 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1351 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1352 Flags.setInReg(); 1353 1354 // Propagate extension type if any 1355 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1356 Flags.setSExt(); 1357 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1358 Flags.setZExt(); 1359 1360 for (unsigned i = 0; i < NumParts; ++i) 1361 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1362 } 1363} 1364 1365/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1366/// function arguments in the caller parameter area. This is the actual 1367/// alignment, not its logarithm. 1368unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const { 1369 return DL->getABITypeAlignment(Ty); 1370} 1371 1372//===----------------------------------------------------------------------===// 1373// TargetTransformInfo Helpers 1374//===----------------------------------------------------------------------===// 1375 1376int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1377 enum InstructionOpcodes { 1378#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1379#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1380#include "llvm/IR/Instruction.def" 1381 }; 1382 switch (static_cast<InstructionOpcodes>(Opcode)) { 1383 case Ret: return 0; 1384 case Br: return 0; 1385 case Switch: return 0; 1386 case IndirectBr: return 0; 1387 case Invoke: return 0; 1388 case Resume: return 0; 1389 case Unreachable: return 0; 1390 case Add: return ISD::ADD; 1391 case FAdd: return ISD::FADD; 1392 case Sub: return ISD::SUB; 1393 case FSub: return ISD::FSUB; 1394 case Mul: return ISD::MUL; 1395 case FMul: return ISD::FMUL; 1396 case UDiv: return ISD::UDIV; 1397 case SDiv: return ISD::SDIV; 1398 case FDiv: return ISD::FDIV; 1399 case URem: return ISD::UREM; 1400 case SRem: return ISD::SREM; 1401 case FRem: return ISD::FREM; 1402 case Shl: return ISD::SHL; 1403 case LShr: return ISD::SRL; 1404 case AShr: return ISD::SRA; 1405 case And: return ISD::AND; 1406 case Or: return ISD::OR; 1407 case Xor: return ISD::XOR; 1408 case Alloca: return 0; 1409 case Load: return ISD::LOAD; 1410 case Store: return ISD::STORE; 1411 case GetElementPtr: return 0; 1412 case Fence: return 0; 1413 case AtomicCmpXchg: return 0; 1414 case AtomicRMW: return 0; 1415 case Trunc: return ISD::TRUNCATE; 1416 case ZExt: return ISD::ZERO_EXTEND; 1417 case SExt: return ISD::SIGN_EXTEND; 1418 case FPToUI: return ISD::FP_TO_UINT; 1419 case FPToSI: return ISD::FP_TO_SINT; 1420 case UIToFP: return ISD::UINT_TO_FP; 1421 case SIToFP: return ISD::SINT_TO_FP; 1422 case FPTrunc: return ISD::FP_ROUND; 1423 case FPExt: return ISD::FP_EXTEND; 1424 case PtrToInt: return ISD::BITCAST; 1425 case IntToPtr: return ISD::BITCAST; 1426 case BitCast: return ISD::BITCAST; 1427 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1428 case ICmp: return ISD::SETCC; 1429 case FCmp: return ISD::SETCC; 1430 case PHI: return 0; 1431 case Call: return 0; 1432 case Select: return ISD::SELECT; 1433 case UserOp1: return 0; 1434 case UserOp2: return 0; 1435 case VAArg: return 0; 1436 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1437 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1438 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1439 case ExtractValue: return ISD::MERGE_VALUES; 1440 case InsertValue: return ISD::MERGE_VALUES; 1441 case LandingPad: return 0; 1442 } 1443 1444 llvm_unreachable("Unknown instruction type encountered!"); 1445} 1446 1447std::pair<unsigned, MVT> 1448TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const { 1449 LLVMContext &C = Ty->getContext(); 1450 EVT MTy = getValueType(Ty); 1451 1452 unsigned Cost = 1; 1453 // We keep legalizing the type until we find a legal kind. We assume that 1454 // the only operation that costs anything is the split. After splitting 1455 // we need to handle two types. 1456 while (true) { 1457 LegalizeKind LK = getTypeConversion(C, MTy); 1458 1459 if (LK.first == TypeLegal) 1460 return std::make_pair(Cost, MTy.getSimpleVT()); 1461 1462 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1463 Cost *= 2; 1464 1465 // Keep legalizing the type. 1466 MTy = LK.second; 1467 } 1468} 1469 1470//===----------------------------------------------------------------------===// 1471// Loop Strength Reduction hooks 1472//===----------------------------------------------------------------------===// 1473 1474/// isLegalAddressingMode - Return true if the addressing mode represented 1475/// by AM is legal for this target, for a load/store of the specified type. 1476bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, 1477 Type *Ty) const { 1478 // The default implementation of this implements a conservative RISCy, r+r and 1479 // r+i addr mode. 1480 1481 // Allows a sign-extended 16-bit immediate field. 1482 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1483 return false; 1484 1485 // No global is ever allowed as a base. 1486 if (AM.BaseGV) 1487 return false; 1488 1489 // Only support r+r, 1490 switch (AM.Scale) { 1491 case 0: // "r+i" or just "i", depending on HasBaseReg. 1492 break; 1493 case 1: 1494 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1495 return false; 1496 // Otherwise we have r+r or r+i. 1497 break; 1498 case 2: 1499 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1500 return false; 1501 // Allow 2*r as r+r. 1502 break; 1503 default: // Don't allow n * r 1504 return false; 1505 } 1506 1507 return true; 1508} 1509