ScheduleDAGSDNodes.cpp revision 206083
1193323Sed//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This implements the ScheduleDAG class, which is a base class used by 11193323Sed// scheduling implementation classes. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#define DEBUG_TYPE "pre-RA-sched" 16205218Srdivacky#include "SDNodeDbgValue.h" 17193323Sed#include "ScheduleDAGSDNodes.h" 18198090Srdivacky#include "InstrEmitter.h" 19193323Sed#include "llvm/CodeGen/SelectionDAG.h" 20193323Sed#include "llvm/Target/TargetMachine.h" 21193323Sed#include "llvm/Target/TargetInstrInfo.h" 22193323Sed#include "llvm/Target/TargetRegisterInfo.h" 23198090Srdivacky#include "llvm/Target/TargetSubtarget.h" 24202878Srdivacky#include "llvm/ADT/DenseMap.h" 25202878Srdivacky#include "llvm/ADT/SmallPtrSet.h" 26206083Srdivacky#include "llvm/ADT/SmallSet.h" 27202878Srdivacky#include "llvm/ADT/SmallVector.h" 28202878Srdivacky#include "llvm/ADT/Statistic.h" 29193323Sed#include "llvm/Support/Debug.h" 30193323Sed#include "llvm/Support/raw_ostream.h" 31193323Sedusing namespace llvm; 32193323Sed 33202878SrdivackySTATISTIC(LoadsClustered, "Number of loads clustered together"); 34202878Srdivacky 35193323SedScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf) 36193323Sed : ScheduleDAG(mf) { 37193323Sed} 38193323Sed 39193323Sed/// Run - perform scheduling. 40193323Sed/// 41193323Sedvoid ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb, 42193323Sed MachineBasicBlock::iterator insertPos) { 43193323Sed DAG = dag; 44193323Sed ScheduleDAG::Run(bb, insertPos); 45193323Sed} 46193323Sed 47193323SedSUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) { 48193323Sed SUnit *SU = NewSUnit(Old->getNode()); 49193323Sed SU->OrigNode = Old->OrigNode; 50193323Sed SU->Latency = Old->Latency; 51193323Sed SU->isTwoAddress = Old->isTwoAddress; 52193323Sed SU->isCommutable = Old->isCommutable; 53193323Sed SU->hasPhysRegDefs = Old->hasPhysRegDefs; 54193323Sed SU->hasPhysRegClobbers = Old->hasPhysRegClobbers; 55193323Sed Old->isCloned = true; 56193323Sed return SU; 57193323Sed} 58193323Sed 59193323Sed/// CheckForPhysRegDependency - Check if the dependency between def and use of 60193323Sed/// a specified operand is a physical register dependency. If so, returns the 61193323Sed/// register and the cost of copying the register. 62193323Sedstatic void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, 63193323Sed const TargetRegisterInfo *TRI, 64193323Sed const TargetInstrInfo *TII, 65193323Sed unsigned &PhysReg, int &Cost) { 66193323Sed if (Op != 2 || User->getOpcode() != ISD::CopyToReg) 67193323Sed return; 68193323Sed 69193323Sed unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 70193323Sed if (TargetRegisterInfo::isVirtualRegister(Reg)) 71193323Sed return; 72193323Sed 73193323Sed unsigned ResNo = User->getOperand(2).getResNo(); 74193323Sed if (Def->isMachineOpcode()) { 75193323Sed const TargetInstrDesc &II = TII->get(Def->getMachineOpcode()); 76193323Sed if (ResNo >= II.getNumDefs() && 77193323Sed II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { 78193323Sed PhysReg = Reg; 79193323Sed const TargetRegisterClass *RC = 80193323Sed TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo)); 81193323Sed Cost = RC->getCopyCost(); 82193323Sed } 83193323Sed } 84193323Sed} 85193323Sed 86202878Srdivackystatic void AddFlags(SDNode *N, SDValue Flag, bool AddFlag, 87202878Srdivacky SelectionDAG *DAG) { 88202878Srdivacky SmallVector<EVT, 4> VTs; 89202878Srdivacky for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) 90202878Srdivacky VTs.push_back(N->getValueType(i)); 91202878Srdivacky if (AddFlag) 92202878Srdivacky VTs.push_back(MVT::Flag); 93202878Srdivacky SmallVector<SDValue, 4> Ops; 94202878Srdivacky for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 95202878Srdivacky Ops.push_back(N->getOperand(i)); 96202878Srdivacky if (Flag.getNode()) 97202878Srdivacky Ops.push_back(Flag); 98202878Srdivacky SDVTList VTList = DAG->getVTList(&VTs[0], VTs.size()); 99202878Srdivacky DAG->MorphNodeTo(N, N->getOpcode(), VTList, &Ops[0], Ops.size()); 100202878Srdivacky} 101202878Srdivacky 102202878Srdivacky/// ClusterNeighboringLoads - Force nearby loads together by "flagging" them. 103202878Srdivacky/// This function finds loads of the same base and different offsets. If the 104202878Srdivacky/// offsets are not far apart (target specific), it add MVT::Flag inputs and 105202878Srdivacky/// outputs to ensure they are scheduled together and in order. This 106202878Srdivacky/// optimization may benefit some targets by improving cache locality. 107202878Srdivackyvoid ScheduleDAGSDNodes::ClusterNeighboringLoads() { 108202878Srdivacky SmallPtrSet<SDNode*, 16> Visited; 109202878Srdivacky SmallVector<int64_t, 4> Offsets; 110202878Srdivacky DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode. 111202878Srdivacky for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), 112202878Srdivacky E = DAG->allnodes_end(); NI != E; ++NI) { 113202878Srdivacky SDNode *Node = &*NI; 114202878Srdivacky if (!Node || !Node->isMachineOpcode()) 115202878Srdivacky continue; 116202878Srdivacky 117202878Srdivacky unsigned Opc = Node->getMachineOpcode(); 118202878Srdivacky const TargetInstrDesc &TID = TII->get(Opc); 119202878Srdivacky if (!TID.mayLoad()) 120202878Srdivacky continue; 121202878Srdivacky 122202878Srdivacky SDNode *Chain = 0; 123202878Srdivacky unsigned NumOps = Node->getNumOperands(); 124202878Srdivacky if (Node->getOperand(NumOps-1).getValueType() == MVT::Other) 125202878Srdivacky Chain = Node->getOperand(NumOps-1).getNode(); 126202878Srdivacky if (!Chain) 127202878Srdivacky continue; 128202878Srdivacky 129202878Srdivacky // Look for other loads of the same chain. Find loads that are loading from 130202878Srdivacky // the same base pointer and different offsets. 131202878Srdivacky Visited.clear(); 132202878Srdivacky Offsets.clear(); 133202878Srdivacky O2SMap.clear(); 134202878Srdivacky bool Cluster = false; 135202878Srdivacky SDNode *Base = Node; 136202878Srdivacky int64_t BaseOffset; 137202878Srdivacky for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end(); 138202878Srdivacky I != E; ++I) { 139202878Srdivacky SDNode *User = *I; 140202878Srdivacky if (User == Node || !Visited.insert(User)) 141202878Srdivacky continue; 142202878Srdivacky int64_t Offset1, Offset2; 143202878Srdivacky if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || 144202878Srdivacky Offset1 == Offset2) 145202878Srdivacky // FIXME: Should be ok if they addresses are identical. But earlier 146202878Srdivacky // optimizations really should have eliminated one of the loads. 147202878Srdivacky continue; 148202878Srdivacky if (O2SMap.insert(std::make_pair(Offset1, Base)).second) 149202878Srdivacky Offsets.push_back(Offset1); 150202878Srdivacky O2SMap.insert(std::make_pair(Offset2, User)); 151202878Srdivacky Offsets.push_back(Offset2); 152202878Srdivacky if (Offset2 < Offset1) { 153202878Srdivacky Base = User; 154202878Srdivacky BaseOffset = Offset2; 155202878Srdivacky } else { 156202878Srdivacky BaseOffset = Offset1; 157202878Srdivacky } 158202878Srdivacky Cluster = true; 159202878Srdivacky } 160202878Srdivacky 161202878Srdivacky if (!Cluster) 162202878Srdivacky continue; 163202878Srdivacky 164202878Srdivacky // Sort them in increasing order. 165202878Srdivacky std::sort(Offsets.begin(), Offsets.end()); 166202878Srdivacky 167202878Srdivacky // Check if the loads are close enough. 168202878Srdivacky SmallVector<SDNode*, 4> Loads; 169202878Srdivacky unsigned NumLoads = 0; 170202878Srdivacky int64_t BaseOff = Offsets[0]; 171202878Srdivacky SDNode *BaseLoad = O2SMap[BaseOff]; 172202878Srdivacky Loads.push_back(BaseLoad); 173202878Srdivacky for (unsigned i = 1, e = Offsets.size(); i != e; ++i) { 174202878Srdivacky int64_t Offset = Offsets[i]; 175202878Srdivacky SDNode *Load = O2SMap[Offset]; 176202878Srdivacky if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset, 177202878Srdivacky NumLoads)) 178202878Srdivacky break; // Stop right here. Ignore loads that are further away. 179202878Srdivacky Loads.push_back(Load); 180202878Srdivacky ++NumLoads; 181202878Srdivacky } 182202878Srdivacky 183202878Srdivacky if (NumLoads == 0) 184202878Srdivacky continue; 185202878Srdivacky 186202878Srdivacky // Cluster loads by adding MVT::Flag outputs and inputs. This also 187202878Srdivacky // ensure they are scheduled in order of increasing addresses. 188202878Srdivacky SDNode *Lead = Loads[0]; 189202878Srdivacky AddFlags(Lead, SDValue(0,0), true, DAG); 190202878Srdivacky SDValue InFlag = SDValue(Lead, Lead->getNumValues()-1); 191202878Srdivacky for (unsigned i = 1, e = Loads.size(); i != e; ++i) { 192202878Srdivacky bool OutFlag = i < e-1; 193202878Srdivacky SDNode *Load = Loads[i]; 194202878Srdivacky AddFlags(Load, InFlag, OutFlag, DAG); 195202878Srdivacky if (OutFlag) 196202878Srdivacky InFlag = SDValue(Load, Load->getNumValues()-1); 197202878Srdivacky ++LoadsClustered; 198202878Srdivacky } 199202878Srdivacky } 200202878Srdivacky} 201202878Srdivacky 202193323Sedvoid ScheduleDAGSDNodes::BuildSchedUnits() { 203193323Sed // During scheduling, the NodeId field of SDNode is used to map SDNodes 204193323Sed // to their associated SUnits by holding SUnits table indices. A value 205193323Sed // of -1 means the SDNode does not yet have an associated SUnit. 206193323Sed unsigned NumNodes = 0; 207193323Sed for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), 208193323Sed E = DAG->allnodes_end(); NI != E; ++NI) { 209193323Sed NI->setNodeId(-1); 210193323Sed ++NumNodes; 211193323Sed } 212193323Sed 213193323Sed // Reserve entries in the vector for each of the SUnits we are creating. This 214193323Sed // ensure that reallocation of the vector won't happen, so SUnit*'s won't get 215193323Sed // invalidated. 216193323Sed // FIXME: Multiply by 2 because we may clone nodes during scheduling. 217193323Sed // This is a temporary workaround. 218193323Sed SUnits.reserve(NumNodes * 2); 219193323Sed 220193323Sed // Check to see if the scheduler cares about latencies. 221193323Sed bool UnitLatencies = ForceUnitLatencies(); 222193323Sed 223204642Srdivacky // Add all nodes in depth first order. 224204642Srdivacky SmallVector<SDNode*, 64> Worklist; 225204642Srdivacky SmallPtrSet<SDNode*, 64> Visited; 226204642Srdivacky Worklist.push_back(DAG->getRoot().getNode()); 227204642Srdivacky Visited.insert(DAG->getRoot().getNode()); 228204642Srdivacky 229204642Srdivacky while (!Worklist.empty()) { 230204642Srdivacky SDNode *NI = Worklist.pop_back_val(); 231204642Srdivacky 232204642Srdivacky // Add all operands to the worklist unless they've already been added. 233204642Srdivacky for (unsigned i = 0, e = NI->getNumOperands(); i != e; ++i) 234204642Srdivacky if (Visited.insert(NI->getOperand(i).getNode())) 235204642Srdivacky Worklist.push_back(NI->getOperand(i).getNode()); 236204642Srdivacky 237193323Sed if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate. 238193323Sed continue; 239193323Sed 240193323Sed // If this node has already been processed, stop now. 241193323Sed if (NI->getNodeId() != -1) continue; 242193323Sed 243193323Sed SUnit *NodeSUnit = NewSUnit(NI); 244193323Sed 245193323Sed // See if anything is flagged to this node, if so, add them to flagged 246193323Sed // nodes. Nodes can have at most one flag input and one flag output. Flags 247193323Sed // are required to be the last operand and result of a node. 248193323Sed 249193323Sed // Scan up to find flagged preds. 250193323Sed SDNode *N = NI; 251193323Sed while (N->getNumOperands() && 252193323Sed N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) { 253193323Sed N = N->getOperand(N->getNumOperands()-1).getNode(); 254193323Sed assert(N->getNodeId() == -1 && "Node already inserted!"); 255193323Sed N->setNodeId(NodeSUnit->NodeNum); 256193323Sed } 257193323Sed 258193323Sed // Scan down to find any flagged succs. 259193323Sed N = NI; 260193323Sed while (N->getValueType(N->getNumValues()-1) == MVT::Flag) { 261193323Sed SDValue FlagVal(N, N->getNumValues()-1); 262193323Sed 263193323Sed // There are either zero or one users of the Flag result. 264193323Sed bool HasFlagUse = false; 265193323Sed for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 266193323Sed UI != E; ++UI) 267193323Sed if (FlagVal.isOperandOf(*UI)) { 268193323Sed HasFlagUse = true; 269193323Sed assert(N->getNodeId() == -1 && "Node already inserted!"); 270193323Sed N->setNodeId(NodeSUnit->NodeNum); 271193323Sed N = *UI; 272193323Sed break; 273193323Sed } 274193323Sed if (!HasFlagUse) break; 275193323Sed } 276193323Sed 277193323Sed // If there are flag operands involved, N is now the bottom-most node 278193323Sed // of the sequence of nodes that are flagged together. 279193323Sed // Update the SUnit. 280193323Sed NodeSUnit->setNode(N); 281193323Sed assert(N->getNodeId() == -1 && "Node already inserted!"); 282193323Sed N->setNodeId(NodeSUnit->NodeNum); 283193323Sed 284193323Sed // Assign the Latency field of NodeSUnit using target-provided information. 285193323Sed if (UnitLatencies) 286193323Sed NodeSUnit->Latency = 1; 287193323Sed else 288193323Sed ComputeLatency(NodeSUnit); 289193323Sed } 290193323Sed} 291193323Sed 292193323Sedvoid ScheduleDAGSDNodes::AddSchedEdges() { 293198090Srdivacky const TargetSubtarget &ST = TM.getSubtarget<TargetSubtarget>(); 294198090Srdivacky 295198090Srdivacky // Check to see if the scheduler cares about latencies. 296198090Srdivacky bool UnitLatencies = ForceUnitLatencies(); 297198090Srdivacky 298193323Sed // Pass 2: add the preds, succs, etc. 299193323Sed for (unsigned su = 0, e = SUnits.size(); su != e; ++su) { 300193323Sed SUnit *SU = &SUnits[su]; 301193323Sed SDNode *MainNode = SU->getNode(); 302193323Sed 303193323Sed if (MainNode->isMachineOpcode()) { 304193323Sed unsigned Opc = MainNode->getMachineOpcode(); 305193323Sed const TargetInstrDesc &TID = TII->get(Opc); 306193323Sed for (unsigned i = 0; i != TID.getNumOperands(); ++i) { 307193323Sed if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { 308193323Sed SU->isTwoAddress = true; 309193323Sed break; 310193323Sed } 311193323Sed } 312193323Sed if (TID.isCommutable()) 313193323Sed SU->isCommutable = true; 314193323Sed } 315193323Sed 316193323Sed // Find all predecessors and successors of the group. 317193323Sed for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) { 318193323Sed if (N->isMachineOpcode() && 319193323Sed TII->get(N->getMachineOpcode()).getImplicitDefs()) { 320193323Sed SU->hasPhysRegClobbers = true; 321198090Srdivacky unsigned NumUsed = InstrEmitter::CountResults(N); 322193323Sed while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1)) 323193323Sed --NumUsed; // Skip over unused values at the end. 324193323Sed if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) 325193323Sed SU->hasPhysRegDefs = true; 326193323Sed } 327193323Sed 328193323Sed for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 329193323Sed SDNode *OpN = N->getOperand(i).getNode(); 330193323Sed if (isPassiveNode(OpN)) continue; // Not scheduled. 331193323Sed SUnit *OpSU = &SUnits[OpN->getNodeId()]; 332193323Sed assert(OpSU && "Node has no SUnit!"); 333193323Sed if (OpSU == SU) continue; // In the same group. 334193323Sed 335198090Srdivacky EVT OpVT = N->getOperand(i).getValueType(); 336193323Sed assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!"); 337193323Sed bool isChain = OpVT == MVT::Other; 338193323Sed 339193323Sed unsigned PhysReg = 0; 340193323Sed int Cost = 1; 341193323Sed // Determine if this is a physical register dependency. 342193323Sed CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 343193323Sed assert((PhysReg == 0 || !isChain) && 344193323Sed "Chain dependence via physreg data?"); 345193323Sed // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler 346193323Sed // emits a copy from the physical register to a virtual register unless 347193323Sed // it requires a cross class copy (cost < 0). That means we are only 348193323Sed // treating "expensive to copy" register dependency as physical register 349193323Sed // dependency. This may change in the future though. 350193323Sed if (Cost >= 0) 351193323Sed PhysReg = 0; 352198090Srdivacky 353198090Srdivacky const SDep& dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data, 354198090Srdivacky OpSU->Latency, PhysReg); 355198090Srdivacky if (!isChain && !UnitLatencies) { 356198090Srdivacky ComputeOperandLatency(OpSU, SU, (SDep &)dep); 357198090Srdivacky ST.adjustSchedDependency(OpSU, SU, (SDep &)dep); 358198090Srdivacky } 359198090Srdivacky 360198090Srdivacky SU->addPred(dep); 361193323Sed } 362193323Sed } 363193323Sed } 364193323Sed} 365193323Sed 366193323Sed/// BuildSchedGraph - Build the SUnit graph from the selection dag that we 367193323Sed/// are input. This SUnit graph is similar to the SelectionDAG, but 368193323Sed/// excludes nodes that aren't interesting to scheduling, and represents 369193323Sed/// flagged together nodes with a single SUnit. 370198090Srdivackyvoid ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) { 371202878Srdivacky // Cluster loads from "near" addresses into combined SUnits. 372202878Srdivacky ClusterNeighboringLoads(); 373193323Sed // Populate the SUnits array. 374193323Sed BuildSchedUnits(); 375193323Sed // Compute all the scheduling dependencies between nodes. 376193323Sed AddSchedEdges(); 377193323Sed} 378193323Sed 379193323Sedvoid ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) { 380193323Sed const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); 381193323Sed 382193323Sed // Compute the latency for the node. We use the sum of the latencies for 383193323Sed // all nodes flagged together into this SUnit. 384193323Sed SU->Latency = 0; 385193323Sed for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) 386193323Sed if (N->isMachineOpcode()) { 387198090Srdivacky SU->Latency += InstrItins. 388198090Srdivacky getStageLatency(TII->get(N->getMachineOpcode()).getSchedClass()); 389193323Sed } 390193323Sed} 391193323Sed 392193323Sedvoid ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const { 393193323Sed if (!SU->getNode()) { 394202375Srdivacky dbgs() << "PHYS REG COPY\n"; 395193323Sed return; 396193323Sed } 397193323Sed 398193323Sed SU->getNode()->dump(DAG); 399202375Srdivacky dbgs() << "\n"; 400193323Sed SmallVector<SDNode *, 4> FlaggedNodes; 401193323Sed for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode()) 402193323Sed FlaggedNodes.push_back(N); 403193323Sed while (!FlaggedNodes.empty()) { 404202375Srdivacky dbgs() << " "; 405193323Sed FlaggedNodes.back()->dump(DAG); 406202375Srdivacky dbgs() << "\n"; 407193323Sed FlaggedNodes.pop_back(); 408193323Sed } 409193323Sed} 410198090Srdivacky 411206083Srdivackynamespace { 412206083Srdivacky struct OrderSorter { 413206083Srdivacky bool operator()(const std::pair<unsigned, MachineInstr*> &A, 414206083Srdivacky const std::pair<unsigned, MachineInstr*> &B) { 415206083Srdivacky return A.first < B.first; 416206083Srdivacky } 417206083Srdivacky }; 418206083Srdivacky} 419206083Srdivacky 420206083Srdivacky// ProcessSourceNode - Process nodes with source order numbers. These are added 421206083Srdivacky// to a vector which EmitSchedule use to determine how to insert dbg_value 422206083Srdivacky// instructions in the right order. 423206083Srdivackystatic void ProcessSourceNode(SDNode *N, SelectionDAG *DAG, 424206083Srdivacky InstrEmitter &Emitter, 425206083Srdivacky DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM, 426206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 427206083Srdivacky SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders, 428206083Srdivacky SmallSet<unsigned, 8> &Seen) { 429206083Srdivacky unsigned Order = DAG->GetOrdering(N); 430206083Srdivacky if (!Order || !Seen.insert(Order)) 431206083Srdivacky return; 432206083Srdivacky 433206083Srdivacky MachineBasicBlock *BB = Emitter.getBlock(); 434206083Srdivacky if (BB->empty() || BB->back().isPHI()) { 435206083Srdivacky // Did not insert any instruction. 436206083Srdivacky Orders.push_back(std::make_pair(Order, (MachineInstr*)0)); 437206083Srdivacky return; 438206083Srdivacky } 439206083Srdivacky 440206083Srdivacky Orders.push_back(std::make_pair(Order, &BB->back())); 441206083Srdivacky if (!N->getHasDebugValue()) 442206083Srdivacky return; 443206083Srdivacky // Opportunistically insert immediate dbg_value uses, i.e. those with source 444206083Srdivacky // order number right after the N. 445206083Srdivacky MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos(); 446206083Srdivacky SmallVector<SDDbgValue*,2> &DVs = DAG->GetDbgValues(N); 447206083Srdivacky for (unsigned i = 0, e = DVs.size(); i != e; ++i) { 448206083Srdivacky if (DVs[i]->isInvalidated()) 449206083Srdivacky continue; 450206083Srdivacky unsigned DVOrder = DVs[i]->getOrder(); 451206083Srdivacky if (DVOrder == ++Order) { 452206083Srdivacky MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], BB, VRBaseMap, EM); 453206083Srdivacky Orders.push_back(std::make_pair(DVOrder, DbgMI)); 454206083Srdivacky BB->insert(InsertPos, DbgMI); 455206083Srdivacky DVs[i]->setIsInvalidated(); 456206083Srdivacky } 457206083Srdivacky } 458206083Srdivacky} 459206083Srdivacky 460206083Srdivacky 461198090Srdivacky/// EmitSchedule - Emit the machine code in scheduled order. 462198090SrdivackyMachineBasicBlock *ScheduleDAGSDNodes:: 463198090SrdivackyEmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) { 464198090Srdivacky InstrEmitter Emitter(BB, InsertPos); 465198090Srdivacky DenseMap<SDValue, unsigned> VRBaseMap; 466198090Srdivacky DenseMap<SUnit*, unsigned> CopyVRBaseMap; 467206083Srdivacky SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; 468206083Srdivacky SmallSet<unsigned, 8> Seen; 469206083Srdivacky bool HasDbg = DAG->hasDebugValues(); 470205218Srdivacky 471198090Srdivacky for (unsigned i = 0, e = Sequence.size(); i != e; i++) { 472198090Srdivacky SUnit *SU = Sequence[i]; 473198090Srdivacky if (!SU) { 474198090Srdivacky // Null SUnit* is a noop. 475198090Srdivacky EmitNoop(); 476198090Srdivacky continue; 477198090Srdivacky } 478198090Srdivacky 479198090Srdivacky // For pre-regalloc scheduling, create instructions corresponding to the 480198090Srdivacky // SDNode and any flagged SDNodes and append them to the block. 481198090Srdivacky if (!SU->getNode()) { 482198090Srdivacky // Emit a copy. 483198090Srdivacky EmitPhysRegCopy(SU, CopyVRBaseMap); 484198090Srdivacky continue; 485198090Srdivacky } 486198090Srdivacky 487198090Srdivacky SmallVector<SDNode *, 4> FlaggedNodes; 488198090Srdivacky for (SDNode *N = SU->getNode()->getFlaggedNode(); N; 489198090Srdivacky N = N->getFlaggedNode()) 490198090Srdivacky FlaggedNodes.push_back(N); 491198090Srdivacky while (!FlaggedNodes.empty()) { 492206083Srdivacky SDNode *N = FlaggedNodes.back(); 493198090Srdivacky Emitter.EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned, 494198090Srdivacky VRBaseMap, EM); 495206083Srdivacky // Remember the the source order of the inserted instruction. 496206083Srdivacky if (HasDbg) 497206083Srdivacky ProcessSourceNode(N, DAG, Emitter, EM, VRBaseMap, Orders, Seen); 498198090Srdivacky FlaggedNodes.pop_back(); 499198090Srdivacky } 500198090Srdivacky Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, 501198090Srdivacky VRBaseMap, EM); 502206083Srdivacky // Remember the the source order of the inserted instruction. 503206083Srdivacky if (HasDbg) 504206083Srdivacky ProcessSourceNode(SU->getNode(), DAG, Emitter, EM, VRBaseMap, Orders, 505206083Srdivacky Seen); 506206083Srdivacky } 507206083Srdivacky 508206083Srdivacky // Insert all the dbg_value which have not already been inserted in source 509206083Srdivacky // order sequence. 510206083Srdivacky if (HasDbg) { 511206083Srdivacky MachineBasicBlock::iterator BBBegin = BB->empty() ? BB->end() : BB->begin(); 512206083Srdivacky while (BBBegin != BB->end() && BBBegin->isPHI()) 513206083Srdivacky ++BBBegin; 514206083Srdivacky 515206083Srdivacky // Sort the source order instructions and use the order to insert debug 516206083Srdivacky // values. 517206083Srdivacky std::sort(Orders.begin(), Orders.end(), OrderSorter()); 518206083Srdivacky 519206083Srdivacky SDDbgInfo::DbgIterator DI = DAG->DbgBegin(); 520206083Srdivacky SDDbgInfo::DbgIterator DE = DAG->DbgEnd(); 521206083Srdivacky // Now emit the rest according to source order. 522206083Srdivacky unsigned LastOrder = 0; 523206083Srdivacky MachineInstr *LastMI = 0; 524206083Srdivacky for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) { 525206083Srdivacky unsigned Order = Orders[i].first; 526206083Srdivacky MachineInstr *MI = Orders[i].second; 527206083Srdivacky // Insert all SDDbgValue's whose order(s) are before "Order". 528206083Srdivacky if (!MI) 529206083Srdivacky continue; 530206083Srdivacky MachineBasicBlock *MIBB = MI->getParent(); 531206083Srdivacky#ifndef NDEBUG 532206083Srdivacky unsigned LastDIOrder = 0; 533206083Srdivacky#endif 534206083Srdivacky for (; DI != DE && 535206083Srdivacky (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) { 536206083Srdivacky#ifndef NDEBUG 537206083Srdivacky assert((*DI)->getOrder() >= LastDIOrder && 538206083Srdivacky "SDDbgValue nodes must be in source order!"); 539206083Srdivacky LastDIOrder = (*DI)->getOrder(); 540206083Srdivacky#endif 541206083Srdivacky if ((*DI)->isInvalidated()) 542206083Srdivacky continue; 543206083Srdivacky MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, MIBB, VRBaseMap, EM); 544206083Srdivacky if (!LastOrder) 545206083Srdivacky // Insert to start of the BB (after PHIs). 546206083Srdivacky BB->insert(BBBegin, DbgMI); 547206083Srdivacky else { 548206083Srdivacky MachineBasicBlock::iterator Pos = MI; 549206083Srdivacky MIBB->insert(llvm::next(Pos), DbgMI); 550206083Srdivacky } 551205218Srdivacky } 552206083Srdivacky LastOrder = Order; 553206083Srdivacky LastMI = MI; 554206083Srdivacky } 555206083Srdivacky // Add trailing DbgValue's before the terminator. FIXME: May want to add 556206083Srdivacky // some of them before one or more conditional branches? 557206083Srdivacky while (DI != DE) { 558206083Srdivacky MachineBasicBlock *InsertBB = Emitter.getBlock(); 559206083Srdivacky MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator(); 560206083Srdivacky if (!(*DI)->isInvalidated()) { 561206083Srdivacky MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, InsertBB, VRBaseMap, EM); 562206083Srdivacky InsertBB->insert(Pos, DbgMI); 563206083Srdivacky } 564206083Srdivacky ++DI; 565206083Srdivacky } 566198090Srdivacky } 567198090Srdivacky 568198090Srdivacky BB = Emitter.getBlock(); 569198090Srdivacky InsertPos = Emitter.getInsertPos(); 570198090Srdivacky return BB; 571198090Srdivacky} 572