RegAllocPBQP.cpp revision 261991
1238438Sdteske//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===// 2238438Sdteske// 3240684Sdteske// The LLVM Compiler Infrastructure 4238438Sdteske// 5238438Sdteske// This file is distributed under the University of Illinois Open Source 6238438Sdteske// License. See LICENSE.TXT for details. 7238438Sdteske// 8238438Sdteske//===----------------------------------------------------------------------===// 9301973Sdteske// 10301973Sdteske// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based 11238438Sdteske// register allocator for LLVM. This allocator works by constructing a PBQP 12238438Sdteske// problem representing the register allocation problem under consideration, 13// solving this using a PBQP solver, and mapping the solution back to a 14// register assignment. If any variables are selected for spilling then spill 15// code is inserted and the process repeated. 16// 17// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned 18// for register allocation. For more information on PBQP for register 19// allocation, see the following papers: 20// 21// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with 22// PBQP. In Proceedings of the 7th Joint Modular Languages Conference 23// (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361. 24// 25// (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular 26// architectures. In Proceedings of the Joint Conference on Languages, 27// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York, 28// NY, USA, 139-148. 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "regalloc" 33 34#include "llvm/CodeGen/RegAllocPBQP.h" 35#include "RegisterCoalescer.h" 36#include "Spiller.h" 37#include "llvm/ADT/OwningPtr.h" 38#include "llvm/Analysis/AliasAnalysis.h" 39#include "llvm/CodeGen/CalcSpillWeights.h" 40#include "llvm/CodeGen/LiveIntervalAnalysis.h" 41#include "llvm/CodeGen/LiveRangeEdit.h" 42#include "llvm/CodeGen/LiveStackAnalysis.h" 43#include "llvm/CodeGen/MachineBlockFrequencyInfo.h" 44#include "llvm/CodeGen/MachineDominators.h" 45#include "llvm/CodeGen/MachineFunctionPass.h" 46#include "llvm/CodeGen/MachineLoopInfo.h" 47#include "llvm/CodeGen/MachineRegisterInfo.h" 48#include "llvm/CodeGen/PBQP/Graph.h" 49#include "llvm/CodeGen/PBQP/HeuristicSolver.h" 50#include "llvm/CodeGen/PBQP/Heuristics/Briggs.h" 51#include "llvm/CodeGen/RegAllocRegistry.h" 52#include "llvm/CodeGen/VirtRegMap.h" 53#include "llvm/IR/Module.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/raw_ostream.h" 56#include "llvm/Target/TargetInstrInfo.h" 57#include "llvm/Target/TargetMachine.h" 58#include <limits> 59#include <memory> 60#include <set> 61#include <sstream> 62#include <vector> 63 64using namespace llvm; 65 66static RegisterRegAlloc 67registerPBQPRepAlloc("pbqp", "PBQP register allocator", 68 createDefaultPBQPRegisterAllocator); 69 70static cl::opt<bool> 71pbqpCoalescing("pbqp-coalescing", 72 cl::desc("Attempt coalescing during PBQP register allocation."), 73 cl::init(false), cl::Hidden); 74 75#ifndef NDEBUG 76static cl::opt<bool> 77pbqpDumpGraphs("pbqp-dump-graphs", 78 cl::desc("Dump graphs for each function/round in the compilation unit."), 79 cl::init(false), cl::Hidden); 80#endif 81 82namespace { 83 84/// 85/// PBQP based allocators solve the register allocation problem by mapping 86/// register allocation problems to Partitioned Boolean Quadratic 87/// Programming problems. 88class RegAllocPBQP : public MachineFunctionPass { 89public: 90 91 static char ID; 92 93 /// Construct a PBQP register allocator. 94 RegAllocPBQP(OwningPtr<PBQPBuilder> &b, char *cPassID=0) 95 : MachineFunctionPass(ID), builder(b.take()), customPassID(cPassID) { 96 initializeSlotIndexesPass(*PassRegistry::getPassRegistry()); 97 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry()); 98 initializeLiveStacksPass(*PassRegistry::getPassRegistry()); 99 initializeVirtRegMapPass(*PassRegistry::getPassRegistry()); 100 } 101 102 /// Return the pass name. 103 virtual const char* getPassName() const { 104 return "PBQP Register Allocator"; 105 } 106 107 /// PBQP analysis usage. 108 virtual void getAnalysisUsage(AnalysisUsage &au) const; 109 110 /// Perform register allocation 111 virtual bool runOnMachineFunction(MachineFunction &MF); 112 113private: 114 115 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap; 116 typedef std::vector<const LiveInterval*> Node2LIMap; 117 typedef std::vector<unsigned> AllowedSet; 118 typedef std::vector<AllowedSet> AllowedSetMap; 119 typedef std::pair<unsigned, unsigned> RegPair; 120 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap; 121 typedef std::set<unsigned> RegSet; 122 123 124 OwningPtr<PBQPBuilder> builder; 125 126 char *customPassID; 127 128 MachineFunction *mf; 129 const TargetMachine *tm; 130 const TargetRegisterInfo *tri; 131 const TargetInstrInfo *tii; 132 MachineRegisterInfo *mri; 133 const MachineBlockFrequencyInfo *mbfi; 134 135 OwningPtr<Spiller> spiller; 136 LiveIntervals *lis; 137 LiveStacks *lss; 138 VirtRegMap *vrm; 139 140 RegSet vregsToAlloc, emptyIntervalVRegs; 141 142 /// \brief Finds the initial set of vreg intervals to allocate. 143 void findVRegIntervalsToAlloc(); 144 145 /// \brief Given a solved PBQP problem maps this solution back to a register 146 /// assignment. 147 bool mapPBQPToRegAlloc(const PBQPRAProblem &problem, 148 const PBQP::Solution &solution); 149 150 /// \brief Postprocessing before final spilling. Sets basic block "live in" 151 /// variables. 152 void finalizeAlloc() const; 153 154}; 155 156char RegAllocPBQP::ID = 0; 157 158} // End anonymous namespace. 159 160unsigned PBQPRAProblem::getVRegForNode(PBQP::Graph::NodeId node) const { 161 Node2VReg::const_iterator vregItr = node2VReg.find(node); 162 assert(vregItr != node2VReg.end() && "No vreg for node."); 163 return vregItr->second; 164} 165 166PBQP::Graph::NodeId PBQPRAProblem::getNodeForVReg(unsigned vreg) const { 167 VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg); 168 assert(nodeItr != vreg2Node.end() && "No node for vreg."); 169 return nodeItr->second; 170 171} 172 173const PBQPRAProblem::AllowedSet& 174 PBQPRAProblem::getAllowedSet(unsigned vreg) const { 175 AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg); 176 assert(allowedSetItr != allowedSets.end() && "No pregs for vreg."); 177 const AllowedSet &allowedSet = allowedSetItr->second; 178 return allowedSet; 179} 180 181unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const { 182 assert(isPRegOption(vreg, option) && "Not a preg option."); 183 184 const AllowedSet& allowedSet = getAllowedSet(vreg); 185 assert(option <= allowedSet.size() && "Option outside allowed set."); 186 return allowedSet[option - 1]; 187} 188 189PBQPRAProblem *PBQPBuilder::build(MachineFunction *mf, const LiveIntervals *lis, 190 const MachineBlockFrequencyInfo *mbfi, 191 const RegSet &vregs) { 192 193 LiveIntervals *LIS = const_cast<LiveIntervals*>(lis); 194 MachineRegisterInfo *mri = &mf->getRegInfo(); 195 const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo(); 196 197 OwningPtr<PBQPRAProblem> p(new PBQPRAProblem()); 198 PBQP::Graph &g = p->getGraph(); 199 RegSet pregs; 200 201 // Collect the set of preg intervals, record that they're used in the MF. 202 for (unsigned Reg = 1, e = tri->getNumRegs(); Reg != e; ++Reg) { 203 if (mri->def_empty(Reg)) 204 continue; 205 pregs.insert(Reg); 206 mri->setPhysRegUsed(Reg); 207 } 208 209 // Iterate over vregs. 210 for (RegSet::const_iterator vregItr = vregs.begin(), vregEnd = vregs.end(); 211 vregItr != vregEnd; ++vregItr) { 212 unsigned vreg = *vregItr; 213 const TargetRegisterClass *trc = mri->getRegClass(vreg); 214 LiveInterval *vregLI = &LIS->getInterval(vreg); 215 216 // Record any overlaps with regmask operands. 217 BitVector regMaskOverlaps; 218 LIS->checkRegMaskInterference(*vregLI, regMaskOverlaps); 219 220 // Compute an initial allowed set for the current vreg. 221 typedef std::vector<unsigned> VRAllowed; 222 VRAllowed vrAllowed; 223 ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(*mf); 224 for (unsigned i = 0; i != rawOrder.size(); ++i) { 225 unsigned preg = rawOrder[i]; 226 if (mri->isReserved(preg)) 227 continue; 228 229 // vregLI crosses a regmask operand that clobbers preg. 230 if (!regMaskOverlaps.empty() && !regMaskOverlaps.test(preg)) 231 continue; 232 233 // vregLI overlaps fixed regunit interference. 234 bool Interference = false; 235 for (MCRegUnitIterator Units(preg, tri); Units.isValid(); ++Units) { 236 if (vregLI->overlaps(LIS->getRegUnit(*Units))) { 237 Interference = true; 238 break; 239 } 240 } 241 if (Interference) 242 continue; 243 244 // preg is usable for this virtual register. 245 vrAllowed.push_back(preg); 246 } 247 248 // Construct the node. 249 PBQP::Graph::NodeId node = 250 g.addNode(PBQP::Vector(vrAllowed.size() + 1, 0)); 251 252 // Record the mapping and allowed set in the problem. 253 p->recordVReg(vreg, node, vrAllowed.begin(), vrAllowed.end()); 254 255 PBQP::PBQPNum spillCost = (vregLI->weight != 0.0) ? 256 vregLI->weight : std::numeric_limits<PBQP::PBQPNum>::min(); 257 258 addSpillCosts(g.getNodeCosts(node), spillCost); 259 } 260 261 for (RegSet::const_iterator vr1Itr = vregs.begin(), vrEnd = vregs.end(); 262 vr1Itr != vrEnd; ++vr1Itr) { 263 unsigned vr1 = *vr1Itr; 264 const LiveInterval &l1 = lis->getInterval(vr1); 265 const PBQPRAProblem::AllowedSet &vr1Allowed = p->getAllowedSet(vr1); 266 267 for (RegSet::const_iterator vr2Itr = llvm::next(vr1Itr); 268 vr2Itr != vrEnd; ++vr2Itr) { 269 unsigned vr2 = *vr2Itr; 270 const LiveInterval &l2 = lis->getInterval(vr2); 271 const PBQPRAProblem::AllowedSet &vr2Allowed = p->getAllowedSet(vr2); 272 273 assert(!l2.empty() && "Empty interval in vreg set?"); 274 if (l1.overlaps(l2)) { 275 PBQP::Graph::EdgeId edge = 276 g.addEdge(p->getNodeForVReg(vr1), p->getNodeForVReg(vr2), 277 PBQP::Matrix(vr1Allowed.size()+1, vr2Allowed.size()+1, 0)); 278 279 addInterferenceCosts(g.getEdgeCosts(edge), vr1Allowed, vr2Allowed, tri); 280 } 281 } 282 } 283 284 return p.take(); 285} 286 287void PBQPBuilder::addSpillCosts(PBQP::Vector &costVec, 288 PBQP::PBQPNum spillCost) { 289 costVec[0] = spillCost; 290} 291 292void PBQPBuilder::addInterferenceCosts( 293 PBQP::Matrix &costMat, 294 const PBQPRAProblem::AllowedSet &vr1Allowed, 295 const PBQPRAProblem::AllowedSet &vr2Allowed, 296 const TargetRegisterInfo *tri) { 297 assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch."); 298 assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch."); 299 300 for (unsigned i = 0; i != vr1Allowed.size(); ++i) { 301 unsigned preg1 = vr1Allowed[i]; 302 303 for (unsigned j = 0; j != vr2Allowed.size(); ++j) { 304 unsigned preg2 = vr2Allowed[j]; 305 306 if (tri->regsOverlap(preg1, preg2)) { 307 costMat[i + 1][j + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity(); 308 } 309 } 310 } 311} 312 313PBQPRAProblem *PBQPBuilderWithCoalescing::build(MachineFunction *mf, 314 const LiveIntervals *lis, 315 const MachineBlockFrequencyInfo *mbfi, 316 const RegSet &vregs) { 317 318 OwningPtr<PBQPRAProblem> p(PBQPBuilder::build(mf, lis, mbfi, vregs)); 319 PBQP::Graph &g = p->getGraph(); 320 321 const TargetMachine &tm = mf->getTarget(); 322 CoalescerPair cp(*tm.getRegisterInfo()); 323 324 // Scan the machine function and add a coalescing cost whenever CoalescerPair 325 // gives the Ok. 326 for (MachineFunction::const_iterator mbbItr = mf->begin(), 327 mbbEnd = mf->end(); 328 mbbItr != mbbEnd; ++mbbItr) { 329 const MachineBasicBlock *mbb = &*mbbItr; 330 331 for (MachineBasicBlock::const_iterator miItr = mbb->begin(), 332 miEnd = mbb->end(); 333 miItr != miEnd; ++miItr) { 334 const MachineInstr *mi = &*miItr; 335 336 if (!cp.setRegisters(mi)) { 337 continue; // Not coalescable. 338 } 339 340 if (cp.getSrcReg() == cp.getDstReg()) { 341 continue; // Already coalesced. 342 } 343 344 unsigned dst = cp.getDstReg(), 345 src = cp.getSrcReg(); 346 347 const float copyFactor = 0.5; // Cost of copy relative to load. Current 348 // value plucked randomly out of the air. 349 350 PBQP::PBQPNum cBenefit = 351 copyFactor * LiveIntervals::getSpillWeight(false, true, 352 mbfi->getBlockFreq(mbb)); 353 354 if (cp.isPhys()) { 355 if (!mf->getRegInfo().isAllocatable(dst)) { 356 continue; 357 } 358 359 const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src); 360 unsigned pregOpt = 0; 361 while (pregOpt < allowed.size() && allowed[pregOpt] != dst) { 362 ++pregOpt; 363 } 364 if (pregOpt < allowed.size()) { 365 ++pregOpt; // +1 to account for spill option. 366 PBQP::Graph::NodeId node = p->getNodeForVReg(src); 367 addPhysRegCoalesce(g.getNodeCosts(node), pregOpt, cBenefit); 368 } 369 } else { 370 const PBQPRAProblem::AllowedSet *allowed1 = &p->getAllowedSet(dst); 371 const PBQPRAProblem::AllowedSet *allowed2 = &p->getAllowedSet(src); 372 PBQP::Graph::NodeId node1 = p->getNodeForVReg(dst); 373 PBQP::Graph::NodeId node2 = p->getNodeForVReg(src); 374 PBQP::Graph::EdgeId edge = g.findEdge(node1, node2); 375 if (edge == g.invalidEdgeId()) { 376 edge = g.addEdge(node1, node2, PBQP::Matrix(allowed1->size() + 1, 377 allowed2->size() + 1, 378 0)); 379 } else { 380 if (g.getEdgeNode1(edge) == node2) { 381 std::swap(node1, node2); 382 std::swap(allowed1, allowed2); 383 } 384 } 385 386 addVirtRegCoalesce(g.getEdgeCosts(edge), *allowed1, *allowed2, 387 cBenefit); 388 } 389 } 390 } 391 392 return p.take(); 393} 394 395void PBQPBuilderWithCoalescing::addPhysRegCoalesce(PBQP::Vector &costVec, 396 unsigned pregOption, 397 PBQP::PBQPNum benefit) { 398 costVec[pregOption] += -benefit; 399} 400 401void PBQPBuilderWithCoalescing::addVirtRegCoalesce( 402 PBQP::Matrix &costMat, 403 const PBQPRAProblem::AllowedSet &vr1Allowed, 404 const PBQPRAProblem::AllowedSet &vr2Allowed, 405 PBQP::PBQPNum benefit) { 406 407 assert(costMat.getRows() == vr1Allowed.size() + 1 && "Size mismatch."); 408 assert(costMat.getCols() == vr2Allowed.size() + 1 && "Size mismatch."); 409 410 for (unsigned i = 0; i != vr1Allowed.size(); ++i) { 411 unsigned preg1 = vr1Allowed[i]; 412 for (unsigned j = 0; j != vr2Allowed.size(); ++j) { 413 unsigned preg2 = vr2Allowed[j]; 414 415 if (preg1 == preg2) { 416 costMat[i + 1][j + 1] += -benefit; 417 } 418 } 419 } 420} 421 422 423void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const { 424 au.setPreservesCFG(); 425 au.addRequired<AliasAnalysis>(); 426 au.addPreserved<AliasAnalysis>(); 427 au.addRequired<SlotIndexes>(); 428 au.addPreserved<SlotIndexes>(); 429 au.addRequired<LiveIntervals>(); 430 au.addPreserved<LiveIntervals>(); 431 //au.addRequiredID(SplitCriticalEdgesID); 432 if (customPassID) 433 au.addRequiredID(*customPassID); 434 au.addRequired<LiveStacks>(); 435 au.addPreserved<LiveStacks>(); 436 au.addRequired<MachineBlockFrequencyInfo>(); 437 au.addPreserved<MachineBlockFrequencyInfo>(); 438 au.addRequired<MachineLoopInfo>(); 439 au.addPreserved<MachineLoopInfo>(); 440 au.addRequired<MachineDominatorTree>(); 441 au.addPreserved<MachineDominatorTree>(); 442 au.addRequired<VirtRegMap>(); 443 au.addPreserved<VirtRegMap>(); 444 MachineFunctionPass::getAnalysisUsage(au); 445} 446 447void RegAllocPBQP::findVRegIntervalsToAlloc() { 448 449 // Iterate over all live ranges. 450 for (unsigned i = 0, e = mri->getNumVirtRegs(); i != e; ++i) { 451 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 452 if (mri->reg_nodbg_empty(Reg)) 453 continue; 454 LiveInterval *li = &lis->getInterval(Reg); 455 456 // If this live interval is non-empty we will use pbqp to allocate it. 457 // Empty intervals we allocate in a simple post-processing stage in 458 // finalizeAlloc. 459 if (!li->empty()) { 460 vregsToAlloc.insert(li->reg); 461 } else { 462 emptyIntervalVRegs.insert(li->reg); 463 } 464 } 465} 466 467bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem, 468 const PBQP::Solution &solution) { 469 // Set to true if we have any spills 470 bool anotherRoundNeeded = false; 471 472 // Clear the existing allocation. 473 vrm->clearAllVirt(); 474 475 const PBQP::Graph &g = problem.getGraph(); 476 // Iterate over the nodes mapping the PBQP solution to a register 477 // assignment. 478 for (PBQP::Graph::NodeItr nodeItr = g.nodesBegin(), 479 nodeEnd = g.nodesEnd(); 480 nodeItr != nodeEnd; ++nodeItr) { 481 unsigned vreg = problem.getVRegForNode(*nodeItr); 482 unsigned alloc = solution.getSelection(*nodeItr); 483 484 if (problem.isPRegOption(vreg, alloc)) { 485 unsigned preg = problem.getPRegForOption(vreg, alloc); 486 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> " 487 << tri->getName(preg) << "\n"); 488 assert(preg != 0 && "Invalid preg selected."); 489 vrm->assignVirt2Phys(vreg, preg); 490 } else if (problem.isSpillOption(vreg, alloc)) { 491 vregsToAlloc.erase(vreg); 492 SmallVector<unsigned, 8> newSpills; 493 LiveRangeEdit LRE(&lis->getInterval(vreg), newSpills, *mf, *lis, vrm); 494 spiller->spill(LRE); 495 496 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> SPILLED (Cost: " 497 << LRE.getParent().weight << ", New vregs: "); 498 499 // Copy any newly inserted live intervals into the list of regs to 500 // allocate. 501 for (LiveRangeEdit::iterator itr = LRE.begin(), end = LRE.end(); 502 itr != end; ++itr) { 503 LiveInterval &li = lis->getInterval(*itr); 504 assert(!li.empty() && "Empty spill range."); 505 DEBUG(dbgs() << PrintReg(li.reg, tri) << " "); 506 vregsToAlloc.insert(li.reg); 507 } 508 509 DEBUG(dbgs() << ")\n"); 510 511 // We need another round if spill intervals were added. 512 anotherRoundNeeded |= !LRE.empty(); 513 } else { 514 llvm_unreachable("Unknown allocation option."); 515 } 516 } 517 518 return !anotherRoundNeeded; 519} 520 521 522void RegAllocPBQP::finalizeAlloc() const { 523 // First allocate registers for the empty intervals. 524 for (RegSet::const_iterator 525 itr = emptyIntervalVRegs.begin(), end = emptyIntervalVRegs.end(); 526 itr != end; ++itr) { 527 LiveInterval *li = &lis->getInterval(*itr); 528 529 unsigned physReg = mri->getSimpleHint(li->reg); 530 531 if (physReg == 0) { 532 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 533 physReg = liRC->getRawAllocationOrder(*mf).front(); 534 } 535 536 vrm->assignVirt2Phys(li->reg, physReg); 537 } 538} 539 540bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) { 541 542 mf = &MF; 543 tm = &mf->getTarget(); 544 tri = tm->getRegisterInfo(); 545 tii = tm->getInstrInfo(); 546 mri = &mf->getRegInfo(); 547 548 lis = &getAnalysis<LiveIntervals>(); 549 lss = &getAnalysis<LiveStacks>(); 550 mbfi = &getAnalysis<MachineBlockFrequencyInfo>(); 551 552 calculateSpillWeightsAndHints(*lis, MF, getAnalysis<MachineLoopInfo>(), 553 *mbfi); 554 555 vrm = &getAnalysis<VirtRegMap>(); 556 spiller.reset(createInlineSpiller(*this, MF, *vrm)); 557 558 mri->freezeReservedRegs(MF); 559 560 DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getName() << "\n"); 561 562 // Allocator main loop: 563 // 564 // * Map current regalloc problem to a PBQP problem 565 // * Solve the PBQP problem 566 // * Map the solution back to a register allocation 567 // * Spill if necessary 568 // 569 // This process is continued till no more spills are generated. 570 571 // Find the vreg intervals in need of allocation. 572 findVRegIntervalsToAlloc(); 573 574#ifndef NDEBUG 575 const Function* func = mf->getFunction(); 576 std::string fqn = 577 func->getParent()->getModuleIdentifier() + "." + 578 func->getName().str(); 579#endif 580 581 // If there are non-empty intervals allocate them using pbqp. 582 if (!vregsToAlloc.empty()) { 583 584 bool pbqpAllocComplete = false; 585 unsigned round = 0; 586 587 while (!pbqpAllocComplete) { 588 DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n"); 589 590 OwningPtr<PBQPRAProblem> problem( 591 builder->build(mf, lis, mbfi, vregsToAlloc)); 592 593#ifndef NDEBUG 594 if (pbqpDumpGraphs) { 595 std::ostringstream rs; 596 rs << round; 597 std::string graphFileName(fqn + "." + rs.str() + ".pbqpgraph"); 598 std::string tmp; 599 raw_fd_ostream os(graphFileName.c_str(), tmp); 600 DEBUG(dbgs() << "Dumping graph for round " << round << " to \"" 601 << graphFileName << "\"\n"); 602 problem->getGraph().dump(os); 603 } 604#endif 605 606 PBQP::Solution solution = 607 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve( 608 problem->getGraph()); 609 610 pbqpAllocComplete = mapPBQPToRegAlloc(*problem, solution); 611 612 ++round; 613 } 614 } 615 616 // Finalise allocation, allocate empty ranges. 617 finalizeAlloc(); 618 vregsToAlloc.clear(); 619 emptyIntervalVRegs.clear(); 620 621 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n"); 622 623 return true; 624} 625 626FunctionPass* llvm::createPBQPRegisterAllocator( 627 OwningPtr<PBQPBuilder> &builder, 628 char *customPassID) { 629 return new RegAllocPBQP(builder, customPassID); 630} 631 632FunctionPass* llvm::createDefaultPBQPRegisterAllocator() { 633 OwningPtr<PBQPBuilder> Builder; 634 if (pbqpCoalescing) 635 Builder.reset(new PBQPBuilderWithCoalescing()); 636 else 637 Builder.reset(new PBQPBuilder()); 638 return createPBQPRegisterAllocator(Builder); 639} 640 641#undef DEBUG_TYPE 642