RegAllocPBQP.cpp revision 198090
1//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based 11// register allocator for LLVM. This allocator works by constructing a PBQP 12// problem representing the register allocation problem under consideration, 13// solving this using a PBQP solver, and mapping the solution back to a 14// register assignment. If any variables are selected for spilling then spill 15// code is inserted and the process repeated. 16// 17// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned 18// for register allocation. For more information on PBQP for register 19// allocation, see the following papers: 20// 21// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with 22// PBQP. In Proceedings of the 7th Joint Modular Languages Conference 23// (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361. 24// 25// (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular 26// architectures. In Proceedings of the Joint Conference on Languages, 27// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York, 28// NY, USA, 139-148. 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "regalloc" 33 34#include "PBQP/HeuristicSolver.h" 35#include "PBQP/SimpleGraph.h" 36#include "PBQP/Heuristics/Briggs.h" 37#include "VirtRegMap.h" 38#include "VirtRegRewriter.h" 39#include "llvm/CodeGen/LiveIntervalAnalysis.h" 40#include "llvm/CodeGen/LiveStackAnalysis.h" 41#include "llvm/CodeGen/MachineFunctionPass.h" 42#include "llvm/CodeGen/MachineLoopInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/RegAllocRegistry.h" 45#include "llvm/CodeGen/RegisterCoalescer.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/raw_ostream.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetMachine.h" 50#include <limits> 51#include <map> 52#include <memory> 53#include <set> 54#include <vector> 55 56using namespace llvm; 57 58static RegisterRegAlloc 59registerPBQPRepAlloc("pbqp", "PBQP register allocator.", 60 llvm::createPBQPRegisterAllocator); 61 62static cl::opt<bool> 63pbqpCoalescing("pbqp-coalescing", 64 cl::desc("Attempt coalescing during PBQP register allocation."), 65 cl::init(false), cl::Hidden); 66 67namespace { 68 69 /// 70 /// PBQP based allocators solve the register allocation problem by mapping 71 /// register allocation problems to Partitioned Boolean Quadratic 72 /// Programming problems. 73 class VISIBILITY_HIDDEN PBQPRegAlloc : public MachineFunctionPass { 74 public: 75 76 static char ID; 77 78 /// Construct a PBQP register allocator. 79 PBQPRegAlloc() : MachineFunctionPass(&ID) {} 80 81 /// Return the pass name. 82 virtual const char* getPassName() const { 83 return "PBQP Register Allocator"; 84 } 85 86 /// PBQP analysis usage. 87 virtual void getAnalysisUsage(AnalysisUsage &au) const { 88 au.addRequired<LiveIntervals>(); 89 //au.addRequiredID(SplitCriticalEdgesID); 90 au.addRequired<RegisterCoalescer>(); 91 au.addRequired<LiveStacks>(); 92 au.addPreserved<LiveStacks>(); 93 au.addRequired<MachineLoopInfo>(); 94 au.addPreserved<MachineLoopInfo>(); 95 au.addRequired<VirtRegMap>(); 96 MachineFunctionPass::getAnalysisUsage(au); 97 } 98 99 /// Perform register allocation 100 virtual bool runOnMachineFunction(MachineFunction &MF); 101 102 private: 103 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap; 104 typedef std::vector<const LiveInterval*> Node2LIMap; 105 typedef std::vector<unsigned> AllowedSet; 106 typedef std::vector<AllowedSet> AllowedSetMap; 107 typedef std::set<unsigned> RegSet; 108 typedef std::pair<unsigned, unsigned> RegPair; 109 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap; 110 111 typedef std::set<LiveInterval*> LiveIntervalSet; 112 113 MachineFunction *mf; 114 const TargetMachine *tm; 115 const TargetRegisterInfo *tri; 116 const TargetInstrInfo *tii; 117 const MachineLoopInfo *loopInfo; 118 MachineRegisterInfo *mri; 119 120 LiveIntervals *lis; 121 LiveStacks *lss; 122 VirtRegMap *vrm; 123 124 LI2NodeMap li2Node; 125 Node2LIMap node2LI; 126 AllowedSetMap allowedSets; 127 LiveIntervalSet vregIntervalsToAlloc, 128 emptyVRegIntervals; 129 130 131 /// Builds a PBQP cost vector. 132 template <typename RegContainer> 133 PBQP::Vector buildCostVector(unsigned vReg, 134 const RegContainer &allowed, 135 const CoalesceMap &cealesces, 136 PBQP::PBQPNum spillCost) const; 137 138 /// \brief Builds a PBQP interference matrix. 139 /// 140 /// @return Either a pointer to a non-zero PBQP matrix representing the 141 /// allocation option costs, or a null pointer for a zero matrix. 142 /// 143 /// Expects allowed sets for two interfering LiveIntervals. These allowed 144 /// sets should contain only allocable registers from the LiveInterval's 145 /// register class, with any interfering pre-colored registers removed. 146 template <typename RegContainer> 147 PBQP::Matrix* buildInterferenceMatrix(const RegContainer &allowed1, 148 const RegContainer &allowed2) const; 149 150 /// 151 /// Expects allowed sets for two potentially coalescable LiveIntervals, 152 /// and an estimated benefit due to coalescing. The allowed sets should 153 /// contain only allocable registers from the LiveInterval's register 154 /// classes, with any interfering pre-colored registers removed. 155 template <typename RegContainer> 156 PBQP::Matrix* buildCoalescingMatrix(const RegContainer &allowed1, 157 const RegContainer &allowed2, 158 PBQP::PBQPNum cBenefit) const; 159 160 /// \brief Finds coalescing opportunities and returns them as a map. 161 /// 162 /// Any entries in the map are guaranteed coalescable, even if their 163 /// corresponding live intervals overlap. 164 CoalesceMap findCoalesces(); 165 166 /// \brief Finds the initial set of vreg intervals to allocate. 167 void findVRegIntervalsToAlloc(); 168 169 /// \brief Constructs a PBQP problem representation of the register 170 /// allocation problem for this function. 171 /// 172 /// @return a PBQP solver object for the register allocation problem. 173 PBQP::SimpleGraph constructPBQPProblem(); 174 175 /// \brief Adds a stack interval if the given live interval has been 176 /// spilled. Used to support stack slot coloring. 177 void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri); 178 179 /// \brief Given a solved PBQP problem maps this solution back to a register 180 /// assignment. 181 bool mapPBQPToRegAlloc(const PBQP::Solution &solution); 182 183 /// \brief Postprocessing before final spilling. Sets basic block "live in" 184 /// variables. 185 void finalizeAlloc() const; 186 187 }; 188 189 char PBQPRegAlloc::ID = 0; 190} 191 192 193template <typename RegContainer> 194PBQP::Vector PBQPRegAlloc::buildCostVector(unsigned vReg, 195 const RegContainer &allowed, 196 const CoalesceMap &coalesces, 197 PBQP::PBQPNum spillCost) const { 198 199 typedef typename RegContainer::const_iterator AllowedItr; 200 201 // Allocate vector. Additional element (0th) used for spill option 202 PBQP::Vector v(allowed.size() + 1, 0); 203 204 v[0] = spillCost; 205 206 // Iterate over the allowed registers inserting coalesce benefits if there 207 // are any. 208 unsigned ai = 0; 209 for (AllowedItr itr = allowed.begin(), end = allowed.end(); 210 itr != end; ++itr, ++ai) { 211 212 unsigned pReg = *itr; 213 214 CoalesceMap::const_iterator cmItr = 215 coalesces.find(RegPair(vReg, pReg)); 216 217 // No coalesce - on to the next preg. 218 if (cmItr == coalesces.end()) 219 continue; 220 221 // We have a coalesce - insert the benefit. 222 v[ai + 1] = -cmItr->second; 223 } 224 225 return v; 226} 227 228template <typename RegContainer> 229PBQP::Matrix* PBQPRegAlloc::buildInterferenceMatrix( 230 const RegContainer &allowed1, const RegContainer &allowed2) const { 231 232 typedef typename RegContainer::const_iterator RegContainerIterator; 233 234 // Construct a PBQP matrix representing the cost of allocation options. The 235 // rows and columns correspond to the allocation options for the two live 236 // intervals. Elements will be infinite where corresponding registers alias, 237 // since we cannot allocate aliasing registers to interfering live intervals. 238 // All other elements (non-aliasing combinations) will have zero cost. Note 239 // that the spill option (element 0,0) has zero cost, since we can allocate 240 // both intervals to memory safely (the cost for each individual allocation 241 // to memory is accounted for by the cost vectors for each live interval). 242 PBQP::Matrix *m = 243 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0); 244 245 // Assume this is a zero matrix until proven otherwise. Zero matrices occur 246 // between interfering live ranges with non-overlapping register sets (e.g. 247 // non-overlapping reg classes, or disjoint sets of allowed regs within the 248 // same class). The term "overlapping" is used advisedly: sets which do not 249 // intersect, but contain registers which alias, will have non-zero matrices. 250 // We optimize zero matrices away to improve solver speed. 251 bool isZeroMatrix = true; 252 253 254 // Row index. Starts at 1, since the 0th row is for the spill option, which 255 // is always zero. 256 unsigned ri = 1; 257 258 // Iterate over allowed sets, insert infinities where required. 259 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end(); 260 a1Itr != a1End; ++a1Itr) { 261 262 // Column index, starts at 1 as for row index. 263 unsigned ci = 1; 264 unsigned reg1 = *a1Itr; 265 266 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end(); 267 a2Itr != a2End; ++a2Itr) { 268 269 unsigned reg2 = *a2Itr; 270 271 // If the row/column regs are identical or alias insert an infinity. 272 if (tri->regsOverlap(reg1, reg2)) { 273 (*m)[ri][ci] = std::numeric_limits<PBQP::PBQPNum>::infinity(); 274 isZeroMatrix = false; 275 } 276 277 ++ci; 278 } 279 280 ++ri; 281 } 282 283 // If this turns out to be a zero matrix... 284 if (isZeroMatrix) { 285 // free it and return null. 286 delete m; 287 return 0; 288 } 289 290 // ...otherwise return the cost matrix. 291 return m; 292} 293 294template <typename RegContainer> 295PBQP::Matrix* PBQPRegAlloc::buildCoalescingMatrix( 296 const RegContainer &allowed1, const RegContainer &allowed2, 297 PBQP::PBQPNum cBenefit) const { 298 299 typedef typename RegContainer::const_iterator RegContainerIterator; 300 301 // Construct a PBQP Matrix representing the benefits of coalescing. As with 302 // interference matrices the rows and columns represent allowed registers 303 // for the LiveIntervals which are (potentially) to be coalesced. The amount 304 // -cBenefit will be placed in any element representing the same register 305 // for both intervals. 306 PBQP::Matrix *m = 307 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0); 308 309 // Reset costs to zero. 310 m->reset(0); 311 312 // Assume the matrix is zero till proven otherwise. Zero matrices will be 313 // optimized away as in the interference case. 314 bool isZeroMatrix = true; 315 316 // Row index. Starts at 1, since the 0th row is for the spill option, which 317 // is always zero. 318 unsigned ri = 1; 319 320 // Iterate over the allowed sets, insert coalescing benefits where 321 // appropriate. 322 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end(); 323 a1Itr != a1End; ++a1Itr) { 324 325 // Column index, starts at 1 as for row index. 326 unsigned ci = 1; 327 unsigned reg1 = *a1Itr; 328 329 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end(); 330 a2Itr != a2End; ++a2Itr) { 331 332 // If the row and column represent the same register insert a beneficial 333 // cost to preference this allocation - it would allow us to eliminate a 334 // move instruction. 335 if (reg1 == *a2Itr) { 336 (*m)[ri][ci] = -cBenefit; 337 isZeroMatrix = false; 338 } 339 340 ++ci; 341 } 342 343 ++ri; 344 } 345 346 // If this turns out to be a zero matrix... 347 if (isZeroMatrix) { 348 // ...free it and return null. 349 delete m; 350 return 0; 351 } 352 353 return m; 354} 355 356PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() { 357 358 typedef MachineFunction::const_iterator MFIterator; 359 typedef MachineBasicBlock::const_iterator MBBIterator; 360 typedef LiveInterval::const_vni_iterator VNIIterator; 361 362 CoalesceMap coalescesFound; 363 364 // To find coalesces we need to iterate over the function looking for 365 // copy instructions. 366 for (MFIterator bbItr = mf->begin(), bbEnd = mf->end(); 367 bbItr != bbEnd; ++bbItr) { 368 369 const MachineBasicBlock *mbb = &*bbItr; 370 371 for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end(); 372 iItr != iEnd; ++iItr) { 373 374 const MachineInstr *instr = &*iItr; 375 unsigned srcReg, dstReg, srcSubReg, dstSubReg; 376 377 // If this isn't a copy then continue to the next instruction. 378 if (!tii->isMoveInstr(*instr, srcReg, dstReg, srcSubReg, dstSubReg)) 379 continue; 380 381 // If the registers are already the same our job is nice and easy. 382 if (dstReg == srcReg) 383 continue; 384 385 bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg), 386 dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg); 387 388 // If both registers are physical then we can't coalesce. 389 if (srcRegIsPhysical && dstRegIsPhysical) 390 continue; 391 392 // If it's a copy that includes a virtual register but the source and 393 // destination classes differ then we can't coalesce, so continue with 394 // the next instruction. 395 const TargetRegisterClass *srcRegClass = srcRegIsPhysical ? 396 tri->getPhysicalRegisterRegClass(srcReg) : mri->getRegClass(srcReg); 397 398 const TargetRegisterClass *dstRegClass = dstRegIsPhysical ? 399 tri->getPhysicalRegisterRegClass(dstReg) : mri->getRegClass(dstReg); 400 401 if (srcRegClass != dstRegClass) 402 continue; 403 404 // We also need any physical regs to be allocable, coalescing with 405 // a non-allocable register is invalid. 406 if (srcRegIsPhysical) { 407 if (std::find(srcRegClass->allocation_order_begin(*mf), 408 srcRegClass->allocation_order_end(*mf), srcReg) == 409 srcRegClass->allocation_order_end(*mf)) 410 continue; 411 } 412 413 if (dstRegIsPhysical) { 414 if (std::find(dstRegClass->allocation_order_begin(*mf), 415 dstRegClass->allocation_order_end(*mf), dstReg) == 416 dstRegClass->allocation_order_end(*mf)) 417 continue; 418 } 419 420 // If we've made it here we have a copy with compatible register classes. 421 // We can probably coalesce, but we need to consider overlap. 422 const LiveInterval *srcLI = &lis->getInterval(srcReg), 423 *dstLI = &lis->getInterval(dstReg); 424 425 if (srcLI->overlaps(*dstLI)) { 426 // Even in the case of an overlap we might still be able to coalesce, 427 // but we need to make sure that no definition of either range occurs 428 // while the other range is live. 429 430 // Otherwise start by assuming we're ok. 431 bool badDef = false; 432 433 // Test all defs of the source range. 434 for (VNIIterator 435 vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end(); 436 vniItr != vniEnd; ++vniItr) { 437 438 // If we find a def that kills the coalescing opportunity then 439 // record it and break from the loop. 440 if (dstLI->liveAt((*vniItr)->def)) { 441 badDef = true; 442 break; 443 } 444 } 445 446 // If we have a bad def give up, continue to the next instruction. 447 if (badDef) 448 continue; 449 450 // Otherwise test definitions of the destination range. 451 for (VNIIterator 452 vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end(); 453 vniItr != vniEnd; ++vniItr) { 454 455 // We want to make sure we skip the copy instruction itself. 456 if ((*vniItr)->getCopy() == instr) 457 continue; 458 459 if (srcLI->liveAt((*vniItr)->def)) { 460 badDef = true; 461 break; 462 } 463 } 464 465 // As before a bad def we give up and continue to the next instr. 466 if (badDef) 467 continue; 468 } 469 470 // If we make it to here then either the ranges didn't overlap, or they 471 // did, but none of their definitions would prevent us from coalescing. 472 // We're good to go with the coalesce. 473 474 float cBenefit = powf(10.0f, loopInfo->getLoopDepth(mbb)) / 5.0; 475 476 coalescesFound[RegPair(srcReg, dstReg)] = cBenefit; 477 coalescesFound[RegPair(dstReg, srcReg)] = cBenefit; 478 } 479 480 } 481 482 return coalescesFound; 483} 484 485void PBQPRegAlloc::findVRegIntervalsToAlloc() { 486 487 // Iterate over all live ranges. 488 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); 489 itr != end; ++itr) { 490 491 // Ignore physical ones. 492 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) 493 continue; 494 495 LiveInterval *li = itr->second; 496 497 // If this live interval is non-empty we will use pbqp to allocate it. 498 // Empty intervals we allocate in a simple post-processing stage in 499 // finalizeAlloc. 500 if (!li->empty()) { 501 vregIntervalsToAlloc.insert(li); 502 } 503 else { 504 emptyVRegIntervals.insert(li); 505 } 506 } 507} 508 509PBQP::SimpleGraph PBQPRegAlloc::constructPBQPProblem() { 510 511 typedef std::vector<const LiveInterval*> LIVector; 512 typedef std::vector<unsigned> RegVector; 513 typedef std::vector<PBQP::SimpleGraph::NodeIterator> NodeVector; 514 515 // This will store the physical intervals for easy reference. 516 LIVector physIntervals; 517 518 // Start by clearing the old node <-> live interval mappings & allowed sets 519 li2Node.clear(); 520 node2LI.clear(); 521 allowedSets.clear(); 522 523 // Populate physIntervals, update preg use: 524 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); 525 itr != end; ++itr) { 526 527 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) { 528 physIntervals.push_back(itr->second); 529 mri->setPhysRegUsed(itr->second->reg); 530 } 531 } 532 533 // Iterate over vreg intervals, construct live interval <-> node number 534 // mappings. 535 for (LiveIntervalSet::const_iterator 536 itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end(); 537 itr != end; ++itr) { 538 const LiveInterval *li = *itr; 539 540 li2Node[li] = node2LI.size(); 541 node2LI.push_back(li); 542 } 543 544 // Get the set of potential coalesces. 545 CoalesceMap coalesces; 546 547 if (pbqpCoalescing) { 548 coalesces = findCoalesces(); 549 } 550 551 // Construct a PBQP solver for this problem 552 PBQP::SimpleGraph problem; 553 NodeVector problemNodes(vregIntervalsToAlloc.size()); 554 555 // Resize allowedSets container appropriately. 556 allowedSets.resize(vregIntervalsToAlloc.size()); 557 558 // Iterate over virtual register intervals to compute allowed sets... 559 for (unsigned node = 0; node < node2LI.size(); ++node) { 560 561 // Grab pointers to the interval and its register class. 562 const LiveInterval *li = node2LI[node]; 563 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 564 565 // Start by assuming all allocable registers in the class are allowed... 566 RegVector liAllowed(liRC->allocation_order_begin(*mf), 567 liRC->allocation_order_end(*mf)); 568 569 // Eliminate the physical registers which overlap with this range, along 570 // with all their aliases. 571 for (LIVector::iterator pItr = physIntervals.begin(), 572 pEnd = physIntervals.end(); pItr != pEnd; ++pItr) { 573 574 if (!li->overlaps(**pItr)) 575 continue; 576 577 unsigned pReg = (*pItr)->reg; 578 579 // If we get here then the live intervals overlap, but we're still ok 580 // if they're coalescable. 581 if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end()) 582 continue; 583 584 // If we get here then we have a genuine exclusion. 585 586 // Remove the overlapping reg... 587 RegVector::iterator eraseItr = 588 std::find(liAllowed.begin(), liAllowed.end(), pReg); 589 590 if (eraseItr != liAllowed.end()) 591 liAllowed.erase(eraseItr); 592 593 const unsigned *aliasItr = tri->getAliasSet(pReg); 594 595 if (aliasItr != 0) { 596 // ...and its aliases. 597 for (; *aliasItr != 0; ++aliasItr) { 598 RegVector::iterator eraseItr = 599 std::find(liAllowed.begin(), liAllowed.end(), *aliasItr); 600 601 if (eraseItr != liAllowed.end()) { 602 liAllowed.erase(eraseItr); 603 } 604 } 605 } 606 } 607 608 // Copy the allowed set into a member vector for use when constructing cost 609 // vectors & matrices, and mapping PBQP solutions back to assignments. 610 allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end()); 611 612 // Set the spill cost to the interval weight, or epsilon if the 613 // interval weight is zero 614 PBQP::PBQPNum spillCost = (li->weight != 0.0) ? 615 li->weight : std::numeric_limits<PBQP::PBQPNum>::min(); 616 617 // Build a cost vector for this interval. 618 problemNodes[node] = 619 problem.addNode( 620 buildCostVector(li->reg, allowedSets[node], coalesces, spillCost)); 621 622 } 623 624 625 // Now add the cost matrices... 626 for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) { 627 const LiveInterval *li = node2LI[node1]; 628 629 // Test for live range overlaps and insert interference matrices. 630 for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) { 631 const LiveInterval *li2 = node2LI[node2]; 632 633 CoalesceMap::const_iterator cmItr = 634 coalesces.find(RegPair(li->reg, li2->reg)); 635 636 PBQP::Matrix *m = 0; 637 638 if (cmItr != coalesces.end()) { 639 m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2], 640 cmItr->second); 641 } 642 else if (li->overlaps(*li2)) { 643 m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]); 644 } 645 646 if (m != 0) { 647 problem.addEdge(problemNodes[node1], 648 problemNodes[node2], 649 *m); 650 651 delete m; 652 } 653 } 654 } 655 656 problem.assignNodeIDs(); 657 658 assert(problem.getNumNodes() == allowedSets.size()); 659 for (unsigned i = 0; i < allowedSets.size(); ++i) { 660 assert(problem.getNodeItr(i) == problemNodes[i]); 661 } 662/* 663 std::cerr << "Allocating for " << problem.getNumNodes() << " nodes, " 664 << problem.getNumEdges() << " edges.\n"; 665 666 problem.printDot(std::cerr); 667*/ 668 // We're done, PBQP problem constructed - return it. 669 return problem; 670} 671 672void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled, 673 MachineRegisterInfo* mri) { 674 int stackSlot = vrm->getStackSlot(spilled->reg); 675 676 if (stackSlot == VirtRegMap::NO_STACK_SLOT) 677 return; 678 679 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg); 680 LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC); 681 682 VNInfo *vni; 683 if (stackInterval.getNumValNums() != 0) 684 vni = stackInterval.getValNumInfo(0); 685 else 686 vni = stackInterval.getNextValue( 687 LiveIndex(), 0, false, lss->getVNInfoAllocator()); 688 689 LiveInterval &rhsInterval = lis->getInterval(spilled->reg); 690 stackInterval.MergeRangesInAsValue(rhsInterval, vni); 691} 692 693bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) { 694 // Set to true if we have any spills 695 bool anotherRoundNeeded = false; 696 697 // Clear the existing allocation. 698 vrm->clearAllVirt(); 699 700 // Iterate over the nodes mapping the PBQP solution to a register assignment. 701 for (unsigned node = 0; node < node2LI.size(); ++node) { 702 unsigned virtReg = node2LI[node]->reg, 703 allocSelection = solution.getSelection(node); 704 705 706 // If the PBQP solution is non-zero it's a physical register... 707 if (allocSelection != 0) { 708 // Get the physical reg, subtracting 1 to account for the spill option. 709 unsigned physReg = allowedSets[node][allocSelection - 1]; 710 711 DEBUG(errs() << "VREG " << virtReg << " -> " 712 << tri->getName(physReg) << "\n"); 713 714 assert(physReg != 0); 715 716 // Add to the virt reg map and update the used phys regs. 717 vrm->assignVirt2Phys(virtReg, physReg); 718 } 719 // ...Otherwise it's a spill. 720 else { 721 722 // Make sure we ignore this virtual reg on the next round 723 // of allocation 724 vregIntervalsToAlloc.erase(&lis->getInterval(virtReg)); 725 726 // Insert spill ranges for this live range 727 const LiveInterval *spillInterval = node2LI[node]; 728 double oldSpillWeight = spillInterval->weight; 729 SmallVector<LiveInterval*, 8> spillIs; 730 std::vector<LiveInterval*> newSpills = 731 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm); 732 addStackInterval(spillInterval, mri); 733 734 (void) oldSpillWeight; 735 DEBUG(errs() << "VREG " << virtReg << " -> SPILLED (Cost: " 736 << oldSpillWeight << ", New vregs: "); 737 738 // Copy any newly inserted live intervals into the list of regs to 739 // allocate. 740 for (std::vector<LiveInterval*>::const_iterator 741 itr = newSpills.begin(), end = newSpills.end(); 742 itr != end; ++itr) { 743 744 assert(!(*itr)->empty() && "Empty spill range."); 745 746 DEBUG(errs() << (*itr)->reg << " "); 747 748 vregIntervalsToAlloc.insert(*itr); 749 } 750 751 DEBUG(errs() << ")\n"); 752 753 // We need another round if spill intervals were added. 754 anotherRoundNeeded |= !newSpills.empty(); 755 } 756 } 757 758 return !anotherRoundNeeded; 759} 760 761void PBQPRegAlloc::finalizeAlloc() const { 762 typedef LiveIntervals::iterator LIIterator; 763 typedef LiveInterval::Ranges::const_iterator LRIterator; 764 765 // First allocate registers for the empty intervals. 766 for (LiveIntervalSet::const_iterator 767 itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end(); 768 itr != end; ++itr) { 769 LiveInterval *li = *itr; 770 771 unsigned physReg = vrm->getRegAllocPref(li->reg); 772 773 if (physReg == 0) { 774 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 775 physReg = *liRC->allocation_order_begin(*mf); 776 } 777 778 vrm->assignVirt2Phys(li->reg, physReg); 779 } 780 781 // Finally iterate over the basic blocks to compute and set the live-in sets. 782 SmallVector<MachineBasicBlock*, 8> liveInMBBs; 783 MachineBasicBlock *entryMBB = &*mf->begin(); 784 785 for (LIIterator liItr = lis->begin(), liEnd = lis->end(); 786 liItr != liEnd; ++liItr) { 787 788 const LiveInterval *li = liItr->second; 789 unsigned reg = 0; 790 791 // Get the physical register for this interval 792 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) { 793 reg = li->reg; 794 } 795 else if (vrm->isAssignedReg(li->reg)) { 796 reg = vrm->getPhys(li->reg); 797 } 798 else { 799 // Ranges which are assigned a stack slot only are ignored. 800 continue; 801 } 802 803 if (reg == 0) { 804 // Filter out zero regs - they're for intervals that were spilled. 805 continue; 806 } 807 808 // Iterate over the ranges of the current interval... 809 for (LRIterator lrItr = li->begin(), lrEnd = li->end(); 810 lrItr != lrEnd; ++lrItr) { 811 812 // Find the set of basic blocks which this range is live into... 813 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) { 814 // And add the physreg for this interval to their live-in sets. 815 for (unsigned i = 0; i < liveInMBBs.size(); ++i) { 816 if (liveInMBBs[i] != entryMBB) { 817 if (!liveInMBBs[i]->isLiveIn(reg)) { 818 liveInMBBs[i]->addLiveIn(reg); 819 } 820 } 821 } 822 liveInMBBs.clear(); 823 } 824 } 825 } 826 827} 828 829bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) { 830 831 mf = &MF; 832 tm = &mf->getTarget(); 833 tri = tm->getRegisterInfo(); 834 tii = tm->getInstrInfo(); 835 mri = &mf->getRegInfo(); 836 837 lis = &getAnalysis<LiveIntervals>(); 838 lss = &getAnalysis<LiveStacks>(); 839 loopInfo = &getAnalysis<MachineLoopInfo>(); 840 841 vrm = &getAnalysis<VirtRegMap>(); 842 843 DEBUG(errs() << "PBQP2 Register Allocating for " << mf->getFunction()->getName() << "\n"); 844 845 // Allocator main loop: 846 // 847 // * Map current regalloc problem to a PBQP problem 848 // * Solve the PBQP problem 849 // * Map the solution back to a register allocation 850 // * Spill if necessary 851 // 852 // This process is continued till no more spills are generated. 853 854 // Find the vreg intervals in need of allocation. 855 findVRegIntervalsToAlloc(); 856 857 // If there aren't any then we're done here. 858 if (vregIntervalsToAlloc.empty() && emptyVRegIntervals.empty()) 859 return true; 860 861 // If there are non-empty intervals allocate them using pbqp. 862 if (!vregIntervalsToAlloc.empty()) { 863 864 bool pbqpAllocComplete = false; 865 unsigned round = 0; 866 867 while (!pbqpAllocComplete) { 868 DEBUG(errs() << " PBQP Regalloc round " << round << ":\n"); 869 870 PBQP::SimpleGraph problem = constructPBQPProblem(); 871 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs> solver; 872 problem.assignNodeIDs(); 873 PBQP::Solution solution = solver.solve(problem); 874 875 pbqpAllocComplete = mapPBQPToRegAlloc(solution); 876 877 ++round; 878 } 879 } 880 881 // Finalise allocation, allocate empty ranges. 882 finalizeAlloc(); 883 884 vregIntervalsToAlloc.clear(); 885 emptyVRegIntervals.clear(); 886 li2Node.clear(); 887 node2LI.clear(); 888 allowedSets.clear(); 889 890 DEBUG(errs() << "Post alloc VirtRegMap:\n" << *vrm << "\n"); 891 892 // Run rewriter 893 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter()); 894 895 rewriter->runOnMachineFunction(*mf, *vrm, lis); 896 897 return true; 898} 899 900FunctionPass* llvm::createPBQPRegisterAllocator() { 901 return new PBQPRegAlloc(); 902} 903 904 905#undef DEBUG_TYPE 906