ProcessImplicitDefs.cpp revision 218893 
1//===---------------------- ProcessImplicitDefs.cpp -----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#define DEBUG_TYPE "processimplicitdefs"
11
12#include "llvm/CodeGen/ProcessImplicitDefs.h"
13
14#include "llvm/ADT/DepthFirstIterator.h"
15#include "llvm/ADT/SmallSet.h"
16#include "llvm/Analysis/AliasAnalysis.h"
17#include "llvm/CodeGen/LiveVariables.h"
18#include "llvm/CodeGen/MachineInstr.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/Passes.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Target/TargetInstrInfo.h"
23#include "llvm/Target/TargetRegisterInfo.h"
24
25
26using namespace llvm;
27
28char ProcessImplicitDefs::ID = 0;
29INITIALIZE_PASS_BEGIN(ProcessImplicitDefs, "processimpdefs",
30                "Process Implicit Definitions", false, false)
31INITIALIZE_PASS_DEPENDENCY(LiveVariables)
32INITIALIZE_PASS_END(ProcessImplicitDefs, "processimpdefs",
33                "Process Implicit Definitions", false, false)
34
35void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
36  AU.setPreservesCFG();
37  AU.addPreserved<AliasAnalysis>();
38  AU.addPreserved<LiveVariables>();
39  AU.addRequired<LiveVariables>();
40  AU.addPreservedID(MachineLoopInfoID);
41  AU.addPreservedID(MachineDominatorsID);
42  AU.addPreservedID(TwoAddressInstructionPassID);
43  AU.addPreservedID(PHIEliminationID);
44  MachineFunctionPass::getAnalysisUsage(AU);
45}
46
47bool
48ProcessImplicitDefs::CanTurnIntoImplicitDef(MachineInstr *MI,
49                                            unsigned Reg, unsigned OpIdx,
50                                            const TargetInstrInfo *tii_,
51                                            SmallSet<unsigned, 8> &ImpDefRegs) {
52  switch(OpIdx) {
53  case 1:
54    return MI->isCopy() && (MI->getOperand(0).getSubReg() == 0 ||
55                            ImpDefRegs.count(MI->getOperand(0).getReg()));
56  case 2:
57    return MI->isSubregToReg() && (MI->getOperand(0).getSubReg() == 0 ||
58                                  ImpDefRegs.count(MI->getOperand(0).getReg()));
59  default: return false;
60  }
61}
62
63static bool isUndefCopy(MachineInstr *MI, unsigned Reg,
64                        const TargetInstrInfo *tii_,
65                        SmallSet<unsigned, 8> &ImpDefRegs) {
66  if (MI->isCopy()) {
67    MachineOperand &MO0 = MI->getOperand(0);
68    MachineOperand &MO1 = MI->getOperand(1);
69    if (MO1.getReg() != Reg)
70      return false;
71    if (!MO0.getSubReg() || ImpDefRegs.count(MO0.getReg()))
72      return true;
73    return false;
74  }
75  return false;
76}
77
78/// processImplicitDefs - Process IMPLICIT_DEF instructions and make sure
79/// there is one implicit_def for each use. Add isUndef marker to
80/// implicit_def defs and their uses.
81bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
82
83  DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
84               << "********** Function: "
85               << ((Value*)fn.getFunction())->getName() << '\n');
86
87  bool Changed = false;
88
89  const TargetInstrInfo *tii_ = fn.getTarget().getInstrInfo();
90  const TargetRegisterInfo *tri_ = fn.getTarget().getRegisterInfo();
91  MachineRegisterInfo *mri_ = &fn.getRegInfo();
92
93  LiveVariables *lv_ = &getAnalysis<LiveVariables>();
94
95  SmallSet<unsigned, 8> ImpDefRegs;
96  SmallVector<MachineInstr*, 8> ImpDefMIs;
97  SmallVector<MachineInstr*, 4> RUses;
98  SmallPtrSet<MachineBasicBlock*,16> Visited;
99  SmallPtrSet<MachineInstr*, 8> ModInsts;
100
101  MachineBasicBlock *Entry = fn.begin();
102  for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
103         DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
104       DFI != E; ++DFI) {
105    MachineBasicBlock *MBB = *DFI;
106    for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
107         I != E; ) {
108      MachineInstr *MI = &*I;
109      ++I;
110      if (MI->isImplicitDef()) {
111        if (MI->getOperand(0).getSubReg())
112          continue;
113        unsigned Reg = MI->getOperand(0).getReg();
114        ImpDefRegs.insert(Reg);
115        if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
116          for (const unsigned *SS = tri_->getSubRegisters(Reg); *SS; ++SS)
117            ImpDefRegs.insert(*SS);
118        }
119        ImpDefMIs.push_back(MI);
120        continue;
121      }
122
123      // Eliminate %reg1032:sub<def> = COPY undef.
124      if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
125        MachineOperand &MO = MI->getOperand(1);
126        if (MO.isUndef() || ImpDefRegs.count(MO.getReg())) {
127          if (MO.isKill()) {
128            LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
129            vi.removeKill(MI);
130          }
131          MI->eraseFromParent();
132          Changed = true;
133          continue;
134        }
135      }
136
137      bool ChangedToImpDef = false;
138      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
139        MachineOperand& MO = MI->getOperand(i);
140        if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef())
141          continue;
142        unsigned Reg = MO.getReg();
143        if (!Reg)
144          continue;
145        if (!ImpDefRegs.count(Reg))
146          continue;
147        // Use is a copy, just turn it into an implicit_def.
148        if (CanTurnIntoImplicitDef(MI, Reg, i, tii_, ImpDefRegs)) {
149          bool isKill = MO.isKill();
150          MI->setDesc(tii_->get(TargetOpcode::IMPLICIT_DEF));
151          for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
152            MI->RemoveOperand(j);
153          if (isKill) {
154            ImpDefRegs.erase(Reg);
155            LiveVariables::VarInfo& vi = lv_->getVarInfo(Reg);
156            vi.removeKill(MI);
157          }
158          ChangedToImpDef = true;
159          Changed = true;
160          break;
161        }
162
163        Changed = true;
164        MO.setIsUndef();
165        // This is a partial register redef of an implicit def.
166        // Make sure the whole register is defined by the instruction.
167        if (MO.isDef()) {
168          MI->addRegisterDefined(Reg);
169          continue;
170        }
171        if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
172          // Make sure other uses of
173          for (unsigned j = i+1; j != e; ++j) {
174            MachineOperand &MOJ = MI->getOperand(j);
175            if (MOJ.isReg() && MOJ.isUse() && MOJ.getReg() == Reg)
176              MOJ.setIsUndef();
177          }
178          ImpDefRegs.erase(Reg);
179        }
180      }
181
182      if (ChangedToImpDef) {
183        // Backtrack to process this new implicit_def.
184        --I;
185      } else {
186        for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
187          MachineOperand& MO = MI->getOperand(i);
188          if (!MO.isReg() || !MO.isDef())
189            continue;
190          ImpDefRegs.erase(MO.getReg());
191        }
192      }
193    }
194
195    // Any outstanding liveout implicit_def's?
196    for (unsigned i = 0, e = ImpDefMIs.size(); i != e; ++i) {
197      MachineInstr *MI = ImpDefMIs[i];
198      unsigned Reg = MI->getOperand(0).getReg();
199      if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
200          !ImpDefRegs.count(Reg)) {
201        // Delete all "local" implicit_def's. That include those which define
202        // physical registers since they cannot be liveout.
203        MI->eraseFromParent();
204        Changed = true;
205        continue;
206      }
207
208      // If there are multiple defs of the same register and at least one
209      // is not an implicit_def, do not insert implicit_def's before the
210      // uses.
211      bool Skip = false;
212      SmallVector<MachineInstr*, 4> DeadImpDefs;
213      for (MachineRegisterInfo::def_iterator DI = mri_->def_begin(Reg),
214             DE = mri_->def_end(); DI != DE; ++DI) {
215        MachineInstr *DeadImpDef = &*DI;
216        if (!DeadImpDef->isImplicitDef()) {
217          Skip = true;
218          break;
219        }
220        DeadImpDefs.push_back(DeadImpDef);
221      }
222      if (Skip)
223        continue;
224
225      // The only implicit_def which we want to keep are those that are live
226      // out of its block.
227      for (unsigned j = 0, ee = DeadImpDefs.size(); j != ee; ++j)
228        DeadImpDefs[j]->eraseFromParent();
229      Changed = true;
230
231      // Process each use instruction once.
232      for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
233             UE = mri_->use_end(); UI != UE; ++UI) {
234        if (UI.getOperand().isUndef())
235          continue;
236        MachineInstr *RMI = &*UI;
237        if (ModInsts.insert(RMI))
238          RUses.push_back(RMI);
239      }
240
241      for (unsigned i = 0, e = RUses.size(); i != e; ++i) {
242        MachineInstr *RMI = RUses[i];
243
244        // Turn a copy use into an implicit_def.
245        if (isUndefCopy(RMI, Reg, tii_, ImpDefRegs)) {
246          RMI->setDesc(tii_->get(TargetOpcode::IMPLICIT_DEF));
247
248          bool isKill = false;
249          SmallVector<unsigned, 4> Ops;
250          for (unsigned j = 0, ee = RMI->getNumOperands(); j != ee; ++j) {
251            MachineOperand &RRMO = RMI->getOperand(j);
252            if (RRMO.isReg() && RRMO.getReg() == Reg) {
253              Ops.push_back(j);
254              if (RRMO.isKill())
255                isKill = true;
256            }
257          }
258          // Leave the other operands along.
259          for (unsigned j = 0, ee = Ops.size(); j != ee; ++j) {
260            unsigned OpIdx = Ops[j];
261            RMI->RemoveOperand(OpIdx-j);
262          }
263
264          // Update LiveVariables varinfo if the instruction is a kill.
265          if (isKill) {
266            LiveVariables::VarInfo& vi = lv_->getVarInfo(Reg);
267            vi.removeKill(RMI);
268          }
269          continue;
270        }
271
272        // Replace Reg with a new vreg that's marked implicit.
273        const TargetRegisterClass* RC = mri_->getRegClass(Reg);
274        unsigned NewVReg = mri_->createVirtualRegister(RC);
275        bool isKill = true;
276        for (unsigned j = 0, ee = RMI->getNumOperands(); j != ee; ++j) {
277          MachineOperand &RRMO = RMI->getOperand(j);
278          if (RRMO.isReg() && RRMO.getReg() == Reg) {
279            RRMO.setReg(NewVReg);
280            RRMO.setIsUndef();
281            if (isKill) {
282              // Only the first operand of NewVReg is marked kill.
283              RRMO.setIsKill();
284              isKill = false;
285            }
286          }
287        }
288      }
289      RUses.clear();
290      ModInsts.clear();
291    }
292    ImpDefRegs.clear();
293    ImpDefMIs.clear();
294  }
295
296  return Changed;
297}
298
299