1193323Sed//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2218893Sdim// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7218893Sdim// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines the target-independent interfaces which should be 11193323Sed// implemented by each target which is using a TableGen based code generator. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed// Include all information about LLVM intrinsics. 16249423Sdiminclude "llvm/IR/Intrinsics.td" 17193323Sed 18193323Sed//===----------------------------------------------------------------------===// 19193323Sed// Register file description - These classes are used to fill in the target 20193323Sed// description classes. 21193323Sed 22193323Sedclass RegisterClass; // Forward def 23193323Sed 24208599Srdivacky// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25261991Sdimclass SubRegIndex<int size, int offset = 0> { 26208599Srdivacky string Namespace = ""; 27234353Sdim 28261991Sdim // Size - Size (in bits) of the sub-registers represented by this index. 29261991Sdim int Size = size; 30261991Sdim 31261991Sdim // Offset - Offset of the first bit that is part of this sub-register index. 32261991Sdim // Set it to -1 if the same index is used to represent sub-registers that can 33261991Sdim // be at different offsets (for example when using an index to access an 34261991Sdim // element in a register tuple). 35261991Sdim int Offset = offset; 36261991Sdim 37234353Sdim // ComposedOf - A list of two SubRegIndex instances, [A, B]. 38234353Sdim // This indicates that this SubRegIndex is the result of composing A and B. 39261991Sdim // See ComposedSubRegIndex. 40261991Sdim list<SubRegIndex> ComposedOf = []; 41239462Sdim 42239462Sdim // CoveringSubRegIndices - A list of two or more sub-register indexes that 43239462Sdim // cover this sub-register. 44239462Sdim // 45239462Sdim // This field should normally be left blank as TableGen can infer it. 46239462Sdim // 47239462Sdim // TableGen automatically detects sub-registers that straddle the registers 48239462Sdim // in the SubRegs field of a Register definition. For example: 49239462Sdim // 50239462Sdim // Q0 = dsub_0 -> D0, dsub_1 -> D1 51239462Sdim // Q1 = dsub_0 -> D2, dsub_1 -> D3 52239462Sdim // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 53239462Sdim // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 54239462Sdim // 55239462Sdim // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given 56239462Sdim // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with 57239462Sdim // CoveringSubRegIndices = [dsub_1, dsub_2]. 58239462Sdim list<SubRegIndex> CoveringSubRegIndices = []; 59208599Srdivacky} 60208599Srdivacky 61261991Sdim// ComposedSubRegIndex - A sub-register that is the result of composing A and B. 62261991Sdim// Offset is set to the sum of A and B's Offsets. Size is set to B's Size. 63261991Sdimclass ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> 64261991Sdim : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1, 65261991Sdim !if(!eq(B.Offset, -1), -1, 66261991Sdim !add(A.Offset, B.Offset)))> { 67261991Sdim // See SubRegIndex. 68261991Sdim let ComposedOf = [A, B]; 69261991Sdim} 70261991Sdim 71224145Sdim// RegAltNameIndex - The alternate name set to use for register operands of 72224145Sdim// this register class when printing. 73224145Sdimclass RegAltNameIndex { 74224145Sdim string Namespace = ""; 75224145Sdim} 76224145Sdimdef NoRegAltName : RegAltNameIndex; 77224145Sdim 78193323Sed// Register - You should define one instance of this class for each register 79193323Sed// in the target machine. String n will become the "name" of the register. 80224145Sdimclass Register<string n, list<string> altNames = []> { 81193323Sed string Namespace = ""; 82193323Sed string AsmName = n; 83224145Sdim list<string> AltNames = altNames; 84193323Sed 85193323Sed // Aliases - A list of registers that this register overlaps with. A read or 86193323Sed // modification of this register can potentially read or modify the aliased 87193323Sed // registers. 88193323Sed list<Register> Aliases = []; 89218893Sdim 90193323Sed // SubRegs - A list of registers that are parts of this register. Note these 91193323Sed // are "immediate" sub-registers and the registers within the list do not 92193323Sed // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 93193323Sed // not [AX, AH, AL]. 94193323Sed list<Register> SubRegs = []; 95193323Sed 96208599Srdivacky // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 97208599Srdivacky // to address it. Sub-sub-register indices are automatically inherited from 98208599Srdivacky // SubRegs. 99208599Srdivacky list<SubRegIndex> SubRegIndices = []; 100208599Srdivacky 101224145Sdim // RegAltNameIndices - The alternate name indices which are valid for this 102224145Sdim // register. 103224145Sdim list<RegAltNameIndex> RegAltNameIndices = []; 104224145Sdim 105193323Sed // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 106193323Sed // These values can be determined by locating the <target>.h file in the 107193323Sed // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 108193323Sed // order of these names correspond to the enumeration used by gcc. A value of 109193323Sed // -1 indicates that the gcc number is undefined and -2 that register number 110193323Sed // is invalid for this mode/flavour. 111193323Sed list<int> DwarfNumbers = []; 112221345Sdim 113221345Sdim // CostPerUse - Additional cost of instructions using this register compared 114221345Sdim // to other registers in its class. The register allocator will try to 115221345Sdim // minimize the number of instructions using a register with a CostPerUse. 116234353Sdim // This is used by the x86-64 and ARM Thumb targets where some registers 117221345Sdim // require larger instruction encodings. 118221345Sdim int CostPerUse = 0; 119234353Sdim 120234353Sdim // CoveredBySubRegs - When this bit is set, the value of this register is 121234353Sdim // completely determined by the value of its sub-registers. For example, the 122234353Sdim // x86 register AX is covered by its sub-registers AL and AH, but EAX is not 123234353Sdim // covered by its sub-register AX. 124234353Sdim bit CoveredBySubRegs = 0; 125239462Sdim 126239462Sdim // HWEncoding - The target specific hardware encoding for this register. 127239462Sdim bits<16> HWEncoding = 0; 128193323Sed} 129193323Sed 130193323Sed// RegisterWithSubRegs - This can be used to define instances of Register which 131193323Sed// need to specify sub-registers. 132193323Sed// List "subregs" specifies which registers are sub-registers to this one. This 133193323Sed// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 134218893Sdim// This allows the code generator to be careful not to put two values with 135193323Sed// overlapping live ranges into registers which alias. 136193323Sedclass RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 137193323Sed let SubRegs = subregs; 138193323Sed} 139193323Sed 140239462Sdim// DAGOperand - An empty base class that unifies RegisterClass's and other forms 141239462Sdim// of Operand's that are legal as type qualifiers in DAG patterns. This should 142239462Sdim// only ever be used for defining multiclasses that are polymorphic over both 143239462Sdim// RegisterClass's and other Operand's. 144239462Sdimclass DAGOperand { } 145239462Sdim 146193323Sed// RegisterClass - Now that all of the registers are defined, and aliases 147193323Sed// between registers are defined, specify which registers belong to which 148193323Sed// register classes. This also defines the default allocation order of 149193323Sed// registers by register allocators. 150193323Sed// 151193323Sedclass RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 152239462Sdim dag regList, RegAltNameIndex idx = NoRegAltName> 153239462Sdim : DAGOperand { 154193323Sed string Namespace = namespace; 155193323Sed 156193323Sed // RegType - Specify the list ValueType of the registers in this register 157193323Sed // class. Note that all registers in a register class must have the same 158218893Sdim // ValueTypes. This is a list because some targets permit storing different 159193323Sed // types in same register, for example vector values with 128-bit total size, 160193323Sed // but different count/size of items, like SSE on x86. 161193323Sed // 162193323Sed list<ValueType> RegTypes = regTypes; 163193323Sed 164193323Sed // Size - Specify the spill size in bits of the registers. A default value of 165193323Sed // zero lets tablgen pick an appropriate size. 166193323Sed int Size = 0; 167193323Sed 168193323Sed // Alignment - Specify the alignment required of the registers when they are 169193323Sed // stored or loaded to memory. 170193323Sed // 171193323Sed int Alignment = alignment; 172193323Sed 173193323Sed // CopyCost - This value is used to specify the cost of copying a value 174193323Sed // between two registers in this register class. The default value is one 175193323Sed // meaning it takes a single instruction to perform the copying. A negative 176193323Sed // value means copying is extremely expensive or impossible. 177193323Sed int CopyCost = 1; 178193323Sed 179193323Sed // MemberList - Specify which registers are in this class. If the 180193323Sed // allocation_order_* method are not specified, this also defines the order of 181193323Sed // allocation used by the register allocator. 182193323Sed // 183224145Sdim dag MemberList = regList; 184218893Sdim 185224145Sdim // AltNameIndex - The alternate register name to use when printing operands 186224145Sdim // of this register class. Every register in the register class must have 187224145Sdim // a valid alternate name for the given index. 188224145Sdim RegAltNameIndex altNameIndex = idx; 189224145Sdim 190223017Sdim // isAllocatable - Specify that the register class can be used for virtual 191223017Sdim // registers and register allocation. Some register classes are only used to 192223017Sdim // model instruction operand constraints, and should have isAllocatable = 0. 193223017Sdim bit isAllocatable = 1; 194223017Sdim 195224145Sdim // AltOrders - List of alternative allocation orders. The default order is 196224145Sdim // MemberList itself, and that is good enough for most targets since the 197224145Sdim // register allocators automatically remove reserved registers and move 198224145Sdim // callee-saved registers to the end. 199224145Sdim list<dag> AltOrders = []; 200224145Sdim 201224145Sdim // AltOrderSelect - The body of a function that selects the allocation order 202224145Sdim // to use in a given machine function. The code will be inserted in a 203224145Sdim // function like this: 204224145Sdim // 205224145Sdim // static inline unsigned f(const MachineFunction &MF) { ... } 206224145Sdim // 207224145Sdim // The function should return 0 to select the default order defined by 208224145Sdim // MemberList, 1 to select the first AltOrders entry and so on. 209224145Sdim code AltOrderSelect = [{}]; 210288943Sdim 211288943Sdim // Specify allocation priority for register allocators using a greedy 212288943Sdim // heuristic. Classes with higher priority values are assigned first. This is 213288943Sdim // useful as it is sometimes beneficial to assign registers to highly 214288943Sdim // constrained classes first. The value has to be in the range [0,63]. 215288943Sdim int AllocationPriority = 0; 216193323Sed} 217193323Sed 218224145Sdim// The memberList in a RegisterClass is a dag of set operations. TableGen 219224145Sdim// evaluates these set operations and expand them into register lists. These 220224145Sdim// are the most common operation, see test/TableGen/SetTheory.td for more 221224145Sdim// examples of what is possible: 222224145Sdim// 223224145Sdim// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 224224145Sdim// register class, or a sub-expression. This is also the way to simply list 225224145Sdim// registers. 226224145Sdim// 227224145Sdim// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 228224145Sdim// 229224145Sdim// (and GPR, CSR) - Set intersection. All registers from the first set that are 230224145Sdim// also in the second set. 231224145Sdim// 232224145Sdim// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 233239462Sdim// numbered registers. Takes an optional 4th operand which is a stride to use 234239462Sdim// when generating the sequence. 235224145Sdim// 236224145Sdim// (shl GPR, 4) - Remove the first N elements. 237224145Sdim// 238224145Sdim// (trunc GPR, 4) - Truncate after the first N elements. 239224145Sdim// 240224145Sdim// (rotl GPR, 1) - Rotate N places to the left. 241224145Sdim// 242224145Sdim// (rotr GPR, 1) - Rotate N places to the right. 243224145Sdim// 244224145Sdim// (decimate GPR, 2) - Pick every N'th element, starting with the first. 245224145Sdim// 246234353Sdim// (interleave A, B, ...) - Interleave the elements from each argument list. 247234353Sdim// 248224145Sdim// All of these operators work on ordered sets, not lists. That means 249224145Sdim// duplicates are removed from sub-expressions. 250193323Sed 251224145Sdim// Set operators. The rest is defined in TargetSelectionDAG.td. 252224145Sdimdef sequence; 253224145Sdimdef decimate; 254234353Sdimdef interleave; 255224145Sdim 256224145Sdim// RegisterTuples - Automatically generate super-registers by forming tuples of 257224145Sdim// sub-registers. This is useful for modeling register sequence constraints 258224145Sdim// with pseudo-registers that are larger than the architectural registers. 259224145Sdim// 260224145Sdim// The sub-register lists are zipped together: 261224145Sdim// 262224145Sdim// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 263224145Sdim// 264224145Sdim// Generates the same registers as: 265224145Sdim// 266224145Sdim// let SubRegIndices = [sube, subo] in { 267224145Sdim// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 268224145Sdim// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 269224145Sdim// } 270224145Sdim// 271224145Sdim// The generated pseudo-registers inherit super-classes and fields from their 272224145Sdim// first sub-register. Most fields from the Register class are inferred, and 273224145Sdim// the AsmName and Dwarf numbers are cleared. 274224145Sdim// 275224145Sdim// RegisterTuples instances can be used in other set operations to form 276224145Sdim// register classes and so on. This is the only way of using the generated 277224145Sdim// registers. 278224145Sdimclass RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { 279224145Sdim // SubRegs - N lists of registers to be zipped up. Super-registers are 280224145Sdim // synthesized from the first element of each SubRegs list, the second 281224145Sdim // element and so on. 282224145Sdim list<dag> SubRegs = Regs; 283224145Sdim 284224145Sdim // SubRegIndices - N SubRegIndex instances. This provides the names of the 285224145Sdim // sub-registers in the synthesized super-registers. 286224145Sdim list<SubRegIndex> SubRegIndices = Indices; 287224145Sdim} 288224145Sdim 289224145Sdim 290193323Sed//===----------------------------------------------------------------------===// 291193323Sed// DwarfRegNum - This class provides a mapping of the llvm register enumeration 292193323Sed// to the register numbering used by gcc and gdb. These values are used by a 293206274Srdivacky// debug information writer to describe where values may be located during 294206274Srdivacky// execution. 295193323Sedclass DwarfRegNum<list<int> Numbers> { 296193323Sed // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 297193323Sed // These values can be determined by locating the <target>.h file in the 298193323Sed // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 299193323Sed // order of these names correspond to the enumeration used by gcc. A value of 300218893Sdim // -1 indicates that the gcc number is undefined and -2 that register number 301218893Sdim // is invalid for this mode/flavour. 302193323Sed list<int> DwarfNumbers = Numbers; 303193323Sed} 304193323Sed 305223017Sdim// DwarfRegAlias - This class declares that a given register uses the same dwarf 306223017Sdim// numbers as another one. This is useful for making it clear that the two 307223017Sdim// registers do have the same number. It also lets us build a mapping 308223017Sdim// from dwarf register number to llvm register. 309223017Sdimclass DwarfRegAlias<Register reg> { 310223017Sdim Register DwarfAlias = reg; 311223017Sdim} 312223017Sdim 313193323Sed//===----------------------------------------------------------------------===// 314193323Sed// Pull in the common support for scheduling 315193323Sed// 316193323Sedinclude "llvm/Target/TargetSchedule.td" 317193323Sed 318193323Sedclass Predicate; // Forward def 319193323Sed 320193323Sed//===----------------------------------------------------------------------===// 321193323Sed// Instruction set description - These classes correspond to the C++ classes in 322193323Sed// the Target/TargetInstrInfo.h file. 323193323Sed// 324193323Sedclass Instruction { 325193323Sed string Namespace = ""; 326193323Sed 327193323Sed dag OutOperandList; // An dag containing the MI def operand list. 328193323Sed dag InOperandList; // An dag containing the MI use operand list. 329193323Sed string AsmString = ""; // The .s format to print the instruction with. 330193323Sed 331193323Sed // Pattern - Set to the DAG pattern for this instruction, if we know of one, 332193323Sed // otherwise, uninitialized. 333193323Sed list<dag> Pattern; 334193323Sed 335193323Sed // The follow state will eventually be inferred automatically from the 336193323Sed // instruction pattern. 337193323Sed 338193323Sed list<Register> Uses = []; // Default to using no non-operand registers 339193323Sed list<Register> Defs = []; // Default to modifying no non-operand registers 340193323Sed 341193323Sed // Predicates - List of predicates which will be turned into isel matching 342193323Sed // code. 343193323Sed list<Predicate> Predicates = []; 344193323Sed 345224145Sdim // Size - Size of encoded instruction, or zero if the size cannot be determined 346224145Sdim // from the opcode. 347224145Sdim int Size = 0; 348224145Sdim 349226633Sdim // DecoderNamespace - The "namespace" in which this instruction exists, on 350226633Sdim // targets like ARM which multiple ISA namespaces exist. 351226633Sdim string DecoderNamespace = ""; 352226633Sdim 353224145Sdim // Code size, for instruction selection. 354224145Sdim // FIXME: What does this actually mean? 355193323Sed int CodeSize = 0; 356193323Sed 357193323Sed // Added complexity passed onto matching pattern. 358193323Sed int AddedComplexity = 0; 359193323Sed 360193323Sed // These bits capture information about the high-level semantics of the 361193323Sed // instruction. 362193323Sed bit isReturn = 0; // Is this instruction a return instruction? 363193323Sed bit isBranch = 0; // Is this instruction a branch instruction? 364193323Sed bit isIndirectBranch = 0; // Is this instruction an indirect branch? 365212904Sdim bit isCompare = 0; // Is this instruction a comparison instruction? 366218893Sdim bit isMoveImm = 0; // Is this instruction a move immediate instruction? 367221345Sdim bit isBitcast = 0; // Is this instruction a bitcast instruction? 368239462Sdim bit isSelect = 0; // Is this instruction a select instruction? 369193323Sed bit isBarrier = 0; // Can control flow fall through this instruction? 370193323Sed bit isCall = 0; // Is this instruction a call instruction? 371193323Sed bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 372243830Sdim bit mayLoad = ?; // Is it possible for this inst to read memory? 373243830Sdim bit mayStore = ?; // Is it possible for this inst to write memory? 374193323Sed bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 375193323Sed bit isCommutable = 0; // Is this 3 operand instruction commutable? 376193323Sed bit isTerminator = 0; // Is this part of the terminator for a basic block? 377193323Sed bit isReMaterializable = 0; // Is this instruction re-materializable? 378193323Sed bit isPredicable = 0; // Is this instruction predicable? 379193323Sed bit hasDelaySlot = 0; // Does this instruction have an delay slot? 380198892Srdivacky bit usesCustomInserter = 0; // Pseudo instr needing special help. 381226633Sdim bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. 382193323Sed bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 383193323Sed bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 384288943Sdim bit isConvergent = 0; // Is this instruction convergent? 385193323Sed bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 386198090Srdivacky bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 387198090Srdivacky bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 388280031Sdim bit isRegSequence = 0; // Is this instruction a kind of reg sequence? 389280031Sdim // If so, make sure to override 390280031Sdim // TargetInstrInfo::getRegSequenceLikeInputs. 391224145Sdim bit isPseudo = 0; // Is this instruction a pseudo-instruction? 392224145Sdim // If so, won't have encoding information for 393224145Sdim // the [MC]CodeEmitter stuff. 394280031Sdim bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg? 395280031Sdim // If so, make sure to override 396280031Sdim // TargetInstrInfo::getExtractSubregLikeInputs. 397280031Sdim bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg? 398280031Sdim // If so, make sure to override 399280031Sdim // TargetInstrInfo::getInsertSubregLikeInputs. 400193323Sed 401193323Sed // Side effect flags - When set, the flags have these meanings: 402193323Sed // 403193323Sed // hasSideEffects - The instruction has side effects that are not 404193323Sed // captured by any operands of the instruction or other flags. 405193323Sed // 406243830Sdim bit hasSideEffects = ?; 407193323Sed 408198090Srdivacky // Is this instruction a "real" instruction (with a distinct machine 409198090Srdivacky // encoding), or is it a pseudo instruction used for codegen modeling 410198090Srdivacky // purposes. 411224145Sdim // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 412224145Sdim // instructions can (and often do) still have encoding information 413224145Sdim // associated with them. Once we've migrated all of them over to true 414224145Sdim // pseudo-instructions that are lowered to real instructions prior to 415224145Sdim // the printer/emitter, we can remove this attribute and just use isPseudo. 416234353Sdim // 417234353Sdim // The intended use is: 418234353Sdim // isPseudo: Does not have encoding information and should be expanded, 419234353Sdim // at the latest, during lowering to MCInst. 420234353Sdim // 421234353Sdim // isCodeGenOnly: Does have encoding information and can go through to the 422234353Sdim // CodeEmitter unchanged, but duplicates a canonical instruction 423234353Sdim // definition's encoding and should be ignored when constructing the 424234353Sdim // assembler match tables. 425198090Srdivacky bit isCodeGenOnly = 0; 426198090Srdivacky 427208599Srdivacky // Is this instruction a pseudo instruction for use by the assembler parser. 428208599Srdivacky bit isAsmParserOnly = 0; 429208599Srdivacky 430193323Sed InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 431193323Sed 432249423Sdim // Scheduling information from TargetSchedule.td. 433249423Sdim list<SchedReadWrite> SchedRW; 434249423Sdim 435193323Sed string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 436206274Srdivacky 437193323Sed /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 438193323Sed /// be encoded into the output machineinstr. 439193323Sed string DisableEncoding = ""; 440206274Srdivacky 441218893Sdim string PostEncoderMethod = ""; 442218893Sdim string DecoderMethod = ""; 443218893Sdim 444296417Sdim // Is the instruction decoder method able to completely determine if the 445296417Sdim // given instruction is valid or not. If the TableGen definition of the 446296417Sdim // instruction specifies bitpattern A??B where A and B are static bits, the 447296417Sdim // hasCompleteDecoder flag says whether the decoder method fully handles the 448296417Sdim // ?? space, i.e. if it is a final arbiter for the instruction validity. 449296417Sdim // If not then the decoder attempts to continue decoding when the decoder 450296417Sdim // method fails. 451296417Sdim // 452296417Sdim // This allows to handle situations where the encoding is not fully 453296417Sdim // orthogonal. Example: 454296417Sdim // * InstA with bitpattern 0b0000????, 455296417Sdim // * InstB with bitpattern 0b000000?? but the associated decoder method 456296417Sdim // DecodeInstB() returns Fail when ?? is 0b00 or 0b11. 457296417Sdim // 458296417Sdim // The decoder tries to decode a bitpattern that matches both InstA and 459296417Sdim // InstB bitpatterns first as InstB (because it is the most specific 460296417Sdim // encoding). In the default case (hasCompleteDecoder = 1), when 461296417Sdim // DecodeInstB() returns Fail the bitpattern gets rejected. By setting 462296417Sdim // hasCompleteDecoder = 0 in InstB, the decoder is informed that 463296417Sdim // DecodeInstB() is not able to determine if all possible values of ?? are 464296417Sdim // valid or not. If DecodeInstB() returns Fail the decoder will attempt to 465296417Sdim // decode the bitpattern as InstA too. 466296417Sdim bit hasCompleteDecoder = 1; 467296417Sdim 468206274Srdivacky /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 469210299Sed bits<64> TSFlags = 0; 470218893Sdim 471218893Sdim ///@name Assembler Parser Support 472218893Sdim ///@{ 473218893Sdim 474218893Sdim string AsmMatchConverter = ""; 475218893Sdim 476239462Sdim /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a 477239462Sdim /// two-operand matcher inst-alias for a three operand instruction. 478239462Sdim /// For example, the arm instruction "add r3, r3, r5" can be written 479239462Sdim /// as "add r3, r5". The constraint is of the same form as a tied-operand 480239462Sdim /// constraint. For example, "$Rn = $Rd". 481239462Sdim string TwoOperandAliasConstraint = ""; 482239462Sdim 483218893Sdim ///@} 484261991Sdim 485261991Sdim /// UseNamedOperandTable - If set, the operand indices of this instruction 486261991Sdim /// can be queried via the getNamedOperandIdx() function which is generated 487261991Sdim /// by TableGen. 488261991Sdim bit UseNamedOperandTable = 0; 489193323Sed} 490193323Sed 491224145Sdim/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 492224145Sdim/// Which instruction it expands to and how the operands map from the 493224145Sdim/// pseudo. 494224145Sdimclass PseudoInstExpansion<dag Result> { 495224145Sdim dag ResultInst = Result; // The instruction to generate. 496224145Sdim bit isPseudo = 1; 497224145Sdim} 498224145Sdim 499193323Sed/// Predicates - These are extra conditionals which are turned into instruction 500193323Sed/// selector matching code. Currently each predicate is just a string. 501193323Sedclass Predicate<string cond> { 502193323Sed string CondString = cond; 503218893Sdim 504218893Sdim /// AssemblerMatcherPredicate - If this feature can be used by the assembler 505218893Sdim /// matcher, this is true. Targets should set this by inheriting their 506218893Sdim /// feature from the AssemblerPredicate class in addition to Predicate. 507218893Sdim bit AssemblerMatcherPredicate = 0; 508224145Sdim 509224145Sdim /// AssemblerCondString - Name of the subtarget feature being tested used 510224145Sdim /// as alternative condition string used for assembler matcher. 511224145Sdim /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". 512224145Sdim /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". 513224145Sdim /// It can also list multiple features separated by ",". 514224145Sdim /// e.g. "ModeThumb,FeatureThumb2" is translated to 515224145Sdim /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 516224145Sdim string AssemblerCondString = ""; 517239462Sdim 518239462Sdim /// PredicateName - User-level name to use for the predicate. Mainly for use 519239462Sdim /// in diagnostics such as missing feature errors in the asm matcher. 520239462Sdim string PredicateName = ""; 521193323Sed} 522193323Sed 523193323Sed/// NoHonorSignDependentRounding - This predicate is true if support for 524193323Sed/// sign-dependent-rounding is not enabled. 525193323Seddef NoHonorSignDependentRounding 526234353Sdim : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 527193323Sed 528193323Sedclass Requires<list<Predicate> preds> { 529193323Sed list<Predicate> Predicates = preds; 530193323Sed} 531193323Sed 532218893Sdim/// ops definition - This is just a simple marker used to identify the operand 533218893Sdim/// list for an instruction. outs and ins are identical both syntactically and 534288943Sdim/// semantically; they are used to define def operands and use operands to 535193323Sed/// improve readibility. This should be used like this: 536193323Sed/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 537193323Seddef ops; 538193323Seddef outs; 539193323Seddef ins; 540193323Sed 541193323Sed/// variable_ops definition - Mark this instruction as taking a variable number 542193323Sed/// of operands. 543193323Seddef variable_ops; 544193323Sed 545198090Srdivacky 546198090Srdivacky/// PointerLikeRegClass - Values that are designed to have pointer width are 547198090Srdivacky/// derived from this. TableGen treats the register class as having a symbolic 548198090Srdivacky/// type that it doesn't know, and resolves the actual regclass to use by using 549198090Srdivacky/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 550198090Srdivackyclass PointerLikeRegClass<int Kind> { 551198090Srdivacky int RegClassKind = Kind; 552198090Srdivacky} 553198090Srdivacky 554198090Srdivacky 555193323Sed/// ptr_rc definition - Mark this operand as being a pointer value whose 556193323Sed/// register class is resolved dynamically via a callback to TargetInstrInfo. 557193323Sed/// FIXME: We should probably change this to a class which contain a list of 558193323Sed/// flags. But currently we have but one flag. 559198090Srdivackydef ptr_rc : PointerLikeRegClass<0>; 560193323Sed 561193323Sed/// unknown definition - Mark this operand as being of unknown type, causing 562193323Sed/// it to be resolved by inference in the context it is used. 563243830Sdimclass unknown_class; 564243830Sdimdef unknown : unknown_class; 565193323Sed 566198090Srdivacky/// AsmOperandClass - Representation for the kinds of operands which the target 567198090Srdivacky/// specific parser can create and the assembly matcher may need to distinguish. 568198090Srdivacky/// 569198090Srdivacky/// Operand classes are used to define the order in which instructions are 570198090Srdivacky/// matched, to ensure that the instruction which gets matched for any 571198090Srdivacky/// particular list of operands is deterministic. 572198090Srdivacky/// 573198090Srdivacky/// The target specific parser must be able to classify a parsed operand into a 574198090Srdivacky/// unique class which does not partially overlap with any other classes. It can 575198090Srdivacky/// match a subset of some other class, in which case the super class field 576198090Srdivacky/// should be defined. 577198090Srdivackyclass AsmOperandClass { 578198090Srdivacky /// The name to use for this class, which should be usable as an enum value. 579198090Srdivacky string Name = ?; 580198090Srdivacky 581208599Srdivacky /// The super classes of this operand. 582208599Srdivacky list<AsmOperandClass> SuperClasses = []; 583198090Srdivacky 584198090Srdivacky /// The name of the method on the target specific operand to call to test 585198090Srdivacky /// whether the operand is an instance of this class. If not set, this will 586198090Srdivacky /// default to "isFoo", where Foo is the AsmOperandClass name. The method 587198090Srdivacky /// signature should be: 588198090Srdivacky /// bool isFoo() const; 589198090Srdivacky string PredicateMethod = ?; 590198090Srdivacky 591198090Srdivacky /// The name of the method on the target specific operand to call to add the 592198090Srdivacky /// target specific operand to an MCInst. If not set, this will default to 593198090Srdivacky /// "addFooOperands", where Foo is the AsmOperandClass name. The method 594198090Srdivacky /// signature should be: 595198090Srdivacky /// void addFooOperands(MCInst &Inst, unsigned N) const; 596198090Srdivacky string RenderMethod = ?; 597218893Sdim 598218893Sdim /// The name of the method on the target specific operand to call to custom 599218893Sdim /// handle the operand parsing. This is useful when the operands do not relate 600218893Sdim /// to immediates or registers and are very instruction specific (as flags to 601218893Sdim /// set in a processor register, coprocessor number, ...). 602218893Sdim string ParserMethod = ?; 603239462Sdim 604239462Sdim // The diagnostic type to present when referencing this operand in a 605239462Sdim // match failure error message. By default, use a generic "invalid operand" 606239462Sdim // diagnostic. The target AsmParser maps these codes to text. 607239462Sdim string DiagnosticType = ""; 608198090Srdivacky} 609198090Srdivacky 610198090Srdivackydef ImmAsmOperand : AsmOperandClass { 611198090Srdivacky let Name = "Imm"; 612198090Srdivacky} 613218893Sdim 614193323Sed/// Operand Types - These provide the built-in operand types that may be used 615193323Sed/// by a target. Targets can optionally provide their own operand types as 616193323Sed/// needed, though this should not be needed for RISC targets. 617239462Sdimclass Operand<ValueType ty> : DAGOperand { 618193323Sed ValueType Type = ty; 619193323Sed string PrintMethod = "printOperand"; 620218893Sdim string EncoderMethod = ""; 621218893Sdim string DecoderMethod = ""; 622296417Sdim bit hasCompleteDecoder = 1; 623296417Sdim string OperandNamespace = "MCOI"; 624224145Sdim string OperandType = "OPERAND_UNKNOWN"; 625193323Sed dag MIOperandInfo = (ops); 626198090Srdivacky 627276479Sdim // MCOperandPredicate - Optionally, a code fragment operating on 628276479Sdim // const MCOperand &MCOp, and returning a bool, to indicate if 629276479Sdim // the value of MCOp is valid for the specific subclass of Operand 630276479Sdim code MCOperandPredicate; 631276479Sdim 632198090Srdivacky // ParserMatchClass - The "match class" that operands of this type fit 633198090Srdivacky // in. Match classes are used to define the order in which instructions are 634198090Srdivacky // match, to ensure that which instructions gets matched is deterministic. 635198090Srdivacky // 636208599Srdivacky // The target specific parser must be able to classify an parsed operand into 637208599Srdivacky // a unique class, which does not partially overlap with any other classes. It 638208599Srdivacky // can match a subset of some other class, in which case the AsmOperandClass 639208599Srdivacky // should declare the other operand as one of its super classes. 640198090Srdivacky AsmOperandClass ParserMatchClass = ImmAsmOperand; 641193323Sed} 642193323Sed 643239462Sdimclass RegisterOperand<RegisterClass regclass, string pm = "printOperand"> 644239462Sdim : DAGOperand { 645224145Sdim // RegClass - The register class of the operand. 646224145Sdim RegisterClass RegClass = regclass; 647224145Sdim // PrintMethod - The target method to call to print register operands of 648224145Sdim // this type. The method normally will just use an alt-name index to look 649224145Sdim // up the name to print. Default to the generic printOperand(). 650224145Sdim string PrintMethod = pm; 651224145Sdim // ParserMatchClass - The "match class" that operands of this type fit 652224145Sdim // in. Match classes are used to define the order in which instructions are 653224145Sdim // match, to ensure that which instructions gets matched is deterministic. 654224145Sdim // 655224145Sdim // The target specific parser must be able to classify an parsed operand into 656224145Sdim // a unique class, which does not partially overlap with any other classes. It 657224145Sdim // can match a subset of some other class, in which case the AsmOperandClass 658224145Sdim // should declare the other operand as one of its super classes. 659224145Sdim AsmOperandClass ParserMatchClass; 660280031Sdim 661280031Sdim string OperandNamespace = "MCOI"; 662280031Sdim string OperandType = "OPERAND_REGISTER"; 663224145Sdim} 664224145Sdim 665224145Sdimlet OperandType = "OPERAND_IMMEDIATE" in { 666193323Seddef i1imm : Operand<i1>; 667193323Seddef i8imm : Operand<i8>; 668193323Seddef i16imm : Operand<i16>; 669193323Seddef i32imm : Operand<i32>; 670193323Seddef i64imm : Operand<i64>; 671193323Sed 672193323Seddef f32imm : Operand<f32>; 673193323Seddef f64imm : Operand<f64>; 674224145Sdim} 675193323Sed 676193323Sed/// zero_reg definition - Special node to stand for the zero register. 677193323Sed/// 678193323Seddef zero_reg; 679193323Sed 680261991Sdim/// All operands which the MC layer classifies as predicates should inherit from 681261991Sdim/// this class in some manner. This is already handled for the most commonly 682261991Sdim/// used PredicateOperand, but may be useful in other circumstances. 683261991Sdimclass PredicateOp; 684261991Sdim 685243830Sdim/// OperandWithDefaultOps - This Operand class can be used as the parent class 686243830Sdim/// for an Operand that needs to be initialized with a default value if 687243830Sdim/// no value is supplied in a pattern. This class can be used to simplify the 688243830Sdim/// pattern definitions for instructions that have target specific flags 689243830Sdim/// encoded as immediate operands. 690243830Sdimclass OperandWithDefaultOps<ValueType ty, dag defaultops> 691243830Sdim : Operand<ty> { 692243830Sdim dag DefaultOps = defaultops; 693243830Sdim} 694243830Sdim 695193323Sed/// PredicateOperand - This can be used to define a predicate operand for an 696193323Sed/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 697193323Sed/// AlwaysVal specifies the value of this predicate when set to "always 698193323Sed/// execute". 699193323Sedclass PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 700261991Sdim : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp { 701193323Sed let MIOperandInfo = OpTypes; 702193323Sed} 703193323Sed 704193323Sed/// OptionalDefOperand - This is used to define a optional definition operand 705198090Srdivacky/// for an instruction. DefaultOps is the register the operand represents if 706198090Srdivacky/// none is supplied, e.g. zero_reg. 707193323Sedclass OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 708243830Sdim : OperandWithDefaultOps<ty, defaultops> { 709193323Sed let MIOperandInfo = OpTypes; 710193323Sed} 711193323Sed 712193323Sed 713193323Sed// InstrInfo - This class should only be instantiated once to provide parameters 714203954Srdivacky// which are global to the target machine. 715193323Sed// 716193323Sedclass InstrInfo { 717193323Sed // Target can specify its instructions in either big or little-endian formats. 718193323Sed // For instance, while both Sparc and PowerPC are big-endian platforms, the 719193323Sed // Sparc manual specifies its instructions in the format [31..0] (big), while 720193323Sed // PowerPC specifies them using the format [0..31] (little). 721193323Sed bit isLittleEndianEncoding = 0; 722243830Sdim 723243830Sdim // The instruction properties mayLoad, mayStore, and hasSideEffects are unset 724243830Sdim // by default, and TableGen will infer their value from the instruction 725243830Sdim // pattern when possible. 726243830Sdim // 727243830Sdim // Normally, TableGen will issue an error it it can't infer the value of a 728243830Sdim // property that hasn't been set explicitly. When guessInstructionProperties 729243830Sdim // is set, it will guess a safe value instead. 730243830Sdim // 731243830Sdim // This option is a temporary migration help. It will go away. 732243830Sdim bit guessInstructionProperties = 1; 733276479Sdim 734276479Sdim // TableGen's instruction encoder generator has support for matching operands 735276479Sdim // to bit-field variables both by name and by position. While matching by 736276479Sdim // name is preferred, this is currently not possible for complex operands, 737276479Sdim // and some targets still reply on the positional encoding rules. When 738276479Sdim // generating a decoder for such targets, the positional encoding rules must 739276479Sdim // be used by the decoder generator as well. 740276479Sdim // 741276479Sdim // This option is temporary; it will go away once the TableGen decoder 742276479Sdim // generator has better support for complex operands and targets have 743276479Sdim // migrated away from using positionally encoded operands. 744276479Sdim bit decodePositionallyEncodedOperands = 0; 745276479Sdim 746276479Sdim // When set, this indicates that there will be no overlap between those 747276479Sdim // operands that are matched by ordering (positional operands) and those 748276479Sdim // matched by name. 749276479Sdim // 750276479Sdim // This option is temporary; it will go away once the TableGen decoder 751276479Sdim // generator has better support for complex operands and targets have 752276479Sdim // migrated away from using positionally encoded operands. 753276479Sdim bit noNamedPositionallyEncodedOperands = 0; 754193323Sed} 755193323Sed 756198090Srdivacky// Standard Pseudo Instructions. 757210299Sed// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 758210299Sed// Only these instructions are allowed in the TargetOpcode namespace. 759226633Sdimlet isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in { 760193323Seddef PHI : Instruction { 761205407Srdivacky let OutOperandList = (outs); 762205407Srdivacky let InOperandList = (ins variable_ops); 763193323Sed let AsmString = "PHINODE"; 764193323Sed} 765193323Seddef INLINEASM : Instruction { 766205407Srdivacky let OutOperandList = (outs); 767205407Srdivacky let InOperandList = (ins variable_ops); 768193323Sed let AsmString = ""; 769280031Sdim let hasSideEffects = 0; // Note side effect is encoded in an operand. 770193323Sed} 771276479Sdimdef CFI_INSTRUCTION : Instruction { 772205407Srdivacky let OutOperandList = (outs); 773205407Srdivacky let InOperandList = (ins i32imm:$id); 774193323Sed let AsmString = ""; 775193323Sed let hasCtrlDep = 1; 776199481Srdivacky let isNotDuplicable = 1; 777193323Sed} 778193323Seddef EH_LABEL : Instruction { 779205407Srdivacky let OutOperandList = (outs); 780205407Srdivacky let InOperandList = (ins i32imm:$id); 781193323Sed let AsmString = ""; 782193323Sed let hasCtrlDep = 1; 783199481Srdivacky let isNotDuplicable = 1; 784193323Sed} 785193323Seddef GC_LABEL : Instruction { 786205407Srdivacky let OutOperandList = (outs); 787205407Srdivacky let InOperandList = (ins i32imm:$id); 788193323Sed let AsmString = ""; 789193323Sed let hasCtrlDep = 1; 790199481Srdivacky let isNotDuplicable = 1; 791193323Sed} 792198090Srdivackydef KILL : Instruction { 793205407Srdivacky let OutOperandList = (outs); 794205407Srdivacky let InOperandList = (ins variable_ops); 795193323Sed let AsmString = ""; 796280031Sdim let hasSideEffects = 0; 797193323Sed} 798193323Seddef EXTRACT_SUBREG : Instruction { 799205407Srdivacky let OutOperandList = (outs unknown:$dst); 800205407Srdivacky let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 801193323Sed let AsmString = ""; 802280031Sdim let hasSideEffects = 0; 803193323Sed} 804193323Seddef INSERT_SUBREG : Instruction { 805205407Srdivacky let OutOperandList = (outs unknown:$dst); 806205407Srdivacky let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 807193323Sed let AsmString = ""; 808280031Sdim let hasSideEffects = 0; 809193323Sed let Constraints = "$supersrc = $dst"; 810193323Sed} 811193323Seddef IMPLICIT_DEF : Instruction { 812205407Srdivacky let OutOperandList = (outs unknown:$dst); 813205407Srdivacky let InOperandList = (ins); 814193323Sed let AsmString = ""; 815280031Sdim let hasSideEffects = 0; 816193323Sed let isReMaterializable = 1; 817193323Sed let isAsCheapAsAMove = 1; 818193323Sed} 819193323Seddef SUBREG_TO_REG : Instruction { 820205407Srdivacky let OutOperandList = (outs unknown:$dst); 821205407Srdivacky let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 822193323Sed let AsmString = ""; 823280031Sdim let hasSideEffects = 0; 824193323Sed} 825193323Seddef COPY_TO_REGCLASS : Instruction { 826205407Srdivacky let OutOperandList = (outs unknown:$dst); 827205407Srdivacky let InOperandList = (ins unknown:$src, i32imm:$regclass); 828193323Sed let AsmString = ""; 829280031Sdim let hasSideEffects = 0; 830193323Sed let isAsCheapAsAMove = 1; 831193323Sed} 832203954Srdivackydef DBG_VALUE : Instruction { 833205407Srdivacky let OutOperandList = (outs); 834205407Srdivacky let InOperandList = (ins variable_ops); 835203954Srdivacky let AsmString = "DBG_VALUE"; 836280031Sdim let hasSideEffects = 0; 837198090Srdivacky} 838207618Srdivackydef REG_SEQUENCE : Instruction { 839207618Srdivacky let OutOperandList = (outs unknown:$dst); 840280031Sdim let InOperandList = (ins unknown:$supersrc, variable_ops); 841207618Srdivacky let AsmString = ""; 842280031Sdim let hasSideEffects = 0; 843207618Srdivacky let isAsCheapAsAMove = 1; 844202375Srdivacky} 845210299Seddef COPY : Instruction { 846210299Sed let OutOperandList = (outs unknown:$dst); 847210299Sed let InOperandList = (ins unknown:$src); 848210299Sed let AsmString = ""; 849280031Sdim let hasSideEffects = 0; 850210299Sed let isAsCheapAsAMove = 1; 851207618Srdivacky} 852234353Sdimdef BUNDLE : Instruction { 853234353Sdim let OutOperandList = (outs); 854234353Sdim let InOperandList = (ins variable_ops); 855234353Sdim let AsmString = "BUNDLE"; 856210299Sed} 857243830Sdimdef LIFETIME_START : Instruction { 858243830Sdim let OutOperandList = (outs); 859243830Sdim let InOperandList = (ins i32imm:$id); 860243830Sdim let AsmString = "LIFETIME_START"; 861280031Sdim let hasSideEffects = 0; 862234353Sdim} 863243830Sdimdef LIFETIME_END : Instruction { 864243830Sdim let OutOperandList = (outs); 865243830Sdim let InOperandList = (ins i32imm:$id); 866243830Sdim let AsmString = "LIFETIME_END"; 867280031Sdim let hasSideEffects = 0; 868243830Sdim} 869261991Sdimdef STACKMAP : Instruction { 870261991Sdim let OutOperandList = (outs); 871276479Sdim let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops); 872261991Sdim let isCall = 1; 873261991Sdim let mayLoad = 1; 874276479Sdim let usesCustomInserter = 1; 875243830Sdim} 876261991Sdimdef PATCHPOINT : Instruction { 877261991Sdim let OutOperandList = (outs unknown:$dst); 878276479Sdim let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee, 879261991Sdim i32imm:$nargs, i32imm:$cc, variable_ops); 880261991Sdim let isCall = 1; 881261991Sdim let mayLoad = 1; 882276479Sdim let usesCustomInserter = 1; 883261991Sdim} 884280031Sdimdef STATEPOINT : Instruction { 885280031Sdim let OutOperandList = (outs); 886280031Sdim let InOperandList = (ins variable_ops); 887280031Sdim let usesCustomInserter = 1; 888280031Sdim let mayLoad = 1; 889280031Sdim let mayStore = 1; 890280031Sdim let hasSideEffects = 1; 891280031Sdim let isCall = 1; 892261991Sdim} 893280031Sdimdef LOAD_STACK_GUARD : Instruction { 894280031Sdim let OutOperandList = (outs ptr_rc:$dst); 895280031Sdim let InOperandList = (ins); 896280031Sdim let mayLoad = 1; 897280031Sdim bit isReMaterializable = 1; 898280031Sdim let hasSideEffects = 0; 899280031Sdim bit isPseudo = 1; 900280031Sdim} 901288943Sdimdef LOCAL_ESCAPE : Instruction { 902280031Sdim // This instruction is really just a label. It has to be part of the chain so 903280031Sdim // that it doesn't get dropped from the DAG, but it produces nothing and has 904280031Sdim // no side effects. 905280031Sdim let OutOperandList = (outs); 906280031Sdim let InOperandList = (ins ptr_rc:$symbol, i32imm:$id); 907280031Sdim let hasSideEffects = 0; 908280031Sdim let hasCtrlDep = 1; 909280031Sdim} 910288943Sdimdef FAULTING_LOAD_OP : Instruction { 911288943Sdim let OutOperandList = (outs unknown:$dst); 912288943Sdim let InOperandList = (ins variable_ops); 913288943Sdim let usesCustomInserter = 1; 914288943Sdim let mayLoad = 1; 915280031Sdim} 916288943Sdim} 917193323Sed 918193323Sed//===----------------------------------------------------------------------===// 919207618Srdivacky// AsmParser - This class can be implemented by targets that wish to implement 920198090Srdivacky// .s file parsing. 921198090Srdivacky// 922207618Srdivacky// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 923198090Srdivacky// syntax on X86 for example). 924198090Srdivacky// 925198090Srdivackyclass AsmParser { 926198090Srdivacky // AsmParserClassName - This specifies the suffix to use for the asmparser 927198090Srdivacky // class. Generated AsmParser classes are always prefixed with the target 928198090Srdivacky // name. 929198090Srdivacky string AsmParserClassName = "AsmParser"; 930205407Srdivacky 931218893Sdim // AsmParserInstCleanup - If non-empty, this is the name of a custom member 932218893Sdim // function of the AsmParser class to call on every matched instruction. 933218893Sdim // This can be used to perform target specific instruction post-processing. 934205407Srdivacky string AsmParserInstCleanup = ""; 935243830Sdim 936251662Sdim // ShouldEmitMatchRegisterName - Set to false if the target needs a hand 937251662Sdim // written register name matcher 938243830Sdim bit ShouldEmitMatchRegisterName = 1; 939261991Sdim 940296417Sdim // HasMnemonicFirst - Set to false if target instructions don't always 941296417Sdim // start with a mnemonic as the first token. 942296417Sdim bit HasMnemonicFirst = 1; 943234353Sdim} 944234353Sdimdef DefaultAsmParser : AsmParser; 945207618Srdivacky 946234353Sdim//===----------------------------------------------------------------------===// 947239462Sdim// AsmParserVariant - Subtargets can have multiple different assembly parsers 948234353Sdim// (e.g. AT&T vs Intel syntax on X86 for example). This class can be 949234353Sdim// implemented by targets to describe such variants. 950234353Sdim// 951234353Sdimclass AsmParserVariant { 952198090Srdivacky // Variant - AsmParsers can be of multiple different variants. Variants are 953207618Srdivacky // used to support targets that need to parser multiple formats for the 954198090Srdivacky // assembly language. 955198090Srdivacky int Variant = 0; 956198090Srdivacky 957251662Sdim // Name - The AsmParser variant name (e.g., AT&T vs Intel). 958251662Sdim string Name = ""; 959251662Sdim 960198090Srdivacky // CommentDelimiter - If given, the delimiter string used to recognize 961198090Srdivacky // comments which are hard coded in the .td assembler strings for individual 962198090Srdivacky // instructions. 963198090Srdivacky string CommentDelimiter = ""; 964198090Srdivacky 965198090Srdivacky // RegisterPrefix - If given, the token prefix which indicates a register 966198090Srdivacky // token. This is used by the matcher to automatically recognize hard coded 967198090Srdivacky // register tokens as constrained registers, instead of tokens, for the 968198090Srdivacky // purposes of matching. 969198090Srdivacky string RegisterPrefix = ""; 970296417Sdim 971296417Sdim // TokenizingCharacters - Characters that are standalone tokens 972296417Sdim string TokenizingCharacters = "[]*!"; 973296417Sdim 974296417Sdim // SeparatorCharacters - Characters that are not tokens 975296417Sdim string SeparatorCharacters = " \t,"; 976296417Sdim 977296417Sdim // BreakCharacters - Characters that start new identifiers 978296417Sdim string BreakCharacters = ""; 979198090Srdivacky} 980234353Sdimdef DefaultAsmParserVariant : AsmParserVariant; 981198090Srdivacky 982218893Sdim/// AssemblerPredicate - This is a Predicate that can be used when the assembler 983218893Sdim/// matches instructions and aliases. 984239462Sdimclass AssemblerPredicate<string cond, string name = ""> { 985218893Sdim bit AssemblerMatcherPredicate = 1; 986224145Sdim string AssemblerCondString = cond; 987239462Sdim string PredicateName = name; 988218893Sdim} 989198090Srdivacky 990234353Sdim/// TokenAlias - This class allows targets to define assembler token 991234353Sdim/// operand aliases. That is, a token literal operand which is equivalent 992234353Sdim/// to another, canonical, token literal. For example, ARM allows: 993234353Sdim/// vmov.u32 s4, #0 -> vmov.i32, #0 994234353Sdim/// 'u32' is a more specific designator for the 32-bit integer type specifier 995234353Sdim/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 996234353Sdim/// def : TokenAlias<".u32", ".i32">; 997234353Sdim/// 998234353Sdim/// This works by marking the match class of 'From' as a subclass of the 999234353Sdim/// match class of 'To'. 1000234353Sdimclass TokenAlias<string From, string To> { 1001234353Sdim string FromToken = From; 1002234353Sdim string ToToken = To; 1003234353Sdim} 1004218893Sdim 1005218893Sdim/// MnemonicAlias - This class allows targets to define assembler mnemonic 1006218893Sdim/// aliases. This should be used when all forms of one mnemonic are accepted 1007218893Sdim/// with a different mnemonic. For example, X86 allows: 1008218893Sdim/// sal %al, 1 -> shl %al, 1 1009218893Sdim/// sal %ax, %cl -> shl %ax, %cl 1010218893Sdim/// sal %eax, %cl -> shl %eax, %cl 1011218893Sdim/// etc. Though "sal" is accepted with many forms, all of them are directly 1012218893Sdim/// translated to a shl, so it can be handled with (in the case of X86, it 1013218893Sdim/// actually has one for each suffix as well): 1014218893Sdim/// def : MnemonicAlias<"sal", "shl">; 1015218893Sdim/// 1016218893Sdim/// Mnemonic aliases are mapped before any other translation in the match phase, 1017218893Sdim/// and do allow Requires predicates, e.g.: 1018218893Sdim/// 1019218893Sdim/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 1020218893Sdim/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 1021218893Sdim/// 1022251662Sdim/// Mnemonic aliases can also be constrained to specific variants, e.g.: 1023251662Sdim/// 1024251662Sdim/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 1025251662Sdim/// 1026251662Sdim/// If no variant (e.g., "att" or "intel") is specified then the alias is 1027251662Sdim/// applied unconditionally. 1028251662Sdimclass MnemonicAlias<string From, string To, string VariantName = ""> { 1029218893Sdim string FromMnemonic = From; 1030218893Sdim string ToMnemonic = To; 1031251662Sdim string AsmVariantName = VariantName; 1032218893Sdim 1033218893Sdim // Predicates - Predicates that must be true for this remapping to happen. 1034218893Sdim list<Predicate> Predicates = []; 1035218893Sdim} 1036218893Sdim 1037218893Sdim/// InstAlias - This defines an alternate assembly syntax that is allowed to 1038218893Sdim/// match an instruction that has a different (more canonical) assembly 1039218893Sdim/// representation. 1040276479Sdimclass InstAlias<string Asm, dag Result, int Emit = 1> { 1041218893Sdim string AsmString = Asm; // The .s format to match the instruction with. 1042218893Sdim dag ResultInst = Result; // The MCInst to generate. 1043218893Sdim 1044276479Sdim // This determines which order the InstPrinter detects aliases for 1045276479Sdim // printing. A larger value makes the alias more likely to be 1046276479Sdim // emitted. The Instruction's own definition is notionally 0.5, so 0 1047276479Sdim // disables printing and 1 enables it if there are no conflicting aliases. 1048276479Sdim int EmitPriority = Emit; 1049276479Sdim 1050218893Sdim // Predicates - Predicates that must be true for this to match. 1051218893Sdim list<Predicate> Predicates = []; 1052288943Sdim 1053288943Sdim // If the instruction specified in Result has defined an AsmMatchConverter 1054288943Sdim // then setting this to 1 will cause the alias to use the AsmMatchConverter 1055288943Sdim // function when converting the OperandVector into an MCInst instead of the 1056288943Sdim // function that is generated by the dag Result. 1057288943Sdim // Setting this to 0 will cause the alias to ignore the Result instruction's 1058288943Sdim // defined AsmMatchConverter and instead use the function generated by the 1059288943Sdim // dag Result. 1060288943Sdim bit UseInstAsmMatchConverter = 1; 1061218893Sdim} 1062218893Sdim 1063198090Srdivacky//===----------------------------------------------------------------------===// 1064193323Sed// AsmWriter - This class can be implemented by targets that need to customize 1065193323Sed// the format of the .s file writer. 1066193323Sed// 1067193323Sed// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 1068193323Sed// on X86 for example). 1069193323Sed// 1070193323Sedclass AsmWriter { 1071193323Sed // AsmWriterClassName - This specifies the suffix to use for the asmwriter 1072193323Sed // class. Generated AsmWriter classes are always prefixed with the target 1073193323Sed // name. 1074276479Sdim string AsmWriterClassName = "InstPrinter"; 1075193323Sed 1076288943Sdim // PassSubtarget - Determines whether MCSubtargetInfo should be passed to 1077288943Sdim // the various print methods. 1078288943Sdim // FIXME: Remove after all ports are updated. 1079288943Sdim int PassSubtarget = 0; 1080288943Sdim 1081193323Sed // Variant - AsmWriters can be of multiple different variants. Variants are 1082193323Sed // used to support targets that need to emit assembly code in ways that are 1083193323Sed // mostly the same for different targets, but have minor differences in 1084193323Sed // syntax. If the asmstring contains {|} characters in them, this integer 1085193323Sed // will specify which alternative to use. For example "{x|y|z}" with Variant 1086193323Sed // == 1, will expand to "y". 1087193323Sed int Variant = 0; 1088193323Sed} 1089193323Seddef DefaultAsmWriter : AsmWriter; 1090193323Sed 1091193323Sed 1092193323Sed//===----------------------------------------------------------------------===// 1093193323Sed// Target - This class contains the "global" target information 1094193323Sed// 1095193323Sedclass Target { 1096193323Sed // InstructionSet - Instruction set description for this target. 1097193323Sed InstrInfo InstructionSet; 1098193323Sed 1099198090Srdivacky // AssemblyParsers - The AsmParser instances available for this target. 1100198090Srdivacky list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 1101198090Srdivacky 1102239462Sdim /// AssemblyParserVariants - The AsmParserVariant instances available for 1103234353Sdim /// this target. 1104234353Sdim list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; 1105234353Sdim 1106193323Sed // AssemblyWriters - The AsmWriter instances available for this target. 1107193323Sed list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 1108193323Sed} 1109193323Sed 1110193323Sed//===----------------------------------------------------------------------===// 1111193323Sed// SubtargetFeature - A characteristic of the chip set. 1112193323Sed// 1113193323Sedclass SubtargetFeature<string n, string a, string v, string d, 1114193323Sed list<SubtargetFeature> i = []> { 1115193323Sed // Name - Feature name. Used by command line (-mattr=) to determine the 1116193323Sed // appropriate target chip. 1117193323Sed // 1118193323Sed string Name = n; 1119218893Sdim 1120193323Sed // Attribute - Attribute to be set by feature. 1121193323Sed // 1122193323Sed string Attribute = a; 1123218893Sdim 1124193323Sed // Value - Value the attribute to be set to by feature. 1125193323Sed // 1126193323Sed string Value = v; 1127218893Sdim 1128193323Sed // Desc - Feature description. Used by command line (-mattr=) to display help 1129193323Sed // information. 1130193323Sed // 1131193323Sed string Desc = d; 1132193323Sed 1133193323Sed // Implies - Features that this feature implies are present. If one of those 1134193323Sed // features isn't set, then this one shouldn't be set either. 1135193323Sed // 1136193323Sed list<SubtargetFeature> Implies = i; 1137193323Sed} 1138193323Sed 1139261991Sdim/// Specifies a Subtarget feature that this instruction is deprecated on. 1140261991Sdimclass Deprecated<SubtargetFeature dep> { 1141261991Sdim SubtargetFeature DeprecatedFeatureMask = dep; 1142261991Sdim} 1143261991Sdim 1144261991Sdim/// A custom predicate used to determine if an instruction is 1145261991Sdim/// deprecated or not. 1146261991Sdimclass ComplexDeprecationPredicate<string dep> { 1147261991Sdim string ComplexDeprecationPredicate = dep; 1148261991Sdim} 1149261991Sdim 1150193323Sed//===----------------------------------------------------------------------===// 1151193323Sed// Processor chip sets - These values represent each of the chip sets supported 1152193323Sed// by the scheduler. Each Processor definition requires corresponding 1153193323Sed// instruction itineraries. 1154193323Sed// 1155193323Sedclass Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 1156193323Sed // Name - Chip set name. Used by command line (-mcpu=) to determine the 1157193323Sed // appropriate target chip. 1158193323Sed // 1159193323Sed string Name = n; 1160218893Sdim 1161239462Sdim // SchedModel - The machine model for scheduling and instruction cost. 1162239462Sdim // 1163239462Sdim SchedMachineModel SchedModel = NoSchedModel; 1164239462Sdim 1165193323Sed // ProcItin - The scheduling information for the target processor. 1166193323Sed // 1167193323Sed ProcessorItineraries ProcItin = pi; 1168218893Sdim 1169218893Sdim // Features - list of 1170193323Sed list<SubtargetFeature> Features = f; 1171193323Sed} 1172193323Sed 1173239462Sdim// ProcessorModel allows subtargets to specify the more general 1174239462Sdim// SchedMachineModel instead if a ProcessorItinerary. Subtargets will 1175239462Sdim// gradually move to this newer form. 1176243830Sdim// 1177243830Sdim// Although this class always passes NoItineraries to the Processor 1178243830Sdim// class, the SchedMachineModel may still define valid Itineraries. 1179239462Sdimclass ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f> 1180239462Sdim : Processor<n, NoItineraries, f> { 1181239462Sdim let SchedModel = m; 1182239462Sdim} 1183239462Sdim 1184193323Sed//===----------------------------------------------------------------------===// 1185243830Sdim// InstrMapping - This class is used to create mapping tables to relate 1186243830Sdim// instructions with each other based on the values specified in RowFields, 1187243830Sdim// ColFields, KeyCol and ValueCols. 1188243830Sdim// 1189243830Sdimclass InstrMapping { 1190243830Sdim // FilterClass - Used to limit search space only to the instructions that 1191243830Sdim // define the relationship modeled by this InstrMapping record. 1192243830Sdim string FilterClass; 1193243830Sdim 1194243830Sdim // RowFields - List of fields/attributes that should be same for all the 1195243830Sdim // instructions in a row of the relation table. Think of this as a set of 1196243830Sdim // properties shared by all the instructions related by this relationship 1197243830Sdim // model and is used to categorize instructions into subgroups. For instance, 1198243830Sdim // if we want to define a relation that maps 'Add' instruction to its 1199243830Sdim // predicated forms, we can define RowFields like this: 1200243830Sdim // 1201243830Sdim // let RowFields = BaseOp 1202243830Sdim // All add instruction predicated/non-predicated will have to set their BaseOp 1203243830Sdim // to the same value. 1204243830Sdim // 1205243830Sdim // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' } 1206243830Sdim // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' } 1207243830Sdim // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' } 1208243830Sdim list<string> RowFields = []; 1209243830Sdim 1210243830Sdim // List of fields/attributes that are same for all the instructions 1211243830Sdim // in a column of the relation table. 1212243830Sdim // Ex: let ColFields = 'predSense' -- It means that the columns are arranged 1213243830Sdim // based on the 'predSense' values. All the instruction in a specific 1214243830Sdim // column have the same value and it is fixed for the column according 1215243830Sdim // to the values set in 'ValueCols'. 1216243830Sdim list<string> ColFields = []; 1217243830Sdim 1218243830Sdim // Values for the fields/attributes listed in 'ColFields'. 1219243830Sdim // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction 1220243830Sdim // that models this relation) should be non-predicated. 1221243830Sdim // In the example above, 'Add' is the key instruction. 1222243830Sdim list<string> KeyCol = []; 1223243830Sdim 1224243830Sdim // List of values for the fields/attributes listed in 'ColFields', one for 1225243830Sdim // each column in the relation table. 1226243830Sdim // 1227243830Sdim // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the 1228243830Sdim // table. First column requires all the instructions to have predSense 1229243830Sdim // set to 'true' and second column requires it to be 'false'. 1230243830Sdim list<list<string> > ValueCols = []; 1231243830Sdim} 1232243830Sdim 1233243830Sdim//===----------------------------------------------------------------------===// 1234193323Sed// Pull in the common support for calling conventions. 1235193323Sed// 1236193323Sedinclude "llvm/Target/TargetCallingConv.td" 1237193323Sed 1238193323Sed//===----------------------------------------------------------------------===// 1239193323Sed// Pull in the common support for DAG isel generation. 1240193323Sed// 1241193323Sedinclude "llvm/Target/TargetSelectionDAG.td" 1242