rtl.def revision 258428
1/* This file contains the definitions and documentation for the 2 Register Transfer Expressions (rtx's) that make up the 3 Register Transfer Language (rtl) used in the Back End of the GNU compiler. 4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004, 5 2005, 2006 6 Free Software Foundation, Inc. 7 8This file is part of GCC. 9 10GCC is free software; you can redistribute it and/or modify it under 11the terms of the GNU General Public License as published by the Free 12Software Foundation; either version 2, or (at your option) any later 13version. 14 15GCC is distributed in the hope that it will be useful, but WITHOUT ANY 16WARRANTY; without even the implied warranty of MERCHANTABILITY or 17FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18for more details. 19 20You should have received a copy of the GNU General Public License 21along with GCC; see the file COPYING. If not, write to the Free 22Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 2302110-1301, USA. */ 24 25 26/* Expression definitions and descriptions for all targets are in this file. 27 Some will not be used for some targets. 28 29 The fields in the cpp macro call "DEF_RTL_EXPR()" 30 are used to create declarations in the C source of the compiler. 31 32 The fields are: 33 34 1. The internal name of the rtx used in the C source. 35 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". 36 By convention these are in UPPER_CASE. 37 38 2. The name of the rtx in the external ASCII format read by 39 read_rtx(), and printed by print_rtx(). 40 These names are stored in rtx_name[]. 41 By convention these are the internal (field 1) names in lower_case. 42 43 3. The print format, and type of each rtx->u.fld[] (field) in this rtx. 44 These formats are stored in rtx_format[]. 45 The meaning of the formats is documented in front of this array in rtl.c 46 47 4. The class of the rtx. These are stored in rtx_class and are accessed 48 via the GET_RTX_CLASS macro. They are defined as follows: 49 50 RTX_CONST_OBJ 51 an rtx code that can be used to represent a constant object 52 (e.g, CONST_INT) 53 RTX_OBJ 54 an rtx code that can be used to represent an object (e.g, REG, MEM) 55 RTX_COMPARE 56 an rtx code for a comparison (e.g, LT, GT) 57 RTX_COMM_COMPARE 58 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED) 59 RTX_UNARY 60 an rtx code for a unary arithmetic expression (e.g, NEG, NOT) 61 RTX_COMM_ARITH 62 an rtx code for a commutative binary operation (e.g,, PLUS, MULT) 63 RTX_TERNARY 64 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) 65 RTX_BIN_ARITH 66 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) 67 RTX_BITFIELD_OPS 68 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) 69 RTX_INSN 70 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) 71 RTX_MATCH 72 an rtx code for something that matches in insns (e.g, MATCH_DUP) 73 RTX_AUTOINC 74 an rtx code for autoincrement addressing modes (e.g. POST_DEC) 75 RTX_EXTRA 76 everything else 77 78 All of the expressions that appear only in machine descriptions, 79 not in RTL used by the compiler itself, are at the end of the file. */ 80 81/* Unknown, or no such operation; the enumeration constant should have 82 value zero. */ 83DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA) 84 85/* --------------------------------------------------------------------- 86 Expressions used in constructing lists. 87 --------------------------------------------------------------------- */ 88 89/* a linked list of expressions */ 90DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA) 91 92/* a linked list of instructions. 93 The insns are represented in print by their uids. */ 94DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA) 95 96/* a linked list of dependencies. 97 The insns are represented in print by their uids. 98 Operand 2 is the status of a dependence (see sched-int.h for more). */ 99DEF_RTL_EXPR(DEPS_LIST, "deps_list", "uei", RTX_EXTRA) 100 101/* SEQUENCE appears in the result of a `gen_...' function 102 for a DEFINE_EXPAND that wants to make several insns. 103 Its elements are the bodies of the insns that should be made. 104 `emit_insn' takes the SEQUENCE apart and makes separate insns. */ 105DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA) 106 107/* Refers to the address of its argument. This is only used in alias.c. */ 108DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH) 109 110/* ---------------------------------------------------------------------- 111 Expression types used for things in the instruction chain. 112 113 All formats must start with "iuu" to handle the chain. 114 Each insn expression holds an rtl instruction and its semantics 115 during back-end processing. 116 See macros's in "rtl.h" for the meaning of each rtx->u.fld[]. 117 118 ---------------------------------------------------------------------- */ 119 120/* An instruction that cannot jump. */ 121DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN) 122 123/* An instruction that can possibly jump. 124 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ 125DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN) 126 127/* An instruction that can possibly call a subroutine 128 but which will not change which instruction comes next 129 in the current function. 130 Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE. 131 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ 132DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN) 133 134/* A marker that indicates that control will not flow through. */ 135DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA) 136 137/* Holds a label that is followed by instructions. 138 Operand: 139 4: is used in jump.c for the use-count of the label. 140 5: is used in flow.c to point to the chain of label_ref's to this label. 141 6: is a number that is unique in the entire compilation. 142 7: is the user-given name of the label, if any. */ 143DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA) 144 145#ifdef USE_MAPPED_LOCATION 146/* Say where in the code a source line starts, for symbol table's sake. 147 Operand: 148 4: unused if line number > 0, note-specific data otherwise. 149 5: line number if > 0, enum note_insn otherwise. 150 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */ 151#else 152/* Say where in the code a source line starts, for symbol table's sake. 153 Operand: 154 4: filename, if line number > 0, note-specific data otherwise. 155 5: line number if > 0, enum note_insn otherwise. 156 6: unique number if line number == note_insn_deleted_label. */ 157#endif 158DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA) 159 160/* ---------------------------------------------------------------------- 161 Top level constituents of INSN, JUMP_INSN and CALL_INSN. 162 ---------------------------------------------------------------------- */ 163 164/* Conditionally execute code. 165 Operand 0 is the condition that if true, the code is executed. 166 Operand 1 is the code to be executed (typically a SET). 167 168 Semantics are that there are no side effects if the condition 169 is false. This pattern is created automatically by the if_convert 170 pass run after reload or by target-specific splitters. */ 171DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA) 172 173/* Several operations to be done in parallel (perhaps under COND_EXEC). */ 174DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA) 175 176/* A string that is passed through to the assembler as input. 177 One can obviously pass comments through by using the 178 assembler comment syntax. 179 These occur in an insn all by themselves as the PATTERN. 180 They also appear inside an ASM_OPERANDS 181 as a convenient way to hold a string. */ 182DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA) 183 184#ifdef USE_MAPPED_LOCATION 185/* An assembler instruction with operands. 186 1st operand is the instruction template. 187 2nd operand is the constraint for the output. 188 3rd operand is the number of the output this expression refers to. 189 When an insn stores more than one value, a separate ASM_OPERANDS 190 is made for each output; this integer distinguishes them. 191 4th is a vector of values of input operands. 192 5th is a vector of modes and constraints for the input operands. 193 Each element is an ASM_INPUT containing a constraint string 194 and whose mode indicates the mode of the input operand. 195 6th is the source line number. */ 196DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA) 197#else 198/* An assembler instruction with operands. 199 1st operand is the instruction template. 200 2nd operand is the constraint for the output. 201 3rd operand is the number of the output this expression refers to. 202 When an insn stores more than one value, a separate ASM_OPERANDS 203 is made for each output; this integer distinguishes them. 204 4th is a vector of values of input operands. 205 5th is a vector of modes and constraints for the input operands. 206 Each element is an ASM_INPUT containing a constraint string 207 and whose mode indicates the mode of the input operand. 208 6th is the name of the containing source file. 209 7th is the source line number. */ 210DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA) 211#endif 212 213/* A machine-specific operation. 214 1st operand is a vector of operands being used by the operation so that 215 any needed reloads can be done. 216 2nd operand is a unique value saying which of a number of machine-specific 217 operations is to be performed. 218 (Note that the vector must be the first operand because of the way that 219 genrecog.c record positions within an insn.) 220 This can occur all by itself in a PATTERN, as a component of a PARALLEL, 221 or inside an expression. */ 222DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA) 223 224/* Similar, but a volatile operation and one which may trap. */ 225DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA) 226 227/* Vector of addresses, stored as full words. */ 228/* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ 229DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA) 230 231/* Vector of address differences X0 - BASE, X1 - BASE, ... 232 First operand is BASE; the vector contains the X's. 233 The machine mode of this rtx says how much space to leave 234 for each difference and is adjusted by branch shortening if 235 CASE_VECTOR_SHORTEN_MODE is defined. 236 The third and fourth operands store the target labels with the 237 minimum and maximum addresses respectively. 238 The fifth operand stores flags for use by branch shortening. 239 Set at the start of shorten_branches: 240 min_align: the minimum alignment for any of the target labels. 241 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. 242 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. 243 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. 244 min_after_base: true iff minimum address target label is after BASE. 245 max_after_base: true iff maximum address target label is after BASE. 246 Set by the actual branch shortening process: 247 offset_unsigned: true iff offsets have to be treated as unsigned. 248 scale: scaling that is necessary to make offsets fit into the mode. 249 250 The third, fourth and fifth operands are only valid when 251 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing 252 compilations. */ 253 254DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA) 255 256/* Memory prefetch, with attributes supported on some targets. 257 Operand 1 is the address of the memory to fetch. 258 Operand 2 is 1 for a write access, 0 otherwise. 259 Operand 3 is the level of temporal locality; 0 means there is no 260 temporal locality and 1, 2, and 3 are for increasing levels of temporal 261 locality. 262 263 The attributes specified by operands 2 and 3 are ignored for targets 264 whose prefetch instructions do not support them. */ 265DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA) 266 267/* ---------------------------------------------------------------------- 268 At the top level of an instruction (perhaps under PARALLEL). 269 ---------------------------------------------------------------------- */ 270 271/* Assignment. 272 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. 273 Operand 2 is the value stored there. 274 ALL assignment must use SET. 275 Instructions that do multiple assignments must use multiple SET, 276 under PARALLEL. */ 277DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA) 278 279/* Indicate something is used in a way that we don't want to explain. 280 For example, subroutine calls will use the register 281 in which the static chain is passed. */ 282DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA) 283 284/* Indicate something is clobbered in a way that we don't want to explain. 285 For example, subroutine calls will clobber some physical registers 286 (the ones that are by convention not saved). */ 287DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA) 288 289/* Call a subroutine. 290 Operand 1 is the address to call. 291 Operand 2 is the number of arguments. */ 292 293DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA) 294 295/* Return from a subroutine. */ 296 297DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA) 298 299/* Conditional trap. 300 Operand 1 is the condition. 301 Operand 2 is the trap code. 302 For an unconditional trap, make the condition (const_int 1). */ 303DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA) 304 305/* Placeholder for _Unwind_Resume before we know if a function call 306 or a branch is needed. Operand 1 is the exception region from 307 which control is flowing. */ 308DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA) 309 310/* ---------------------------------------------------------------------- 311 Primitive values for use in expressions. 312 ---------------------------------------------------------------------- */ 313 314/* numeric integer constant */ 315DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ) 316 317/* numeric floating point constant. 318 Operands hold the value. They are all 'w' and there may be from 2 to 6; 319 see real.h. */ 320DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ) 321 322/* Describes a vector constant. */ 323DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ) 324 325/* String constant. Used for attributes in machine descriptions and 326 for special cases in DWARF2 debug output. NOT used for source- 327 language string constants. */ 328DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ) 329 330/* This is used to encapsulate an expression whose value is constant 331 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be 332 recognized as a constant operand rather than by arithmetic instructions. */ 333 334DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ) 335 336/* program counter. Ordinary jumps are represented 337 by a SET whose first operand is (PC). */ 338DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ) 339 340/* Used in the cselib routines to describe a value. Objects of this 341 kind are only allocated in cselib.c, in an alloc pool instead of 342 in GC memory. The only operand of a VALUE is a cselib_val_struct. */ 343DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ) 344 345/* A register. The "operand" is the register number, accessed with 346 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER 347 than a hardware register is being referred to. The second operand 348 holds the original register number - this will be different for a 349 pseudo register that got turned into a hard register. The third 350 operand points to a reg_attrs structure. 351 This rtx needs to have as many (or more) fields as a MEM, since we 352 can change REG rtx's into MEMs during reload. */ 353DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ) 354 355/* A scratch register. This represents a register used only within a 356 single insn. It will be turned into a REG during register allocation 357 or reload unless the constraint indicates that the register won't be 358 needed, in which case it can remain a SCRATCH. This code is 359 marked as having one operand so it can be turned into a REG. */ 360DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ) 361 362/* One word of a multi-word value. 363 The first operand is the complete value; the second says which word. 364 The WORDS_BIG_ENDIAN flag controls whether word number 0 365 (as numbered in a SUBREG) is the most or least significant word. 366 367 This is also used to refer to a value in a different machine mode. 368 For example, it can be used to refer to a SImode value as if it were 369 Qimode, or vice versa. Then the word number is always 0. */ 370DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA) 371 372/* This one-argument rtx is used for move instructions 373 that are guaranteed to alter only the low part of a destination. 374 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) 375 has an unspecified effect on the high part of REG, 376 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) 377 is guaranteed to alter only the bits of REG that are in HImode. 378 379 The actual instruction used is probably the same in both cases, 380 but the register constraints may be tighter when STRICT_LOW_PART 381 is in use. */ 382 383DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA) 384 385/* (CONCAT a b) represents the virtual concatenation of a and b 386 to make a value that has as many bits as a and b put together. 387 This is used for complex values. Normally it appears only 388 in DECL_RTLs and during RTL generation, but not in the insn chain. */ 389DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ) 390 391/* A memory location; operand is the address. The second operand is the 392 alias set to which this MEM belongs. We use `0' instead of `w' for this 393 field so that the field need not be specified in machine descriptions. */ 394DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ) 395 396/* Reference to an assembler label in the code for this function. 397 The operand is a CODE_LABEL found in the insn chain. */ 398DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ) 399 400/* Reference to a named label: 401 Operand 0: label name 402 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h) 403 Operand 2: tree from which this symbol is derived, or null. 404 This is either a DECL node, or some kind of constant. */ 405DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ) 406 407/* The condition code register is represented, in our imagination, 408 as a register holding a value that can be compared to zero. 409 In fact, the machine has already compared them and recorded the 410 results; but instructions that look at the condition code 411 pretend to be looking at the entire value and comparing it. */ 412DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ) 413 414/* ---------------------------------------------------------------------- 415 Expressions for operators in an rtl pattern 416 ---------------------------------------------------------------------- */ 417 418/* if_then_else. This is used in representing ordinary 419 conditional jump instructions. 420 Operand: 421 0: condition 422 1: then expr 423 2: else expr */ 424DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY) 425 426/* Comparison, produces a condition code result. */ 427DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH) 428 429/* plus */ 430DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH) 431 432/* Operand 0 minus operand 1. */ 433DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH) 434 435/* Minus operand 0. */ 436DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY) 437 438DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH) 439 440/* Operand 0 divided by operand 1. */ 441DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH) 442/* Remainder of operand 0 divided by operand 1. */ 443DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH) 444 445/* Unsigned divide and remainder. */ 446DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH) 447DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH) 448 449/* Bitwise operations. */ 450DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH) 451DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH) 452DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH) 453DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY) 454 455/* Operand: 456 0: value to be shifted. 457 1: number of bits. */ 458DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */ 459DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */ 460DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */ 461DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */ 462DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */ 463 464/* Minimum and maximum values of two operands. We need both signed and 465 unsigned forms. (We cannot use MIN for SMIN because it conflicts 466 with a macro of the same name.) The signed variants should be used 467 with floating point. Further, if both operands are zeros, or if either 468 operand is NaN, then it is unspecified which of the two operands is 469 returned as the result. */ 470 471DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH) 472DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH) 473DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH) 474DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH) 475 476/* These unary operations are used to represent incrementation 477 and decrementation as they occur in memory addresses. 478 The amount of increment or decrement are not represented 479 because they can be understood from the machine-mode of the 480 containing MEM. These operations exist in only two cases: 481 1. pushes onto the stack. 482 2. created automatically by the life_analysis pass in flow.c. */ 483DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC) 484DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC) 485DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC) 486DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC) 487 488/* These binary operations are used to represent generic address 489 side-effects in memory addresses, except for simple incrementation 490 or decrementation which use the above operations. They are 491 created automatically by the life_analysis pass in flow.c. 492 The first operand is a REG which is used as the address. 493 The second operand is an expression that is assigned to the 494 register, either before (PRE_MODIFY) or after (POST_MODIFY) 495 evaluating the address. 496 Currently, the compiler can only handle second operands of the 497 form (plus (reg) (reg)) and (plus (reg) (const_int)), where 498 the first operand of the PLUS has to be the same register as 499 the first operand of the *_MODIFY. */ 500DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC) 501DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC) 502 503/* Comparison operations. The ordered comparisons exist in two 504 flavors, signed and unsigned. */ 505DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE) 506DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE) 507DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE) 508DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE) 509DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE) 510DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE) 511DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE) 512DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE) 513DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE) 514DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE) 515 516/* Additional floating point unordered comparison flavors. */ 517DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE) 518DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE) 519 520/* These are equivalent to unordered or ... */ 521DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE) 522DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE) 523DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE) 524DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE) 525DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE) 526 527/* This is an ordered NE, ie !UNEQ, ie false for NaN. */ 528DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE) 529 530/* Represents the result of sign-extending the sole operand. 531 The machine modes of the operand and of the SIGN_EXTEND expression 532 determine how much sign-extension is going on. */ 533DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY) 534 535/* Similar for zero-extension (such as unsigned short to int). */ 536DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY) 537 538/* Similar but here the operand has a wider mode. */ 539DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY) 540 541/* Similar for extending floating-point values (such as SFmode to DFmode). */ 542DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY) 543DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY) 544 545/* Conversion of fixed point operand to floating point value. */ 546DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY) 547 548/* With fixed-point machine mode: 549 Conversion of floating point operand to fixed point value. 550 Value is defined only when the operand's value is an integer. 551 With floating-point machine mode (and operand with same mode): 552 Operand is rounded toward zero to produce an integer value 553 represented in floating point. */ 554DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY) 555 556/* Conversion of unsigned fixed point operand to floating point value. */ 557DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY) 558 559/* With fixed-point machine mode: 560 Conversion of floating point operand to *unsigned* fixed point value. 561 Value is defined only when the operand's value is an integer. */ 562DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY) 563 564/* Absolute value */ 565DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY) 566 567/* Square root */ 568DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY) 569 570/* Swap bytes. */ 571DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY) 572 573/* Find first bit that is set. 574 Value is 1 + number of trailing zeros in the arg., 575 or 0 if arg is 0. */ 576DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY) 577 578/* Count leading zeros. */ 579DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY) 580 581/* Count trailing zeros. */ 582DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY) 583 584/* Population count (number of 1 bits). */ 585DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY) 586 587/* Population parity (number of 1 bits modulo 2). */ 588DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY) 589 590/* Reference to a signed bit-field of specified size and position. 591 Operand 0 is the memory unit (usually SImode or QImode) which 592 contains the field's first bit. Operand 1 is the width, in bits. 593 Operand 2 is the number of bits in the memory unit before the 594 first bit of this field. 595 If BITS_BIG_ENDIAN is defined, the first bit is the msb and 596 operand 2 counts from the msb of the memory unit. 597 Otherwise, the first bit is the lsb and operand 2 counts from 598 the lsb of the memory unit. 599 This kind of expression can not appear as an lvalue in RTL. */ 600DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS) 601 602/* Similar for unsigned bit-field. 603 But note! This kind of expression _can_ appear as an lvalue. */ 604DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS) 605 606/* For RISC machines. These save memory when splitting insns. */ 607 608/* HIGH are the high-order bits of a constant expression. */ 609DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ) 610 611/* LO_SUM is the sum of a register and the low-order bits 612 of a constant expression. */ 613DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ) 614 615/* Describes a merge operation between two vector values. 616 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask 617 that specifies where the parts of the result are taken from. Set bits 618 indicate operand 0, clear bits indicate operand 1. The parts are defined 619 by the mode of the vectors. */ 620DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY) 621 622/* Describes an operation that selects parts of a vector. 623 Operands 0 is the source vector, operand 1 is a PARALLEL that contains 624 a CONST_INT for each of the subparts of the result vector, giving the 625 number of the source subpart that should be stored into it. */ 626DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH) 627 628/* Describes a vector concat operation. Operands 0 and 1 are the source 629 vectors, the result is a vector that is as long as operands 0 and 1 630 combined and is the concatenation of the two source vectors. */ 631DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH) 632 633/* Describes an operation that converts a small vector into a larger one by 634 duplicating the input values. The output vector mode must have the same 635 submodes as the input vector mode, and the number of output parts must be 636 an integer multiple of the number of input parts. */ 637DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY) 638 639/* Addition with signed saturation */ 640DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH) 641 642/* Addition with unsigned saturation */ 643DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH) 644 645/* Operand 0 minus operand 1, with signed saturation. */ 646DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH) 647 648/* Negation with signed saturation. */ 649DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY) 650 651/* Shift left with signed saturation. */ 652DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH) 653 654/* Operand 0 minus operand 1, with unsigned saturation. */ 655DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH) 656 657/* Signed saturating truncate. */ 658DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY) 659 660/* Unsigned saturating truncate. */ 661DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY) 662 663/* Information about the variable and its location. */ 664DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA) 665 666/* All expressions from this point forward appear only in machine 667 descriptions. */ 668#ifdef GENERATOR_FILE 669 670/* Include a secondary machine-description file at this point. */ 671DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA) 672 673/* Pattern-matching operators: */ 674 675/* Use the function named by the second arg (the string) 676 as a predicate; if matched, store the structure that was matched 677 in the operand table at index specified by the first arg (the integer). 678 If the second arg is the null string, the structure is just stored. 679 680 A third string argument indicates to the register allocator restrictions 681 on where the operand can be allocated. 682 683 If the target needs no restriction on any instruction this field should 684 be the null string. 685 686 The string is prepended by: 687 '=' to indicate the operand is only written to. 688 '+' to indicate the operand is both read and written to. 689 690 Each character in the string represents an allocable class for an operand. 691 'g' indicates the operand can be any valid class. 692 'i' indicates the operand can be immediate (in the instruction) data. 693 'r' indicates the operand can be in a register. 694 'm' indicates the operand can be in memory. 695 'o' a subset of the 'm' class. Those memory addressing modes that 696 can be offset at compile time (have a constant added to them). 697 698 Other characters indicate target dependent operand classes and 699 are described in each target's machine description. 700 701 For instructions with more than one operand, sets of classes can be 702 separated by a comma to indicate the appropriate multi-operand constraints. 703 There must be a 1 to 1 correspondence between these sets of classes in 704 all operands for an instruction. 705 */ 706DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH) 707 708/* Match a SCRATCH or a register. When used to generate rtl, a 709 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies 710 the desired mode and the first argument is the operand number. 711 The second argument is the constraint. */ 712DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH) 713 714/* Apply a predicate, AND match recursively the operands of the rtx. 715 Operand 0 is the operand-number, as in match_operand. 716 Operand 1 is a predicate to apply (as a string, a function name). 717 Operand 2 is a vector of expressions, each of which must match 718 one subexpression of the rtx this construct is matching. */ 719DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH) 720 721/* Match a PARALLEL of arbitrary length. The predicate is applied 722 to the PARALLEL and the initial expressions in the PARALLEL are matched. 723 Operand 0 is the operand-number, as in match_operand. 724 Operand 1 is a predicate to apply to the PARALLEL. 725 Operand 2 is a vector of expressions, each of which must match the 726 corresponding element in the PARALLEL. */ 727DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH) 728 729/* Match only something equal to what is stored in the operand table 730 at the index specified by the argument. Use with MATCH_OPERAND. */ 731DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH) 732 733/* Match only something equal to what is stored in the operand table 734 at the index specified by the argument. Use with MATCH_OPERATOR. */ 735DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH) 736 737/* Match only something equal to what is stored in the operand table 738 at the index specified by the argument. Use with MATCH_PARALLEL. */ 739DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH) 740 741/* Appears only in define_predicate/define_special_predicate 742 expressions. Evaluates true only if the operand has an RTX code 743 from the set given by the argument (a comma-separated list). If the 744 second argument is present and nonempty, it is a sequence of digits 745 and/or letters which indicates the subexpression to test, using the 746 same syntax as genextract/genrecog's location strings: 0-9 for 747 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to 748 the result of the one before it. */ 749DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH) 750 751/* Appears only in define_predicate/define_special_predicate 752 expressions. The argument is a C expression to be injected at this 753 point in the predicate formula. */ 754DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH) 755 756/* Insn (and related) definitions. */ 757 758/* Definition of the pattern for one kind of instruction. 759 Operand: 760 0: names this instruction. 761 If the name is the null string, the instruction is in the 762 machine description just to be recognized, and will never be emitted by 763 the tree to rtl expander. 764 1: is the pattern. 765 2: is a string which is a C expression 766 giving an additional condition for recognizing this pattern. 767 A null string means no extra condition. 768 3: is the action to execute if this pattern is matched. 769 If this assembler code template starts with a * then it is a fragment of 770 C code to run to decide on a template to use. Otherwise, it is the 771 template to use. 772 4: optionally, a vector of attributes for this insn. 773 */ 774DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA) 775 776/* Definition of a peephole optimization. 777 1st operand: vector of insn patterns to match 778 2nd operand: C expression that must be true 779 3rd operand: template or C code to produce assembler output. 780 4: optionally, a vector of attributes for this insn. 781 782 This form is deprecated; use define_peephole2 instead. */ 783DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA) 784 785/* Definition of a split operation. 786 1st operand: insn pattern to match 787 2nd operand: C expression that must be true 788 3rd operand: vector of insn patterns to place into a SEQUENCE 789 4th operand: optionally, some C code to execute before generating the 790 insns. This might, for example, create some RTX's and store them in 791 elements of `recog_data.operand' for use by the vector of 792 insn-patterns. 793 (`operands' is an alias here for `recog_data.operand'). */ 794DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA) 795 796/* Definition of an insn and associated split. 797 This is the concatenation, with a few modifications, of a define_insn 798 and a define_split which share the same pattern. 799 Operand: 800 0: names this instruction. 801 If the name is the null string, the instruction is in the 802 machine description just to be recognized, and will never be emitted by 803 the tree to rtl expander. 804 1: is the pattern. 805 2: is a string which is a C expression 806 giving an additional condition for recognizing this pattern. 807 A null string means no extra condition. 808 3: is the action to execute if this pattern is matched. 809 If this assembler code template starts with a * then it is a fragment of 810 C code to run to decide on a template to use. Otherwise, it is the 811 template to use. 812 4: C expression that must be true for split. This may start with "&&" 813 in which case the split condition is the logical and of the insn 814 condition and what follows the "&&" of this operand. 815 5: vector of insn patterns to place into a SEQUENCE 816 6: optionally, some C code to execute before generating the 817 insns. This might, for example, create some RTX's and store them in 818 elements of `recog_data.operand' for use by the vector of 819 insn-patterns. 820 (`operands' is an alias here for `recog_data.operand'). 821 7: optionally, a vector of attributes for this insn. */ 822DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA) 823 824/* Definition of an RTL peephole operation. 825 Follows the same arguments as define_split. */ 826DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA) 827 828/* Define how to generate multiple insns for a standard insn name. 829 1st operand: the insn name. 830 2nd operand: vector of insn-patterns. 831 Use match_operand to substitute an element of `recog_data.operand'. 832 3rd operand: C expression that must be true for this to be available. 833 This may not test any operands. 834 4th operand: Extra C code to execute before generating the insns. 835 This might, for example, create some RTX's and store them in 836 elements of `recog_data.operand' for use by the vector of 837 insn-patterns. 838 (`operands' is an alias here for `recog_data.operand'). */ 839DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA) 840 841/* Define a requirement for delay slots. 842 1st operand: Condition involving insn attributes that, if true, 843 indicates that the insn requires the number of delay slots 844 shown. 845 2nd operand: Vector whose length is the three times the number of delay 846 slots required. 847 Each entry gives three conditions, each involving attributes. 848 The first must be true for an insn to occupy that delay slot 849 location. The second is true for all insns that can be 850 annulled if the branch is true and the third is true for all 851 insns that can be annulled if the branch is false. 852 853 Multiple DEFINE_DELAYs may be present. They indicate differing 854 requirements for delay slots. */ 855DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA) 856 857/* Define attribute computation for `asm' instructions. */ 858DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA) 859 860/* Definition of a conditional execution meta operation. Automatically 861 generates new instances of DEFINE_INSN, selected by having attribute 862 "predicable" true. The new pattern will contain a COND_EXEC and the 863 predicate at top-level. 864 865 Operand: 866 0: The predicate pattern. The top-level form should match a 867 relational operator. Operands should have only one alternative. 868 1: A C expression giving an additional condition for recognizing 869 the generated pattern. 870 2: A template or C code to produce assembler output. */ 871DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA) 872 873/* Definition of an operand predicate. The difference between 874 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will 875 not warn about a match_operand with no mode if it has a predicate 876 defined with DEFINE_SPECIAL_PREDICATE. 877 878 Operand: 879 0: The name of the predicate. 880 1: A boolean expression which computes whether or not the predicate 881 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND, 882 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog 883 can calculate the set of RTX codes that can possibly match. 884 2: A C function body which must return true for the predicate to match. 885 Optional. Use this when the test is too complicated to fit into a 886 match_test expression. */ 887DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA) 888DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA) 889 890/* Definition of a register operand constraint. This simply maps the 891 constraint string to a register class. 892 893 Operand: 894 0: The name of the constraint (often, but not always, a single letter). 895 1: A C expression which evaluates to the appropriate register class for 896 this constraint. If this is not just a constant, it should look only 897 at -m switches and the like. 898 2: A docstring for this constraint, in Texinfo syntax; not currently 899 used, in future will be incorporated into the manual's list of 900 machine-specific operand constraints. */ 901DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA) 902 903/* Definition of a non-register operand constraint. These look at the 904 operand and decide whether it fits the constraint. 905 906 DEFINE_CONSTRAINT gets no special treatment if it fails to match. 907 It is appropriate for constant-only constraints, and most others. 908 909 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made 910 to match, if it doesn't already, by converting the operand to the form 911 (mem (reg X)) where X is a base register. It is suitable for constraints 912 that describe a subset of all memory references. 913 914 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made 915 to match, if it doesn't already, by converting the operand to the form 916 (reg X) where X is a base register. It is suitable for constraints that 917 describe a subset of all address references. 918 919 When in doubt, use plain DEFINE_CONSTRAINT. 920 921 Operand: 922 0: The name of the constraint (often, but not always, a single letter). 923 1: A docstring for this constraint, in Texinfo syntax; not currently 924 used, in future will be incorporated into the manual's list of 925 machine-specific operand constraints. 926 2: A boolean expression which computes whether or not the constraint 927 matches. It should follow the same rules as a define_predicate 928 expression, including the bit about specifying the set of RTX codes 929 that could possibly match. MATCH_TEST subexpressions may make use of 930 these variables: 931 `op' - the RTL object defining the operand. 932 `mode' - the mode of `op'. 933 `ival' - INTVAL(op), if op is a CONST_INT. 934 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE. 935 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE. 936 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point 937 CONST_DOUBLE. 938 Do not use ival/hval/lval/rval if op is not the appropriate kind of 939 RTL object. */ 940DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA) 941DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA) 942DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA) 943 944 945/* Constructions for CPU pipeline description described by NDFAs. */ 946 947/* (define_cpu_unit string [string]) describes cpu functional 948 units (separated by comma). 949 950 1st operand: Names of cpu functional units. 951 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON). 952 953 All define_reservations, define_cpu_units, and 954 define_query_cpu_units should have unique names which may not be 955 "nothing". */ 956DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA) 957 958/* (define_query_cpu_unit string [string]) describes cpu functional 959 units analogously to define_cpu_unit. The reservation of such 960 units can be queried for automaton state. */ 961DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA) 962 963/* (exclusion_set string string) means that each CPU functional unit 964 in the first string can not be reserved simultaneously with any 965 unit whose name is in the second string and vise versa. CPU units 966 in the string are separated by commas. For example, it is useful 967 for description CPU with fully pipelined floating point functional 968 unit which can execute simultaneously only single floating point 969 insns or only double floating point insns. All CPU functional 970 units in a set should belong to the same automaton. */ 971DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA) 972 973/* (presence_set string string) means that each CPU functional unit in 974 the first string can not be reserved unless at least one of pattern 975 of units whose names are in the second string is reserved. This is 976 an asymmetric relation. CPU units or unit patterns in the strings 977 are separated by commas. Pattern is one unit name or unit names 978 separated by white-spaces. 979 980 For example, it is useful for description that slot1 is reserved 981 after slot0 reservation for a VLIW processor. We could describe it 982 by the following construction 983 984 (presence_set "slot1" "slot0") 985 986 Or slot1 is reserved only after slot0 and unit b0 reservation. In 987 this case we could write 988 989 (presence_set "slot1" "slot0 b0") 990 991 All CPU functional units in a set should belong to the same 992 automaton. */ 993DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA) 994 995/* (final_presence_set string string) is analogous to `presence_set'. 996 The difference between them is when checking is done. When an 997 instruction is issued in given automaton state reflecting all 998 current and planned unit reservations, the automaton state is 999 changed. The first state is a source state, the second one is a 1000 result state. Checking for `presence_set' is done on the source 1001 state reservation, checking for `final_presence_set' is done on the 1002 result reservation. This construction is useful to describe a 1003 reservation which is actually two subsequent reservations. For 1004 example, if we use 1005 1006 (presence_set "slot1" "slot0") 1007 1008 the following insn will be never issued (because slot1 requires 1009 slot0 which is absent in the source state). 1010 1011 (define_reservation "insn_and_nop" "slot0 + slot1") 1012 1013 but it can be issued if we use analogous `final_presence_set'. */ 1014DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA) 1015 1016/* (absence_set string string) means that each CPU functional unit in 1017 the first string can be reserved only if each pattern of units 1018 whose names are in the second string is not reserved. This is an 1019 asymmetric relation (actually exclusion set is analogous to this 1020 one but it is symmetric). CPU units or unit patterns in the string 1021 are separated by commas. Pattern is one unit name or unit names 1022 separated by white-spaces. 1023 1024 For example, it is useful for description that slot0 can not be 1025 reserved after slot1 or slot2 reservation for a VLIW processor. We 1026 could describe it by the following construction 1027 1028 (absence_set "slot2" "slot0, slot1") 1029 1030 Or slot2 can not be reserved if slot0 and unit b0 are reserved or 1031 slot1 and unit b1 are reserved . In this case we could write 1032 1033 (absence_set "slot2" "slot0 b0, slot1 b1") 1034 1035 All CPU functional units in a set should to belong the same 1036 automaton. */ 1037DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA) 1038 1039/* (final_absence_set string string) is analogous to `absence_set' but 1040 checking is done on the result (state) reservation. See comments 1041 for `final_presence_set'. */ 1042DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA) 1043 1044/* (define_bypass number out_insn_names in_insn_names) names bypass 1045 with given latency (the first number) from insns given by the first 1046 string (see define_insn_reservation) into insns given by the second 1047 string. Insn names in the strings are separated by commas. The 1048 third operand is optional name of function which is additional 1049 guard for the bypass. The function will get the two insns as 1050 parameters. If the function returns zero the bypass will be 1051 ignored for this case. Additional guard is necessary to recognize 1052 complicated bypasses, e.g. when consumer is load address. */ 1053DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA) 1054 1055/* (define_automaton string) describes names of automata generated and 1056 used for pipeline hazards recognition. The names are separated by 1057 comma. Actually it is possibly to generate the single automaton 1058 but unfortunately it can be very large. If we use more one 1059 automata, the summary size of the automata usually is less than the 1060 single one. The automaton name is used in define_cpu_unit and 1061 define_query_cpu_unit. All automata should have unique names. */ 1062DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA) 1063 1064/* (automata_option string) describes option for generation of 1065 automata. Currently there are the following options: 1066 1067 o "no-minimization" which makes no minimization of automata. This 1068 is only worth to do when we are debugging the description and 1069 need to look more accurately at reservations of states. 1070 1071 o "time" which means printing additional time statistics about 1072 generation of automata. 1073 1074 o "v" which means generation of file describing the result 1075 automata. The file has suffix `.dfa' and can be used for the 1076 description verification and debugging. 1077 1078 o "w" which means generation of warning instead of error for 1079 non-critical errors. 1080 1081 o "ndfa" which makes nondeterministic finite state automata. 1082 1083 o "progress" which means output of a progress bar showing how many 1084 states were generated so far for automaton being processed. */ 1085DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA) 1086 1087/* (define_reservation string string) names reservation (the first 1088 string) of cpu functional units (the 2nd string). Sometimes unit 1089 reservations for different insns contain common parts. In such 1090 case, you can describe common part and use its name (the 1st 1091 parameter) in regular expression in define_insn_reservation. All 1092 define_reservations, define_cpu_units, and define_query_cpu_units 1093 should have unique names which may not be "nothing". */ 1094DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA) 1095 1096/* (define_insn_reservation name default_latency condition regexpr) 1097 describes reservation of cpu functional units (the 3nd operand) for 1098 instruction which is selected by the condition (the 2nd parameter). 1099 The first parameter is used for output of debugging information. 1100 The reservations are described by a regular expression according 1101 the following syntax: 1102 1103 regexp = regexp "," oneof 1104 | oneof 1105 1106 oneof = oneof "|" allof 1107 | allof 1108 1109 allof = allof "+" repeat 1110 | repeat 1111 1112 repeat = element "*" number 1113 | element 1114 1115 element = cpu_function_unit_name 1116 | reservation_name 1117 | result_name 1118 | "nothing" 1119 | "(" regexp ")" 1120 1121 1. "," is used for describing start of the next cycle in 1122 reservation. 1123 1124 2. "|" is used for describing the reservation described by the 1125 first regular expression *or* the reservation described by the 1126 second regular expression *or* etc. 1127 1128 3. "+" is used for describing the reservation described by the 1129 first regular expression *and* the reservation described by the 1130 second regular expression *and* etc. 1131 1132 4. "*" is used for convenience and simply means sequence in 1133 which the regular expression are repeated NUMBER times with 1134 cycle advancing (see ","). 1135 1136 5. cpu functional unit name which means its reservation. 1137 1138 6. reservation name -- see define_reservation. 1139 1140 7. string "nothing" means no units reservation. */ 1141 1142DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA) 1143 1144/* Expressions used for insn attributes. */ 1145 1146/* Definition of an insn attribute. 1147 1st operand: name of the attribute 1148 2nd operand: comma-separated list of possible attribute values 1149 3rd operand: expression for the default value of the attribute. */ 1150DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA) 1151 1152/* Marker for the name of an attribute. */ 1153DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA) 1154 1155/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and 1156 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that 1157 pattern. 1158 1159 (set_attr "name" "value") is equivalent to 1160 (set (attr "name") (const_string "value")) */ 1161DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA) 1162 1163/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to 1164 specify that attribute values are to be assigned according to the 1165 alternative matched. 1166 1167 The following three expressions are equivalent: 1168 1169 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") 1170 (eq_attrq "alternative" "2") (const_string "a2")] 1171 (const_string "a3"))) 1172 (set_attr_alternative "att" [(const_string "a1") (const_string "a2") 1173 (const_string "a3")]) 1174 (set_attr "att" "a1,a2,a3") 1175 */ 1176DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA) 1177 1178/* A conditional expression true if the value of the specified attribute of 1179 the current insn equals the specified value. The first operand is the 1180 attribute name and the second is the comparison value. */ 1181DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA) 1182 1183/* A special case of the above representing a set of alternatives. The first 1184 operand is bitmap of the set, the second one is the default value. */ 1185DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA) 1186 1187/* A conditional expression which is true if the specified flag is 1188 true for the insn being scheduled in reorg. 1189 1190 genattr.c defines the following flags which can be tested by 1191 (attr_flag "foo") expressions in eligible_for_delay. 1192 1193 forward, backward, very_likely, likely, very_unlikely, and unlikely. */ 1194 1195DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA) 1196 1197/* General conditional. The first operand is a vector composed of pairs of 1198 expressions. The first element of each pair is evaluated, in turn. 1199 The value of the conditional is the second expression of the first pair 1200 whose first expression evaluates nonzero. If none of the expressions is 1201 true, the second operand will be used as the value of the conditional. */ 1202DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA) 1203 1204#endif /* GENERATOR_FILE */ 1205 1206/* 1207Local variables: 1208mode:c 1209End: 1210*/ 1211