s390.md revision 146895
189580Smsmith;;- Machine description for GNU compiler -- S/390 / zSeries version. 2120477Sscottl;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 3120477Sscottl;; Free Software Foundation, Inc. 4120477Sscottl;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and 589580Smsmith;; Ulrich Weigand (uweigand@de.ibm.com). 689580Smsmith 789580Smsmith;; This file is part of GCC. 889580Smsmith 989580Smsmith;; GCC is free software; you can redistribute it and/or modify it under 1089580Smsmith;; the terms of the GNU General Public License as published by the Free 1189580Smsmith;; Software Foundation; either version 2, or (at your option) any later 1289580Smsmith;; version. 1389580Smsmith 1489580Smsmith;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 1589580Smsmith;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 1689580Smsmith;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 1789580Smsmith;; for more details. 1889580Smsmith 1989580Smsmith;; You should have received a copy of the GNU General Public License 2089580Smsmith;; along with GCC; see the file COPYING. If not, write to the Free 2189580Smsmith;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2289580Smsmith;; 02111-1307, USA. 2389580Smsmith 2489580Smsmith;; 2589580Smsmith;; Special constraints for s/390 machine description: 2689580Smsmith;; 2789580Smsmith;; a -- Any address register from 1 to 15. 2889580Smsmith;; d -- Any register from 0 to 15. 2989580Smsmith;; I -- An 8-bit constant (0..255). 3089580Smsmith;; J -- A 12-bit constant (0..4095). 3189580Smsmith;; K -- A 16-bit constant (-32768..32767). 3289580Smsmith;; L -- Value appropriate as displacement. 3389580Smsmith;; (0..4095) for short displacement 3489580Smsmith;; (-524288..524287) for long displacement 35120477Sscottl;; M -- Constant integer with a value of 0x7fffffff. 3689580Smsmith;; N -- Multiple letter constraint followed by 4 parameter letters. 3789580Smsmith;; 0..9: number of the part counting from most to least significant 38120477Sscottl;; H,Q: mode of the part 3989580Smsmith;; D,S,H: mode of the containing operand 4089580Smsmith;; 0,F: value of the other parts (F - all bits set) 41119418Sobrien;; 42119418Sobrien;; The constraint matches if the specified part of a constant 4389580Smsmith;; has a value different from its other parts. 4489580Smsmith;; Q -- Memory reference without index register and with short displacement. 4589580Smsmith;; R -- Memory reference with index register and short displacement. 4695533Smike;; S -- Memory reference without index register but with long displacement. 4789580Smsmith;; T -- Memory reference with index register and long displacement. 4889580Smsmith;; U -- Pointer with short displacement. 4989580Smsmith;; W -- Pointer with long displacement. 5089580Smsmith;; Y -- Shift count operand. 51114001Sscottl;; 5289580Smsmith;; Special formats used for outputting 390 instructions. 53114001Sscottl;; 5489580Smsmith;; %C: print opcode suffix for branch condition. 5589580Smsmith;; %D: print opcode suffix for inverse branch condition. 5689580Smsmith;; %J: print tls_load/tls_gdcall/tls_ldcall suffix 5789580Smsmith;; %O: print only the displacement of a memory reference. 5889580Smsmith;; %R: print only the base register of a memory reference. 5989580Smsmith;; %N: print the second word of a DImode operand. 6089580Smsmith;; %M: print the second word of a TImode operand. 6189580Smsmith 6289580Smsmith;; %b: print integer X as if it's an unsigned byte. 6389580Smsmith;; %x: print integer X as if it's an unsigned word. 6489580Smsmith;; %h: print integer X as if it's a signed word. 6589580Smsmith;; %i: print the first nonzero HImode part of X 6689580Smsmith;; %j: print the first HImode part unequal to 0xffff of X 6789580Smsmith 6889580Smsmith;; 6989580Smsmith;; We have a special constraint for pattern matching. 7089580Smsmith;; 7189580Smsmith;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. 7289580Smsmith;; 73126080Sphk 74126080Sphk;; 75111815Sphk;; UNSPEC usage 76111815Sphk;; 77111815Sphk 78111815Sphk(define_constants 79111815Sphk [; Miscellaneous 80111815Sphk (UNSPEC_ROUND 1) 8189580Smsmith (UNSPEC_SETHIGH 10) 8289580Smsmith 83114001Sscottl ; GOT/PLT and lt-relative accesses 84114001Sscottl (UNSPEC_LTREL_OFFSET 100) 85114001Sscottl (UNSPEC_LTREL_BASE 101) 8689580Smsmith (UNSPEC_GOTENT 110) 8789580Smsmith (UNSPEC_GOT 111) 8889580Smsmith (UNSPEC_GOTOFF 112) 8989580Smsmith (UNSPEC_PLT 113) 9089580Smsmith (UNSPEC_PLTOFF 114) 9189580Smsmith 9289580Smsmith ; Literal pool 9389580Smsmith (UNSPEC_RELOAD_BASE 210) 9489580Smsmith (UNSPEC_MAIN_BASE 211) 9589580Smsmith 9689580Smsmith ; TLS relocation specifiers 9789580Smsmith (UNSPEC_TLSGD 500) 98130585Sphk (UNSPEC_TLSLDM 501) 9989580Smsmith (UNSPEC_NTPOFF 502) 10089580Smsmith (UNSPEC_DTPOFF 503) 101130585Sphk (UNSPEC_GOTNTPOFF 504) 10289580Smsmith (UNSPEC_INDNTPOFF 505) 10389580Smsmith 10489580Smsmith ; TLS support 105114001Sscottl (UNSPEC_TP 510) 10689580Smsmith (UNSPEC_TLSLDM_NTPOFF 511) 10789580Smsmith (UNSPEC_TLS_LOAD 512) 10889580Smsmith 10989580Smsmith ; String Functions 110114001Sscottl (UNSPEC_SRST 600) 11189580Smsmith ]) 11289580Smsmith 11389580Smsmith;; 11489580Smsmith;; UNSPEC_VOLATILE usage 11589580Smsmith;; 11689580Smsmith 117130585Sphk(define_constants 11889580Smsmith [; Blockage 11989580Smsmith (UNSPECV_BLOCKAGE 0) 12089580Smsmith 12189580Smsmith ; Literal pool 12289580Smsmith (UNSPECV_POOL 200) 12389580Smsmith (UNSPECV_POOL_START 201) 12489580Smsmith (UNSPECV_POOL_END 202) 12589580Smsmith (UNSPECV_POOL_ENTRY 203) 12689580Smsmith (UNSPECV_MAIN_POOL 300) 12789580Smsmith 12889580Smsmith ; TLS support 12989580Smsmith (UNSPECV_SET_TP 500) 13089580Smsmith ]) 13189580Smsmith 13289580Smsmith 13389580Smsmith;; Processor type. This attribute must exactly match the processor_type 13489580Smsmith;; enumeration in s390.h. 13589580Smsmith 13689580Smsmith(define_attr "cpu" "g5,g6,z900,z990" 13789580Smsmith (const (symbol_ref "s390_tune"))) 13889580Smsmith 13989580Smsmith;; Define an insn type attribute. This is used in function unit delay 14089580Smsmith;; computations. 14189580Smsmith 14289580Smsmith(define_attr "type" "none,integer,load,lr,la,larl,lm,stm, 14389580Smsmith cs,vs,store,imul,idiv, 14489580Smsmith branch,jsr,fsimpd,fsimps, 14589580Smsmith floadd,floads,fstored, fstores, 14689580Smsmith fmuld,fmuls,fdivd,fdivs, 147130585Sphk ftoi,itof,fsqrtd,fsqrts, 14889580Smsmith other,o2,o3" 14989580Smsmith (const_string "integer")) 15089580Smsmith 15189580Smsmith;; Operand type. Used to default length attribute values 15289580Smsmith 15389580Smsmith(define_attr "op_type" 15489580Smsmith "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" 15589580Smsmith (const_string "RX")) 15689580Smsmith 15789580Smsmith;; Insn are devide in two classes: 15889580Smsmith;; agen: Insn using agen 15989580Smsmith;; reg: Insn not using agen 16089580Smsmith 16189580Smsmith(define_attr "atype" "agen,reg" 16289580Smsmith(cond [ (eq_attr "op_type" "E") (const_string "reg") 16389580Smsmith (eq_attr "op_type" "RR") (const_string "reg") 16489580Smsmith (eq_attr "op_type" "RX") (const_string "agen") 165130585Sphk (eq_attr "op_type" "RI") (const_string "reg") 16689580Smsmith (eq_attr "op_type" "RRE") (const_string "reg") 16789580Smsmith (eq_attr "op_type" "RS") (const_string "agen") 16889580Smsmith (eq_attr "op_type" "RSI") (const_string "agen") 16989580Smsmith (eq_attr "op_type" "S") (const_string "agen") 17089580Smsmith (eq_attr "op_type" "SI") (const_string "agen") 17189580Smsmith (eq_attr "op_type" "SS") (const_string "agen") 17289580Smsmith (eq_attr "op_type" "SSE") (const_string "agen") 17389580Smsmith (eq_attr "op_type" "RXE") (const_string "agen") 17489580Smsmith (eq_attr "op_type" "RSE") (const_string "agen") 17589580Smsmith (eq_attr "op_type" "RIL") (const_string "agen") 17689580Smsmith (eq_attr "op_type" "RXY") (const_string "agen") 17789580Smsmith (eq_attr "op_type" "RSY") (const_string "agen") 17889580Smsmith (eq_attr "op_type" "SIY") (const_string "agen")] 17989580Smsmith (const_string "reg"))) 18089580Smsmith 18189580Smsmith;; Generic pipeline function unit. 18289580Smsmith 183130585Sphk(define_function_unit "integer" 1 0 18489580Smsmith (eq_attr "type" "none") 0 0) 18589580Smsmith 18689580Smsmith(define_function_unit "integer" 1 0 18789580Smsmith (eq_attr "type" "integer") 1 1) 18889580Smsmith 18989580Smsmith(define_function_unit "integer" 1 0 19089580Smsmith (eq_attr "type" "fsimpd") 1 1) 19189580Smsmith 19289580Smsmith(define_function_unit "integer" 1 0 19389580Smsmith (eq_attr "type" "fsimps") 1 1) 19489580Smsmith 19589580Smsmith(define_function_unit "integer" 1 0 19689580Smsmith (eq_attr "type" "load") 1 1) 19789580Smsmith 19889580Smsmith(define_function_unit "integer" 1 0 19989580Smsmith (eq_attr "type" "floadd") 1 1) 20089580Smsmith 201130585Sphk(define_function_unit "integer" 1 0 20289580Smsmith (eq_attr "type" "floads") 1 1) 20389580Smsmith 20489580Smsmith(define_function_unit "integer" 1 0 20589580Smsmith (eq_attr "type" "la") 1 1) 20689580Smsmith 20789580Smsmith(define_function_unit "integer" 1 0 20889580Smsmith (eq_attr "type" "larl") 1 1) 20989580Smsmith 21089580Smsmith(define_function_unit "integer" 1 0 21189580Smsmith (eq_attr "type" "lr") 1 1) 21289580Smsmith 21389580Smsmith(define_function_unit "integer" 1 0 21489580Smsmith (eq_attr "type" "branch") 1 1) 21589580Smsmith 21689580Smsmith(define_function_unit "integer" 1 0 21789580Smsmith (eq_attr "type" "store") 1 1) 21889580Smsmith 21989580Smsmith(define_function_unit "integer" 1 0 22089580Smsmith (eq_attr "type" "fstored") 1 1) 22189580Smsmith 22289580Smsmith(define_function_unit "integer" 1 0 22389580Smsmith (eq_attr "type" "fstores") 1 1) 22489580Smsmith 225130585Sphk(define_function_unit "integer" 1 0 22689580Smsmith (eq_attr "type" "lm") 2 2) 22789580Smsmith 22889580Smsmith(define_function_unit "integer" 1 0 22989580Smsmith (eq_attr "type" "stm") 2 2) 23089580Smsmith 23189580Smsmith(define_function_unit "integer" 1 0 23289580Smsmith (eq_attr "type" "cs") 5 5) 23389580Smsmith 23489580Smsmith(define_function_unit "integer" 1 0 23589580Smsmith (eq_attr "type" "vs") 30 30) 23689580Smsmith 23789580Smsmith(define_function_unit "integer" 1 0 23889580Smsmith (eq_attr "type" "jsr") 5 5) 23989580Smsmith 24089580Smsmith(define_function_unit "integer" 1 0 24189580Smsmith (eq_attr "type" "imul") 7 7) 24289580Smsmith 24389580Smsmith(define_function_unit "integer" 1 0 24489580Smsmith (eq_attr "type" "fmuld") 6 6) 24589580Smsmith 24689580Smsmith(define_function_unit "integer" 1 0 24789580Smsmith (eq_attr "type" "fmuls") 6 6) 24889580Smsmith 24989580Smsmith(define_function_unit "integer" 1 0 25089580Smsmith (eq_attr "type" "idiv") 33 33) 25189580Smsmith 25289580Smsmith(define_function_unit "integer" 1 0 25389580Smsmith (eq_attr "type" "fdivd") 33 33) 25489580Smsmith 25589580Smsmith(define_function_unit "integer" 1 0 25689580Smsmith (eq_attr "type" "fdivs") 33 33) 25789580Smsmith 25889580Smsmith(define_function_unit "integer" 1 0 25989580Smsmith (eq_attr "type" "fsqrtd") 30 30) 26089580Smsmith 26189580Smsmith(define_function_unit "integer" 1 0 26289580Smsmith (eq_attr "type" "fsqrts") 30 30) 26389580Smsmith 264129449Sscottl(define_function_unit "integer" 1 0 26589580Smsmith (eq_attr "type" "ftoi") 2 2) 26689580Smsmith 26789580Smsmith(define_function_unit "integer" 1 0 26889580Smsmith (eq_attr "type" "itof") 2 2) 26989580Smsmith 270129449Sscottl(define_function_unit "integer" 1 0 27189580Smsmith (eq_attr "type" "o2") 2 2) 27289580Smsmith 27389580Smsmith(define_function_unit "integer" 1 0 27489580Smsmith (eq_attr "type" "o3") 3 3) 27589580Smsmith 27689580Smsmith(define_function_unit "integer" 1 0 27789580Smsmith (eq_attr "type" "other") 5 5) 27889580Smsmith 279120477Sscottl;; Pipeline description for z900 280120477Sscottl 281120477Sscottl(include "2064.md") 282120477Sscottl(include "2084.md") 283120477Sscottl 284120477Sscottl;; Length in bytes. 285120477Sscottl 286120477Sscottl(define_attr "length" "" 287120477Sscottl(cond [ (eq_attr "op_type" "E") (const_int 2) 288120477Sscottl (eq_attr "op_type" "RR") (const_int 2) 289120477Sscottl (eq_attr "op_type" "RX") (const_int 4) 290120477Sscottl (eq_attr "op_type" "RI") (const_int 4) 291120477Sscottl (eq_attr "op_type" "RRE") (const_int 4) 292120477Sscottl (eq_attr "op_type" "RS") (const_int 4) 293120477Sscottl (eq_attr "op_type" "RSI") (const_int 4) 29489580Smsmith (eq_attr "op_type" "S") (const_int 4) 29589580Smsmith (eq_attr "op_type" "SI") (const_int 4) 29689580Smsmith (eq_attr "op_type" "SS") (const_int 6) 29789580Smsmith (eq_attr "op_type" "SSE") (const_int 6) 29889580Smsmith (eq_attr "op_type" "RXE") (const_int 6) 29989580Smsmith (eq_attr "op_type" "RSE") (const_int 6) 30089580Smsmith (eq_attr "op_type" "RIL") (const_int 6) 30189580Smsmith (eq_attr "op_type" "RXY") (const_int 6) 30289580Smsmith (eq_attr "op_type" "RSY") (const_int 6) 30389580Smsmith (eq_attr "op_type" "SIY") (const_int 6)] 30489580Smsmith (const_int 4))) 30589580Smsmith 30689580Smsmith;; Define attributes for `asm' insns. 30789580Smsmith 30889580Smsmith(define_asm_attributes [(set_attr "type" "other") 30989580Smsmith (set_attr "op_type" "NN")]) 31089580Smsmith 31189580Smsmith;; 31289580Smsmith;; Condition Codes 31389580Smsmith;; 31489580Smsmith; 31589580Smsmith; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR) 31689580Smsmith; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA) 31789580Smsmith; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM) 31889580Smsmith; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM) 31989580Smsmith; CCT: Zero Mixed Mixed Ones (TM, TMH, TML) 32089580Smsmith 32189580Smsmith; CCZ -> CCL / CCZ1 32289580Smsmith; CCZ1 -> CCA/CCU/CCS/CCT 32389580Smsmith; CCS -> CCA 32489580Smsmith 32589580Smsmith; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST 32689580Smsmith; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT 32789580Smsmith 32889580Smsmith 32989580Smsmith;; 33089580Smsmith;;- Compare instructions. 33189580Smsmith;; 33289580Smsmith 33389580Smsmith(define_expand "cmpdi" 33489580Smsmith [(set (reg:CC 33) 33589580Smsmith (compare:CC (match_operand:DI 0 "register_operand" "") 33689580Smsmith (match_operand:DI 1 "general_operand" "")))] 33789580Smsmith "TARGET_64BIT" 33889580Smsmith{ 33989580Smsmith s390_compare_op0 = operands[0]; 34089580Smsmith s390_compare_op1 = operands[1]; 34189580Smsmith DONE; 34289580Smsmith}) 34389580Smsmith 34489580Smsmith(define_expand "cmpsi" 34589580Smsmith [(set (reg:CC 33) 34689580Smsmith (compare:CC (match_operand:SI 0 "register_operand" "") 34789580Smsmith (match_operand:SI 1 "general_operand" "")))] 34889580Smsmith "" 34989580Smsmith{ 35089580Smsmith s390_compare_op0 = operands[0]; 35189580Smsmith s390_compare_op1 = operands[1]; 35289580Smsmith DONE; 35389580Smsmith}) 35489580Smsmith 35589580Smsmith(define_expand "cmpdf" 35689580Smsmith [(set (reg:CC 33) 35789580Smsmith (compare:CC (match_operand:DF 0 "register_operand" "") 35889580Smsmith (match_operand:DF 1 "general_operand" "")))] 35989580Smsmith "TARGET_HARD_FLOAT" 36089580Smsmith{ 36189580Smsmith s390_compare_op0 = operands[0]; 36289580Smsmith s390_compare_op1 = operands[1]; 36389580Smsmith DONE; 36489580Smsmith}) 36589580Smsmith 36689580Smsmith(define_expand "cmpsf" 36789580Smsmith [(set (reg:CC 33) 36889580Smsmith (compare:CC (match_operand:SF 0 "register_operand" "") 36989580Smsmith (match_operand:SF 1 "general_operand" "")))] 370114001Sscottl "TARGET_HARD_FLOAT" 371114001Sscottl{ 372114001Sscottl s390_compare_op0 = operands[0]; 373114001Sscottl s390_compare_op1 = operands[1]; 374114001Sscottl DONE; 375114001Sscottl}) 376114001Sscottl 377114001Sscottl 378114001Sscottl; Test-under-Mask (zero_extract) instructions 379114001Sscottl 380114001Sscottl(define_insn "*tmdi_ext" 381114001Sscottl [(set (reg 33) 382114001Sscottl (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d") 383125834Sscottl (match_operand:DI 1 "const_int_operand" "n") 384114001Sscottl (match_operand:DI 2 "const_int_operand" "n")) 385 (const_int 0)))] 386 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT 387 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 388 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64 389 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 390 == INTVAL (operands[2]) >> 4" 391{ 392 int part = INTVAL (operands[2]) >> 4; 393 int block = (1 << INTVAL (operands[1])) - 1; 394 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); 395 396 operands[2] = GEN_INT (block << shift); 397 398 switch (part) 399 { 400 case 0: return "tmhh\t%0,%x2"; 401 case 1: return "tmhl\t%0,%x2"; 402 case 2: return "tmlh\t%0,%x2"; 403 case 3: return "tmll\t%0,%x2"; 404 default: abort (); 405 } 406} 407 [(set_attr "op_type" "RI")]) 408 409(define_insn "*tmsi_ext" 410 [(set (reg 33) 411 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") 412 (match_operand:SI 1 "const_int_operand" "n") 413 (match_operand:SI 2 "const_int_operand" "n")) 414 (const_int 0)))] 415 "s390_match_ccmode(insn, CCTmode) 416 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 417 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 418 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 419 == INTVAL (operands[2]) >> 4" 420{ 421 int part = INTVAL (operands[2]) >> 4; 422 int block = (1 << INTVAL (operands[1])) - 1; 423 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); 424 425 operands[2] = GEN_INT (block << shift); 426 427 switch (part) 428 { 429 case 0: return "tmh\t%0,%x2"; 430 case 1: return "tml\t%0,%x2"; 431 default: abort (); 432 } 433} 434 [(set_attr "op_type" "RI")]) 435 436(define_insn "*tmqisi_ext" 437 [(set (reg 33) 438 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S") 439 (match_operand:SI 1 "const_int_operand" "n,n") 440 (match_operand:SI 2 "const_int_operand" "n,n")) 441 (const_int 0)))] 442 "!TARGET_64BIT && s390_match_ccmode(insn, CCTmode) 443 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 444 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" 445{ 446 int block = (1 << INTVAL (operands[1])) - 1; 447 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); 448 449 operands[2] = GEN_INT (block << shift); 450 return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2"; 451} 452 [(set_attr "op_type" "SI,SIY")]) 453 454(define_insn "*tmqidi_ext" 455 [(set (reg 33) 456 (compare (zero_extract:DI (match_operand:QI 0 "memory_operand" "Q,S") 457 (match_operand:SI 1 "const_int_operand" "n,n") 458 (match_operand:SI 2 "const_int_operand" "n,n")) 459 (const_int 0)))] 460 "TARGET_64BIT && s390_match_ccmode(insn, CCTmode) 461 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 462 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" 463{ 464 int block = (1 << INTVAL (operands[1])) - 1; 465 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); 466 467 operands[2] = GEN_INT (block << shift); 468 return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2"; 469} 470 [(set_attr "op_type" "SI,SIY")]) 471 472 473; Test-under-Mask instructions 474 475(define_insn "*tmdi_mem" 476 [(set (reg 33) 477 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S") 478 (match_operand:DI 1 "immediate_operand" "n,n")) 479 (match_operand:DI 2 "immediate_operand" "n,n")))] 480 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) 481 && s390_single_part (operands[1], DImode, QImode, 0) >= 0" 482{ 483 int part = s390_single_part (operands[1], DImode, QImode, 0); 484 operands[1] = GEN_INT (s390_extract_part (operands[1], QImode, 0)); 485 486 operands[0] = gen_rtx_MEM (QImode, 487 plus_constant (XEXP (operands[0], 0), part)); 488 return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; 489} 490 [(set_attr "op_type" "SI,SIY")]) 491 492(define_insn "*tmsi_mem" 493 [(set (reg 33) 494 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q,S") 495 (match_operand:SI 1 "immediate_operand" "n,n")) 496 (match_operand:SI 2 "immediate_operand" "n,n")))] 497 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) 498 && s390_single_part (operands[1], SImode, QImode, 0) >= 0" 499{ 500 int part = s390_single_part (operands[1], SImode, QImode, 0); 501 operands[1] = GEN_INT (s390_extract_part (operands[1], QImode, 0)); 502 503 operands[0] = gen_rtx_MEM (QImode, 504 plus_constant (XEXP (operands[0], 0), part)); 505 return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; 506} 507 [(set_attr "op_type" "SI")]) 508 509(define_insn "*tmhi_mem" 510 [(set (reg 33) 511 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q,S") 0) 512 (match_operand:SI 1 "immediate_operand" "n,n")) 513 (match_operand:SI 2 "immediate_operand" "n,n")))] 514 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) 515 && s390_single_part (operands[1], HImode, QImode, 0) >= 0" 516{ 517 int part = s390_single_part (operands[1], HImode, QImode, 0); 518 operands[1] = GEN_INT (s390_extract_part (operands[1], QImode, 0)); 519 520 operands[0] = gen_rtx_MEM (QImode, 521 plus_constant (XEXP (operands[0], 0), part)); 522 return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; 523} 524 [(set_attr "op_type" "SI")]) 525 526(define_insn "*tmqi_mem" 527 [(set (reg 33) 528 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q,S") 0) 529 (match_operand:SI 1 "immediate_operand" "n,n")) 530 (match_operand:SI 2 "immediate_operand" "n,n")))] 531 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" 532 "@ 533 tm\t%0,%b1 534 tmy\t%0,%b1" 535 [(set_attr "op_type" "SI,SIY")]) 536 537(define_insn "*tmdi_reg" 538 [(set (reg 33) 539 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") 540 (match_operand:DI 1 "immediate_operand" 541 "N0HD0,N1HD0,N2HD0,N3HD0")) 542 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] 543 "TARGET_64BIT 544 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) 545 && s390_single_part (operands[1], DImode, HImode, 0) >= 0" 546 "@ 547 tmhh\t%0,%i1 548 tmhl\t%0,%i1 549 tmlh\t%0,%i1 550 tmll\t%0,%i1" 551 [(set_attr "op_type" "RI")]) 552 553(define_insn "*tmsi_reg" 554 [(set (reg 33) 555 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") 556 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) 557 (match_operand:SI 2 "immediate_operand" "n,n")))] 558 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) 559 && s390_single_part (operands[1], SImode, HImode, 0) >= 0" 560 "@ 561 tmh\t%0,%i1 562 tml\t%0,%i1" 563 [(set_attr "op_type" "RI")]) 564 565(define_insn "*tmhi_full" 566 [(set (reg 33) 567 (compare (match_operand:HI 0 "register_operand" "d") 568 (match_operand:HI 1 "immediate_operand" "n")))] 569 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))" 570 "tml\t%0,65535" 571 [(set_attr "op_type" "RX")]) 572 573(define_insn "*tmqi_full" 574 [(set (reg 33) 575 (compare (match_operand:QI 0 "register_operand" "d") 576 (match_operand:QI 1 "immediate_operand" "n")))] 577 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))" 578 "tml\t%0,255" 579 [(set_attr "op_type" "RI")]) 580 581 582; Load-and-Test instructions 583 584(define_insn "*tstdi_sign" 585 [(set (reg 33) 586 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) 587 (const_int 32)) (const_int 32)) 588 (match_operand:DI 1 "const0_operand" ""))) 589 (set (match_operand:DI 2 "register_operand" "=d") 590 (sign_extend:DI (match_dup 0)))] 591 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 592 "ltgfr\t%2,%0" 593 [(set_attr "op_type" "RRE")]) 594 595(define_insn "*tstdi" 596 [(set (reg 33) 597 (compare (match_operand:DI 0 "register_operand" "d") 598 (match_operand:DI 1 "const0_operand" ""))) 599 (set (match_operand:DI 2 "register_operand" "=d") 600 (match_dup 0))] 601 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 602 "ltgr\t%2,%0" 603 [(set_attr "op_type" "RRE")]) 604 605(define_insn "*tstdi_cconly" 606 [(set (reg 33) 607 (compare (match_operand:DI 0 "register_operand" "d") 608 (match_operand:DI 1 "const0_operand" "")))] 609 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 610 "ltgr\t%0,%0" 611 [(set_attr "op_type" "RRE")]) 612 613(define_insn "*tstdi_cconly_31" 614 [(set (reg 33) 615 (compare (match_operand:DI 0 "register_operand" "d") 616 (match_operand:DI 1 "const0_operand" "")))] 617 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" 618 "srda\t%0,0" 619 [(set_attr "op_type" "RS") 620 (set_attr "atype" "reg")]) 621 622 623(define_insn "*tstsi" 624 [(set (reg 33) 625 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") 626 (match_operand:SI 1 "const0_operand" ""))) 627 (set (match_operand:SI 2 "register_operand" "=d,d,d") 628 (match_dup 0))] 629 "s390_match_ccmode(insn, CCSmode)" 630 "@ 631 ltr\t%2,%0 632 icm\t%2,15,%0 633 icmy\t%2,15,%0" 634 [(set_attr "op_type" "RR,RS,RSY")]) 635 636(define_insn "*tstsi_cconly" 637 [(set (reg 33) 638 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") 639 (match_operand:SI 1 "const0_operand" ""))) 640 (clobber (match_scratch:SI 2 "=X,d,d"))] 641 "s390_match_ccmode(insn, CCSmode)" 642 "@ 643 ltr\t%0,%0 644 icm\t%2,15,%0 645 icmy\t%2,15,%0" 646 [(set_attr "op_type" "RR,RS,RSY")]) 647 648(define_insn "*tstsi_cconly2" 649 [(set (reg 33) 650 (compare (match_operand:SI 0 "register_operand" "d") 651 (match_operand:SI 1 "const0_operand" "")))] 652 "s390_match_ccmode(insn, CCSmode)" 653 "ltr\t%0,%0" 654 [(set_attr "op_type" "RR")]) 655 656(define_insn "*tsthiCCT" 657 [(set (reg 33) 658 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d") 659 (match_operand:HI 1 "const0_operand" ""))) 660 (set (match_operand:HI 2 "register_operand" "=d,d,0") 661 (match_dup 0))] 662 "s390_match_ccmode(insn, CCTmode)" 663 "@ 664 icm\t%2,3,%0 665 icmy\t%2,3,%0 666 tml\t%0,65535" 667 [(set_attr "op_type" "RS,RSY,RI")]) 668 669(define_insn "*tsthiCCT_cconly" 670 [(set (reg 33) 671 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") 672 (match_operand:HI 1 "const0_operand" ""))) 673 (clobber (match_scratch:HI 2 "=d,d,X"))] 674 "s390_match_ccmode(insn, CCTmode)" 675 "@ 676 icm\t%2,3,%0 677 icmy\t%2,3,%0 678 tml\t%0,65535" 679 [(set_attr "op_type" "RS,RSY,RI")]) 680 681(define_insn "*tsthi" 682 [(set (reg 33) 683 (compare (match_operand:HI 0 "s_operand" "Q,S") 684 (match_operand:HI 1 "const0_operand" ""))) 685 (set (match_operand:HI 2 "register_operand" "=d,d") 686 (match_dup 0))] 687 "s390_match_ccmode(insn, CCSmode)" 688 "@ 689 icm\t%2,3,%0 690 icmy\t%2,3,%0" 691 [(set_attr "op_type" "RS,RSY")]) 692 693(define_insn "*tsthi_cconly" 694 [(set (reg 33) 695 (compare (match_operand:HI 0 "s_operand" "Q,S") 696 (match_operand:HI 1 "const0_operand" ""))) 697 (clobber (match_scratch:HI 2 "=d,d"))] 698 "s390_match_ccmode(insn, CCSmode)" 699 "@ 700 icm\t%2,3,%0 701 icmy\t%2,3,%0" 702 [(set_attr "op_type" "RS,RSY")]) 703 704(define_insn "*tstqiCCT" 705 [(set (reg 33) 706 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") 707 (match_operand:QI 1 "const0_operand" ""))) 708 (set (match_operand:QI 2 "register_operand" "=d,d,0") 709 (match_dup 0))] 710 "s390_match_ccmode(insn, CCTmode)" 711 "@ 712 icm\t%2,1,%0 713 icmy\t%2,1,%0 714 tml\t%0,255" 715 [(set_attr "op_type" "RS,RSY,RI")]) 716 717(define_insn "*tstqiCCT_cconly" 718 [(set (reg 33) 719 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") 720 (match_operand:QI 1 "const0_operand" "")))] 721 "s390_match_ccmode(insn, CCTmode)" 722 "@ 723 cli\t%0,0 724 cliy\t%0,0 725 tml\t%0,255" 726 [(set_attr "op_type" "SI,SIY,RI")]) 727 728(define_insn "*tstqi" 729 [(set (reg 33) 730 (compare (match_operand:QI 0 "s_operand" "Q,S") 731 (match_operand:QI 1 "const0_operand" ""))) 732 (set (match_operand:QI 2 "register_operand" "=d,d") 733 (match_dup 0))] 734 "s390_match_ccmode(insn, CCSmode)" 735 "@ 736 icm\t%2,1,%0 737 icmy\t%2,1,%0" 738 [(set_attr "op_type" "RS,RSY")]) 739 740(define_insn "*tstqi_cconly" 741 [(set (reg 33) 742 (compare (match_operand:QI 0 "s_operand" "Q,S") 743 (match_operand:QI 1 "const0_operand" ""))) 744 (clobber (match_scratch:QI 2 "=d,d"))] 745 "s390_match_ccmode(insn, CCSmode)" 746 "@ 747 icm\t%2,1,%0 748 icmy\t%2,1,%0" 749 [(set_attr "op_type" "RS,RSY")]) 750 751 752; Compare (signed) instructions 753 754(define_insn "*cmpdi_ccs_sign" 755 [(set (reg 33) 756 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) 757 (match_operand:DI 0 "register_operand" "d,d")))] 758 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" 759 "@ 760 cgfr\t%0,%1 761 cgf\t%0,%1" 762 [(set_attr "op_type" "RRE,RXY")]) 763 764(define_insn "*cmpdi_ccs" 765 [(set (reg 33) 766 (compare (match_operand:DI 0 "register_operand" "d,d,d") 767 (match_operand:DI 1 "general_operand" "d,K,m")))] 768 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 769 "@ 770 cgr\t%0,%1 771 cghi\t%0,%c1 772 cg\t%0,%1" 773 [(set_attr "op_type" "RRE,RI,RXY")]) 774 775(define_insn "*cmpsi_ccs_sign" 776 [(set (reg 33) 777 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) 778 (match_operand:SI 0 "register_operand" "d,d")))] 779 "s390_match_ccmode(insn, CCSRmode)" 780 "@ 781 ch\t%0,%1 782 chy\t%0,%1" 783 [(set_attr "op_type" "RX,RXY")]) 784 785(define_insn "*cmpsi_ccs" 786 [(set (reg 33) 787 (compare (match_operand:SI 0 "register_operand" "d,d,d,d") 788 (match_operand:SI 1 "general_operand" "d,K,R,T")))] 789 "s390_match_ccmode(insn, CCSmode)" 790 "@ 791 cr\t%0,%1 792 chi\t%0,%c1 793 c\t%0,%1 794 cy\t%0,%1" 795 [(set_attr "op_type" "RR,RI,RX,RXY")]) 796 797 798; Compare (unsigned) instructions 799 800(define_insn "*cmpdi_ccu_zero" 801 [(set (reg 33) 802 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) 803 (match_operand:DI 0 "register_operand" "d,d")))] 804 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT" 805 "@ 806 clgfr\t%0,%1 807 clgf\t%0,%1" 808 [(set_attr "op_type" "RRE,RXY")]) 809 810(define_insn "*cmpdi_ccu" 811 [(set (reg 33) 812 (compare (match_operand:DI 0 "register_operand" "d,d") 813 (match_operand:DI 1 "general_operand" "d,m")))] 814 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT" 815 "@ 816 clgr\t%0,%1 817 clg\t%0,%1" 818 [(set_attr "op_type" "RRE,RXY")]) 819 820(define_insn "*cmpsi_ccu" 821 [(set (reg 33) 822 (compare (match_operand:SI 0 "register_operand" "d,d,d") 823 (match_operand:SI 1 "general_operand" "d,R,T")))] 824 "s390_match_ccmode(insn, CCUmode)" 825 "@ 826 clr\t%0,%1 827 cl\t%0,%1 828 cly\t%0,%1" 829 [(set_attr "op_type" "RR,RX,RXY")]) 830 831(define_insn "*cmphi_ccu" 832 [(set (reg 33) 833 (compare (match_operand:HI 0 "register_operand" "d,d") 834 (match_operand:HI 1 "s_imm_operand" "Q,S")))] 835 "s390_match_ccmode(insn, CCUmode)" 836 "@ 837 clm\t%0,3,%1 838 clmy\t%0,3,%1" 839 [(set_attr "op_type" "RS,RSY")]) 840 841(define_insn "*cmpqi_ccu" 842 [(set (reg 33) 843 (compare (match_operand:QI 0 "register_operand" "d,d") 844 (match_operand:QI 1 "s_imm_operand" "Q,S")))] 845 "s390_match_ccmode(insn, CCUmode)" 846 "@ 847 clm\t%0,1,%1 848 clmy\t%0,1,%1" 849 [(set_attr "op_type" "RS,RSY")]) 850 851(define_insn "*cli" 852 [(set (reg 33) 853 (compare (match_operand:QI 0 "memory_operand" "Q,S") 854 (match_operand:QI 1 "immediate_operand" "n,n")))] 855 "s390_match_ccmode (insn, CCUmode)" 856 "@ 857 cli\t%0,%b1 858 cliy\t%0,%b1" 859 [(set_attr "op_type" "SI,SIY")]) 860 861(define_insn "*cmpdi_ccu_mem" 862 [(set (reg 33) 863 (compare (match_operand:DI 0 "s_operand" "Q") 864 (match_operand:DI 1 "s_imm_operand" "Q")))] 865 "s390_match_ccmode(insn, CCUmode)" 866 "clc\t%O0(8,%R0),%1" 867 [(set_attr "op_type" "SS")]) 868 869(define_insn "*cmpsi_ccu_mem" 870 [(set (reg 33) 871 (compare (match_operand:SI 0 "s_operand" "Q") 872 (match_operand:SI 1 "s_imm_operand" "Q")))] 873 "s390_match_ccmode(insn, CCUmode)" 874 "clc\t%O0(4,%R0),%1" 875 [(set_attr "op_type" "SS")]) 876 877(define_insn "*cmphi_ccu_mem" 878 [(set (reg 33) 879 (compare (match_operand:HI 0 "s_operand" "Q") 880 (match_operand:HI 1 "s_imm_operand" "Q")))] 881 "s390_match_ccmode(insn, CCUmode)" 882 "clc\t%O0(2,%R0),%1" 883 [(set_attr "op_type" "SS")]) 884 885(define_insn "*cmpqi_ccu_mem" 886 [(set (reg 33) 887 (compare (match_operand:QI 0 "s_operand" "Q") 888 (match_operand:QI 1 "s_imm_operand" "Q")))] 889 "s390_match_ccmode(insn, CCUmode)" 890 "clc\t%O0(1,%R0),%1" 891 [(set_attr "op_type" "SS")]) 892 893 894; DF instructions 895 896(define_insn "*cmpdf_ccs_0" 897 [(set (reg 33) 898 (compare (match_operand:DF 0 "register_operand" "f") 899 (match_operand:DF 1 "const0_operand" "")))] 900 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 901 "ltdbr\t%0,%0" 902 [(set_attr "op_type" "RRE") 903 (set_attr "type" "fsimpd")]) 904 905(define_insn "*cmpdf_ccs_0_ibm" 906 [(set (reg 33) 907 (compare (match_operand:DF 0 "register_operand" "f") 908 (match_operand:DF 1 "const0_operand" "")))] 909 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 910 "ltdr\t%0,%0" 911 [(set_attr "op_type" "RR") 912 (set_attr "type" "fsimpd")]) 913 914(define_insn "*cmpdf_ccs" 915 [(set (reg 33) 916 (compare (match_operand:DF 0 "register_operand" "f,f") 917 (match_operand:DF 1 "general_operand" "f,R")))] 918 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 919 "@ 920 cdbr\t%0,%1 921 cdb\t%0,%1" 922 [(set_attr "op_type" "RRE,RXE") 923 (set_attr "type" "fsimpd")]) 924 925(define_insn "*cmpdf_ccs_ibm" 926 [(set (reg 33) 927 (compare (match_operand:DF 0 "register_operand" "f,f") 928 (match_operand:DF 1 "general_operand" "f,R")))] 929 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 930 "@ 931 cdr\t%0,%1 932 cd\t%0,%1" 933 [(set_attr "op_type" "RR,RX") 934 (set_attr "type" "fsimpd")]) 935 936 937; SF instructions 938 939(define_insn "*cmpsf_ccs_0" 940 [(set (reg 33) 941 (compare (match_operand:SF 0 "register_operand" "f") 942 (match_operand:SF 1 "const0_operand" "")))] 943 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 944 "ltebr\t%0,%0" 945 [(set_attr "op_type" "RRE") 946 (set_attr "type" "fsimps")]) 947 948(define_insn "*cmpsf_ccs_0_ibm" 949 [(set (reg 33) 950 (compare (match_operand:SF 0 "register_operand" "f") 951 (match_operand:SF 1 "const0_operand" "")))] 952 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 953 "lter\t%0,%0" 954 [(set_attr "op_type" "RR") 955 (set_attr "type" "fsimps")]) 956 957(define_insn "*cmpsf_ccs" 958 [(set (reg 33) 959 (compare (match_operand:SF 0 "register_operand" "f,f") 960 (match_operand:SF 1 "general_operand" "f,R")))] 961 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 962 "@ 963 cebr\t%0,%1 964 ceb\t%0,%1" 965 [(set_attr "op_type" "RRE,RXE") 966 (set_attr "type" "fsimps")]) 967 968(define_insn "*cmpsf_ccs" 969 [(set (reg 33) 970 (compare (match_operand:SF 0 "register_operand" "f,f") 971 (match_operand:SF 1 "general_operand" "f,R")))] 972 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 973 "@ 974 cer\t%0,%1 975 ce\t%0,%1" 976 [(set_attr "op_type" "RR,RX") 977 (set_attr "type" "fsimps")]) 978 979 980;; 981;;- Move instructions. 982;; 983 984; 985; movti instruction pattern(s). 986; 987 988(define_insn "movti" 989 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") 990 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))] 991 "TARGET_64BIT" 992 "@ 993 lmg\t%0,%N0,%1 994 stmg\t%1,%N1,%0 995 # 996 # 997 mvc\t%O0(16,%R0),%1" 998 [(set_attr "op_type" "RSY,RSY,NN,NN,SS") 999 (set_attr "type" "lm,stm,*,*,cs")]) 1000 1001(define_split 1002 [(set (match_operand:TI 0 "nonimmediate_operand" "") 1003 (match_operand:TI 1 "general_operand" ""))] 1004 "TARGET_64BIT && reload_completed 1005 && s390_split_ok_p (operands[0], operands[1], TImode, 0)" 1006 [(set (match_dup 2) (match_dup 4)) 1007 (set (match_dup 3) (match_dup 5))] 1008{ 1009 operands[2] = operand_subword (operands[0], 0, 0, TImode); 1010 operands[3] = operand_subword (operands[0], 1, 0, TImode); 1011 operands[4] = operand_subword (operands[1], 0, 0, TImode); 1012 operands[5] = operand_subword (operands[1], 1, 0, TImode); 1013}) 1014 1015(define_split 1016 [(set (match_operand:TI 0 "nonimmediate_operand" "") 1017 (match_operand:TI 1 "general_operand" ""))] 1018 "TARGET_64BIT && reload_completed 1019 && s390_split_ok_p (operands[0], operands[1], TImode, 1)" 1020 [(set (match_dup 2) (match_dup 4)) 1021 (set (match_dup 3) (match_dup 5))] 1022{ 1023 operands[2] = operand_subword (operands[0], 1, 0, TImode); 1024 operands[3] = operand_subword (operands[0], 0, 0, TImode); 1025 operands[4] = operand_subword (operands[1], 1, 0, TImode); 1026 operands[5] = operand_subword (operands[1], 0, 0, TImode); 1027}) 1028 1029(define_split 1030 [(set (match_operand:TI 0 "register_operand" "") 1031 (match_operand:TI 1 "memory_operand" ""))] 1032 "TARGET_64BIT && reload_completed 1033 && !s_operand (operands[1], VOIDmode)" 1034 [(set (match_dup 0) (match_dup 1))] 1035{ 1036 rtx addr = operand_subword (operands[0], 1, 0, TImode); 1037 s390_load_address (addr, XEXP (operands[1], 0)); 1038 operands[1] = replace_equiv_address (operands[1], addr); 1039}) 1040 1041(define_expand "reload_outti" 1042 [(parallel [(match_operand:TI 0 "" "") 1043 (match_operand:TI 1 "register_operand" "d") 1044 (match_operand:DI 2 "register_operand" "=&a")])] 1045 "TARGET_64BIT" 1046{ 1047 if (GET_CODE (operands[0]) != MEM) 1048 abort (); 1049 s390_load_address (operands[2], XEXP (operands[0], 0)); 1050 operands[0] = replace_equiv_address (operands[0], operands[2]); 1051 emit_move_insn (operands[0], operands[1]); 1052 DONE; 1053}) 1054 1055; 1056; movdi instruction pattern(s). 1057; 1058 1059(define_expand "movdi" 1060 [(set (match_operand:DI 0 "general_operand" "") 1061 (match_operand:DI 1 "general_operand" ""))] 1062 "" 1063{ 1064 /* Handle symbolic constants. */ 1065 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) 1066 emit_symbolic_move (operands); 1067 1068 /* During and after reload, we need to force constants 1069 to the literal pool ourselves, if necessary. */ 1070 if ((reload_in_progress || reload_completed) 1071 && CONSTANT_P (operands[1]) 1072 && (!legitimate_reload_constant_p (operands[1]) 1073 || FP_REG_P (operands[0]))) 1074 operands[1] = force_const_mem (DImode, operands[1]); 1075}) 1076 1077(define_insn "*movdi_larl" 1078 [(set (match_operand:DI 0 "register_operand" "=d") 1079 (match_operand:DI 1 "larl_operand" "X"))] 1080 "TARGET_64BIT 1081 && !FP_REG_P (operands[0])" 1082 "larl\t%0,%1" 1083 [(set_attr "op_type" "RIL") 1084 (set_attr "type" "larl")]) 1085 1086(define_insn "*movdi_64" 1087 [(set (match_operand:DI 0 "nonimmediate_operand" 1088 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,?Q") 1089 (match_operand:DI 1 "general_operand" 1090 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,?Q"))] 1091 "TARGET_64BIT" 1092 "@ 1093 lghi\t%0,%h1 1094 llihh\t%0,%i1 1095 llihl\t%0,%i1 1096 llilh\t%0,%i1 1097 llill\t%0,%i1 1098 lay\t%0,%a1 1099 lgr\t%0,%1 1100 lg\t%0,%1 1101 stg\t%1,%0 1102 ldr\t%0,%1 1103 ld\t%0,%1 1104 ldy\t%0,%1 1105 std\t%1,%0 1106 stdy\t%1,%0 1107 mvc\t%O0(8,%R0),%1" 1108 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS") 1109 (set_attr "type" "*,*,*,*,*,la,lr,load,store,floadd,floadd,floadd, 1110 fstored,fstored,cs")]) 1111 1112(define_insn "*movdi_31" 1113 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q") 1114 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))] 1115 "!TARGET_64BIT" 1116 "@ 1117 lm\t%0,%N0,%1 1118 stm\t%1,%N1,%0 1119 # 1120 # 1121 ldr\t%0,%1 1122 ld\t%0,%1 1123 ldy\t%0,%1 1124 std\t%1,%0 1125 stdy\t%1,%0 1126 mvc\t%O0(8,%R0),%1" 1127 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS") 1128 (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")]) 1129 1130(define_split 1131 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1132 (match_operand:DI 1 "general_operand" ""))] 1133 "!TARGET_64BIT && reload_completed 1134 && s390_split_ok_p (operands[0], operands[1], DImode, 0)" 1135 [(set (match_dup 2) (match_dup 4)) 1136 (set (match_dup 3) (match_dup 5))] 1137{ 1138 operands[2] = operand_subword (operands[0], 0, 0, DImode); 1139 operands[3] = operand_subword (operands[0], 1, 0, DImode); 1140 operands[4] = operand_subword (operands[1], 0, 0, DImode); 1141 operands[5] = operand_subword (operands[1], 1, 0, DImode); 1142}) 1143 1144(define_split 1145 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1146 (match_operand:DI 1 "general_operand" ""))] 1147 "!TARGET_64BIT && reload_completed 1148 && s390_split_ok_p (operands[0], operands[1], DImode, 1)" 1149 [(set (match_dup 2) (match_dup 4)) 1150 (set (match_dup 3) (match_dup 5))] 1151{ 1152 operands[2] = operand_subword (operands[0], 1, 0, DImode); 1153 operands[3] = operand_subword (operands[0], 0, 0, DImode); 1154 operands[4] = operand_subword (operands[1], 1, 0, DImode); 1155 operands[5] = operand_subword (operands[1], 0, 0, DImode); 1156}) 1157 1158(define_split 1159 [(set (match_operand:DI 0 "register_operand" "") 1160 (match_operand:DI 1 "memory_operand" ""))] 1161 "!TARGET_64BIT && reload_completed 1162 && !FP_REG_P (operands[0]) 1163 && !s_operand (operands[1], VOIDmode)" 1164 [(set (match_dup 0) (match_dup 1))] 1165{ 1166 rtx addr = operand_subword (operands[0], 1, 0, DImode); 1167 s390_load_address (addr, XEXP (operands[1], 0)); 1168 operands[1] = replace_equiv_address (operands[1], addr); 1169}) 1170 1171(define_expand "reload_outdi" 1172 [(parallel [(match_operand:DI 0 "" "") 1173 (match_operand:DI 1 "register_operand" "d") 1174 (match_operand:SI 2 "register_operand" "=&a")])] 1175 "!TARGET_64BIT" 1176{ 1177 if (GET_CODE (operands[0]) != MEM) 1178 abort (); 1179 s390_load_address (operands[2], XEXP (operands[0], 0)); 1180 operands[0] = replace_equiv_address (operands[0], operands[2]); 1181 emit_move_insn (operands[0], operands[1]); 1182 DONE; 1183}) 1184 1185(define_peephole2 1186 [(set (match_operand:DI 0 "register_operand" "") 1187 (mem:DI (match_operand 1 "address_operand" "")))] 1188 "TARGET_64BIT 1189 && !FP_REG_P (operands[0]) 1190 && GET_CODE (operands[1]) == SYMBOL_REF 1191 && CONSTANT_POOL_ADDRESS_P (operands[1]) 1192 && get_pool_mode (operands[1]) == DImode 1193 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" 1194 [(set (match_dup 0) (match_dup 2))] 1195 "operands[2] = get_pool_constant (operands[1]);") 1196 1197(define_insn "*la_64" 1198 [(set (match_operand:DI 0 "register_operand" "=d,d") 1199 (match_operand:QI 1 "address_operand" "U,W"))] 1200 "TARGET_64BIT" 1201 "@ 1202 la\t%0,%a1 1203 lay\t%0,%a1" 1204 [(set_attr "op_type" "RX,RXY") 1205 (set_attr "type" "la")]) 1206 1207(define_peephole2 1208 [(parallel 1209 [(set (match_operand:DI 0 "register_operand" "") 1210 (match_operand:QI 1 "address_operand" "")) 1211 (clobber (reg:CC 33))])] 1212 "TARGET_64BIT 1213 && strict_memory_address_p (VOIDmode, operands[1]) 1214 && preferred_la_operand_p (operands[1])" 1215 [(set (match_dup 0) (match_dup 1))] 1216 "") 1217 1218(define_peephole2 1219 [(set (match_operand:DI 0 "register_operand" "") 1220 (match_operand:DI 1 "register_operand" "")) 1221 (parallel 1222 [(set (match_dup 0) 1223 (plus:DI (match_dup 0) 1224 (match_operand:DI 2 "nonmemory_operand" ""))) 1225 (clobber (reg:CC 33))])] 1226 "TARGET_64BIT 1227 && !reg_overlap_mentioned_p (operands[0], operands[2]) 1228 && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (DImode, operands[1], operands[2])) 1229 && preferred_la_operand_p (gen_rtx_PLUS (DImode, operands[1], operands[2]))" 1230 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] 1231 "") 1232 1233(define_expand "reload_indi" 1234 [(parallel [(match_operand:DI 0 "register_operand" "=a") 1235 (match_operand:DI 1 "s390_plus_operand" "") 1236 (match_operand:DI 2 "register_operand" "=&a")])] 1237 "TARGET_64BIT" 1238{ 1239 s390_expand_plus_operand (operands[0], operands[1], operands[2]); 1240 DONE; 1241}) 1242 1243; 1244; movsi instruction pattern(s). 1245; 1246 1247(define_expand "movsi" 1248 [(set (match_operand:SI 0 "general_operand" "") 1249 (match_operand:SI 1 "general_operand" ""))] 1250 "" 1251{ 1252 /* Handle symbolic constants. */ 1253 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) 1254 emit_symbolic_move (operands); 1255 1256 /* expr.c tries to load an effective address using 1257 force_reg. This fails because we don't have a 1258 generic load_address pattern. Convert the move 1259 to a proper arithmetic operation instead, unless 1260 it is guaranteed to be OK. */ 1261 if (GET_CODE (operands[1]) == PLUS 1262 && !legitimate_la_operand_p (operands[1])) 1263 { 1264 operands[1] = force_operand (operands[1], operands[0]); 1265 if (operands[1] == operands[0]) 1266 DONE; 1267 } 1268 1269 /* During and after reload, we need to force constants 1270 to the literal pool ourselves, if necessary. */ 1271 if ((reload_in_progress || reload_completed) 1272 && CONSTANT_P (operands[1]) 1273 && (!legitimate_reload_constant_p (operands[1]) 1274 || FP_REG_P (operands[0]))) 1275 operands[1] = force_const_mem (SImode, operands[1]); 1276}) 1277 1278(define_insn "*movsi_larl" 1279 [(set (match_operand:SI 0 "register_operand" "=d") 1280 (match_operand:SI 1 "larl_operand" "X"))] 1281 "!TARGET_64BIT && TARGET_CPU_ZARCH 1282 && !FP_REG_P (operands[0])" 1283 "larl\t%0,%1" 1284 [(set_attr "op_type" "RIL") 1285 (set_attr "type" "larl")]) 1286 1287(define_insn "*movsi_zarch" 1288 [(set (match_operand:SI 0 "nonimmediate_operand" 1289 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q") 1290 (match_operand:SI 1 "general_operand" 1291 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,?Q"))] 1292 "TARGET_ZARCH" 1293 "@ 1294 lhi\t%0,%h1 1295 llilh\t%0,%i1 1296 llill\t%0,%i1 1297 lay\t%0,%a1 1298 lr\t%0,%1 1299 l\t%0,%1 1300 ly\t%0,%1 1301 st\t%1,%0 1302 sty\t%1,%0 1303 ler\t%0,%1 1304 le\t%0,%1 1305 ley\t%0,%1 1306 ste\t%1,%0 1307 stey\t%1,%0 1308 mvc\t%O0(4,%R0),%1" 1309 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") 1310 (set_attr "type" "*,*,*,la,lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")]) 1311 1312(define_insn "*movsi_esa" 1313 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,?Q") 1314 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,?Q"))] 1315 "!TARGET_ZARCH" 1316 "@ 1317 lhi\t%0,%h1 1318 lr\t%0,%1 1319 l\t%0,%1 1320 st\t%1,%0 1321 ler\t%0,%1 1322 le\t%0,%1 1323 ste\t%1,%0 1324 mvc\t%O0(4,%R0),%1" 1325 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,SS") 1326 (set_attr "type" "*,lr,load,store,floads,floads,fstores,cs")]) 1327 1328(define_peephole2 1329 [(set (match_operand:SI 0 "register_operand" "") 1330 (mem:SI (match_operand 1 "address_operand" "")))] 1331 "!FP_REG_P (operands[0]) 1332 && GET_CODE (operands[1]) == SYMBOL_REF 1333 && CONSTANT_POOL_ADDRESS_P (operands[1]) 1334 && get_pool_mode (operands[1]) == SImode 1335 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" 1336 [(set (match_dup 0) (match_dup 2))] 1337 "operands[2] = get_pool_constant (operands[1]);") 1338 1339(define_insn "*la_31" 1340 [(set (match_operand:SI 0 "register_operand" "=d,d") 1341 (match_operand:QI 1 "address_operand" "U,W"))] 1342 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" 1343 "@ 1344 la\t%0,%a1 1345 lay\t%0,%a1" 1346 [(set_attr "op_type" "RX,RXY") 1347 (set_attr "type" "la")]) 1348 1349(define_peephole2 1350 [(parallel 1351 [(set (match_operand:SI 0 "register_operand" "") 1352 (match_operand:QI 1 "address_operand" "")) 1353 (clobber (reg:CC 33))])] 1354 "!TARGET_64BIT 1355 && strict_memory_address_p (VOIDmode, operands[1]) 1356 && preferred_la_operand_p (operands[1])" 1357 [(set (match_dup 0) (match_dup 1))] 1358 "") 1359 1360(define_peephole2 1361 [(set (match_operand:SI 0 "register_operand" "") 1362 (match_operand:SI 1 "register_operand" "")) 1363 (parallel 1364 [(set (match_dup 0) 1365 (plus:SI (match_dup 0) 1366 (match_operand:SI 2 "nonmemory_operand" ""))) 1367 (clobber (reg:CC 33))])] 1368 "!TARGET_64BIT 1369 && !reg_overlap_mentioned_p (operands[0], operands[2]) 1370 && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (SImode, operands[1], operands[2])) 1371 && preferred_la_operand_p (gen_rtx_PLUS (SImode, operands[1], operands[2]))" 1372 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] 1373 "") 1374 1375(define_insn "*la_31_and" 1376 [(set (match_operand:SI 0 "register_operand" "=d,d") 1377 (and:SI (match_operand:QI 1 "address_operand" "U,W") 1378 (const_int 2147483647)))] 1379 "!TARGET_64BIT" 1380 "@ 1381 la\t%0,%a1 1382 lay\t%0,%a1" 1383 [(set_attr "op_type" "RX,RXY") 1384 (set_attr "type" "la")]) 1385 1386(define_insn_and_split "*la_31_and_cc" 1387 [(set (match_operand:SI 0 "register_operand" "=d") 1388 (and:SI (match_operand:QI 1 "address_operand" "p") 1389 (const_int 2147483647))) 1390 (clobber (reg:CC 33))] 1391 "!TARGET_64BIT" 1392 "#" 1393 "&& reload_completed" 1394 [(set (match_dup 0) 1395 (and:SI (match_dup 1) (const_int 2147483647)))] 1396 "" 1397 [(set_attr "op_type" "RX") 1398 (set_attr "type" "la")]) 1399 1400(define_insn "force_la_31" 1401 [(set (match_operand:SI 0 "register_operand" "=d,d") 1402 (match_operand:QI 1 "address_operand" "U,W")) 1403 (use (const_int 0))] 1404 "!TARGET_64BIT" 1405 "@ 1406 la\t%0,%a1 1407 lay\t%0,%a1" 1408 [(set_attr "op_type" "RX") 1409 (set_attr "type" "la")]) 1410 1411(define_expand "reload_insi" 1412 [(parallel [(match_operand:SI 0 "register_operand" "=a") 1413 (match_operand:SI 1 "s390_plus_operand" "") 1414 (match_operand:SI 2 "register_operand" "=&a")])] 1415 "!TARGET_64BIT" 1416{ 1417 s390_expand_plus_operand (operands[0], operands[1], operands[2]); 1418 DONE; 1419}) 1420 1421; 1422; movhi instruction pattern(s). 1423; 1424 1425(define_expand "movhi" 1426 [(set (match_operand:HI 0 "nonimmediate_operand" "") 1427 (match_operand:HI 1 "general_operand" ""))] 1428 "" 1429{ 1430 /* Make it explicit that loading a register from memory 1431 always sign-extends (at least) to SImode. */ 1432 if (optimize && !no_new_pseudos 1433 && register_operand (operands[0], VOIDmode) 1434 && GET_CODE (operands[1]) == MEM 1435 && GET_CODE (XEXP (operands[1], 0)) != ADDRESSOF) 1436 { 1437 rtx tmp = gen_reg_rtx (SImode); 1438 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); 1439 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); 1440 operands[1] = gen_lowpart (HImode, tmp); 1441 } 1442}) 1443 1444(define_insn "*movhi" 1445 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") 1446 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] 1447 "" 1448 "@ 1449 lr\t%0,%1 1450 lhi\t%0,%h1 1451 lh\t%0,%1 1452 lhy\t%0,%1 1453 sth\t%1,%0 1454 sthy\t%1,%0 1455 mvc\t%O0(2,%R0),%1" 1456 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") 1457 (set_attr "type" "lr,*,*,*,store,store,cs")]) 1458 1459(define_peephole2 1460 [(set (match_operand:HI 0 "register_operand" "") 1461 (mem:HI (match_operand 1 "address_operand" "")))] 1462 "GET_CODE (operands[1]) == SYMBOL_REF 1463 && CONSTANT_POOL_ADDRESS_P (operands[1]) 1464 && get_pool_mode (operands[1]) == HImode 1465 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" 1466 [(set (match_dup 0) (match_dup 2))] 1467 "operands[2] = get_pool_constant (operands[1]);") 1468 1469; 1470; movqi instruction pattern(s). 1471; 1472 1473(define_expand "movqi" 1474 [(set (match_operand:QI 0 "nonimmediate_operand" "") 1475 (match_operand:QI 1 "general_operand" ""))] 1476 "" 1477{ 1478 /* On z/Architecture, zero-extending from memory to register 1479 is just as fast as a QImode load. */ 1480 if (TARGET_ZARCH && optimize && !no_new_pseudos 1481 && register_operand (operands[0], VOIDmode) 1482 && GET_CODE (operands[1]) == MEM 1483 && GET_CODE (XEXP (operands[1], 0)) != ADDRESSOF) 1484 { 1485 rtx tmp = gen_reg_rtx (word_mode); 1486 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); 1487 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); 1488 operands[1] = gen_lowpart (QImode, tmp); 1489 } 1490}) 1491 1492(define_insn "*movqi" 1493 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") 1494 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] 1495 "" 1496 "@ 1497 lr\t%0,%1 1498 lhi\t%0,%b1 1499 ic\t%0,%1 1500 icy\t%0,%1 1501 stc\t%1,%0 1502 stcy\t%1,%0 1503 mvi\t%0,%b1 1504 mviy\t%0,%b1 1505 mvc\t%O0(1,%R0),%1" 1506 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") 1507 (set_attr "type" "lr,*,*,*,store,store,store,store,cs")]) 1508 1509(define_peephole2 1510 [(set (match_operand:QI 0 "nonimmediate_operand" "") 1511 (mem:QI (match_operand 1 "address_operand" "")))] 1512 "GET_CODE (operands[1]) == SYMBOL_REF 1513 && CONSTANT_POOL_ADDRESS_P (operands[1]) 1514 && get_pool_mode (operands[1]) == QImode 1515 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" 1516 [(set (match_dup 0) (match_dup 2))] 1517 "operands[2] = get_pool_constant (operands[1]);") 1518 1519; 1520; movstrictqi instruction pattern(s). 1521; 1522 1523(define_insn "*movstrictqi" 1524 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) 1525 (match_operand:QI 1 "memory_operand" "R,T"))] 1526 "" 1527 "@ 1528 ic\t%0,%1 1529 icy\t%0,%1" 1530 [(set_attr "op_type" "RX,RXY")]) 1531 1532; 1533; movstricthi instruction pattern(s). 1534; 1535 1536(define_insn "*movstricthi" 1537 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) 1538 (match_operand:HI 1 "s_imm_operand" "Q,S")) 1539 (clobber (reg:CC 33))] 1540 "" 1541 "@ 1542 icm\t%0,3,%1 1543 icmy\t%0,3,%1" 1544 [(set_attr "op_type" "RS,RSY")]) 1545 1546; 1547; movstrictsi instruction pattern(s). 1548; 1549 1550(define_insn "movstrictsi" 1551 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d")) 1552 (match_operand:SI 1 "general_operand" "d,R,T"))] 1553 "TARGET_64BIT" 1554 "@ 1555 lr\t%0,%1 1556 l\t%0,%1 1557 ly\t%0,%1" 1558 [(set_attr "op_type" "RR,RX,RXY") 1559 (set_attr "type" "lr,load,load")]) 1560 1561; 1562; movdf instruction pattern(s). 1563; 1564 1565(define_expand "movdf" 1566 [(set (match_operand:DF 0 "nonimmediate_operand" "") 1567 (match_operand:DF 1 "general_operand" ""))] 1568 "" 1569{ 1570 /* During and after reload, we need to force constants 1571 to the literal pool ourselves, if necessary. */ 1572 if ((reload_in_progress || reload_completed) 1573 && CONSTANT_P (operands[1])) 1574 operands[1] = force_const_mem (DFmode, operands[1]); 1575}) 1576 1577(define_insn "*movdf_64" 1578 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q") 1579 (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))] 1580 "TARGET_64BIT" 1581 "@ 1582 ldr\t%0,%1 1583 ld\t%0,%1 1584 ldy\t%0,%1 1585 std\t%1,%0 1586 stdy\t%1,%0 1587 lgr\t%0,%1 1588 lg\t%0,%1 1589 stg\t%1,%0 1590 mvc\t%O0(8,%R0),%1" 1591 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") 1592 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")]) 1593 1594(define_insn "*movdf_31" 1595 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q") 1596 (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))] 1597 "!TARGET_64BIT" 1598 "@ 1599 ldr\t%0,%1 1600 ld\t%0,%1 1601 ldy\t%0,%1 1602 std\t%1,%0 1603 stdy\t%1,%0 1604 lm\t%0,%N0,%1 1605 stm\t%1,%N1,%0 1606 # 1607 # 1608 mvc\t%O0(8,%R0),%1" 1609 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS") 1610 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")]) 1611 1612(define_split 1613 [(set (match_operand:DF 0 "nonimmediate_operand" "") 1614 (match_operand:DF 1 "general_operand" ""))] 1615 "!TARGET_64BIT && reload_completed 1616 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" 1617 [(set (match_dup 2) (match_dup 4)) 1618 (set (match_dup 3) (match_dup 5))] 1619{ 1620 operands[2] = operand_subword (operands[0], 0, 0, DFmode); 1621 operands[3] = operand_subword (operands[0], 1, 0, DFmode); 1622 operands[4] = operand_subword (operands[1], 0, 0, DFmode); 1623 operands[5] = operand_subword (operands[1], 1, 0, DFmode); 1624}) 1625 1626(define_split 1627 [(set (match_operand:DF 0 "nonimmediate_operand" "") 1628 (match_operand:DF 1 "general_operand" ""))] 1629 "!TARGET_64BIT && reload_completed 1630 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" 1631 [(set (match_dup 2) (match_dup 4)) 1632 (set (match_dup 3) (match_dup 5))] 1633{ 1634 operands[2] = operand_subword (operands[0], 1, 0, DFmode); 1635 operands[3] = operand_subword (operands[0], 0, 0, DFmode); 1636 operands[4] = operand_subword (operands[1], 1, 0, DFmode); 1637 operands[5] = operand_subword (operands[1], 0, 0, DFmode); 1638}) 1639 1640(define_split 1641 [(set (match_operand:DF 0 "register_operand" "") 1642 (match_operand:DF 1 "memory_operand" ""))] 1643 "!TARGET_64BIT && reload_completed 1644 && !FP_REG_P (operands[0]) 1645 && !s_operand (operands[1], VOIDmode)" 1646 [(set (match_dup 0) (match_dup 1))] 1647{ 1648 rtx addr = operand_subword (operands[0], 1, 0, DFmode); 1649 s390_load_address (addr, XEXP (operands[1], 0)); 1650 operands[1] = replace_equiv_address (operands[1], addr); 1651}) 1652 1653(define_expand "reload_outdf" 1654 [(parallel [(match_operand:DF 0 "" "") 1655 (match_operand:DF 1 "register_operand" "d") 1656 (match_operand:SI 2 "register_operand" "=&a")])] 1657 "!TARGET_64BIT" 1658{ 1659 if (GET_CODE (operands[0]) != MEM) 1660 abort (); 1661 s390_load_address (operands[2], XEXP (operands[0], 0)); 1662 operands[0] = replace_equiv_address (operands[0], operands[2]); 1663 emit_move_insn (operands[0], operands[1]); 1664 DONE; 1665}) 1666 1667; 1668; movsf instruction pattern(s). 1669; 1670 1671(define_expand "movsf" 1672 [(set (match_operand:SF 0 "nonimmediate_operand" "") 1673 (match_operand:SF 1 "general_operand" ""))] 1674 "" 1675{ 1676 /* During and after reload, we need to force constants 1677 to the literal pool ourselves, if necessary. */ 1678 if ((reload_in_progress || reload_completed) 1679 && CONSTANT_P (operands[1])) 1680 operands[1] = force_const_mem (SFmode, operands[1]); 1681}) 1682 1683(define_insn "*movsf" 1684 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q") 1685 (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))] 1686 "" 1687 "@ 1688 ler\t%0,%1 1689 le\t%0,%1 1690 ley\t%0,%1 1691 ste\t%1,%0 1692 stey\t%1,%0 1693 lr\t%0,%1 1694 l\t%0,%1 1695 ly\t%0,%1 1696 st\t%1,%0 1697 sty\t%1,%0 1698 mvc\t%O0(4,%R0),%1" 1699 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") 1700 (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")]) 1701 1702; 1703; load_multiple pattern(s). 1704; 1705; ??? Due to reload problems with replacing registers inside match_parallel 1706; we currently support load_multiple/store_multiple only after reload. 1707; 1708 1709(define_expand "load_multiple" 1710 [(match_par_dup 3 [(set (match_operand 0 "" "") 1711 (match_operand 1 "" "")) 1712 (use (match_operand 2 "" ""))])] 1713 "reload_completed" 1714{ 1715 enum machine_mode mode; 1716 int regno; 1717 int count; 1718 rtx from; 1719 int i, off; 1720 1721 /* Support only loading a constant number of fixed-point registers from 1722 memory and only bother with this if more than two */ 1723 if (GET_CODE (operands[2]) != CONST_INT 1724 || INTVAL (operands[2]) < 2 1725 || INTVAL (operands[2]) > 16 1726 || GET_CODE (operands[1]) != MEM 1727 || GET_CODE (operands[0]) != REG 1728 || REGNO (operands[0]) >= 16) 1729 FAIL; 1730 1731 count = INTVAL (operands[2]); 1732 regno = REGNO (operands[0]); 1733 mode = GET_MODE (operands[0]); 1734 if (mode != SImode && mode != word_mode) 1735 FAIL; 1736 1737 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 1738 if (no_new_pseudos) 1739 { 1740 if (GET_CODE (XEXP (operands[1], 0)) == REG) 1741 { 1742 from = XEXP (operands[1], 0); 1743 off = 0; 1744 } 1745 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS 1746 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG 1747 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) 1748 { 1749 from = XEXP (XEXP (operands[1], 0), 0); 1750 off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); 1751 } 1752 else 1753 FAIL; 1754 1755 if (from == frame_pointer_rtx || from == arg_pointer_rtx) 1756 FAIL; 1757 } 1758 else 1759 { 1760 from = force_reg (Pmode, XEXP (operands[1], 0)); 1761 off = 0; 1762 } 1763 1764 for (i = 0; i < count; i++) 1765 XVECEXP (operands[3], 0, i) 1766 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), 1767 change_address (operands[1], mode, 1768 plus_constant (from, off + i * GET_MODE_SIZE (mode)))); 1769}) 1770 1771(define_insn "*load_multiple_di" 1772 [(match_parallel 0 "load_multiple_operation" 1773 [(set (match_operand:DI 1 "register_operand" "=r") 1774 (match_operand:DI 2 "s_operand" "QS"))])] 1775 "reload_completed && word_mode == DImode" 1776{ 1777 int words = XVECLEN (operands[0], 0); 1778 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); 1779 return "lmg\t%1,%0,%2"; 1780} 1781 [(set_attr "op_type" "RSY") 1782 (set_attr "type" "lm")]) 1783 1784(define_insn "*load_multiple_si" 1785 [(match_parallel 0 "load_multiple_operation" 1786 [(set (match_operand:SI 1 "register_operand" "=r,r") 1787 (match_operand:SI 2 "s_operand" "Q,S"))])] 1788 "reload_completed" 1789{ 1790 int words = XVECLEN (operands[0], 0); 1791 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); 1792 return which_alternative == 0 ? "lm\t%1,%0,%2" : "lmy\t%1,%0,%2"; 1793} 1794 [(set_attr "op_type" "RS,RSY") 1795 (set_attr "type" "lm")]) 1796 1797; 1798; store multiple pattern(s). 1799; 1800 1801(define_expand "store_multiple" 1802 [(match_par_dup 3 [(set (match_operand 0 "" "") 1803 (match_operand 1 "" "")) 1804 (use (match_operand 2 "" ""))])] 1805 "reload_completed" 1806{ 1807 enum machine_mode mode; 1808 int regno; 1809 int count; 1810 rtx to; 1811 int i, off; 1812 1813 /* Support only storing a constant number of fixed-point registers to 1814 memory and only bother with this if more than two. */ 1815 if (GET_CODE (operands[2]) != CONST_INT 1816 || INTVAL (operands[2]) < 2 1817 || INTVAL (operands[2]) > 16 1818 || GET_CODE (operands[0]) != MEM 1819 || GET_CODE (operands[1]) != REG 1820 || REGNO (operands[1]) >= 16) 1821 FAIL; 1822 1823 count = INTVAL (operands[2]); 1824 regno = REGNO (operands[1]); 1825 mode = GET_MODE (operands[1]); 1826 if (mode != SImode && mode != word_mode) 1827 FAIL; 1828 1829 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 1830 1831 if (no_new_pseudos) 1832 { 1833 if (GET_CODE (XEXP (operands[0], 0)) == REG) 1834 { 1835 to = XEXP (operands[0], 0); 1836 off = 0; 1837 } 1838 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS 1839 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG 1840 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) 1841 { 1842 to = XEXP (XEXP (operands[0], 0), 0); 1843 off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); 1844 } 1845 else 1846 FAIL; 1847 1848 if (to == frame_pointer_rtx || to == arg_pointer_rtx) 1849 FAIL; 1850 } 1851 else 1852 { 1853 to = force_reg (Pmode, XEXP (operands[0], 0)); 1854 off = 0; 1855 } 1856 1857 for (i = 0; i < count; i++) 1858 XVECEXP (operands[3], 0, i) 1859 = gen_rtx_SET (VOIDmode, 1860 change_address (operands[0], mode, 1861 plus_constant (to, off + i * GET_MODE_SIZE (mode))), 1862 gen_rtx_REG (mode, regno + i)); 1863}) 1864 1865(define_insn "*store_multiple_di" 1866 [(match_parallel 0 "store_multiple_operation" 1867 [(set (match_operand:DI 1 "s_operand" "=QS") 1868 (match_operand:DI 2 "register_operand" "r"))])] 1869 "reload_completed && word_mode == DImode" 1870{ 1871 int words = XVECLEN (operands[0], 0); 1872 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); 1873 return "stmg\t%2,%0,%1"; 1874} 1875 [(set_attr "op_type" "RSY") 1876 (set_attr "type" "stm")]) 1877 1878 1879(define_insn "*store_multiple_si" 1880 [(match_parallel 0 "store_multiple_operation" 1881 [(set (match_operand:SI 1 "s_operand" "=Q,S") 1882 (match_operand:SI 2 "register_operand" "r,r"))])] 1883 "reload_completed" 1884{ 1885 int words = XVECLEN (operands[0], 0); 1886 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); 1887 return which_alternative == 0 ? "stm\t%2,%0,%1" : "stmy\t%2,%0,%1"; 1888} 1889 [(set_attr "op_type" "RS,RSY") 1890 (set_attr "type" "stm")]) 1891 1892;; 1893;; String instructions. 1894;; 1895 1896; 1897; strlenM instruction pattern(s). 1898; 1899 1900(define_expand "strlendi" 1901 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) 1902 (parallel 1903 [(set (match_dup 4) 1904 (unspec:DI [(const_int 0) 1905 (match_operand:BLK 1 "memory_operand" "") 1906 (reg:QI 0) 1907 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) 1908 (clobber (scratch:DI)) 1909 (clobber (reg:CC 33))]) 1910 (parallel 1911 [(set (match_operand:DI 0 "register_operand" "") 1912 (minus:DI (match_dup 4) (match_dup 5))) 1913 (clobber (reg:CC 33))])] 1914 "TARGET_64BIT" 1915{ 1916 operands[4] = gen_reg_rtx (DImode); 1917 operands[5] = gen_reg_rtx (DImode); 1918 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); 1919 operands[1] = replace_equiv_address (operands[1], operands[5]); 1920}) 1921 1922(define_insn "*strlendi" 1923 [(set (match_operand:DI 0 "register_operand" "=a") 1924 (unspec:DI [(match_operand:DI 2 "general_operand" "0") 1925 (mem:BLK (match_operand:DI 3 "register_operand" "1")) 1926 (reg:QI 0) 1927 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) 1928 (clobber (match_scratch:DI 1 "=a")) 1929 (clobber (reg:CC 33))] 1930 "TARGET_64BIT" 1931 "srst\t%0,%1\;jo\t.-4" 1932 [(set_attr "op_type" "NN") 1933 (set_attr "type" "vs") 1934 (set_attr "length" "8")]) 1935 1936(define_expand "strlensi" 1937 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) 1938 (parallel 1939 [(set (match_dup 4) 1940 (unspec:SI [(const_int 0) 1941 (match_operand:BLK 1 "memory_operand" "") 1942 (reg:QI 0) 1943 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) 1944 (clobber (scratch:SI)) 1945 (clobber (reg:CC 33))]) 1946 (parallel 1947 [(set (match_operand:SI 0 "register_operand" "") 1948 (minus:SI (match_dup 4) (match_dup 5))) 1949 (clobber (reg:CC 33))])] 1950 "!TARGET_64BIT" 1951{ 1952 operands[4] = gen_reg_rtx (SImode); 1953 operands[5] = gen_reg_rtx (SImode); 1954 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); 1955 operands[1] = replace_equiv_address (operands[1], operands[5]); 1956}) 1957 1958(define_insn "*strlensi" 1959 [(set (match_operand:SI 0 "register_operand" "=a") 1960 (unspec:SI [(match_operand:SI 2 "general_operand" "0") 1961 (mem:BLK (match_operand:SI 3 "register_operand" "1")) 1962 (reg:QI 0) 1963 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) 1964 (clobber (match_scratch:SI 1 "=a")) 1965 (clobber (reg:CC 33))] 1966 "!TARGET_64BIT" 1967 "srst\t%0,%1\;jo\t.-4" 1968 [(set_attr "op_type" "NN") 1969 (set_attr "type" "vs") 1970 (set_attr "length" "8")]) 1971 1972; 1973; movstrM instruction pattern(s). 1974; 1975 1976(define_expand "movstrdi" 1977 [(set (match_operand:BLK 0 "memory_operand" "") 1978 (match_operand:BLK 1 "memory_operand" "")) 1979 (use (match_operand:DI 2 "general_operand" "")) 1980 (match_operand 3 "" "")] 1981 "TARGET_64BIT" 1982 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") 1983 1984(define_expand "movstrsi" 1985 [(set (match_operand:BLK 0 "memory_operand" "") 1986 (match_operand:BLK 1 "memory_operand" "")) 1987 (use (match_operand:SI 2 "general_operand" "")) 1988 (match_operand 3 "" "")] 1989 "" 1990 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") 1991 1992; Move a block that is up to 256 bytes in length. 1993; The block length is taken as (operands[2] % 256) + 1. 1994 1995(define_expand "movstr_short" 1996 [(parallel 1997 [(set (match_operand:BLK 0 "memory_operand" "") 1998 (match_operand:BLK 1 "memory_operand" "")) 1999 (use (match_operand 2 "nonmemory_operand" "")) 2000 (clobber (match_dup 3))])] 2001 "" 2002 "operands[3] = gen_rtx_SCRATCH (Pmode);") 2003 2004(define_insn "*movstr_short" 2005 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") 2006 (match_operand:BLK 1 "memory_operand" "Q,Q")) 2007 (use (match_operand 2 "nonmemory_operand" "n,a")) 2008 (clobber (match_scratch 3 "=X,&a"))] 2009 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) 2010 && GET_MODE (operands[3]) == Pmode" 2011{ 2012 switch (which_alternative) 2013 { 2014 case 0: 2015 return "mvc\t%O0(%b2+1,%R0),%1"; 2016 2017 case 1: 2018 output_asm_insn ("bras\t%3,.+10", operands); 2019 output_asm_insn ("mvc\t%O0(1,%R0),%1", operands); 2020 return "ex\t%2,0(%3)"; 2021 2022 default: 2023 abort (); 2024 } 2025} 2026 [(set_attr "op_type" "SS,NN") 2027 (set_attr "type" "cs,cs") 2028 (set_attr "atype" "*,agen") 2029 (set_attr "length" "*,14")]) 2030 2031; Move a block of arbitrary length. 2032 2033(define_expand "movstr_long" 2034 [(parallel 2035 [(clobber (match_dup 2)) 2036 (clobber (match_dup 3)) 2037 (set (match_operand:BLK 0 "memory_operand" "") 2038 (match_operand:BLK 1 "memory_operand" "")) 2039 (use (match_operand 2 "general_operand" "")) 2040 (use (match_dup 3)) 2041 (clobber (reg:CC 33))])] 2042 "" 2043{ 2044 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; 2045 rtx reg0 = gen_reg_rtx (dword_mode); 2046 rtx reg1 = gen_reg_rtx (dword_mode); 2047 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); 2048 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); 2049 rtx len0 = gen_lowpart (Pmode, reg0); 2050 rtx len1 = gen_lowpart (Pmode, reg1); 2051 2052 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); 2053 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 2054 emit_move_insn (len0, operands[2]); 2055 2056 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); 2057 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); 2058 emit_move_insn (len1, operands[2]); 2059 2060 operands[0] = replace_equiv_address_nv (operands[0], addr0); 2061 operands[1] = replace_equiv_address_nv (operands[1], addr1); 2062 operands[2] = reg0; 2063 operands[3] = reg1; 2064}) 2065 2066(define_insn "*movstr_long_64" 2067 [(clobber (match_operand:TI 0 "register_operand" "=d")) 2068 (clobber (match_operand:TI 1 "register_operand" "=d")) 2069 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) 2070 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))) 2071 (use (match_dup 2)) 2072 (use (match_dup 3)) 2073 (clobber (reg:CC 33))] 2074 "TARGET_64BIT" 2075 "mvcle\t%0,%1,0\;jo\t.-4" 2076 [(set_attr "op_type" "NN") 2077 (set_attr "type" "vs") 2078 (set_attr "length" "8")]) 2079 2080(define_insn "*movstr_long_31" 2081 [(clobber (match_operand:DI 0 "register_operand" "=d")) 2082 (clobber (match_operand:DI 1 "register_operand" "=d")) 2083 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) 2084 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))) 2085 (use (match_dup 2)) 2086 (use (match_dup 3)) 2087 (clobber (reg:CC 33))] 2088 "!TARGET_64BIT" 2089 "mvcle\t%0,%1,0\;jo\t.-4" 2090 [(set_attr "op_type" "NN") 2091 (set_attr "type" "vs") 2092 (set_attr "length" "8")]) 2093 2094; 2095; clrstrM instruction pattern(s). 2096; 2097 2098(define_expand "clrstrdi" 2099 [(set (match_operand:BLK 0 "memory_operand" "") 2100 (const_int 0)) 2101 (use (match_operand:DI 1 "general_operand" "")) 2102 (match_operand 2 "" "")] 2103 "TARGET_64BIT" 2104 "s390_expand_clrstr (operands[0], operands[1]); DONE;") 2105 2106(define_expand "clrstrsi" 2107 [(set (match_operand:BLK 0 "memory_operand" "") 2108 (const_int 0)) 2109 (use (match_operand:SI 1 "general_operand" "")) 2110 (match_operand 2 "" "")] 2111 "" 2112 "s390_expand_clrstr (operands[0], operands[1]); DONE;") 2113 2114; Clear a block that is up to 256 bytes in length. 2115; The block length is taken as (operands[1] % 256) + 1. 2116 2117(define_expand "clrstr_short" 2118 [(parallel 2119 [(set (match_operand:BLK 0 "memory_operand" "") 2120 (const_int 0)) 2121 (use (match_operand 1 "nonmemory_operand" "")) 2122 (clobber (match_dup 2)) 2123 (clobber (reg:CC 33))])] 2124 "" 2125 "operands[2] = gen_rtx_SCRATCH (Pmode);") 2126 2127(define_insn "*clrstr_short" 2128 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") 2129 (const_int 0)) 2130 (use (match_operand 1 "nonmemory_operand" "n,a")) 2131 (clobber (match_scratch 2 "=X,&a")) 2132 (clobber (reg:CC 33))] 2133 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) 2134 && GET_MODE (operands[2]) == Pmode" 2135{ 2136 switch (which_alternative) 2137 { 2138 case 0: 2139 return "xc\t%O0(%b1+1,%R0),%0"; 2140 2141 case 1: 2142 output_asm_insn ("bras\t%2,.+10", operands); 2143 output_asm_insn ("xc\t%O0(1,%R0),%0", operands); 2144 return "ex\t%1,0(%2)"; 2145 2146 default: 2147 abort (); 2148 } 2149} 2150 [(set_attr "op_type" "SS,NN") 2151 (set_attr "type" "cs,cs") 2152 (set_attr "atype" "*,agen") 2153 (set_attr "length" "*,14")]) 2154 2155; Clear a block of arbitrary length. 2156 2157(define_expand "clrstr_long" 2158 [(parallel 2159 [(clobber (match_dup 1)) 2160 (set (match_operand:BLK 0 "memory_operand" "") 2161 (const_int 0)) 2162 (use (match_operand 1 "general_operand" "")) 2163 (use (match_dup 2)) 2164 (clobber (reg:CC 33))])] 2165 "" 2166{ 2167 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; 2168 rtx reg0 = gen_reg_rtx (dword_mode); 2169 rtx reg1 = gen_reg_rtx (dword_mode); 2170 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); 2171 rtx len0 = gen_lowpart (Pmode, reg0); 2172 2173 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); 2174 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 2175 emit_move_insn (len0, operands[1]); 2176 2177 emit_move_insn (reg1, const0_rtx); 2178 2179 operands[0] = replace_equiv_address_nv (operands[0], addr0); 2180 operands[1] = reg0; 2181 operands[2] = reg1; 2182}) 2183 2184(define_insn "*clrstr_long_64" 2185 [(clobber (match_operand:TI 0 "register_operand" "=d")) 2186 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) 2187 (const_int 0)) 2188 (use (match_dup 2)) 2189 (use (match_operand:TI 1 "register_operand" "d")) 2190 (clobber (reg:CC 33))] 2191 "TARGET_64BIT" 2192 "mvcle\t%0,%1,0\;jo\t.-4" 2193 [(set_attr "op_type" "NN") 2194 (set_attr "type" "vs") 2195 (set_attr "length" "8")]) 2196 2197(define_insn "*clrstr_long_31" 2198 [(clobber (match_operand:DI 0 "register_operand" "=d")) 2199 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) 2200 (const_int 0)) 2201 (use (match_dup 2)) 2202 (use (match_operand:DI 1 "register_operand" "d")) 2203 (clobber (reg:CC 33))] 2204 "!TARGET_64BIT" 2205 "mvcle\t%0,%1,0\;jo\t.-4" 2206 [(set_attr "op_type" "NN") 2207 (set_attr "type" "vs") 2208 (set_attr "length" "8")]) 2209 2210; 2211; cmpmemM instruction pattern(s). 2212; 2213 2214(define_expand "cmpmemdi" 2215 [(set (match_operand:DI 0 "register_operand" "") 2216 (compare:DI (match_operand:BLK 1 "memory_operand" "") 2217 (match_operand:BLK 2 "memory_operand" "") ) ) 2218 (use (match_operand:DI 3 "general_operand" "")) 2219 (use (match_operand:DI 4 "" ""))] 2220 "TARGET_64BIT" 2221 "s390_expand_cmpmem (operands[0], operands[1], 2222 operands[2], operands[3]); DONE;") 2223 2224(define_expand "cmpmemsi" 2225 [(set (match_operand:SI 0 "register_operand" "") 2226 (compare:SI (match_operand:BLK 1 "memory_operand" "") 2227 (match_operand:BLK 2 "memory_operand" "") ) ) 2228 (use (match_operand:SI 3 "general_operand" "")) 2229 (use (match_operand:SI 4 "" ""))] 2230 "" 2231 "s390_expand_cmpmem (operands[0], operands[1], 2232 operands[2], operands[3]); DONE;") 2233 2234; Compare a block that is up to 256 bytes in length. 2235; The block length is taken as (operands[2] % 256) + 1. 2236 2237(define_expand "cmpmem_short" 2238 [(parallel 2239 [(set (reg:CCS 33) 2240 (compare:CCS (match_operand:BLK 0 "memory_operand" "") 2241 (match_operand:BLK 1 "memory_operand" ""))) 2242 (use (match_operand 2 "nonmemory_operand" "")) 2243 (clobber (match_dup 3))])] 2244 "" 2245 "operands[3] = gen_rtx_SCRATCH (Pmode);") 2246 2247(define_insn "*cmpmem_short" 2248 [(set (reg:CCS 33) 2249 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q") 2250 (match_operand:BLK 1 "memory_operand" "Q,Q"))) 2251 (use (match_operand 2 "nonmemory_operand" "n,a")) 2252 (clobber (match_scratch 3 "=X,&a"))] 2253 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) 2254 && GET_MODE (operands[3]) == Pmode" 2255{ 2256 switch (which_alternative) 2257 { 2258 case 0: 2259 return "clc\t%O0(%b2+1,%R0),%1"; 2260 2261 case 1: 2262 output_asm_insn ("bras\t%3,.+10", operands); 2263 output_asm_insn ("clc\t%O0(1,%R0),%1", operands); 2264 return "ex\t%2,0(%3)"; 2265 2266 default: 2267 abort (); 2268 } 2269} 2270 [(set_attr "op_type" "SS,NN") 2271 (set_attr "type" "cs,cs") 2272 (set_attr "atype" "*,agen") 2273 (set_attr "length" "*,14")]) 2274 2275; Compare a block of arbitrary length. 2276 2277(define_expand "cmpmem_long" 2278 [(parallel 2279 [(clobber (match_dup 2)) 2280 (clobber (match_dup 3)) 2281 (set (reg:CCS 33) 2282 (compare:CCS (match_operand:BLK 0 "memory_operand" "") 2283 (match_operand:BLK 1 "memory_operand" ""))) 2284 (use (match_operand 2 "general_operand" "")) 2285 (use (match_dup 3))])] 2286 "" 2287{ 2288 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; 2289 rtx reg0 = gen_reg_rtx (dword_mode); 2290 rtx reg1 = gen_reg_rtx (dword_mode); 2291 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); 2292 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); 2293 rtx len0 = gen_lowpart (Pmode, reg0); 2294 rtx len1 = gen_lowpart (Pmode, reg1); 2295 2296 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); 2297 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 2298 emit_move_insn (len0, operands[2]); 2299 2300 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); 2301 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); 2302 emit_move_insn (len1, operands[2]); 2303 2304 operands[0] = replace_equiv_address_nv (operands[0], addr0); 2305 operands[1] = replace_equiv_address_nv (operands[1], addr1); 2306 operands[2] = reg0; 2307 operands[3] = reg1; 2308}) 2309 2310(define_insn "*cmpmem_long_64" 2311 [(clobber (match_operand:TI 0 "register_operand" "=d")) 2312 (clobber (match_operand:TI 1 "register_operand" "=d")) 2313 (set (reg:CCS 33) 2314 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) 2315 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) 2316 (use (match_dup 2)) 2317 (use (match_dup 3))] 2318 "TARGET_64BIT" 2319 "clcle\t%0,%1,0\;jo\t.-4" 2320 [(set_attr "op_type" "NN") 2321 (set_attr "type" "vs") 2322 (set_attr "length" "8")]) 2323 2324(define_insn "*cmpmem_long_31" 2325 [(clobber (match_operand:DI 0 "register_operand" "=d")) 2326 (clobber (match_operand:DI 1 "register_operand" "=d")) 2327 (set (reg:CCS 33) 2328 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) 2329 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) 2330 (use (match_dup 2)) 2331 (use (match_dup 3))] 2332 "!TARGET_64BIT" 2333 "clcle\t%0,%1,0\;jo\t.-4" 2334 [(set_attr "op_type" "NN") 2335 (set_attr "type" "vs") 2336 (set_attr "length" "8")]) 2337 2338; Convert condition code to integer in range (-1, 0, 1) 2339 2340(define_insn "cmpint_si" 2341 [(set (match_operand:SI 0 "register_operand" "=d") 2342 (compare:SI (reg:CCS 33) (const_int 0)))] 2343 "" 2344{ 2345 output_asm_insn ("lhi\t%0,1", operands); 2346 output_asm_insn ("jh\t.+12", operands); 2347 output_asm_insn ("jl\t.+6", operands); 2348 output_asm_insn ("sr\t%0,%0", operands); 2349 return "lcr\t%0,%0"; 2350} 2351 [(set_attr "op_type" "NN") 2352 (set_attr "length" "16") 2353 (set_attr "type" "other")]) 2354 2355(define_insn "cmpint_di" 2356 [(set (match_operand:DI 0 "register_operand" "=d") 2357 (compare:DI (reg:CCS 33) (const_int 0)))] 2358 "TARGET_64BIT" 2359{ 2360 output_asm_insn ("lghi\t%0,1", operands); 2361 output_asm_insn ("jh\t.+16", operands); 2362 output_asm_insn ("jl\t.+8", operands); 2363 output_asm_insn ("sgr\t%0,%0", operands); 2364 return "lcgr\t%0,%0"; 2365} 2366 [(set_attr "op_type" "NN") 2367 (set_attr "length" "20") 2368 (set_attr "type" "other")]) 2369 2370 2371;; 2372;;- Conversion instructions. 2373;; 2374 2375(define_insn "*sethighqisi" 2376 [(set (match_operand:SI 0 "register_operand" "=d,d") 2377 (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) 2378 (clobber (reg:CC 33))] 2379 "" 2380 "@ 2381 icm\t%0,8,%1 2382 icmy\t%0,8,%1" 2383 [(set_attr "op_type" "RS,RSY")]) 2384 2385(define_insn "*sethighhisi" 2386 [(set (match_operand:SI 0 "register_operand" "=d,d") 2387 (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) 2388 (clobber (reg:CC 33))] 2389 "" 2390 "@ 2391 icm\t%0,12,%1 2392 icmy\t%0,12,%1" 2393 [(set_attr "op_type" "RS,RSY")]) 2394 2395(define_insn "*sethighqidi_64" 2396 [(set (match_operand:DI 0 "register_operand" "=d") 2397 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) 2398 (clobber (reg:CC 33))] 2399 "TARGET_64BIT" 2400 "icmh\t%0,8,%1" 2401 [(set_attr "op_type" "RSY")]) 2402 2403(define_insn "*sethighqidi_31" 2404 [(set (match_operand:DI 0 "register_operand" "=d,d") 2405 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) 2406 (clobber (reg:CC 33))] 2407 "!TARGET_64BIT" 2408 "@ 2409 icm\t%0,8,%1 2410 icmy\t%0,8,%1" 2411 [(set_attr "op_type" "RS,RSY")]) 2412 2413(define_insn_and_split "*extractqi" 2414 [(set (match_operand:SI 0 "register_operand" "=d") 2415 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") 2416 (match_operand 2 "const_int_operand" "n") 2417 (const_int 0))) 2418 (clobber (reg:CC 33))] 2419 "!TARGET_64BIT 2420 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" 2421 "#" 2422 "&& reload_completed" 2423 [(parallel 2424 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) 2425 (clobber (reg:CC 33))]) 2426 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] 2427{ 2428 operands[2] = GEN_INT (32 - INTVAL (operands[2])); 2429 operands[1] = change_address (operands[1], QImode, 0); 2430} 2431 [(set_attr "atype" "agen")]) 2432 2433(define_insn_and_split "*extracthi" 2434 [(set (match_operand:SI 0 "register_operand" "=d") 2435 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") 2436 (match_operand 2 "const_int_operand" "n") 2437 (const_int 0))) 2438 (clobber (reg:CC 33))] 2439 "!TARGET_64BIT 2440 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" 2441 "#" 2442 "&& reload_completed" 2443 [(parallel 2444 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) 2445 (clobber (reg:CC 33))]) 2446 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] 2447{ 2448 operands[2] = GEN_INT (32 - INTVAL (operands[2])); 2449 operands[1] = change_address (operands[1], HImode, 0); 2450} 2451 [(set_attr "atype" "agen")]) 2452 2453; 2454; extendsidi2 instruction pattern(s). 2455; 2456 2457(define_expand "extendsidi2" 2458 [(set (match_operand:DI 0 "register_operand" "") 2459 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 2460 "" 2461 " 2462{ 2463 if (!TARGET_64BIT) 2464 { 2465 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); 2466 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); 2467 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); 2468 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); 2469 DONE; 2470 } 2471} 2472") 2473 2474(define_insn "*extendsidi2" 2475 [(set (match_operand:DI 0 "register_operand" "=d,d") 2476 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] 2477 "TARGET_64BIT" 2478 "@ 2479 lgfr\t%0,%1 2480 lgf\t%0,%1" 2481 [(set_attr "op_type" "RRE,RXY")]) 2482 2483; 2484; extendhidi2 instruction pattern(s). 2485; 2486 2487(define_expand "extendhidi2" 2488 [(set (match_operand:DI 0 "register_operand" "") 2489 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] 2490 "" 2491 " 2492{ 2493 if (!TARGET_64BIT) 2494 { 2495 rtx tmp = gen_reg_rtx (SImode); 2496 emit_insn (gen_extendhisi2 (tmp, operands[1])); 2497 emit_insn (gen_extendsidi2 (operands[0], tmp)); 2498 DONE; 2499 } 2500 else 2501 { 2502 operands[1] = gen_lowpart (DImode, operands[1]); 2503 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); 2504 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); 2505 DONE; 2506 } 2507} 2508") 2509 2510(define_insn "*extendhidi2" 2511 [(set (match_operand:DI 0 "register_operand" "=d") 2512 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] 2513 "TARGET_64BIT" 2514 "lgh\t%0,%1" 2515 [(set_attr "op_type" "RXY")]) 2516 2517; 2518; extendqidi2 instruction pattern(s). 2519; 2520 2521(define_expand "extendqidi2" 2522 [(set (match_operand:DI 0 "register_operand" "") 2523 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] 2524 "" 2525 " 2526{ 2527 if (!TARGET_64BIT) 2528 { 2529 rtx tmp = gen_reg_rtx (SImode); 2530 emit_insn (gen_extendqisi2 (tmp, operands[1])); 2531 emit_insn (gen_extendsidi2 (operands[0], tmp)); 2532 DONE; 2533 } 2534 else 2535 { 2536 operands[1] = gen_lowpart (DImode, operands[1]); 2537 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); 2538 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); 2539 DONE; 2540 } 2541} 2542") 2543 2544(define_insn "*extendqidi2" 2545 [(set (match_operand:DI 0 "register_operand" "=d") 2546 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] 2547 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" 2548 "lgb\t%0,%1" 2549 [(set_attr "op_type" "RXY")]) 2550 2551(define_insn_and_split "*extendqidi2_short_displ" 2552 [(set (match_operand:DI 0 "register_operand" "=d") 2553 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q"))) 2554 (clobber (reg:CC 33))] 2555 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT" 2556 "#" 2557 "&& reload_completed" 2558 [(parallel 2559 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) 2560 (clobber (reg:CC 33))]) 2561 (parallel 2562 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) 2563 (clobber (reg:CC 33))])] 2564 "") 2565 2566; 2567; extendhisi2 instruction pattern(s). 2568; 2569 2570(define_expand "extendhisi2" 2571 [(set (match_operand:SI 0 "register_operand" "") 2572 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] 2573 "" 2574 " 2575{ 2576 operands[1] = gen_lowpart (SImode, operands[1]); 2577 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); 2578 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); 2579 DONE; 2580} 2581") 2582 2583(define_insn "*extendhisi2" 2584 [(set (match_operand:SI 0 "register_operand" "=d,d") 2585 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] 2586 "" 2587 "@ 2588 lh\t%0,%1 2589 lhy\t%0,%1" 2590 [(set_attr "op_type" "RX,RXY")]) 2591 2592; 2593; extendqisi2 instruction pattern(s). 2594; 2595 2596(define_expand "extendqisi2" 2597 [(set (match_operand:SI 0 "register_operand" "") 2598 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] 2599 "" 2600 " 2601{ 2602 operands[1] = gen_lowpart (SImode, operands[1]); 2603 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); 2604 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); 2605 DONE; 2606} 2607") 2608 2609(define_insn "*extendqisi2" 2610 [(set (match_operand:SI 0 "register_operand" "=d") 2611 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] 2612 "TARGET_LONG_DISPLACEMENT" 2613 "lb\t%0,%1" 2614 [(set_attr "op_type" "RXY")]) 2615 2616(define_insn_and_split "*extendsiqi2_short_displ" 2617 [(set (match_operand:SI 0 "register_operand" "=d") 2618 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q"))) 2619 (clobber (reg:CC 33))] 2620 "!TARGET_LONG_DISPLACEMENT" 2621 "#" 2622 "&& reload_completed" 2623 [(parallel 2624 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) 2625 (clobber (reg:CC 33))]) 2626 (parallel 2627 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) 2628 (clobber (reg:CC 33))])] 2629 "") 2630 2631; 2632; extendqihi2 instruction pattern(s). 2633; 2634 2635 2636; 2637; zero_extendsidi2 instruction pattern(s). 2638; 2639 2640(define_expand "zero_extendsidi2" 2641 [(set (match_operand:DI 0 "register_operand" "") 2642 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 2643 "" 2644 " 2645{ 2646 if (!TARGET_64BIT) 2647 { 2648 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); 2649 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); 2650 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); 2651 DONE; 2652 } 2653} 2654") 2655 2656(define_insn "*zero_extendsidi2" 2657 [(set (match_operand:DI 0 "register_operand" "=d,d") 2658 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] 2659 "TARGET_64BIT" 2660 "@ 2661 llgfr\t%0,%1 2662 llgf\t%0,%1" 2663 [(set_attr "op_type" "RRE,RXY")]) 2664 2665; 2666; zero_extendhidi2 instruction pattern(s). 2667; 2668 2669(define_expand "zero_extendhidi2" 2670 [(set (match_operand:DI 0 "register_operand" "") 2671 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] 2672 "" 2673 " 2674{ 2675 if (!TARGET_64BIT) 2676 { 2677 rtx tmp = gen_reg_rtx (SImode); 2678 emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); 2679 emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); 2680 DONE; 2681 } 2682 else 2683 { 2684 operands[1] = gen_lowpart (DImode, operands[1]); 2685 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); 2686 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); 2687 DONE; 2688 } 2689} 2690") 2691 2692(define_insn "*zero_extendhidi2" 2693 [(set (match_operand:DI 0 "register_operand" "=d") 2694 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] 2695 "TARGET_64BIT" 2696 "llgh\t%0,%1" 2697 [(set_attr "op_type" "RXY")]) 2698 2699; 2700; LLGT-type instructions (zero-extend from 31 bit to 64 bit). 2701; 2702 2703(define_insn "*llgt_sisi" 2704 [(set (match_operand:SI 0 "register_operand" "=d,d") 2705 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") 2706 (const_int 2147483647)))] 2707 "TARGET_64BIT" 2708 "@ 2709 llgtr\t%0,%1 2710 llgt\t%0,%1" 2711 [(set_attr "op_type" "RRE,RXE")]) 2712 2713(define_split 2714 [(set (match_operand:SI 0 "register_operand" "") 2715 (and:SI (match_operand:SI 1 "nonimmediate_operand" "") 2716 (const_int 2147483647))) 2717 (clobber (reg:CC 33))] 2718 "TARGET_64BIT && reload_completed" 2719 [(set (match_dup 0) 2720 (and:SI (match_dup 1) 2721 (const_int 2147483647)))] 2722 "") 2723 2724(define_insn "*llgt_didi" 2725 [(set (match_operand:DI 0 "register_operand" "=d,d") 2726 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") 2727 (const_int 2147483647)))] 2728 "TARGET_64BIT" 2729 "@ 2730 llgtr\t%0,%1 2731 llgt\t%0,%N1" 2732 [(set_attr "op_type" "RRE,RXE")]) 2733 2734(define_split 2735 [(set (match_operand:DI 0 "register_operand" "") 2736 (and:DI (match_operand:DI 1 "nonimmediate_operand" "") 2737 (const_int 2147483647))) 2738 (clobber (reg:CC 33))] 2739 "TARGET_64BIT && reload_completed" 2740 [(set (match_dup 0) 2741 (and:DI (match_dup 1) 2742 (const_int 2147483647)))] 2743 "") 2744 2745(define_insn "*llgt_sidi" 2746 [(set (match_operand:DI 0 "register_operand" "=d") 2747 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) 2748 (const_int 2147483647)))] 2749 "TARGET_64BIT" 2750 "llgt\t%0,%1" 2751 [(set_attr "op_type" "RXE")]) 2752 2753(define_insn_and_split "*llgt_sidi_split" 2754 [(set (match_operand:DI 0 "register_operand" "=d") 2755 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) 2756 (const_int 2147483647))) 2757 (clobber (reg:CC 33))] 2758 "TARGET_64BIT" 2759 "#" 2760 "&& reload_completed" 2761 [(set (match_dup 0) 2762 (and:DI (subreg:DI (match_dup 1) 0) 2763 (const_int 2147483647)))] 2764 "") 2765 2766; 2767; zero_extendqidi2 instruction pattern(s) 2768; 2769 2770(define_expand "zero_extendqidi2" 2771 [(set (match_operand:DI 0 "register_operand" "") 2772 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] 2773 "" 2774 " 2775{ 2776 if (!TARGET_64BIT) 2777 { 2778 rtx tmp = gen_reg_rtx (SImode); 2779 emit_insn (gen_zero_extendqisi2 (tmp, operands[1])); 2780 emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); 2781 DONE; 2782 } 2783 else 2784 { 2785 operands[1] = gen_lowpart (DImode, operands[1]); 2786 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); 2787 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); 2788 DONE; 2789 } 2790} 2791") 2792 2793(define_insn "*zero_extendqidi2" 2794 [(set (match_operand:DI 0 "register_operand" "=d") 2795 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] 2796 "TARGET_64BIT" 2797 "llgc\t%0,%1" 2798 [(set_attr "op_type" "RXY")]) 2799 2800; 2801; zero_extendhisi2 instruction pattern(s). 2802; 2803 2804(define_expand "zero_extendhisi2" 2805 [(set (match_operand:SI 0 "register_operand" "") 2806 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] 2807 "" 2808 " 2809{ 2810 operands[1] = gen_lowpart (SImode, operands[1]); 2811 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); 2812 DONE; 2813} 2814") 2815 2816(define_insn "*zero_extendhisi2_64" 2817 [(set (match_operand:SI 0 "register_operand" "=d") 2818 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] 2819 "TARGET_64BIT" 2820 "llgh\t%0,%1" 2821 [(set_attr "op_type" "RXY")]) 2822 2823(define_insn_and_split "*zero_extendhisi2_31" 2824 [(set (match_operand:SI 0 "register_operand" "=&d") 2825 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) 2826 (clobber (reg:CC 33))] 2827 "!TARGET_64BIT" 2828 "#" 2829 "&& reload_completed" 2830 [(set (match_dup 0) (const_int 0)) 2831 (parallel 2832 [(set (strict_low_part (match_dup 2)) (match_dup 1)) 2833 (clobber (reg:CC 33))])] 2834 "operands[2] = gen_lowpart (HImode, operands[0]);" 2835 [(set_attr "atype" "agen")]) 2836 2837; 2838; zero_extendqisi2 instruction pattern(s). 2839; 2840 2841(define_expand "zero_extendqisi2" 2842 [(set (match_operand:SI 0 "register_operand" "") 2843 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] 2844 "" 2845 " 2846{ 2847 operands[1] = gen_lowpart (SImode, operands[1]); 2848 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff))); 2849 DONE; 2850} 2851") 2852 2853(define_insn "*zero_extendqisi2_64" 2854 [(set (match_operand:SI 0 "register_operand" "=d") 2855 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] 2856 "TARGET_ZARCH" 2857 "llgc\t%0,%1" 2858 [(set_attr "op_type" "RXY")]) 2859 2860(define_insn_and_split "*zero_extendqisi2_31" 2861 [(set (match_operand:SI 0 "register_operand" "=&d") 2862 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] 2863 "!TARGET_ZARCH" 2864 "#" 2865 "&& reload_completed" 2866 [(set (match_dup 0) (const_int 0)) 2867 (set (strict_low_part (match_dup 2)) (match_dup 1))] 2868 "operands[2] = gen_lowpart (QImode, operands[0]);" 2869 [(set_attr "atype" "agen")]) 2870 2871; 2872; zero_extendqihi2 instruction pattern(s). 2873; 2874 2875(define_expand "zero_extendqihi2" 2876 [(set (match_operand:HI 0 "register_operand" "") 2877 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] 2878 "TARGET_ZARCH" 2879 " 2880{ 2881 operands[1] = gen_lowpart (HImode, operands[1]); 2882 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); 2883 DONE; 2884} 2885") 2886 2887(define_insn "*zero_extendqihi2_64" 2888 [(set (match_operand:HI 0 "register_operand" "=d") 2889 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] 2890 "TARGET_ZARCH" 2891 "llgc\t%0,%1" 2892 [(set_attr "op_type" "RXY")]) 2893 2894(define_insn_and_split "*zero_extendqihi2_31" 2895 [(set (match_operand:HI 0 "register_operand" "=&d") 2896 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] 2897 "!TARGET_ZARCH" 2898 "#" 2899 "&& reload_completed" 2900 [(set (match_dup 0) (const_int 0)) 2901 (set (strict_low_part (match_dup 2)) (match_dup 1))] 2902 "operands[2] = gen_lowpart (QImode, operands[0]);" 2903 [(set_attr "atype" "agen")]) 2904 2905 2906; 2907; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). 2908; 2909 2910(define_expand "fixuns_truncdfdi2" 2911 [(set (match_operand:DI 0 "register_operand" "") 2912 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] 2913 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2914{ 2915 rtx label1 = gen_label_rtx (); 2916 rtx label2 = gen_label_rtx (); 2917 rtx temp = gen_reg_rtx (DFmode); 2918 operands[1] = force_reg (DFmode, operands[1]); 2919 2920 emit_insn (gen_cmpdf (operands[1], 2921 CONST_DOUBLE_FROM_REAL_VALUE ( 2922 REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode))); 2923 emit_jump_insn (gen_blt (label1)); 2924 emit_insn (gen_subdf3 (temp, operands[1], 2925 CONST_DOUBLE_FROM_REAL_VALUE ( 2926 REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode))); 2927 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); 2928 emit_jump (label2); 2929 2930 emit_label (label1); 2931 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); 2932 emit_label (label2); 2933 DONE; 2934}) 2935 2936(define_expand "fix_truncdfdi2" 2937 [(set (match_operand:DI 0 "register_operand" "") 2938 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] 2939 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2940{ 2941 operands[1] = force_reg (DFmode, operands[1]); 2942 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); 2943 DONE; 2944}) 2945 2946(define_insn "fix_truncdfdi2_ieee" 2947 [(set (match_operand:DI 0 "register_operand" "=d") 2948 (fix:DI (match_operand:DF 1 "register_operand" "f"))) 2949 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) 2950 (clobber (reg:CC 33))] 2951 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2952 "cgdbr\t%0,%h2,%1" 2953 [(set_attr "op_type" "RRE") 2954 (set_attr "type" "ftoi")]) 2955 2956; 2957; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). 2958; 2959 2960(define_expand "fixuns_truncdfsi2" 2961 [(set (match_operand:SI 0 "register_operand" "") 2962 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] 2963 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2964{ 2965 rtx label1 = gen_label_rtx (); 2966 rtx label2 = gen_label_rtx (); 2967 rtx temp = gen_reg_rtx (DFmode); 2968 2969 operands[1] = force_reg (DFmode,operands[1]); 2970 emit_insn (gen_cmpdf (operands[1], 2971 CONST_DOUBLE_FROM_REAL_VALUE ( 2972 REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode))); 2973 emit_jump_insn (gen_blt (label1)); 2974 emit_insn (gen_subdf3 (temp, operands[1], 2975 CONST_DOUBLE_FROM_REAL_VALUE ( 2976 REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode))); 2977 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); 2978 emit_jump (label2); 2979 2980 emit_label (label1); 2981 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); 2982 emit_label (label2); 2983 DONE; 2984}) 2985 2986(define_expand "fix_truncdfsi2" 2987 [(set (match_operand:SI 0 "register_operand" "") 2988 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] 2989 "TARGET_HARD_FLOAT" 2990{ 2991 if (TARGET_IBM_FLOAT) 2992 { 2993 /* This is the algorithm from POP chapter A.5.7.2. */ 2994 2995 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); 2996 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); 2997 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); 2998 2999 operands[1] = force_reg (DFmode, operands[1]); 3000 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], 3001 two31r, two32, temp)); 3002 } 3003 else 3004 { 3005 operands[1] = force_reg (DFmode, operands[1]); 3006 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); 3007 } 3008 3009 DONE; 3010}) 3011 3012(define_insn "fix_truncdfsi2_ieee" 3013 [(set (match_operand:SI 0 "register_operand" "=d") 3014 (fix:SI (match_operand:DF 1 "register_operand" "f"))) 3015 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) 3016 (clobber (reg:CC 33))] 3017 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3018 "cfdbr\t%0,%h2,%1" 3019 [(set_attr "op_type" "RRE") 3020 (set_attr "type" "other" )]) 3021 3022(define_insn "fix_truncdfsi2_ibm" 3023 [(set (match_operand:SI 0 "register_operand" "=d") 3024 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) 3025 (use (match_operand:DI 2 "immediate_operand" "m")) 3026 (use (match_operand:DI 3 "immediate_operand" "m")) 3027 (use (match_operand:BLK 4 "memory_operand" "m")) 3028 (clobber (reg:CC 33))] 3029 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 3030{ 3031 output_asm_insn ("sd\t%1,%2", operands); 3032 output_asm_insn ("aw\t%1,%3", operands); 3033 output_asm_insn ("std\t%1,%4", operands); 3034 output_asm_insn ("xi\t%N4,128", operands); 3035 return "l\t%0,%N4"; 3036} 3037 [(set_attr "op_type" "NN") 3038 (set_attr "type" "ftoi") 3039 (set_attr "atype" "agen") 3040 (set_attr "length" "20")]) 3041 3042; 3043; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). 3044; 3045 3046(define_expand "fixuns_truncsfdi2" 3047 [(set (match_operand:DI 0 "register_operand" "") 3048 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] 3049 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3050{ 3051 rtx label1 = gen_label_rtx (); 3052 rtx label2 = gen_label_rtx (); 3053 rtx temp = gen_reg_rtx (SFmode); 3054 3055 operands[1] = force_reg (SFmode, operands[1]); 3056 emit_insn (gen_cmpsf (operands[1], 3057 CONST_DOUBLE_FROM_REAL_VALUE ( 3058 REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode))); 3059 emit_jump_insn (gen_blt (label1)); 3060 3061 emit_insn (gen_subsf3 (temp, operands[1], 3062 CONST_DOUBLE_FROM_REAL_VALUE ( 3063 REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode))); 3064 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); 3065 emit_jump (label2); 3066 3067 emit_label (label1); 3068 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); 3069 emit_label (label2); 3070 DONE; 3071}) 3072 3073(define_expand "fix_truncsfdi2" 3074 [(set (match_operand:DI 0 "register_operand" "") 3075 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] 3076 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3077{ 3078 operands[1] = force_reg (SFmode, operands[1]); 3079 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); 3080 DONE; 3081}) 3082 3083(define_insn "fix_truncsfdi2_ieee" 3084 [(set (match_operand:DI 0 "register_operand" "=d") 3085 (fix:DI (match_operand:SF 1 "register_operand" "f"))) 3086 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) 3087 (clobber (reg:CC 33))] 3088 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3089 "cgebr\t%0,%h2,%1" 3090 [(set_attr "op_type" "RRE") 3091 (set_attr "type" "ftoi")]) 3092 3093; 3094; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). 3095; 3096 3097(define_expand "fixuns_truncsfsi2" 3098 [(set (match_operand:SI 0 "register_operand" "") 3099 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] 3100 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3101{ 3102 rtx label1 = gen_label_rtx (); 3103 rtx label2 = gen_label_rtx (); 3104 rtx temp = gen_reg_rtx (SFmode); 3105 3106 operands[1] = force_reg (SFmode, operands[1]); 3107 emit_insn (gen_cmpsf (operands[1], 3108 CONST_DOUBLE_FROM_REAL_VALUE ( 3109 REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode))); 3110 emit_jump_insn (gen_blt (label1)); 3111 emit_insn (gen_subsf3 (temp, operands[1], 3112 CONST_DOUBLE_FROM_REAL_VALUE ( 3113 REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode))); 3114 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); 3115 emit_jump (label2); 3116 3117 emit_label (label1); 3118 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); 3119 emit_label (label2); 3120 DONE; 3121}) 3122 3123(define_expand "fix_truncsfsi2" 3124 [(set (match_operand:SI 0 "register_operand" "") 3125 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] 3126 "TARGET_HARD_FLOAT" 3127{ 3128 if (TARGET_IBM_FLOAT) 3129 { 3130 /* Convert to DFmode and then use the POP algorithm. */ 3131 rtx temp = gen_reg_rtx (DFmode); 3132 emit_insn (gen_extendsfdf2 (temp, operands[1])); 3133 emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); 3134 } 3135 else 3136 { 3137 operands[1] = force_reg (SFmode, operands[1]); 3138 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); 3139 } 3140 3141 DONE; 3142}) 3143 3144(define_insn "fix_truncsfsi2_ieee" 3145 [(set (match_operand:SI 0 "register_operand" "=d") 3146 (fix:SI (match_operand:SF 1 "register_operand" "f"))) 3147 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) 3148 (clobber (reg:CC 33))] 3149 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3150 "cfebr\t%0,%h2,%1" 3151 [(set_attr "op_type" "RRE") 3152 (set_attr "type" "ftoi")]) 3153 3154; 3155; floatdidf2 instruction pattern(s). 3156; 3157 3158(define_insn "floatdidf2" 3159 [(set (match_operand:DF 0 "register_operand" "=f") 3160 (float:DF (match_operand:DI 1 "register_operand" "d"))) 3161 (clobber (reg:CC 33))] 3162 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3163 "cdgbr\t%0,%1" 3164 [(set_attr "op_type" "RRE") 3165 (set_attr "type" "itof" )]) 3166 3167; 3168; floatdisf2 instruction pattern(s). 3169; 3170 3171(define_insn "floatdisf2" 3172 [(set (match_operand:SF 0 "register_operand" "=f") 3173 (float:SF (match_operand:DI 1 "register_operand" "d"))) 3174 (clobber (reg:CC 33))] 3175 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3176 "cegbr\t%0,%1" 3177 [(set_attr "op_type" "RRE") 3178 (set_attr "type" "itof" )]) 3179 3180; 3181; floatsidf2 instruction pattern(s). 3182; 3183 3184(define_expand "floatsidf2" 3185 [(parallel 3186 [(set (match_operand:DF 0 "register_operand" "") 3187 (float:DF (match_operand:SI 1 "register_operand" ""))) 3188 (clobber (reg:CC 33))])] 3189 "TARGET_HARD_FLOAT" 3190{ 3191 if (TARGET_IBM_FLOAT) 3192 { 3193 /* This is the algorithm from POP chapter A.5.7.1. */ 3194 3195 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); 3196 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); 3197 3198 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); 3199 DONE; 3200 } 3201}) 3202 3203(define_insn "floatsidf2_ieee" 3204 [(set (match_operand:DF 0 "register_operand" "=f") 3205 (float:DF (match_operand:SI 1 "register_operand" "d"))) 3206 (clobber (reg:CC 33))] 3207 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3208 "cdfbr\t%0,%1" 3209 [(set_attr "op_type" "RRE") 3210 (set_attr "type" "itof" )]) 3211 3212(define_insn "floatsidf2_ibm" 3213 [(set (match_operand:DF 0 "register_operand" "=f") 3214 (float:DF (match_operand:SI 1 "register_operand" "d"))) 3215 (use (match_operand:DI 2 "immediate_operand" "m")) 3216 (use (match_operand:BLK 3 "memory_operand" "m")) 3217 (clobber (reg:CC 33))] 3218 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 3219{ 3220 output_asm_insn ("st\t%1,%N3", operands); 3221 output_asm_insn ("xi\t%N3,128", operands); 3222 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); 3223 output_asm_insn ("ld\t%0,%3", operands); 3224 return "sd\t%0,%2"; 3225} 3226 [(set_attr "op_type" "NN") 3227 (set_attr "type" "other" ) 3228 (set_attr "atype" "agen") 3229 (set_attr "length" "20")]) 3230 3231; 3232; floatsisf2 instruction pattern(s). 3233; 3234 3235(define_expand "floatsisf2" 3236 [(parallel 3237 [(set (match_operand:SF 0 "register_operand" "") 3238 (float:SF (match_operand:SI 1 "register_operand" ""))) 3239 (clobber (reg:CC 33))])] 3240 "TARGET_HARD_FLOAT" 3241{ 3242 if (TARGET_IBM_FLOAT) 3243 { 3244 /* Use the POP algorithm to convert to DFmode and then truncate. */ 3245 rtx temp = gen_reg_rtx (DFmode); 3246 emit_insn (gen_floatsidf2 (temp, operands[1])); 3247 emit_insn (gen_truncdfsf2 (operands[0], temp)); 3248 DONE; 3249 } 3250}) 3251 3252(define_insn "floatsisf2_ieee" 3253 [(set (match_operand:SF 0 "register_operand" "=f") 3254 (float:SF (match_operand:SI 1 "register_operand" "d"))) 3255 (clobber (reg:CC 33))] 3256 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3257 "cefbr\t%0,%1" 3258 [(set_attr "op_type" "RRE") 3259 (set_attr "type" "itof" )]) 3260 3261; 3262; truncdfsf2 instruction pattern(s). 3263; 3264 3265(define_expand "truncdfsf2" 3266 [(set (match_operand:SF 0 "register_operand" "") 3267 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))] 3268 "TARGET_HARD_FLOAT" 3269 "") 3270 3271(define_insn "truncdfsf2_ieee" 3272 [(set (match_operand:SF 0 "register_operand" "=f") 3273 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] 3274 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3275 "ledbr\t%0,%1" 3276 [(set_attr "op_type" "RRE")]) 3277 3278(define_insn "truncdfsf2_ibm" 3279 [(set (match_operand:SF 0 "register_operand" "=f,f") 3280 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))] 3281 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 3282 "@ 3283 lrer\t%0,%1 3284 le\t%0,%1" 3285 [(set_attr "op_type" "RR,RX") 3286 (set_attr "type" "floads,floads")]) 3287 3288; 3289; extendsfdf2 instruction pattern(s). 3290; 3291 3292(define_expand "extendsfdf2" 3293 [(set (match_operand:DF 0 "register_operand" "") 3294 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] 3295 "TARGET_HARD_FLOAT" 3296{ 3297 if (TARGET_IBM_FLOAT) 3298 { 3299 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); 3300 DONE; 3301 } 3302}) 3303 3304(define_insn "extendsfdf2_ieee" 3305 [(set (match_operand:DF 0 "register_operand" "=f,f") 3306 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] 3307 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3308 "@ 3309 ldebr\t%0,%1 3310 ldeb\t%0,%1" 3311 [(set_attr "op_type" "RRE,RXE") 3312 (set_attr "type" "floads,floads")]) 3313 3314(define_insn "extendsfdf2_ibm" 3315 [(set (match_operand:DF 0 "register_operand" "=f,f") 3316 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) 3317 (clobber (reg:CC 33))] 3318 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 3319 "@ 3320 sdr\t%0,%0\;ler\t%0,%1 3321 sdr\t%0,%0\;le\t%0,%1" 3322 [(set_attr "op_type" "NN,NN") 3323 (set_attr "atype" "reg,agen") 3324 (set_attr "length" "4,6") 3325 (set_attr "type" "o2,o2")]) 3326 3327 3328;; 3329;; ARITHMETIC OPERATIONS 3330;; 3331; arithmetic operations set the ConditionCode, 3332; because of unpredictable Bits in Register for Halfword and Byte 3333; the ConditionCode can be set wrong in operations for Halfword and Byte 3334 3335;; 3336;;- Add instructions. 3337;; 3338 3339; 3340; adddi3 instruction pattern(s). 3341; 3342 3343(define_insn "*adddi3_sign" 3344 [(set (match_operand:DI 0 "register_operand" "=d,d") 3345 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) 3346 (match_operand:DI 1 "register_operand" "0,0"))) 3347 (clobber (reg:CC 33))] 3348 "TARGET_64BIT" 3349 "@ 3350 agfr\t%0,%2 3351 agf\t%0,%2" 3352 [(set_attr "op_type" "RRE,RXY")]) 3353 3354(define_insn "*adddi3_zero_cc" 3355 [(set (reg 33) 3356 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) 3357 (match_operand:DI 1 "register_operand" "0,0")) 3358 (const_int 0))) 3359 (set (match_operand:DI 0 "register_operand" "=d,d") 3360 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] 3361 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 3362 "@ 3363 algfr\t%0,%2 3364 algf\t%0,%2" 3365 [(set_attr "op_type" "RRE,RXY")]) 3366 3367(define_insn "*adddi3_zero_cconly" 3368 [(set (reg 33) 3369 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) 3370 (match_operand:DI 1 "register_operand" "0,0")) 3371 (const_int 0))) 3372 (clobber (match_scratch:DI 0 "=d,d"))] 3373 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 3374 "@ 3375 algfr\t%0,%2 3376 algf\t%0,%2" 3377 [(set_attr "op_type" "RRE,RXY")]) 3378 3379(define_insn "*adddi3_zero" 3380 [(set (match_operand:DI 0 "register_operand" "=d,d") 3381 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) 3382 (match_operand:DI 1 "register_operand" "0,0"))) 3383 (clobber (reg:CC 33))] 3384 "TARGET_64BIT" 3385 "@ 3386 algfr\t%0,%2 3387 algf\t%0,%2" 3388 [(set_attr "op_type" "RRE,RXY")]) 3389 3390(define_insn "*adddi3_imm_cc" 3391 [(set (reg 33) 3392 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") 3393 (match_operand:DI 2 "const_int_operand" "K")) 3394 (const_int 0))) 3395 (set (match_operand:DI 0 "register_operand" "=d") 3396 (plus:DI (match_dup 1) (match_dup 2)))] 3397 "TARGET_64BIT 3398 && s390_match_ccmode (insn, CCAmode) 3399 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" 3400 "aghi\t%0,%h2" 3401 [(set_attr "op_type" "RI")]) 3402 3403(define_insn "*adddi3_carry1_cc" 3404 [(set (reg 33) 3405 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 3406 (match_operand:DI 2 "general_operand" "d,m")) 3407 (match_dup 1))) 3408 (set (match_operand:DI 0 "register_operand" "=d,d") 3409 (plus:DI (match_dup 1) (match_dup 2)))] 3410 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" 3411 "@ 3412 algr\t%0,%2 3413 alg\t%0,%2" 3414 [(set_attr "op_type" "RRE,RXY")]) 3415 3416(define_insn "*adddi3_carry1_cconly" 3417 [(set (reg 33) 3418 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 3419 (match_operand:DI 2 "general_operand" "d,m")) 3420 (match_dup 1))) 3421 (clobber (match_scratch:DI 0 "=d,d"))] 3422 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" 3423 "@ 3424 algr\t%0,%2 3425 alg\t%0,%2" 3426 [(set_attr "op_type" "RRE,RXY")]) 3427 3428(define_insn "*adddi3_carry2_cc" 3429 [(set (reg 33) 3430 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 3431 (match_operand:DI 2 "general_operand" "d,m")) 3432 (match_dup 2))) 3433 (set (match_operand:DI 0 "register_operand" "=d,d") 3434 (plus:DI (match_dup 1) (match_dup 2)))] 3435 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" 3436 "@ 3437 algr\t%0,%2 3438 alg\t%0,%2" 3439 [(set_attr "op_type" "RRE,RXY")]) 3440 3441(define_insn "*adddi3_carry2_cconly" 3442 [(set (reg 33) 3443 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 3444 (match_operand:DI 2 "general_operand" "d,m")) 3445 (match_dup 2))) 3446 (clobber (match_scratch:DI 0 "=d,d"))] 3447 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" 3448 "@ 3449 algr\t%0,%2 3450 alg\t%0,%2" 3451 [(set_attr "op_type" "RRE,RXY")]) 3452 3453(define_insn "*adddi3_cc" 3454 [(set (reg 33) 3455 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 3456 (match_operand:DI 2 "general_operand" "d,m")) 3457 (const_int 0))) 3458 (set (match_operand:DI 0 "register_operand" "=d,d") 3459 (plus:DI (match_dup 1) (match_dup 2)))] 3460 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 3461 "@ 3462 algr\t%0,%2 3463 alg\t%0,%2" 3464 [(set_attr "op_type" "RRE,RXY")]) 3465 3466(define_insn "*adddi3_cconly" 3467 [(set (reg 33) 3468 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 3469 (match_operand:DI 2 "general_operand" "d,m")) 3470 (const_int 0))) 3471 (clobber (match_scratch:DI 0 "=d,d"))] 3472 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 3473 "@ 3474 algr\t%0,%2 3475 alg\t%0,%2" 3476 [(set_attr "op_type" "RRE,RXY")]) 3477 3478(define_insn "*adddi3_cconly2" 3479 [(set (reg 33) 3480 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") 3481 (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) 3482 (clobber (match_scratch:DI 0 "=d,d"))] 3483 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" 3484 "@ 3485 algr\t%0,%2 3486 alg\t%0,%2" 3487 [(set_attr "op_type" "RRE,RXY")]) 3488 3489(define_insn "*adddi3_64" 3490 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 3491 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") 3492 (match_operand:DI 2 "general_operand" "d,K,m") ) ) 3493 (clobber (reg:CC 33))] 3494 "TARGET_64BIT" 3495 "@ 3496 agr\t%0,%2 3497 aghi\t%0,%h2 3498 ag\t%0,%2" 3499 [(set_attr "op_type" "RRE,RI,RXY")]) 3500 3501(define_insn_and_split "*adddi3_31z" 3502 [(set (match_operand:DI 0 "register_operand" "=&d") 3503 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") 3504 (match_operand:DI 2 "general_operand" "do") ) ) 3505 (clobber (reg:CC 33))] 3506 "!TARGET_64BIT && TARGET_CPU_ZARCH" 3507 "#" 3508 "&& reload_completed" 3509 [(parallel 3510 [(set (reg:CCL1 33) 3511 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) 3512 (match_dup 7))) 3513 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) 3514 (parallel 3515 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) 3516 (ltu:SI (reg:CCL1 33) (const_int 0)))) 3517 (clobber (reg:CC 33))])] 3518 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 3519 operands[4] = operand_subword (operands[1], 0, 0, DImode); 3520 operands[5] = operand_subword (operands[2], 0, 0, DImode); 3521 operands[6] = operand_subword (operands[0], 1, 0, DImode); 3522 operands[7] = operand_subword (operands[1], 1, 0, DImode); 3523 operands[8] = operand_subword (operands[2], 1, 0, DImode);" 3524 [(set_attr "op_type" "NN")]) 3525 3526(define_insn_and_split "*adddi3_31" 3527 [(set (match_operand:DI 0 "register_operand" "=&d") 3528 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") 3529 (match_operand:DI 2 "general_operand" "do") ) ) 3530 (clobber (reg:CC 33))] 3531 "!TARGET_CPU_ZARCH" 3532 "#" 3533 "&& reload_completed" 3534 [(parallel 3535 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) 3536 (clobber (reg:CC 33))]) 3537 (parallel 3538 [(set (reg:CCL1 33) 3539 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) 3540 (match_dup 7))) 3541 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) 3542 (set (pc) 3543 (if_then_else (ltu (reg:CCL1 33) (const_int 0)) 3544 (pc) 3545 (label_ref (match_dup 9)))) 3546 (parallel 3547 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) 3548 (clobber (reg:CC 33))]) 3549 (match_dup 9)] 3550 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 3551 operands[4] = operand_subword (operands[1], 0, 0, DImode); 3552 operands[5] = operand_subword (operands[2], 0, 0, DImode); 3553 operands[6] = operand_subword (operands[0], 1, 0, DImode); 3554 operands[7] = operand_subword (operands[1], 1, 0, DImode); 3555 operands[8] = operand_subword (operands[2], 1, 0, DImode); 3556 operands[9] = gen_label_rtx ();" 3557 [(set_attr "op_type" "NN")]) 3558 3559(define_expand "adddi3" 3560 [(parallel 3561 [(set (match_operand:DI 0 "register_operand" "") 3562 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") 3563 (match_operand:DI 2 "general_operand" ""))) 3564 (clobber (reg:CC 33))])] 3565 "" 3566 "") 3567 3568; 3569; addsi3 instruction pattern(s). 3570; 3571 3572(define_insn "*addsi3_imm_cc" 3573 [(set (reg 33) 3574 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") 3575 (match_operand:SI 2 "const_int_operand" "K")) 3576 (const_int 0))) 3577 (set (match_operand:SI 0 "register_operand" "=d") 3578 (plus:SI (match_dup 1) (match_dup 2)))] 3579 "s390_match_ccmode (insn, CCAmode) 3580 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" 3581 "ahi\t%0,%h2" 3582 [(set_attr "op_type" "RI")]) 3583 3584(define_insn "*addsi3_carry1_cc" 3585 [(set (reg 33) 3586 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 3587 (match_operand:SI 2 "general_operand" "d,R,T")) 3588 (match_dup 1))) 3589 (set (match_operand:SI 0 "register_operand" "=d,d,d") 3590 (plus:SI (match_dup 1) (match_dup 2)))] 3591 "s390_match_ccmode (insn, CCL1mode)" 3592 "@ 3593 alr\t%0,%2 3594 al\t%0,%2 3595 aly\t%0,%2" 3596 [(set_attr "op_type" "RR,RX,RXY")]) 3597 3598(define_insn "*addsi3_carry1_cconly" 3599 [(set (reg 33) 3600 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 3601 (match_operand:SI 2 "general_operand" "d,R,T")) 3602 (match_dup 1))) 3603 (clobber (match_scratch:SI 0 "=d,d,d"))] 3604 "s390_match_ccmode (insn, CCL1mode)" 3605 "@ 3606 alr\t%0,%2 3607 al\t%0,%2 3608 aly\t%0,%2" 3609 [(set_attr "op_type" "RR,RX,RXY")]) 3610 3611(define_insn "*addsi3_carry2_cc" 3612 [(set (reg 33) 3613 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 3614 (match_operand:SI 2 "general_operand" "d,R,T")) 3615 (match_dup 2))) 3616 (set (match_operand:SI 0 "register_operand" "=d,d,d") 3617 (plus:SI (match_dup 1) (match_dup 2)))] 3618 "s390_match_ccmode (insn, CCL1mode)" 3619 "@ 3620 alr\t%0,%2 3621 al\t%0,%2 3622 aly\t%0,%2" 3623 [(set_attr "op_type" "RR,RX,RXY")]) 3624 3625(define_insn "*addsi3_carry2_cconly" 3626 [(set (reg 33) 3627 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 3628 (match_operand:SI 2 "general_operand" "d,R,T")) 3629 (match_dup 2))) 3630 (clobber (match_scratch:SI 0 "=d,d,d"))] 3631 "s390_match_ccmode (insn, CCL1mode)" 3632 "@ 3633 alr\t%0,%2 3634 al\t%0,%2 3635 aly\t%0,%2" 3636 [(set_attr "op_type" "RR,RX,RXY")]) 3637 3638(define_insn "*addsi3_cc" 3639 [(set (reg 33) 3640 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 3641 (match_operand:SI 2 "general_operand" "d,R,T")) 3642 (const_int 0))) 3643 (set (match_operand:SI 0 "register_operand" "=d,d,d") 3644 (plus:SI (match_dup 1) (match_dup 2)))] 3645 "s390_match_ccmode (insn, CCLmode)" 3646 "@ 3647 alr\t%0,%2 3648 al\t%0,%2 3649 aly\t%0,%2" 3650 [(set_attr "op_type" "RR,RX,RXY")]) 3651 3652(define_insn "*addsi3_cconly" 3653 [(set (reg 33) 3654 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 3655 (match_operand:SI 2 "general_operand" "d,R,T")) 3656 (const_int 0))) 3657 (clobber (match_scratch:SI 0 "=d,d,d"))] 3658 "s390_match_ccmode (insn, CCLmode)" 3659 "@ 3660 alr\t%0,%2 3661 al\t%0,%2 3662 aly\t%0,%2" 3663 [(set_attr "op_type" "RR,RX,RXY")]) 3664 3665(define_insn "*addsi3_cconly2" 3666 [(set (reg 33) 3667 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 3668 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) 3669 (clobber (match_scratch:SI 0 "=d,d,d"))] 3670 "s390_match_ccmode (insn, CCLmode)" 3671 "@ 3672 alr\t%0,%2 3673 al\t%0,%2 3674 aly\t%0,%2" 3675 [(set_attr "op_type" "RR,RX,RXY")]) 3676 3677(define_insn "*addsi3_sign" 3678 [(set (match_operand:SI 0 "register_operand" "=d,d") 3679 (plus:SI (match_operand:SI 1 "register_operand" "0,0") 3680 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) 3681 (clobber (reg:CC 33))] 3682 "" 3683 "@ 3684 ah\t%0,%2 3685 ahy\t%0,%2" 3686 [(set_attr "op_type" "RX,RXY")]) 3687 3688(define_insn "addsi3" 3689 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") 3690 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") 3691 (match_operand:SI 2 "general_operand" "d,K,R,T"))) 3692 (clobber (reg:CC 33))] 3693 "" 3694 "@ 3695 ar\t%0,%2 3696 ahi\t%0,%h2 3697 a\t%0,%2 3698 ay\t%0,%2" 3699 [(set_attr "op_type" "RR,RI,RX,RXY")]) 3700 3701; 3702; adddf3 instruction pattern(s). 3703; 3704 3705(define_expand "adddf3" 3706 [(parallel 3707 [(set (match_operand:DF 0 "register_operand" "=f,f") 3708 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 3709 (match_operand:DF 2 "general_operand" "f,R"))) 3710 (clobber (reg:CC 33))])] 3711 "TARGET_HARD_FLOAT" 3712 "") 3713 3714(define_insn "*adddf3" 3715 [(set (match_operand:DF 0 "register_operand" "=f,f") 3716 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 3717 (match_operand:DF 2 "general_operand" "f,R"))) 3718 (clobber (reg:CC 33))] 3719 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3720 "@ 3721 adbr\t%0,%2 3722 adb\t%0,%2" 3723 [(set_attr "op_type" "RRE,RXE") 3724 (set_attr "type" "fsimpd,fsimpd")]) 3725 3726(define_insn "*adddf3_cc" 3727 [(set (reg 33) 3728 (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 3729 (match_operand:DF 2 "general_operand" "f,R")) 3730 (match_operand:DF 3 "const0_operand" ""))) 3731 (set (match_operand:DF 0 "register_operand" "=f,f") 3732 (plus:DF (match_dup 1) (match_dup 2)))] 3733 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3734 "@ 3735 adbr\t%0,%2 3736 adb\t%0,%2" 3737 [(set_attr "op_type" "RRE,RXE") 3738 (set_attr "type" "fsimpd,fsimpd")]) 3739 3740(define_insn "*adddf3_cconly" 3741 [(set (reg 33) 3742 (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 3743 (match_operand:DF 2 "general_operand" "f,R")) 3744 (match_operand:DF 3 "const0_operand" ""))) 3745 (clobber (match_scratch:DF 0 "=f,f"))] 3746 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3747 "@ 3748 adbr\t%0,%2 3749 adb\t%0,%2" 3750 [(set_attr "op_type" "RRE,RXE") 3751 (set_attr "type" "fsimpd,fsimpd")]) 3752 3753(define_insn "*adddf3_ibm" 3754 [(set (match_operand:DF 0 "register_operand" "=f,f") 3755 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 3756 (match_operand:DF 2 "general_operand" "f,R"))) 3757 (clobber (reg:CC 33))] 3758 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 3759 "@ 3760 adr\t%0,%2 3761 ad\t%0,%2" 3762 [(set_attr "op_type" "RR,RX") 3763 (set_attr "type" "fsimpd,fsimpd")]) 3764 3765; 3766; addsf3 instruction pattern(s). 3767; 3768 3769(define_expand "addsf3" 3770 [(parallel 3771 [(set (match_operand:SF 0 "register_operand" "=f,f") 3772 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 3773 (match_operand:SF 2 "general_operand" "f,R"))) 3774 (clobber (reg:CC 33))])] 3775 "TARGET_HARD_FLOAT" 3776 "") 3777 3778(define_insn "*addsf3" 3779 [(set (match_operand:SF 0 "register_operand" "=f,f") 3780 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 3781 (match_operand:SF 2 "general_operand" "f,R"))) 3782 (clobber (reg:CC 33))] 3783 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3784 "@ 3785 aebr\t%0,%2 3786 aeb\t%0,%2" 3787 [(set_attr "op_type" "RRE,RXE") 3788 (set_attr "type" "fsimps,fsimps")]) 3789 3790(define_insn "*addsf3_cc" 3791 [(set (reg 33) 3792 (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 3793 (match_operand:SF 2 "general_operand" "f,R")) 3794 (match_operand:SF 3 "const0_operand" ""))) 3795 (set (match_operand:SF 0 "register_operand" "=f,f") 3796 (plus:SF (match_dup 1) (match_dup 2)))] 3797 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3798 "@ 3799 aebr\t%0,%2 3800 aeb\t%0,%2" 3801 [(set_attr "op_type" "RRE,RXE") 3802 (set_attr "type" "fsimps,fsimps")]) 3803 3804(define_insn "*addsf3_cconly" 3805 [(set (reg 33) 3806 (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 3807 (match_operand:SF 2 "general_operand" "f,R")) 3808 (match_operand:SF 3 "const0_operand" ""))) 3809 (clobber (match_scratch:SF 0 "=f,f"))] 3810 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3811 "@ 3812 aebr\t%0,%2 3813 aeb\t%0,%2" 3814 [(set_attr "op_type" "RRE,RXE") 3815 (set_attr "type" "fsimps,fsimps")]) 3816 3817(define_insn "*addsf3" 3818 [(set (match_operand:SF 0 "register_operand" "=f,f") 3819 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 3820 (match_operand:SF 2 "general_operand" "f,R"))) 3821 (clobber (reg:CC 33))] 3822 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 3823 "@ 3824 aer\t%0,%2 3825 ae\t%0,%2" 3826 [(set_attr "op_type" "RR,RX") 3827 (set_attr "type" "fsimps,fsimps")]) 3828 3829 3830;; 3831;;- Subtract instructions. 3832;; 3833 3834; 3835; subdi3 instruction pattern(s). 3836; 3837 3838(define_insn "*subdi3_sign" 3839 [(set (match_operand:DI 0 "register_operand" "=d,d") 3840 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3841 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) 3842 (clobber (reg:CC 33))] 3843 "TARGET_64BIT" 3844 "@ 3845 sgfr\t%0,%2 3846 sgf\t%0,%2" 3847 [(set_attr "op_type" "RRE,RXY")]) 3848 3849(define_insn "*subdi3_zero_cc" 3850 [(set (reg 33) 3851 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3852 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) 3853 (const_int 0))) 3854 (set (match_operand:DI 0 "register_operand" "=d,d") 3855 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] 3856 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 3857 "@ 3858 slgfr\t%0,%2 3859 slgf\t%0,%2" 3860 [(set_attr "op_type" "RRE,RXY")]) 3861 3862(define_insn "*subdi3_zero_cconly" 3863 [(set (reg 33) 3864 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3865 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) 3866 (const_int 0))) 3867 (clobber (match_scratch:DI 0 "=d,d"))] 3868 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 3869 "@ 3870 slgfr\t%0,%2 3871 slgf\t%0,%2" 3872 [(set_attr "op_type" "RRE,RXY")]) 3873 3874(define_insn "*subdi3_zero" 3875 [(set (match_operand:DI 0 "register_operand" "=d,d") 3876 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3877 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) 3878 (clobber (reg:CC 33))] 3879 "TARGET_64BIT" 3880 "@ 3881 slgfr\t%0,%2 3882 slgf\t%0,%2" 3883 [(set_attr "op_type" "RRE,RXY")]) 3884 3885(define_insn "*subdi3_borrow_cc" 3886 [(set (reg 33) 3887 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3888 (match_operand:DI 2 "general_operand" "d,m")) 3889 (match_dup 1))) 3890 (set (match_operand:DI 0 "register_operand" "=d,d") 3891 (minus:DI (match_dup 1) (match_dup 2)))] 3892 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" 3893 "@ 3894 slgr\t%0,%2 3895 slg\t%0,%2" 3896 [(set_attr "op_type" "RRE,RXY")]) 3897 3898(define_insn "*subdi3_borrow_cconly" 3899 [(set (reg 33) 3900 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3901 (match_operand:DI 2 "general_operand" "d,m")) 3902 (match_dup 1))) 3903 (clobber (match_scratch:DI 0 "=d,d"))] 3904 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" 3905 "@ 3906 slgr\t%0,%2 3907 slg\t%0,%2" 3908 [(set_attr "op_type" "RRE,RXY")]) 3909 3910(define_insn "*subdi3_cc" 3911 [(set (reg 33) 3912 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3913 (match_operand:DI 2 "general_operand" "d,m")) 3914 (const_int 0))) 3915 (set (match_operand:DI 0 "register_operand" "=d,d") 3916 (minus:DI (match_dup 1) (match_dup 2)))] 3917 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 3918 "@ 3919 slgr\t%0,%2 3920 slg\t%0,%2" 3921 [(set_attr "op_type" "RRE,RXY")]) 3922 3923(define_insn "*subdi3_cconly" 3924 [(set (reg 33) 3925 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3926 (match_operand:DI 2 "general_operand" "d,m")) 3927 (const_int 0))) 3928 (clobber (match_scratch:DI 0 "=d,d"))] 3929 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 3930 "@ 3931 slgr\t%0,%2 3932 slg\t%0,%2" 3933 [(set_attr "op_type" "RRE,RXY")]) 3934 3935(define_insn "*subdi3_64" 3936 [(set (match_operand:DI 0 "register_operand" "=d,d") 3937 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3938 (match_operand:DI 2 "general_operand" "d,m") ) ) 3939 (clobber (reg:CC 33))] 3940 "TARGET_64BIT" 3941 "@ 3942 sgr\t%0,%2 3943 sg\t%0,%2" 3944 [(set_attr "op_type" "RRE,RRE")]) 3945 3946(define_insn_and_split "*subdi3_31z" 3947 [(set (match_operand:DI 0 "register_operand" "=&d") 3948 (minus:DI (match_operand:DI 1 "register_operand" "0") 3949 (match_operand:DI 2 "general_operand" "do") ) ) 3950 (clobber (reg:CC 33))] 3951 "!TARGET_64BIT && TARGET_CPU_ZARCH" 3952 "#" 3953 "&& reload_completed" 3954 [(parallel 3955 [(set (reg:CCL2 33) 3956 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) 3957 (match_dup 7))) 3958 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) 3959 (parallel 3960 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) 3961 (gtu:SI (reg:CCL2 33) (const_int 0)))) 3962 (clobber (reg:CC 33))])] 3963 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 3964 operands[4] = operand_subword (operands[1], 0, 0, DImode); 3965 operands[5] = operand_subword (operands[2], 0, 0, DImode); 3966 operands[6] = operand_subword (operands[0], 1, 0, DImode); 3967 operands[7] = operand_subword (operands[1], 1, 0, DImode); 3968 operands[8] = operand_subword (operands[2], 1, 0, DImode);" 3969 [(set_attr "op_type" "NN")]) 3970 3971(define_insn_and_split "*subdi3_31" 3972 [(set (match_operand:DI 0 "register_operand" "=&d") 3973 (minus:DI (match_operand:DI 1 "register_operand" "0") 3974 (match_operand:DI 2 "general_operand" "do") ) ) 3975 (clobber (reg:CC 33))] 3976 "!TARGET_CPU_ZARCH" 3977 "#" 3978 "&& reload_completed" 3979 [(parallel 3980 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) 3981 (clobber (reg:CC 33))]) 3982 (parallel 3983 [(set (reg:CCL2 33) 3984 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) 3985 (match_dup 7))) 3986 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) 3987 (set (pc) 3988 (if_then_else (gtu (reg:CCL2 33) (const_int 0)) 3989 (pc) 3990 (label_ref (match_dup 9)))) 3991 (parallel 3992 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) 3993 (clobber (reg:CC 33))]) 3994 (match_dup 9)] 3995 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 3996 operands[4] = operand_subword (operands[1], 0, 0, DImode); 3997 operands[5] = operand_subword (operands[2], 0, 0, DImode); 3998 operands[6] = operand_subword (operands[0], 1, 0, DImode); 3999 operands[7] = operand_subword (operands[1], 1, 0, DImode); 4000 operands[8] = operand_subword (operands[2], 1, 0, DImode); 4001 operands[9] = gen_label_rtx ();" 4002 [(set_attr "op_type" "NN")]) 4003 4004(define_expand "subdi3" 4005 [(parallel 4006 [(set (match_operand:DI 0 "register_operand" "") 4007 (minus:DI (match_operand:DI 1 "register_operand" "") 4008 (match_operand:DI 2 "general_operand" ""))) 4009 (clobber (reg:CC 33))])] 4010 "" 4011 "") 4012 4013; 4014; subsi3 instruction pattern(s). 4015; 4016 4017(define_insn "*subsi3_borrow_cc" 4018 [(set (reg 33) 4019 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") 4020 (match_operand:SI 2 "general_operand" "d,R,T")) 4021 (match_dup 1))) 4022 (set (match_operand:SI 0 "register_operand" "=d,d,d") 4023 (minus:SI (match_dup 1) (match_dup 2)))] 4024 "s390_match_ccmode (insn, CCL2mode)" 4025 "@ 4026 slr\t%0,%2 4027 sl\t%0,%2 4028 sly\t%0,%2" 4029 [(set_attr "op_type" "RR,RX,RXY")]) 4030 4031(define_insn "*subsi3_borrow_cconly" 4032 [(set (reg 33) 4033 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") 4034 (match_operand:SI 2 "general_operand" "d,R,T")) 4035 (match_dup 1))) 4036 (clobber (match_scratch:SI 0 "=d,d,d"))] 4037 "s390_match_ccmode (insn, CCL2mode)" 4038 "@ 4039 slr\t%0,%2 4040 sl\t%0,%2 4041 sly\t%0,%2" 4042 [(set_attr "op_type" "RR,RX,RXY")]) 4043 4044(define_insn "*subsi3_cc" 4045 [(set (reg 33) 4046 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") 4047 (match_operand:SI 2 "general_operand" "d,R,T")) 4048 (const_int 0))) 4049 (set (match_operand:SI 0 "register_operand" "=d,d,d") 4050 (minus:SI (match_dup 1) (match_dup 2)))] 4051 "s390_match_ccmode (insn, CCLmode)" 4052 "@ 4053 slr\t%0,%2 4054 sl\t%0,%2 4055 sly\t%0,%2" 4056 [(set_attr "op_type" "RR,RX,RXY")]) 4057 4058(define_insn "*subsi3_cconly" 4059 [(set (reg 33) 4060 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") 4061 (match_operand:SI 2 "general_operand" "d,R,T")) 4062 (const_int 0))) 4063 (clobber (match_scratch:SI 0 "=d,d,d"))] 4064 "s390_match_ccmode (insn, CCLmode)" 4065 "@ 4066 slr\t%0,%2 4067 sl\t%0,%2 4068 sly\t%0,%2" 4069 [(set_attr "op_type" "RR,RX,RXY")]) 4070 4071(define_insn "*subsi3_sign" 4072 [(set (match_operand:SI 0 "register_operand" "=d,d") 4073 (minus:SI (match_operand:SI 1 "register_operand" "0,0") 4074 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) 4075 (clobber (reg:CC 33))] 4076 "" 4077 "@ 4078 sh\t%0,%2 4079 shy\t%0,%2" 4080 [(set_attr "op_type" "RX,RXY")]) 4081 4082(define_insn "subsi3" 4083 [(set (match_operand:SI 0 "register_operand" "=d,d,d") 4084 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") 4085 (match_operand:SI 2 "general_operand" "d,R,T"))) 4086 (clobber (reg:CC 33))] 4087 "" 4088 "@ 4089 sr\t%0,%2 4090 s\t%0,%2 4091 sy\t%0,%2" 4092 [(set_attr "op_type" "RR,RX,RXY")]) 4093 4094 4095; 4096; subdf3 instruction pattern(s). 4097; 4098 4099(define_expand "subdf3" 4100 [(parallel 4101 [(set (match_operand:DF 0 "register_operand" "=f,f") 4102 (minus:DF (match_operand:DF 1 "register_operand" "0,0") 4103 (match_operand:DF 2 "general_operand" "f,R"))) 4104 (clobber (reg:CC 33))])] 4105 "TARGET_HARD_FLOAT" 4106 "") 4107 4108(define_insn "*subdf3" 4109 [(set (match_operand:DF 0 "register_operand" "=f,f") 4110 (minus:DF (match_operand:DF 1 "register_operand" "0,0") 4111 (match_operand:DF 2 "general_operand" "f,R"))) 4112 (clobber (reg:CC 33))] 4113 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 4114 "@ 4115 sdbr\t%0,%2 4116 sdb\t%0,%2" 4117 [(set_attr "op_type" "RRE,RXE") 4118 (set_attr "type" "fsimpd,fsimpd")]) 4119 4120(define_insn "*subdf3_cc" 4121 [(set (reg 33) 4122 (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") 4123 (match_operand:DF 2 "general_operand" "f,R")) 4124 (match_operand:DF 3 "const0_operand" ""))) 4125 (set (match_operand:DF 0 "register_operand" "=f,f") 4126 (minus:DF (match_dup 1) (match_dup 2)))] 4127 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 4128 "@ 4129 sdbr\t%0,%2 4130 sdb\t%0,%2" 4131 [(set_attr "op_type" "RRE,RXE") 4132 (set_attr "type" "fsimpd,fsimpd")]) 4133 4134(define_insn "*subdf3_cconly" 4135 [(set (reg 33) 4136 (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") 4137 (match_operand:DF 2 "general_operand" "f,R")) 4138 (match_operand:DF 3 "const0_operand" ""))) 4139 (clobber (match_scratch:DF 0 "=f,f"))] 4140 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 4141 "@ 4142 sdbr\t%0,%2 4143 sdb\t%0,%2" 4144 [(set_attr "op_type" "RRE,RXE") 4145 (set_attr "type" "fsimpd,fsimpd")]) 4146 4147(define_insn "*subdf3_ibm" 4148 [(set (match_operand:DF 0 "register_operand" "=f,f") 4149 (minus:DF (match_operand:DF 1 "register_operand" "0,0") 4150 (match_operand:DF 2 "general_operand" "f,R"))) 4151 (clobber (reg:CC 33))] 4152 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 4153 "@ 4154 sdr\t%0,%2 4155 sd\t%0,%2" 4156 [(set_attr "op_type" "RR,RX") 4157 (set_attr "type" "fsimpd,fsimpd")]) 4158 4159; 4160; subsf3 instruction pattern(s). 4161; 4162 4163(define_expand "subsf3" 4164 [(parallel 4165 [(set (match_operand:SF 0 "register_operand" "=f,f") 4166 (minus:SF (match_operand:SF 1 "register_operand" "0,0") 4167 (match_operand:SF 2 "general_operand" "f,R"))) 4168 (clobber (reg:CC 33))])] 4169 "TARGET_HARD_FLOAT" 4170 "") 4171 4172(define_insn "*subsf3" 4173 [(set (match_operand:SF 0 "register_operand" "=f,f") 4174 (minus:SF (match_operand:SF 1 "register_operand" "0,0") 4175 (match_operand:SF 2 "general_operand" "f,R"))) 4176 (clobber (reg:CC 33))] 4177 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 4178 "@ 4179 sebr\t%0,%2 4180 seb\t%0,%2" 4181 [(set_attr "op_type" "RRE,RXE") 4182 (set_attr "type" "fsimps,fsimps")]) 4183 4184(define_insn "*subsf3_cc" 4185 [(set (reg 33) 4186 (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") 4187 (match_operand:SF 2 "general_operand" "f,R")) 4188 (match_operand:SF 3 "const0_operand" ""))) 4189 (set (match_operand:SF 0 "register_operand" "=f,f") 4190 (minus:SF (match_dup 1) (match_dup 2)))] 4191 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 4192 "@ 4193 sebr\t%0,%2 4194 seb\t%0,%2" 4195 [(set_attr "op_type" "RRE,RXE") 4196 (set_attr "type" "fsimps,fsimps")]) 4197 4198(define_insn "*subsf3_cconly" 4199 [(set (reg 33) 4200 (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") 4201 (match_operand:SF 2 "general_operand" "f,R")) 4202 (match_operand:SF 3 "const0_operand" ""))) 4203 (clobber (match_scratch:SF 0 "=f,f"))] 4204 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 4205 "@ 4206 sebr\t%0,%2 4207 seb\t%0,%2" 4208 [(set_attr "op_type" "RRE,RXE") 4209 (set_attr "type" "fsimps,fsimps")]) 4210 4211(define_insn "*subsf3_ibm" 4212 [(set (match_operand:SF 0 "register_operand" "=f,f") 4213 (minus:SF (match_operand:SF 1 "register_operand" "0,0") 4214 (match_operand:SF 2 "general_operand" "f,R"))) 4215 (clobber (reg:CC 33))] 4216 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 4217 "@ 4218 ser\t%0,%2 4219 se\t%0,%2" 4220 [(set_attr "op_type" "RR,RX") 4221 (set_attr "type" "fsimps,fsimps")]) 4222 4223 4224;; 4225;;- Conditional add/subtract instructions. 4226;; 4227 4228; 4229; adddicc instruction pattern(s). 4230; 4231 4232(define_insn "*adddi3_alc_cc" 4233 [(set (reg 33) 4234 (compare 4235 (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 4236 (match_operand:DI 2 "general_operand" "d,m")) 4237 (match_operand:DI 3 "s390_alc_comparison" "")) 4238 (const_int 0))) 4239 (set (match_operand:DI 0 "register_operand" "=d,d") 4240 (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4241 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 4242 "@ 4243 alcgr\\t%0,%2 4244 alcg\\t%0,%2" 4245 [(set_attr "op_type" "RRE,RXY")]) 4246 4247(define_insn "*adddi3_alc" 4248 [(set (match_operand:DI 0 "register_operand" "=d,d") 4249 (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 4250 (match_operand:DI 2 "general_operand" "d,m")) 4251 (match_operand:DI 3 "s390_alc_comparison" ""))) 4252 (clobber (reg:CC 33))] 4253 "TARGET_64BIT" 4254 "@ 4255 alcgr\\t%0,%2 4256 alcg\\t%0,%2" 4257 [(set_attr "op_type" "RRE,RXY")]) 4258 4259(define_insn "*subdi3_slb_cc" 4260 [(set (reg 33) 4261 (compare 4262 (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") 4263 (match_operand:DI 2 "general_operand" "d,m")) 4264 (match_operand:DI 3 "s390_slb_comparison" "")) 4265 (const_int 0))) 4266 (set (match_operand:DI 0 "register_operand" "=d,d") 4267 (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4268 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 4269 "@ 4270 slbgr\\t%0,%2 4271 slbg\\t%0,%2" 4272 [(set_attr "op_type" "RRE,RXY")]) 4273 4274(define_insn "*subdi3_slb" 4275 [(set (match_operand:DI 0 "register_operand" "=d,d") 4276 (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") 4277 (match_operand:DI 2 "general_operand" "d,m")) 4278 (match_operand:DI 3 "s390_slb_comparison" ""))) 4279 (clobber (reg:CC 33))] 4280 "TARGET_64BIT" 4281 "@ 4282 slbgr\\t%0,%2 4283 slbg\\t%0,%2" 4284 [(set_attr "op_type" "RRE,RXY")]) 4285 4286; 4287; addsicc instruction pattern(s). 4288; 4289 4290(define_insn "*addsi3_alc_cc" 4291 [(set (reg 33) 4292 (compare 4293 (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 4294 (match_operand:SI 2 "general_operand" "d,m")) 4295 (match_operand:SI 3 "s390_alc_comparison" "")) 4296 (const_int 0))) 4297 (set (match_operand:SI 0 "register_operand" "=d,d") 4298 (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4299 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" 4300 "@ 4301 alcr\\t%0,%2 4302 alc\\t%0,%2" 4303 [(set_attr "op_type" "RRE,RXY")]) 4304 4305(define_insn "*addsi3_alc" 4306 [(set (match_operand:SI 0 "register_operand" "=d,d") 4307 (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 4308 (match_operand:SI 2 "general_operand" "d,m")) 4309 (match_operand:SI 3 "s390_alc_comparison" ""))) 4310 (clobber (reg:CC 33))] 4311 "TARGET_CPU_ZARCH" 4312 "@ 4313 alcr\\t%0,%2 4314 alc\\t%0,%2" 4315 [(set_attr "op_type" "RRE,RXY")]) 4316 4317(define_insn "*subsi3_slb_cc" 4318 [(set (reg 33) 4319 (compare 4320 (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") 4321 (match_operand:SI 2 "general_operand" "d,m")) 4322 (match_operand:SI 3 "s390_slb_comparison" "")) 4323 (const_int 0))) 4324 (set (match_operand:SI 0 "register_operand" "=d,d") 4325 (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4326 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" 4327 "@ 4328 slbr\\t%0,%2 4329 slb\\t%0,%2" 4330 [(set_attr "op_type" "RRE,RXY")]) 4331 4332(define_insn "*subsi3_slb" 4333 [(set (match_operand:SI 0 "register_operand" "=d,d") 4334 (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") 4335 (match_operand:SI 2 "general_operand" "d,m")) 4336 (match_operand:SI 3 "s390_slb_comparison" ""))) 4337 (clobber (reg:CC 33))] 4338 "TARGET_CPU_ZARCH" 4339 "@ 4340 slbr\\t%0,%2 4341 slb\\t%0,%2" 4342 [(set_attr "op_type" "RRE,RXY")]) 4343 4344 4345;; 4346;;- Multiply instructions. 4347;; 4348 4349; 4350; muldi3 instruction pattern(s). 4351; 4352 4353(define_insn "*muldi3_sign" 4354 [(set (match_operand:DI 0 "register_operand" "=d,d") 4355 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) 4356 (match_operand:DI 1 "register_operand" "0,0")))] 4357 "TARGET_64BIT" 4358 "@ 4359 msgfr\t%0,%2 4360 msgf\t%0,%2" 4361 [(set_attr "op_type" "RRE,RXY") 4362 (set_attr "type" "imul")]) 4363 4364(define_insn "muldi3" 4365 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 4366 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") 4367 (match_operand:DI 2 "general_operand" "d,K,m")))] 4368 "TARGET_64BIT" 4369 "@ 4370 msgr\t%0,%2 4371 mghi\t%0,%h2 4372 msg\t%0,%2" 4373 [(set_attr "op_type" "RRE,RI,RXY") 4374 (set_attr "type" "imul")]) 4375 4376; 4377; mulsi3 instruction pattern(s). 4378; 4379 4380(define_insn "*mulsi3_sign" 4381 [(set (match_operand:SI 0 "register_operand" "=d") 4382 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) 4383 (match_operand:SI 1 "register_operand" "0")))] 4384 "" 4385 "mh\t%0,%2" 4386 [(set_attr "op_type" "RX") 4387 (set_attr "type" "imul")]) 4388 4389(define_insn "mulsi3" 4390 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") 4391 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") 4392 (match_operand:SI 2 "general_operand" "d,K,R,T")))] 4393 "" 4394 "@ 4395 msr\t%0,%2 4396 mhi\t%0,%h2 4397 ms\t%0,%2 4398 msy\t%0,%2" 4399 [(set_attr "op_type" "RRE,RI,RX,RXY") 4400 (set_attr "type" "imul")]) 4401 4402; 4403; mulsidi3 instruction pattern(s). 4404; 4405 4406(define_insn "mulsidi3" 4407 [(set (match_operand:DI 0 "register_operand" "=d,d") 4408 (mult:DI (sign_extend:DI 4409 (match_operand:SI 1 "register_operand" "%0,0")) 4410 (sign_extend:DI 4411 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] 4412 "!TARGET_64BIT" 4413 "@ 4414 mr\t%0,%2 4415 m\t%0,%2" 4416 [(set_attr "op_type" "RR,RX") 4417 (set_attr "type" "imul")]) 4418 4419; 4420; umulsidi3 instruction pattern(s). 4421; 4422 4423(define_insn "umulsidi3" 4424 [(set (match_operand:DI 0 "register_operand" "=d,d") 4425 (mult:DI (zero_extend:DI 4426 (match_operand:SI 1 "register_operand" "%0,0")) 4427 (zero_extend:DI 4428 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] 4429 "!TARGET_64BIT && TARGET_CPU_ZARCH" 4430 "@ 4431 mlr\t%0,%2 4432 ml\t%0,%2" 4433 [(set_attr "op_type" "RRE,RXY") 4434 (set_attr "type" "imul")]) 4435 4436; 4437; muldf3 instruction pattern(s). 4438; 4439 4440(define_expand "muldf3" 4441 [(set (match_operand:DF 0 "register_operand" "=f,f") 4442 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 4443 (match_operand:DF 2 "general_operand" "f,R")))] 4444 "TARGET_HARD_FLOAT" 4445 "") 4446 4447(define_insn "*muldf3" 4448 [(set (match_operand:DF 0 "register_operand" "=f,f") 4449 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 4450 (match_operand:DF 2 "general_operand" "f,R")))] 4451 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 4452 "@ 4453 mdbr\t%0,%2 4454 mdb\t%0,%2" 4455 [(set_attr "op_type" "RRE,RXE") 4456 (set_attr "type" "fmuld")]) 4457 4458(define_insn "*muldf3_ibm" 4459 [(set (match_operand:DF 0 "register_operand" "=f,f") 4460 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 4461 (match_operand:DF 2 "general_operand" "f,R")))] 4462 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 4463 "@ 4464 mdr\t%0,%2 4465 md\t%0,%2" 4466 [(set_attr "op_type" "RR,RX") 4467 (set_attr "type" "fmuld")]) 4468 4469(define_insn "*fmadddf" 4470 [(set (match_operand:DF 0 "register_operand" "=f,f") 4471 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f") 4472 (match_operand:DF 2 "nonimmediate_operand" "f,R")) 4473 (match_operand:DF 3 "register_operand" "0,0")))] 4474 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" 4475 "@ 4476 madbr\t%0,%1,%2 4477 madb\t%0,%1,%2" 4478 [(set_attr "op_type" "RRE,RXE") 4479 (set_attr "type" "fmuld")]) 4480 4481(define_insn "*fmsubdf" 4482 [(set (match_operand:DF 0 "register_operand" "=f,f") 4483 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f") 4484 (match_operand:DF 2 "nonimmediate_operand" "f,R")) 4485 (match_operand:DF 3 "register_operand" "0,0")))] 4486 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" 4487 "@ 4488 msdbr\t%0,%1,%2 4489 msdb\t%0,%1,%2" 4490 [(set_attr "op_type" "RRE,RXE") 4491 (set_attr "type" "fmuld")]) 4492 4493; 4494; mulsf3 instruction pattern(s). 4495; 4496 4497(define_expand "mulsf3" 4498 [(set (match_operand:SF 0 "register_operand" "=f,f") 4499 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 4500 (match_operand:SF 2 "general_operand" "f,R")))] 4501 "TARGET_HARD_FLOAT" 4502 "") 4503 4504(define_insn "*mulsf3" 4505 [(set (match_operand:SF 0 "register_operand" "=f,f") 4506 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 4507 (match_operand:SF 2 "general_operand" "f,R")))] 4508 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 4509 "@ 4510 meebr\t%0,%2 4511 meeb\t%0,%2" 4512 [(set_attr "op_type" "RRE,RXE") 4513 (set_attr "type" "fmuls")]) 4514 4515(define_insn "*mulsf3_ibm" 4516 [(set (match_operand:SF 0 "register_operand" "=f,f") 4517 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 4518 (match_operand:SF 2 "general_operand" "f,R")))] 4519 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 4520 "@ 4521 mer\t%0,%2 4522 me\t%0,%2" 4523 [(set_attr "op_type" "RR,RX") 4524 (set_attr "type" "fmuls")]) 4525 4526(define_insn "*fmaddsf" 4527 [(set (match_operand:SF 0 "register_operand" "=f,f") 4528 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f") 4529 (match_operand:SF 2 "nonimmediate_operand" "f,R")) 4530 (match_operand:SF 3 "register_operand" "0,0")))] 4531 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" 4532 "@ 4533 maebr\t%0,%1,%2 4534 maeb\t%0,%1,%2" 4535 [(set_attr "op_type" "RRE,RXE") 4536 (set_attr "type" "fmuls")]) 4537 4538(define_insn "*fmsubsf" 4539 [(set (match_operand:SF 0 "register_operand" "=f,f") 4540 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f") 4541 (match_operand:SF 2 "nonimmediate_operand" "f,R")) 4542 (match_operand:SF 3 "register_operand" "0,0")))] 4543 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" 4544 "@ 4545 msebr\t%0,%1,%2 4546 mseb\t%0,%1,%2" 4547 [(set_attr "op_type" "RRE,RXE") 4548 (set_attr "type" "fmuls")]) 4549 4550;; 4551;;- Divide and modulo instructions. 4552;; 4553 4554; 4555; divmoddi4 instruction pattern(s). 4556; 4557 4558(define_expand "divmoddi4" 4559 [(parallel [(set (match_operand:DI 0 "general_operand" "") 4560 (div:DI (match_operand:DI 1 "register_operand" "") 4561 (match_operand:DI 2 "general_operand" ""))) 4562 (set (match_operand:DI 3 "general_operand" "") 4563 (mod:DI (match_dup 1) (match_dup 2)))]) 4564 (clobber (match_dup 4))] 4565 "TARGET_64BIT" 4566{ 4567 rtx insn, div_equal, mod_equal; 4568 4569 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); 4570 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); 4571 4572 operands[4] = gen_reg_rtx(TImode); 4573 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); 4574 4575 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); 4576 REG_NOTES (insn) = 4577 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); 4578 4579 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); 4580 REG_NOTES (insn) = 4581 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); 4582 4583 DONE; 4584}) 4585 4586(define_insn "divmodtidi3" 4587 [(set (match_operand:TI 0 "register_operand" "=d,d") 4588 (ior:TI 4589 (zero_extend:TI 4590 (div:DI (match_operand:DI 1 "register_operand" "0,0") 4591 (match_operand:DI 2 "general_operand" "d,m"))) 4592 (ashift:TI 4593 (zero_extend:TI 4594 (mod:DI (match_dup 1) 4595 (match_dup 2))) 4596 (const_int 64))))] 4597 "TARGET_64BIT" 4598 "@ 4599 dsgr\t%0,%2 4600 dsg\t%0,%2" 4601 [(set_attr "op_type" "RRE,RXY") 4602 (set_attr "type" "idiv")]) 4603 4604(define_insn "divmodtisi3" 4605 [(set (match_operand:TI 0 "register_operand" "=d,d") 4606 (ior:TI 4607 (zero_extend:TI 4608 (div:DI (match_operand:DI 1 "register_operand" "0,0") 4609 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")))) 4610 (ashift:TI 4611 (zero_extend:TI 4612 (mod:DI (match_dup 1) 4613 (sign_extend:DI (match_dup 2)))) 4614 (const_int 64))))] 4615 "TARGET_64BIT" 4616 "@ 4617 dsgfr\t%0,%2 4618 dsgf\t%0,%2" 4619 [(set_attr "op_type" "RRE,RXY") 4620 (set_attr "type" "idiv")]) 4621 4622; 4623; udivmoddi4 instruction pattern(s). 4624; 4625 4626(define_expand "udivmoddi4" 4627 [(parallel [(set (match_operand:DI 0 "general_operand" "") 4628 (udiv:DI (match_operand:DI 1 "general_operand" "") 4629 (match_operand:DI 2 "nonimmediate_operand" ""))) 4630 (set (match_operand:DI 3 "general_operand" "") 4631 (umod:DI (match_dup 1) (match_dup 2)))]) 4632 (clobber (match_dup 4))] 4633 "TARGET_64BIT" 4634{ 4635 rtx insn, div_equal, mod_equal, equal; 4636 4637 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); 4638 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); 4639 equal = gen_rtx_IOR (TImode, 4640 gen_rtx_ZERO_EXTEND (TImode, div_equal), 4641 gen_rtx_ASHIFT (TImode, 4642 gen_rtx_ZERO_EXTEND (TImode, mod_equal), 4643 GEN_INT (64))); 4644 4645 operands[4] = gen_reg_rtx(TImode); 4646 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); 4647 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); 4648 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); 4649 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); 4650 REG_NOTES (insn) = 4651 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4652 4653 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); 4654 REG_NOTES (insn) = 4655 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); 4656 4657 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); 4658 REG_NOTES (insn) = 4659 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); 4660 4661 DONE; 4662}) 4663 4664(define_insn "udivmodtidi3" 4665 [(set (match_operand:TI 0 "register_operand" "=d,d") 4666 (ior:TI (zero_extend:TI 4667 (truncate:DI 4668 (udiv:TI (match_operand:TI 1 "register_operand" "0,0") 4669 (zero_extend:TI 4670 (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) 4671 (ashift:TI 4672 (zero_extend:TI 4673 (truncate:DI 4674 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2))))) 4675 (const_int 64))))] 4676 "TARGET_64BIT" 4677 "@ 4678 dlgr\t%0,%2 4679 dlg\t%0,%2" 4680 [(set_attr "op_type" "RRE,RXY") 4681 (set_attr "type" "idiv")]) 4682 4683; 4684; divmodsi4 instruction pattern(s). 4685; 4686 4687(define_expand "divmodsi4" 4688 [(parallel [(set (match_operand:SI 0 "general_operand" "") 4689 (div:SI (match_operand:SI 1 "general_operand" "") 4690 (match_operand:SI 2 "nonimmediate_operand" ""))) 4691 (set (match_operand:SI 3 "general_operand" "") 4692 (mod:SI (match_dup 1) (match_dup 2)))]) 4693 (clobber (match_dup 4))] 4694 "!TARGET_64BIT" 4695{ 4696 rtx insn, div_equal, mod_equal, equal; 4697 4698 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); 4699 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); 4700 equal = gen_rtx_IOR (DImode, 4701 gen_rtx_ZERO_EXTEND (DImode, div_equal), 4702 gen_rtx_ASHIFT (DImode, 4703 gen_rtx_ZERO_EXTEND (DImode, mod_equal), 4704 GEN_INT (32))); 4705 4706 operands[4] = gen_reg_rtx(DImode); 4707 emit_insn (gen_extendsidi2 (operands[4], operands[1])); 4708 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); 4709 REG_NOTES (insn) = 4710 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4711 4712 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); 4713 REG_NOTES (insn) = 4714 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); 4715 4716 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); 4717 REG_NOTES (insn) = 4718 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); 4719 4720 DONE; 4721}) 4722 4723(define_insn "divmoddisi3" 4724 [(set (match_operand:DI 0 "register_operand" "=d,d") 4725 (ior:DI (zero_extend:DI 4726 (truncate:SI 4727 (div:DI (match_operand:DI 1 "register_operand" "0,0") 4728 (sign_extend:DI 4729 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) 4730 (ashift:DI 4731 (zero_extend:DI 4732 (truncate:SI 4733 (mod:DI (match_dup 1) (sign_extend:DI (match_dup 2))))) 4734 (const_int 32))))] 4735 "!TARGET_64BIT" 4736 "@ 4737 dr\t%0,%2 4738 d\t%0,%2" 4739 [(set_attr "op_type" "RR,RX") 4740 (set_attr "type" "idiv")]) 4741 4742; 4743; udivsi3 and umodsi3 instruction pattern(s). 4744; 4745 4746(define_expand "udivmodsi4" 4747 [(parallel [(set (match_operand:SI 0 "general_operand" "") 4748 (udiv:SI (match_operand:SI 1 "general_operand" "") 4749 (match_operand:SI 2 "nonimmediate_operand" ""))) 4750 (set (match_operand:SI 3 "general_operand" "") 4751 (umod:SI (match_dup 1) (match_dup 2)))]) 4752 (clobber (match_dup 4))] 4753 "!TARGET_64BIT && TARGET_CPU_ZARCH" 4754{ 4755 rtx insn, div_equal, mod_equal, equal; 4756 4757 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 4758 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 4759 equal = gen_rtx_IOR (DImode, 4760 gen_rtx_ZERO_EXTEND (DImode, div_equal), 4761 gen_rtx_ASHIFT (DImode, 4762 gen_rtx_ZERO_EXTEND (DImode, mod_equal), 4763 GEN_INT (32))); 4764 4765 operands[4] = gen_reg_rtx(DImode); 4766 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); 4767 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); 4768 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); 4769 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); 4770 REG_NOTES (insn) = 4771 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4772 4773 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); 4774 REG_NOTES (insn) = 4775 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); 4776 4777 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); 4778 REG_NOTES (insn) = 4779 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); 4780 4781 DONE; 4782}) 4783 4784(define_insn "udivmoddisi3" 4785 [(set (match_operand:DI 0 "register_operand" "=d,d") 4786 (ior:DI (zero_extend:DI 4787 (truncate:SI 4788 (udiv:DI (match_operand:DI 1 "register_operand" "0,0") 4789 (zero_extend:DI 4790 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) 4791 (ashift:DI 4792 (zero_extend:DI 4793 (truncate:SI 4794 (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2))))) 4795 (const_int 32))))] 4796 "!TARGET_64BIT && TARGET_CPU_ZARCH" 4797 "@ 4798 dlr\t%0,%2 4799 dl\t%0,%2" 4800 [(set_attr "op_type" "RRE,RXY") 4801 (set_attr "type" "idiv")]) 4802 4803(define_expand "udivsi3" 4804 [(set (match_operand:SI 0 "register_operand" "=d") 4805 (udiv:SI (match_operand:SI 1 "general_operand" "") 4806 (match_operand:SI 2 "general_operand" ""))) 4807 (clobber (match_dup 3))] 4808 "!TARGET_64BIT && !TARGET_CPU_ZARCH" 4809{ 4810 rtx insn, udiv_equal, umod_equal, equal; 4811 4812 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 4813 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 4814 equal = gen_rtx_IOR (DImode, 4815 gen_rtx_ZERO_EXTEND (DImode, udiv_equal), 4816 gen_rtx_ASHIFT (DImode, 4817 gen_rtx_ZERO_EXTEND (DImode, umod_equal), 4818 GEN_INT (32))); 4819 4820 operands[3] = gen_reg_rtx (DImode); 4821 4822 if (CONSTANT_P (operands[2])) 4823 { 4824 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 4825 { 4826 rtx label1 = gen_label_rtx (); 4827 4828 operands[1] = make_safe_from (operands[1], operands[0]); 4829 emit_move_insn (operands[0], const0_rtx); 4830 emit_insn (gen_cmpsi (operands[1], operands[2])); 4831 emit_jump_insn (gen_bltu (label1)); 4832 emit_move_insn (operands[0], const1_rtx); 4833 emit_label (label1); 4834 } 4835 else 4836 { 4837 operands[2] = force_reg (SImode, operands[2]); 4838 operands[2] = make_safe_from (operands[2], operands[0]); 4839 4840 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 4841 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 4842 operands[2])); 4843 REG_NOTES (insn) = 4844 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4845 4846 insn = emit_move_insn (operands[0], 4847 gen_lowpart (SImode, operands[3])); 4848 REG_NOTES (insn) = 4849 gen_rtx_EXPR_LIST (REG_EQUAL, 4850 udiv_equal, REG_NOTES (insn)); 4851 } 4852 } 4853 else 4854 { 4855 rtx label1 = gen_label_rtx (); 4856 rtx label2 = gen_label_rtx (); 4857 rtx label3 = gen_label_rtx (); 4858 4859 operands[1] = force_reg (SImode, operands[1]); 4860 operands[1] = make_safe_from (operands[1], operands[0]); 4861 operands[2] = force_reg (SImode, operands[2]); 4862 operands[2] = make_safe_from (operands[2], operands[0]); 4863 4864 emit_move_insn (operands[0], const0_rtx); 4865 emit_insn (gen_cmpsi (operands[2], operands[1])); 4866 emit_jump_insn (gen_bgtu (label3)); 4867 emit_insn (gen_cmpsi (operands[2], const1_rtx)); 4868 emit_jump_insn (gen_blt (label2)); 4869 emit_insn (gen_cmpsi (operands[2], const1_rtx)); 4870 emit_jump_insn (gen_beq (label1)); 4871 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 4872 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 4873 operands[2])); 4874 REG_NOTES (insn) = 4875 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4876 4877 insn = emit_move_insn (operands[0], 4878 gen_lowpart (SImode, operands[3])); 4879 REG_NOTES (insn) = 4880 gen_rtx_EXPR_LIST (REG_EQUAL, 4881 udiv_equal, REG_NOTES (insn)); 4882 emit_jump (label3); 4883 emit_label (label1); 4884 emit_move_insn (operands[0], operands[1]); 4885 emit_jump (label3); 4886 emit_label (label2); 4887 emit_move_insn (operands[0], const1_rtx); 4888 emit_label (label3); 4889 } 4890 emit_move_insn (operands[0], operands[0]); 4891 DONE; 4892}) 4893 4894(define_expand "umodsi3" 4895 [(set (match_operand:SI 0 "register_operand" "=d") 4896 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") 4897 (match_operand:SI 2 "nonimmediate_operand" ""))) 4898 (clobber (match_dup 3))] 4899 "!TARGET_64BIT && !TARGET_CPU_ZARCH" 4900{ 4901 rtx insn, udiv_equal, umod_equal, equal; 4902 4903 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 4904 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 4905 equal = gen_rtx_IOR (DImode, 4906 gen_rtx_ZERO_EXTEND (DImode, udiv_equal), 4907 gen_rtx_ASHIFT (DImode, 4908 gen_rtx_ZERO_EXTEND (DImode, umod_equal), 4909 GEN_INT (32))); 4910 4911 operands[3] = gen_reg_rtx (DImode); 4912 4913 if (CONSTANT_P (operands[2])) 4914 { 4915 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) 4916 { 4917 rtx label1 = gen_label_rtx (); 4918 4919 operands[1] = make_safe_from (operands[1], operands[0]); 4920 emit_move_insn (operands[0], operands[1]); 4921 emit_insn (gen_cmpsi (operands[0], operands[2])); 4922 emit_jump_insn (gen_bltu (label1)); 4923 emit_insn (gen_abssi2 (operands[0], operands[2])); 4924 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); 4925 emit_label (label1); 4926 } 4927 else 4928 { 4929 operands[2] = force_reg (SImode, operands[2]); 4930 operands[2] = make_safe_from (operands[2], operands[0]); 4931 4932 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 4933 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 4934 operands[2])); 4935 REG_NOTES (insn) = 4936 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4937 4938 insn = emit_move_insn (operands[0], 4939 gen_highpart (SImode, operands[3])); 4940 REG_NOTES (insn) = 4941 gen_rtx_EXPR_LIST (REG_EQUAL, 4942 umod_equal, REG_NOTES (insn)); 4943 } 4944 } 4945 else 4946 { 4947 rtx label1 = gen_label_rtx (); 4948 rtx label2 = gen_label_rtx (); 4949 rtx label3 = gen_label_rtx (); 4950 4951 operands[1] = force_reg (SImode, operands[1]); 4952 operands[1] = make_safe_from (operands[1], operands[0]); 4953 operands[2] = force_reg (SImode, operands[2]); 4954 operands[2] = make_safe_from (operands[2], operands[0]); 4955 4956 emit_move_insn(operands[0], operands[1]); 4957 emit_insn (gen_cmpsi (operands[2], operands[1])); 4958 emit_jump_insn (gen_bgtu (label3)); 4959 emit_insn (gen_cmpsi (operands[2], const1_rtx)); 4960 emit_jump_insn (gen_blt (label2)); 4961 emit_insn (gen_cmpsi (operands[2], const1_rtx)); 4962 emit_jump_insn (gen_beq (label1)); 4963 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 4964 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 4965 operands[2])); 4966 REG_NOTES (insn) = 4967 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4968 4969 insn = emit_move_insn (operands[0], 4970 gen_highpart (SImode, operands[3])); 4971 REG_NOTES (insn) = 4972 gen_rtx_EXPR_LIST (REG_EQUAL, 4973 umod_equal, REG_NOTES (insn)); 4974 emit_jump (label3); 4975 emit_label (label1); 4976 emit_move_insn (operands[0], const0_rtx); 4977 emit_jump (label3); 4978 emit_label (label2); 4979 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); 4980 emit_label (label3); 4981 } 4982 DONE; 4983}) 4984 4985; 4986; divdf3 instruction pattern(s). 4987; 4988 4989(define_expand "divdf3" 4990 [(set (match_operand:DF 0 "register_operand" "=f,f") 4991 (div:DF (match_operand:DF 1 "register_operand" "0,0") 4992 (match_operand:DF 2 "general_operand" "f,R")))] 4993 "TARGET_HARD_FLOAT" 4994 "") 4995 4996(define_insn "*divdf3" 4997 [(set (match_operand:DF 0 "register_operand" "=f,f") 4998 (div:DF (match_operand:DF 1 "register_operand" "0,0") 4999 (match_operand:DF 2 "general_operand" "f,R")))] 5000 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5001 "@ 5002 ddbr\t%0,%2 5003 ddb\t%0,%2" 5004 [(set_attr "op_type" "RRE,RXE") 5005 (set_attr "type" "fdivd")]) 5006 5007(define_insn "*divdf3_ibm" 5008 [(set (match_operand:DF 0 "register_operand" "=f,f") 5009 (div:DF (match_operand:DF 1 "register_operand" "0,0") 5010 (match_operand:DF 2 "general_operand" "f,R")))] 5011 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 5012 "@ 5013 ddr\t%0,%2 5014 dd\t%0,%2" 5015 [(set_attr "op_type" "RR,RX") 5016 (set_attr "type" "fdivd")]) 5017 5018; 5019; divsf3 instruction pattern(s). 5020; 5021 5022(define_expand "divsf3" 5023 [(set (match_operand:SF 0 "register_operand" "=f,f") 5024 (div:SF (match_operand:SF 1 "register_operand" "0,0") 5025 (match_operand:SF 2 "general_operand" "f,R")))] 5026 "TARGET_HARD_FLOAT" 5027 "") 5028 5029(define_insn "*divsf3" 5030 [(set (match_operand:SF 0 "register_operand" "=f,f") 5031 (div:SF (match_operand:SF 1 "register_operand" "0,0") 5032 (match_operand:SF 2 "general_operand" "f,R")))] 5033 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5034 "@ 5035 debr\t%0,%2 5036 deb\t%0,%2" 5037 [(set_attr "op_type" "RRE,RXE") 5038 (set_attr "type" "fdivs")]) 5039 5040(define_insn "*divsf3" 5041 [(set (match_operand:SF 0 "register_operand" "=f,f") 5042 (div:SF (match_operand:SF 1 "register_operand" "0,0") 5043 (match_operand:SF 2 "general_operand" "f,R")))] 5044 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 5045 "@ 5046 der\t%0,%2 5047 de\t%0,%2" 5048 [(set_attr "op_type" "RR,RX") 5049 (set_attr "type" "fdivs")]) 5050 5051 5052;; 5053;;- And instructions. 5054;; 5055 5056; 5057; anddi3 instruction pattern(s). 5058; 5059 5060(define_insn "*anddi3_cc" 5061 [(set (reg 33) 5062 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 5063 (match_operand:DI 2 "general_operand" "d,m")) 5064 (const_int 0))) 5065 (set (match_operand:DI 0 "register_operand" "=d,d") 5066 (and:DI (match_dup 1) (match_dup 2)))] 5067 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 5068 "@ 5069 ngr\t%0,%2 5070 ng\t%0,%2" 5071 [(set_attr "op_type" "RRE,RXY")]) 5072 5073(define_insn "*anddi3_cconly" 5074 [(set (reg 33) 5075 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 5076 (match_operand:DI 2 "general_operand" "d,m")) 5077 (const_int 0))) 5078 (clobber (match_scratch:DI 0 "=d,d"))] 5079 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 5080 "@ 5081 ngr\t%0,%2 5082 ng\t%0,%2" 5083 [(set_attr "op_type" "RRE,RXY")]) 5084 5085(define_insn "anddi3" 5086 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d,d,d,d") 5087 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o,0,0,0,0,0,0") 5088 (match_operand:DI 2 "general_operand" 5089 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m"))) 5090 (clobber (reg:CC 33))] 5091 "TARGET_64BIT" 5092 "@ 5093 # 5094 # 5095 nihh\t%0,%j2 5096 nihl\t%0,%j2 5097 nilh\t%0,%j2 5098 nill\t%0,%j2 5099 ngr\t%0,%2 5100 ng\t%0,%2" 5101 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY")]) 5102 5103(define_insn "*anddi3_ss" 5104 [(set (match_operand:DI 0 "s_operand" "=Q") 5105 (and:DI (match_dup 0) 5106 (match_operand:DI 1 "s_imm_operand" "Q"))) 5107 (clobber (reg:CC 33))] 5108 "" 5109 "nc\t%O0(8,%R0),%1" 5110 [(set_attr "op_type" "SS")]) 5111 5112(define_insn "*anddi3_ss_inv" 5113 [(set (match_operand:DI 0 "s_operand" "=Q") 5114 (and:DI (match_operand:DI 1 "s_imm_operand" "Q") 5115 (match_dup 0))) 5116 (clobber (reg:CC 33))] 5117 "" 5118 "nc\t%O0(8,%R0),%1" 5119 [(set_attr "op_type" "SS")]) 5120 5121; 5122; andsi3 instruction pattern(s). 5123; 5124 5125(define_insn "*andsi3_cc" 5126 [(set (reg 33) 5127 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 5128 (match_operand:SI 2 "general_operand" "d,R,T")) 5129 (const_int 0))) 5130 (set (match_operand:SI 0 "register_operand" "=d,d,d") 5131 (and:SI (match_dup 1) (match_dup 2)))] 5132 "s390_match_ccmode(insn, CCTmode)" 5133 "@ 5134 nr\t%0,%2 5135 n\t%0,%2 5136 ny\t%0,%2" 5137 [(set_attr "op_type" "RR,RX,RXY")]) 5138 5139(define_insn "*andsi3_cconly" 5140 [(set (reg 33) 5141 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 5142 (match_operand:SI 2 "general_operand" "d,R,T")) 5143 (const_int 0))) 5144 (clobber (match_scratch:SI 0 "=d,d,d"))] 5145 "s390_match_ccmode(insn, CCTmode)" 5146 "@ 5147 nr\t%0,%2 5148 n\t%0,%2 5149 ny\t%0,%2" 5150 [(set_attr "op_type" "RR,RX,RXY")]) 5151 5152(define_expand "andsi3" 5153 [(parallel 5154 [(set (match_operand:SI 0 "register_operand" "") 5155 (and:SI (match_operand:SI 1 "nonimmediate_operand" "") 5156 (match_operand:SI 2 "general_operand" ""))) 5157 (clobber (reg:CC 33))])] 5158 "" 5159 "") 5160 5161(define_insn "*andsi3_zarch" 5162 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d,d") 5163 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,o,0,0,0,0,0") 5164 (match_operand:SI 2 "general_operand" "M,M,N0HSF,N1HSF,d,R,T"))) 5165 (clobber (reg:CC 33))] 5166 "TARGET_ZARCH" 5167 "@ 5168 # 5169 # 5170 nilh\t%0,%j2 5171 nill\t%0,%j2 5172 nr\t%0,%2 5173 n\t%0,%2 5174 ny\t%0,%2" 5175 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY")]) 5176 5177(define_insn "*andsi3_esa" 5178 [(set (match_operand:SI 0 "register_operand" "=d,d") 5179 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 5180 (match_operand:SI 2 "general_operand" "d,R"))) 5181 (clobber (reg:CC 33))] 5182 "!TARGET_ZARCH" 5183 "@ 5184 nr\t%0,%2 5185 n\t%0,%2" 5186 [(set_attr "op_type" "RR,RX")]) 5187 5188(define_insn "*andsi3_ss" 5189 [(set (match_operand:SI 0 "s_operand" "=Q") 5190 (and:SI (match_dup 0) 5191 (match_operand:SI 1 "s_imm_operand" "Q"))) 5192 (clobber (reg:CC 33))] 5193 "" 5194 "nc\t%O0(4,%R0),%1" 5195 [(set_attr "op_type" "SS")]) 5196 5197(define_insn "*andsi3_ss_inv" 5198 [(set (match_operand:SI 0 "s_operand" "=Q") 5199 (and:SI (match_operand:SI 1 "s_imm_operand" "Q") 5200 (match_dup 0))) 5201 (clobber (reg:CC 33))] 5202 "" 5203 "nc\t%O0(4,%R0),%1" 5204 [(set_attr "op_type" "SS")]) 5205 5206; 5207; andhi3 instruction pattern(s). 5208; 5209 5210(define_insn "*andhi3_ni" 5211 [(set (match_operand:HI 0 "register_operand" "=d,d") 5212 (and:HI (match_operand:HI 1 "register_operand" "%0,0") 5213 (match_operand:HI 2 "nonmemory_operand" "d,n"))) 5214 (clobber (reg:CC 33))] 5215 "TARGET_ZARCH" 5216 "@ 5217 nr\t%0,%2 5218 nill\t%0,%x2" 5219 [(set_attr "op_type" "RR,RI")]) 5220 5221(define_insn "andhi3" 5222 [(set (match_operand:HI 0 "register_operand" "=d") 5223 (and:HI (match_operand:HI 1 "register_operand" "%0") 5224 (match_operand:HI 2 "nonmemory_operand" "d"))) 5225 (clobber (reg:CC 33))] 5226 "" 5227 "nr\t%0,%2" 5228 [(set_attr "op_type" "RR")]) 5229 5230(define_insn "*andhi3_ss" 5231 [(set (match_operand:HI 0 "s_operand" "=Q") 5232 (and:HI (match_dup 0) 5233 (match_operand:HI 1 "s_imm_operand" "Q"))) 5234 (clobber (reg:CC 33))] 5235 "" 5236 "nc\t%O0(2,%R0),%1" 5237 [(set_attr "op_type" "SS")]) 5238 5239(define_insn "*andhi3_ss_inv" 5240 [(set (match_operand:HI 0 "s_operand" "=Q") 5241 (and:HI (match_operand:HI 1 "s_imm_operand" "Q") 5242 (match_dup 0))) 5243 (clobber (reg:CC 33))] 5244 "" 5245 "nc\t%O0(2,%R0),%1" 5246 [(set_attr "op_type" "SS")]) 5247 5248; 5249; andqi3 instruction pattern(s). 5250; 5251 5252(define_insn "*andqi3_ni" 5253 [(set (match_operand:QI 0 "register_operand" "=d,d") 5254 (and:QI (match_operand:QI 1 "register_operand" "%0,0") 5255 (match_operand:QI 2 "nonmemory_operand" "d,n"))) 5256 (clobber (reg:CC 33))] 5257 "TARGET_ZARCH" 5258 "@ 5259 nr\t%0,%2 5260 nill\t%0,%b2" 5261 [(set_attr "op_type" "RR,RI")]) 5262 5263(define_insn "andqi3" 5264 [(set (match_operand:QI 0 "register_operand" "=d") 5265 (and:QI (match_operand:QI 1 "register_operand" "%0") 5266 (match_operand:QI 2 "nonmemory_operand" "d"))) 5267 (clobber (reg:CC 33))] 5268 "" 5269 "nr\t%0,%2" 5270 [(set_attr "op_type" "RR")]) 5271 5272(define_insn "*andqi3_ss" 5273 [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") 5274 (and:QI (match_dup 0) 5275 (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) 5276 (clobber (reg:CC 33))] 5277 "" 5278 "@ 5279 ni\t%0,%b1 5280 niy\t%0,%b1 5281 nc\t%O0(1,%R0),%1" 5282 [(set_attr "op_type" "SI,SIY,SS")]) 5283 5284(define_insn "*andqi3_ss_inv" 5285 [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") 5286 (and:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") 5287 (match_dup 0))) 5288 (clobber (reg:CC 33))] 5289 "" 5290 "@ 5291 ni\t%0,%b1 5292 niy\t%0,%b1 5293 nc\t%O0(1,%R0),%1" 5294 [(set_attr "op_type" "SI,SIY,SS")]) 5295 5296 5297;; 5298;;- Bit set (inclusive or) instructions. 5299;; 5300 5301; 5302; iordi3 instruction pattern(s). 5303; 5304 5305(define_insn "*iordi3_cc" 5306 [(set (reg 33) 5307 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 5308 (match_operand:DI 2 "general_operand" "d,m")) 5309 (const_int 0))) 5310 (set (match_operand:DI 0 "register_operand" "=d,d") 5311 (ior:DI (match_dup 1) (match_dup 2)))] 5312 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 5313 "@ 5314 ogr\t%0,%2 5315 og\t%0,%2" 5316 [(set_attr "op_type" "RRE,RXY")]) 5317 5318(define_insn "*iordi3_cconly" 5319 [(set (reg 33) 5320 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 5321 (match_operand:DI 2 "general_operand" "d,m")) 5322 (const_int 0))) 5323 (clobber (match_scratch:DI 0 "=d,d"))] 5324 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 5325 "@ 5326 ogr\t%0,%2 5327 og\t%0,%2" 5328 [(set_attr "op_type" "RRE,RXY")]) 5329 5330(define_insn "iordi3" 5331 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d,d") 5332 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "0,0,0,0,0,0") 5333 (match_operand:DI 2 "general_operand" "N0HD0,N1HD0,N2HD0,N3HD0,d,m"))) 5334 (clobber (reg:CC 33))] 5335 "TARGET_64BIT" 5336 "@ 5337 oihh\t%0,%i2 5338 oihl\t%0,%i2 5339 oilh\t%0,%i2 5340 oill\t%0,%i2 5341 ogr\t%0,%2 5342 og\t%0,%2" 5343 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY")]) 5344 5345(define_insn "*iordi3_ss" 5346 [(set (match_operand:DI 0 "s_operand" "=Q") 5347 (ior:DI (match_dup 0) 5348 (match_operand:DI 1 "s_imm_operand" "Q"))) 5349 (clobber (reg:CC 33))] 5350 "" 5351 "oc\t%O0(8,%R0),%1" 5352 [(set_attr "op_type" "SS")]) 5353 5354(define_insn "*iordi3_ss_inv" 5355 [(set (match_operand:DI 0 "s_operand" "=Q") 5356 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q") 5357 (match_dup 0))) 5358 (clobber (reg:CC 33))] 5359 "" 5360 "oc\t%O0(8,%R0),%1" 5361 [(set_attr "op_type" "SS")]) 5362 5363; 5364; iorsi3 instruction pattern(s). 5365; 5366 5367(define_insn "*iorsi3_cc" 5368 [(set (reg 33) 5369 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 5370 (match_operand:SI 2 "general_operand" "d,R,T")) 5371 (const_int 0))) 5372 (set (match_operand:SI 0 "register_operand" "=d,d,d") 5373 (ior:SI (match_dup 1) (match_dup 2)))] 5374 "s390_match_ccmode(insn, CCTmode)" 5375 "@ 5376 or\t%0,%2 5377 o\t%0,%2 5378 oy\t%0,%2" 5379 [(set_attr "op_type" "RR,RX,RXY")]) 5380 5381(define_insn "*iorsi3_cconly" 5382 [(set (reg 33) 5383 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 5384 (match_operand:SI 2 "general_operand" "d,R,T")) 5385 (const_int 0))) 5386 (clobber (match_scratch:SI 0 "=d,d,d"))] 5387 "s390_match_ccmode(insn, CCTmode)" 5388 "@ 5389 or\t%0,%2 5390 o\t%0,%2 5391 oy\t%0,%2" 5392 [(set_attr "op_type" "RR,RX,RXY")]) 5393 5394(define_expand "iorsi3" 5395 [(parallel 5396 [(set (match_operand:SI 0 "register_operand" "") 5397 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") 5398 (match_operand:SI 2 "general_operand" ""))) 5399 (clobber (reg:CC 33))])] 5400 "" 5401 "") 5402 5403(define_insn "iorsi3_zarch" 5404 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") 5405 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0,0,0,0,0") 5406 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T"))) 5407 (clobber (reg:CC 33))] 5408 "TARGET_ZARCH" 5409 "@ 5410 oilh\t%0,%i2 5411 oill\t%0,%i2 5412 or\t%0,%2 5413 o\t%0,%2 5414 oy\t%0,%2" 5415 [(set_attr "op_type" "RI,RI,RR,RX,RXY")]) 5416 5417(define_insn "iorsi3_esa" 5418 [(set (match_operand:SI 0 "register_operand" "=d,d") 5419 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") 5420 (match_operand:SI 2 "general_operand" "d,R"))) 5421 (clobber (reg:CC 33))] 5422 "!TARGET_ZARCH" 5423 "@ 5424 or\t%0,%2 5425 o\t%0,%2" 5426 [(set_attr "op_type" "RR,RX")]) 5427 5428(define_insn "*iorsi3_ss" 5429 [(set (match_operand:SI 0 "s_operand" "=Q") 5430 (ior:SI (match_dup 0) 5431 (match_operand:SI 1 "s_imm_operand" "Q"))) 5432 (clobber (reg:CC 33))] 5433 "" 5434 "oc\t%O0(4,%R0),%1" 5435 [(set_attr "op_type" "SS")]) 5436 5437(define_insn "*iorsi3_ss_inv" 5438 [(set (match_operand:SI 0 "s_operand" "=Q") 5439 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q") 5440 (match_dup 0))) 5441 (clobber (reg:CC 33))] 5442 "" 5443 "oc\t%O0(4,%R0),%1" 5444 [(set_attr "op_type" "SS")]) 5445 5446; 5447; iorhi3 instruction pattern(s). 5448; 5449 5450(define_insn "*iorhi3_oi" 5451 [(set (match_operand:HI 0 "register_operand" "=d,d") 5452 (ior:HI (match_operand:HI 1 "register_operand" "%0,0") 5453 (match_operand:HI 2 "nonmemory_operand" "d,n"))) 5454 (clobber (reg:CC 33))] 5455 "TARGET_ZARCH" 5456 "@ 5457 or\t%0,%2 5458 oill\t%0,%x2" 5459 [(set_attr "op_type" "RR,RI")]) 5460 5461(define_insn "iorhi3" 5462 [(set (match_operand:HI 0 "register_operand" "=d") 5463 (ior:HI (match_operand:HI 1 "register_operand" "%0") 5464 (match_operand:HI 2 "nonmemory_operand" "d"))) 5465 (clobber (reg:CC 33))] 5466 "" 5467 "or\t%0,%2" 5468 [(set_attr "op_type" "RR")]) 5469 5470(define_insn "*iorhi3_ss" 5471 [(set (match_operand:HI 0 "s_operand" "=Q") 5472 (ior:HI (match_dup 0) 5473 (match_operand:HI 1 "s_imm_operand" "Q"))) 5474 (clobber (reg:CC 33))] 5475 "" 5476 "oc\t%O0(2,%R0),%1" 5477 [(set_attr "op_type" "SS")]) 5478 5479(define_insn "*iorhi3_ss_inv" 5480 [(set (match_operand:HI 0 "s_operand" "=Q") 5481 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q") 5482 (match_dup 0))) 5483 (clobber (reg:CC 33))] 5484 "" 5485 "oc\t%O0(2,%R0),%1" 5486 [(set_attr "op_type" "SS")]) 5487 5488; 5489; iorqi3 instruction pattern(s). 5490; 5491 5492(define_insn "*iorqi3_oi" 5493 [(set (match_operand:QI 0 "register_operand" "=d,d") 5494 (ior:QI (match_operand:QI 1 "register_operand" "%0,0") 5495 (match_operand:QI 2 "nonmemory_operand" "d,n"))) 5496 (clobber (reg:CC 33))] 5497 "TARGET_ZARCH" 5498 "@ 5499 or\t%0,%2 5500 oill\t%0,%b2" 5501 [(set_attr "op_type" "RR,RI")]) 5502 5503(define_insn "iorqi3" 5504 [(set (match_operand:QI 0 "register_operand" "=d") 5505 (ior:QI (match_operand:QI 1 "register_operand" "%0") 5506 (match_operand:QI 2 "nonmemory_operand" "d"))) 5507 (clobber (reg:CC 33))] 5508 "" 5509 "or\t%0,%2" 5510 [(set_attr "op_type" "RR")]) 5511 5512(define_insn "*iorqi3_ss" 5513 [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") 5514 (ior:QI (match_dup 0) 5515 (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) 5516 (clobber (reg:CC 33))] 5517 "" 5518 "@ 5519 oi\t%0,%b1 5520 oiy\t%0,%b1 5521 oc\t%O0(1,%R0),%1" 5522 [(set_attr "op_type" "SI,SIY,SS")]) 5523 5524(define_insn "*iorqi3_ss_inv" 5525 [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") 5526 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") 5527 (match_dup 0))) 5528 (clobber (reg:CC 33))] 5529 "" 5530 "@ 5531 oi\t%0,%b1 5532 oiy\t%0,%b1 5533 oc\t%O0(1,%R0),%1" 5534 [(set_attr "op_type" "SI,SIY,SS")]) 5535 5536 5537;; 5538;;- Xor instructions. 5539;; 5540 5541; 5542; xordi3 instruction pattern(s). 5543; 5544 5545(define_insn "*xordi3_cc" 5546 [(set (reg 33) 5547 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 5548 (match_operand:DI 2 "general_operand" "d,m")) 5549 (const_int 0))) 5550 (set (match_operand:DI 0 "register_operand" "=d,d") 5551 (xor:DI (match_dup 1) (match_dup 2)))] 5552 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 5553 "@ 5554 xgr\t%0,%2 5555 xg\t%0,%2" 5556 [(set_attr "op_type" "RRE,RXY")]) 5557 5558(define_insn "*xordi3_cconly" 5559 [(set (reg 33) 5560 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 5561 (match_operand:DI 2 "general_operand" "d,m")) 5562 (const_int 0))) 5563 (clobber (match_scratch:DI 0 "=d,d"))] 5564 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 5565 "@ 5566 xgr\t%0,%2 5567 xr\t%0,%2" 5568 [(set_attr "op_type" "RRE,RXY")]) 5569 5570(define_insn "xordi3" 5571 [(set (match_operand:DI 0 "register_operand" "=d,d") 5572 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 5573 (match_operand:DI 2 "general_operand" "d,m"))) 5574 (clobber (reg:CC 33))] 5575 "TARGET_64BIT" 5576 "@ 5577 xgr\t%0,%2 5578 xg\t%0,%2" 5579 [(set_attr "op_type" "RRE,RXY")]) 5580 5581(define_insn "*xordi3_ss" 5582 [(set (match_operand:DI 0 "s_operand" "=Q") 5583 (xor:DI (match_dup 0) 5584 (match_operand:DI 1 "s_imm_operand" "Q"))) 5585 (clobber (reg:CC 33))] 5586 "" 5587 "xc\t%O0(8,%R0),%1" 5588 [(set_attr "op_type" "SS")]) 5589 5590(define_insn "*xordi3_ss_inv" 5591 [(set (match_operand:DI 0 "s_operand" "=Q") 5592 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q") 5593 (match_dup 0))) 5594 (clobber (reg:CC 33))] 5595 "" 5596 "xc\t%O0(8,%R0),%1" 5597 [(set_attr "op_type" "SS")]) 5598 5599; 5600; xorsi3 instruction pattern(s). 5601; 5602 5603(define_insn "*xorsi3_cc" 5604 [(set (reg 33) 5605 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 5606 (match_operand:SI 2 "general_operand" "d,R,T")) 5607 (const_int 0))) 5608 (set (match_operand:SI 0 "register_operand" "=d,d,d") 5609 (xor:SI (match_dup 1) (match_dup 2)))] 5610 "s390_match_ccmode(insn, CCTmode)" 5611 "@ 5612 xr\t%0,%2 5613 x\t%0,%2 5614 xy\t%0,%2" 5615 [(set_attr "op_type" "RR,RX,RXY")]) 5616 5617(define_insn "*xorsi3_cconly" 5618 [(set (reg 33) 5619 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 5620 (match_operand:SI 2 "general_operand" "d,R,T")) 5621 (const_int 0))) 5622 (clobber (match_scratch:SI 0 "=d,d,d"))] 5623 "s390_match_ccmode(insn, CCTmode)" 5624 "@ 5625 xr\t%0,%2 5626 x\t%0,%2 5627 xy\t%0,%2" 5628 [(set_attr "op_type" "RR,RX,RXY")]) 5629 5630(define_insn "xorsi3" 5631 [(set (match_operand:SI 0 "register_operand" "=d,d,d") 5632 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 5633 (match_operand:SI 2 "general_operand" "d,R,T"))) 5634 (clobber (reg:CC 33))] 5635 "" 5636 "@ 5637 xr\t%0,%2 5638 x\t%0,%2 5639 xy\t%0,%2" 5640 [(set_attr "op_type" "RR,RX,RXY")]) 5641 5642(define_insn "*xorsi3_ss" 5643 [(set (match_operand:SI 0 "s_operand" "=Q") 5644 (xor:SI (match_dup 0) 5645 (match_operand:SI 1 "s_imm_operand" "Q"))) 5646 (clobber (reg:CC 33))] 5647 "" 5648 "xc\t%O0(4,%R0),%1" 5649 [(set_attr "op_type" "SS")]) 5650 5651(define_insn "*xorsi3_ss_inv" 5652 [(set (match_operand:SI 0 "s_operand" "=Q") 5653 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q") 5654 (match_dup 0))) 5655 (clobber (reg:CC 33))] 5656 "" 5657 "xc\t%O0(4,%R0),%1" 5658 [(set_attr "op_type" "SS")]) 5659 5660; 5661; xorhi3 instruction pattern(s). 5662; 5663 5664(define_insn "xorhi3" 5665 [(set (match_operand:HI 0 "register_operand" "=d") 5666 (xor:HI (match_operand:HI 1 "register_operand" "%0") 5667 (match_operand:HI 2 "nonmemory_operand" "d"))) 5668 (clobber (reg:CC 33))] 5669 "" 5670 "xr\t%0,%2" 5671 [(set_attr "op_type" "RR")]) 5672 5673(define_insn "*xorhi3_ss" 5674 [(set (match_operand:HI 0 "s_operand" "=Q") 5675 (xor:HI (match_dup 0) 5676 (match_operand:HI 1 "s_imm_operand" "Q"))) 5677 (clobber (reg:CC 33))] 5678 "" 5679 "xc\t%O0(2,%R0),%1" 5680 [(set_attr "op_type" "SS")]) 5681 5682(define_insn "*xorhi3_ss_inv" 5683 [(set (match_operand:HI 0 "s_operand" "=Q") 5684 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q") 5685 (match_dup 0))) 5686 (clobber (reg:CC 33))] 5687 "" 5688 "xc\t%O0(2,%R0),%1" 5689 [(set_attr "op_type" "SS")]) 5690 5691; 5692; xorqi3 instruction pattern(s). 5693; 5694 5695(define_insn "xorqi3" 5696 [(set (match_operand:QI 0 "register_operand" "=d") 5697 (xor:QI (match_operand:QI 1 "register_operand" "%0") 5698 (match_operand:QI 2 "nonmemory_operand" "d"))) 5699 (clobber (reg:CC 33))] 5700 "" 5701 "xr\t%0,%2" 5702 [(set_attr "op_type" "RR")]) 5703 5704(define_insn "*xorqi3_ss" 5705 [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") 5706 (xor:QI (match_dup 0) 5707 (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) 5708 (clobber (reg:CC 33))] 5709 "" 5710 "@ 5711 xi\t%0,%b1 5712 xiy\t%0,%b1 5713 xc\t%O0(1,%R0),%1" 5714 [(set_attr "op_type" "SI,SIY,SS")]) 5715 5716(define_insn "*xorqi3_ss_inv" 5717 [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") 5718 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") 5719 (match_dup 0))) 5720 (clobber (reg:CC 33))] 5721 "" 5722 "@ 5723 xi\t%0,%b1 5724 xiy\t%0,%b1 5725 xc\t%O0(1,%R0),%1" 5726 [(set_attr "op_type" "SI,SIY,SS")]) 5727 5728 5729;; 5730;;- Negate instructions. 5731;; 5732 5733; 5734; negdi2 instruction pattern(s). 5735; 5736 5737(define_expand "negdi2" 5738 [(parallel 5739 [(set (match_operand:DI 0 "register_operand" "=d") 5740 (neg:DI (match_operand:DI 1 "register_operand" "d"))) 5741 (clobber (reg:CC 33))])] 5742 "" 5743 "") 5744 5745(define_insn "*negdi2_64" 5746 [(set (match_operand:DI 0 "register_operand" "=d") 5747 (neg:DI (match_operand:DI 1 "register_operand" "d"))) 5748 (clobber (reg:CC 33))] 5749 "TARGET_64BIT" 5750 "lcgr\t%0,%1" 5751 [(set_attr "op_type" "RR")]) 5752 5753(define_insn "*negdi2_31" 5754 [(set (match_operand:DI 0 "register_operand" "=d") 5755 (neg:DI (match_operand:DI 1 "register_operand" "d"))) 5756 (clobber (reg:CC 33))] 5757 "!TARGET_64BIT" 5758{ 5759 rtx xop[1]; 5760 xop[0] = gen_label_rtx (); 5761 output_asm_insn ("lcr\t%0,%1", operands); 5762 output_asm_insn ("lcr\t%N0,%N1", operands); 5763 output_asm_insn ("je\t%l0", xop); 5764 output_asm_insn ("bctr\t%0,0", operands); 5765 targetm.asm_out.internal_label (asm_out_file, "L", 5766 CODE_LABEL_NUMBER (xop[0])); 5767 return ""; 5768} 5769 [(set_attr "op_type" "NN") 5770 (set_attr "type" "other") 5771 (set_attr "length" "10")]) 5772 5773; 5774; negsi2 instruction pattern(s). 5775; 5776 5777(define_insn "negsi2" 5778 [(set (match_operand:SI 0 "register_operand" "=d") 5779 (neg:SI (match_operand:SI 1 "register_operand" "d"))) 5780 (clobber (reg:CC 33))] 5781 "" 5782 "lcr\t%0,%1" 5783 [(set_attr "op_type" "RR")]) 5784 5785; 5786; negdf2 instruction pattern(s). 5787; 5788 5789(define_expand "negdf2" 5790 [(parallel 5791 [(set (match_operand:DF 0 "register_operand" "=f") 5792 (neg:DF (match_operand:DF 1 "register_operand" "f"))) 5793 (clobber (reg:CC 33))])] 5794 "TARGET_HARD_FLOAT" 5795 "") 5796 5797(define_insn "*negdf2" 5798 [(set (match_operand:DF 0 "register_operand" "=f") 5799 (neg:DF (match_operand:DF 1 "register_operand" "f"))) 5800 (clobber (reg:CC 33))] 5801 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5802 "lcdbr\t%0,%1" 5803 [(set_attr "op_type" "RRE") 5804 (set_attr "type" "fsimpd")]) 5805 5806(define_insn "*negdf2_ibm" 5807 [(set (match_operand:DF 0 "register_operand" "=f") 5808 (neg:DF (match_operand:DF 1 "register_operand" "f"))) 5809 (clobber (reg:CC 33))] 5810 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 5811 "lcdr\t%0,%1" 5812 [(set_attr "op_type" "RR") 5813 (set_attr "type" "fsimpd")]) 5814 5815; 5816; negsf2 instruction pattern(s). 5817; 5818 5819(define_expand "negsf2" 5820 [(parallel 5821 [(set (match_operand:SF 0 "register_operand" "=f") 5822 (neg:SF (match_operand:SF 1 "register_operand" "f"))) 5823 (clobber (reg:CC 33))])] 5824 "TARGET_HARD_FLOAT" 5825 "") 5826 5827(define_insn "*negsf2" 5828 [(set (match_operand:SF 0 "register_operand" "=f") 5829 (neg:SF (match_operand:SF 1 "register_operand" "f"))) 5830 (clobber (reg:CC 33))] 5831 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5832 "lcebr\t%0,%1" 5833 [(set_attr "op_type" "RRE") 5834 (set_attr "type" "fsimps")]) 5835 5836(define_insn "*negsf2" 5837 [(set (match_operand:SF 0 "register_operand" "=f") 5838 (neg:SF (match_operand:SF 1 "register_operand" "f"))) 5839 (clobber (reg:CC 33))] 5840 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 5841 "lcer\t%0,%1" 5842 [(set_attr "op_type" "RR") 5843 (set_attr "type" "fsimps")]) 5844 5845 5846;; 5847;;- Absolute value instructions. 5848;; 5849 5850; 5851; absdi2 instruction pattern(s). 5852; 5853 5854(define_insn "absdi2" 5855 [(set (match_operand:DI 0 "register_operand" "=d") 5856 (abs:DI (match_operand:DI 1 "register_operand" "d"))) 5857 (clobber (reg:CC 33))] 5858 "TARGET_64BIT" 5859 "lpgr\t%0,%1" 5860 [(set_attr "op_type" "RRE")]) 5861 5862; 5863; abssi2 instruction pattern(s). 5864; 5865 5866(define_insn "abssi2" 5867 [(set (match_operand:SI 0 "register_operand" "=d") 5868 (abs:SI (match_operand:SI 1 "register_operand" "d"))) 5869 (clobber (reg:CC 33))] 5870 "" 5871 "lpr\t%0,%1" 5872 [(set_attr "op_type" "RR")]) 5873 5874; 5875; absdf2 instruction pattern(s). 5876; 5877 5878(define_expand "absdf2" 5879 [(parallel 5880 [(set (match_operand:DF 0 "register_operand" "=f") 5881 (abs:DF (match_operand:DF 1 "register_operand" "f"))) 5882 (clobber (reg:CC 33))])] 5883 "TARGET_HARD_FLOAT" 5884 "") 5885 5886(define_insn "*absdf2" 5887 [(set (match_operand:DF 0 "register_operand" "=f") 5888 (abs:DF (match_operand:DF 1 "register_operand" "f"))) 5889 (clobber (reg:CC 33))] 5890 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5891 "lpdbr\t%0,%1" 5892 [(set_attr "op_type" "RRE") 5893 (set_attr "type" "fsimpd")]) 5894 5895(define_insn "*absdf2_ibm" 5896 [(set (match_operand:DF 0 "register_operand" "=f") 5897 (abs:DF (match_operand:DF 1 "register_operand" "f"))) 5898 (clobber (reg:CC 33))] 5899 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 5900 "lpdr\t%0,%1" 5901 [(set_attr "op_type" "RR") 5902 (set_attr "type" "fsimpd")]) 5903 5904; 5905; abssf2 instruction pattern(s). 5906; 5907 5908(define_expand "abssf2" 5909 [(parallel 5910 [(set (match_operand:SF 0 "register_operand" "=f") 5911 (abs:SF (match_operand:SF 1 "register_operand" "f"))) 5912 (clobber (reg:CC 33))])] 5913 "TARGET_HARD_FLOAT" 5914 "") 5915 5916(define_insn "*abssf2" 5917 [(set (match_operand:SF 0 "register_operand" "=f") 5918 (abs:SF (match_operand:SF 1 "register_operand" "f"))) 5919 (clobber (reg:CC 33))] 5920 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5921 "lpebr\t%0,%1" 5922 [(set_attr "op_type" "RRE") 5923 (set_attr "type" "fsimps")]) 5924 5925(define_insn "*abssf2_ibm" 5926 [(set (match_operand:SF 0 "register_operand" "=f") 5927 (abs:SF (match_operand:SF 1 "register_operand" "f"))) 5928 (clobber (reg:CC 33))] 5929 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 5930 "lper\t%0,%1" 5931 [(set_attr "op_type" "RR") 5932 (set_attr "type" "fsimps")]) 5933 5934;; 5935;;- Negated absolute value instructions 5936;; 5937 5938; 5939; Integer 5940; 5941 5942(define_insn "*negabssi2" 5943 [(set (match_operand:SI 0 "register_operand" "=d") 5944 (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))) 5945 (clobber (reg:CC 33))] 5946 "" 5947 "lnr\t%0,%1" 5948 [(set_attr "op_type" "RR")]) 5949 5950(define_insn "*negabsdi2" 5951 [(set (match_operand:DI 0 "register_operand" "=d") 5952 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))) 5953 (clobber (reg:CC 33))] 5954 "TARGET_64BIT" 5955 "lngr\t%0,%1" 5956 [(set_attr "op_type" "RRE")]) 5957 5958; 5959; Floating point 5960; 5961 5962(define_insn "*negabssf2" 5963 [(set (match_operand:SF 0 "register_operand" "=f") 5964 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) 5965 (clobber (reg:CC 33))] 5966 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5967 "lnebr\t%0,%1" 5968 [(set_attr "op_type" "RRE") 5969 (set_attr "type" "fsimps")]) 5970 5971(define_insn "*negabsdf2" 5972 [(set (match_operand:DF 0 "register_operand" "=f") 5973 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) 5974 (clobber (reg:CC 33))] 5975 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5976 "lndbr\t%0,%1" 5977 [(set_attr "op_type" "RRE") 5978 (set_attr "type" "fsimpd")]) 5979 5980;; 5981;;- Square root instructions. 5982;; 5983 5984; 5985; sqrtdf2 instruction pattern(s). 5986; 5987 5988(define_insn "sqrtdf2" 5989 [(set (match_operand:DF 0 "register_operand" "=f,f") 5990 (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))] 5991 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5992 "@ 5993 sqdbr\t%0,%1 5994 sqdb\t%0,%1" 5995 [(set_attr "op_type" "RRE,RXE")]) 5996 5997; 5998; sqrtsf2 instruction pattern(s). 5999; 6000 6001(define_insn "sqrtsf2" 6002 [(set (match_operand:SF 0 "register_operand" "=f,f") 6003 (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))] 6004 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 6005 "@ 6006 sqebr\t%0,%1 6007 sqeb\t%0,%1" 6008 [(set_attr "op_type" "RRE,RXE")]) 6009 6010;; 6011;;- One complement instructions. 6012;; 6013 6014; 6015; one_cmpldi2 instruction pattern(s). 6016; 6017 6018(define_expand "one_cmpldi2" 6019 [(parallel 6020 [(set (match_operand:DI 0 "register_operand" "") 6021 (xor:DI (match_operand:DI 1 "register_operand" "") 6022 (const_int -1))) 6023 (clobber (reg:CC 33))])] 6024 "TARGET_64BIT" 6025 "") 6026 6027; 6028; one_cmplsi2 instruction pattern(s). 6029; 6030 6031(define_expand "one_cmplsi2" 6032 [(parallel 6033 [(set (match_operand:SI 0 "register_operand" "") 6034 (xor:SI (match_operand:SI 1 "register_operand" "") 6035 (const_int -1))) 6036 (clobber (reg:CC 33))])] 6037 "" 6038 "") 6039 6040; 6041; one_cmplhi2 instruction pattern(s). 6042; 6043 6044(define_expand "one_cmplhi2" 6045 [(parallel 6046 [(set (match_operand:HI 0 "register_operand" "") 6047 (xor:HI (match_operand:HI 1 "register_operand" "") 6048 (const_int -1))) 6049 (clobber (reg:CC 33))])] 6050 "" 6051 "") 6052 6053; 6054; one_cmplqi2 instruction pattern(s). 6055; 6056 6057(define_expand "one_cmplqi2" 6058 [(parallel 6059 [(set (match_operand:QI 0 "register_operand" "") 6060 (xor:QI (match_operand:QI 1 "register_operand" "") 6061 (const_int -1))) 6062 (clobber (reg:CC 33))])] 6063 "" 6064 "") 6065 6066 6067;; 6068;;- Rotate instructions. 6069;; 6070 6071; 6072; rotldi3 instruction pattern(s). 6073; 6074 6075(define_insn "rotldi3" 6076 [(set (match_operand:DI 0 "register_operand" "=d") 6077 (rotate:DI (match_operand:DI 1 "register_operand" "d") 6078 (match_operand:SI 2 "shift_count_operand" "Y")))] 6079 "TARGET_64BIT" 6080 "rllg\t%0,%1,%Y2" 6081 [(set_attr "op_type" "RSE") 6082 (set_attr "atype" "reg")]) 6083 6084; 6085; rotlsi3 instruction pattern(s). 6086; 6087 6088(define_insn "rotlsi3" 6089 [(set (match_operand:SI 0 "register_operand" "=d") 6090 (rotate:SI (match_operand:SI 1 "register_operand" "d") 6091 (match_operand:SI 2 "shift_count_operand" "Y")))] 6092 "TARGET_CPU_ZARCH" 6093 "rll\t%0,%1,%Y2" 6094 [(set_attr "op_type" "RSE") 6095 (set_attr "atype" "reg")]) 6096 6097 6098;; 6099;;- Arithmetic shift instructions. 6100;; 6101 6102; 6103; ashldi3 instruction pattern(s). 6104; 6105 6106(define_expand "ashldi3" 6107 [(set (match_operand:DI 0 "register_operand" "") 6108 (ashift:DI (match_operand:DI 1 "register_operand" "") 6109 (match_operand:SI 2 "shift_count_operand" "")))] 6110 "" 6111 "") 6112 6113(define_insn "*ashldi3_31" 6114 [(set (match_operand:DI 0 "register_operand" "=d") 6115 (ashift:DI (match_operand:DI 1 "register_operand" "0") 6116 (match_operand:SI 2 "shift_count_operand" "Y")))] 6117 "!TARGET_64BIT" 6118 "sldl\t%0,%Y2" 6119 [(set_attr "op_type" "RS") 6120 (set_attr "atype" "reg")]) 6121 6122(define_insn "*ashldi3_64" 6123 [(set (match_operand:DI 0 "register_operand" "=d") 6124 (ashift:DI (match_operand:DI 1 "register_operand" "d") 6125 (match_operand:SI 2 "shift_count_operand" "Y")))] 6126 "TARGET_64BIT" 6127 "sllg\t%0,%1,%Y2" 6128 [(set_attr "op_type" "RSE") 6129 (set_attr "atype" "reg")]) 6130 6131; 6132; ashrdi3 instruction pattern(s). 6133; 6134 6135(define_expand "ashrdi3" 6136 [(parallel 6137 [(set (match_operand:DI 0 "register_operand" "") 6138 (ashiftrt:DI (match_operand:DI 1 "register_operand" "") 6139 (match_operand:SI 2 "shift_count_operand" ""))) 6140 (clobber (reg:CC 33))])] 6141 "" 6142 "") 6143 6144(define_insn "*ashrdi3_cc_31" 6145 [(set (reg 33) 6146 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 6147 (match_operand:SI 2 "shift_count_operand" "Y")) 6148 (const_int 0))) 6149 (set (match_operand:DI 0 "register_operand" "=d") 6150 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 6151 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" 6152 "srda\t%0,%Y2" 6153 [(set_attr "op_type" "RS") 6154 (set_attr "atype" "reg")]) 6155 6156(define_insn "*ashrdi3_cconly_31" 6157 [(set (reg 33) 6158 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 6159 (match_operand:SI 2 "shift_count_operand" "Y")) 6160 (const_int 0))) 6161 (clobber (match_scratch:DI 0 "=d"))] 6162 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" 6163 "srda\t%0,%Y2" 6164 [(set_attr "op_type" "RS") 6165 (set_attr "atype" "reg")]) 6166 6167(define_insn "*ashrdi3_31" 6168 [(set (match_operand:DI 0 "register_operand" "=d") 6169 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 6170 (match_operand:SI 2 "shift_count_operand" "Y"))) 6171 (clobber (reg:CC 33))] 6172 "!TARGET_64BIT" 6173 "srda\t%0,%Y2" 6174 [(set_attr "op_type" "RS") 6175 (set_attr "atype" "reg")]) 6176 6177(define_insn "*ashrdi3_cc_64" 6178 [(set (reg 33) 6179 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") 6180 (match_operand:SI 2 "shift_count_operand" "Y")) 6181 (const_int 0))) 6182 (set (match_operand:DI 0 "register_operand" "=d") 6183 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 6184 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 6185 "srag\t%0,%1,%Y2" 6186 [(set_attr "op_type" "RSE") 6187 (set_attr "atype" "reg")]) 6188 6189(define_insn "*ashrdi3_cconly_64" 6190 [(set (reg 33) 6191 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") 6192 (match_operand:SI 2 "shift_count_operand" "Y")) 6193 (const_int 0))) 6194 (clobber (match_scratch:DI 0 "=d"))] 6195 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 6196 "srag\t%0,%1,%Y2" 6197 [(set_attr "op_type" "RSE") 6198 (set_attr "atype" "reg")]) 6199 6200(define_insn "*ashrdi3_64" 6201 [(set (match_operand:DI 0 "register_operand" "=d") 6202 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") 6203 (match_operand:SI 2 "shift_count_operand" "Y"))) 6204 (clobber (reg:CC 33))] 6205 "TARGET_64BIT" 6206 "srag\t%0,%1,%Y2" 6207 [(set_attr "op_type" "RSE") 6208 (set_attr "atype" "reg")]) 6209 6210 6211; 6212; ashlsi3 instruction pattern(s). 6213; 6214 6215(define_insn "ashlsi3" 6216 [(set (match_operand:SI 0 "register_operand" "=d") 6217 (ashift:SI (match_operand:SI 1 "register_operand" "0") 6218 (match_operand:SI 2 "shift_count_operand" "Y")))] 6219 "" 6220 "sll\t%0,%Y2" 6221 [(set_attr "op_type" "RS") 6222 (set_attr "atype" "reg")]) 6223 6224; 6225; ashrsi3 instruction pattern(s). 6226; 6227 6228(define_insn "*ashrsi3_cc" 6229 [(set (reg 33) 6230 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 6231 (match_operand:SI 2 "shift_count_operand" "Y")) 6232 (const_int 0))) 6233 (set (match_operand:SI 0 "register_operand" "=d") 6234 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 6235 "s390_match_ccmode(insn, CCSmode)" 6236 "sra\t%0,%Y2" 6237 [(set_attr "op_type" "RS") 6238 (set_attr "atype" "reg")]) 6239 6240 6241(define_insn "*ashrsi3_cconly" 6242 [(set (reg 33) 6243 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 6244 (match_operand:SI 2 "shift_count_operand" "Y")) 6245 (const_int 0))) 6246 (clobber (match_scratch:SI 0 "=d"))] 6247 "s390_match_ccmode(insn, CCSmode)" 6248 "sra\t%0,%Y2" 6249 [(set_attr "op_type" "RS") 6250 (set_attr "atype" "reg")]) 6251 6252(define_insn "ashrsi3" 6253 [(set (match_operand:SI 0 "register_operand" "=d") 6254 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 6255 (match_operand:SI 2 "shift_count_operand" "Y"))) 6256 (clobber (reg:CC 33))] 6257 "" 6258 "sra\t%0,%Y2" 6259 [(set_attr "op_type" "RS") 6260 (set_attr "atype" "reg")]) 6261 6262 6263;; 6264;;- logical shift instructions. 6265;; 6266 6267; 6268; lshrdi3 instruction pattern(s). 6269; 6270 6271(define_expand "lshrdi3" 6272 [(set (match_operand:DI 0 "register_operand" "") 6273 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 6274 (match_operand:SI 2 "shift_count_operand" "")))] 6275 "" 6276 "") 6277 6278(define_insn "*lshrdi3_31" 6279 [(set (match_operand:DI 0 "register_operand" "=d") 6280 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") 6281 (match_operand:SI 2 "shift_count_operand" "Y")))] 6282 "!TARGET_64BIT" 6283 "srdl\t%0,%Y2" 6284 [(set_attr "op_type" "RS") 6285 (set_attr "atype" "reg")]) 6286 6287(define_insn "*lshrdi3_64" 6288 [(set (match_operand:DI 0 "register_operand" "=d") 6289 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") 6290 (match_operand:SI 2 "shift_count_operand" "Y")))] 6291 "TARGET_64BIT" 6292 "srlg\t%0,%1,%Y2" 6293 [(set_attr "op_type" "RSE") 6294 (set_attr "atype" "reg")]) 6295 6296; 6297; lshrsi3 instruction pattern(s). 6298; 6299 6300(define_insn "lshrsi3" 6301 [(set (match_operand:SI 0 "register_operand" "=d") 6302 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 6303 (match_operand:SI 2 "shift_count_operand" "Y")))] 6304 "" 6305 "srl\t%0,%Y2" 6306 [(set_attr "op_type" "RS") 6307 (set_attr "atype" "reg")]) 6308 6309 6310;; 6311;; Branch instruction patterns. 6312;; 6313 6314(define_expand "beq" 6315 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) 6316 (set (pc) 6317 (if_then_else (eq (reg:CCZ 33) (const_int 0)) 6318 (label_ref (match_operand 0 "" "")) 6319 (pc)))] 6320 "" 6321 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6322 6323(define_expand "bne" 6324 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) 6325 (set (pc) 6326 (if_then_else (ne (reg:CCZ 33) (const_int 0)) 6327 (label_ref (match_operand 0 "" "")) 6328 (pc)))] 6329 "" 6330 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6331 6332(define_expand "bgt" 6333 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 6334 (set (pc) 6335 (if_then_else (gt (reg:CCS 33) (const_int 0)) 6336 (label_ref (match_operand 0 "" "")) 6337 (pc)))] 6338 "" 6339 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6340 6341(define_expand "bgtu" 6342 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) 6343 (set (pc) 6344 (if_then_else (gtu (reg:CCU 33) (const_int 0)) 6345 (label_ref (match_operand 0 "" "")) 6346 (pc)))] 6347 "" 6348 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6349 6350(define_expand "blt" 6351 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 6352 (set (pc) 6353 (if_then_else (lt (reg:CCS 33) (const_int 0)) 6354 (label_ref (match_operand 0 "" "")) 6355 (pc)))] 6356 "" 6357 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6358 6359(define_expand "bltu" 6360 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) 6361 (set (pc) 6362 (if_then_else (ltu (reg:CCU 33) (const_int 0)) 6363 (label_ref (match_operand 0 "" "")) 6364 (pc)))] 6365 "" 6366 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6367 6368(define_expand "bge" 6369 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 6370 (set (pc) 6371 (if_then_else (ge (reg:CCS 33) (const_int 0)) 6372 (label_ref (match_operand 0 "" "")) 6373 (pc)))] 6374 "" 6375 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6376 6377(define_expand "bgeu" 6378 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) 6379 (set (pc) 6380 (if_then_else (geu (reg:CCU 33) (const_int 0)) 6381 (label_ref (match_operand 0 "" "")) 6382 (pc)))] 6383 "" 6384 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6385 6386(define_expand "ble" 6387 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 6388 (set (pc) 6389 (if_then_else (le (reg:CCS 33) (const_int 0)) 6390 (label_ref (match_operand 0 "" "")) 6391 (pc)))] 6392 "" 6393 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6394 6395(define_expand "bleu" 6396 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) 6397 (set (pc) 6398 (if_then_else (leu (reg:CCU 33) (const_int 0)) 6399 (label_ref (match_operand 0 "" "")) 6400 (pc)))] 6401 "" 6402 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6403 6404(define_expand "bunordered" 6405 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 6406 (set (pc) 6407 (if_then_else (unordered (reg:CCS 33) (const_int 0)) 6408 (label_ref (match_operand 0 "" "")) 6409 (pc)))] 6410 "" 6411 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6412 6413(define_expand "bordered" 6414 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 6415 (set (pc) 6416 (if_then_else (ordered (reg:CCS 33) (const_int 0)) 6417 (label_ref (match_operand 0 "" "")) 6418 (pc)))] 6419 "" 6420 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6421 6422(define_expand "buneq" 6423 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 6424 (set (pc) 6425 (if_then_else (uneq (reg:CCS 33) (const_int 0)) 6426 (label_ref (match_operand 0 "" "")) 6427 (pc)))] 6428 "" 6429 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6430 6431(define_expand "bungt" 6432 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 6433 (set (pc) 6434 (if_then_else (ungt (reg:CCS 33) (const_int 0)) 6435 (label_ref (match_operand 0 "" "")) 6436 (pc)))] 6437 "" 6438 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6439 6440(define_expand "bunlt" 6441 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 6442 (set (pc) 6443 (if_then_else (unlt (reg:CCS 33) (const_int 0)) 6444 (label_ref (match_operand 0 "" "")) 6445 (pc)))] 6446 "" 6447 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6448 6449(define_expand "bunge" 6450 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 6451 (set (pc) 6452 (if_then_else (unge (reg:CCS 33) (const_int 0)) 6453 (label_ref (match_operand 0 "" "")) 6454 (pc)))] 6455 "" 6456 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6457 6458(define_expand "bunle" 6459 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 6460 (set (pc) 6461 (if_then_else (unle (reg:CCS 33) (const_int 0)) 6462 (label_ref (match_operand 0 "" "")) 6463 (pc)))] 6464 "" 6465 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6466 6467(define_expand "bltgt" 6468 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 6469 (set (pc) 6470 (if_then_else (ltgt (reg:CCS 33) (const_int 0)) 6471 (label_ref (match_operand 0 "" "")) 6472 (pc)))] 6473 "" 6474 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") 6475 6476 6477;; 6478;;- Conditional jump instructions. 6479;; 6480 6481(define_insn "cjump" 6482 [(set (pc) 6483 (if_then_else 6484 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) 6485 (label_ref (match_operand 0 "" "")) 6486 (pc)))] 6487 "" 6488{ 6489 if (get_attr_length (insn) == 4) 6490 return "j%C1\t%l0"; 6491 else if (TARGET_CPU_ZARCH) 6492 return "jg%C1\t%l0"; 6493 else 6494 abort (); 6495} 6496 [(set_attr "op_type" "RI") 6497 (set_attr "type" "branch") 6498 (set (attr "length") 6499 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 6500 (const_int 4) 6501 (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) 6502 (const_int 6) 6503 (eq (symbol_ref "flag_pic") (const_int 0)) 6504 (const_int 6)] (const_int 8)))]) 6505 6506(define_insn "*cjump_long" 6507 [(set (pc) 6508 (if_then_else 6509 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) 6510 (match_operand 0 "address_operand" "U") 6511 (pc)))] 6512 "" 6513{ 6514 if (get_attr_op_type (insn) == OP_TYPE_RR) 6515 return "b%C1r\t%0"; 6516 else 6517 return "b%C1\t%a0"; 6518} 6519 [(set (attr "op_type") 6520 (if_then_else (match_operand 0 "register_operand" "") 6521 (const_string "RR") (const_string "RX"))) 6522 (set_attr "type" "branch") 6523 (set_attr "atype" "agen")]) 6524 6525 6526;; 6527;;- Negated conditional jump instructions. 6528;; 6529 6530(define_insn "icjump" 6531 [(set (pc) 6532 (if_then_else 6533 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) 6534 (pc) 6535 (label_ref (match_operand 0 "" ""))))] 6536 "" 6537{ 6538 if (get_attr_length (insn) == 4) 6539 return "j%D1\t%l0"; 6540 else if (TARGET_CPU_ZARCH) 6541 return "jg%D1\t%l0"; 6542 else 6543 abort (); 6544} 6545 [(set_attr "op_type" "RI") 6546 (set_attr "type" "branch") 6547 (set (attr "length") 6548 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 6549 (const_int 4) 6550 (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) 6551 (const_int 6) 6552 (eq (symbol_ref "flag_pic") (const_int 0)) 6553 (const_int 6)] (const_int 8)))]) 6554 6555(define_insn "*icjump_long" 6556 [(set (pc) 6557 (if_then_else 6558 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) 6559 (pc) 6560 (match_operand 0 "address_operand" "U")))] 6561 "" 6562{ 6563 if (get_attr_op_type (insn) == OP_TYPE_RR) 6564 return "b%D1r\t%0"; 6565 else 6566 return "b%D1\t%a0"; 6567} 6568 [(set (attr "op_type") 6569 (if_then_else (match_operand 0 "register_operand" "") 6570 (const_string "RR") (const_string "RX"))) 6571 (set_attr "type" "branch") 6572 (set_attr "atype" "agen")]) 6573 6574;; 6575;;- Trap instructions. 6576;; 6577 6578(define_insn "trap" 6579 [(trap_if (const_int 1) (const_int 0))] 6580 "" 6581 "j\t.+2" 6582 [(set_attr "op_type" "RX") 6583 (set_attr "type" "branch")]) 6584 6585(define_expand "conditional_trap" 6586 [(set (match_dup 2) (match_dup 3)) 6587 (trap_if (match_operator 0 "comparison_operator" 6588 [(match_dup 2) (const_int 0)]) 6589 (match_operand:SI 1 "general_operand" ""))] 6590 "" 6591{ 6592 enum machine_mode ccmode; 6593 6594 if (operands[1] != const0_rtx) FAIL; 6595 6596 ccmode = s390_select_ccmode (GET_CODE (operands[0]), 6597 s390_compare_op0, s390_compare_op1); 6598 operands[2] = gen_rtx_REG (ccmode, 33); 6599 operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1); 6600}) 6601 6602(define_insn "*trap" 6603 [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)]) 6604 (const_int 0))] 6605 "" 6606 "j%C0\t.+2"; 6607 [(set_attr "op_type" "RI") 6608 (set_attr "type" "branch")]) 6609 6610;; 6611;;- Loop instructions. 6612;; 6613;; This is all complicated by the fact that since this is a jump insn 6614;; we must handle our own output reloads. 6615 6616(define_expand "doloop_end" 6617 [(use (match_operand 0 "" "")) ; loop pseudo 6618 (use (match_operand 1 "" "")) ; iterations; zero if unknown 6619 (use (match_operand 2 "" "")) ; max iterations 6620 (use (match_operand 3 "" "")) ; loop level 6621 (use (match_operand 4 "" ""))] ; label 6622 "" 6623{ 6624 if (GET_MODE (operands[0]) == SImode) 6625 emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0])); 6626 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) 6627 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); 6628 else 6629 FAIL; 6630 6631 DONE; 6632}) 6633 6634(define_insn "doloop_si" 6635 [(set (pc) 6636 (if_then_else 6637 (ne (match_operand:SI 1 "register_operand" "d,d") 6638 (const_int 1)) 6639 (label_ref (match_operand 0 "" "")) 6640 (pc))) 6641 (set (match_operand:SI 2 "register_operand" "=1,?*m*d") 6642 (plus:SI (match_dup 1) (const_int -1))) 6643 (clobber (match_scratch:SI 3 "=X,&d")) 6644 (clobber (reg:CC 33))] 6645 "" 6646{ 6647 if (which_alternative != 0) 6648 return "#"; 6649 else if (get_attr_length (insn) == 4) 6650 return "brct\t%1,%l0"; 6651 else if (TARGET_CPU_ZARCH) 6652 return "ahi\t%1,-1\;jgne\t%l0"; 6653 else 6654 abort (); 6655} 6656 [(set_attr "op_type" "RI") 6657 (set_attr "type" "branch") 6658 (set (attr "length") 6659 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 6660 (const_int 4) 6661 (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) 6662 (const_int 10) 6663 (eq (symbol_ref "flag_pic") (const_int 0)) 6664 (const_int 6)] (const_int 8)))]) 6665 6666(define_insn "*doloop_si_long" 6667 [(set (pc) 6668 (if_then_else 6669 (ne (match_operand:SI 1 "register_operand" "d,d") 6670 (const_int 1)) 6671 (match_operand 0 "address_operand" "U,U") 6672 (pc))) 6673 (set (match_operand:SI 2 "register_operand" "=1,?*m*d") 6674 (plus:SI (match_dup 1) (const_int -1))) 6675 (clobber (match_scratch:SI 3 "=X,&d")) 6676 (clobber (reg:CC 33))] 6677 "" 6678{ 6679 if (get_attr_op_type (insn) == OP_TYPE_RR) 6680 return "bctr\t%1,%0"; 6681 else 6682 return "bct\t%1,%a0"; 6683} 6684 [(set (attr "op_type") 6685 (if_then_else (match_operand 0 "register_operand" "") 6686 (const_string "RR") (const_string "RX"))) 6687 (set_attr "type" "branch") 6688 (set_attr "atype" "agen")]) 6689 6690(define_split 6691 [(set (pc) 6692 (if_then_else (ne (match_operand:SI 1 "register_operand" "") 6693 (const_int 1)) 6694 (match_operand 0 "" "") 6695 (pc))) 6696 (set (match_operand:SI 2 "nonimmediate_operand" "") 6697 (plus:SI (match_dup 1) (const_int -1))) 6698 (clobber (match_scratch:SI 3 "")) 6699 (clobber (reg:CC 33))] 6700 "reload_completed 6701 && (! REG_P (operands[2]) 6702 || ! rtx_equal_p (operands[1], operands[2]))" 6703 [(set (match_dup 3) (match_dup 1)) 6704 (parallel [(set (reg:CCAN 33) 6705 (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) 6706 (const_int 0))) 6707 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) 6708 (set (match_dup 2) (match_dup 3)) 6709 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) 6710 (match_dup 0) 6711 (pc)))] 6712 "") 6713 6714(define_insn "doloop_di" 6715 [(set (pc) 6716 (if_then_else 6717 (ne (match_operand:DI 1 "register_operand" "d,d") 6718 (const_int 1)) 6719 (label_ref (match_operand 0 "" "")) 6720 (pc))) 6721 (set (match_operand:DI 2 "register_operand" "=1,?*m*r") 6722 (plus:DI (match_dup 1) (const_int -1))) 6723 (clobber (match_scratch:DI 3 "=X,&d")) 6724 (clobber (reg:CC 33))] 6725 "TARGET_64BIT" 6726{ 6727 if (which_alternative != 0) 6728 return "#"; 6729 else if (get_attr_length (insn) == 4) 6730 return "brctg\t%1,%l0"; 6731 else 6732 return "aghi\t%1,-1\;jgne\t%l0"; 6733} 6734 [(set_attr "op_type" "RI") 6735 (set_attr "type" "branch") 6736 (set (attr "length") 6737 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 6738 (const_int 4) (const_int 10)))]) 6739 6740(define_split 6741 [(set (pc) 6742 (if_then_else (ne (match_operand:DI 1 "register_operand" "") 6743 (const_int 1)) 6744 (match_operand 0 "" "") 6745 (pc))) 6746 (set (match_operand:DI 2 "nonimmediate_operand" "") 6747 (plus:DI (match_dup 1) (const_int -1))) 6748 (clobber (match_scratch:DI 3 "")) 6749 (clobber (reg:CC 33))] 6750 "reload_completed 6751 && (! REG_P (operands[2]) 6752 || ! rtx_equal_p (operands[1], operands[2]))" 6753 [(set (match_dup 3) (match_dup 1)) 6754 (parallel [(set (reg:CCAN 33) 6755 (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) 6756 (const_int 0))) 6757 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) 6758 (set (match_dup 2) (match_dup 3)) 6759 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) 6760 (match_dup 0) 6761 (pc)))] 6762 "") 6763 6764;; 6765;;- Unconditional jump instructions. 6766;; 6767 6768; 6769; jump instruction pattern(s). 6770; 6771 6772(define_insn "jump" 6773 [(set (pc) (label_ref (match_operand 0 "" "")))] 6774 "" 6775{ 6776 if (get_attr_length (insn) == 4) 6777 return "j\t%l0"; 6778 else if (TARGET_CPU_ZARCH) 6779 return "jg\t%l0"; 6780 else 6781 abort (); 6782} 6783 [(set_attr "op_type" "RI") 6784 (set_attr "type" "branch") 6785 (set (attr "length") 6786 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 6787 (const_int 4) 6788 (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) 6789 (const_int 6) 6790 (eq (symbol_ref "flag_pic") (const_int 0)) 6791 (const_int 6)] (const_int 8)))]) 6792 6793; 6794; indirect-jump instruction pattern(s). 6795; 6796 6797(define_insn "indirect_jump" 6798 [(set (pc) (match_operand 0 "address_operand" "U"))] 6799 "" 6800{ 6801 if (get_attr_op_type (insn) == OP_TYPE_RR) 6802 return "br\t%0"; 6803 else 6804 return "b\t%a0"; 6805} 6806 [(set (attr "op_type") 6807 (if_then_else (match_operand 0 "register_operand" "") 6808 (const_string "RR") (const_string "RX"))) 6809 (set_attr "type" "branch") 6810 (set_attr "atype" "agen")]) 6811 6812; 6813; casesi instruction pattern(s). 6814; 6815 6816(define_insn "casesi_jump" 6817 [(set (pc) (match_operand 0 "address_operand" "U")) 6818 (use (label_ref (match_operand 1 "" "")))] 6819 "" 6820{ 6821 if (get_attr_op_type (insn) == OP_TYPE_RR) 6822 return "br\t%0"; 6823 else 6824 return "b\t%a0"; 6825} 6826 [(set (attr "op_type") 6827 (if_then_else (match_operand 0 "register_operand" "") 6828 (const_string "RR") (const_string "RX"))) 6829 (set_attr "type" "branch") 6830 (set_attr "atype" "agen")]) 6831 6832(define_expand "casesi" 6833 [(match_operand:SI 0 "general_operand" "") 6834 (match_operand:SI 1 "general_operand" "") 6835 (match_operand:SI 2 "general_operand" "") 6836 (label_ref (match_operand 3 "" "")) 6837 (label_ref (match_operand 4 "" ""))] 6838 "" 6839{ 6840 rtx index = gen_reg_rtx (SImode); 6841 rtx base = gen_reg_rtx (Pmode); 6842 rtx target = gen_reg_rtx (Pmode); 6843 6844 emit_move_insn (index, operands[0]); 6845 emit_insn (gen_subsi3 (index, index, operands[1])); 6846 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, 6847 operands[4]); 6848 6849 if (Pmode != SImode) 6850 index = convert_to_mode (Pmode, index, 1); 6851 if (GET_CODE (index) != REG) 6852 index = copy_to_mode_reg (Pmode, index); 6853 6854 if (TARGET_64BIT) 6855 emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); 6856 else 6857 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2))); 6858 6859 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); 6860 6861 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index)); 6862 emit_move_insn (target, index); 6863 6864 if (flag_pic) 6865 target = gen_rtx_PLUS (Pmode, base, target); 6866 emit_jump_insn (gen_casesi_jump (target, operands[3])); 6867 6868 DONE; 6869}) 6870 6871 6872;; 6873;;- Jump to subroutine. 6874;; 6875;; 6876 6877; 6878; untyped call instruction pattern(s). 6879; 6880 6881;; Call subroutine returning any type. 6882(define_expand "untyped_call" 6883 [(parallel [(call (match_operand 0 "" "") 6884 (const_int 0)) 6885 (match_operand 1 "" "") 6886 (match_operand 2 "" "")])] 6887 "" 6888{ 6889 int i; 6890 6891 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); 6892 6893 for (i = 0; i < XVECLEN (operands[2], 0); i++) 6894 { 6895 rtx set = XVECEXP (operands[2], 0, i); 6896 emit_move_insn (SET_DEST (set), SET_SRC (set)); 6897 } 6898 6899 /* The optimizer does not know that the call sets the function value 6900 registers we stored in the result block. We avoid problems by 6901 claiming that all hard registers are used and clobbered at this 6902 point. */ 6903 emit_insn (gen_blockage ()); 6904 6905 DONE; 6906}) 6907 6908;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 6909;; all of memory. This blocks insns from being moved across this point. 6910 6911(define_insn "blockage" 6912 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 6913 "" 6914 "" 6915 [(set_attr "type" "none") 6916 (set_attr "length" "0")]) 6917 6918 6919 6920; 6921; call instruction pattern(s). 6922; 6923 6924(define_expand "call" 6925 [(call (match_operand 0 "" "") 6926 (match_operand 1 "" "")) 6927 (use (match_operand 2 "" ""))] 6928 "" 6929{ 6930 bool plt_call = false; 6931 rtx insn; 6932 6933 /* Direct function calls need special treatment. */ 6934 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) 6935 { 6936 rtx sym = XEXP (operands[0], 0); 6937 6938 /* When calling a global routine in PIC mode, we must 6939 replace the symbol itself with the PLT stub. */ 6940 if (flag_pic && !SYMBOL_REF_LOCAL_P (sym)) 6941 { 6942 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); 6943 sym = gen_rtx_CONST (Pmode, sym); 6944 plt_call = true; 6945 } 6946 6947 /* Unless we can use the bras(l) insn, force the 6948 routine address into a register. */ 6949 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) 6950 { 6951 if (flag_pic) 6952 sym = legitimize_pic_address (sym, 0); 6953 else 6954 sym = force_reg (Pmode, sym); 6955 } 6956 6957 operands[0] = gen_rtx_MEM (QImode, sym); 6958 } 6959 6960 /* Emit insn. */ 6961 insn = emit_call_insn (gen_call_exp (operands[0], operands[1], 6962 gen_rtx_REG (Pmode, RETURN_REGNUM))); 6963 6964 /* 31-bit PLT stubs use the GOT register implicitly. */ 6965 if (!TARGET_64BIT && plt_call) 6966 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); 6967 6968 DONE; 6969}) 6970 6971(define_expand "call_exp" 6972 [(parallel [(call (match_operand 0 "" "") 6973 (match_operand 1 "" "")) 6974 (clobber (match_operand 2 "" ""))])] 6975 "" 6976 "") 6977 6978(define_insn "*bras" 6979 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 6980 (match_operand 1 "const_int_operand" "n")) 6981 (clobber (match_operand 2 "register_operand" "=r"))] 6982 "TARGET_SMALL_EXEC && GET_MODE (operands[2]) == Pmode" 6983 "bras\t%2,%0" 6984 [(set_attr "op_type" "RI") 6985 (set_attr "type" "jsr")]) 6986 6987(define_insn "*brasl" 6988 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 6989 (match_operand 1 "const_int_operand" "n")) 6990 (clobber (match_operand 2 "register_operand" "=r"))] 6991 "TARGET_CPU_ZARCH && GET_MODE (operands[2]) == Pmode" 6992 "brasl\t%2,%0" 6993 [(set_attr "op_type" "RIL") 6994 (set_attr "type" "jsr")]) 6995 6996(define_insn "*basr" 6997 [(call (mem:QI (match_operand 0 "address_operand" "U")) 6998 (match_operand 1 "const_int_operand" "n")) 6999 (clobber (match_operand 2 "register_operand" "=r"))] 7000 "GET_MODE (operands[2]) == Pmode" 7001{ 7002 if (get_attr_op_type (insn) == OP_TYPE_RR) 7003 return "basr\t%2,%0"; 7004 else 7005 return "bas\t%2,%a0"; 7006} 7007 [(set (attr "op_type") 7008 (if_then_else (match_operand 0 "register_operand" "") 7009 (const_string "RR") (const_string "RX"))) 7010 (set_attr "type" "jsr") 7011 (set_attr "atype" "agen")]) 7012 7013; 7014; call_value instruction pattern(s). 7015; 7016 7017(define_expand "call_value" 7018 [(set (match_operand 0 "" "") 7019 (call (match_operand 1 "" "") 7020 (match_operand 2 "" ""))) 7021 (use (match_operand 3 "" ""))] 7022 "" 7023{ 7024 bool plt_call = false; 7025 rtx insn; 7026 7027 /* Direct function calls need special treatment. */ 7028 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) 7029 { 7030 rtx sym = XEXP (operands[1], 0); 7031 7032 /* When calling a global routine in PIC mode, we must 7033 replace the symbol itself with the PLT stub. */ 7034 if (flag_pic && !SYMBOL_REF_LOCAL_P (sym)) 7035 { 7036 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); 7037 sym = gen_rtx_CONST (Pmode, sym); 7038 plt_call = true; 7039 } 7040 7041 /* Unless we can use the bras(l) insn, force the 7042 routine address into a register. */ 7043 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) 7044 { 7045 if (flag_pic) 7046 sym = legitimize_pic_address (sym, 0); 7047 else 7048 sym = force_reg (Pmode, sym); 7049 } 7050 7051 operands[1] = gen_rtx_MEM (QImode, sym); 7052 } 7053 7054 /* Emit insn. */ 7055 insn = emit_call_insn ( 7056 gen_call_value_exp (operands[0], operands[1], operands[2], 7057 gen_rtx_REG (Pmode, RETURN_REGNUM))); 7058 7059 /* 31-bit PLT stubs use the GOT register implicitly. */ 7060 if (!TARGET_64BIT && plt_call) 7061 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); 7062 7063 DONE; 7064}) 7065 7066(define_expand "call_value_exp" 7067 [(parallel [(set (match_operand 0 "" "") 7068 (call (match_operand 1 "" "") 7069 (match_operand 2 "" ""))) 7070 (clobber (match_operand 3 "" ""))])] 7071 "" 7072 "") 7073 7074(define_insn "*bras_r" 7075 [(set (match_operand 0 "" "") 7076 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 7077 (match_operand:SI 2 "const_int_operand" "n"))) 7078 (clobber (match_operand 3 "register_operand" "=r"))] 7079 "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode" 7080 "bras\t%3,%1" 7081 [(set_attr "op_type" "RI") 7082 (set_attr "type" "jsr")]) 7083 7084(define_insn "*brasl_r" 7085 [(set (match_operand 0 "" "") 7086 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 7087 (match_operand 2 "const_int_operand" "n"))) 7088 (clobber (match_operand 3 "register_operand" "=r"))] 7089 "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode" 7090 "brasl\t%3,%1" 7091 [(set_attr "op_type" "RIL") 7092 (set_attr "type" "jsr")]) 7093 7094(define_insn "*basr_r" 7095 [(set (match_operand 0 "" "") 7096 (call (mem:QI (match_operand 1 "address_operand" "U")) 7097 (match_operand 2 "const_int_operand" "n"))) 7098 (clobber (match_operand 3 "register_operand" "=r"))] 7099 "GET_MODE (operands[3]) == Pmode" 7100{ 7101 if (get_attr_op_type (insn) == OP_TYPE_RR) 7102 return "basr\t%3,%1"; 7103 else 7104 return "bas\t%3,%a1"; 7105} 7106 [(set (attr "op_type") 7107 (if_then_else (match_operand 1 "register_operand" "") 7108 (const_string "RR") (const_string "RX"))) 7109 (set_attr "type" "jsr") 7110 (set_attr "atype" "agen")]) 7111 7112;; 7113;;- Thread-local storage support. 7114;; 7115 7116(define_insn "get_tp_64" 7117 [(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q") 7118 (unspec:DI [(const_int 0)] UNSPEC_TP))] 7119 "TARGET_64BIT" 7120 "@ 7121 ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1 7122 stam\t%%a0,%%a1,%0" 7123 [(set_attr "op_type" "NN,RS") 7124 (set_attr "atype" "reg,*") 7125 (set_attr "type" "o3,*") 7126 (set_attr "length" "14,*")]) 7127 7128(define_insn "get_tp_31" 7129 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q") 7130 (unspec:SI [(const_int 0)] UNSPEC_TP))] 7131 "!TARGET_64BIT" 7132 "@ 7133 ear\t%0,%%a0 7134 stam\t%%a0,%%a0,%0" 7135 [(set_attr "op_type" "RRE,RS")]) 7136 7137(define_insn "set_tp_64" 7138 [(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP) 7139 (clobber (match_scratch:SI 1 "=d,X"))] 7140 "TARGET_64BIT" 7141 "@ 7142 sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1 7143 lam\t%%a0,%%a1,%0" 7144 [(set_attr "op_type" "NN,RS") 7145 (set_attr "atype" "reg,*") 7146 (set_attr "type" "o3,*") 7147 (set_attr "length" "14,*")]) 7148 7149(define_insn "set_tp_31" 7150 [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)] 7151 "!TARGET_64BIT" 7152 "@ 7153 sar\t%%a0,%0 7154 lam\t%%a0,%%a0,%0" 7155 [(set_attr "op_type" "RRE,RS")]) 7156 7157(define_insn "*tls_load_64" 7158 [(set (match_operand:DI 0 "register_operand" "=d") 7159 (unspec:DI [(match_operand:DI 1 "memory_operand" "m") 7160 (match_operand:DI 2 "" "")] 7161 UNSPEC_TLS_LOAD))] 7162 "TARGET_64BIT" 7163 "lg\t%0,%1%J2" 7164 [(set_attr "op_type" "RXE")]) 7165 7166(define_insn "*tls_load_31" 7167 [(set (match_operand:SI 0 "register_operand" "=d,d") 7168 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") 7169 (match_operand:SI 2 "" "")] 7170 UNSPEC_TLS_LOAD))] 7171 "!TARGET_64BIT" 7172 "@ 7173 l\t%0,%1%J2 7174 ly\t%0,%1%J2" 7175 [(set_attr "op_type" "RX,RXY")]) 7176 7177(define_expand "call_value_tls" 7178 [(set (match_operand 0 "" "") 7179 (call (const_int 0) (const_int 0))) 7180 (use (match_operand 1 "" ""))] 7181 "" 7182{ 7183 rtx insn, sym; 7184 7185 if (!flag_pic) 7186 abort (); 7187 7188 sym = s390_tls_get_offset (); 7189 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); 7190 sym = gen_rtx_CONST (Pmode, sym); 7191 7192 /* Unless we can use the bras(l) insn, force the 7193 routine address into a register. */ 7194 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) 7195 { 7196 if (flag_pic) 7197 sym = legitimize_pic_address (sym, 0); 7198 else 7199 sym = force_reg (Pmode, sym); 7200 } 7201 7202 sym = gen_rtx_MEM (QImode, sym); 7203 7204 /* Emit insn. */ 7205 insn = emit_call_insn ( 7206 gen_call_value_tls_exp (operands[0], sym, const0_rtx, 7207 gen_rtx_REG (Pmode, RETURN_REGNUM), 7208 operands[1])); 7209 7210 /* The calling convention of __tls_get_offset uses the 7211 GOT register implicitly. */ 7212 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); 7213 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), operands[0]); 7214 CONST_OR_PURE_CALL_P (insn) = 1; 7215 7216 DONE; 7217}) 7218 7219(define_expand "call_value_tls_exp" 7220 [(parallel [(set (match_operand 0 "" "") 7221 (call (match_operand 1 "" "") 7222 (match_operand 2 "" ""))) 7223 (clobber (match_operand 3 "" "")) 7224 (use (match_operand 4 "" ""))])] 7225 "" 7226 "") 7227 7228(define_insn "*bras_tls" 7229 [(set (match_operand 0 "" "") 7230 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 7231 (match_operand 2 "const_int_operand" "n"))) 7232 (clobber (match_operand 3 "register_operand" "=r")) 7233 (use (match_operand 4 "" ""))] 7234 "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode" 7235 "bras\t%3,%1%J4" 7236 [(set_attr "op_type" "RI") 7237 (set_attr "type" "jsr")]) 7238 7239(define_insn "*brasl_tls" 7240 [(set (match_operand 0 "" "") 7241 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 7242 (match_operand 2 "const_int_operand" "n"))) 7243 (clobber (match_operand 3 "register_operand" "=r")) 7244 (use (match_operand 4 "" ""))] 7245 "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode" 7246 "brasl\t%3,%1%J4" 7247 [(set_attr "op_type" "RIL") 7248 (set_attr "type" "jsr")]) 7249 7250(define_insn "*basr_tls" 7251 [(set (match_operand 0 "" "") 7252 (call (mem:QI (match_operand 1 "address_operand" "U")) 7253 (match_operand 2 "const_int_operand" "n"))) 7254 (clobber (match_operand 3 "register_operand" "=r")) 7255 (use (match_operand 4 "" ""))] 7256 "GET_MODE (operands[3]) == Pmode" 7257{ 7258 if (get_attr_op_type (insn) == OP_TYPE_RR) 7259 return "basr\t%3,%1%J4"; 7260 else 7261 return "bas\t%3,%a1%J4"; 7262} 7263 [(set (attr "op_type") 7264 (if_then_else (match_operand 1 "register_operand" "") 7265 (const_string "RR") (const_string "RX"))) 7266 (set_attr "type" "jsr") 7267 (set_attr "atype" "agen")]) 7268 7269;; 7270;;- Miscellaneous instructions. 7271;; 7272 7273; 7274; allocate stack instruction pattern(s). 7275; 7276 7277(define_expand "allocate_stack" 7278 [(set (reg 15) 7279 (plus (reg 15) (match_operand 1 "general_operand" ""))) 7280 (set (match_operand 0 "general_operand" "") 7281 (reg 15))] 7282 "TARGET_BACKCHAIN" 7283{ 7284 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM); 7285 rtx chain = gen_rtx (MEM, Pmode, stack); 7286 rtx temp = gen_reg_rtx (Pmode); 7287 7288 emit_move_insn (temp, chain); 7289 7290 if (TARGET_64BIT) 7291 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1]))); 7292 else 7293 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1]))); 7294 7295 emit_move_insn (chain, temp); 7296 7297 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 7298 DONE; 7299}) 7300 7301 7302; 7303; setjmp instruction pattern. 7304; 7305 7306(define_expand "builtin_setjmp_receiver" 7307 [(match_operand 0 "" "")] 7308 "flag_pic" 7309{ 7310 s390_load_got (false); 7311 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); 7312 DONE; 7313}) 7314 7315;; These patterns say how to save and restore the stack pointer. We need not 7316;; save the stack pointer at function level since we are careful to 7317;; preserve the backchain. At block level, we have to restore the backchain 7318;; when we restore the stack pointer. 7319;; 7320;; For nonlocal gotos, we must save both the stack pointer and its 7321;; backchain and restore both. Note that in the nonlocal case, the 7322;; save area is a memory location. 7323 7324(define_expand "save_stack_function" 7325 [(match_operand 0 "general_operand" "") 7326 (match_operand 1 "general_operand" "")] 7327 "" 7328 "DONE;") 7329 7330(define_expand "restore_stack_function" 7331 [(match_operand 0 "general_operand" "") 7332 (match_operand 1 "general_operand" "")] 7333 "" 7334 "DONE;") 7335 7336(define_expand "restore_stack_block" 7337 [(use (match_operand 0 "register_operand" "")) 7338 (set (match_dup 2) (match_dup 3)) 7339 (set (match_dup 0) (match_operand 1 "register_operand" "")) 7340 (set (match_dup 3) (match_dup 2))] 7341 "" 7342{ 7343 operands[2] = gen_reg_rtx (Pmode); 7344 operands[3] = gen_rtx_MEM (Pmode, operands[0]); 7345}) 7346 7347(define_expand "save_stack_nonlocal" 7348 [(match_operand 0 "memory_operand" "") 7349 (match_operand 1 "register_operand" "")] 7350 "" 7351{ 7352 rtx temp = gen_reg_rtx (Pmode); 7353 7354 /* Copy the backchain to the first word, sp to the second and the literal pool 7355 base to the third. */ 7356 emit_move_insn (operand_subword (operands[0], 2, 0, 7357 TARGET_64BIT ? OImode : TImode), 7358 gen_rtx_REG (Pmode, BASE_REGISTER)); 7359 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); 7360 emit_move_insn (operand_subword (operands[0], 0, 0, 7361 TARGET_64BIT ? OImode : TImode), 7362 temp); 7363 emit_move_insn (operand_subword (operands[0], 1, 0, 7364 TARGET_64BIT ? OImode : TImode), 7365 operands[1]); 7366 DONE; 7367}) 7368 7369(define_expand "restore_stack_nonlocal" 7370 [(match_operand 0 "register_operand" "") 7371 (match_operand 1 "memory_operand" "")] 7372 "" 7373{ 7374 rtx temp = gen_reg_rtx (Pmode); 7375 rtx base = gen_rtx_REG (Pmode, BASE_REGISTER); 7376 7377 /* Restore the backchain from the first word, sp from the second and the 7378 literal pool base from the third. */ 7379 emit_move_insn (temp, 7380 operand_subword (operands[1], 0, 0, 7381 TARGET_64BIT ? OImode : TImode)); 7382 emit_move_insn (operands[0], 7383 operand_subword (operands[1], 1, 0, 7384 TARGET_64BIT ? OImode : TImode)); 7385 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); 7386 emit_move_insn (base, 7387 operand_subword (operands[1], 2, 0, 7388 TARGET_64BIT ? OImode : TImode)); 7389 emit_insn (gen_rtx_USE (VOIDmode, base)); 7390 7391 DONE; 7392}) 7393 7394 7395; 7396; nop instruction pattern(s). 7397; 7398 7399(define_insn "nop" 7400 [(const_int 0)] 7401 "" 7402 "lr\t0,0" 7403 [(set_attr "op_type" "RR")]) 7404 7405 7406; 7407; Special literal pool access instruction pattern(s). 7408; 7409 7410(define_insn "*pool_entry" 7411 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] 7412 UNSPECV_POOL_ENTRY)] 7413 "" 7414{ 7415 enum machine_mode mode = GET_MODE (PATTERN (insn)); 7416 unsigned int align = GET_MODE_BITSIZE (mode); 7417 s390_output_pool_entry (asm_out_file, operands[0], mode, align); 7418 return ""; 7419} 7420 [(set_attr "op_type" "NN") 7421 (set (attr "length") 7422 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) 7423 7424(define_insn "pool_start_31" 7425 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] 7426 "!TARGET_CPU_ZARCH" 7427 ".align\t4" 7428 [(set_attr "op_type" "NN") 7429 (set_attr "length" "2")]) 7430 7431(define_insn "pool_end_31" 7432 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] 7433 "!TARGET_CPU_ZARCH" 7434 ".align\t2" 7435 [(set_attr "op_type" "NN") 7436 (set_attr "length" "2")]) 7437 7438(define_insn "pool_start_64" 7439 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] 7440 "TARGET_CPU_ZARCH" 7441 ".section\t.rodata\;.align\t8" 7442 [(set_attr "op_type" "NN") 7443 (set_attr "length" "0")]) 7444 7445(define_insn "pool_end_64" 7446 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] 7447 "TARGET_CPU_ZARCH" 7448 ".previous" 7449 [(set_attr "op_type" "NN") 7450 (set_attr "length" "0")]) 7451 7452(define_insn "main_base_31_small" 7453 [(set (match_operand 0 "register_operand" "=a") 7454 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] 7455 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 7456 "basr\t%0,0" 7457 [(set_attr "op_type" "RR") 7458 (set_attr "type" "la")]) 7459 7460(define_insn "main_base_31_large" 7461 [(set (match_operand 0 "register_operand" "=a") 7462 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) 7463 (set (pc) (label_ref (match_operand 2 "" "")))] 7464 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 7465 "bras\t%0,%2" 7466 [(set_attr "op_type" "RI")]) 7467 7468(define_insn "main_base_64" 7469 [(set (match_operand 0 "register_operand" "=a") 7470 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] 7471 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 7472 "larl\t%0,%1" 7473 [(set_attr "op_type" "RIL") 7474 (set_attr "type" "larl")]) 7475 7476(define_insn "main_pool" 7477 [(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL)] 7478 "" 7479 "* abort ();" 7480 [(set_attr "op_type" "NN")]) 7481 7482(define_insn "reload_base_31" 7483 [(set (match_operand 0 "register_operand" "=a") 7484 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] 7485 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 7486 "basr\t%0,0\;la\t%0,%1-.(%0)" 7487 [(set_attr "op_type" "NN") 7488 (set_attr "type" "la") 7489 (set_attr "length" "6")]) 7490 7491(define_insn "reload_base_64" 7492 [(set (match_operand 0 "register_operand" "=a") 7493 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] 7494 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 7495 "larl\t%0,%1" 7496 [(set_attr "op_type" "RIL") 7497 (set_attr "type" "larl")]) 7498 7499(define_insn "pool" 7500 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] 7501 "" 7502 "* abort ();" 7503 [(set_attr "op_type" "NN") 7504 (set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) 7505 7506;; 7507;; Insns related to generating the function prologue and epilogue. 7508;; 7509 7510 7511(define_expand "prologue" 7512 [(use (const_int 0))] 7513 "" 7514 "s390_emit_prologue (); DONE;") 7515 7516(define_expand "epilogue" 7517 [(use (const_int 1))] 7518 "" 7519 "s390_emit_epilogue (); DONE;") 7520 7521(define_insn "*return" 7522 [(return) 7523 (use (match_operand 0 "register_operand" "a"))] 7524 "GET_MODE (operands[0]) == Pmode" 7525 "br\t%0" 7526 [(set_attr "op_type" "RR") 7527 (set_attr "type" "jsr") 7528 (set_attr "atype" "agen")]) 7529 7530 7531;; Instruction definition to extend a 31-bit pointer into a 64-bit 7532;; pointer. This is used for compatibility. 7533 7534(define_expand "ptr_extend" 7535 [(set (match_operand:DI 0 "register_operand" "=r") 7536 (match_operand:SI 1 "register_operand" "r"))] 7537 "TARGET_64BIT" 7538{ 7539 emit_insn (gen_anddi3 (operands[0], 7540 gen_lowpart (DImode, operands[1]), 7541 GEN_INT (0x7fffffff))); 7542 DONE; 7543}) 7544