s390.md revision 117395
1;;- Machine description for GNU compiler -- S/390 / zSeries version. 2;; Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. 3;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4;; Ulrich Weigand (uweigand@de.ibm.com). 5;; This file is part of GNU CC. 6 7;; GNU CC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 2, or (at your option) 10;; any later version. 11 12;; GNU CC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GNU CC; see the file COPYING. If not, write to 19;; the Free Software Foundation, 59 Temple Place - Suite 330, 20;; Boston, MA 02111-1307, USA. 21 22;; 23;; Special constraints for s/390 machine description: 24;; 25;; a -- Any address register from 1 to 15. 26;; d -- Any register from 0 to 15. 27;; I -- An 8-bit constant (0..255). 28;; J -- A 12-bit constant (0..4095). 29;; K -- A 16-bit constant (-32768..32767). 30;; Q -- A memory reference without index-register. 31;; S -- Valid operand for the LARL instruction. 32;; 33;; Special formats used for outputting 390 instructions. 34;; 35;; %b -- Print a constant byte integer. xy 36;; %h -- Print a signed 16-bit. wxyz 37;; %N -- Print next register (second word of a DImode reg) or next word. 38;; %M -- Print next register (second word of a TImode reg) or next word. 39;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)). 40;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)). 41;; 42;; We have a special constraint for pattern matching. 43;; 44;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. 45;; 46 47;; 48;; UNSPEC usage 49;; 50 51(define_constants 52 [; TLS relocation specifiers 53 (UNSPEC_TLSGD 500) 54 (UNSPEC_TLSLDM 501) 55 (UNSPEC_NTPOFF 502) 56 (UNSPEC_DTPOFF 503) 57 (UNSPEC_GOTNTPOFF 504) 58 (UNSPEC_INDNTPOFF 505) 59 60 ; TLS support 61 (UNSPEC_TP 510) 62 (UNSPEC_TLSLDM_NTPOFF 511) 63 (UNSPEC_TLS_LOAD 512) 64 ]) 65 66;; 67;; UNSPEC_VOLATILE usage 68;; 69 70(define_constants 71 [; TLS support 72 (UNSPECV_SET_TP 500) 73 ]) 74 75 76;; Define an insn type attribute. This is used in function unit delay 77;; computations. 78 79(define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3" 80 (const_string "integer")) 81 82;; Insn are devide in two classes: 83;; mem: Insn accessing memory 84;; reg: Insn operands all in registers 85 86(define_attr "atype" "reg,mem" 87 (const_string "reg")) 88 89;; Generic pipeline function unit. 90 91(define_function_unit "integer" 1 0 92 (eq_attr "type" "none") 0 0) 93 94(define_function_unit "integer" 1 0 95 (eq_attr "type" "integer") 1 1) 96 97(define_function_unit "integer" 1 0 98 (eq_attr "type" "load") 1 1) 99 100(define_function_unit "integer" 1 0 101 (eq_attr "type" "la") 1 1) 102 103(define_function_unit "integer" 1 0 104 (eq_attr "type" "lr") 1 1) 105 106(define_function_unit "integer" 1 0 107 (eq_attr "type" "store") 1 1) 108 109(define_function_unit "integer" 1 0 110 (eq_attr "type" "lm") 2 2) 111 112(define_function_unit "integer" 1 0 113 (eq_attr "type" "stm") 2 2) 114 115(define_function_unit "integer" 1 0 116 (eq_attr "type" "cs") 5 5) 117 118(define_function_unit "integer" 1 0 119 (eq_attr "type" "vs") 30 30) 120 121(define_function_unit "integer" 1 0 122 (eq_attr "type" "jsr") 5 5) 123 124(define_function_unit "integer" 1 0 125 (eq_attr "type" "imul") 7 7) 126 127(define_function_unit "integer" 1 0 128 (eq_attr "type" "fmul") 6 6) 129 130(define_function_unit "integer" 1 0 131 (eq_attr "type" "idiv") 33 33) 132 133(define_function_unit "integer" 1 0 134 (eq_attr "type" "fdiv") 33 33) 135 136(define_function_unit "integer" 1 0 137 (eq_attr "type" "o2") 2 2) 138 139(define_function_unit "integer" 1 0 140 (eq_attr "type" "o3") 3 3) 141 142(define_function_unit "integer" 1 0 143 (eq_attr "type" "other") 5 5) 144 145;; Operand type. Used to default length attribute values 146 147(define_attr "op_type" 148 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE" 149 (const_string "RX")) 150 151;; Length in bytes. 152 153(define_attr "length" "" 154(cond [ (eq_attr "op_type" "E") (const_int 2) 155 (eq_attr "op_type" "RR") (const_int 2) 156 (eq_attr "op_type" "RX") (const_int 4) 157 (eq_attr "op_type" "RI") (const_int 4) 158 (eq_attr "op_type" "RRE") (const_int 4) 159 (eq_attr "op_type" "RS") (const_int 4) 160 (eq_attr "op_type" "RSI") (const_int 4) 161 (eq_attr "op_type" "RX") (const_int 4) 162 (eq_attr "op_type" "S") (const_int 4) 163 (eq_attr "op_type" "SI") (const_int 4) 164 (eq_attr "op_type" "SS") (const_int 6) 165 (eq_attr "op_type" "SSE") (const_int 6) 166 (eq_attr "op_type" "RXE") (const_int 6) 167 (eq_attr "op_type" "RSE") (const_int 6) 168 (eq_attr "op_type" "RIL") (const_int 6)] 169 (const_int 4))) 170 171;; Define attributes for `asm' insns. 172 173(define_asm_attributes [(set_attr "type" "other") 174 (set_attr "op_type" "NN")]) 175 176;; 177;; Condition Codes 178;; 179; 180; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR) 181; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA) 182; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM) 183; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM) 184; CCT: Zero Mixed Mixed Ones (TM, TMH, TML) 185 186; CCZ -> CCL / CCZ1 187; CCZ1 -> CCA/CCU/CCS/CCT 188; CCS -> CCA 189 190; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST 191; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT 192 193 194;; 195;;- Compare instructions. 196;; 197 198(define_expand "cmpdi" 199 [(set (reg:CC 33) 200 (compare:CC (match_operand:DI 0 "register_operand" "") 201 (match_operand:DI 1 "general_operand" "")))] 202 "TARGET_64BIT" 203 " 204{ 205 s390_compare_op0 = operands[0]; 206 s390_compare_op1 = operands[1]; 207 DONE; 208}") 209 210(define_expand "cmpsi" 211 [(set (reg:CC 33) 212 (compare:CC (match_operand:SI 0 "register_operand" "") 213 (match_operand:SI 1 "general_operand" "")))] 214 "" 215 " 216{ 217 s390_compare_op0 = operands[0]; 218 s390_compare_op1 = operands[1]; 219 DONE; 220}") 221 222(define_expand "cmpdf" 223 [(set (reg:CC 33) 224 (compare:CC (match_operand:DF 0 "register_operand" "") 225 (match_operand:DF 1 "general_operand" "")))] 226 "TARGET_HARD_FLOAT" 227 " 228{ 229 s390_compare_op0 = operands[0]; 230 s390_compare_op1 = operands[1]; 231 DONE; 232}") 233 234(define_expand "cmpsf" 235 [(set (reg:CC 33) 236 (compare:CC (match_operand:SF 0 "register_operand" "") 237 (match_operand:SF 1 "general_operand" "")))] 238 "TARGET_HARD_FLOAT" 239 " 240{ 241 s390_compare_op0 = operands[0]; 242 s390_compare_op1 = operands[1]; 243 DONE; 244}") 245 246 247; Test-under-Mask (zero_extract) instructions 248 249(define_insn "*tmdi_ext" 250 [(set (reg 33) 251 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d") 252 (match_operand:DI 1 "const_int_operand" "n") 253 (match_operand:DI 2 "const_int_operand" "n")) 254 (const_int 0)))] 255 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT 256 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 257 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64 258 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 259 == INTVAL (operands[2]) >> 4" 260 "* 261{ 262 int part = INTVAL (operands[2]) >> 4; 263 int block = (1 << INTVAL (operands[1])) - 1; 264 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); 265 266 operands[2] = GEN_INT (block << shift); 267 268 switch (part) 269 { 270 case 0: return \"tmhh\\t%0,%x2\"; 271 case 1: return \"tmhl\\t%0,%x2\"; 272 case 2: return \"tmlh\\t%0,%x2\"; 273 case 3: return \"tmll\\t%0,%x2\"; 274 default: abort (); 275 } 276}" 277 [(set_attr "op_type" "RI")]) 278 279(define_insn "*tmsi_ext" 280 [(set (reg 33) 281 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") 282 (match_operand:SI 1 "const_int_operand" "n") 283 (match_operand:SI 2 "const_int_operand" "n")) 284 (const_int 0)))] 285 "s390_match_ccmode(insn, CCTmode) 286 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 287 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 288 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 289 == INTVAL (operands[2]) >> 4" 290 "* 291{ 292 int part = INTVAL (operands[2]) >> 4; 293 int block = (1 << INTVAL (operands[1])) - 1; 294 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); 295 296 operands[2] = GEN_INT (block << shift); 297 298 switch (part) 299 { 300 case 0: return \"tmh\\t%0,%x2\"; 301 case 1: return \"tml\\t%0,%x2\"; 302 default: abort (); 303 } 304}" 305 [(set_attr "op_type" "RI")]) 306 307(define_insn "*tmqi_ext" 308 [(set (reg 33) 309 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q") 310 (match_operand:SI 1 "const_int_operand" "n") 311 (match_operand:SI 2 "const_int_operand" "n")) 312 (const_int 0)))] 313 "s390_match_ccmode(insn, CCTmode) 314 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 315 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" 316 "* 317{ 318 int block = (1 << INTVAL (operands[1])) - 1; 319 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); 320 321 operands[2] = GEN_INT (block << shift); 322 return \"tm\\t%0,%b2\"; 323}" 324 [(set_attr "op_type" "SI") 325 (set_attr "atype" "mem")]) 326 327; Test-under-Mask instructions 328 329(define_insn "*tmdi_mem" 330 [(set (reg 33) 331 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q") 332 (match_operand:DI 1 "immediate_operand" "n")) 333 (match_operand:DI 2 "immediate_operand" "n")))] 334 "TARGET_64BIT 335 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) 336 && s390_single_qi (operands[1], DImode, 0) >= 0" 337 "* 338{ 339 int part = s390_single_qi (operands[1], DImode, 0); 340 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part)); 341 342 operands[0] = gen_rtx_MEM (QImode, 343 plus_constant (XEXP (operands[0], 0), part)); 344 return \"tm\\t%0,%b1\"; 345}" 346 [(set_attr "op_type" "SI") 347 (set_attr "atype" "mem")]) 348 349(define_insn "*tmsi_mem" 350 [(set (reg 33) 351 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q") 352 (match_operand:SI 1 "immediate_operand" "n")) 353 (match_operand:SI 2 "immediate_operand" "n")))] 354 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) 355 && s390_single_qi (operands[1], SImode, 0) >= 0" 356 "* 357{ 358 int part = s390_single_qi (operands[1], SImode, 0); 359 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part)); 360 361 operands[0] = gen_rtx_MEM (QImode, 362 plus_constant (XEXP (operands[0], 0), part)); 363 return \"tm\\t%0,%b1\"; 364}" 365 [(set_attr "op_type" "SI") 366 (set_attr "atype" "mem")]) 367 368(define_insn "*tmhi_mem" 369 [(set (reg 33) 370 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0) 371 (match_operand:SI 1 "immediate_operand" "n")) 372 (match_operand:SI 2 "immediate_operand" "n")))] 373 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) 374 && s390_single_qi (operands[1], HImode, 0) >= 0" 375 "* 376{ 377 int part = s390_single_qi (operands[1], HImode, 0); 378 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part)); 379 380 operands[0] = gen_rtx_MEM (QImode, 381 plus_constant (XEXP (operands[0], 0), part)); 382 return \"tm\\t%0,%b1\"; 383}" 384 [(set_attr "op_type" "SI") 385 (set_attr "atype" "mem")]) 386 387(define_insn "*tmqi_mem" 388 [(set (reg 33) 389 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0) 390 (match_operand:SI 1 "immediate_operand" "n")) 391 (match_operand:SI 2 "immediate_operand" "n")))] 392 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" 393 "tm\\t%0,%b1" 394 [(set_attr "op_type" "SI") 395 (set_attr "atype" "mem")]) 396 397(define_insn "*tmdi_reg" 398 [(set (reg 33) 399 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d") 400 (match_operand:DI 1 "immediate_operand" "n")) 401 (match_operand:DI 2 "immediate_operand" "n")))] 402 "TARGET_64BIT 403 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) 404 && s390_single_hi (operands[1], DImode, 0) >= 0" 405 "* 406{ 407 int part = s390_single_hi (operands[1], DImode, 0); 408 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part)); 409 410 switch (part) 411 { 412 case 0: return \"tmhh\\t%0,%x1\"; 413 case 1: return \"tmhl\\t%0,%x1\"; 414 case 2: return \"tmlh\\t%0,%x1\"; 415 case 3: return \"tmll\\t%0,%x1\"; 416 default: abort (); 417 } 418}" 419 [(set_attr "op_type" "RI")]) 420 421(define_insn "*tmsi_reg" 422 [(set (reg 33) 423 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d") 424 (match_operand:SI 1 "immediate_operand" "n")) 425 (match_operand:SI 2 "immediate_operand" "n")))] 426 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) 427 && s390_single_hi (operands[1], SImode, 0) >= 0" 428 "* 429{ 430 int part = s390_single_hi (operands[1], SImode, 0); 431 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part)); 432 433 switch (part) 434 { 435 case 0: return \"tmh\\t%0,%x1\"; 436 case 1: return \"tml\\t%0,%x1\"; 437 default: abort (); 438 } 439}" 440 [(set_attr "op_type" "RI")]) 441 442(define_insn "*tmhi_full" 443 [(set (reg 33) 444 (compare (match_operand:HI 0 "register_operand" "d") 445 (match_operand:HI 1 "immediate_operand" "n")))] 446 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))" 447 "tml\\t%0,65535" 448 [(set_attr "op_type" "RX")]) 449 450(define_insn "*tmqi_full" 451 [(set (reg 33) 452 (compare (match_operand:QI 0 "register_operand" "d") 453 (match_operand:QI 1 "immediate_operand" "n")))] 454 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))" 455 "tml\\t%0,255" 456 [(set_attr "op_type" "RI")]) 457 458 459; Load-and-Test instructions 460 461(define_insn "*tstdi_sign" 462 [(set (reg 33) 463 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) 464 (const_int 32)) (const_int 32)) 465 (match_operand:DI 1 "const0_operand" ""))) 466 (set (match_operand:DI 2 "register_operand" "=d") 467 (sign_extend:DI (match_dup 0)))] 468 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 469 "ltgfr\\t%2,%0" 470 [(set_attr "op_type" "RRE")]) 471 472(define_insn "*tstdi" 473 [(set (reg 33) 474 (compare (match_operand:DI 0 "register_operand" "d") 475 (match_operand:DI 1 "const0_operand" ""))) 476 (set (match_operand:DI 2 "register_operand" "=d") 477 (match_dup 0))] 478 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 479 "ltgr\\t%2,%0" 480 [(set_attr "op_type" "RRE")]) 481 482(define_insn "*tstdi_cconly" 483 [(set (reg 33) 484 (compare (match_operand:DI 0 "register_operand" "d") 485 (match_operand:DI 1 "const0_operand" "")))] 486 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 487 "ltgr\\t%0,%0" 488 [(set_attr "op_type" "RRE")]) 489 490(define_insn "*tstdi_cconly_31" 491 [(set (reg 33) 492 (compare (match_operand:DI 0 "register_operand" "d") 493 (match_operand:DI 1 "const0_operand" "")))] 494 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" 495 "srda\\t%0,0" 496 [(set_attr "op_type" "RS")]) 497 498(define_insn "*tstsi" 499 [(set (reg 33) 500 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q") 501 (match_operand:SI 1 "const0_operand" ""))) 502 (set (match_operand:SI 2 "register_operand" "=d,d") 503 (match_dup 0))] 504 "s390_match_ccmode(insn, CCSmode)" 505 "@ 506 ltr\\t%2,%0 507 icm\\t%2,15,%0" 508 [(set_attr "op_type" "RR,RS") 509 (set_attr "atype" "reg,mem")]) 510 511(define_insn "*tstsi_cconly" 512 [(set (reg 33) 513 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q") 514 (match_operand:SI 1 "const0_operand" ""))) 515 (clobber (match_scratch:SI 2 "=X,d"))] 516 "s390_match_ccmode(insn, CCSmode)" 517 "@ 518 ltr\\t%0,%0 519 icm\\t%2,15,%0" 520 [(set_attr "op_type" "RR,RS") 521 (set_attr "atype" "reg,mem")]) 522 523(define_insn "*tstsi_cconly2" 524 [(set (reg 33) 525 (compare (match_operand:SI 0 "register_operand" "d") 526 (match_operand:SI 1 "const0_operand" "")))] 527 "s390_match_ccmode(insn, CCSmode)" 528 "ltr\\t%0,%0" 529 [(set_attr "op_type" "RR")]) 530 531(define_insn "*tsthiCCT" 532 [(set (reg 33) 533 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d") 534 (match_operand:HI 1 "const0_operand" ""))) 535 (set (match_operand:HI 2 "register_operand" "=d,0") 536 (match_dup 0))] 537 "s390_match_ccmode(insn, CCTmode)" 538 "@ 539 icm\\t%2,3,%0 540 tml\\t%0,65535" 541 [(set_attr "op_type" "RS,RI") 542 (set_attr "atype" "mem,reg")]) 543 544(define_insn "*tsthiCCT_cconly" 545 [(set (reg 33) 546 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,d") 547 (match_operand:HI 1 "const0_operand" ""))) 548 (clobber (match_scratch:HI 2 "=d,X"))] 549 "s390_match_ccmode(insn, CCTmode)" 550 "@ 551 icm\\t%2,3,%0 552 tml\\t%0,65535" 553 [(set_attr "op_type" "RS,RI") 554 (set_attr "atype" "mem,reg")]) 555 556(define_insn "*tsthi" 557 [(set (reg 33) 558 (compare (match_operand:HI 0 "s_operand" "Q") 559 (match_operand:HI 1 "const0_operand" ""))) 560 (set (match_operand:HI 2 "register_operand" "=d") 561 (match_dup 0))] 562 "s390_match_ccmode(insn, CCSmode)" 563 "icm\\t%2,3,%0" 564 [(set_attr "op_type" "RS") 565 (set_attr "atype" "mem")]) 566 567(define_insn "*tsthi_cconly" 568 [(set (reg 33) 569 (compare (match_operand:HI 0 "s_operand" "Q") 570 (match_operand:HI 1 "const0_operand" ""))) 571 (clobber (match_scratch:HI 2 "=d"))] 572 "s390_match_ccmode(insn, CCSmode)" 573 "icm\\t%2,3,%0" 574 [(set_attr "op_type" "RS") 575 (set_attr "atype" "mem")]) 576 577(define_insn "*tstqiCCT" 578 [(set (reg 33) 579 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d") 580 (match_operand:QI 1 "const0_operand" ""))) 581 (set (match_operand:QI 2 "register_operand" "=d,0") 582 (match_dup 0))] 583 "s390_match_ccmode(insn, CCTmode)" 584 "@ 585 icm\\t%2,1,%0 586 tml\\t%0,255" 587 [(set_attr "op_type" "RS,RI") 588 (set_attr "atype" "mem,reg")]) 589 590(define_insn "*tstqiCCT_cconly" 591 [(set (reg 33) 592 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d") 593 (match_operand:QI 1 "const0_operand" "")))] 594 "s390_match_ccmode(insn, CCTmode)" 595 "@ 596 cli\\t%0,0 597 tml\\t%0,255" 598 [(set_attr "op_type" "SI,RI") 599 (set_attr "atype" "mem,reg")]) 600 601(define_insn "*tstqi" 602 [(set (reg 33) 603 (compare (match_operand:QI 0 "s_operand" "Q") 604 (match_operand:QI 1 "const0_operand" ""))) 605 (set (match_operand:QI 2 "register_operand" "=d") 606 (match_dup 0))] 607 "s390_match_ccmode(insn, CCSmode)" 608 "icm\\t%2,1,%0" 609 [(set_attr "op_type" "RS") 610 (set_attr "atype" "mem")]) 611 612(define_insn "*tstqi_cconly" 613 [(set (reg 33) 614 (compare (match_operand:QI 0 "s_operand" "Q") 615 (match_operand:QI 1 "const0_operand" ""))) 616 (clobber (match_scratch:QI 2 "=d"))] 617 "s390_match_ccmode(insn, CCSmode)" 618 "icm\\t%2,1,%0" 619 [(set_attr "op_type" "RS") 620 (set_attr "atype" "mem")]) 621 622 623; Compare (signed) instructions 624 625(define_insn "*cmpdi_ccs_sign" 626 [(set (reg 33) 627 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) 628 (match_operand:DI 0 "register_operand" "d,d")))] 629 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" 630 "@ 631 cgfr\\t%0,%1 632 cgf\\t%0,%1" 633 [(set_attr "op_type" "RRE,RXE") 634 (set_attr "atype" "reg,mem")]) 635 636(define_insn "*cmpdi_ccs" 637 [(set (reg 33) 638 (compare (match_operand:DI 0 "register_operand" "d,d,d") 639 (match_operand:DI 1 "general_operand" "d,K,m")))] 640 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 641 "@ 642 cgr\\t%0,%1 643 cghi\\t%0,%c1 644 cg\\t%0,%1" 645 [(set_attr "op_type" "RRE,RI,RXE") 646 (set_attr "atype" "reg,reg,mem")]) 647 648(define_insn "*cmpsi_ccs_sign" 649 [(set (reg 33) 650 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")) 651 (match_operand:SI 0 "register_operand" "d")))] 652 "s390_match_ccmode(insn, CCSRmode)" 653 "ch\\t%0,%1" 654 [(set_attr "op_type" "RX") 655 (set_attr "atype" "mem")]) 656 657(define_insn "*cmpsi_ccs" 658 [(set (reg 33) 659 (compare (match_operand:SI 0 "register_operand" "d,d,d") 660 (match_operand:SI 1 "general_operand" "d,K,m")))] 661 "s390_match_ccmode(insn, CCSmode)" 662 "@ 663 cr\\t%0,%1 664 chi\\t%0,%c1 665 c\\t%0,%1" 666 [(set_attr "op_type" "RR,RI,RX") 667 (set_attr "atype" "reg,reg,mem")]) 668 669 670; Compare (unsigned) instructions 671 672(define_insn "*cmpdi_ccu_zero" 673 [(set (reg 33) 674 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) 675 (match_operand:DI 0 "register_operand" "d,d")))] 676 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT" 677 "@ 678 clgfr\\t%0,%1 679 clgf\\t%0,%1" 680 [(set_attr "op_type" "RRE,RXE") 681 (set_attr "atype" "reg,mem")]) 682 683(define_insn "*cmpdi_ccu" 684 [(set (reg 33) 685 (compare (match_operand:DI 0 "register_operand" "d,d") 686 (match_operand:DI 1 "general_operand" "d,m")))] 687 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT" 688 "@ 689 clgr\\t%0,%1 690 clg\\t%0,%1" 691 [(set_attr "op_type" "RRE,RXE") 692 (set_attr "atype" "reg,mem")]) 693 694(define_insn "*cmpsi_ccu" 695 [(set (reg 33) 696 (compare (match_operand:SI 0 "register_operand" "d,d") 697 (match_operand:SI 1 "general_operand" "d,m")))] 698 "s390_match_ccmode(insn, CCUmode)" 699 "@ 700 clr\\t%0,%1 701 cl\\t%0,%1" 702 [(set_attr "op_type" "RR,RX") 703 (set_attr "atype" "reg,mem")]) 704 705(define_insn "*cmphi_ccu" 706 [(set (reg 33) 707 (compare (match_operand:HI 0 "register_operand" "d") 708 (match_operand:HI 1 "s_imm_operand" "Q")))] 709 "s390_match_ccmode(insn, CCUmode)" 710 "clm\\t%0,3,%1" 711 [(set_attr "op_type" "RS") 712 (set_attr "atype" "mem")]) 713 714(define_insn "*cmpqi_ccu" 715 [(set (reg 33) 716 (compare (match_operand:QI 0 "register_operand" "d") 717 (match_operand:QI 1 "s_imm_operand" "Q")))] 718 "s390_match_ccmode(insn, CCUmode)" 719 "clm\\t%0,1,%1" 720 [(set_attr "op_type" "RS") 721 (set_attr "atype" "mem")]) 722 723(define_insn "*cli" 724 [(set (reg 33) 725 (compare (match_operand:QI 0 "memory_operand" "Q") 726 (match_operand:QI 1 "immediate_operand" "n")))] 727 "s390_match_ccmode (insn, CCUmode)" 728 "cli\\t%0,%b1" 729 [(set_attr "op_type" "SI") 730 (set_attr "atype" "mem")]) 731 732(define_insn "*cmpdi_ccu_mem" 733 [(set (reg 33) 734 (compare (match_operand:DI 0 "s_operand" "Q") 735 (match_operand:DI 1 "s_imm_operand" "Q")))] 736 "s390_match_ccmode(insn, CCUmode)" 737 "clc\\t%O0(8,%R0),%1" 738 [(set_attr "op_type" "SS") 739 (set_attr "atype" "mem")]) 740 741(define_insn "*cmpsi_ccu_mem" 742 [(set (reg 33) 743 (compare (match_operand:SI 0 "s_operand" "Q") 744 (match_operand:SI 1 "s_imm_operand" "Q")))] 745 "s390_match_ccmode(insn, CCUmode)" 746 "clc\\t%O0(4,%R0),%1" 747 [(set_attr "op_type" "SS") 748 (set_attr "atype" "mem")]) 749 750(define_insn "*cmphi_ccu_mem" 751 [(set (reg 33) 752 (compare (match_operand:HI 0 "s_operand" "Q") 753 (match_operand:HI 1 "s_imm_operand" "Q")))] 754 "s390_match_ccmode(insn, CCUmode)" 755 "clc\\t%O0(2,%R0),%1" 756 [(set_attr "op_type" "SS") 757 (set_attr "atype" "mem")]) 758 759(define_insn "*cmpqi_ccu_mem" 760 [(set (reg 33) 761 (compare (match_operand:QI 0 "s_operand" "Q") 762 (match_operand:QI 1 "s_imm_operand" "Q")))] 763 "s390_match_ccmode(insn, CCUmode)" 764 "clc\\t%O0(1,%R0),%1" 765 [(set_attr "op_type" "SS") 766 (set_attr "atype" "mem")]) 767 768 769; DF instructions 770 771(define_insn "*cmpdf_ccs_0" 772 [(set (reg 33) 773 (compare (match_operand:DF 0 "register_operand" "f") 774 (match_operand:DF 1 "const0_operand" "")))] 775 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 776 "ltdbr\\t%0,%0" 777 [(set_attr "op_type" "RRE")]) 778 779(define_insn "*cmpdf_ccs_0_ibm" 780 [(set (reg 33) 781 (compare (match_operand:DF 0 "register_operand" "f") 782 (match_operand:DF 1 "const0_operand" "")))] 783 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 784 "ltdr\\t%0,%0" 785 [(set_attr "op_type" "RR")]) 786 787(define_insn "*cmpdf_ccs" 788 [(set (reg 33) 789 (compare (match_operand:DF 0 "register_operand" "f,f") 790 (match_operand:DF 1 "general_operand" "f,m")))] 791 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 792 "@ 793 cdbr\\t%0,%1 794 cdb\\t%0,%1" 795 [(set_attr "op_type" "RRE,RXE") 796 (set_attr "atype" "reg,mem")]) 797 798(define_insn "*cmpdf_ccs_ibm" 799 [(set (reg 33) 800 (compare (match_operand:DF 0 "register_operand" "f,f") 801 (match_operand:DF 1 "general_operand" "f,m")))] 802 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 803 "@ 804 cdr\\t%0,%1 805 cd\\t%0,%1" 806 [(set_attr "op_type" "RR,RX") 807 (set_attr "atype" "reg,mem")]) 808 809 810; SF instructions 811 812(define_insn "*cmpsf_ccs_0" 813 [(set (reg 33) 814 (compare (match_operand:SF 0 "register_operand" "f") 815 (match_operand:SF 1 "const0_operand" "")))] 816 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 817 "ltebr\\t%0,%0" 818 [(set_attr "op_type" "RRE")]) 819 820(define_insn "*cmpsf_ccs_0_ibm" 821 [(set (reg 33) 822 (compare (match_operand:SF 0 "register_operand" "f") 823 (match_operand:SF 1 "const0_operand" "")))] 824 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 825 "lter\\t%0,%0" 826 [(set_attr "op_type" "RR")]) 827 828(define_insn "*cmpsf_ccs" 829 [(set (reg 33) 830 (compare (match_operand:SF 0 "register_operand" "f,f") 831 (match_operand:SF 1 "general_operand" "f,m")))] 832 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 833 "@ 834 cebr\\t%0,%1 835 ceb\\t%0,%1" 836 [(set_attr "op_type" "RRE,RXE") 837 (set_attr "atype" "reg,mem")]) 838 839(define_insn "*cmpsf_ccs" 840 [(set (reg 33) 841 (compare (match_operand:SF 0 "register_operand" "f,f") 842 (match_operand:SF 1 "general_operand" "f,m")))] 843 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 844 "@ 845 cer\\t%0,%1 846 ce\\t%0,%1" 847 [(set_attr "op_type" "RR,RX") 848 (set_attr "atype" "reg,mem")]) 849 850 851;; 852;;- Move instructions. 853;; 854 855; 856; movti instruction pattern(s). 857; 858 859(define_insn "movti" 860 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,o,Q") 861 (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))] 862 "TARGET_64BIT" 863 "@ 864 lmg\\t%0,%N0,%1 865 stmg\\t%1,%N1,%0 866 # 867 # 868 mvc\\t%O0(16,%R0),%1" 869 [(set_attr "op_type" "RSE,RSE,NN,NN,SS") 870 (set_attr "atype" "mem")]) 871 872(define_split 873 [(set (match_operand:TI 0 "nonimmediate_operand" "") 874 (match_operand:TI 1 "general_operand" ""))] 875 "TARGET_64BIT && reload_completed 876 && s390_split_ok_p (operands[0], operands[1], TImode, 0)" 877 [(set (match_dup 2) (match_dup 4)) 878 (set (match_dup 3) (match_dup 5))] 879{ 880 operands[2] = operand_subword (operands[0], 0, 0, TImode); 881 operands[3] = operand_subword (operands[0], 1, 0, TImode); 882 operands[4] = operand_subword (operands[1], 0, 0, TImode); 883 operands[5] = operand_subword (operands[1], 1, 0, TImode); 884}) 885 886(define_split 887 [(set (match_operand:TI 0 "nonimmediate_operand" "") 888 (match_operand:TI 1 "general_operand" ""))] 889 "TARGET_64BIT && reload_completed 890 && s390_split_ok_p (operands[0], operands[1], TImode, 1)" 891 [(set (match_dup 2) (match_dup 4)) 892 (set (match_dup 3) (match_dup 5))] 893{ 894 operands[2] = operand_subword (operands[0], 1, 0, TImode); 895 operands[3] = operand_subword (operands[0], 0, 0, TImode); 896 operands[4] = operand_subword (operands[1], 1, 0, TImode); 897 operands[5] = operand_subword (operands[1], 0, 0, TImode); 898}) 899 900(define_split 901 [(set (match_operand:TI 0 "register_operand" "") 902 (match_operand:TI 1 "memory_operand" ""))] 903 "TARGET_64BIT && reload_completed 904 && !s_operand (operands[1], VOIDmode)" 905 [(set (match_dup 0) (match_dup 1))] 906{ 907 rtx addr = operand_subword (operands[0], 1, 0, TImode); 908 s390_load_address (addr, XEXP (operands[1], 0)); 909 operands[1] = replace_equiv_address (operands[1], addr); 910}) 911 912(define_expand "reload_outti" 913 [(parallel [(match_operand:TI 0 "memory_operand" "") 914 (match_operand:TI 1 "register_operand" "d") 915 (match_operand:DI 2 "register_operand" "=&a")])] 916 "TARGET_64BIT" 917{ 918 s390_load_address (operands[2], XEXP (operands[0], 0)); 919 operands[0] = replace_equiv_address (operands[0], operands[2]); 920 emit_move_insn (operands[0], operands[1]); 921 DONE; 922}) 923 924; 925; movdi instruction pattern(s). 926; 927 928(define_expand "movdi" 929 [(set (match_operand:DI 0 "general_operand" "") 930 (match_operand:DI 1 "general_operand" ""))] 931 "" 932 " 933{ 934 /* Handle symbolic constants. */ 935 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) 936 emit_symbolic_move (operands); 937 938 /* During and after reload, we need to force constants 939 to the literal pool ourselves, if necessary. */ 940 if ((reload_in_progress || reload_completed) 941 && CONSTANT_P (operands[1]) 942 && (!legitimate_reload_constant_p (operands[1]) 943 || FP_REG_P (operands[0]))) 944 operands[1] = force_const_mem (DImode, operands[1]); 945}") 946 947(define_insn "*movdi_lhi" 948 [(set (match_operand:DI 0 "register_operand" "=d") 949 (match_operand:DI 1 "immediate_operand" "K"))] 950 "TARGET_64BIT 951 && GET_CODE (operands[1]) == CONST_INT 952 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') 953 && !FP_REG_P (operands[0])" 954 "lghi\\t%0,%h1" 955 [(set_attr "op_type" "RI") 956 (set_attr "atype" "reg")]) 957 958(define_insn "*movdi_lli" 959 [(set (match_operand:DI 0 "register_operand" "=d") 960 (match_operand:DI 1 "immediate_operand" "n"))] 961 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0 962 && !FP_REG_P (operands[0])" 963 "* 964{ 965 int part = s390_single_hi (operands[1], DImode, 0); 966 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part)); 967 968 switch (part) 969 { 970 case 0: return \"llihh\\t%0,%x1\"; 971 case 1: return \"llihl\\t%0,%x1\"; 972 case 2: return \"llilh\\t%0,%x1\"; 973 case 3: return \"llill\\t%0,%x1\"; 974 default: abort (); 975 } 976}" 977 [(set_attr "op_type" "RI") 978 (set_attr "atype" "reg")]) 979 980(define_insn "*movdi_larl" 981 [(set (match_operand:DI 0 "register_operand" "=d") 982 (match_operand:DI 1 "larl_operand" "X"))] 983 "TARGET_64BIT 984 && !FP_REG_P (operands[0])" 985 "larl\\t%0,%1" 986 [(set_attr "op_type" "RIL") 987 (set_attr "atype" "reg") 988 (set_attr "type" "la")]) 989 990(define_insn "*movdi_64" 991 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q") 992 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))] 993 "TARGET_64BIT" 994 "@ 995 lgr\\t%0,%1 996 lg\\t%0,%1 997 stg\\t%1,%0 998 ldr\\t%0,%1 999 ld\\t%0,%1 1000 std\\t%1,%0 1001 mvc\\t%O0(8,%R0),%1" 1002 [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS") 1003 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")]) 1004 1005(define_insn "*movdi_31" 1006 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!m,Q") 1007 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))] 1008 "!TARGET_64BIT" 1009 "@ 1010 lm\\t%0,%N0,%1 1011 stm\\t%1,%N1,%0 1012 # 1013 # 1014 ldr\\t%0,%1 1015 ld\\t%0,%1 1016 std\\t%1,%0 1017 mvc\\t%O0(8,%R0),%1" 1018 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS") 1019 (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")]) 1020 1021(define_split 1022 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1023 (match_operand:DI 1 "general_operand" ""))] 1024 "!TARGET_64BIT && reload_completed 1025 && s390_split_ok_p (operands[0], operands[1], DImode, 0)" 1026 [(set (match_dup 2) (match_dup 4)) 1027 (set (match_dup 3) (match_dup 5))] 1028{ 1029 operands[2] = operand_subword (operands[0], 0, 0, DImode); 1030 operands[3] = operand_subword (operands[0], 1, 0, DImode); 1031 operands[4] = operand_subword (operands[1], 0, 0, DImode); 1032 operands[5] = operand_subword (operands[1], 1, 0, DImode); 1033}) 1034 1035(define_split 1036 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1037 (match_operand:DI 1 "general_operand" ""))] 1038 "!TARGET_64BIT && reload_completed 1039 && s390_split_ok_p (operands[0], operands[1], DImode, 1)" 1040 [(set (match_dup 2) (match_dup 4)) 1041 (set (match_dup 3) (match_dup 5))] 1042{ 1043 operands[2] = operand_subword (operands[0], 1, 0, DImode); 1044 operands[3] = operand_subword (operands[0], 0, 0, DImode); 1045 operands[4] = operand_subword (operands[1], 1, 0, DImode); 1046 operands[5] = operand_subword (operands[1], 0, 0, DImode); 1047}) 1048 1049(define_split 1050 [(set (match_operand:DI 0 "register_operand" "") 1051 (match_operand:DI 1 "memory_operand" ""))] 1052 "!TARGET_64BIT && reload_completed 1053 && !FP_REG_P (operands[0]) 1054 && !s_operand (operands[1], VOIDmode)" 1055 [(set (match_dup 0) (match_dup 1))] 1056{ 1057 rtx addr = operand_subword (operands[0], 1, 0, DImode); 1058 s390_load_address (addr, XEXP (operands[1], 0)); 1059 operands[1] = replace_equiv_address (operands[1], addr); 1060}) 1061 1062(define_expand "reload_outdi" 1063 [(parallel [(match_operand:DI 0 "memory_operand" "") 1064 (match_operand:DI 1 "register_operand" "d") 1065 (match_operand:SI 2 "register_operand" "=&a")])] 1066 "!TARGET_64BIT" 1067{ 1068 s390_load_address (operands[2], XEXP (operands[0], 0)); 1069 operands[0] = replace_equiv_address (operands[0], operands[2]); 1070 emit_move_insn (operands[0], operands[1]); 1071 DONE; 1072}) 1073 1074(define_peephole2 1075 [(set (match_operand:DI 0 "register_operand" "") 1076 (mem:DI (match_operand 1 "address_operand" "")))] 1077 "TARGET_64BIT 1078 && !FP_REG_P (operands[0]) 1079 && GET_CODE (operands[1]) == SYMBOL_REF 1080 && CONSTANT_POOL_ADDRESS_P (operands[1]) 1081 && get_pool_mode (operands[1]) == DImode 1082 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" 1083 [(set (match_dup 0) (match_dup 2))] 1084 "operands[2] = get_pool_constant (operands[1]);") 1085 1086; 1087; movsi instruction pattern(s). 1088; 1089 1090(define_expand "movsi" 1091 [(set (match_operand:SI 0 "general_operand" "") 1092 (match_operand:SI 1 "general_operand" ""))] 1093 "" 1094 " 1095{ 1096 /* Handle symbolic constants. */ 1097 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) 1098 emit_symbolic_move (operands); 1099 1100 /* expr.c tries to load an effective address using 1101 force_reg. This fails because we don't have a 1102 generic load_address pattern. Convert the move 1103 to a proper arithmetic operation instead, unless 1104 it is guaranteed to be OK. */ 1105 if (GET_CODE (operands[1]) == PLUS 1106 && !legitimate_la_operand_p (operands[1])) 1107 { 1108 operands[1] = force_operand (operands[1], operands[0]); 1109 if (operands[1] == operands[0]) 1110 DONE; 1111 } 1112 1113 /* During and after reload, we need to force constants 1114 to the literal pool ourselves, if necessary. */ 1115 if ((reload_in_progress || reload_completed) 1116 && CONSTANT_P (operands[1]) 1117 && (!legitimate_reload_constant_p (operands[1]) 1118 || FP_REG_P (operands[0]))) 1119 operands[1] = force_const_mem (SImode, operands[1]); 1120}") 1121 1122(define_insn "*movsi_lhi" 1123 [(set (match_operand:SI 0 "register_operand" "=d") 1124 (match_operand:SI 1 "immediate_operand" "K"))] 1125 "GET_CODE (operands[1]) == CONST_INT 1126 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') 1127 && !FP_REG_P (operands[0])" 1128 "lhi\\t%0,%h1" 1129 [(set_attr "op_type" "RI")]) 1130 1131(define_insn "*movsi_lli" 1132 [(set (match_operand:SI 0 "register_operand" "=d") 1133 (match_operand:SI 1 "immediate_operand" "n"))] 1134 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0 1135 && !FP_REG_P (operands[0])" 1136 "* 1137{ 1138 int part = s390_single_hi (operands[1], SImode, 0); 1139 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part)); 1140 1141 switch (part) 1142 { 1143 case 0: return \"llilh\\t%0,%x1\"; 1144 case 1: return \"llill\\t%0,%x1\"; 1145 default: abort (); 1146 } 1147}" 1148 [(set_attr "op_type" "RI")]) 1149 1150(define_insn "*movsi" 1151 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q") 1152 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))] 1153 "" 1154 "@ 1155 lr\\t%0,%1 1156 l\\t%0,%1 1157 st\\t%1,%0 1158 ler\\t%0,%1 1159 le\\t%0,%1 1160 ste\\t%1,%0 1161 mvc\\t%O0(4,%R0),%1" 1162 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS") 1163 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")]) 1164 1165(define_peephole2 1166 [(set (match_operand:SI 0 "register_operand" "") 1167 (mem:SI (match_operand 1 "address_operand" "")))] 1168 "!FP_REG_P (operands[0]) 1169 && GET_CODE (operands[1]) == SYMBOL_REF 1170 && CONSTANT_POOL_ADDRESS_P (operands[1]) 1171 && get_pool_mode (operands[1]) == SImode 1172 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" 1173 [(set (match_dup 0) (match_dup 2))] 1174 "operands[2] = get_pool_constant (operands[1]);") 1175 1176; 1177; movhi instruction pattern(s). 1178; 1179 1180(define_insn "movhi" 1181 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,?Q") 1182 (match_operand:HI 1 "general_operand" "d,n,m,d,?Q"))] 1183 "" 1184 "@ 1185 lr\\t%0,%1 1186 lhi\\t%0,%h1 1187 lh\\t%0,%1 1188 sth\\t%1,%0 1189 mvc\\t%O0(2,%R0),%1" 1190 [(set_attr "op_type" "RR,RI,RX,RX,SS") 1191 (set_attr "atype" "reg,reg,mem,mem,mem")]) 1192 1193(define_peephole2 1194 [(set (match_operand:HI 0 "register_operand" "") 1195 (mem:HI (match_operand 1 "address_operand" "")))] 1196 "GET_CODE (operands[1]) == SYMBOL_REF 1197 && CONSTANT_POOL_ADDRESS_P (operands[1]) 1198 && get_pool_mode (operands[1]) == HImode 1199 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" 1200 [(set (match_dup 0) (match_dup 2))] 1201 "operands[2] = get_pool_constant (operands[1]);") 1202 1203; 1204; movqi instruction pattern(s). 1205; 1206 1207(define_insn "movqi_64" 1208 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q") 1209 (match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))] 1210 "TARGET_64BIT" 1211 "@ 1212 lr\\t%0,%1 1213 lhi\\t%0,%b1 1214 llgc\\t%0,%1 1215 stc\\t%1,%0 1216 mvi\\t%0,%b1 1217 mvc\\t%O0(1,%R0),%1" 1218 [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS") 1219 (set_attr "atype" "reg,reg,mem,mem,mem,mem")]) 1220 1221 1222(define_insn "movqi" 1223 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q") 1224 (match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))] 1225 "" 1226 "@ 1227 lr\\t%0,%1 1228 lhi\\t%0,%b1 1229 ic\\t%0,%1 1230 stc\\t%1,%0 1231 mvi\\t%0,%b1 1232 mvc\\t%O0(1,%R0),%1" 1233 [(set_attr "op_type" "RR,RI,RX,RX,SI,SS") 1234 (set_attr "atype" "reg,reg,mem,mem,mem,mem")]) 1235 1236(define_peephole2 1237 [(set (match_operand:QI 0 "nonimmediate_operand" "") 1238 (mem:QI (match_operand 1 "address_operand" "")))] 1239 "GET_CODE (operands[1]) == SYMBOL_REF 1240 && CONSTANT_POOL_ADDRESS_P (operands[1]) 1241 && get_pool_mode (operands[1]) == QImode 1242 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" 1243 [(set (match_dup 0) (match_dup 2))] 1244 "operands[2] = get_pool_constant (operands[1]);") 1245 1246; 1247; movstrictqi instruction pattern(s). 1248; 1249 1250(define_insn "*movstrictqi" 1251 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 1252 (match_operand:QI 1 "memory_operand" "m"))] 1253 "" 1254 "ic\\t%0,%1" 1255 [(set_attr "op_type" "RX") 1256 (set_attr "atype" "mem")]) 1257 1258; 1259; movstricthi instruction pattern(s). 1260; 1261 1262(define_insn "*movstricthi" 1263 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 1264 (match_operand:HI 1 "s_imm_operand" "Q")) 1265 (clobber (reg:CC 33))] 1266 "" 1267 "icm\\t%0,3,%1" 1268 [(set_attr "op_type" "RS") 1269 (set_attr "atype" "mem")]) 1270 1271 1272; 1273; movstrictsi instruction pattern(s). 1274; 1275 1276(define_insn "movstrictsi" 1277 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d")) 1278 (match_operand:SI 1 "general_operand" "d,m"))] 1279 "TARGET_64BIT" 1280 "@ 1281 lr\\t%0,%1 1282 l\\t%0,%1" 1283 [(set_attr "op_type" "RR,RS") 1284 (set_attr "atype" "reg,mem")]) 1285 1286 1287; 1288; movdf instruction pattern(s). 1289; 1290 1291(define_expand "movdf" 1292 [(set (match_operand:DF 0 "nonimmediate_operand" "") 1293 (match_operand:DF 1 "general_operand" ""))] 1294 "" 1295 " 1296{ 1297 /* During and after reload, we need to force constants 1298 to the literal pool ourselves, if necessary. */ 1299 if ((reload_in_progress || reload_completed) 1300 && CONSTANT_P (operands[1])) 1301 operands[1] = force_const_mem (DFmode, operands[1]); 1302}") 1303 1304(define_insn "*movdf_64" 1305 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q") 1306 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,?Q"))] 1307 "TARGET_64BIT" 1308 "@ 1309 ldr\\t%0,%1 1310 ld\\t%0,%1 1311 std\\t%1,%0 1312 lgr\\t%0,%1 1313 lg\\t%0,%1 1314 stg\\t%1,%0 1315 mvc\\t%O0(8,%R0),%1" 1316 [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS") 1317 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")]) 1318 1319(define_insn "*movdf_31" 1320 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,o,Q") 1321 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))] 1322 "!TARGET_64BIT" 1323 "@ 1324 ldr\\t%0,%1 1325 ld\\t%0,%1 1326 std\\t%1,%0 1327 lm\\t%0,%N0,%1 1328 stm\\t%1,%N1,%0 1329 # 1330 # 1331 mvc\\t%O0(8,%R0),%1" 1332 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS") 1333 (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")]) 1334 1335(define_split 1336 [(set (match_operand:DF 0 "nonimmediate_operand" "") 1337 (match_operand:DF 1 "general_operand" ""))] 1338 "!TARGET_64BIT && reload_completed 1339 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" 1340 [(set (match_dup 2) (match_dup 4)) 1341 (set (match_dup 3) (match_dup 5))] 1342{ 1343 operands[2] = operand_subword (operands[0], 0, 0, DFmode); 1344 operands[3] = operand_subword (operands[0], 1, 0, DFmode); 1345 operands[4] = operand_subword (operands[1], 0, 0, DFmode); 1346 operands[5] = operand_subword (operands[1], 1, 0, DFmode); 1347}) 1348 1349(define_split 1350 [(set (match_operand:DF 0 "nonimmediate_operand" "") 1351 (match_operand:DF 1 "general_operand" ""))] 1352 "!TARGET_64BIT && reload_completed 1353 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" 1354 [(set (match_dup 2) (match_dup 4)) 1355 (set (match_dup 3) (match_dup 5))] 1356{ 1357 operands[2] = operand_subword (operands[0], 1, 0, DFmode); 1358 operands[3] = operand_subword (operands[0], 0, 0, DFmode); 1359 operands[4] = operand_subword (operands[1], 1, 0, DFmode); 1360 operands[5] = operand_subword (operands[1], 0, 0, DFmode); 1361}) 1362 1363(define_split 1364 [(set (match_operand:DF 0 "register_operand" "") 1365 (match_operand:DF 1 "memory_operand" ""))] 1366 "!TARGET_64BIT && reload_completed 1367 && !FP_REG_P (operands[0]) 1368 && !s_operand (operands[1], VOIDmode)" 1369 [(set (match_dup 0) (match_dup 1))] 1370{ 1371 rtx addr = operand_subword (operands[0], 1, 0, DFmode); 1372 s390_load_address (addr, XEXP (operands[1], 0)); 1373 operands[1] = replace_equiv_address (operands[1], addr); 1374}) 1375 1376(define_expand "reload_outdf" 1377 [(parallel [(match_operand:DF 0 "memory_operand" "") 1378 (match_operand:DF 1 "register_operand" "d") 1379 (match_operand:SI 2 "register_operand" "=&a")])] 1380 "!TARGET_64BIT" 1381{ 1382 s390_load_address (operands[2], XEXP (operands[0], 0)); 1383 operands[0] = replace_equiv_address (operands[0], operands[2]); 1384 emit_move_insn (operands[0], operands[1]); 1385 DONE; 1386}) 1387 1388; 1389; movsf instruction pattern(s). 1390; 1391 1392(define_expand "movsf" 1393 [(set (match_operand:SF 0 "nonimmediate_operand" "") 1394 (match_operand:SF 1 "general_operand" ""))] 1395 "" 1396 " 1397{ 1398 /* During and after reload, we need to force constants 1399 to the literal pool ourselves, if necessary. */ 1400 if ((reload_in_progress || reload_completed) 1401 && CONSTANT_P (operands[1])) 1402 operands[1] = force_const_mem (SFmode, operands[1]); 1403}") 1404 1405(define_insn "*movsf" 1406 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q") 1407 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,?Q"))] 1408 "" 1409 "@ 1410 ler\\t%0,%1 1411 le\\t%0,%1 1412 ste\\t%1,%0 1413 lr\\t%0,%1 1414 l\\t%0,%1 1415 st\\t%1,%0 1416 mvc\\t%O0(4,%R0),%1" 1417 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS") 1418 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")]) 1419 1420; 1421; load_multiple pattern(s). 1422; 1423 1424(define_expand "load_multiple" 1425 [(match_par_dup 3 [(set (match_operand 0 "" "") 1426 (match_operand 1 "" "")) 1427 (use (match_operand 2 "" ""))])] 1428 "" 1429 " 1430{ 1431 int regno; 1432 int count; 1433 rtx from; 1434 int i, off; 1435 1436 /* Support only loading a constant number of fixed-point registers from 1437 memory and only bother with this if more than two */ 1438 if (GET_CODE (operands[2]) != CONST_INT 1439 || INTVAL (operands[2]) < 2 1440 || INTVAL (operands[2]) > 16 1441 || GET_CODE (operands[1]) != MEM 1442 || GET_CODE (operands[0]) != REG 1443 || REGNO (operands[0]) >= 16) 1444 FAIL; 1445 1446 count = INTVAL (operands[2]); 1447 regno = REGNO (operands[0]); 1448 1449 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 1450 if (no_new_pseudos) 1451 { 1452 if (GET_CODE (XEXP (operands[1], 0)) == REG) 1453 { 1454 from = XEXP (operands[1], 0); 1455 off = 0; 1456 } 1457 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS 1458 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG 1459 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) 1460 { 1461 from = XEXP (XEXP (operands[1], 0), 0); 1462 off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); 1463 } 1464 else 1465 FAIL; 1466 1467 if (from == frame_pointer_rtx || from == arg_pointer_rtx) 1468 FAIL; 1469 } 1470 else 1471 { 1472 from = force_reg (Pmode, XEXP (operands[1], 0)); 1473 off = 0; 1474 } 1475 1476 for (i = 0; i < count; i++) 1477 XVECEXP (operands[3], 0, i) 1478 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i), 1479 change_address (operands[1], Pmode, 1480 plus_constant (from, 1481 off + i * UNITS_PER_WORD))); 1482}") 1483 1484(define_insn "*load_multiple_di" 1485 [(match_parallel 0 "load_multiple_operation" 1486 [(set (match_operand:DI 1 "register_operand" "=r") 1487 (match_operand:DI 2 "s_operand" "Q"))])] 1488 "" 1489 "* 1490{ 1491 int words = XVECLEN (operands[0], 0); 1492 1493 if (XVECLEN (operands[0], 0) == 1) 1494 return \"lg\\t%1,0(%2)\"; 1495 1496 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); 1497 return \"lmg\\t%1,%0,%2\"; 1498}" 1499 [(set_attr "op_type" "RXE") 1500 (set_attr "atype" "mem") 1501 (set_attr "type" "lm")]) 1502 1503(define_insn "*load_multiple_si" 1504 [(match_parallel 0 "load_multiple_operation" 1505 [(set (match_operand:SI 1 "register_operand" "=r") 1506 (match_operand:SI 2 "s_operand" "Q"))])] 1507 "" 1508 "* 1509{ 1510 int words = XVECLEN (operands[0], 0); 1511 1512 if (XVECLEN (operands[0], 0) == 1) 1513 return \"l\\t%1,0(%2)\"; 1514 1515 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); 1516 return \"lm\\t%1,%0,%2\"; 1517}" 1518 [(set_attr "op_type" "RXE") 1519 (set_attr "atype" "mem") 1520 (set_attr "type" "lm")]) 1521 1522; 1523; store multiple pattern(s). 1524; 1525 1526(define_expand "store_multiple" 1527 [(match_par_dup 3 [(set (match_operand 0 "" "") 1528 (match_operand 1 "" "")) 1529 (use (match_operand 2 "" ""))])] 1530 "" 1531 " 1532{ 1533 int regno; 1534 int count; 1535 rtx to; 1536 int i, off; 1537 1538 /* Support only storing a constant number of fixed-point registers to 1539 memory and only bother with this if more than two. */ 1540 if (GET_CODE (operands[2]) != CONST_INT 1541 || INTVAL (operands[2]) < 2 1542 || INTVAL (operands[2]) > 16 1543 || GET_CODE (operands[0]) != MEM 1544 || GET_CODE (operands[1]) != REG 1545 || REGNO (operands[1]) >= 16) 1546 FAIL; 1547 1548 count = INTVAL (operands[2]); 1549 regno = REGNO (operands[1]); 1550 1551 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 1552 1553 if (no_new_pseudos) 1554 { 1555 if (GET_CODE (XEXP (operands[0], 0)) == REG) 1556 { 1557 to = XEXP (operands[0], 0); 1558 off = 0; 1559 } 1560 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS 1561 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG 1562 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) 1563 { 1564 to = XEXP (XEXP (operands[0], 0), 0); 1565 off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); 1566 } 1567 else 1568 FAIL; 1569 1570 if (to == frame_pointer_rtx || to == arg_pointer_rtx) 1571 FAIL; 1572 } 1573 else 1574 { 1575 to = force_reg (Pmode, XEXP (operands[0], 0)); 1576 off = 0; 1577 } 1578 1579 for (i = 0; i < count; i++) 1580 XVECEXP (operands[3], 0, i) 1581 = gen_rtx_SET (VOIDmode, 1582 change_address (operands[0], Pmode, 1583 plus_constant (to, 1584 off + i * UNITS_PER_WORD)), 1585 gen_rtx_REG (Pmode, regno + i)); 1586}") 1587 1588(define_insn "*store_multiple_di" 1589 [(match_parallel 0 "store_multiple_operation" 1590 [(set (match_operand:DI 1 "s_operand" "=Q") 1591 (match_operand:DI 2 "register_operand" "r"))])] 1592 "" 1593 "* 1594{ 1595 int words = XVECLEN (operands[0], 0); 1596 1597 if (XVECLEN (operands[0], 0) == 1) 1598 return \"stg\\t%1,0(%2)\"; 1599 1600 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); 1601 return \"stmg\\t%2,%0,%1\"; 1602}" 1603 [(set_attr "op_type" "RXE") 1604 (set_attr "atype" "mem") 1605 (set_attr "type" "stm")]) 1606 1607 1608(define_insn "*store_multiple_si" 1609 [(match_parallel 0 "store_multiple_operation" 1610 [(set (match_operand:SI 1 "s_operand" "=Q") 1611 (match_operand:SI 2 "register_operand" "r"))])] 1612 "" 1613 "* 1614{ 1615 int words = XVECLEN (operands[0], 0); 1616 1617 if (XVECLEN (operands[0], 0) == 1) 1618 return \"st\\t%1,0(%2)\"; 1619 1620 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); 1621 return \"stm\\t%2,%0,%1\"; 1622}" 1623 [(set_attr "op_type" "RXE") 1624 (set_attr "atype" "mem") 1625 (set_attr "type" "stm")]) 1626 1627;; 1628;; String instructions. 1629;; 1630 1631; 1632; movstrM instruction pattern(s). 1633; 1634 1635(define_expand "movstrdi" 1636 [(set (match_operand:BLK 0 "memory_operand" "") 1637 (match_operand:BLK 1 "memory_operand" "")) 1638 (use (match_operand:DI 2 "general_operand" "")) 1639 (match_operand 3 "" "")] 1640 "TARGET_64BIT" 1641 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") 1642 1643(define_expand "movstrsi" 1644 [(set (match_operand:BLK 0 "memory_operand" "") 1645 (match_operand:BLK 1 "memory_operand" "")) 1646 (use (match_operand:SI 2 "general_operand" "")) 1647 (match_operand 3 "" "")] 1648 "" 1649 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") 1650 1651; Move a block that is up to 256 bytes in length. 1652; The block length is taken as (operands[2] % 256) + 1. 1653 1654(define_insn "movstr_short_64" 1655 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") 1656 (match_operand:BLK 1 "memory_operand" "Q,Q")) 1657 (use (match_operand:DI 2 "nonmemory_operand" "n,a")) 1658 (clobber (match_scratch:DI 3 "=X,&a"))] 1659 "TARGET_64BIT" 1660 "* 1661{ 1662 switch (which_alternative) 1663 { 1664 case 0: 1665 return \"mvc\\t%O0(%b2+1,%R0),%1\"; 1666 1667 case 1: 1668 output_asm_insn (\"bras\\t%3,.+10\", operands); 1669 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands); 1670 return \"ex\\t%2,0(%3)\"; 1671 1672 default: 1673 abort (); 1674 } 1675}" 1676 [(set_attr "op_type" "SS,NN") 1677 (set_attr "type" "cs,cs") 1678 (set_attr "atype" "mem,mem") 1679 (set_attr "length" "*,14")]) 1680 1681(define_insn "movstr_short_31" 1682 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") 1683 (match_operand:BLK 1 "memory_operand" "Q,Q")) 1684 (use (match_operand:SI 2 "nonmemory_operand" "n,a")) 1685 (clobber (match_scratch:SI 3 "=X,&a"))] 1686 "!TARGET_64BIT" 1687 "* 1688{ 1689 switch (which_alternative) 1690 { 1691 case 0: 1692 return \"mvc\\t%O0(%b2+1,%R0),%1\"; 1693 1694 case 1: 1695 output_asm_insn (\"bras\\t%3,.+10\", operands); 1696 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands); 1697 return \"ex\\t%2,0(%3)\"; 1698 1699 default: 1700 abort (); 1701 } 1702}" 1703 [(set_attr "op_type" "SS,NN") 1704 (set_attr "type" "cs,cs") 1705 (set_attr "atype" "mem,mem") 1706 (set_attr "length" "*,14")]) 1707 1708; Move a block of arbitrary length. 1709 1710(define_insn "movstr_long_64" 1711 [(set (match_operand:TI 0 "register_operand" "=d") 1712 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0") 1713 (lshiftrt:TI (match_dup 2) (const_int 64))) 1714 (const_int 64))) 1715 (set (match_operand:TI 1 "register_operand" "=d") 1716 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1") 1717 (lshiftrt:TI (match_dup 3) (const_int 64))) 1718 (const_int 64))) 1719 (set (mem:BLK (subreg:DI (match_dup 2) 0)) 1720 (mem:BLK (subreg:DI (match_dup 3) 0))) 1721 (clobber (reg:CC 33))] 1722 "TARGET_64BIT" 1723 "mvcle\\t%0,%1,0\;jo\\t.-4" 1724 [(set_attr "op_type" "NN") 1725 (set_attr "type" "vs") 1726 (set_attr "atype" "mem") 1727 (set_attr "length" "8")]) 1728 1729(define_insn "movstr_long_31" 1730 [(set (match_operand:DI 0 "register_operand" "=d") 1731 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0") 1732 (lshiftrt:DI (match_dup 2) (const_int 32))) 1733 (const_int 32))) 1734 (set (match_operand:DI 1 "register_operand" "=d") 1735 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1") 1736 (lshiftrt:DI (match_dup 3) (const_int 32))) 1737 (const_int 32))) 1738 (set (mem:BLK (subreg:SI (match_dup 2) 0)) 1739 (mem:BLK (subreg:SI (match_dup 3) 0))) 1740 (clobber (reg:CC 33))] 1741 "!TARGET_64BIT" 1742 "mvcle\\t%0,%1,0\;jo\\t.-4" 1743 [(set_attr "op_type" "NN") 1744 (set_attr "type" "vs") 1745 (set_attr "atype" "mem") 1746 (set_attr "length" "8")]) 1747 1748; 1749; clrstrM instruction pattern(s). 1750; 1751 1752(define_expand "clrstrdi" 1753 [(set (match_operand:BLK 0 "memory_operand" "") 1754 (const_int 0)) 1755 (use (match_operand:DI 1 "general_operand" "")) 1756 (match_operand 2 "" "")] 1757 "TARGET_64BIT" 1758 "s390_expand_clrstr (operands[0], operands[1]); DONE;") 1759 1760(define_expand "clrstrsi" 1761 [(set (match_operand:BLK 0 "memory_operand" "") 1762 (const_int 0)) 1763 (use (match_operand:SI 1 "general_operand" "")) 1764 (match_operand 2 "" "")] 1765 "" 1766 "s390_expand_clrstr (operands[0], operands[1]); DONE;") 1767 1768; Clear a block that is up to 256 bytes in length. 1769; The block length is taken as (operands[2] % 256) + 1. 1770 1771(define_insn "clrstr_short_64" 1772 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") 1773 (const_int 0)) 1774 (use (match_operand:DI 1 "nonmemory_operand" "n,a")) 1775 (clobber (match_scratch:DI 2 "=X,&a")) 1776 (clobber (reg:CC 33))] 1777 "TARGET_64BIT" 1778 "* 1779{ 1780 switch (which_alternative) 1781 { 1782 case 0: 1783 return \"xc\\t%O0(%b1+1,%R0),%0\"; 1784 1785 case 1: 1786 output_asm_insn (\"bras\\t%2,.+10\", operands); 1787 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands); 1788 return \"ex\\t%1,0(%2)\"; 1789 1790 default: 1791 abort (); 1792 } 1793}" 1794 [(set_attr "op_type" "SS,NN") 1795 (set_attr "type" "cs,cs") 1796 (set_attr "atype" "mem,mem") 1797 (set_attr "length" "*,14")]) 1798 1799(define_insn "clrstr_short_31" 1800 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") 1801 (const_int 0)) 1802 (use (match_operand:SI 1 "nonmemory_operand" "n,a")) 1803 (clobber (match_scratch:SI 2 "=X,&a")) 1804 (clobber (reg:CC 33))] 1805 "!TARGET_64BIT" 1806 "* 1807{ 1808 switch (which_alternative) 1809 { 1810 case 0: 1811 return \"xc\\t%O0(%b1+1,%R0),%0\"; 1812 1813 case 1: 1814 output_asm_insn (\"bras\\t%2,.+10\", operands); 1815 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands); 1816 return \"ex\\t%1,0(%2)\"; 1817 1818 default: 1819 abort (); 1820 } 1821}" 1822 [(set_attr "op_type" "SS,NN") 1823 (set_attr "type" "cs,cs") 1824 (set_attr "atype" "mem,mem") 1825 (set_attr "length" "*,14")]) 1826 1827; Clear a block of arbitrary length. 1828 1829(define_insn "clrstr_long_64" 1830 [(set (match_operand:TI 0 "register_operand" "=d") 1831 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0") 1832 (lshiftrt:TI (match_dup 2) (const_int 64))) 1833 (const_int 64))) 1834 (set (mem:BLK (subreg:DI (match_dup 2) 0)) 1835 (const_int 0)) 1836 (use (match_operand:TI 1 "register_operand" "d")) 1837 (clobber (reg:CC 33))] 1838 "TARGET_64BIT" 1839 "mvcle\\t%0,%1,0\;jo\\t.-4" 1840 [(set_attr "op_type" "NN") 1841 (set_attr "atype" "mem") 1842 (set_attr "type" "vs") 1843 (set_attr "length" "8")]) 1844 1845(define_insn "clrstr_long_31" 1846 [(set (match_operand:DI 0 "register_operand" "=d") 1847 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0") 1848 (lshiftrt:DI (match_dup 2) (const_int 32))) 1849 (const_int 32))) 1850 (set (mem:BLK (subreg:SI (match_dup 2) 0)) 1851 (const_int 0)) 1852 (use (match_operand:DI 1 "register_operand" "d")) 1853 (clobber (reg:CC 33))] 1854 "!TARGET_64BIT" 1855 "mvcle\\t%0,%1,0\;jo\\t.-4" 1856 [(set_attr "op_type" "NN") 1857 (set_attr "atype" "mem") 1858 (set_attr "type" "vs") 1859 (set_attr "length" "8")]) 1860 1861; 1862; cmpstrM instruction pattern(s). 1863; 1864 1865(define_expand "cmpstrdi" 1866 [(set (match_operand:DI 0 "register_operand" "") 1867 (compare:DI (match_operand:BLK 1 "memory_operand" "") 1868 (match_operand:BLK 2 "memory_operand" "") ) ) 1869 (use (match_operand:DI 3 "general_operand" "")) 1870 (use (match_operand:DI 4 "" ""))] 1871 "TARGET_64BIT" 1872 "s390_expand_cmpstr (operands[0], operands[1], 1873 operands[2], operands[3]); DONE;") 1874 1875(define_expand "cmpstrsi" 1876 [(set (match_operand:SI 0 "register_operand" "") 1877 (compare:SI (match_operand:BLK 1 "memory_operand" "") 1878 (match_operand:BLK 2 "memory_operand" "") ) ) 1879 (use (match_operand:SI 3 "general_operand" "")) 1880 (use (match_operand:SI 4 "" ""))] 1881 "" 1882 "s390_expand_cmpstr (operands[0], operands[1], 1883 operands[2], operands[3]); DONE;") 1884 1885; Compare a block that is up to 256 bytes in length. 1886; The block length is taken as (operands[2] % 256) + 1. 1887 1888(define_insn "cmpstr_short_64" 1889 [(set (reg:CCS 33) 1890 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q") 1891 (match_operand:BLK 1 "memory_operand" "Q,Q"))) 1892 (use (match_operand:DI 2 "nonmemory_operand" "n,a")) 1893 (clobber (match_scratch:DI 3 "=X,&a"))] 1894 "TARGET_64BIT" 1895 "* 1896{ 1897 switch (which_alternative) 1898 { 1899 case 0: 1900 return \"clc\\t%O0(%b2+1,%R0),%1\"; 1901 1902 case 1: 1903 output_asm_insn (\"bras\\t%3,.+10\", operands); 1904 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands); 1905 return \"ex\\t%2,0(%3)\"; 1906 1907 default: 1908 abort (); 1909 } 1910}" 1911 [(set_attr "op_type" "SS,NN") 1912 (set_attr "type" "cs,cs") 1913 (set_attr "atype" "mem,mem") 1914 (set_attr "length" "*,14")]) 1915 1916(define_insn "cmpstr_short_31" 1917 [(set (reg:CCS 33) 1918 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q") 1919 (match_operand:BLK 1 "memory_operand" "Q,Q"))) 1920 (use (match_operand:SI 2 "nonmemory_operand" "n,a")) 1921 (clobber (match_scratch:SI 3 "=X,&a"))] 1922 "!TARGET_64BIT" 1923 "* 1924{ 1925 switch (which_alternative) 1926 { 1927 case 0: 1928 return \"clc\\t%O0(%b2+1,%R0),%1\"; 1929 1930 case 1: 1931 output_asm_insn (\"bras\\t%3,.+10\", operands); 1932 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands); 1933 return \"ex\\t%2,0(%3)\"; 1934 1935 default: 1936 abort (); 1937 } 1938}" 1939 [(set_attr "op_type" "SS,NN") 1940 (set_attr "type" "cs,cs") 1941 (set_attr "atype" "mem,mem") 1942 (set_attr "length" "*,14")]) 1943 1944; Compare a block of arbitrary length. 1945 1946(define_insn "cmpstr_long_64" 1947 [(clobber (match_operand:TI 0 "register_operand" "=d")) 1948 (clobber (match_operand:TI 1 "register_operand" "=d")) 1949 (set (reg:CCS 33) 1950 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) 1951 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) 1952 (use (match_dup 2)) 1953 (use (match_dup 3))] 1954 "TARGET_64BIT" 1955 "clcl\\t%0,%1" 1956 [(set_attr "op_type" "RR") 1957 (set_attr "atype" "mem") 1958 (set_attr "type" "vs")]) 1959 1960(define_insn "cmpstr_long_31" 1961 [(clobber (match_operand:DI 0 "register_operand" "=d")) 1962 (clobber (match_operand:DI 1 "register_operand" "=d")) 1963 (set (reg:CCS 33) 1964 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) 1965 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) 1966 (use (match_dup 2)) 1967 (use (match_dup 3))] 1968 "!TARGET_64BIT" 1969 "clcl\\t%0,%1" 1970 [(set_attr "op_type" "RR") 1971 (set_attr "atype" "mem") 1972 (set_attr "type" "vs")]) 1973 1974; Convert condition code to integer in range (-1, 0, 1) 1975 1976(define_insn "cmpint_si" 1977 [(set (match_operand:SI 0 "register_operand" "=d") 1978 (compare:SI (reg:CCS 33) (const_int 0)))] 1979 "" 1980 "* 1981{ 1982 output_asm_insn (\"lhi\\t%0,1\", operands); 1983 output_asm_insn (\"jh\\t.+12\", operands); 1984 output_asm_insn (\"jl\\t.+6\", operands); 1985 output_asm_insn (\"sr\\t%0,%0\", operands); 1986 return \"lcr\\t%0,%0\"; 1987}" 1988 [(set_attr "op_type" "NN") 1989 (set_attr "length" "16") 1990 (set_attr "atype" "reg") 1991 (set_attr "type" "other")]) 1992 1993(define_insn "cmpint_di" 1994 [(set (match_operand:DI 0 "register_operand" "=d") 1995 (compare:DI (reg:CCS 33) (const_int 0)))] 1996 "TARGET_64BIT" 1997 "* 1998{ 1999 output_asm_insn (\"lghi\\t%0,1\", operands); 2000 output_asm_insn (\"jh\\t.+12\", operands); 2001 output_asm_insn (\"jl\\t.+6\", operands); 2002 output_asm_insn (\"sgr\\t%0,%0\", operands); 2003 return \"lcgr\\t%0,%0\"; 2004}" 2005 [(set_attr "op_type" "NN") 2006 (set_attr "length" "22") 2007 (set_attr "atype" "reg") 2008 (set_attr "type" "other")]) 2009 2010 2011;; 2012;;- Conversion instructions. 2013;; 2014 2015(define_insn "*sethighqisi" 2016 [(set (match_operand:SI 0 "register_operand" "=d") 2017 (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10)) 2018 (clobber (reg:CC 33))] 2019 "" 2020 "icm\\t%0,8,%1" 2021 [(set_attr "op_type" "RS") 2022 (set_attr "atype" "mem")]) 2023 2024(define_insn "*sethighhisi" 2025 [(set (match_operand:SI 0 "register_operand" "=d") 2026 (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10)) 2027 (clobber (reg:CC 33))] 2028 "" 2029 "icm\\t%0,12,%1" 2030 [(set_attr "op_type" "RS") 2031 (set_attr "atype" "mem")]) 2032 2033(define_insn "*sethighqidi_64" 2034 [(set (match_operand:DI 0 "register_operand" "=d") 2035 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10)) 2036 (clobber (reg:CC 33))] 2037 "TARGET_64BIT" 2038 "icmh\\t%0,8,%1" 2039 [(set_attr "op_type" "RSE") 2040 (set_attr "atype" "mem")]) 2041 2042(define_insn "*sethighqidi_31" 2043 [(set (match_operand:DI 0 "register_operand" "=d") 2044 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10)) 2045 (clobber (reg:CC 33))] 2046 "!TARGET_64BIT" 2047 "icm\\t%0,8,%1" 2048 [(set_attr "op_type" "RS") 2049 (set_attr "atype" "mem")]) 2050 2051(define_insn_and_split "*extractqi" 2052 [(set (match_operand:SI 0 "register_operand" "=d") 2053 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") 2054 (match_operand 2 "const_int_operand" "n") 2055 (const_int 0))) 2056 (clobber (reg:CC 33))] 2057 "!TARGET_64BIT 2058 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" 2059 "#" 2060 "&& reload_completed" 2061 [(parallel 2062 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) 2063 (clobber (reg:CC 33))]) 2064 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] 2065 " 2066{ 2067 operands[2] = GEN_INT (32 - INTVAL (operands[2])); 2068 operands[1] = change_address (operands[1], QImode, 0); 2069}" 2070 [(set_attr "atype" "mem")]) 2071 2072(define_insn_and_split "*extracthi" 2073 [(set (match_operand:SI 0 "register_operand" "=d") 2074 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") 2075 (match_operand 2 "const_int_operand" "n") 2076 (const_int 0))) 2077 (clobber (reg:CC 33))] 2078 "!TARGET_64BIT 2079 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" 2080 "#" 2081 "&& reload_completed" 2082 [(parallel 2083 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) 2084 (clobber (reg:CC 33))]) 2085 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] 2086 " 2087{ 2088 operands[2] = GEN_INT (32 - INTVAL (operands[2])); 2089 operands[1] = change_address (operands[1], HImode, 0); 2090}" 2091 [(set_attr "atype" "mem")]) 2092 2093; 2094; extendsidi2 instruction pattern(s). 2095; 2096 2097(define_expand "extendsidi2" 2098 [(set (match_operand:DI 0 "register_operand" "") 2099 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 2100 "" 2101 " 2102{ 2103 if (!TARGET_64BIT) 2104 { 2105 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); 2106 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); 2107 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); 2108 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); 2109 DONE; 2110 } 2111} 2112") 2113 2114(define_insn "*extendsidi2" 2115 [(set (match_operand:DI 0 "register_operand" "=d,d") 2116 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] 2117 "TARGET_64BIT" 2118 "@ 2119 lgfr\\t%0,%1 2120 lgf\\t%0,%1" 2121 [(set_attr "op_type" "RRE,RXE") 2122 (set_attr "atype" "reg,mem")]) 2123 2124; 2125; extendhidi2 instruction pattern(s). 2126; 2127 2128(define_expand "extendhidi2" 2129 [(set (match_operand:DI 0 "register_operand" "") 2130 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] 2131 "" 2132 " 2133{ 2134 if (!TARGET_64BIT) 2135 { 2136 rtx tmp = gen_reg_rtx (SImode); 2137 emit_insn (gen_extendhisi2 (tmp, operands[1])); 2138 emit_insn (gen_extendsidi2 (operands[0], tmp)); 2139 DONE; 2140 } 2141 else 2142 { 2143 operands[1] = gen_lowpart (DImode, operands[1]); 2144 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); 2145 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); 2146 DONE; 2147 } 2148} 2149") 2150 2151(define_insn "*extendhidi2" 2152 [(set (match_operand:DI 0 "register_operand" "=d") 2153 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] 2154 "TARGET_64BIT" 2155 "lgh\\t%0,%1" 2156 [(set_attr "op_type" "RXE") 2157 (set_attr "atype" "mem")]) 2158 2159; 2160; extendqidi2 instruction pattern(s). 2161; 2162 2163(define_expand "extendqidi2" 2164 [(set (match_operand:DI 0 "register_operand" "") 2165 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] 2166 "" 2167 " 2168{ 2169 if (!TARGET_64BIT) 2170 { 2171 rtx tmp = gen_reg_rtx (SImode); 2172 emit_insn (gen_extendqisi2 (tmp, operands[1])); 2173 emit_insn (gen_extendsidi2 (operands[0], tmp)); 2174 DONE; 2175 } 2176 else 2177 { 2178 operands[1] = gen_lowpart (DImode, operands[1]); 2179 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); 2180 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); 2181 DONE; 2182 } 2183} 2184") 2185 2186(define_split 2187 [(set (match_operand:DI 0 "register_operand" "") 2188 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))] 2189 "TARGET_64BIT && !reload_completed" 2190 [(parallel 2191 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10)) 2192 (clobber (reg:CC 33))]) 2193 (parallel 2194 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) 2195 (clobber (reg:CC 33))])] 2196 "") 2197 2198; 2199; extendhisi2 instruction pattern(s). 2200; 2201 2202(define_expand "extendhisi2" 2203 [(set (match_operand:SI 0 "register_operand" "") 2204 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] 2205 "" 2206 " 2207{ 2208 operands[1] = gen_lowpart (SImode, operands[1]); 2209 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); 2210 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); 2211 DONE; 2212} 2213") 2214 2215(define_insn "*extendhisi2" 2216 [(set (match_operand:SI 0 "register_operand" "=d") 2217 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] 2218 "" 2219 "lh\\t%0,%1" 2220 [(set_attr "op_type" "RX") 2221 (set_attr "atype" "mem")]) 2222 2223; 2224; extendqisi2 instruction pattern(s). 2225; 2226 2227(define_expand "extendqisi2" 2228 [(set (match_operand:SI 0 "register_operand" "") 2229 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] 2230 "" 2231 " 2232{ 2233 operands[1] = gen_lowpart (SImode, operands[1]); 2234 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); 2235 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); 2236 DONE; 2237} 2238") 2239 2240(define_split 2241 [(set (match_operand:SI 0 "register_operand" "") 2242 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))] 2243 "!reload_completed" 2244 [(parallel 2245 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) 2246 (clobber (reg:CC 33))]) 2247 (parallel 2248 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) 2249 (clobber (reg:CC 33))])] 2250 "") 2251 2252; 2253; extendqihi2 instruction pattern(s). 2254; 2255 2256 2257; 2258; zero_extendsidi2 instruction pattern(s). 2259; 2260 2261(define_expand "zero_extendsidi2" 2262 [(set (match_operand:DI 0 "register_operand" "") 2263 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 2264 "" 2265 " 2266{ 2267 if (!TARGET_64BIT) 2268 { 2269 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); 2270 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); 2271 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); 2272 DONE; 2273 } 2274} 2275") 2276 2277(define_insn "*zero_extendsidi2" 2278 [(set (match_operand:DI 0 "register_operand" "=d,d") 2279 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] 2280 "TARGET_64BIT" 2281 "@ 2282 llgfr\\t%0,%1 2283 llgf\\t%0,%1" 2284 [(set_attr "op_type" "RRE,RXE") 2285 (set_attr "atype" "reg,mem")]) 2286 2287; 2288; zero_extendhidi2 instruction pattern(s). 2289; 2290 2291(define_expand "zero_extendhidi2" 2292 [(set (match_operand:DI 0 "register_operand" "") 2293 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] 2294 "" 2295 " 2296{ 2297 if (!TARGET_64BIT) 2298 { 2299 rtx tmp = gen_reg_rtx (SImode); 2300 emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); 2301 emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); 2302 DONE; 2303 } 2304 else 2305 { 2306 operands[1] = gen_lowpart (DImode, operands[1]); 2307 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); 2308 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); 2309 DONE; 2310 } 2311} 2312") 2313 2314(define_insn "*zero_extendhidi2" 2315 [(set (match_operand:DI 0 "register_operand" "=d") 2316 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] 2317 "TARGET_64BIT" 2318 "llgh\\t%0,%1" 2319 [(set_attr "op_type" "RXE") 2320 (set_attr "atype" "mem")]) 2321 2322; 2323; zero_extendqidi2 instruction pattern(s) 2324; 2325 2326(define_expand "zero_extendqidi2" 2327 [(set (match_operand:DI 0 "register_operand" "") 2328 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] 2329 "" 2330 " 2331{ 2332 if (!TARGET_64BIT) 2333 { 2334 rtx tmp = gen_reg_rtx (SImode); 2335 emit_insn (gen_zero_extendqisi2 (tmp, operands[1])); 2336 emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); 2337 DONE; 2338 } 2339 else 2340 { 2341 operands[1] = gen_lowpart (DImode, operands[1]); 2342 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); 2343 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); 2344 DONE; 2345 } 2346} 2347") 2348 2349(define_insn "*zero_extendqidi2" 2350 [(set (match_operand:DI 0 "register_operand" "=d") 2351 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] 2352 "TARGET_64BIT" 2353 "llgc\\t%0,%1" 2354 [(set_attr "op_type" "RXE") 2355 (set_attr "atype" "mem")]) 2356 2357; 2358; zero_extendhisi2 instruction pattern(s). 2359; 2360 2361(define_expand "zero_extendhisi2" 2362 [(set (match_operand:SI 0 "register_operand" "") 2363 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] 2364 "" 2365 " 2366{ 2367 operands[1] = gen_lowpart (SImode, operands[1]); 2368 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); 2369 DONE; 2370} 2371") 2372 2373(define_insn "*zero_extendhisi2_64" 2374 [(set (match_operand:SI 0 "register_operand" "=d") 2375 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] 2376 "TARGET_64BIT" 2377 "llgh\\t%0,%1" 2378 [(set_attr "op_type" "RXE") 2379 (set_attr "atype" "mem")]) 2380 2381(define_insn_and_split "*zero_extendhisi2_31" 2382 [(set (match_operand:SI 0 "register_operand" "=&d") 2383 (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q"))) 2384 (clobber (reg:CC 33))] 2385 "!TARGET_64BIT" 2386 "#" 2387 "&& reload_completed" 2388 [(set (match_dup 0) (const_int 0)) 2389 (parallel 2390 [(set (strict_low_part (match_dup 2)) (match_dup 1)) 2391 (clobber (reg:CC 33))])] 2392 "operands[2] = gen_lowpart (HImode, operands[0]);" 2393 [(set_attr "atype" "mem")]) 2394 2395; 2396; zero_extendqisi2 instruction pattern(s). 2397; 2398 2399(define_expand "zero_extendqisi2" 2400 [(set (match_operand:SI 0 "register_operand" "") 2401 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] 2402 "" 2403 " 2404{ 2405 operands[1] = gen_lowpart (SImode, operands[1]); 2406 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff))); 2407 DONE; 2408} 2409") 2410 2411(define_insn "*zero_extendqisi2_64" 2412 [(set (match_operand:SI 0 "register_operand" "=d") 2413 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] 2414 "TARGET_64BIT" 2415 "llgc\\t%0,%1" 2416 [(set_attr "op_type" "RXE") 2417 (set_attr "atype" "mem")]) 2418 2419(define_insn_and_split "*zero_extendqisi2_31" 2420 [(set (match_operand:SI 0 "register_operand" "=&d") 2421 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] 2422 "!TARGET_64BIT" 2423 "#" 2424 "&& reload_completed" 2425 [(set (match_dup 0) (const_int 0)) 2426 (set (strict_low_part (match_dup 2)) (match_dup 1))] 2427 "operands[2] = gen_lowpart (QImode, operands[0]);" 2428 [(set_attr "atype" "mem")]) 2429 2430; 2431; zero_extendqihi2 instruction pattern(s). 2432; 2433 2434(define_expand "zero_extendqihi2" 2435 [(set (match_operand:HI 0 "register_operand" "") 2436 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] 2437 "TARGET_64BIT" 2438 " 2439{ 2440 operands[1] = gen_lowpart (HImode, operands[1]); 2441 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); 2442 DONE; 2443} 2444") 2445 2446(define_insn "*zero_extendqihi2_64" 2447 [(set (match_operand:HI 0 "register_operand" "=d") 2448 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] 2449 "TARGET_64BIT" 2450 "llgc\\t%0,%1" 2451 [(set_attr "op_type" "RXE") 2452 (set_attr "atype" "mem")]) 2453 2454(define_insn_and_split "*zero_extendqihi2_31" 2455 [(set (match_operand:HI 0 "register_operand" "=&d") 2456 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] 2457 "!TARGET_64BIT" 2458 "#" 2459 "&& reload_completed" 2460 [(set (match_dup 0) (const_int 0)) 2461 (set (strict_low_part (match_dup 2)) (match_dup 1))] 2462 "operands[2] = gen_lowpart (QImode, operands[0]);" 2463 [(set_attr "atype" "mem")]) 2464 2465 2466; 2467; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). 2468; 2469 2470(define_expand "fixuns_truncdfdi2" 2471 [(set (match_operand:DI 0 "register_operand" "") 2472 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] 2473 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2474 " 2475{ 2476 rtx label1 = gen_label_rtx (); 2477 rtx label2 = gen_label_rtx (); 2478 rtx temp = gen_reg_rtx (DFmode); 2479 operands[1] = force_reg (DFmode, operands[1]); 2480 2481 emit_insn (gen_cmpdf (operands[1], 2482 CONST_DOUBLE_FROM_REAL_VALUE ( 2483 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode))); 2484 emit_jump_insn (gen_blt (label1)); 2485 emit_insn (gen_subdf3 (temp, operands[1], 2486 CONST_DOUBLE_FROM_REAL_VALUE ( 2487 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode))); 2488 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); 2489 emit_jump (label2); 2490 2491 emit_label (label1); 2492 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); 2493 emit_label (label2); 2494 DONE; 2495}") 2496 2497(define_expand "fix_truncdfdi2" 2498 [(set (match_operand:DI 0 "register_operand" "") 2499 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] 2500 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2501 " 2502{ 2503 operands[1] = force_reg (DFmode, operands[1]); 2504 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); 2505 DONE; 2506}") 2507 2508(define_insn "fix_truncdfdi2_ieee" 2509 [(set (match_operand:DI 0 "register_operand" "=d") 2510 (fix:DI (match_operand:DF 1 "register_operand" "f"))) 2511 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1) 2512 (clobber (reg:CC 33))] 2513 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2514 "cgdbr\\t%0,%h2,%1" 2515 [(set_attr "op_type" "RRE") 2516 (set_attr "type" "other")]) 2517 2518; 2519; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). 2520; 2521 2522(define_expand "fixuns_truncdfsi2" 2523 [(set (match_operand:SI 0 "register_operand" "") 2524 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] 2525 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2526 " 2527{ 2528 rtx label1 = gen_label_rtx (); 2529 rtx label2 = gen_label_rtx (); 2530 rtx temp = gen_reg_rtx (DFmode); 2531 2532 operands[1] = force_reg (DFmode,operands[1]); 2533 emit_insn (gen_cmpdf (operands[1], 2534 CONST_DOUBLE_FROM_REAL_VALUE ( 2535 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode))); 2536 emit_jump_insn (gen_blt (label1)); 2537 emit_insn (gen_subdf3 (temp, operands[1], 2538 CONST_DOUBLE_FROM_REAL_VALUE ( 2539 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode))); 2540 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); 2541 emit_jump (label2); 2542 2543 emit_label (label1); 2544 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); 2545 emit_label (label2); 2546 DONE; 2547}") 2548 2549(define_expand "fix_truncdfsi2" 2550 [(set (match_operand:SI 0 "register_operand" "") 2551 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] 2552 "TARGET_HARD_FLOAT" 2553 " 2554{ 2555 if (TARGET_IBM_FLOAT) 2556 { 2557 /* This is the algorithm from POP chapter A.5.7.2. */ 2558 2559 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD); 2560 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); 2561 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); 2562 2563 operands[1] = force_reg (DFmode, operands[1]); 2564 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], 2565 two31r, two32, temp)); 2566 } 2567 else 2568 { 2569 operands[1] = force_reg (DFmode, operands[1]); 2570 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); 2571 } 2572 2573 DONE; 2574}") 2575 2576(define_insn "fix_truncdfsi2_ieee" 2577 [(set (match_operand:SI 0 "register_operand" "=d") 2578 (fix:SI (match_operand:DF 1 "register_operand" "f"))) 2579 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1) 2580 (clobber (reg:CC 33))] 2581 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2582 "cfdbr\\t%0,%h2,%1" 2583 [(set_attr "op_type" "RRE") 2584 (set_attr "type" "other" )]) 2585 2586(define_insn "fix_truncdfsi2_ibm" 2587 [(set (match_operand:SI 0 "register_operand" "=d") 2588 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) 2589 (use (match_operand:DI 2 "immediate_operand" "m")) 2590 (use (match_operand:DI 3 "immediate_operand" "m")) 2591 (use (match_operand:BLK 4 "memory_operand" "m")) 2592 (clobber (reg:CC 33))] 2593 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 2594 "* 2595{ 2596 output_asm_insn (\"sd\\t%1,%2\", operands); 2597 output_asm_insn (\"aw\\t%1,%3\", operands); 2598 output_asm_insn (\"std\\t%1,%4\", operands); 2599 output_asm_insn (\"xi\\t%N4,128\", operands); 2600 return \"l\\t%0,%N4\"; 2601}" 2602 [(set_attr "op_type" "NN") 2603 (set_attr "type" "other") 2604 (set_attr "length" "20")]) 2605 2606; 2607; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). 2608; 2609 2610(define_expand "fixuns_truncsfdi2" 2611 [(set (match_operand:DI 0 "register_operand" "") 2612 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] 2613 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2614 " 2615{ 2616 rtx label1 = gen_label_rtx (); 2617 rtx label2 = gen_label_rtx (); 2618 rtx temp = gen_reg_rtx (SFmode); 2619 2620 operands[1] = force_reg (SFmode, operands[1]); 2621 emit_insn (gen_cmpsf (operands[1], 2622 CONST_DOUBLE_FROM_REAL_VALUE ( 2623 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode))); 2624 emit_jump_insn (gen_blt (label1)); 2625 2626 emit_insn (gen_subsf3 (temp, operands[1], 2627 CONST_DOUBLE_FROM_REAL_VALUE ( 2628 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode))); 2629 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); 2630 emit_jump (label2); 2631 2632 emit_label (label1); 2633 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); 2634 emit_label (label2); 2635 DONE; 2636}") 2637 2638(define_expand "fix_truncsfdi2" 2639 [(set (match_operand:DI 0 "register_operand" "") 2640 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] 2641 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2642 " 2643{ 2644 operands[1] = force_reg (SFmode, operands[1]); 2645 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); 2646 DONE; 2647}") 2648 2649(define_insn "fix_truncsfdi2_ieee" 2650 [(set (match_operand:DI 0 "register_operand" "=d") 2651 (fix:DI (match_operand:SF 1 "register_operand" "f"))) 2652 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1) 2653 (clobber (reg:CC 33))] 2654 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2655 "cgebr\\t%0,%h2,%1" 2656 [(set_attr "op_type" "RRE") 2657 (set_attr "type" "other")]) 2658 2659; 2660; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). 2661; 2662 2663(define_expand "fixuns_truncsfsi2" 2664 [(set (match_operand:SI 0 "register_operand" "") 2665 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] 2666 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2667 " 2668{ 2669 rtx label1 = gen_label_rtx (); 2670 rtx label2 = gen_label_rtx (); 2671 rtx temp = gen_reg_rtx (SFmode); 2672 2673 operands[1] = force_reg (SFmode, operands[1]); 2674 emit_insn (gen_cmpsf (operands[1], 2675 CONST_DOUBLE_FROM_REAL_VALUE ( 2676 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode))); 2677 emit_jump_insn (gen_blt (label1)); 2678 emit_insn (gen_subsf3 (temp, operands[1], 2679 CONST_DOUBLE_FROM_REAL_VALUE ( 2680 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode))); 2681 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); 2682 emit_jump (label2); 2683 2684 emit_label (label1); 2685 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); 2686 emit_label (label2); 2687 DONE; 2688}") 2689 2690(define_expand "fix_truncsfsi2" 2691 [(set (match_operand:SI 0 "register_operand" "") 2692 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] 2693 "TARGET_HARD_FLOAT" 2694 " 2695{ 2696 if (TARGET_IBM_FLOAT) 2697 { 2698 /* Convert to DFmode and then use the POP algorithm. */ 2699 rtx temp = gen_reg_rtx (DFmode); 2700 emit_insn (gen_extendsfdf2 (temp, operands[1])); 2701 emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); 2702 } 2703 else 2704 { 2705 operands[1] = force_reg (SFmode, operands[1]); 2706 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); 2707 } 2708 2709 DONE; 2710}") 2711 2712(define_insn "fix_truncsfsi2_ieee" 2713 [(set (match_operand:SI 0 "register_operand" "=d") 2714 (fix:SI (match_operand:SF 1 "register_operand" "f"))) 2715 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1) 2716 (clobber (reg:CC 33))] 2717 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2718 "cfebr\\t%0,%h2,%1" 2719 [(set_attr "op_type" "RRE") 2720 (set_attr "type" "other")]) 2721 2722; 2723; floatdidf2 instruction pattern(s). 2724; 2725 2726(define_insn "floatdidf2" 2727 [(set (match_operand:DF 0 "register_operand" "=f") 2728 (float:DF (match_operand:DI 1 "register_operand" "d"))) 2729 (clobber (reg:CC 33))] 2730 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2731 "cdgbr\\t%0,%1" 2732 [(set_attr "op_type" "RRE") 2733 (set_attr "type" "other" )]) 2734 2735; 2736; floatdisf2 instruction pattern(s). 2737; 2738 2739(define_insn "floatdisf2" 2740 [(set (match_operand:SF 0 "register_operand" "=f") 2741 (float:SF (match_operand:DI 1 "register_operand" "d"))) 2742 (clobber (reg:CC 33))] 2743 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2744 "cegbr\\t%0,%1" 2745 [(set_attr "op_type" "RRE") 2746 (set_attr "type" "other" )]) 2747 2748; 2749; floatsidf2 instruction pattern(s). 2750; 2751 2752(define_expand "floatsidf2" 2753 [(parallel 2754 [(set (match_operand:DF 0 "register_operand" "") 2755 (float:DF (match_operand:SI 1 "register_operand" ""))) 2756 (clobber (reg:CC 33))])] 2757 "TARGET_HARD_FLOAT" 2758 " 2759{ 2760 if (TARGET_IBM_FLOAT) 2761 { 2762 /* This is the algorithm from POP chapter A.5.7.1. */ 2763 2764 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD); 2765 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); 2766 2767 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); 2768 DONE; 2769 } 2770}") 2771 2772(define_insn "floatsidf2_ieee" 2773 [(set (match_operand:DF 0 "register_operand" "=f") 2774 (float:DF (match_operand:SI 1 "register_operand" "d"))) 2775 (clobber (reg:CC 33))] 2776 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2777 "cdfbr\\t%0,%1" 2778 [(set_attr "op_type" "RRE") 2779 (set_attr "type" "other" )]) 2780 2781(define_insn "floatsidf2_ibm" 2782 [(set (match_operand:DF 0 "register_operand" "=f") 2783 (float:DF (match_operand:SI 1 "register_operand" "d"))) 2784 (use (match_operand:DI 2 "immediate_operand" "m")) 2785 (use (match_operand:BLK 3 "memory_operand" "m")) 2786 (clobber (reg:CC 33))] 2787 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 2788 "* 2789{ 2790 output_asm_insn (\"st\\t%1,%N3\", operands); 2791 output_asm_insn (\"xi\\t%N3,128\", operands); 2792 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands); 2793 output_asm_insn (\"ld\\t%0,%3\", operands); 2794 return \"sd\\t%0,%2\"; 2795}" 2796 [(set_attr "op_type" "NN") 2797 (set_attr "type" "other" ) 2798 (set_attr "length" "20")]) 2799 2800; 2801; floatsisf2 instruction pattern(s). 2802; 2803 2804(define_expand "floatsisf2" 2805 [(parallel 2806 [(set (match_operand:SF 0 "register_operand" "") 2807 (float:SF (match_operand:SI 1 "register_operand" ""))) 2808 (clobber (reg:CC 33))])] 2809 "TARGET_HARD_FLOAT" 2810 " 2811{ 2812 if (TARGET_IBM_FLOAT) 2813 { 2814 /* Use the POP algorithm to convert to DFmode and then truncate. */ 2815 rtx temp = gen_reg_rtx (DFmode); 2816 emit_insn (gen_floatsidf2 (temp, operands[1])); 2817 emit_insn (gen_truncdfsf2 (operands[0], temp)); 2818 DONE; 2819 } 2820}") 2821 2822(define_insn "floatsisf2_ieee" 2823 [(set (match_operand:SF 0 "register_operand" "=f") 2824 (float:SF (match_operand:SI 1 "register_operand" "d"))) 2825 (clobber (reg:CC 33))] 2826 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2827 "cefbr\\t%0,%1" 2828 [(set_attr "op_type" "RRE") 2829 (set_attr "type" "other" )]) 2830 2831; 2832; truncdfsf2 instruction pattern(s). 2833; 2834 2835(define_expand "truncdfsf2" 2836 [(set (match_operand:SF 0 "register_operand" "") 2837 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))] 2838 "TARGET_HARD_FLOAT" 2839 "") 2840 2841(define_insn "truncdfsf2_ieee" 2842 [(set (match_operand:SF 0 "register_operand" "=f") 2843 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] 2844 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2845 "ledbr\\t%0,%1" 2846 [(set_attr "op_type" "RRE")]) 2847 2848(define_insn "truncdfsf2_ibm" 2849 [(set (match_operand:SF 0 "register_operand" "=f,f") 2850 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))] 2851 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 2852 "@ 2853 lrer\\t%0,%1 2854 le\\t%0,%1" 2855 [(set_attr "op_type" "RR,RX") 2856 (set_attr "atype" "reg,mem")]) 2857 2858; 2859; extendsfdf2 instruction pattern(s). 2860; 2861 2862(define_expand "extendsfdf2" 2863 [(set (match_operand:DF 0 "register_operand" "") 2864 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] 2865 "TARGET_HARD_FLOAT" 2866 " 2867{ 2868 if (TARGET_IBM_FLOAT) 2869 { 2870 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); 2871 DONE; 2872 } 2873}") 2874 2875(define_insn "extendsfdf2_ieee" 2876 [(set (match_operand:DF 0 "register_operand" "=f,f") 2877 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))] 2878 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 2879 "@ 2880 ldebr\\t%0,%1 2881 ldeb\\t%0,%1" 2882 [(set_attr "op_type" "RRE,RXE")]) 2883 2884(define_insn "extendsfdf2_ibm" 2885 [(set (match_operand:DF 0 "register_operand" "=f,f") 2886 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m"))) 2887 (clobber (reg:CC 33))] 2888 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 2889 "@ 2890 sdr\\t%0,%0\;ler\\t%0,%1 2891 sdr\\t%0,%0\;le\\t%0,%1" 2892 [(set_attr "op_type" "RRE,RXE") 2893 (set_attr "atype" "reg,mem") 2894 (set_attr "type" "o2,o2")]) 2895 2896 2897;; 2898;; ARITHMETRIC OPERATIONS 2899;; 2900; arithmetric operations set the ConditionCode, 2901; because of unpredictable Bits in Register for Halfword and Byte 2902; the ConditionCode can be set wrong in operations for Halfword and Byte 2903 2904;; 2905;;- Add instructions. 2906;; 2907 2908; 2909; adddi3 instruction pattern(s). 2910; 2911 2912(define_insn "*adddi3_sign" 2913 [(set (match_operand:DI 0 "register_operand" "=d,d") 2914 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) 2915 (match_operand:DI 1 "register_operand" "0,0"))) 2916 (clobber (reg:CC 33))] 2917 "TARGET_64BIT" 2918 "@ 2919 agfr\\t%0,%2 2920 agf\\t%0,%2" 2921 [(set_attr "op_type" "RRE,RXE") 2922 (set_attr "atype" "reg,mem")]) 2923 2924(define_insn "*adddi3_zero_cc" 2925 [(set (reg 33) 2926 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) 2927 (match_operand:DI 1 "register_operand" "0,0")) 2928 (const_int 0))) 2929 (set (match_operand:DI 0 "register_operand" "=d,d") 2930 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] 2931 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 2932 "@ 2933 algfr\\t%0,%2 2934 algf\\t%0,%2" 2935 [(set_attr "op_type" "RRE,RXE") 2936 (set_attr "atype" "reg,mem")]) 2937 2938(define_insn "*adddi3_zero_cconly" 2939 [(set (reg 33) 2940 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) 2941 (match_operand:DI 1 "register_operand" "0,0")) 2942 (const_int 0))) 2943 (clobber (match_scratch:DI 0 "=d,d"))] 2944 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 2945 "@ 2946 algfr\\t%0,%2 2947 algf\\t%0,%2" 2948 [(set_attr "op_type" "RRE,RXE") 2949 (set_attr "atype" "reg,mem")]) 2950 2951(define_insn "*adddi3_zero" 2952 [(set (match_operand:DI 0 "register_operand" "=d,d") 2953 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) 2954 (match_operand:DI 1 "register_operand" "0,0"))) 2955 (clobber (reg:CC 33))] 2956 "TARGET_64BIT" 2957 "@ 2958 algfr\\t%0,%2 2959 algf\\t%0,%2" 2960 [(set_attr "op_type" "RRE,RXE") 2961 (set_attr "atype" "reg,mem")]) 2962 2963(define_insn "*adddi3_imm_cc" 2964 [(set (reg 33) 2965 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") 2966 (match_operand:DI 2 "const_int_operand" "K")) 2967 (const_int 0))) 2968 (set (match_operand:DI 0 "register_operand" "=d") 2969 (plus:DI (match_dup 1) (match_dup 2)))] 2970 "TARGET_64BIT 2971 && s390_match_ccmode (insn, CCAmode) 2972 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" 2973 "aghi\\t%0,%h2" 2974 [(set_attr "op_type" "RI") 2975 (set_attr "atype" "reg")]) 2976 2977(define_insn "*adddi3_cc" 2978 [(set (reg 33) 2979 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 2980 (match_operand:DI 2 "general_operand" "d,m")) 2981 (const_int 0))) 2982 (set (match_operand:DI 0 "register_operand" "=d,d") 2983 (plus:DI (match_dup 1) (match_dup 2)))] 2984 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 2985 "@ 2986 algr\\t%0,%2 2987 alg\\t%0,%2" 2988 [(set_attr "op_type" "RRE,RXE") 2989 (set_attr "atype" "reg,mem")]) 2990 2991(define_insn "*adddi3_cconly" 2992 [(set (reg 33) 2993 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 2994 (match_operand:DI 2 "general_operand" "d,m")) 2995 (const_int 0))) 2996 (clobber (match_scratch:DI 0 "=d,d"))] 2997 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 2998 "@ 2999 algr\\t%0,%2 3000 alg\\t%0,%2" 3001 [(set_attr "op_type" "RRE,RXE") 3002 (set_attr "atype" "reg,mem")]) 3003 3004(define_insn "*adddi3_cconly2" 3005 [(set (reg 33) 3006 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") 3007 (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) 3008 (clobber (match_scratch:DI 0 "=d,d"))] 3009 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" 3010 "@ 3011 algr\\t%0,%2 3012 alg\\t%0,%2" 3013 [(set_attr "op_type" "RRE,RXE") 3014 (set_attr "atype" "reg,mem")]) 3015 3016(define_insn "*adddi3_64" 3017 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 3018 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") 3019 (match_operand:DI 2 "general_operand" "d,K,m") ) ) 3020 (clobber (reg:CC 33))] 3021 "TARGET_64BIT" 3022 "@ 3023 agr\\t%0,%2 3024 aghi\\t%0,%h2 3025 ag\\t%0,%2" 3026 [(set_attr "op_type" "RRE,RI,RXE") 3027 (set_attr "atype" "reg,reg,mem")]) 3028 3029(define_insn_and_split "*adddi3_31" 3030 [(set (match_operand:DI 0 "register_operand" "=&d") 3031 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") 3032 (match_operand:DI 2 "general_operand" "do") ) ) 3033 (clobber (reg:CC 33))] 3034 "!TARGET_64BIT" 3035 "#" 3036 "&& reload_completed" 3037 [(parallel 3038 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) 3039 (clobber (reg:CC 33))]) 3040 (parallel 3041 [(set (reg:CCL1 33) 3042 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) 3043 (match_dup 7))) 3044 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) 3045 (set (pc) 3046 (if_then_else (ltu (reg:CCL1 33) (const_int 0)) 3047 (pc) 3048 (label_ref (match_dup 9)))) 3049 (parallel 3050 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) 3051 (clobber (reg:CC 33))]) 3052 (match_dup 9)] 3053 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 3054 operands[4] = operand_subword (operands[1], 0, 0, DImode); 3055 operands[5] = operand_subword (operands[2], 0, 0, DImode); 3056 operands[6] = operand_subword (operands[0], 1, 0, DImode); 3057 operands[7] = operand_subword (operands[1], 1, 0, DImode); 3058 operands[8] = operand_subword (operands[2], 1, 0, DImode); 3059 operands[9] = gen_label_rtx ();" 3060 [(set_attr "op_type" "NN")]) 3061 3062(define_expand "adddi3" 3063 [(parallel 3064 [(set (match_operand:DI 0 "register_operand" "") 3065 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") 3066 (match_operand:DI 2 "general_operand" ""))) 3067 (clobber (reg:CC 33))])] 3068 "" 3069 "") 3070 3071(define_insn "*la_64" 3072 [(set (match_operand:DI 0 "register_operand" "=d") 3073 (match_operand:QI 1 "address_operand" "p"))] 3074 "TARGET_64BIT" 3075 "la\\t%0,%a1" 3076 [(set_attr "op_type" "RX") 3077 (set_attr "atype" "mem") 3078 (set_attr "type" "la")]) 3079 3080(define_peephole2 3081 [(parallel 3082 [(set (match_operand:DI 0 "register_operand" "") 3083 (match_operand:QI 1 "address_operand" "")) 3084 (clobber (reg:CC 33))])] 3085 "TARGET_64BIT 3086 && strict_memory_address_p (VOIDmode, operands[1]) 3087 && preferred_la_operand_p (operands[1])" 3088 [(set (match_dup 0) (match_dup 1))] 3089 "") 3090 3091(define_peephole2 3092 [(set (match_operand:DI 0 "register_operand" "") 3093 (match_operand:DI 1 "register_operand" "")) 3094 (parallel 3095 [(set (match_dup 0) 3096 (plus:DI (match_dup 0) 3097 (match_operand:DI 2 "nonmemory_operand" ""))) 3098 (clobber (reg:CC 33))])] 3099 "TARGET_64BIT 3100 && !reg_overlap_mentioned_p (operands[0], operands[2]) 3101 && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (DImode, operands[1], operands[2])) 3102 && preferred_la_operand_p (gen_rtx_PLUS (DImode, operands[1], operands[2]))" 3103 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] 3104 "") 3105 3106(define_expand "reload_indi" 3107 [(parallel [(match_operand:DI 0 "register_operand" "=a") 3108 (match_operand:DI 1 "s390_plus_operand" "") 3109 (match_operand:DI 2 "register_operand" "=&a")])] 3110 "TARGET_64BIT" 3111 " 3112{ 3113 s390_expand_plus_operand (operands[0], operands[1], operands[2]); 3114 DONE; 3115}") 3116 3117 3118; 3119; addsi3 instruction pattern(s). 3120; 3121 3122(define_insn "*addsi3_imm_cc" 3123 [(set (reg 33) 3124 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") 3125 (match_operand:SI 2 "const_int_operand" "K")) 3126 (const_int 0))) 3127 (set (match_operand:SI 0 "register_operand" "=d") 3128 (plus:SI (match_dup 1) (match_dup 2)))] 3129 "s390_match_ccmode (insn, CCAmode) 3130 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" 3131 "ahi\\t%0,%h2" 3132 [(set_attr "op_type" "RI") 3133 (set_attr "atype" "reg")]) 3134 3135(define_insn "*addsi3_carry1_cc" 3136 [(set (reg 33) 3137 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 3138 (match_operand:SI 2 "general_operand" "d,m")) 3139 (match_dup 1))) 3140 (set (match_operand:SI 0 "register_operand" "=d,d") 3141 (plus:SI (match_dup 1) (match_dup 2)))] 3142 "s390_match_ccmode (insn, CCL1mode)" 3143 "@ 3144 alr\\t%0,%2 3145 al\\t%0,%2" 3146 [(set_attr "op_type" "RR,RX") 3147 (set_attr "atype" "reg,mem")]) 3148 3149(define_insn "*addsi3_carry1_cconly" 3150 [(set (reg 33) 3151 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 3152 (match_operand:SI 2 "general_operand" "d,m")) 3153 (match_dup 1))) 3154 (clobber (match_scratch:SI 0 "=d,d"))] 3155 "s390_match_ccmode (insn, CCL1mode)" 3156 "@ 3157 alr\\t%0,%2 3158 al\\t%0,%2" 3159 [(set_attr "op_type" "RR,RX") 3160 (set_attr "atype" "reg,mem")]) 3161 3162(define_insn "*addsi3_carry2_cc" 3163 [(set (reg 33) 3164 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 3165 (match_operand:SI 2 "general_operand" "d,m")) 3166 (match_dup 2))) 3167 (set (match_operand:SI 0 "register_operand" "=d,d") 3168 (plus:SI (match_dup 1) (match_dup 2)))] 3169 "s390_match_ccmode (insn, CCL1mode)" 3170 "@ 3171 alr\\t%0,%2 3172 al\\t%0,%2" 3173 [(set_attr "op_type" "RR,RX") 3174 (set_attr "atype" "reg,mem")]) 3175 3176(define_insn "*addsi3_carry2_cconly" 3177 [(set (reg 33) 3178 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 3179 (match_operand:SI 2 "general_operand" "d,m")) 3180 (match_dup 2))) 3181 (clobber (match_scratch:SI 0 "=d,d"))] 3182 "s390_match_ccmode (insn, CCL1mode)" 3183 "@ 3184 alr\\t%0,%2 3185 al\\t%0,%2" 3186 [(set_attr "op_type" "RR,RX") 3187 (set_attr "atype" "reg,mem")]) 3188 3189(define_insn "*addsi3_cc" 3190 [(set (reg 33) 3191 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 3192 (match_operand:SI 2 "general_operand" "d,m")) 3193 (const_int 0))) 3194 (set (match_operand:SI 0 "register_operand" "=d,d") 3195 (plus:SI (match_dup 1) (match_dup 2)))] 3196 "s390_match_ccmode (insn, CCLmode)" 3197 "@ 3198 alr\\t%0,%2 3199 al\\t%0,%2" 3200 [(set_attr "op_type" "RR,RX") 3201 (set_attr "atype" "reg,mem")]) 3202 3203(define_insn "*addsi3_cconly" 3204 [(set (reg 33) 3205 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 3206 (match_operand:SI 2 "general_operand" "d,m")) 3207 (const_int 0))) 3208 (clobber (match_scratch:SI 0 "=d,d"))] 3209 "s390_match_ccmode (insn, CCLmode)" 3210 "@ 3211 alr\\t%0,%2 3212 al\\t%0,%2" 3213 [(set_attr "op_type" "RR,RX") 3214 (set_attr "atype" "reg,mem")]) 3215 3216(define_insn "*addsi3_cconly2" 3217 [(set (reg 33) 3218 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0") 3219 (neg:SI (match_operand:SI 2 "general_operand" "d,m")))) 3220 (clobber (match_scratch:SI 0 "=d,d"))] 3221 "s390_match_ccmode(insn, CCLmode)" 3222 "@ 3223 alr\\t%0,%2 3224 al\\t%0,%2" 3225 [(set_attr "op_type" "RR,RX") 3226 (set_attr "atype" "reg,mem")]) 3227 3228(define_insn "*addsi3_sign" 3229 [(set (match_operand:SI 0 "register_operand" "=d") 3230 (plus:SI (match_operand:SI 1 "register_operand" "0") 3231 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m")))) 3232 (clobber (reg:CC 33))] 3233 "" 3234 "ah\\t%0,%2" 3235 [(set_attr "op_type" "RX") 3236 (set_attr "atype" "mem")]) 3237 3238(define_insn "*addsi3_sub" 3239 [(set (match_operand:SI 0 "register_operand" "=d") 3240 (plus:SI (match_operand:SI 1 "register_operand" "0") 3241 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0))) 3242 (clobber (reg:CC 33))] 3243 "" 3244 "ah\\t%0,%2" 3245 [(set_attr "op_type" "RX") 3246 (set_attr "atype" "mem")]) 3247 3248(define_insn "addsi3" 3249 [(set (match_operand:SI 0 "register_operand" "=d,d,d") 3250 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 3251 (match_operand:SI 2 "general_operand" "d,K,m"))) 3252 (clobber (reg:CC 33))] 3253 "" 3254 "@ 3255 ar\\t%0,%2 3256 ahi\\t%0,%h2 3257 a\\t%0,%2" 3258 [(set_attr "op_type" "RR,RI,RX") 3259 (set_attr "atype" "reg,reg,mem")]) 3260 3261(define_insn "*la_31" 3262 [(set (match_operand:SI 0 "register_operand" "=d") 3263 (match_operand:QI 1 "address_operand" "p"))] 3264 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" 3265 "la\\t%0,%a1" 3266 [(set_attr "op_type" "RX") 3267 (set_attr "atype" "mem") 3268 (set_attr "type" "la")]) 3269 3270(define_peephole2 3271 [(parallel 3272 [(set (match_operand:SI 0 "register_operand" "") 3273 (match_operand:QI 1 "address_operand" "")) 3274 (clobber (reg:CC 33))])] 3275 "!TARGET_64BIT 3276 && strict_memory_address_p (VOIDmode, operands[1]) 3277 && preferred_la_operand_p (operands[1])" 3278 [(set (match_dup 0) (match_dup 1))] 3279 "") 3280 3281(define_peephole2 3282 [(set (match_operand:SI 0 "register_operand" "") 3283 (match_operand:SI 1 "register_operand" "")) 3284 (parallel 3285 [(set (match_dup 0) 3286 (plus:SI (match_dup 0) 3287 (match_operand:SI 2 "nonmemory_operand" ""))) 3288 (clobber (reg:CC 33))])] 3289 "!TARGET_64BIT 3290 && !reg_overlap_mentioned_p (operands[0], operands[2]) 3291 && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (SImode, operands[1], operands[2])) 3292 && preferred_la_operand_p (gen_rtx_PLUS (SImode, operands[1], operands[2]))" 3293 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] 3294 "") 3295 3296(define_insn "*la_31_and" 3297 [(set (match_operand:SI 0 "register_operand" "=d") 3298 (and:SI (match_operand:QI 1 "address_operand" "p") 3299 (const_int 2147483647)))] 3300 "!TARGET_64BIT" 3301 "la\\t%0,%a1" 3302 [(set_attr "op_type" "RX") 3303 (set_attr "atype" "mem") 3304 (set_attr "type" "la")]) 3305 3306(define_insn_and_split "*la_31_and_cc" 3307 [(set (match_operand:SI 0 "register_operand" "=d") 3308 (and:SI (match_operand:QI 1 "address_operand" "p") 3309 (const_int 2147483647))) 3310 (clobber (reg:CC 33))] 3311 "!TARGET_64BIT" 3312 "#" 3313 "&& reload_completed" 3314 [(set (match_dup 0) 3315 (and:SI (match_dup 1) (const_int 2147483647)))] 3316 "" 3317 [(set_attr "op_type" "RX") 3318 (set_attr "atype" "mem") 3319 (set_attr "type" "la")]) 3320 3321(define_insn "force_la_31" 3322 [(set (match_operand:SI 0 "register_operand" "=d") 3323 (match_operand:QI 1 "address_operand" "p")) 3324 (use (const_int 0))] 3325 "!TARGET_64BIT" 3326 "la\\t%0,%a1" 3327 [(set_attr "op_type" "RX") 3328 (set_attr "atype" "mem") 3329 (set_attr "type" "la")]) 3330 3331(define_expand "reload_insi" 3332 [(parallel [(match_operand:SI 0 "register_operand" "=a") 3333 (match_operand:SI 1 "s390_plus_operand" "") 3334 (match_operand:SI 2 "register_operand" "=&a")])] 3335 "!TARGET_64BIT" 3336 " 3337{ 3338 s390_expand_plus_operand (operands[0], operands[1], operands[2]); 3339 DONE; 3340}") 3341 3342 3343; 3344; adddf3 instruction pattern(s). 3345; 3346 3347(define_expand "adddf3" 3348 [(parallel 3349 [(set (match_operand:DF 0 "register_operand" "=f,f") 3350 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 3351 (match_operand:DF 2 "general_operand" "f,m"))) 3352 (clobber (reg:CC 33))])] 3353 "TARGET_HARD_FLOAT" 3354 "") 3355 3356(define_insn "*adddf3" 3357 [(set (match_operand:DF 0 "register_operand" "=f,f") 3358 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 3359 (match_operand:DF 2 "general_operand" "f,m"))) 3360 (clobber (reg:CC 33))] 3361 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3362 "@ 3363 adbr\\t%0,%2 3364 adb\\t%0,%2" 3365 [(set_attr "op_type" "RRE,RXE") 3366 (set_attr "atype" "reg,mem")]) 3367 3368(define_insn "*adddf3_ibm" 3369 [(set (match_operand:DF 0 "register_operand" "=f,f") 3370 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 3371 (match_operand:DF 2 "general_operand" "f,m"))) 3372 (clobber (reg:CC 33))] 3373 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 3374 "@ 3375 adr\\t%0,%2 3376 ad\\t%0,%2" 3377 [(set_attr "op_type" "RR,RX") 3378 (set_attr "atype" "reg,mem")]) 3379 3380; 3381; addsf3 instruction pattern(s). 3382; 3383 3384(define_expand "addsf3" 3385 [(parallel 3386 [(set (match_operand:SF 0 "register_operand" "=f,f") 3387 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 3388 (match_operand:SF 2 "general_operand" "f,m"))) 3389 (clobber (reg:CC 33))])] 3390 "TARGET_HARD_FLOAT" 3391 "") 3392 3393(define_insn "*addsf3" 3394 [(set (match_operand:SF 0 "register_operand" "=f,f") 3395 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 3396 (match_operand:SF 2 "general_operand" "f,m"))) 3397 (clobber (reg:CC 33))] 3398 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3399 "@ 3400 aebr\\t%0,%2 3401 aeb\\t%0,%2" 3402 [(set_attr "op_type" "RRE,RXE") 3403 (set_attr "atype" "reg,mem")]) 3404 3405(define_insn "*addsf3" 3406 [(set (match_operand:SF 0 "register_operand" "=f,f") 3407 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 3408 (match_operand:SF 2 "general_operand" "f,m"))) 3409 (clobber (reg:CC 33))] 3410 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 3411 "@ 3412 aer\\t%0,%2 3413 ae\\t%0,%2" 3414 [(set_attr "op_type" "RR,RX") 3415 (set_attr "atype" "reg,mem")]) 3416 3417 3418;; 3419;;- Subtract instructions. 3420;; 3421 3422; 3423; subdi3 instruction pattern(s). 3424; 3425 3426(define_insn "*subdi3_sign" 3427 [(set (match_operand:DI 0 "register_operand" "=d,d") 3428 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3429 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) 3430 (clobber (reg:CC 33))] 3431 "TARGET_64BIT" 3432 "@ 3433 sgfr\\t%0,%2 3434 sgf\\t%0,%2" 3435 [(set_attr "op_type" "RRE,RXE") 3436 (set_attr "atype" "reg,mem")]) 3437 3438(define_insn "*subdi3_zero_cc" 3439 [(set (reg 33) 3440 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3441 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) 3442 (const_int 0))) 3443 (set (match_operand:DI 0 "register_operand" "=d,d") 3444 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] 3445 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 3446 "@ 3447 slgfr\\t%0,%2 3448 slgf\\t%0,%2" 3449 [(set_attr "op_type" "RRE,RXE") 3450 (set_attr "atype" "reg,mem")]) 3451 3452(define_insn "*subdi3_zero_cconly" 3453 [(set (reg 33) 3454 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3455 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) 3456 (const_int 0))) 3457 (clobber (match_scratch:DI 0 "=d,d"))] 3458 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" 3459 "@ 3460 slgfr\\t%0,%2 3461 slgf\\t%0,%2" 3462 [(set_attr "op_type" "RRE,RXE") 3463 (set_attr "atype" "reg,mem")]) 3464 3465(define_insn "*subdi3_zero" 3466 [(set (match_operand:DI 0 "register_operand" "=d,d") 3467 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3468 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) 3469 (clobber (reg:CC 33))] 3470 "TARGET_64BIT" 3471 "@ 3472 slgfr\\t%0,%2 3473 slgf\\t%0,%2" 3474 [(set_attr "op_type" "RRE,RXE") 3475 (set_attr "atype" "reg,mem")]) 3476 3477(define_insn "*subdi3_cc" 3478 [(set (reg 33) 3479 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3480 (match_operand:DI 2 "general_operand" "d,m")) 3481 (const_int 0))) 3482 (set (match_operand:DI 0 "register_operand" "=d,d") 3483 (minus:DI (match_dup 1) (match_dup 2)))] 3484 "s390_match_ccmode (insn, CCLmode)" 3485 "@ 3486 slgr\\t%0,%2 3487 slg\\t%0,%2" 3488 [(set_attr "op_type" "RRE,RXE") 3489 (set_attr "atype" "reg,mem")]) 3490 3491(define_insn "*subdi3_cconly" 3492 [(set (reg 33) 3493 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3494 (match_operand:DI 2 "general_operand" "d,m")) 3495 (const_int 0))) 3496 (clobber (match_scratch:DI 0 "=d,d"))] 3497 "s390_match_ccmode (insn, CCLmode)" 3498 "@ 3499 slgr\\t%0,%2 3500 slg\\t%0,%2" 3501 [(set_attr "op_type" "RRE,RXE") 3502 (set_attr "atype" "reg,mem")]) 3503 3504(define_insn "*subdi3_64" 3505 [(set (match_operand:DI 0 "register_operand" "=d,d") 3506 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 3507 (match_operand:DI 2 "general_operand" "d,m") ) ) 3508 (clobber (reg:CC 33))] 3509 "TARGET_64BIT" 3510 "@ 3511 sgr\\t%0,%2 3512 sg\\t%0,%2" 3513 [(set_attr "op_type" "RRE,RRE") 3514 (set_attr "atype" "reg,mem")]) 3515 3516(define_insn_and_split "*subdi3_31" 3517 [(set (match_operand:DI 0 "register_operand" "=&d") 3518 (minus:DI (match_operand:DI 1 "register_operand" "0") 3519 (match_operand:DI 2 "general_operand" "do") ) ) 3520 (clobber (reg:CC 33))] 3521 "!TARGET_64BIT" 3522 "#" 3523 "&& reload_completed" 3524 [(parallel 3525 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) 3526 (clobber (reg:CC 33))]) 3527 (parallel 3528 [(set (reg:CCL2 33) 3529 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) 3530 (match_dup 7))) 3531 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) 3532 (set (pc) 3533 (if_then_else (gtu (reg:CCL2 33) (const_int 0)) 3534 (pc) 3535 (label_ref (match_dup 9)))) 3536 (parallel 3537 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) 3538 (clobber (reg:CC 33))]) 3539 (match_dup 9)] 3540 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 3541 operands[4] = operand_subword (operands[1], 0, 0, DImode); 3542 operands[5] = operand_subword (operands[2], 0, 0, DImode); 3543 operands[6] = operand_subword (operands[0], 1, 0, DImode); 3544 operands[7] = operand_subword (operands[1], 1, 0, DImode); 3545 operands[8] = operand_subword (operands[2], 1, 0, DImode); 3546 operands[9] = gen_label_rtx ();" 3547 [(set_attr "op_type" "NN")]) 3548 3549(define_expand "subdi3" 3550 [(parallel 3551 [(set (match_operand:DI 0 "register_operand" "") 3552 (minus:DI (match_operand:DI 1 "register_operand" "") 3553 (match_operand:DI 2 "general_operand" ""))) 3554 (clobber (reg:CC 33))])] 3555 "" 3556 "") 3557 3558; 3559; subsi3 instruction pattern(s). 3560; 3561 3562(define_insn "*subsi3_borrow_cc" 3563 [(set (reg 33) 3564 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") 3565 (match_operand:SI 2 "general_operand" "d,m")) 3566 (match_dup 1))) 3567 (set (match_operand:SI 0 "register_operand" "=d,d") 3568 (minus:SI (match_dup 1) (match_dup 2)))] 3569 "s390_match_ccmode(insn, CCL2mode)" 3570 "@ 3571 slr\\t%0,%2 3572 sl\\t%0,%2" 3573 [(set_attr "op_type" "RR,RX") 3574 (set_attr "atype" "reg,mem")]) 3575 3576(define_insn "*subsi3_borrow_cconly" 3577 [(set (reg 33) 3578 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") 3579 (match_operand:SI 2 "general_operand" "d,m")) 3580 (match_dup 1))) 3581 (clobber (match_scratch:SI 0 "=d,d"))] 3582 "s390_match_ccmode(insn, CCL2mode)" 3583 "@ 3584 slr\\t%0,%2 3585 sl\\t%0,%2" 3586 [(set_attr "op_type" "RR,RX") 3587 (set_attr "atype" "reg,mem")]) 3588 3589(define_insn "*subsi3_cc" 3590 [(set (reg 33) 3591 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") 3592 (match_operand:SI 2 "general_operand" "d,m")) 3593 (const_int 0))) 3594 (set (match_operand:SI 0 "register_operand" "=d,d") 3595 (minus:SI (match_dup 1) (match_dup 2)))] 3596 "s390_match_ccmode(insn, CCLmode)" 3597 "@ 3598 slr\\t%0,%2 3599 sl\\t%0,%2" 3600 [(set_attr "op_type" "RR,RX") 3601 (set_attr "atype" "reg,mem")]) 3602 3603(define_insn "*subsi3_cconly" 3604 [(set (reg 33) 3605 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") 3606 (match_operand:SI 2 "general_operand" "d,m")) 3607 (const_int 0))) 3608 (clobber (match_scratch:SI 0 "=d,d"))] 3609 "s390_match_ccmode(insn, CCLmode)" 3610 "@ 3611 slr\\t%0,%2 3612 sl\\t%0,%2" 3613 [(set_attr "op_type" "RR,RX") 3614 (set_attr "atype" "reg,mem")]) 3615 3616(define_insn "*subsi3_sign" 3617 [(set (match_operand:SI 0 "register_operand" "=d") 3618 (minus:SI (match_operand:SI 1 "register_operand" "0") 3619 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m")))) 3620 (clobber (reg:CC 33))] 3621 "" 3622 "sh\\t%0,%2" 3623 [(set_attr "op_type" "RX") 3624 (set_attr "atype" "mem")]) 3625 3626(define_insn "*subsi3_sub" 3627 [(set (match_operand:SI 0 "register_operand" "=d") 3628 (minus:SI (match_operand:SI 1 "register_operand" "0") 3629 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0))) 3630 (clobber (reg:CC 33))] 3631 "" 3632 "sh\\t%0,%2" 3633 [(set_attr "op_type" "RX") 3634 (set_attr "atype" "mem")]) 3635 3636(define_insn "subsi3" 3637 [(set (match_operand:SI 0 "register_operand" "=d,d") 3638 (minus:SI (match_operand:SI 1 "register_operand" "0,0") 3639 (match_operand:SI 2 "general_operand" "d,m"))) 3640 (clobber (reg:CC 33))] 3641 "" 3642 "@ 3643 sr\\t%0,%2 3644 s\\t%0,%2" 3645 [(set_attr "op_type" "RR,RX") 3646 (set_attr "atype" "reg,mem")]) 3647 3648 3649; 3650; subdf3 instruction pattern(s). 3651; 3652 3653(define_expand "subdf3" 3654 [(parallel 3655 [(set (match_operand:DF 0 "register_operand" "=f,f") 3656 (minus:DF (match_operand:DF 1 "register_operand" "0,0") 3657 (match_operand:DF 2 "general_operand" "f,m"))) 3658 (clobber (reg:CC 33))])] 3659 "TARGET_HARD_FLOAT" 3660 "") 3661 3662(define_insn "*subdf3" 3663 [(set (match_operand:DF 0 "register_operand" "=f,f") 3664 (minus:DF (match_operand:DF 1 "register_operand" "0,0") 3665 (match_operand:DF 2 "general_operand" "f,m"))) 3666 (clobber (reg:CC 33))] 3667 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3668 "@ 3669 sdbr\\t%0,%2 3670 sdb\\t%0,%2" 3671 [(set_attr "op_type" "RRE,RXE") 3672 (set_attr "atype" "reg,mem")]) 3673 3674(define_insn "*subdf3_ibm" 3675 [(set (match_operand:DF 0 "register_operand" "=f,f") 3676 (minus:DF (match_operand:DF 1 "register_operand" "0,0") 3677 (match_operand:DF 2 "general_operand" "f,m"))) 3678 (clobber (reg:CC 33))] 3679 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 3680 "@ 3681 sdr\\t%0,%2 3682 sd\\t%0,%2" 3683 [(set_attr "op_type" "RR,RX") 3684 (set_attr "atype" "reg,mem")]) 3685 3686; 3687; subsf3 instruction pattern(s). 3688; 3689 3690(define_expand "subsf3" 3691 [(parallel 3692 [(set (match_operand:SF 0 "register_operand" "=f,f") 3693 (minus:SF (match_operand:SF 1 "register_operand" "0,0") 3694 (match_operand:SF 2 "general_operand" "f,m"))) 3695 (clobber (reg:CC 33))])] 3696 "TARGET_HARD_FLOAT" 3697 "") 3698 3699(define_insn "*subsf3" 3700 [(set (match_operand:SF 0 "register_operand" "=f,f") 3701 (minus:SF (match_operand:SF 1 "register_operand" "0,0") 3702 (match_operand:SF 2 "general_operand" "f,m"))) 3703 (clobber (reg:CC 33))] 3704 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3705 "@ 3706 sebr\\t%0,%2 3707 seb\\t%0,%2" 3708 [(set_attr "op_type" "RRE,RXE") 3709 (set_attr "atype" "reg,mem")]) 3710 3711(define_insn "*subsf3_ibm" 3712 [(set (match_operand:SF 0 "register_operand" "=f,f") 3713 (minus:SF (match_operand:SF 1 "register_operand" "0,0") 3714 (match_operand:SF 2 "general_operand" "f,m"))) 3715 (clobber (reg:CC 33))] 3716 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 3717 "@ 3718 ser\\t%0,%2 3719 se\\t%0,%2" 3720 [(set_attr "op_type" "RR,RX") 3721 (set_attr "atype" "reg,mem")]) 3722 3723 3724;; 3725;;- Multiply instructions. 3726;; 3727 3728; 3729; muldi3 instruction pattern(s). 3730; 3731 3732(define_insn "*muldi3_sign" 3733 [(set (match_operand:DI 0 "register_operand" "=d,d") 3734 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) 3735 (match_operand:DI 1 "register_operand" "0,0")))] 3736 "TARGET_64BIT" 3737 "@ 3738 msgfr\\t%0,%2 3739 msgf\\t%0,%2" 3740 [(set_attr "op_type" "RRE,RXE") 3741 (set_attr "atype" "reg,mem") 3742 (set_attr "type" "imul")]) 3743 3744 3745(define_insn "muldi3" 3746 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 3747 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") 3748 (match_operand:DI 2 "general_operand" "d,K,m")))] 3749 "TARGET_64BIT" 3750 "@ 3751 msgr\\t%0,%2 3752 mghi\\t%0,%h2 3753 msg\\t%0,%2" 3754 [(set_attr "op_type" "RRE,RI,RXE") 3755 (set_attr "atype" "reg,reg,mem") 3756 (set_attr "type" "imul")]) 3757 3758; 3759; mulsi3 instruction pattern(s). 3760; 3761 3762(define_insn "mulsi3" 3763 [(set (match_operand:SI 0 "register_operand" "=d,d,d") 3764 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") 3765 (match_operand:SI 2 "general_operand" "d,K,m")))] 3766 "" 3767 "@ 3768 msr\\t%0,%2 3769 mhi\\t%0,%h2 3770 ms\\t%0,%2" 3771 [(set_attr "op_type" "RRE,RI,RX") 3772 (set_attr "atype" "reg,reg,mem") 3773 (set_attr "type" "imul")]) 3774 3775; 3776; mulsidi3 instruction pattern(s). 3777; 3778 3779(define_expand "mulsidi3" 3780 [(set (match_operand:DI 0 "register_operand" "") 3781 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")) 3782 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))] 3783 "!TARGET_64BIT" 3784 " 3785{ 3786 rtx insn; 3787 3788 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1])); 3789 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2])); 3790 3791 REG_NOTES (insn) = 3792 gen_rtx_EXPR_LIST (REG_EQUAL, 3793 gen_rtx_MULT (DImode, 3794 gen_rtx_SIGN_EXTEND (DImode, operands[1]), 3795 gen_rtx_SIGN_EXTEND (DImode, operands[2])), 3796 REG_NOTES (insn)); 3797 DONE; 3798}") 3799 3800(define_insn "mulsi_6432" 3801 [(set (match_operand:DI 0 "register_operand" "=d,d") 3802 (mult:DI (sign_extend:DI 3803 (truncate:SI (match_operand:DI 1 "register_operand" "0,0"))) 3804 (sign_extend:DI 3805 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] 3806 "!TARGET_64BIT" 3807 "@ 3808 mr\\t%0,%2 3809 m\\t%0,%2" 3810 [(set_attr "op_type" "RR,RX") 3811 (set_attr "atype" "reg,mem") 3812 (set_attr "type" "imul")]) 3813 3814; 3815; muldf3 instruction pattern(s). 3816; 3817 3818(define_expand "muldf3" 3819 [(parallel 3820 [(set (match_operand:DF 0 "register_operand" "=f,f") 3821 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 3822 (match_operand:DF 2 "general_operand" "f,m"))) 3823 (clobber (reg:CC 33))])] 3824 "TARGET_HARD_FLOAT" 3825 "") 3826 3827(define_insn "*muldf3" 3828 [(set (match_operand:DF 0 "register_operand" "=f,f") 3829 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 3830 (match_operand:DF 2 "general_operand" "f,m"))) 3831 (clobber (reg:CC 33))] 3832 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3833 "@ 3834 mdbr\\t%0,%2 3835 mdb\\t%0,%2" 3836 [(set_attr "op_type" "RRE,RXE") 3837 (set_attr "type" "fmul") 3838 (set_attr "atype" "reg,mem")]) 3839 3840(define_insn "*muldf3_ibm" 3841 [(set (match_operand:DF 0 "register_operand" "=f,f") 3842 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") 3843 (match_operand:DF 2 "general_operand" "f,m"))) 3844 (clobber (reg:CC 33))] 3845 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 3846 "@ 3847 mdr\\t%0,%2 3848 md\\t%0,%2" 3849 [(set_attr "op_type" "RR,RX") 3850 (set_attr "type" "fmul") 3851 (set_attr "atype" "reg,mem")]) 3852 3853; 3854; mulsf3 instruction pattern(s). 3855; 3856 3857(define_expand "mulsf3" 3858 [(parallel 3859 [(set (match_operand:SF 0 "register_operand" "=f,f") 3860 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 3861 (match_operand:SF 2 "general_operand" "f,m"))) 3862 (clobber (reg:CC 33))])] 3863 "TARGET_HARD_FLOAT" 3864 "") 3865 3866(define_insn "*mulsf3" 3867 [(set (match_operand:SF 0 "register_operand" "=f,f") 3868 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 3869 (match_operand:SF 2 "general_operand" "f,m"))) 3870 (clobber (reg:CC 33))] 3871 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 3872 "@ 3873 meebr\\t%0,%2 3874 meeb\\t%0,%2" 3875 [(set_attr "op_type" "RRE,RXE") 3876 (set_attr "type" "fmul") 3877 (set_attr "atype" "reg,mem")]) 3878 3879(define_insn "*mulsf3_ibm" 3880 [(set (match_operand:SF 0 "register_operand" "=f,f") 3881 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") 3882 (match_operand:SF 2 "general_operand" "f,m"))) 3883 (clobber (reg:CC 33))] 3884 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 3885 "@ 3886 mer\\t%0,%2 3887 me\\t%0,%2" 3888 [(set_attr "op_type" "RR,RX") 3889 (set_attr "type" "fmul") 3890 (set_attr "atype" "reg,mem")]) 3891 3892 3893;; 3894;;- Divide and modulo instructions. 3895;; 3896 3897; 3898; divmoddi4 instruction pattern(s). 3899; 3900 3901(define_expand "divmoddi4" 3902 [(parallel [(set (match_operand:DI 0 "general_operand" "") 3903 (div:DI (match_operand:DI 1 "general_operand" "") 3904 (match_operand:DI 2 "general_operand" ""))) 3905 (set (match_operand:DI 3 "general_operand" "") 3906 (mod:DI (match_dup 1) (match_dup 2)))]) 3907 (clobber (match_dup 4))] 3908 "TARGET_64BIT" 3909 " 3910{ 3911 rtx insn, div_equal, mod_equal, equal; 3912 3913 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); 3914 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); 3915 equal = gen_rtx_IOR (TImode, 3916 gen_rtx_ZERO_EXTEND (TImode, div_equal), 3917 gen_rtx_ASHIFT (TImode, 3918 gen_rtx_ZERO_EXTEND (TImode, mod_equal), 3919 GEN_INT (64))); 3920 3921 operands[4] = gen_reg_rtx(TImode); 3922 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); 3923 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); 3924 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); 3925 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2])); 3926 REG_NOTES (insn) = 3927 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 3928 3929 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); 3930 REG_NOTES (insn) = 3931 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); 3932 3933 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); 3934 REG_NOTES (insn) = 3935 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); 3936 3937 DONE; 3938}") 3939 3940(define_insn "divmodtidi3" 3941 [(set (match_operand:TI 0 "register_operand" "=d,d") 3942 (ior:TI 3943 (zero_extend:TI 3944 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0")) 3945 (match_operand:DI 2 "general_operand" "d,m"))) 3946 (ashift:TI 3947 (zero_extend:TI 3948 (mod:DI (truncate:DI (match_dup 1)) 3949 (match_dup 2))) 3950 (const_int 64))))] 3951 "TARGET_64BIT" 3952 "@ 3953 dsgr\\t%0,%2 3954 dsg\\t%0,%2" 3955 [(set_attr "op_type" "RRE,RXE") 3956 (set_attr "type" "idiv") 3957 (set_attr "atype" "reg,mem")]) 3958 3959(define_insn "divmodtisi3" 3960 [(set (match_operand:TI 0 "register_operand" "=d,d") 3961 (ior:TI 3962 (zero_extend:TI 3963 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0")) 3964 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")))) 3965 (ashift:TI 3966 (zero_extend:TI 3967 (mod:DI (truncate:DI (match_dup 1)) 3968 (sign_extend:DI (match_dup 2)))) 3969 (const_int 64))))] 3970 "TARGET_64BIT" 3971 "@ 3972 dsgfr\\t%0,%2 3973 dsgf\\t%0,%2" 3974 [(set_attr "op_type" "RRE,RXE") 3975 (set_attr "type" "idiv") 3976 (set_attr "atype" "reg,mem")]) 3977 3978; 3979; udivmoddi4 instruction pattern(s). 3980; 3981 3982(define_expand "udivmoddi4" 3983 [(parallel [(set (match_operand:DI 0 "general_operand" "") 3984 (udiv:DI (match_operand:DI 1 "general_operand" "") 3985 (match_operand:DI 2 "nonimmediate_operand" ""))) 3986 (set (match_operand:DI 3 "general_operand" "") 3987 (umod:DI (match_dup 1) (match_dup 2)))]) 3988 (clobber (match_dup 4))] 3989 "TARGET_64BIT" 3990 " 3991{ 3992 rtx insn, div_equal, mod_equal, equal; 3993 3994 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); 3995 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); 3996 equal = gen_rtx_IOR (TImode, 3997 gen_rtx_ZERO_EXTEND (TImode, div_equal), 3998 gen_rtx_ASHIFT (TImode, 3999 gen_rtx_ZERO_EXTEND (TImode, mod_equal), 4000 GEN_INT (64))); 4001 4002 operands[4] = gen_reg_rtx(TImode); 4003 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); 4004 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); 4005 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); 4006 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); 4007 REG_NOTES (insn) = 4008 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4009 4010 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); 4011 REG_NOTES (insn) = 4012 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); 4013 4014 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); 4015 REG_NOTES (insn) = 4016 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); 4017 4018 DONE; 4019}") 4020 4021(define_insn "udivmodtidi3" 4022 [(set (match_operand:TI 0 "register_operand" "=d,d") 4023 (ior:TI (zero_extend:TI 4024 (truncate:DI 4025 (udiv:TI (match_operand:TI 1 "register_operand" "0,0") 4026 (zero_extend:TI 4027 (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) 4028 (ashift:TI 4029 (zero_extend:TI 4030 (truncate:DI 4031 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2))))) 4032 (const_int 64))))] 4033 "TARGET_64BIT" 4034 "@ 4035 dlgr\\t%0,%2 4036 dlg\\t%0,%2" 4037 [(set_attr "op_type" "RRE,RXE") 4038 (set_attr "type" "idiv") 4039 (set_attr "atype" "reg,mem")]) 4040 4041; 4042; divmodsi4 instruction pattern(s). 4043; 4044 4045(define_expand "divmodsi4" 4046 [(parallel [(set (match_operand:SI 0 "general_operand" "") 4047 (div:SI (match_operand:SI 1 "general_operand" "") 4048 (match_operand:SI 2 "nonimmediate_operand" ""))) 4049 (set (match_operand:SI 3 "general_operand" "") 4050 (mod:SI (match_dup 1) (match_dup 2)))]) 4051 (clobber (match_dup 4))] 4052 "!TARGET_64BIT" 4053 " 4054{ 4055 rtx insn, div_equal, mod_equal, equal; 4056 4057 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); 4058 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); 4059 equal = gen_rtx_IOR (DImode, 4060 gen_rtx_ZERO_EXTEND (DImode, div_equal), 4061 gen_rtx_ASHIFT (DImode, 4062 gen_rtx_ZERO_EXTEND (DImode, mod_equal), 4063 GEN_INT (32))); 4064 4065 operands[4] = gen_reg_rtx(DImode); 4066 emit_insn (gen_extendsidi2 (operands[4], operands[1])); 4067 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); 4068 REG_NOTES (insn) = 4069 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4070 4071 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); 4072 REG_NOTES (insn) = 4073 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); 4074 4075 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); 4076 REG_NOTES (insn) = 4077 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); 4078 4079 DONE; 4080}") 4081 4082(define_insn "divmoddisi3" 4083 [(set (match_operand:DI 0 "register_operand" "=d,d") 4084 (ior:DI (zero_extend:DI 4085 (truncate:SI 4086 (div:DI (match_operand:DI 1 "register_operand" "0,0") 4087 (sign_extend:DI 4088 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) 4089 (ashift:DI 4090 (zero_extend:DI 4091 (truncate:SI 4092 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2))))) 4093 (const_int 32))))] 4094 "!TARGET_64BIT" 4095 "@ 4096 dr\\t%0,%2 4097 d\\t%0,%2" 4098 [(set_attr "op_type" "RR,RX") 4099 (set_attr "type" "idiv") 4100 (set_attr "atype" "reg,mem")]) 4101 4102; 4103; udivsi3 and umodsi3 instruction pattern(s). 4104; 4105 4106 4107(define_expand "udivsi3" 4108 [(set (match_operand:SI 0 "register_operand" "=d") 4109 (udiv:SI (match_operand:SI 1 "general_operand" "") 4110 (match_operand:SI 2 "general_operand" ""))) 4111 (clobber (match_dup 3))] 4112 "!TARGET_64BIT" 4113 " 4114{ 4115 rtx insn, udiv_equal, umod_equal, equal; 4116 4117 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 4118 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 4119 equal = gen_rtx_IOR (DImode, 4120 gen_rtx_ZERO_EXTEND (DImode, udiv_equal), 4121 gen_rtx_ASHIFT (DImode, 4122 gen_rtx_ZERO_EXTEND (DImode, umod_equal), 4123 GEN_INT (32))); 4124 4125 operands[3] = gen_reg_rtx (DImode); 4126 4127 if (CONSTANT_P (operands[2])) 4128 { 4129 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 4130 { 4131 rtx label1 = gen_label_rtx (); 4132 4133 operands[1] = make_safe_from (operands[1], operands[0]); 4134 emit_move_insn (operands[0], const0_rtx); 4135 emit_insn (gen_cmpsi (operands[1], operands[2])); 4136 emit_jump_insn (gen_bltu (label1)); 4137 emit_move_insn (operands[0], const1_rtx); 4138 emit_label (label1); 4139 } 4140 else 4141 { 4142 operands[2] = force_reg (SImode, operands[2]); 4143 operands[2] = make_safe_from (operands[2], operands[0]); 4144 4145 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 4146 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 4147 operands[2])); 4148 REG_NOTES (insn) = 4149 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4150 4151 insn = emit_move_insn (operands[0], 4152 gen_lowpart (SImode, operands[3])); 4153 REG_NOTES (insn) = 4154 gen_rtx_EXPR_LIST (REG_EQUAL, 4155 udiv_equal, REG_NOTES (insn)); 4156 } 4157 } 4158 else 4159 { 4160 rtx label1 = gen_label_rtx (); 4161 rtx label2 = gen_label_rtx (); 4162 rtx label3 = gen_label_rtx (); 4163 4164 operands[1] = force_reg (SImode, operands[1]); 4165 operands[1] = make_safe_from (operands[1], operands[0]); 4166 operands[2] = force_reg (SImode, operands[2]); 4167 operands[2] = make_safe_from (operands[2], operands[0]); 4168 4169 emit_move_insn (operands[0], const0_rtx); 4170 emit_insn (gen_cmpsi (operands[2], operands[1])); 4171 emit_jump_insn (gen_bgtu (label3)); 4172 emit_insn (gen_cmpsi (operands[2], const1_rtx)); 4173 emit_jump_insn (gen_blt (label2)); 4174 emit_insn (gen_cmpsi (operands[2], const1_rtx)); 4175 emit_jump_insn (gen_beq (label1)); 4176 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 4177 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 4178 operands[2])); 4179 REG_NOTES (insn) = 4180 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4181 4182 insn = emit_move_insn (operands[0], 4183 gen_lowpart (SImode, operands[3])); 4184 REG_NOTES (insn) = 4185 gen_rtx_EXPR_LIST (REG_EQUAL, 4186 udiv_equal, REG_NOTES (insn)); 4187 emit_jump (label3); 4188 emit_label (label1); 4189 emit_move_insn (operands[0], operands[1]); 4190 emit_jump (label3); 4191 emit_label (label2); 4192 emit_move_insn (operands[0], const1_rtx); 4193 emit_label (label3); 4194 } 4195 emit_move_insn (operands[0], operands[0]); 4196 DONE; 4197}") 4198 4199(define_expand "umodsi3" 4200 [(set (match_operand:SI 0 "register_operand" "=d") 4201 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") 4202 (match_operand:SI 2 "nonimmediate_operand" ""))) 4203 (clobber (match_dup 3))] 4204 "!TARGET_64BIT" 4205 " 4206{ 4207 rtx insn, udiv_equal, umod_equal, equal; 4208 4209 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 4210 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 4211 equal = gen_rtx_IOR (DImode, 4212 gen_rtx_ZERO_EXTEND (DImode, udiv_equal), 4213 gen_rtx_ASHIFT (DImode, 4214 gen_rtx_ZERO_EXTEND (DImode, umod_equal), 4215 GEN_INT (32))); 4216 4217 operands[3] = gen_reg_rtx (DImode); 4218 4219 if (CONSTANT_P (operands[2])) 4220 { 4221 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) 4222 { 4223 rtx label1 = gen_label_rtx (); 4224 4225 operands[1] = make_safe_from (operands[1], operands[0]); 4226 emit_move_insn (operands[0], operands[1]); 4227 emit_insn (gen_cmpsi (operands[0], operands[2])); 4228 emit_jump_insn (gen_bltu (label1)); 4229 emit_insn (gen_abssi2 (operands[0], operands[2])); 4230 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); 4231 emit_label (label1); 4232 } 4233 else 4234 { 4235 operands[2] = force_reg (SImode, operands[2]); 4236 operands[2] = make_safe_from (operands[2], operands[0]); 4237 4238 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 4239 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 4240 operands[2])); 4241 REG_NOTES (insn) = 4242 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4243 4244 insn = emit_move_insn (operands[0], 4245 gen_highpart (SImode, operands[3])); 4246 REG_NOTES (insn) = 4247 gen_rtx_EXPR_LIST (REG_EQUAL, 4248 umod_equal, REG_NOTES (insn)); 4249 } 4250 } 4251 else 4252 { 4253 rtx label1 = gen_label_rtx (); 4254 rtx label2 = gen_label_rtx (); 4255 rtx label3 = gen_label_rtx (); 4256 4257 operands[1] = force_reg (SImode, operands[1]); 4258 operands[1] = make_safe_from (operands[1], operands[0]); 4259 operands[2] = force_reg (SImode, operands[2]); 4260 operands[2] = make_safe_from (operands[2], operands[0]); 4261 4262 emit_move_insn(operands[0], operands[1]); 4263 emit_insn (gen_cmpsi (operands[2], operands[1])); 4264 emit_jump_insn (gen_bgtu (label3)); 4265 emit_insn (gen_cmpsi (operands[2], const1_rtx)); 4266 emit_jump_insn (gen_blt (label2)); 4267 emit_insn (gen_cmpsi (operands[2], const1_rtx)); 4268 emit_jump_insn (gen_beq (label1)); 4269 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 4270 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 4271 operands[2])); 4272 REG_NOTES (insn) = 4273 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); 4274 4275 insn = emit_move_insn (operands[0], 4276 gen_highpart (SImode, operands[3])); 4277 REG_NOTES (insn) = 4278 gen_rtx_EXPR_LIST (REG_EQUAL, 4279 umod_equal, REG_NOTES (insn)); 4280 emit_jump (label3); 4281 emit_label (label1); 4282 emit_move_insn (operands[0], const0_rtx); 4283 emit_jump (label3); 4284 emit_label (label2); 4285 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); 4286 emit_label (label3); 4287 } 4288 DONE; 4289}") 4290 4291; 4292; divdf3 instruction pattern(s). 4293; 4294 4295(define_expand "divdf3" 4296 [(parallel 4297 [(set (match_operand:DF 0 "register_operand" "=f,f") 4298 (div:DF (match_operand:DF 1 "register_operand" "0,0") 4299 (match_operand:DF 2 "general_operand" "f,m"))) 4300 (clobber (reg:CC 33))])] 4301 "TARGET_HARD_FLOAT" 4302 "") 4303 4304(define_insn "*divdf3" 4305 [(set (match_operand:DF 0 "register_operand" "=f,f") 4306 (div:DF (match_operand:DF 1 "register_operand" "0,0") 4307 (match_operand:DF 2 "general_operand" "f,m"))) 4308 (clobber (reg:CC 33))] 4309 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 4310 "@ 4311 ddbr\\t%0,%2 4312 ddb\\t%0,%2" 4313 [(set_attr "op_type" "RRE,RXE") 4314 (set_attr "type" "fdiv") 4315 (set_attr "atype" "reg,mem")]) 4316 4317(define_insn "*divdf3_ibm" 4318 [(set (match_operand:DF 0 "register_operand" "=f,f") 4319 (div:DF (match_operand:DF 1 "register_operand" "0,0") 4320 (match_operand:DF 2 "general_operand" "f,m"))) 4321 (clobber (reg:CC 33))] 4322 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 4323 "@ 4324 ddr\\t%0,%2 4325 dd\\t%0,%2" 4326 [(set_attr "op_type" "RR,RX") 4327 (set_attr "type" "fdiv") 4328 (set_attr "atype" "reg,mem")]) 4329 4330; 4331; divsf3 instruction pattern(s). 4332; 4333 4334(define_expand "divsf3" 4335 [(parallel 4336 [(set (match_operand:SF 0 "register_operand" "=f,f") 4337 (div:SF (match_operand:SF 1 "register_operand" "0,0") 4338 (match_operand:SF 2 "general_operand" "f,m"))) 4339 (clobber (reg:CC 33))])] 4340 "TARGET_HARD_FLOAT" 4341 "") 4342 4343(define_insn "*divsf3" 4344 [(set (match_operand:SF 0 "register_operand" "=f,f") 4345 (div:SF (match_operand:SF 1 "register_operand" "0,0") 4346 (match_operand:SF 2 "general_operand" "f,m"))) 4347 (clobber (reg:CC 33))] 4348 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 4349 "@ 4350 debr\\t%0,%2 4351 deb\\t%0,%2" 4352 [(set_attr "op_type" "RRE,RXE") 4353 (set_attr "type" "fdiv") 4354 (set_attr "atype" "reg,mem")]) 4355 4356(define_insn "*divsf3" 4357 [(set (match_operand:SF 0 "register_operand" "=f,f") 4358 (div:SF (match_operand:SF 1 "register_operand" "0,0") 4359 (match_operand:SF 2 "general_operand" "f,m"))) 4360 (clobber (reg:CC 33))] 4361 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 4362 "@ 4363 der\\t%0,%2 4364 de\\t%0,%2" 4365 [(set_attr "op_type" "RR,RX") 4366 (set_attr "type" "fdiv") 4367 (set_attr "atype" "reg,mem")]) 4368 4369 4370;; 4371;;- And instructions. 4372;; 4373 4374; 4375; anddi3 instruction pattern(s). 4376; 4377 4378(define_insn "*anddi3_cc" 4379 [(set (reg 33) 4380 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 4381 (match_operand:DI 2 "general_operand" "d,m")) 4382 (const_int 0))) 4383 (set (match_operand:DI 0 "register_operand" "=d,d") 4384 (and:DI (match_dup 1) (match_dup 2)))] 4385 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 4386 "@ 4387 ngr\\t%0,%2 4388 ng\\t%0,%2" 4389 [(set_attr "op_type" "RRE,RXE") 4390 (set_attr "atype" "reg,mem")]) 4391 4392(define_insn "*anddi3_cconly" 4393 [(set (reg 33) 4394 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 4395 (match_operand:DI 2 "general_operand" "d,m")) 4396 (const_int 0))) 4397 (clobber (match_scratch:DI 0 "=d,d"))] 4398 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 4399 "@ 4400 ngr\\t%0,%2 4401 ng\\t%0,%2" 4402 [(set_attr "op_type" "RRE,RXE") 4403 (set_attr "atype" "reg,mem")]) 4404 4405(define_insn "*anddi3_ni" 4406 [(set (match_operand:DI 0 "register_operand" "=d") 4407 (and:DI (match_operand:DI 1 "nonimmediate_operand" "0") 4408 (match_operand:DI 2 "immediate_operand" "n"))) 4409 (clobber (reg:CC 33))] 4410 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0" 4411 "* 4412{ 4413 int part = s390_single_hi (operands[2], DImode, -1); 4414 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part)); 4415 4416 switch (part) 4417 { 4418 case 0: return \"nihh\\t%0,%x2\"; 4419 case 1: return \"nihl\\t%0,%x2\"; 4420 case 2: return \"nilh\\t%0,%x2\"; 4421 case 3: return \"nill\\t%0,%x2\"; 4422 default: abort (); 4423 } 4424}" 4425 [(set_attr "op_type" "RI") 4426 (set_attr "atype" "reg")]) 4427 4428(define_insn "anddi3" 4429 [(set (match_operand:DI 0 "register_operand" "=d,d") 4430 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 4431 (match_operand:DI 2 "general_operand" "d,m"))) 4432 (clobber (reg:CC 33))] 4433 "TARGET_64BIT" 4434 "@ 4435 ngr\\t%0,%2 4436 ng\\t%0,%2" 4437 [(set_attr "op_type" "RRE,RXE") 4438 (set_attr "atype" "reg,mem")]) 4439 4440(define_insn "*anddi3_ss" 4441 [(set (match_operand:DI 0 "s_operand" "=Q") 4442 (and:DI (match_dup 0) 4443 (match_operand:DI 1 "s_imm_operand" "Q"))) 4444 (clobber (reg:CC 33))] 4445 "" 4446 "nc\\t%O0(8,%R0),%1" 4447 [(set_attr "op_type" "SS") 4448 (set_attr "atype" "mem")]) 4449 4450(define_insn "*anddi3_ss_inv" 4451 [(set (match_operand:DI 0 "s_operand" "=Q") 4452 (and:DI (match_operand:DI 1 "s_imm_operand" "Q") 4453 (match_dup 0))) 4454 (clobber (reg:CC 33))] 4455 "" 4456 "nc\\t%O0(8,%R0),%1" 4457 [(set_attr "op_type" "SS") 4458 (set_attr "atype" "mem")]) 4459 4460; 4461; andsi3 instruction pattern(s). 4462; 4463 4464(define_insn "*andsi3_cc" 4465 [(set (reg 33) 4466 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 4467 (match_operand:SI 2 "general_operand" "d,m")) 4468 (const_int 0))) 4469 (set (match_operand:SI 0 "register_operand" "=d,d") 4470 (and:SI (match_dup 1) (match_dup 2)))] 4471 "s390_match_ccmode(insn, CCTmode)" 4472 "@ 4473 nr\\t%0,%2 4474 n\\t%0,%2" 4475 [(set_attr "op_type" "RR,RX") 4476 (set_attr "atype" "reg,mem")]) 4477 4478(define_insn "*andsi3_cconly" 4479 [(set (reg 33) 4480 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 4481 (match_operand:SI 2 "general_operand" "d,m")) 4482 (const_int 0))) 4483 (clobber (match_scratch:SI 0 "=d,d"))] 4484 "s390_match_ccmode(insn, CCTmode)" 4485 "@ 4486 nr\\t%0,%2 4487 n\\t%0,%2" 4488 [(set_attr "op_type" "RR,RX") 4489 (set_attr "atype" "reg,mem")]) 4490 4491(define_insn "*andsi3_ni" 4492 [(set (match_operand:SI 0 "register_operand" "=d") 4493 (and:SI (match_operand:SI 1 "nonimmediate_operand" "0") 4494 (match_operand:SI 2 "immediate_operand" "n"))) 4495 (clobber (reg:CC 33))] 4496 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0" 4497 "* 4498{ 4499 int part = s390_single_hi (operands[2], SImode, -1); 4500 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); 4501 4502 switch (part) 4503 { 4504 case 0: return \"nilh\\t%0,%x2\"; 4505 case 1: return \"nill\\t%0,%x2\"; 4506 default: abort (); 4507 } 4508}" 4509 [(set_attr "op_type" "RI") 4510 (set_attr "atype" "reg")]) 4511 4512(define_insn "andsi3" 4513 [(set (match_operand:SI 0 "register_operand" "=d,d") 4514 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 4515 (match_operand:SI 2 "general_operand" "d,m"))) 4516 (clobber (reg:CC 33))] 4517 "" 4518 "@ 4519 nr\\t%0,%2 4520 n\\t%0,%2" 4521 [(set_attr "op_type" "RR,RX") 4522 (set_attr "atype" "reg,mem")]) 4523 4524(define_insn "*andsi3_ss" 4525 [(set (match_operand:SI 0 "s_operand" "=Q") 4526 (and:SI (match_dup 0) 4527 (match_operand:SI 1 "s_imm_operand" "Q"))) 4528 (clobber (reg:CC 33))] 4529 "" 4530 "nc\\t%O0(4,%R0),%1" 4531 [(set_attr "op_type" "SS") 4532 (set_attr "atype" "mem")]) 4533 4534(define_insn "*andsi3_ss_inv" 4535 [(set (match_operand:SI 0 "s_operand" "=Q") 4536 (and:SI (match_operand:SI 1 "s_imm_operand" "Q") 4537 (match_dup 0))) 4538 (clobber (reg:CC 33))] 4539 "" 4540 "nc\\t%O0(4,%R0),%1" 4541 [(set_attr "op_type" "SS") 4542 (set_attr "atype" "mem")]) 4543 4544; 4545; andhi3 instruction pattern(s). 4546; 4547 4548(define_insn "*andhi3_ni" 4549 [(set (match_operand:HI 0 "register_operand" "=d,d") 4550 (and:HI (match_operand:HI 1 "register_operand" "%0,0") 4551 (match_operand:HI 2 "nonmemory_operand" "d,n"))) 4552 (clobber (reg:CC 33))] 4553 "TARGET_64BIT" 4554 "@ 4555 nr\\t%0,%2 4556 nill\\t%0,%x2" 4557 [(set_attr "op_type" "RR,RI") 4558 (set_attr "atype" "reg")]) 4559 4560(define_insn "andhi3" 4561 [(set (match_operand:HI 0 "register_operand" "=d") 4562 (and:HI (match_operand:HI 1 "register_operand" "%0") 4563 (match_operand:HI 2 "nonmemory_operand" "d"))) 4564 (clobber (reg:CC 33))] 4565 "" 4566 "nr\\t%0,%2" 4567 [(set_attr "op_type" "RR") 4568 (set_attr "atype" "reg")]) 4569 4570(define_insn "*andhi3_ss" 4571 [(set (match_operand:HI 0 "s_operand" "=Q") 4572 (and:HI (match_dup 0) 4573 (match_operand:HI 1 "s_imm_operand" "Q"))) 4574 (clobber (reg:CC 33))] 4575 "" 4576 "nc\\t%O0(2,%R0),%1" 4577 [(set_attr "op_type" "SS") 4578 (set_attr "atype" "mem")]) 4579 4580(define_insn "*andhi3_ss_inv" 4581 [(set (match_operand:HI 0 "s_operand" "=Q") 4582 (and:HI (match_operand:HI 1 "s_imm_operand" "Q") 4583 (match_dup 0))) 4584 (clobber (reg:CC 33))] 4585 "" 4586 "nc\\t%O0(2,%R0),%1" 4587 [(set_attr "op_type" "SS") 4588 (set_attr "atype" "mem")]) 4589 4590; 4591; andqi3 instruction pattern(s). 4592; 4593 4594(define_insn "*andqi3_ni" 4595 [(set (match_operand:QI 0 "register_operand" "=d,d") 4596 (and:QI (match_operand:QI 1 "register_operand" "%0,0") 4597 (match_operand:QI 2 "nonmemory_operand" "d,n"))) 4598 (clobber (reg:CC 33))] 4599 "TARGET_64BIT" 4600 "@ 4601 nr\\t%0,%2 4602 nill\\t%0,%b2" 4603 [(set_attr "op_type" "RR,RI") 4604 (set_attr "atype" "reg")]) 4605 4606(define_insn "andqi3" 4607 [(set (match_operand:QI 0 "register_operand" "=d") 4608 (and:QI (match_operand:QI 1 "register_operand" "%0") 4609 (match_operand:QI 2 "nonmemory_operand" "d"))) 4610 (clobber (reg:CC 33))] 4611 "" 4612 "nr\\t%0,%2" 4613 [(set_attr "op_type" "RR") 4614 (set_attr "atype" "reg")]) 4615 4616(define_insn "*andqi3_ss" 4617 [(set (match_operand:QI 0 "s_operand" "=Q,Q") 4618 (and:QI (match_dup 0) 4619 (match_operand:QI 1 "s_imm_operand" "n,Q"))) 4620 (clobber (reg:CC 33))] 4621 "" 4622 "@ 4623 ni\\t%0,%b1 4624 nc\\t%O0(1,%R0),%1" 4625 [(set_attr "op_type" "SI,SS") 4626 (set_attr "atype" "mem")]) 4627 4628(define_insn "*andqi3_ss_inv" 4629 [(set (match_operand:QI 0 "s_operand" "=Q,Q") 4630 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q") 4631 (match_dup 0))) 4632 (clobber (reg:CC 33))] 4633 "" 4634 "@ 4635 ni\\t%0,%b1 4636 nc\\t%O0(1,%R0),%1" 4637 [(set_attr "op_type" "SI,SS") 4638 (set_attr "atype" "mem")]) 4639 4640 4641;; 4642;;- Bit set (inclusive or) instructions. 4643;; 4644 4645; 4646; iordi3 instruction pattern(s). 4647; 4648 4649(define_insn "*iordi3_cc" 4650 [(set (reg 33) 4651 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 4652 (match_operand:DI 2 "general_operand" "d,m")) 4653 (const_int 0))) 4654 (set (match_operand:DI 0 "register_operand" "=d,d") 4655 (ior:DI (match_dup 1) (match_dup 2)))] 4656 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 4657 "@ 4658 ogr\\t%0,%2 4659 og\\t%0,%2" 4660 [(set_attr "op_type" "RRE,RXE") 4661 (set_attr "atype" "reg,mem")]) 4662 4663(define_insn "*iordi3_cconly" 4664 [(set (reg 33) 4665 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 4666 (match_operand:DI 2 "general_operand" "d,m")) 4667 (const_int 0))) 4668 (clobber (match_scratch:DI 0 "=d,d"))] 4669 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 4670 "@ 4671 ogr\\t%0,%2 4672 og\\t%0,%2" 4673 [(set_attr "op_type" "RRE,RXE") 4674 (set_attr "atype" "reg,mem")]) 4675 4676(define_insn "*iordi3_oi" 4677 [(set (match_operand:DI 0 "register_operand" "=d") 4678 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "0") 4679 (match_operand:DI 2 "immediate_operand" "n"))) 4680 (clobber (reg:CC 33))] 4681 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0" 4682 "* 4683{ 4684 int part = s390_single_hi (operands[2], DImode, 0); 4685 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part)); 4686 4687 switch (part) 4688 { 4689 case 0: return \"oihh\\t%0,%x2\"; 4690 case 1: return \"oihl\\t%0,%x2\"; 4691 case 2: return \"oilh\\t%0,%x2\"; 4692 case 3: return \"oill\\t%0,%x2\"; 4693 default: abort (); 4694 } 4695}" 4696 [(set_attr "op_type" "RI") 4697 (set_attr "atype" "reg")]) 4698 4699(define_insn "iordi3" 4700 [(set (match_operand:DI 0 "register_operand" "=d,d") 4701 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 4702 (match_operand:DI 2 "general_operand" "d,m"))) 4703 (clobber (reg:CC 33))] 4704 "TARGET_64BIT" 4705 "@ 4706 ogr\\t%0,%2 4707 og\\t%0,%2" 4708 [(set_attr "op_type" "RRE,RXE") 4709 (set_attr "atype" "reg,mem")]) 4710 4711(define_insn "*iordi3_ss" 4712 [(set (match_operand:DI 0 "s_operand" "=Q") 4713 (ior:DI (match_dup 0) 4714 (match_operand:DI 1 "s_imm_operand" "Q"))) 4715 (clobber (reg:CC 33))] 4716 "" 4717 "oc\\t%O0(8,%R0),%1" 4718 [(set_attr "op_type" "SS") 4719 (set_attr "atype" "mem")]) 4720 4721(define_insn "*iordi3_ss_inv" 4722 [(set (match_operand:DI 0 "s_operand" "=Q") 4723 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q") 4724 (match_dup 0))) 4725 (clobber (reg:CC 33))] 4726 "" 4727 "oc\\t%O0(8,%R0),%1" 4728 [(set_attr "op_type" "SS") 4729 (set_attr "atype" "mem")]) 4730 4731; 4732; iorsi3 instruction pattern(s). 4733; 4734 4735(define_insn "*iorsi3_cc" 4736 [(set (reg 33) 4737 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 4738 (match_operand:SI 2 "general_operand" "d,m")) 4739 (const_int 0))) 4740 (set (match_operand:SI 0 "register_operand" "=d,d") 4741 (ior:SI (match_dup 1) (match_dup 2)))] 4742 "s390_match_ccmode(insn, CCTmode)" 4743 "@ 4744 or\\t%0,%2 4745 o\\t%0,%2" 4746 [(set_attr "op_type" "RR,RX") 4747 (set_attr "atype" "reg,mem")]) 4748 4749(define_insn "*iorsi3_cconly" 4750 [(set (reg 33) 4751 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 4752 (match_operand:SI 2 "general_operand" "d,m")) 4753 (const_int 0))) 4754 (clobber (match_scratch:SI 0 "=d,d"))] 4755 "s390_match_ccmode(insn, CCTmode)" 4756 "@ 4757 or\\t%0,%2 4758 o\\t%0,%2" 4759 [(set_attr "op_type" "RR,RX") 4760 (set_attr "atype" "reg,mem")]) 4761 4762(define_insn "*iorsi3_oi" 4763 [(set (match_operand:SI 0 "register_operand" "=d") 4764 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0") 4765 (match_operand:SI 2 "immediate_operand" "n"))) 4766 (clobber (reg:CC 33))] 4767 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0" 4768 "* 4769{ 4770 int part = s390_single_hi (operands[2], SImode, 0); 4771 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); 4772 4773 switch (part) 4774 { 4775 case 0: return \"oilh\\t%0,%x2\"; 4776 case 1: return \"oill\\t%0,%x2\"; 4777 default: abort (); 4778 } 4779}" 4780 [(set_attr "op_type" "RI") 4781 (set_attr "atype" "reg")]) 4782 4783(define_insn "iorsi3" 4784 [(set (match_operand:SI 0 "register_operand" "=d,d") 4785 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 4786 (match_operand:SI 2 "general_operand" "d,m"))) 4787 (clobber (reg:CC 33))] 4788 "" 4789 "@ 4790 or\\t%0,%2 4791 o\\t%0,%2" 4792 [(set_attr "op_type" "RR,RX") 4793 (set_attr "atype" "reg,mem")]) 4794 4795(define_insn "*iorsi3_ss" 4796 [(set (match_operand:SI 0 "s_operand" "=Q") 4797 (ior:SI (match_dup 0) 4798 (match_operand:SI 1 "s_imm_operand" "Q"))) 4799 (clobber (reg:CC 33))] 4800 "" 4801 "oc\\t%O0(4,%R0),%1" 4802 [(set_attr "op_type" "SS") 4803 (set_attr "atype" "mem")]) 4804 4805(define_insn "*iorsi3_ss_inv" 4806 [(set (match_operand:SI 0 "s_operand" "=Q") 4807 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q") 4808 (match_dup 0))) 4809 (clobber (reg:CC 33))] 4810 "" 4811 "oc\\t%O0(4,%R0),%1" 4812 [(set_attr "op_type" "SS") 4813 (set_attr "atype" "mem")]) 4814 4815; 4816; iorhi3 instruction pattern(s). 4817; 4818 4819(define_insn "*iorhi3_oi" 4820 [(set (match_operand:HI 0 "register_operand" "=d,d") 4821 (ior:HI (match_operand:HI 1 "register_operand" "%0,0") 4822 (match_operand:HI 2 "nonmemory_operand" "d,n"))) 4823 (clobber (reg:CC 33))] 4824 "TARGET_64BIT" 4825 "@ 4826 or\\t%0,%2 4827 oill\\t%0,%x2" 4828 [(set_attr "op_type" "RR,RI") 4829 (set_attr "atype" "reg")]) 4830 4831(define_insn "iorhi3" 4832 [(set (match_operand:HI 0 "register_operand" "=d") 4833 (ior:HI (match_operand:HI 1 "register_operand" "%0") 4834 (match_operand:HI 2 "nonmemory_operand" "d"))) 4835 (clobber (reg:CC 33))] 4836 "" 4837 "or\\t%0,%2" 4838 [(set_attr "op_type" "RR") 4839 (set_attr "atype" "reg")]) 4840 4841(define_insn "*iorhi3_ss" 4842 [(set (match_operand:HI 0 "s_operand" "=Q") 4843 (ior:HI (match_dup 0) 4844 (match_operand:HI 1 "s_imm_operand" "Q"))) 4845 (clobber (reg:CC 33))] 4846 "" 4847 "oc\\t%O0(2,%R0),%1" 4848 [(set_attr "op_type" "SS") 4849 (set_attr "atype" "mem")]) 4850 4851(define_insn "*iorhi3_ss_inv" 4852 [(set (match_operand:HI 0 "s_operand" "=Q") 4853 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q") 4854 (match_dup 0))) 4855 (clobber (reg:CC 33))] 4856 "" 4857 "oc\\t%O0(2,%R0),%1" 4858 [(set_attr "op_type" "SS") 4859 (set_attr "atype" "mem")]) 4860 4861; 4862; iorqi3 instruction pattern(s). 4863; 4864 4865(define_insn "*iorqi3_oi" 4866 [(set (match_operand:QI 0 "register_operand" "=d,d") 4867 (ior:QI (match_operand:QI 1 "register_operand" "%0,0") 4868 (match_operand:QI 2 "nonmemory_operand" "d,n"))) 4869 (clobber (reg:CC 33))] 4870 "TARGET_64BIT" 4871 "@ 4872 or\\t%0,%2 4873 oill\\t%0,%b2" 4874 [(set_attr "op_type" "RR,RI") 4875 (set_attr "atype" "reg")]) 4876 4877(define_insn "iorqi3" 4878 [(set (match_operand:QI 0 "register_operand" "=d") 4879 (ior:QI (match_operand:QI 1 "register_operand" "%0") 4880 (match_operand:QI 2 "nonmemory_operand" "d"))) 4881 (clobber (reg:CC 33))] 4882 "" 4883 "or\\t%0,%2" 4884 [(set_attr "op_type" "RR") 4885 (set_attr "atype" "reg")]) 4886 4887(define_insn "*iorqi3_ss" 4888 [(set (match_operand:QI 0 "s_operand" "=Q,Q") 4889 (ior:QI (match_dup 0) 4890 (match_operand:QI 1 "s_imm_operand" "n,Q"))) 4891 (clobber (reg:CC 33))] 4892 "" 4893 "@ 4894 oi\\t%0,%b1 4895 oc\\t%O0(1,%R0),%1" 4896 [(set_attr "op_type" "SI,SS") 4897 (set_attr "atype" "reg,mem")]) 4898 4899(define_insn "*iorqi3_ss_inv" 4900 [(set (match_operand:QI 0 "s_operand" "=Q,Q") 4901 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q") 4902 (match_dup 0))) 4903 (clobber (reg:CC 33))] 4904 "" 4905 "@ 4906 oi\\t%0,%b1 4907 oc\\t%O0(1,%R0),%1" 4908 [(set_attr "op_type" "SI,SS") 4909 (set_attr "atype" "reg,mem")]) 4910 4911 4912;; 4913;;- Xor instructions. 4914;; 4915 4916; 4917; xordi3 instruction pattern(s). 4918; 4919 4920(define_insn "*xordi3_cc" 4921 [(set (reg 33) 4922 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 4923 (match_operand:DI 2 "general_operand" "d,m")) 4924 (const_int 0))) 4925 (set (match_operand:DI 0 "register_operand" "=d,d") 4926 (xor:DI (match_dup 1) (match_dup 2)))] 4927 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 4928 "@ 4929 xgr\\t%0,%2 4930 xg\\t%0,%2" 4931 [(set_attr "op_type" "RRE,RXE") 4932 (set_attr "atype" "reg,mem")]) 4933 4934(define_insn "*xordi3_cconly" 4935 [(set (reg 33) 4936 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 4937 (match_operand:DI 2 "general_operand" "d,m")) 4938 (const_int 0))) 4939 (clobber (match_scratch:DI 0 "=d,d"))] 4940 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" 4941 "@ 4942 xgr\\t%0,%2 4943 xr\\t%0,%2" 4944 [(set_attr "op_type" "RRE,RXE") 4945 (set_attr "atype" "reg,mem")]) 4946 4947(define_insn "xordi3" 4948 [(set (match_operand:DI 0 "register_operand" "=d,d") 4949 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 4950 (match_operand:DI 2 "general_operand" "d,m"))) 4951 (clobber (reg:CC 33))] 4952 "TARGET_64BIT" 4953 "@ 4954 xgr\\t%0,%2 4955 xg\\t%0,%2" 4956 [(set_attr "op_type" "RRE,RXE") 4957 (set_attr "atype" "reg,mem")]) 4958 4959(define_insn "*xordi3_ss" 4960 [(set (match_operand:DI 0 "s_operand" "=Q") 4961 (xor:DI (match_dup 0) 4962 (match_operand:DI 1 "s_imm_operand" "Q"))) 4963 (clobber (reg:CC 33))] 4964 "" 4965 "xc\\t%O0(8,%R0),%1" 4966 [(set_attr "op_type" "SS") 4967 (set_attr "atype" "mem")]) 4968 4969(define_insn "*xordi3_ss_inv" 4970 [(set (match_operand:DI 0 "s_operand" "=Q") 4971 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q") 4972 (match_dup 0))) 4973 (clobber (reg:CC 33))] 4974 "" 4975 "xc\\t%O0(8,%R0),%1" 4976 [(set_attr "op_type" "SS") 4977 (set_attr "atype" "mem")]) 4978 4979; 4980; xorsi3 instruction pattern(s). 4981; 4982 4983(define_insn "*xorsi3_cc" 4984 [(set (reg 33) 4985 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 4986 (match_operand:SI 2 "general_operand" "d,m")) 4987 (const_int 0))) 4988 (set (match_operand:SI 0 "register_operand" "=d,d") 4989 (xor:SI (match_dup 1) (match_dup 2)))] 4990 "s390_match_ccmode(insn, CCTmode)" 4991 "@ 4992 xr\\t%0,%2 4993 x\\t%0,%2" 4994 [(set_attr "op_type" "RR,RX") 4995 (set_attr "atype" "reg,mem")]) 4996 4997(define_insn "*xorsi3_cconly" 4998 [(set (reg 33) 4999 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 5000 (match_operand:SI 2 "general_operand" "d,m")) 5001 (const_int 0))) 5002 (clobber (match_scratch:SI 0 "=d,d"))] 5003 "s390_match_ccmode(insn, CCTmode)" 5004 "@ 5005 xr\\t%0,%2 5006 x\\t%0,%2" 5007 [(set_attr "op_type" "RR,RX") 5008 (set_attr "atype" "reg,mem")]) 5009 5010(define_insn "xorsi3" 5011 [(set (match_operand:SI 0 "register_operand" "=d,d") 5012 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 5013 (match_operand:SI 2 "general_operand" "d,m"))) 5014 (clobber (reg:CC 33))] 5015 "" 5016 "@ 5017 xr\\t%0,%2 5018 x\\t%0,%2" 5019 [(set_attr "op_type" "RR,RX") 5020 (set_attr "atype" "reg,mem")]) 5021 5022(define_insn "*xorsi3_ss" 5023 [(set (match_operand:SI 0 "s_operand" "=Q") 5024 (xor:SI (match_dup 0) 5025 (match_operand:SI 1 "s_imm_operand" "Q"))) 5026 (clobber (reg:CC 33))] 5027 "" 5028 "xc\\t%O0(4,%R0),%1" 5029 [(set_attr "op_type" "SS") 5030 (set_attr "atype" "mem")]) 5031 5032(define_insn "*xorsi3_ss_inv" 5033 [(set (match_operand:SI 0 "s_operand" "=Q") 5034 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q") 5035 (match_dup 0))) 5036 (clobber (reg:CC 33))] 5037 "" 5038 "xc\\t%O0(4,%R0),%1" 5039 [(set_attr "op_type" "SS") 5040 (set_attr "atype" "mem")]) 5041 5042; 5043; xorhi3 instruction pattern(s). 5044; 5045 5046(define_insn "xorhi3" 5047 [(set (match_operand:HI 0 "register_operand" "=d") 5048 (xor:HI (match_operand:HI 1 "register_operand" "%0") 5049 (match_operand:HI 2 "nonmemory_operand" "d"))) 5050 (clobber (reg:CC 33))] 5051 "" 5052 "xr\\t%0,%2" 5053 [(set_attr "op_type" "RR") 5054 (set_attr "atype" "reg")]) 5055 5056(define_insn "*xorhi3_ss" 5057 [(set (match_operand:HI 0 "s_operand" "=Q") 5058 (xor:HI (match_dup 0) 5059 (match_operand:HI 1 "s_imm_operand" "Q"))) 5060 (clobber (reg:CC 33))] 5061 "" 5062 "xc\\t%O0(2,%R0),%1" 5063 [(set_attr "op_type" "SS") 5064 (set_attr "atype" "mem")]) 5065 5066(define_insn "*xorhi3_ss_inv" 5067 [(set (match_operand:HI 0 "s_operand" "=Q") 5068 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q") 5069 (match_dup 0))) 5070 (clobber (reg:CC 33))] 5071 "" 5072 "xc\\t%O0(2,%R0),%1" 5073 [(set_attr "op_type" "SS") 5074 (set_attr "atype" "mem")]) 5075 5076; 5077; xorqi3 instruction pattern(s). 5078; 5079 5080(define_insn "xorqi3" 5081 [(set (match_operand:QI 0 "register_operand" "=d") 5082 (xor:QI (match_operand:QI 1 "register_operand" "%0") 5083 (match_operand:QI 2 "nonmemory_operand" "d"))) 5084 (clobber (reg:CC 33))] 5085 "" 5086 "xr\\t%0,%2" 5087 [(set_attr "op_type" "RR") 5088 (set_attr "atype" "reg")]) 5089 5090(define_insn "*xorqi3_ss" 5091 [(set (match_operand:QI 0 "s_operand" "=Q,Q") 5092 (xor:QI (match_dup 0) 5093 (match_operand:QI 1 "s_imm_operand" "n,Q"))) 5094 (clobber (reg:CC 33))] 5095 "" 5096 "@ 5097 xi\\t%0,%b1 5098 xc\\t%O0(1,%R0),%1" 5099 [(set_attr "op_type" "SI,SS") 5100 (set_attr "atype" "mem")]) 5101 5102(define_insn "*xorqi3_ss_inv" 5103 [(set (match_operand:QI 0 "s_operand" "=Q,Q") 5104 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q") 5105 (match_dup 0))) 5106 (clobber (reg:CC 33))] 5107 "" 5108 "@ 5109 xi\\t%0,%b1 5110 xc\\t%O0(1,%R0),%1" 5111 [(set_attr "op_type" "SI,SS") 5112 (set_attr "atype" "mem")]) 5113 5114 5115;; 5116;;- Negate instructions. 5117;; 5118 5119; 5120; negdi2 instruction pattern(s). 5121; 5122 5123(define_expand "negdi2" 5124 [(parallel 5125 [(set (match_operand:DI 0 "register_operand" "=d") 5126 (neg:DI (match_operand:DI 1 "register_operand" "d"))) 5127 (clobber (reg:CC 33))])] 5128 "" 5129 "") 5130 5131(define_insn "*negdi2_64" 5132 [(set (match_operand:DI 0 "register_operand" "=d") 5133 (neg:DI (match_operand:DI 1 "register_operand" "d"))) 5134 (clobber (reg:CC 33))] 5135 "TARGET_64BIT" 5136 "lcgr\\t%0,%1" 5137 [(set_attr "op_type" "RR")]) 5138 5139(define_insn "*negdi2_31" 5140 [(set (match_operand:DI 0 "register_operand" "=d") 5141 (neg:DI (match_operand:DI 1 "register_operand" "d"))) 5142 (clobber (reg:CC 33))] 5143 "!TARGET_64BIT" 5144 "* 5145{ 5146 rtx xop[1]; 5147 xop[0] = gen_label_rtx (); 5148 output_asm_insn (\"lcr\\t%0,%1\", operands); 5149 output_asm_insn (\"lcr\\t%N0,%N1\", operands); 5150 output_asm_insn (\"je\\t%l0\", xop); 5151 output_asm_insn (\"bctr\\t%0,0\", operands); 5152 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", 5153 CODE_LABEL_NUMBER (xop[0])); 5154 return \"\"; 5155}" 5156 [(set_attr "op_type" "NN") 5157 (set_attr "type" "other") 5158 (set_attr "length" "10")]) 5159 5160; 5161; negsi2 instruction pattern(s). 5162; 5163 5164(define_insn "negsi2" 5165 [(set (match_operand:SI 0 "register_operand" "=d") 5166 (neg:SI (match_operand:SI 1 "register_operand" "d"))) 5167 (clobber (reg:CC 33))] 5168 "" 5169 "lcr\\t%0,%1" 5170 [(set_attr "op_type" "RR")]) 5171 5172; 5173; negdf2 instruction pattern(s). 5174; 5175 5176(define_expand "negdf2" 5177 [(parallel 5178 [(set (match_operand:DF 0 "register_operand" "=f") 5179 (neg:DF (match_operand:DF 1 "register_operand" "f"))) 5180 (clobber (reg:CC 33))])] 5181 "TARGET_HARD_FLOAT" 5182 "") 5183 5184(define_insn "*negdf2" 5185 [(set (match_operand:DF 0 "register_operand" "=f") 5186 (neg:DF (match_operand:DF 1 "register_operand" "f"))) 5187 (clobber (reg:CC 33))] 5188 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5189 "lcdbr\\t%0,%1" 5190 [(set_attr "op_type" "RRE")]) 5191 5192(define_insn "*negdf2_ibm" 5193 [(set (match_operand:DF 0 "register_operand" "=f") 5194 (neg:DF (match_operand:DF 1 "register_operand" "f"))) 5195 (clobber (reg:CC 33))] 5196 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 5197 "lcdr\\t%0,%1" 5198 [(set_attr "op_type" "RR")]) 5199 5200; 5201; negsf2 instruction pattern(s). 5202; 5203 5204(define_expand "negsf2" 5205 [(parallel 5206 [(set (match_operand:SF 0 "register_operand" "=f") 5207 (neg:SF (match_operand:SF 1 "register_operand" "f"))) 5208 (clobber (reg:CC 33))])] 5209 "TARGET_HARD_FLOAT" 5210 "") 5211 5212(define_insn "*negsf2" 5213 [(set (match_operand:SF 0 "register_operand" "=f") 5214 (neg:SF (match_operand:SF 1 "register_operand" "f"))) 5215 (clobber (reg:CC 33))] 5216 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5217 "lcebr\\t%0,%1" 5218 [(set_attr "op_type" "RRE")]) 5219 5220(define_insn "*negsf2" 5221 [(set (match_operand:SF 0 "register_operand" "=f") 5222 (neg:SF (match_operand:SF 1 "register_operand" "f"))) 5223 (clobber (reg:CC 33))] 5224 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 5225 "lcer\\t%0,%1" 5226 [(set_attr "op_type" "RR")]) 5227 5228 5229;; 5230;;- Absolute value instructions. 5231;; 5232 5233; 5234; absdi2 instruction pattern(s). 5235; 5236 5237(define_insn "absdi2" 5238 [(set (match_operand:DI 0 "register_operand" "=d") 5239 (abs:DI (match_operand:DI 1 "register_operand" "d"))) 5240 (clobber (reg:CC 33))] 5241 "TARGET_64BIT" 5242 "lpgr\\t%0,%1" 5243 [(set_attr "op_type" "RRE")]) 5244 5245; 5246; abssi2 instruction pattern(s). 5247; 5248 5249(define_insn "abssi2" 5250 [(set (match_operand:SI 0 "register_operand" "=d") 5251 (abs:SI (match_operand:SI 1 "register_operand" "d"))) 5252 (clobber (reg:CC 33))] 5253 "" 5254 "lpr\\t%0,%1" 5255 [(set_attr "op_type" "RR")]) 5256 5257; 5258; absdf2 instruction pattern(s). 5259; 5260 5261(define_expand "absdf2" 5262 [(parallel 5263 [(set (match_operand:DF 0 "register_operand" "=f") 5264 (abs:DF (match_operand:DF 1 "register_operand" "f"))) 5265 (clobber (reg:CC 33))])] 5266 "TARGET_HARD_FLOAT" 5267 "") 5268 5269(define_insn "*absdf2" 5270 [(set (match_operand:DF 0 "register_operand" "=f") 5271 (abs:DF (match_operand:DF 1 "register_operand" "f"))) 5272 (clobber (reg:CC 33))] 5273 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5274 "lpdbr\\t%0,%1" 5275 [(set_attr "op_type" "RRE")]) 5276 5277(define_insn "*absdf2_ibm" 5278 [(set (match_operand:DF 0 "register_operand" "=f") 5279 (abs:DF (match_operand:DF 1 "register_operand" "f"))) 5280 (clobber (reg:CC 33))] 5281 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 5282 "lpdr\\t%0,%1" 5283 [(set_attr "op_type" "RR")]) 5284 5285; 5286; abssf2 instruction pattern(s). 5287; 5288 5289(define_expand "abssf2" 5290 [(parallel 5291 [(set (match_operand:SF 0 "register_operand" "=f") 5292 (abs:SF (match_operand:SF 1 "register_operand" "f"))) 5293 (clobber (reg:CC 33))])] 5294 "TARGET_HARD_FLOAT" 5295 "") 5296 5297(define_insn "*abssf2" 5298 [(set (match_operand:SF 0 "register_operand" "=f") 5299 (abs:SF (match_operand:SF 1 "register_operand" "f"))) 5300 (clobber (reg:CC 33))] 5301 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5302 "lpebr\\t%0,%1" 5303 [(set_attr "op_type" "RRE")]) 5304 5305(define_insn "*abssf2_ibm" 5306 [(set (match_operand:SF 0 "register_operand" "=f") 5307 (abs:SF (match_operand:SF 1 "register_operand" "f"))) 5308 (clobber (reg:CC 33))] 5309 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" 5310 "lper\\t%0,%1" 5311 [(set_attr "op_type" "RR")]) 5312 5313;; 5314;;- Square root instructions. 5315;; 5316 5317; 5318; sqrtdf2 instruction pattern(s). 5319; 5320 5321(define_insn "sqrtdf2" 5322 [(set (match_operand:DF 0 "register_operand" "=f,f") 5323 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))] 5324 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5325 "@ 5326 sqdbr\\t%0,%1 5327 sqdb\\t%0,%1" 5328 [(set_attr "op_type" "RRE,RSE")]) 5329 5330; 5331; sqrtsf2 instruction pattern(s). 5332; 5333 5334(define_insn "sqrtsf2" 5335 [(set (match_operand:SF 0 "register_operand" "=f,f") 5336 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))] 5337 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" 5338 "@ 5339 sqebr\\t%0,%1 5340 sqeb\\t%0,%1" 5341 [(set_attr "op_type" "RRE,RSE")]) 5342 5343;; 5344;;- One complement instructions. 5345;; 5346 5347; 5348; one_cmpldi2 instruction pattern(s). 5349; 5350 5351(define_expand "one_cmpldi2" 5352 [(parallel 5353 [(set (match_operand:DI 0 "register_operand" "") 5354 (xor:DI (match_operand:DI 1 "register_operand" "") 5355 (const_int -1))) 5356 (clobber (reg:CC 33))])] 5357 "TARGET_64BIT" 5358 "") 5359 5360; 5361; one_cmplsi2 instruction pattern(s). 5362; 5363 5364(define_expand "one_cmplsi2" 5365 [(parallel 5366 [(set (match_operand:SI 0 "register_operand" "") 5367 (xor:SI (match_operand:SI 1 "register_operand" "") 5368 (const_int -1))) 5369 (clobber (reg:CC 33))])] 5370 "" 5371 "") 5372 5373; 5374; one_cmplhi2 instruction pattern(s). 5375; 5376 5377(define_expand "one_cmplhi2" 5378 [(parallel 5379 [(set (match_operand:HI 0 "register_operand" "") 5380 (xor:HI (match_operand:HI 1 "register_operand" "") 5381 (const_int -1))) 5382 (clobber (reg:CC 33))])] 5383 "" 5384 "") 5385 5386; 5387; one_cmplqi2 instruction pattern(s). 5388; 5389 5390(define_expand "one_cmplqi2" 5391 [(parallel 5392 [(set (match_operand:QI 0 "register_operand" "") 5393 (xor:QI (match_operand:QI 1 "register_operand" "") 5394 (const_int -1))) 5395 (clobber (reg:CC 33))])] 5396 "" 5397 "") 5398 5399 5400;; 5401;;- Rotate instructions. 5402;; 5403 5404; 5405; rotldi3 instruction pattern(s). 5406; 5407 5408(define_insn "rotldi3" 5409 [(set (match_operand:DI 0 "register_operand" "=d,d") 5410 (rotate:DI (match_operand:DI 1 "register_operand" "d,d") 5411 (match_operand:SI 2 "nonmemory_operand" "J,a")))] 5412 "TARGET_64BIT" 5413 "@ 5414 rllg\\t%0,%1,%c2 5415 rllg\\t%0,%1,0(%2)" 5416 [(set_attr "op_type" "RSE")]) 5417 5418; 5419; rotlsi3 instruction pattern(s). 5420; 5421 5422(define_insn "rotlsi3" 5423 [(set (match_operand:SI 0 "register_operand" "=d,d") 5424 (rotate:SI (match_operand:SI 1 "register_operand" "d,d") 5425 (match_operand:SI 2 "nonmemory_operand" "J,a")))] 5426 "TARGET_64BIT" 5427 "@ 5428 rll\\t%0,%1,%c2 5429 rll\\t%0,%1,0(%2)" 5430 [(set_attr "op_type" "RSE")]) 5431 5432 5433;; 5434;;- Arithmetic shift instructions. 5435;; 5436 5437; 5438; ashldi3 instruction pattern(s). 5439; 5440 5441(define_expand "ashldi3" 5442 [(set (match_operand:DI 0 "register_operand" "") 5443 (ashift:DI (match_operand:DI 1 "register_operand" "") 5444 (match_operand:SI 2 "nonmemory_operand" "")))] 5445 "" 5446 "") 5447 5448(define_insn "*ashldi3_31" 5449 [(set (match_operand:DI 0 "register_operand" "=d,d") 5450 (ashift:DI (match_operand:DI 1 "register_operand" "0,0") 5451 (match_operand:SI 2 "nonmemory_operand" "J,a")))] 5452 "!TARGET_64BIT" 5453 "@ 5454 sldl\\t%0,%c2 5455 sldl\\t%0,0(%2)" 5456 [(set_attr "op_type" "RS")]) 5457 5458(define_insn "*ashldi3_64" 5459 [(set (match_operand:DI 0 "register_operand" "=d,d") 5460 (ashift:DI (match_operand:DI 1 "register_operand" "d,d") 5461 (match_operand:SI 2 "nonmemory_operand" "J,a")))] 5462 "TARGET_64BIT" 5463 "@ 5464 sllg\\t%0,%1,%2 5465 sllg\\t%0,%1,0(%2)" 5466 [(set_attr "op_type" "RSE")]) 5467 5468; 5469; ashrdi3 instruction pattern(s). 5470; 5471 5472(define_expand "ashrdi3" 5473 [(parallel 5474 [(set (match_operand:DI 0 "register_operand" "") 5475 (ashiftrt:DI (match_operand:DI 1 "register_operand" "") 5476 (match_operand:SI 2 "nonmemory_operand" ""))) 5477 (clobber (reg:CC 33))])] 5478 "" 5479 "") 5480 5481(define_insn "*ashrdi3_cc_31" 5482 [(set (reg 33) 5483 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") 5484 (match_operand:SI 2 "nonmemory_operand" "J,a")) 5485 (const_int 0))) 5486 (set (match_operand:DI 0 "register_operand" "=d,d") 5487 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 5488 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" 5489 "@ 5490 srda\\t%0,%c2 5491 srda\\t%0,0(%2)" 5492 [(set_attr "op_type" "RS")]) 5493 5494(define_insn "*ashrdi3_cconly_31" 5495 [(set (reg 33) 5496 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") 5497 (match_operand:SI 2 "nonmemory_operand" "J,a")) 5498 (const_int 0))) 5499 (clobber (match_scratch:DI 0 "=d,d"))] 5500 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" 5501 "@ 5502 srda\\t%0,%c2 5503 srda\\t%0,0(%2)" 5504 [(set_attr "op_type" "RS")]) 5505 5506(define_insn "*ashrdi3_31" 5507 [(set (match_operand:DI 0 "register_operand" "=d,d") 5508 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") 5509 (match_operand:SI 2 "nonmemory_operand" "J,a"))) 5510 (clobber (reg:CC 33))] 5511 "!TARGET_64BIT" 5512 "@ 5513 srda\\t%0,%c2 5514 srda\\t%0,0(%2)" 5515 [(set_attr "op_type" "RS")]) 5516 5517(define_insn "*ashrdi3_cc_64" 5518 [(set (reg 33) 5519 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") 5520 (match_operand:SI 2 "nonmemory_operand" "J,a")) 5521 (const_int 0))) 5522 (set (match_operand:DI 0 "register_operand" "=d,d") 5523 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 5524 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 5525 "@ 5526 srag\\t%0,%1,%c2 5527 srag\\t%0,%1,0(%2)" 5528 [(set_attr "op_type" "RSE")]) 5529 5530(define_insn "*ashrdi3_cconly_64" 5531 [(set (reg 33) 5532 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") 5533 (match_operand:SI 2 "nonmemory_operand" "J,a")) 5534 (const_int 0))) 5535 (clobber (match_scratch:DI 0 "=d,d"))] 5536 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" 5537 "@ 5538 srag\\t%0,%1,%c2 5539 srag\\t%0,%1,0(%2)" 5540 [(set_attr "op_type" "RSE")]) 5541 5542(define_insn "*ashrdi3_64" 5543 [(set (match_operand:DI 0 "register_operand" "=d,d") 5544 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") 5545 (match_operand:SI 2 "nonmemory_operand" "J,a"))) 5546 (clobber (reg:CC 33))] 5547 "TARGET_64BIT" 5548 "@ 5549 srag\\t%0,%1,%c2 5550 srag\\t%0,%1,0(%2)" 5551 [(set_attr "op_type" "RSE")]) 5552 5553; 5554; ashlsi3 instruction pattern(s). 5555; 5556 5557(define_insn "ashlsi3" 5558 [(set (match_operand:SI 0 "register_operand" "=d,d") 5559 (ashift:SI (match_operand:SI 1 "register_operand" "0,0") 5560 (match_operand:SI 2 "nonmemory_operand" "J,a")))] 5561 "" 5562 "@ 5563 sll\\t%0,%c2 5564 sll\\t%0,0(%2)" 5565 [(set_attr "op_type" "RS")]) 5566 5567; 5568; ashrsi3 instruction pattern(s). 5569; 5570 5571(define_insn "*ashrsi3_cc" 5572 [(set (reg 33) 5573 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") 5574 (match_operand:SI 2 "nonmemory_operand" "J,a")) 5575 (const_int 0))) 5576 (set (match_operand:SI 0 "register_operand" "=d,d") 5577 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 5578 "s390_match_ccmode(insn, CCSmode)" 5579 "@ 5580 sra\\t%0,%c2 5581 sra\\t%0,0(%2)" 5582 [(set_attr "op_type" "RS")]) 5583 5584(define_insn "*ashrsi3_cconly" 5585 [(set (reg 33) 5586 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") 5587 (match_operand:SI 2 "nonmemory_operand" "J,a")) 5588 (const_int 0))) 5589 (clobber (match_scratch:SI 0 "=d,d"))] 5590 "s390_match_ccmode(insn, CCSmode)" 5591 "@ 5592 sra\\t%0,%c2 5593 sra\\t%0,0(%2)" 5594 [(set_attr "op_type" "RS")]) 5595 5596(define_insn "ashrsi3" 5597 [(set (match_operand:SI 0 "register_operand" "=d,d") 5598 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") 5599 (match_operand:SI 2 "nonmemory_operand" "J,a"))) 5600 (clobber (reg:CC 33))] 5601 "" 5602 "@ 5603 sra\\t%0,%c2 5604 sra\\t%0,0(%2)" 5605 [(set_attr "op_type" "RS")]) 5606 5607 5608;; 5609;;- logical shift instructions. 5610;; 5611 5612; 5613; lshrdi3 instruction pattern(s). 5614; 5615 5616(define_expand "lshrdi3" 5617 [(set (match_operand:DI 0 "register_operand" "") 5618 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 5619 (match_operand:SI 2 "nonmemory_operand" "")))] 5620 "" 5621 "") 5622 5623(define_insn "*lshrdi3_31" 5624 [(set (match_operand:DI 0 "register_operand" "=d,d") 5625 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0") 5626 (match_operand:SI 2 "nonmemory_operand" "J,a")))] 5627 "!TARGET_64BIT" 5628 "@ 5629 srdl\\t%0,%c2 5630 srdl\\t%0,0(%2)" 5631 [(set_attr "op_type" "RS,RS")]) 5632 5633(define_insn "*lshrdi3_64" 5634 [(set (match_operand:DI 0 "register_operand" "=d,d") 5635 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") 5636 (match_operand:SI 2 "nonmemory_operand" "J,a")))] 5637 "TARGET_64BIT" 5638 "@ 5639 srlg\\t%0,%1,%c2 5640 srlg\\t%0,%1,0(%2)" 5641 [(set_attr "op_type" "RSE,RSE")]) 5642 5643; 5644; lshrsi3 instruction pattern(s). 5645; 5646 5647(define_insn "lshrsi3" 5648 [(set (match_operand:SI 0 "register_operand" "=d,d") 5649 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") 5650 (match_operand:SI 2 "nonmemory_operand" "J,a")))] 5651 "" 5652 "@ 5653 srl\\t%0,%c2 5654 srl\\t%0,0(%2)" 5655 [(set_attr "op_type" "RS")]) 5656 5657 5658;; 5659;; Branch instruction patterns. 5660;; 5661 5662(define_expand "beq" 5663 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) 5664 (set (pc) 5665 (if_then_else (eq (reg:CCZ 33) (const_int 0)) 5666 (label_ref (match_operand 0 "" "")) 5667 (pc)))] 5668 "" 5669 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5670 5671(define_expand "bne" 5672 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) 5673 (set (pc) 5674 (if_then_else (ne (reg:CCZ 33) (const_int 0)) 5675 (label_ref (match_operand 0 "" "")) 5676 (pc)))] 5677 "" 5678 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5679 5680(define_expand "bgt" 5681 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 5682 (set (pc) 5683 (if_then_else (gt (reg:CCS 33) (const_int 0)) 5684 (label_ref (match_operand 0 "" "")) 5685 (pc)))] 5686 "" 5687 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5688 5689(define_expand "bgtu" 5690 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) 5691 (set (pc) 5692 (if_then_else (gtu (reg:CCU 33) (const_int 0)) 5693 (label_ref (match_operand 0 "" "")) 5694 (pc)))] 5695 "" 5696 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5697 5698(define_expand "blt" 5699 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 5700 (set (pc) 5701 (if_then_else (lt (reg:CCS 33) (const_int 0)) 5702 (label_ref (match_operand 0 "" "")) 5703 (pc)))] 5704 "" 5705 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5706 5707(define_expand "bltu" 5708 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) 5709 (set (pc) 5710 (if_then_else (ltu (reg:CCU 33) (const_int 0)) 5711 (label_ref (match_operand 0 "" "")) 5712 (pc)))] 5713 "" 5714 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5715 5716(define_expand "bge" 5717 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 5718 (set (pc) 5719 (if_then_else (ge (reg:CCS 33) (const_int 0)) 5720 (label_ref (match_operand 0 "" "")) 5721 (pc)))] 5722 "" 5723 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5724 5725(define_expand "bgeu" 5726 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) 5727 (set (pc) 5728 (if_then_else (geu (reg:CCU 33) (const_int 0)) 5729 (label_ref (match_operand 0 "" "")) 5730 (pc)))] 5731 "" 5732 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5733 5734(define_expand "ble" 5735 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 5736 (set (pc) 5737 (if_then_else (le (reg:CCS 33) (const_int 0)) 5738 (label_ref (match_operand 0 "" "")) 5739 (pc)))] 5740 "" 5741 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5742 5743(define_expand "bleu" 5744 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) 5745 (set (pc) 5746 (if_then_else (leu (reg:CCU 33) (const_int 0)) 5747 (label_ref (match_operand 0 "" "")) 5748 (pc)))] 5749 "" 5750 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5751 5752(define_expand "bunordered" 5753 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 5754 (set (pc) 5755 (if_then_else (unordered (reg:CCS 33) (const_int 0)) 5756 (label_ref (match_operand 0 "" "")) 5757 (pc)))] 5758 "" 5759 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5760 5761(define_expand "bordered" 5762 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 5763 (set (pc) 5764 (if_then_else (ordered (reg:CCS 33) (const_int 0)) 5765 (label_ref (match_operand 0 "" "")) 5766 (pc)))] 5767 "" 5768 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5769 5770(define_expand "buneq" 5771 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 5772 (set (pc) 5773 (if_then_else (uneq (reg:CCS 33) (const_int 0)) 5774 (label_ref (match_operand 0 "" "")) 5775 (pc)))] 5776 "" 5777 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5778 5779(define_expand "bungt" 5780 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 5781 (set (pc) 5782 (if_then_else (ungt (reg:CCS 33) (const_int 0)) 5783 (label_ref (match_operand 0 "" "")) 5784 (pc)))] 5785 "" 5786 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5787 5788(define_expand "bunlt" 5789 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 5790 (set (pc) 5791 (if_then_else (unlt (reg:CCS 33) (const_int 0)) 5792 (label_ref (match_operand 0 "" "")) 5793 (pc)))] 5794 "" 5795 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5796 5797(define_expand "bunge" 5798 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 5799 (set (pc) 5800 (if_then_else (unge (reg:CCS 33) (const_int 0)) 5801 (label_ref (match_operand 0 "" "")) 5802 (pc)))] 5803 "" 5804 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5805 5806(define_expand "bunle" 5807 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 5808 (set (pc) 5809 (if_then_else (unle (reg:CCS 33) (const_int 0)) 5810 (label_ref (match_operand 0 "" "")) 5811 (pc)))] 5812 "" 5813 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5814 5815(define_expand "bltgt" 5816 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) 5817 (set (pc) 5818 (if_then_else (ltgt (reg:CCS 33) (const_int 0)) 5819 (label_ref (match_operand 0 "" "")) 5820 (pc)))] 5821 "" 5822 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") 5823 5824 5825;; 5826;;- Conditional jump instructions. 5827;; 5828 5829(define_insn "cjump" 5830 [(set (pc) 5831 (if_then_else 5832 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) 5833 (label_ref (match_operand 0 "" "")) 5834 (pc)))] 5835 "" 5836 "* 5837{ 5838 if (get_attr_length (insn) == 4) 5839 return \"j%C1\\t%l0\"; 5840 else if (TARGET_64BIT) 5841 return \"jg%C1\\t%l0\"; 5842 else 5843 abort (); 5844}" 5845 [(set_attr "op_type" "RI") 5846 (set (attr "length") 5847 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 5848 (const_int 4) 5849 (ne (symbol_ref "TARGET_64BIT") (const_int 0)) 5850 (const_int 6) 5851 (eq (symbol_ref "flag_pic") (const_int 0)) 5852 (const_int 6)] (const_int 8)))]) 5853 5854(define_insn "*cjump_long" 5855 [(set (pc) 5856 (if_then_else 5857 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) 5858 (match_operand 0 "address_operand" "p") 5859 (pc)))] 5860 "" 5861 "* 5862{ 5863 if (get_attr_op_type (insn) == OP_TYPE_RR) 5864 return \"b%C1r\\t%0\"; 5865 else 5866 return \"b%C1\\t%a0\"; 5867}" 5868 [(set (attr "op_type") 5869 (if_then_else (match_operand 0 "register_operand" "") 5870 (const_string "RR") (const_string "RX"))) 5871 (set_attr "atype" "mem")]) 5872 5873 5874;; 5875;;- Negated conditional jump instructions. 5876;; 5877 5878(define_insn "icjump" 5879 [(set (pc) 5880 (if_then_else 5881 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) 5882 (pc) 5883 (label_ref (match_operand 0 "" ""))))] 5884 "" 5885 "* 5886{ 5887 if (get_attr_length (insn) == 4) 5888 return \"j%D1\\t%l0\"; 5889 else if (TARGET_64BIT) 5890 return \"jg%D1\\t%l0\"; 5891 else 5892 abort (); 5893}" 5894 [(set_attr "op_type" "RI") 5895 (set (attr "length") 5896 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 5897 (const_int 4) 5898 (ne (symbol_ref "TARGET_64BIT") (const_int 0)) 5899 (const_int 6) 5900 (eq (symbol_ref "flag_pic") (const_int 0)) 5901 (const_int 6)] (const_int 8)))]) 5902 5903(define_insn "*icjump_long" 5904 [(set (pc) 5905 (if_then_else 5906 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) 5907 (pc) 5908 (match_operand 0 "address_operand" "p")))] 5909 "" 5910 "* 5911{ 5912 if (get_attr_op_type (insn) == OP_TYPE_RR) 5913 return \"b%D1r\\t%0\"; 5914 else 5915 return \"b%D1\\t%a0\"; 5916}" 5917 [(set (attr "op_type") 5918 (if_then_else (match_operand 0 "register_operand" "") 5919 (const_string "RR") (const_string "RX"))) 5920 (set_attr "atype" "mem")]) 5921 5922;; 5923;;- Trap instructions. 5924;; 5925 5926(define_insn "trap" 5927 [(trap_if (const_int 1) (const_int 0))] 5928 "" 5929 "j\\t.+2" 5930 [(set_attr "op_type" "RX")]) 5931 5932(define_expand "conditional_trap" 5933 [(set (match_dup 2) (match_dup 3)) 5934 (trap_if (match_operator 0 "comparison_operator" 5935 [(match_dup 2) (const_int 0)]) 5936 (match_operand:SI 1 "general_operand" ""))] 5937 "" 5938 " 5939{ 5940 enum machine_mode ccmode; 5941 5942 if (operands[1] != const0_rtx) FAIL; 5943 5944 ccmode = s390_select_ccmode (GET_CODE (operands[0]), 5945 s390_compare_op0, s390_compare_op1); 5946 operands[2] = gen_rtx_REG (ccmode, 33); 5947 operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1); 5948}") 5949 5950(define_insn "*trap" 5951 [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)]) 5952 (const_int 0))] 5953 "" 5954 "j%C0\\t.+2"; 5955 [(set_attr "op_type" "RX")]) 5956 5957;; 5958;;- Loop instructions. 5959;; 5960;; This is all complicated by the fact that since this is a jump insn 5961;; we must handle our own output reloads. 5962 5963(define_expand "doloop_end" 5964 [(use (match_operand 0 "" "")) ; loop pseudo 5965 (use (match_operand 1 "" "")) ; iterations; zero if unknown 5966 (use (match_operand 2 "" "")) ; max iterations 5967 (use (match_operand 3 "" "")) ; loop level 5968 (use (match_operand 4 "" ""))] ; label 5969 "" 5970 " 5971{ 5972 if (GET_MODE (operands[0]) == SImode) 5973 emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0])); 5974 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) 5975 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); 5976 else 5977 FAIL; 5978 5979 DONE; 5980}") 5981 5982(define_insn "doloop_si" 5983 [(set (pc) 5984 (if_then_else 5985 (ne (match_operand:SI 1 "register_operand" "d,d") 5986 (const_int 1)) 5987 (label_ref (match_operand 0 "" "")) 5988 (pc))) 5989 (set (match_operand:SI 2 "register_operand" "=1,?*m*d") 5990 (plus:SI (match_dup 1) (const_int -1))) 5991 (clobber (match_scratch:SI 3 "=X,&d")) 5992 (clobber (reg:CC 33))] 5993 "" 5994 "* 5995{ 5996 if (which_alternative != 0) 5997 return \"#\"; 5998 else if (get_attr_length (insn) == 4) 5999 return \"brct\\t%1,%l0\"; 6000 else 6001 abort (); 6002}" 6003 [(set_attr "op_type" "RI") 6004 (set (attr "length") 6005 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 6006 (const_int 4) 6007 (ne (symbol_ref "TARGET_64BIT") (const_int 0)) 6008 (const_int 10) 6009 (eq (symbol_ref "flag_pic") (const_int 0)) 6010 (const_int 6)] (const_int 8)))]) 6011 6012(define_insn "*doloop_si_long" 6013 [(set (pc) 6014 (if_then_else 6015 (ne (match_operand:SI 1 "register_operand" "d,d") 6016 (const_int 1)) 6017 (match_operand 0 "address_operand" "p,p") 6018 (pc))) 6019 (set (match_operand:SI 2 "register_operand" "=1,?*m*d") 6020 (plus:SI (match_dup 1) (const_int -1))) 6021 (clobber (match_scratch:SI 3 "=X,&d")) 6022 (clobber (reg:CC 33))] 6023 "" 6024 "* 6025{ 6026 if (get_attr_op_type (insn) == OP_TYPE_RR) 6027 return \"bctr\\t%1,%0\"; 6028 else 6029 return \"bct\\t%1,%a0\"; 6030}" 6031 [(set (attr "op_type") 6032 (if_then_else (match_operand 0 "register_operand" "") 6033 (const_string "RR") (const_string "RX"))) 6034 (set_attr "atype" "mem")]) 6035 6036(define_split 6037 [(set (pc) 6038 (if_then_else (ne (match_operand:SI 1 "register_operand" "") 6039 (const_int 1)) 6040 (match_operand 0 "" "") 6041 (pc))) 6042 (set (match_operand:SI 2 "nonimmediate_operand" "") 6043 (plus:SI (match_dup 1) (const_int -1))) 6044 (clobber (match_scratch:SI 3 "")) 6045 (clobber (reg:CC 33))] 6046 "reload_completed 6047 && (! REG_P (operands[2]) 6048 || ! rtx_equal_p (operands[1], operands[2]))" 6049 [(set (match_dup 3) (match_dup 1)) 6050 (parallel [(set (reg:CCAN 33) 6051 (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) 6052 (const_int 0))) 6053 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) 6054 (set (match_dup 2) (match_dup 3)) 6055 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) 6056 (match_dup 0) 6057 (pc)))] 6058 "") 6059 6060(define_insn "doloop_di" 6061 [(set (pc) 6062 (if_then_else 6063 (ne (match_operand:DI 1 "register_operand" "d,d") 6064 (const_int 1)) 6065 (label_ref (match_operand 0 "" "")) 6066 (pc))) 6067 (set (match_operand:DI 2 "register_operand" "=1,?*m*r") 6068 (plus:DI (match_dup 1) (const_int -1))) 6069 (clobber (match_scratch:DI 3 "=X,&d")) 6070 (clobber (reg:CC 33))] 6071 "TARGET_64BIT" 6072 "* 6073{ 6074 if (which_alternative != 0) 6075 return \"#\"; 6076 else if (get_attr_length (insn) == 4) 6077 return \"brctg\\t%1,%l0\"; 6078 else 6079 abort (); 6080}" 6081 [(set_attr "op_type" "RI") 6082 (set (attr "length") 6083 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 6084 (const_int 4) (const_int 12)))]) 6085 6086(define_insn "*doloop_di_long" 6087 [(set (pc) 6088 (if_then_else 6089 (ne (match_operand:DI 1 "register_operand" "d,d") 6090 (const_int 1)) 6091 (match_operand 0 "address_operand" "p,p") 6092 (pc))) 6093 (set (match_operand:DI 2 "register_operand" "=1,?*m*d") 6094 (plus:DI (match_dup 1) (const_int -1))) 6095 (clobber (match_scratch:DI 3 "=X,&d")) 6096 (clobber (reg:CC 33))] 6097 "" 6098 "* 6099{ 6100 if (get_attr_op_type (insn) == OP_TYPE_RRE) 6101 return \"bctgr\\t%1,%0\"; 6102 else 6103 return \"bctg\\t%1,%a0\"; 6104}" 6105 [(set (attr "op_type") 6106 (if_then_else (match_operand 0 "register_operand" "") 6107 (const_string "RRE") (const_string "RXE"))) 6108 (set_attr "atype" "mem")]) 6109 6110(define_split 6111 [(set (pc) 6112 (if_then_else (ne (match_operand:DI 1 "register_operand" "") 6113 (const_int 1)) 6114 (match_operand 0 "" "") 6115 (pc))) 6116 (set (match_operand:DI 2 "nonimmediate_operand" "") 6117 (plus:DI (match_dup 1) (const_int -1))) 6118 (clobber (match_scratch:DI 3 "")) 6119 (clobber (reg:CC 33))] 6120 "reload_completed 6121 && (! REG_P (operands[2]) 6122 || ! rtx_equal_p (operands[1], operands[2]))" 6123 [(set (match_dup 3) (match_dup 1)) 6124 (parallel [(set (reg:CCAN 33) 6125 (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) 6126 (const_int 0))) 6127 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) 6128 (set (match_dup 2) (match_dup 3)) 6129 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) 6130 (match_dup 0) 6131 (pc)))] 6132 "") 6133 6134;; 6135;;- Unconditional jump instructions. 6136;; 6137 6138; 6139; jump instruction pattern(s). 6140; 6141 6142(define_insn "jump" 6143 [(set (pc) (label_ref (match_operand 0 "" "")))] 6144 "" 6145 "* 6146{ 6147 if (get_attr_length (insn) == 4) 6148 return \"j\\t%l0\"; 6149 else if (TARGET_64BIT) 6150 return \"jg\\t%l0\"; 6151 else 6152 abort (); 6153}" 6154 [(set_attr "op_type" "RI") 6155 (set (attr "length") 6156 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 6157 (const_int 4) 6158 (ne (symbol_ref "TARGET_64BIT") (const_int 0)) 6159 (const_int 6) 6160 (eq (symbol_ref "flag_pic") (const_int 0)) 6161 (const_int 6)] (const_int 8)))]) 6162 6163; 6164; indirect-jump instruction pattern(s). 6165; 6166 6167(define_insn "indirect_jump" 6168 [(set (pc) (match_operand 0 "address_operand" "p"))] 6169 "" 6170 "* 6171{ 6172 if (get_attr_op_type (insn) == OP_TYPE_RR) 6173 return \"br\\t%0\"; 6174 else 6175 return \"b\\t%a0\"; 6176}" 6177 [(set (attr "op_type") 6178 (if_then_else (match_operand 0 "register_operand" "") 6179 (const_string "RR") (const_string "RX"))) 6180 (set_attr "atype" "mem")]) 6181 6182; 6183; casesi instruction pattern(s). 6184; 6185 6186(define_insn "casesi_jump" 6187 [(set (pc) (match_operand 0 "address_operand" "p")) 6188 (use (label_ref (match_operand 1 "" "")))] 6189 "" 6190 "* 6191{ 6192 if (get_attr_op_type (insn) == OP_TYPE_RR) 6193 return \"br\\t%0\"; 6194 else 6195 return \"b\\t%a0\"; 6196}" 6197 [(set (attr "op_type") 6198 (if_then_else (match_operand 0 "register_operand" "") 6199 (const_string "RR") (const_string "RX"))) 6200 (set_attr "atype" "mem")]) 6201 6202(define_expand "casesi" 6203 [(match_operand:SI 0 "general_operand" "") 6204 (match_operand:SI 1 "general_operand" "") 6205 (match_operand:SI 2 "general_operand" "") 6206 (label_ref (match_operand 3 "" "")) 6207 (label_ref (match_operand 4 "" ""))] 6208 "" 6209 " 6210{ 6211 rtx index = gen_reg_rtx (SImode); 6212 rtx base = gen_reg_rtx (Pmode); 6213 rtx target = gen_reg_rtx (Pmode); 6214 6215 emit_move_insn (index, operands[0]); 6216 emit_insn (gen_subsi3 (index, index, operands[1])); 6217 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, 6218 operands[4]); 6219 6220 if (Pmode != SImode) 6221 index = convert_to_mode (Pmode, index, 1); 6222 if (GET_CODE (index) != REG) 6223 index = copy_to_mode_reg (Pmode, index); 6224 6225 if (TARGET_64BIT) 6226 emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); 6227 else 6228 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2))); 6229 6230 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); 6231 6232 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index)); 6233 emit_move_insn (target, index); 6234 6235 if (flag_pic) 6236 target = gen_rtx_PLUS (Pmode, base, target); 6237 emit_jump_insn (gen_casesi_jump (target, operands[3])); 6238 6239 DONE; 6240}") 6241 6242 6243;; 6244;;- Jump to subroutine. 6245;; 6246;; 6247 6248; 6249; untyped call instruction pattern(s). 6250; 6251 6252;; Call subroutine returning any type. 6253(define_expand "untyped_call" 6254 [(parallel [(call (match_operand 0 "" "") 6255 (const_int 0)) 6256 (match_operand 1 "" "") 6257 (match_operand 2 "" "")])] 6258 "" 6259 " 6260{ 6261 int i; 6262 6263 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); 6264 6265 for (i = 0; i < XVECLEN (operands[2], 0); i++) 6266 { 6267 rtx set = XVECEXP (operands[2], 0, i); 6268 emit_move_insn (SET_DEST (set), SET_SRC (set)); 6269 } 6270 6271 /* The optimizer does not know that the call sets the function value 6272 registers we stored in the result block. We avoid problems by 6273 claiming that all hard registers are used and clobbered at this 6274 point. */ 6275 emit_insn (gen_blockage ()); 6276 6277 DONE; 6278}") 6279 6280;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 6281;; all of memory. This blocks insns from being moved across this point. 6282 6283(define_insn "blockage" 6284 [(unspec_volatile [(const_int 0)] 0)] 6285 "" 6286 "" 6287 [(set_attr "type" "none") 6288 (set_attr "length" "0")]) 6289 6290 6291 6292; 6293; call instruction pattern(s). 6294; 6295 6296(define_expand "call" 6297 [(call (match_operand 0 "" "") 6298 (match_operand 1 "" "")) 6299 (use (match_operand 2 "" ""))] 6300 "" 6301 " 6302{ 6303 int plt_call = 0; 6304 rtx insn; 6305 6306 /* Direct function calls need special treatment. */ 6307 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) 6308 { 6309 rtx sym = XEXP (operands[0], 0); 6310 6311 /* When calling a global routine in PIC mode, we must 6312 replace the symbol itself with the PLT stub. */ 6313 if (flag_pic && !SYMBOL_REF_FLAG (sym)) 6314 { 6315 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113); 6316 sym = gen_rtx_CONST (Pmode, sym); 6317 6318 plt_call = 1; 6319 } 6320 6321 /* Unless we can use the bras(l) insn, force the 6322 routine address into a register. */ 6323 if (!TARGET_SMALL_EXEC && !TARGET_64BIT) 6324 { 6325 rtx target = gen_reg_rtx (Pmode); 6326 emit_move_insn (target, sym); 6327 sym = target; 6328 } 6329 6330 operands[0] = gen_rtx_MEM (QImode, sym); 6331 } 6332 6333 /* Emit insn. */ 6334 insn = emit_call_insn (gen_call_exp (operands[0], operands[1], 6335 gen_rtx_REG (Pmode, RETURN_REGNUM))); 6336 6337 /* In 31-bit, we must load the GOT register even if the 6338 compiler doesn't know about it, because the PLT glue 6339 code uses it. In 64-bit, this is not necessary. */ 6340 if (plt_call && !TARGET_64BIT) 6341 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); 6342 6343 DONE; 6344}") 6345 6346(define_expand "call_exp" 6347 [(parallel [(call (match_operand 0 "" "") 6348 (match_operand 1 "" "")) 6349 (clobber (match_operand 2 "" ""))])] 6350 "" 6351 "") 6352 6353(define_insn "brasl" 6354 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X")) 6355 (match_operand:SI 1 "const_int_operand" "n")) 6356 (clobber (match_operand:DI 2 "register_operand" "=r"))] 6357 "TARGET_64BIT" 6358 "brasl\\t%2,%0" 6359 [(set_attr "op_type" "RIL") 6360 (set_attr "type" "jsr")]) 6361 6362(define_insn "bras" 6363 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X")) 6364 (match_operand:SI 1 "const_int_operand" "n")) 6365 (clobber (match_operand:SI 2 "register_operand" "=r"))] 6366 "TARGET_SMALL_EXEC" 6367 "bras\\t%2,%0" 6368 [(set_attr "op_type" "RI") 6369 (set_attr "type" "jsr")]) 6370 6371(define_insn "basr_64" 6372 [(call (mem:QI (match_operand:DI 0 "register_operand" "a")) 6373 (match_operand:SI 1 "const_int_operand" "n")) 6374 (clobber (match_operand:DI 2 "register_operand" "=r"))] 6375 "TARGET_64BIT" 6376 "basr\\t%2,%0" 6377 [(set_attr "op_type" "RR") 6378 (set_attr "type" "jsr") 6379 (set_attr "atype" "mem")]) 6380 6381(define_insn "basr_31" 6382 [(call (mem:QI (match_operand:SI 0 "register_operand" "a")) 6383 (match_operand:SI 1 "const_int_operand" "n")) 6384 (clobber (match_operand:SI 2 "register_operand" "=r"))] 6385 "!TARGET_64BIT" 6386 "basr\\t%2,%0" 6387 [(set_attr "op_type" "RR") 6388 (set_attr "type" "jsr") 6389 (set_attr "atype" "mem")]) 6390 6391(define_insn "bas_64" 6392 [(call (mem:QI (match_operand:QI 0 "address_operand" "p")) 6393 (match_operand:SI 1 "const_int_operand" "n")) 6394 (clobber (match_operand:DI 2 "register_operand" "=r"))] 6395 "TARGET_64BIT" 6396 "bas\\t%2,%a0" 6397 [(set_attr "op_type" "RX") 6398 (set_attr "type" "jsr") 6399 (set_attr "atype" "mem")]) 6400 6401(define_insn "bas_31" 6402 [(call (mem:QI (match_operand:QI 0 "address_operand" "p")) 6403 (match_operand:SI 1 "const_int_operand" "n")) 6404 (clobber (match_operand:SI 2 "register_operand" "=r"))] 6405 "!TARGET_64BIT" 6406 "bas\\t%2,%a0" 6407 [(set_attr "op_type" "RX") 6408 (set_attr "type" "jsr") 6409 (set_attr "atype" "mem")]) 6410 6411 6412; 6413; call_value instruction pattern(s). 6414; 6415 6416(define_expand "call_value" 6417 [(set (match_operand 0 "" "") 6418 (call (match_operand 1 "" "") 6419 (match_operand 2 "" ""))) 6420 (use (match_operand 3 "" ""))] 6421 "" 6422 " 6423{ 6424 int plt_call = 0; 6425 rtx insn; 6426 6427 /* Direct function calls need special treatment. */ 6428 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) 6429 { 6430 rtx sym = XEXP (operands[1], 0); 6431 6432 /* When calling a global routine in PIC mode, we must 6433 replace the symbol itself with the PLT stub. */ 6434 if (flag_pic && !SYMBOL_REF_FLAG (sym)) 6435 { 6436 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113); 6437 sym = gen_rtx_CONST (Pmode, sym); 6438 6439 plt_call = 1; 6440 } 6441 6442 /* Unless we can use the bras(l) insn, force the 6443 routine address into a register. */ 6444 if (!TARGET_SMALL_EXEC && !TARGET_64BIT) 6445 { 6446 rtx target = gen_reg_rtx (Pmode); 6447 emit_move_insn (target, sym); 6448 sym = target; 6449 } 6450 6451 operands[1] = gen_rtx_MEM (QImode, sym); 6452 } 6453 6454 /* Emit insn. */ 6455 insn = emit_call_insn ( 6456 gen_call_value_exp (operands[0], operands[1], operands[2], 6457 gen_rtx_REG (Pmode, RETURN_REGNUM))); 6458 6459 /* In 31-bit, we must load the GOT register even if the 6460 compiler doesn't know about it, because the PLT glue 6461 code uses it. In 64-bit, this is not necessary. */ 6462 if (plt_call && !TARGET_64BIT) 6463 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); 6464 6465 DONE; 6466}") 6467 6468(define_expand "call_value_exp" 6469 [(parallel [(set (match_operand 0 "" "") 6470 (call (match_operand 1 "" "") 6471 (match_operand 2 "" ""))) 6472 (clobber (match_operand 3 "" ""))])] 6473 "" 6474 "") 6475 6476(define_insn "brasl_r" 6477 [(set (match_operand 0 "register_operand" "=df") 6478 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X")) 6479 (match_operand:SI 2 "const_int_operand" "n"))) 6480 (clobber (match_operand:DI 3 "register_operand" "=r"))] 6481 "TARGET_64BIT" 6482 "brasl\\t%3,%1" 6483 [(set_attr "op_type" "RIL") 6484 (set_attr "type" "jsr")]) 6485 6486(define_insn "bras_r" 6487 [(set (match_operand 0 "register_operand" "=df") 6488 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X")) 6489 (match_operand:SI 2 "const_int_operand" "n"))) 6490 (clobber (match_operand:SI 3 "register_operand" "=r"))] 6491 "TARGET_SMALL_EXEC" 6492 "bras\\t%3,%1" 6493 [(set_attr "op_type" "RI") 6494 (set_attr "type" "jsr")]) 6495 6496(define_insn "basr_r_64" 6497 [(set (match_operand 0 "register_operand" "=df") 6498 (call (mem:QI (match_operand:DI 1 "register_operand" "a")) 6499 (match_operand:SI 2 "const_int_operand" "n"))) 6500 (clobber (match_operand:DI 3 "register_operand" "=r"))] 6501 "TARGET_64BIT" 6502 "basr\\t%3,%1" 6503 [(set_attr "op_type" "RR") 6504 (set_attr "type" "jsr")]) 6505 6506(define_insn "basr_r_31" 6507 [(set (match_operand 0 "register_operand" "=df") 6508 (call (mem:QI (match_operand:SI 1 "register_operand" "a")) 6509 (match_operand:SI 2 "const_int_operand" "n"))) 6510 (clobber (match_operand:SI 3 "register_operand" "=r"))] 6511 "!TARGET_64BIT" 6512 "basr\\t%3,%1" 6513 [(set_attr "op_type" "RR") 6514 (set_attr "type" "jsr") 6515 (set_attr "atype" "mem")]) 6516 6517(define_insn "bas_r_64" 6518 [(set (match_operand 0 "register_operand" "=df") 6519 (call (mem:QI (match_operand:QI 1 "address_operand" "p")) 6520 (match_operand:SI 2 "const_int_operand" "n"))) 6521 (clobber (match_operand:DI 3 "register_operand" "=r"))] 6522 "TARGET_64BIT" 6523 "bas\\t%3,%a1" 6524 [(set_attr "op_type" "RX") 6525 (set_attr "type" "jsr") 6526 (set_attr "atype" "mem")]) 6527 6528(define_insn "bas_r_31" 6529 [(set (match_operand 0 "register_operand" "=df") 6530 (call (mem:QI (match_operand:QI 1 "address_operand" "p")) 6531 (match_operand:SI 2 "const_int_operand" "n"))) 6532 (clobber (match_operand:SI 3 "register_operand" "=r"))] 6533 "!TARGET_64BIT" 6534 "bas\\t%3,%a1" 6535 [(set_attr "op_type" "RX") 6536 (set_attr "type" "jsr") 6537 (set_attr "atype" "mem")]) 6538 6539;; 6540;;- Thread-local storage support. 6541;; 6542 6543(define_insn "get_tp_64" 6544 [(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q") 6545 (unspec:DI [(const_int 0)] UNSPEC_TP))] 6546 "TARGET_64BIT" 6547 "@ 6548 ear\\t%0,%%a0\;sllg\\t%0,%0,32\;ear\\t%0,%%a1 6549 stam\\t%%a0,%%a1,%0" 6550 [(set_attr "op_type" "NN,RS") 6551 (set_attr "atype" "reg,mem") 6552 (set_attr "type" "o3,*") 6553 (set_attr "length" "14,*")]) 6554 6555(define_insn "get_tp_31" 6556 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q") 6557 (unspec:SI [(const_int 0)] UNSPEC_TP))] 6558 "!TARGET_64BIT" 6559 "@ 6560 ear\\t%0,%%a0 6561 stam\\t%%a0,%%a0,%0" 6562 [(set_attr "op_type" "RRE,RS") 6563 (set_attr "atype" "reg,mem")]) 6564 6565(define_insn "set_tp_64" 6566 [(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP) 6567 (clobber (match_scratch:SI 1 "=d,X"))] 6568 "TARGET_64BIT" 6569 "@ 6570 sar\\t%%a1,%0\;srlg\\t%1,%0,32\;sar\\t%%a0,%1 6571 lam\\t%%a0,%%a1,%0" 6572 [(set_attr "op_type" "NN,RS") 6573 (set_attr "atype" "reg,mem") 6574 (set_attr "type" "o3,*") 6575 (set_attr "length" "14,*")]) 6576 6577(define_insn "set_tp_31" 6578 [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)] 6579 "!TARGET_64BIT" 6580 "@ 6581 sar\\t%%a0,%0 6582 lam\\t%%a0,%%a0,%0" 6583 [(set_attr "op_type" "RRE,RS") 6584 (set_attr "atype" "reg,mem")]) 6585 6586(define_insn "*tls_load_64" 6587 [(set (match_operand:DI 0 "register_operand" "=d") 6588 (unspec:DI [(match_operand:DI 1 "memory_operand" "m") 6589 (match_operand:DI 2 "" "")] 6590 UNSPEC_TLS_LOAD))] 6591 "TARGET_64BIT" 6592 "lg\\t%0,%1%J2" 6593 [(set_attr "op_type" "RXE") 6594 (set_attr "atype" "mem")]) 6595 6596(define_insn "*tls_load_31" 6597 [(set (match_operand:SI 0 "register_operand" "=d") 6598 (unspec:SI [(match_operand:SI 1 "memory_operand" "m") 6599 (match_operand:SI 2 "" "")] 6600 UNSPEC_TLS_LOAD))] 6601 "!TARGET_64BIT" 6602 "l\\t%0,%1%J2" 6603 [(set_attr "op_type" "RX") 6604 (set_attr "atype" "mem")]) 6605 6606(define_expand "call_value_tls" 6607 [(set (match_operand 0 "" "") 6608 (call (const_int 0) (const_int 0))) 6609 (use (match_operand 1 "" ""))] 6610 "" 6611 " 6612{ 6613 rtx insn, sym; 6614 6615 if (!flag_pic) 6616 abort (); 6617 6618 sym = s390_tls_get_offset (); 6619 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113); 6620 sym = gen_rtx_CONST (Pmode, sym); 6621 6622 /* Unless we can use the bras(l) insn, force the 6623 routine address into a register. */ 6624 if (!TARGET_SMALL_EXEC && !TARGET_64BIT) 6625 { 6626 rtx target = gen_reg_rtx (Pmode); 6627 emit_move_insn (target, sym); 6628 sym = target; 6629 } 6630 6631 sym = gen_rtx_MEM (QImode, sym); 6632 6633 /* Emit insn. */ 6634 insn = emit_call_insn ( 6635 gen_call_value_tls_exp (operands[0], sym, const0_rtx, 6636 gen_rtx_REG (Pmode, RETURN_REGNUM), 6637 operands[1])); 6638 6639 /* The calling convention of __tls_get_offset uses the 6640 GOT register implicitly. */ 6641 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); 6642 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), operands[0]); 6643 CONST_OR_PURE_CALL_P (insn) = 1; 6644 6645 DONE; 6646}") 6647 6648(define_expand "call_value_tls_exp" 6649 [(parallel [(set (match_operand 0 "" "") 6650 (call (match_operand 1 "" "") 6651 (match_operand 2 "" ""))) 6652 (clobber (match_operand 3 "" "")) 6653 (use (match_operand 4 "" ""))])] 6654 "" 6655 "") 6656 6657(define_insn "brasl_tls" 6658 [(set (match_operand 0 "register_operand" "=df") 6659 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X")) 6660 (match_operand:SI 2 "const_int_operand" "n"))) 6661 (clobber (match_operand:DI 3 "register_operand" "=r")) 6662 (use (match_operand:DI 4 "" ""))] 6663 "TARGET_64BIT" 6664 "brasl\\t%3,%1%J4" 6665 [(set_attr "op_type" "RIL") 6666 (set_attr "type" "jsr")]) 6667 6668(define_insn "bras_tls" 6669 [(set (match_operand 0 "register_operand" "=df") 6670 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X")) 6671 (match_operand:SI 2 "const_int_operand" "n"))) 6672 (clobber (match_operand:SI 3 "register_operand" "=r")) 6673 (use (match_operand:SI 4 "" ""))] 6674 "TARGET_SMALL_EXEC" 6675 "bras\\t%3,%1%J4" 6676 [(set_attr "op_type" "RI") 6677 (set_attr "type" "jsr")]) 6678 6679(define_insn "basr_tls_64" 6680 [(set (match_operand 0 "register_operand" "=df") 6681 (call (mem:QI (match_operand:DI 1 "register_operand" "a")) 6682 (match_operand:SI 2 "const_int_operand" "n"))) 6683 (clobber (match_operand:DI 3 "register_operand" "=r")) 6684 (use (match_operand:DI 4 "" ""))] 6685 "TARGET_64BIT" 6686 "basr\\t%3,%1%J4" 6687 [(set_attr "op_type" "RR") 6688 (set_attr "type" "jsr")]) 6689 6690(define_insn "basr_tls_31" 6691 [(set (match_operand 0 "register_operand" "=df") 6692 (call (mem:QI (match_operand:SI 1 "register_operand" "a")) 6693 (match_operand:SI 2 "const_int_operand" "n"))) 6694 (clobber (match_operand:SI 3 "register_operand" "=r")) 6695 (use (match_operand:SI 4 "" ""))] 6696 "!TARGET_64BIT" 6697 "basr\\t%3,%1%J4" 6698 [(set_attr "op_type" "RR") 6699 (set_attr "type" "jsr") 6700 (set_attr "atype" "mem")]) 6701 6702(define_insn "bas_tls_64" 6703 [(set (match_operand 0 "register_operand" "=df") 6704 (call (mem:QI (match_operand:QI 1 "address_operand" "p")) 6705 (match_operand:SI 2 "const_int_operand" "n"))) 6706 (clobber (match_operand:DI 3 "register_operand" "=r")) 6707 (use (match_operand:DI 4 "" ""))] 6708 "TARGET_64BIT" 6709 "bas\\t%3,%a1%J4" 6710 [(set_attr "op_type" "RX") 6711 (set_attr "type" "jsr") 6712 (set_attr "atype" "mem")]) 6713 6714(define_insn "bas_tls_31" 6715 [(set (match_operand 0 "register_operand" "=df") 6716 (call (mem:QI (match_operand:QI 1 "address_operand" "p")) 6717 (match_operand:SI 2 "const_int_operand" "n"))) 6718 (clobber (match_operand:SI 3 "register_operand" "=r")) 6719 (use (match_operand:SI 4 "" ""))] 6720 "!TARGET_64BIT" 6721 "bas\\t%3,%a1%J4" 6722 [(set_attr "op_type" "RX") 6723 (set_attr "type" "jsr") 6724 (set_attr "atype" "mem")]) 6725 6726;; 6727;;- Miscellaneous instructions. 6728;; 6729 6730; 6731; allocate stack instruction pattern(s). 6732; 6733 6734(define_expand "allocate_stack" 6735 [(set (reg 15) 6736 (plus (reg 15) (match_operand 1 "general_operand" ""))) 6737 (set (match_operand 0 "general_operand" "") 6738 (reg 15))] 6739 "" 6740 " 6741{ 6742 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM); 6743 rtx chain = gen_rtx (MEM, Pmode, stack); 6744 rtx temp = gen_reg_rtx (Pmode); 6745 6746 emit_move_insn (temp, chain); 6747 6748 if (TARGET_64BIT) 6749 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1]))); 6750 else 6751 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1]))); 6752 6753 emit_move_insn (chain, temp); 6754 6755 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 6756 DONE; 6757}") 6758 6759 6760; 6761; setjmp/longjmp instruction pattern(s). 6762; 6763 6764(define_expand "builtin_setjmp_setup" 6765 [(unspec [(match_operand 0 "register_operand" "a")] 1)] 6766 "" 6767 " 6768{ 6769 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode))); 6770 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER); 6771 6772 emit_move_insn (base, basereg); 6773 DONE; 6774}") 6775 6776(define_expand "builtin_setjmp_receiver" 6777 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)] 6778 "flag_pic" 6779 " 6780{ 6781 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); 6782 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\"); 6783 SYMBOL_REF_FLAG (got) = 1; 6784 6785 emit_move_insn (gotreg, got); 6786 emit_insn (gen_rtx_USE (VOIDmode, gotreg)); 6787 DONE; 6788}") 6789 6790(define_expand "builtin_longjmp" 6791 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)] 6792 "" 6793 " 6794{ 6795 /* The elements of the buffer are, in order: */ 6796 rtx fp = gen_rtx_MEM (Pmode, operands[0]); 6797 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode))); 6798 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode))); 6799 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode))); 6800 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER); 6801 rtx jmp = gen_rtx_REG (Pmode, 14); 6802 6803 emit_move_insn (jmp, lab); 6804 emit_move_insn (basereg, base); 6805 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX); 6806 emit_move_insn (hard_frame_pointer_rtx, fp); 6807 6808 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx)); 6809 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); 6810 emit_insn (gen_rtx_USE (VOIDmode, basereg)); 6811 emit_indirect_jump (jmp); 6812 DONE; 6813}") 6814 6815 6816;; These patterns say how to save and restore the stack pointer. We need not 6817;; save the stack pointer at function level since we are careful to 6818;; preserve the backchain. At block level, we have to restore the backchain 6819;; when we restore the stack pointer. 6820;; 6821;; For nonlocal gotos, we must save both the stack pointer and its 6822;; backchain and restore both. Note that in the nonlocal case, the 6823;; save area is a memory location. 6824 6825(define_expand "save_stack_function" 6826 [(match_operand 0 "general_operand" "") 6827 (match_operand 1 "general_operand" "")] 6828 "" 6829 "DONE;") 6830 6831(define_expand "restore_stack_function" 6832 [(match_operand 0 "general_operand" "") 6833 (match_operand 1 "general_operand" "")] 6834 "" 6835 "DONE;") 6836 6837(define_expand "restore_stack_block" 6838 [(use (match_operand 0 "register_operand" "")) 6839 (set (match_dup 2) (match_dup 3)) 6840 (set (match_dup 0) (match_operand 1 "register_operand" "")) 6841 (set (match_dup 3) (match_dup 2))] 6842 "" 6843 " 6844{ 6845 operands[2] = gen_reg_rtx (Pmode); 6846 operands[3] = gen_rtx_MEM (Pmode, operands[0]); 6847}") 6848 6849(define_expand "save_stack_nonlocal" 6850 [(match_operand 0 "memory_operand" "") 6851 (match_operand 1 "register_operand" "")] 6852 "" 6853 " 6854{ 6855 rtx temp = gen_reg_rtx (Pmode); 6856 6857 /* Copy the backchain to the first word, sp to the second. */ 6858 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); 6859 emit_move_insn (operand_subword (operands[0], 0, 0, 6860 TARGET_64BIT ? TImode : DImode), 6861 temp); 6862 emit_move_insn (operand_subword (operands[0], 1, 0, 6863 TARGET_64BIT ? TImode : DImode), 6864 operands[1]); 6865 DONE; 6866}") 6867 6868(define_expand "restore_stack_nonlocal" 6869 [(match_operand 0 "register_operand" "") 6870 (match_operand 1 "memory_operand" "")] 6871 "" 6872 " 6873{ 6874 rtx temp = gen_reg_rtx (Pmode); 6875 6876 /* Restore the backchain from the first word, sp from the second. */ 6877 emit_move_insn (temp, 6878 operand_subword (operands[1], 0, 0, 6879 TARGET_64BIT ? TImode : DImode)); 6880 emit_move_insn (operands[0], 6881 operand_subword (operands[1], 1, 0, 6882 TARGET_64BIT ? TImode : DImode)); 6883 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); 6884 DONE; 6885}") 6886 6887 6888; 6889; nop instruction pattern(s). 6890; 6891 6892(define_insn "nop" 6893 [(const_int 0)] 6894 "" 6895 "lr\\t0,0" 6896 [(set_attr "op_type" "RR")]) 6897 6898 6899; 6900; Special literal pool access instruction pattern(s). 6901; 6902 6903(define_insn "consttable_qi" 6904 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)] 6905 "" 6906 "* 6907{ 6908 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1); 6909 return \"\"; 6910}" 6911 [(set_attr "op_type" "NN") 6912 (set_attr "length" "1")]) 6913 6914(define_insn "consttable_hi" 6915 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)] 6916 "" 6917 "* 6918{ 6919 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1); 6920 return \"\"; 6921}" 6922 [(set_attr "op_type" "NN") 6923 (set_attr "length" "2")]) 6924 6925(define_insn "consttable_si" 6926 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)] 6927 "" 6928 "* 6929{ 6930 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0])) 6931 return \".long\\t%0\"; 6932 6933 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1); 6934 return \"\"; 6935}" 6936 [(set_attr "op_type" "NN") 6937 (set_attr "length" "4")]) 6938 6939(define_insn "consttable_di" 6940 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)] 6941 "" 6942 "* 6943{ 6944 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1); 6945 return \"\"; 6946}" 6947 [(set_attr "op_type" "NN") 6948 (set_attr "length" "8")]) 6949 6950(define_insn "consttable_sf" 6951 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)] 6952 "" 6953 "* 6954{ 6955 REAL_VALUE_TYPE r; 6956 6957 if (GET_CODE (operands[0]) != CONST_DOUBLE) 6958 abort (); 6959 6960 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]); 6961 assemble_real (r, SFmode, 4*BITS_PER_UNIT); 6962 return \"\"; 6963}" 6964 [(set_attr "op_type" "NN") 6965 (set_attr "length" "4")]) 6966 6967(define_insn "consttable_df" 6968 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)] 6969 "" 6970 "* 6971{ 6972 REAL_VALUE_TYPE r; 6973 6974 if (GET_CODE (operands[0]) != CONST_DOUBLE) 6975 abort (); 6976 6977 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]); 6978 assemble_real (r, DFmode, 8*BITS_PER_UNIT); 6979 return \"\"; 6980}" 6981 [(set_attr "op_type" "NN") 6982 (set_attr "length" "8")]) 6983 6984(define_insn "pool_start_31" 6985 [(unspec_volatile [(const_int 0)] 206)] 6986 "!TARGET_64BIT" 6987 ".align\\t4" 6988 [(set_attr "op_type" "NN") 6989 (set_attr "length" "2")]) 6990 6991(define_insn "pool_end_31" 6992 [(unspec_volatile [(const_int 0)] 207)] 6993 "!TARGET_64BIT" 6994 ".align\\t2" 6995 [(set_attr "op_type" "NN") 6996 (set_attr "length" "2")]) 6997 6998(define_insn "pool_start_64" 6999 [(unspec_volatile [(const_int 0)] 206)] 7000 "TARGET_64BIT" 7001 ".section\\t.rodata\;.align\\t8" 7002 [(set_attr "op_type" "NN") 7003 (set_attr "length" "0")]) 7004 7005(define_insn "pool_end_64" 7006 [(unspec_volatile [(const_int 0)] 207)] 7007 "TARGET_64BIT" 7008 ".previous" 7009 [(set_attr "op_type" "NN") 7010 (set_attr "length" "0")]) 7011 7012(define_insn "reload_base_31" 7013 [(set (match_operand:SI 0 "register_operand" "=a") 7014 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))] 7015 "!TARGET_64BIT" 7016 "basr\\t%0,0\;la\\t%0,%1-.(%0)" 7017 [(set_attr "op_type" "NN") 7018 (set_attr "type" "la") 7019 (set_attr "length" "6")]) 7020 7021(define_insn "reload_base_64" 7022 [(set (match_operand:DI 0 "register_operand" "=a") 7023 (unspec:DI [(label_ref (match_operand 1 "" ""))] 210))] 7024 "TARGET_64BIT" 7025 "larl\\t%0,%1" 7026 [(set_attr "op_type" "RIL") 7027 (set_attr "type" "la")]) 7028 7029(define_insn "reload_anchor" 7030 [(set (match_operand:SI 0 "register_operand" "=a") 7031 (unspec:SI [(match_operand:SI 1 "register_operand" "a")] 211))] 7032 "!TARGET_64BIT" 7033 "l\\t%0,0(%1)\;la\\t%0,0(%0,%1)" 7034 [(set_attr "op_type" "NN") 7035 (set_attr "type" "la") 7036 (set_attr "length" "8")]) 7037 7038(define_insn "pool" 7039 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 220)] 7040 "" 7041 "* abort ();" 7042 [(set_attr "op_type" "NN") 7043 (set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) 7044 7045;; 7046;; Insns related to generating the function prologue and epilogue. 7047;; 7048 7049 7050(define_expand "prologue" 7051 [(use (const_int 0))] 7052 "" 7053 " 7054{ 7055 s390_emit_prologue (); 7056 DONE; 7057}") 7058 7059(define_expand "epilogue" 7060 [(use (const_int 1))] 7061 "" 7062 " 7063{ 7064 s390_emit_epilogue (); 7065 DONE; 7066}") 7067 7068 7069(define_insn "*return_si" 7070 [(return) 7071 (use (match_operand:SI 0 "register_operand" "a"))] 7072 "!TARGET_64BIT" 7073 "br\\t%0" 7074 [(set_attr "op_type" "RR") 7075 (set_attr "type" "jsr") 7076 (set_attr "atype" "mem")]) 7077 7078(define_insn "*return_di" 7079 [(return) 7080 (use (match_operand:DI 0 "register_operand" "a"))] 7081 "TARGET_64BIT" 7082 "br\\t%0" 7083 [(set_attr "op_type" "RR") 7084 (set_attr "type" "jsr") 7085 (set_attr "atype" "mem")]) 7086 7087(define_insn "literal_pool_31" 7088 [(unspec_volatile [(const_int 0)] 300) 7089 (set (match_operand:SI 0 "register_operand" "=a") 7090 (label_ref (match_operand 1 "" ""))) 7091 (use (label_ref (match_operand 2 "" "")))] 7092 "" 7093{ 7094 if (s390_nr_constants) 7095 { 7096 output_asm_insn ("bras\\t%0,%2", operands); 7097 s390_output_constant_pool (operands[1], operands[2]); 7098 } 7099 else if (flag_pic) 7100 { 7101 /* We need the anchor label in any case. */ 7102 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 7103 CODE_LABEL_NUMBER (operands[1])); 7104 } 7105 7106 return ""; 7107} 7108 [(set_attr "op_type" "NN") 7109 (set_attr "type" "la")]) 7110 7111(define_insn "literal_pool_64" 7112 [(unspec_volatile [(const_int 0)] 300) 7113 (set (match_operand:DI 0 "register_operand" "=a") 7114 (label_ref (match_operand 1 "" ""))) 7115 (use (label_ref (match_operand 2 "" "")))] 7116 "" 7117{ 7118 if (s390_nr_constants) 7119 { 7120 output_asm_insn ("larl\\t%0,%1", operands); 7121 s390_output_constant_pool (operands[1], operands[2]); 7122 } 7123 7124 return ""; 7125} 7126 [(set_attr "op_type" "NN") 7127 (set_attr "type" "la")]) 7128