altivec.md revision 117395
1;; AltiVec patterns. 2;; Copyright (C) 2002 Free Software Foundation, Inc. 3;; Contributed by Aldy Hernandez (aldy@quesejoda.com) 4 5;; This file is part of GNU CC. 6 7;; GNU CC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 2, or (at your option) 10;; any later version. 11 12;; GNU CC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GNU CC; see the file COPYING. If not, write to 19;; the Free Software Foundation, 59 Temple Place - Suite 330, 20;; Boston, MA 02111-1307, USA. 21 22;; Generic LVX load instruction. 23(define_insn "altivec_lvx_4si" 24 [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") 25 (match_operand:V4SI 1 "memory_operand" "m"))] 26 "TARGET_ALTIVEC" 27 "lvx %0,%y1" 28 [(set_attr "type" "vecload")]) 29 30(define_insn "altivec_lvx_8hi" 31 [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") 32 (match_operand:V8HI 1 "memory_operand" "m"))] 33 "TARGET_ALTIVEC" 34 "lvx %0,%y1" 35 [(set_attr "type" "vecload")]) 36 37(define_insn "altivec_lvx_16qi" 38 [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") 39 (match_operand:V16QI 1 "memory_operand" "m"))] 40 "TARGET_ALTIVEC" 41 "lvx %0,%y1" 42 [(set_attr "type" "vecload")]) 43 44(define_insn "altivec_lvx_4sf" 45 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") 46 (match_operand:V4SF 1 "memory_operand" "m"))] 47 "TARGET_ALTIVEC" 48 "lvx %0,%y1" 49 [(set_attr "type" "vecload")]) 50 51;; Generic STVX store instruction. 52(define_insn "altivec_stvx_4si" 53 [(set (match_operand:V4SI 0 "memory_operand" "=m") 54 (match_operand:V4SI 1 "altivec_register_operand" "v"))] 55 "TARGET_ALTIVEC" 56 "stvx %1,%y0" 57 [(set_attr "type" "vecstore")]) 58 59(define_insn "altivec_stvx_8hi" 60 [(set (match_operand:V8HI 0 "memory_operand" "=m") 61 (match_operand:V8HI 1 "altivec_register_operand" "v"))] 62 "TARGET_ALTIVEC" 63 "stvx %1,%y0" 64 [(set_attr "type" "vecstore")]) 65 66(define_insn "altivec_stvx_16qi" 67 [(set (match_operand:V16QI 0 "memory_operand" "=m") 68 (match_operand:V16QI 1 "altivec_register_operand" "v"))] 69 "TARGET_ALTIVEC" 70 "stvx %1,%y0" 71 [(set_attr "type" "vecstore")]) 72 73(define_insn "altivec_stvx_4sf" 74 [(set (match_operand:V4SF 0 "memory_operand" "=m") 75 (match_operand:V4SF 1 "altivec_register_operand" "v"))] 76 "TARGET_ALTIVEC" 77 "stvx %1,%y0" 78 [(set_attr "type" "vecstore")]) 79 80;; Vector move instructions. 81(define_expand "movv4si" 82 [(set (match_operand:V4SI 0 "nonimmediate_operand" "") 83 (match_operand:V4SI 1 "any_operand" ""))] 84 "TARGET_ALTIVEC" 85 "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }") 86 87(define_insn "*movv4si_internal" 88 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r") 89 (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r"))] 90 "TARGET_ALTIVEC" 91 "@ 92 stvx %1,%y0 93 lvx %0,%y1 94 vor %0,%1,%1 95 stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 96 lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 97 mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" 98 [(set_attr "type" "altivec") 99 (set_attr "length" "*,*,*,16,16,16")]) 100 101(define_expand "movv8hi" 102 [(set (match_operand:V8HI 0 "nonimmediate_operand" "") 103 (match_operand:V8HI 1 "any_operand" ""))] 104 "TARGET_ALTIVEC" 105 "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }") 106 107(define_insn "*movv8hi_internal1" 108 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r") 109 (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r"))] 110 "TARGET_ALTIVEC" 111 "@ 112 stvx %1,%y0 113 lvx %0,%y1 114 vor %0,%1,%1 115 stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 116 lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 117 mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" 118 [(set_attr "type" "altivec") 119 (set_attr "length" "*,*,*,16,16,16")]) 120 121(define_expand "movv16qi" 122 [(set (match_operand:V16QI 0 "nonimmediate_operand" "") 123 (match_operand:V16QI 1 "any_operand" ""))] 124 "TARGET_ALTIVEC" 125 "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }") 126 127(define_insn "*movv16qi_internal1" 128 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r") 129 (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r"))] 130 "TARGET_ALTIVEC" 131 "@ 132 stvx %1,%y0 133 lvx %0,%y1 134 vor %0,%1,%1 135 stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 136 lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 137 mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" 138 [(set_attr "type" "altivec") 139 (set_attr "length" "*,*,*,16,16,16")]) 140 141(define_expand "movv4sf" 142 [(set (match_operand:V4SF 0 "nonimmediate_operand" "") 143 (match_operand:V4SF 1 "any_operand" ""))] 144 "TARGET_ALTIVEC" 145 "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }") 146 147(define_insn "*movv4sf_internal1" 148 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r") 149 (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r"))] 150 "TARGET_ALTIVEC" 151 "@ 152 stvx %1,%y0 153 lvx %0,%y1 154 vor %0,%1,%1 155 stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 156 lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 157 mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" 158 [(set_attr "type" "altivec") 159 (set_attr "length" "*,*,*,16,16,16")]) 160 161(define_insn "get_vrsave_internal" 162 [(set (match_operand:SI 0 "register_operand" "=r") 163 (unspec:SI [(reg:SI 109)] 214))] 164 "TARGET_ALTIVEC" 165 "* 166{ 167 if (TARGET_MACHO) 168 return \"mfspr %0,256\"; 169 else 170 return \"mfvrsave %0\"; 171}" 172 [(set_attr "type" "altivec")]) 173 174(define_insn "*set_vrsave_internal" 175 [(match_parallel 0 "vrsave_operation" 176 [(set (reg:SI 109) 177 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") 178 (reg:SI 109)] 30))])] 179 "TARGET_ALTIVEC" 180 "* 181{ 182 if (TARGET_MACHO) 183 return \"mtspr 256,%1\"; 184 else 185 return \"mtvrsave %1\"; 186}" 187 [(set_attr "type" "altivec")]) 188 189;; Vector clears 190(define_insn "*movv4si_const0" 191 [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") 192 (match_operand:V4SI 1 "zero_constant" ""))] 193 "TARGET_ALTIVEC" 194 "vxor %0,%0,%0" 195 [(set_attr "type" "vecsimple")]) 196 197(define_insn "*movv4sf_const0" 198 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") 199 (match_operand:V4SF 1 "zero_constant" ""))] 200 201 "TARGET_ALTIVEC" 202 "vxor %0,%0,%0" 203 [(set_attr "type" "vecsimple")]) 204 205(define_insn "*movv8hi_const0" 206 [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") 207 (match_operand:V8HI 1 "zero_constant" ""))] 208 "TARGET_ALTIVEC" 209 "vxor %0,%0,%0" 210 [(set_attr "type" "vecsimple")]) 211 212(define_insn "*movv16qi_const0" 213 [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") 214 (match_operand:V16QI 1 "zero_constant" ""))] 215 "TARGET_ALTIVEC" 216 "vxor %0,%0,%0" 217 [(set_attr "type" "vecsimple")]) 218 219;; Simple binary operations. 220 221(define_insn "addv16qi3" 222 [(set (match_operand:V16QI 0 "register_operand" "=v") 223 (plus:V16QI (match_operand:V16QI 1 "register_operand" "v") 224 (match_operand:V16QI 2 "register_operand" "v")))] 225 "TARGET_ALTIVEC" 226 "vaddubm %0,%1,%2" 227 [(set_attr "type" "vecsimple")]) 228 229(define_insn "addv8hi3" 230 [(set (match_operand:V8HI 0 "register_operand" "=v") 231 (plus:V8HI (match_operand:V8HI 1 "register_operand" "v") 232 (match_operand:V8HI 2 "register_operand" "v")))] 233 "TARGET_ALTIVEC" 234 "vadduhm %0,%1,%2" 235 [(set_attr "type" "vecsimple")]) 236 237(define_insn "addv4si3" 238 [(set (match_operand:V4SI 0 "register_operand" "=v") 239 (plus:V4SI (match_operand:V4SI 1 "register_operand" "v") 240 (match_operand:V4SI 2 "register_operand" "v")))] 241 "TARGET_ALTIVEC" 242 "vadduwm %0,%1,%2" 243 [(set_attr "type" "vecsimple")]) 244 245(define_insn "addv4sf3" 246 [(set (match_operand:V4SF 0 "register_operand" "=v") 247 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v") 248 (match_operand:V4SF 2 "register_operand" "v")))] 249 "TARGET_ALTIVEC" 250 "vaddfp %0,%1,%2" 251 [(set_attr "type" "vecfloat")]) 252 253(define_insn "altivec_vaddcuw" 254 [(set (match_operand:V4SI 0 "register_operand" "=v") 255 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 256 (match_operand:V4SI 2 "register_operand" "v")] 35))] 257 "TARGET_ALTIVEC" 258 "vaddcuw %0,%1,%2" 259 [(set_attr "type" "vecsimple")]) 260 261(define_insn "altivec_vaddubs" 262 [(set (match_operand:V16QI 0 "register_operand" "=v") 263 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 264 (match_operand:V16QI 2 "register_operand" "v")] 36)) 265 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 266 "TARGET_ALTIVEC" 267 "vaddubs %0,%1,%2" 268 [(set_attr "type" "vecsimple")]) 269 270(define_insn "altivec_vaddsbs" 271 [(set (match_operand:V16QI 0 "register_operand" "=v") 272 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 273 (match_operand:V16QI 2 "register_operand" "v")] 37)) 274 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 275 "TARGET_ALTIVEC" 276 "vaddsbs %0,%1,%2" 277 [(set_attr "type" "vecsimple")]) 278 279(define_insn "altivec_vadduhs" 280 [(set (match_operand:V8HI 0 "register_operand" "=v") 281 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 282 (match_operand:V8HI 2 "register_operand" "v")] 38)) 283 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 284 "TARGET_ALTIVEC" 285 "vadduhs %0,%1,%2" 286 [(set_attr "type" "vecsimple")]) 287 288(define_insn "altivec_vaddshs" 289 [(set (match_operand:V8HI 0 "register_operand" "=v") 290 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 291 (match_operand:V8HI 2 "register_operand" "v")] 39)) 292 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 293 "TARGET_ALTIVEC" 294 "vaddshs %0,%1,%2" 295 [(set_attr "type" "vecsimple")]) 296 297(define_insn "altivec_vadduws" 298 [(set (match_operand:V4SI 0 "register_operand" "=v") 299 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 300 (match_operand:V4SI 2 "register_operand" "v")] 40)) 301 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 302 "TARGET_ALTIVEC" 303 "vadduws %0,%1,%2" 304 [(set_attr "type" "vecsimple")]) 305 306(define_insn "altivec_vaddsws" 307 [(set (match_operand:V4SI 0 "register_operand" "=v") 308 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 309 (match_operand:V4SI 2 "register_operand" "v")] 41)) 310 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 311 "TARGET_ALTIVEC" 312 "vaddsws %0,%1,%2" 313 [(set_attr "type" "vecsimple")]) 314 315(define_insn "andv4si3" 316 [(set (match_operand:V4SI 0 "register_operand" "=v") 317 (and:V4SI (match_operand:V4SI 1 "register_operand" "v") 318 (match_operand:V4SI 2 "register_operand" "v")))] 319 "TARGET_ALTIVEC" 320 "vand %0,%1,%2" 321 [(set_attr "type" "vecsimple")]) 322 323(define_insn "altivec_vandc" 324 [(set (match_operand:V4SI 0 "register_operand" "=v") 325 (and:V4SI (match_operand:V4SI 1 "register_operand" "v") 326 (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))] 327 "TARGET_ALTIVEC" 328 "vandc %0,%1,%2" 329 [(set_attr "type" "vecsimple")]) 330 331(define_insn "altivec_vavgub" 332 [(set (match_operand:V16QI 0 "register_operand" "=v") 333 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 334 (match_operand:V16QI 2 "register_operand" "v")] 44))] 335 "TARGET_ALTIVEC" 336 "vavgub %0,%1,%2" 337 [(set_attr "type" "vecsimple")]) 338 339(define_insn "altivec_vavgsb" 340 [(set (match_operand:V16QI 0 "register_operand" "=v") 341 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 342 (match_operand:V16QI 2 "register_operand" "v")] 45))] 343 "TARGET_ALTIVEC" 344 "vavgsb %0,%1,%2" 345 [(set_attr "type" "vecsimple")]) 346 347(define_insn "altivec_vavguh" 348 [(set (match_operand:V8HI 0 "register_operand" "=v") 349 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 350 (match_operand:V8HI 2 "register_operand" "v")] 46))] 351 "TARGET_ALTIVEC" 352 "vavguh %0,%1,%2" 353 [(set_attr "type" "vecsimple")]) 354 355(define_insn "altivec_vavgsh" 356 [(set (match_operand:V8HI 0 "register_operand" "=v") 357 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 358 (match_operand:V8HI 2 "register_operand" "v")] 47))] 359 "TARGET_ALTIVEC" 360 "vavgsh %0,%1,%2" 361 [(set_attr "type" "vecsimple")]) 362 363(define_insn "altivec_vavguw" 364 [(set (match_operand:V4SI 0 "register_operand" "=v") 365 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 366 (match_operand:V4SI 2 "register_operand" "v")] 48))] 367 "TARGET_ALTIVEC" 368 "vavguw %0,%1,%2" 369 [(set_attr "type" "vecsimple")]) 370 371(define_insn "altivec_vavgsw" 372 [(set (match_operand:V4SI 0 "register_operand" "=v") 373 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 374 (match_operand:V4SI 2 "register_operand" "v")] 49))] 375 "TARGET_ALTIVEC" 376 "vavgsw %0,%1,%2" 377 [(set_attr "type" "vecsimple")]) 378 379(define_insn "altivec_vcmpbfp" 380 [(set (match_operand:V4SI 0 "register_operand" "=v") 381 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 382 (match_operand:V4SF 2 "register_operand" "v")] 50))] 383 "TARGET_ALTIVEC" 384 "vcmpbfp %0,%1,%2" 385 [(set_attr "type" "veccmp")]) 386 387(define_insn "altivec_vcmpequb" 388 [(set (match_operand:V16QI 0 "register_operand" "=v") 389 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 390 (match_operand:V16QI 2 "register_operand" "v")] 51))] 391 "TARGET_ALTIVEC" 392 "vcmpequb %0,%1,%2" 393 [(set_attr "type" "vecsimple")]) 394 395(define_insn "altivec_vcmpequh" 396 [(set (match_operand:V8HI 0 "register_operand" "=v") 397 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 398 (match_operand:V8HI 2 "register_operand" "v")] 52))] 399 "TARGET_ALTIVEC" 400 "vcmpequh %0,%1,%2" 401 [(set_attr "type" "vecsimple")]) 402 403(define_insn "altivec_vcmpequw" 404 [(set (match_operand:V4SI 0 "register_operand" "=v") 405 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 406 (match_operand:V4SI 2 "register_operand" "v")] 53))] 407 "TARGET_ALTIVEC" 408 "vcmpequw %0,%1,%2" 409 [(set_attr "type" "vecsimple")]) 410 411(define_insn "altivec_vcmpeqfp" 412 [(set (match_operand:V4SI 0 "register_operand" "=v") 413 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 414 (match_operand:V4SF 2 "register_operand" "v")] 54))] 415 "TARGET_ALTIVEC" 416 "vcmpeqfp %0,%1,%2" 417 [(set_attr "type" "veccmp")]) 418 419(define_insn "altivec_vcmpgefp" 420 [(set (match_operand:V4SI 0 "register_operand" "=v") 421 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 422 (match_operand:V4SF 2 "register_operand" "v")] 55))] 423 "TARGET_ALTIVEC" 424 "vcmpgefp %0,%1,%2" 425 [(set_attr "type" "veccmp")]) 426 427(define_insn "altivec_vcmpgtub" 428 [(set (match_operand:V16QI 0 "register_operand" "=v") 429 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 430 (match_operand:V16QI 2 "register_operand" "v")] 56))] 431 "TARGET_ALTIVEC" 432 "vcmpgtub %0,%1,%2" 433 [(set_attr "type" "vecsimple")]) 434 435(define_insn "altivec_vcmpgtsb" 436 [(set (match_operand:V16QI 0 "register_operand" "=v") 437 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 438 (match_operand:V16QI 2 "register_operand" "v")] 57))] 439 "TARGET_ALTIVEC" 440 "vcmpgtsb %0,%1,%2" 441 [(set_attr "type" "vecsimple")]) 442 443(define_insn "altivec_vcmpgtuh" 444 [(set (match_operand:V8HI 0 "register_operand" "=v") 445 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 446 (match_operand:V8HI 2 "register_operand" "v")] 58))] 447 "TARGET_ALTIVEC" 448 "vcmpgtuh %0,%1,%2" 449 [(set_attr "type" "vecsimple")]) 450 451(define_insn "altivec_vcmpgtsh" 452 [(set (match_operand:V8HI 0 "register_operand" "=v") 453 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 454 (match_operand:V8HI 2 "register_operand" "v")] 59))] 455 "TARGET_ALTIVEC" 456 "vcmpgtsh %0,%1,%2" 457 [(set_attr "type" "vecsimple")]) 458 459(define_insn "altivec_vcmpgtuw" 460 [(set (match_operand:V4SI 0 "register_operand" "=v") 461 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 462 (match_operand:V4SI 2 "register_operand" "v")] 60))] 463 "TARGET_ALTIVEC" 464 "vcmpgtuw %0,%1,%2" 465 [(set_attr "type" "vecsimple")]) 466 467(define_insn "altivec_vcmpgtsw" 468 [(set (match_operand:V4SI 0 "register_operand" "=v") 469 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 470 (match_operand:V4SI 2 "register_operand" "v")] 61))] 471 "TARGET_ALTIVEC" 472 "vcmpgtsw %0,%1,%2" 473 [(set_attr "type" "vecsimple")]) 474 475(define_insn "altivec_vcmpgtfp" 476 [(set (match_operand:V4SI 0 "register_operand" "=v") 477 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 478 (match_operand:V4SF 2 "register_operand" "v")] 62))] 479 "TARGET_ALTIVEC" 480 "vcmpgtfp %0,%1,%2" 481 [(set_attr "type" "veccmp")]) 482 483;; Fused multiply add 484(define_insn "altivec_vmaddfp" 485 [(set (match_operand:V4SF 0 "register_operand" "=v") 486 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") 487 (match_operand:V4SF 2 "register_operand" "v")) 488 (match_operand:V4SF 3 "register_operand" "v")))] 489 "TARGET_ALTIVEC" 490 "vmaddfp %0,%1,%2,%3" 491 [(set_attr "type" "vecfloat")]) 492 493;; We do multiply as a fused multiply-add with an add of a -0.0 vector. 494 495(define_expand "mulv4sf3" 496 [(use (match_operand:V4SF 0 "register_operand" "")) 497 (use (match_operand:V4SF 1 "register_operand" "")) 498 (use (match_operand:V4SF 2 "register_operand" ""))] 499 "TARGET_ALTIVEC && TARGET_FUSED_MADD" 500 " 501{ 502 rtx neg0; 503 504 /* Generate [-0.0, -0.0, -0.0, -0.0]. */ 505 neg0 = gen_reg_rtx (V4SFmode); 506 emit_insn (gen_altivec_vspltisw_v4sf (neg0, GEN_INT (-1))); 507 emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0)); 508 509 /* Use the multiply-add. */ 510 emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2], 511 neg0)); 512 DONE; 513}") 514 515;; Fused multiply subtract 516(define_insn "altivec_vnmsubfp" 517 [(set (match_operand:V4SF 0 "register_operand" "=v") 518 (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") 519 (match_operand:V4SF 2 "register_operand" "v")) 520 (match_operand:V4SF 3 "register_operand" "v")))] 521 "TARGET_ALTIVEC" 522 "vnmsubfp %0,%1,%2,%3" 523 [(set_attr "type" "vecfloat")]) 524 525 526(define_insn "altivec_vmsumubm" 527 [(set (match_operand:V4SI 0 "register_operand" "=v") 528 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") 529 (match_operand:V16QI 2 "register_operand" "v") 530 (match_operand:V4SI 3 "register_operand" "v")] 65))] 531 "TARGET_ALTIVEC" 532 "vmsumubm %0, %1, %2, %3" 533 [(set_attr "type" "veccomplex")]) 534 535(define_insn "altivec_vmsummbm" 536 [(set (match_operand:V4SI 0 "register_operand" "=v") 537 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") 538 (match_operand:V16QI 2 "register_operand" "v") 539 (match_operand:V4SI 3 "register_operand" "v")] 66))] 540 "TARGET_ALTIVEC" 541 "vmsumubm %0, %1, %2, %3" 542 [(set_attr "type" "veccomplex")]) 543 544(define_insn "altivec_vmsumuhm" 545 [(set (match_operand:V4SI 0 "register_operand" "=v") 546 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 547 (match_operand:V8HI 2 "register_operand" "v") 548 (match_operand:V4SI 3 "register_operand" "v")] 67))] 549 "TARGET_ALTIVEC" 550 "vmsumuhm %0, %1, %2, %3" 551 [(set_attr "type" "veccomplex")]) 552 553(define_insn "altivec_vmsumshm" 554 [(set (match_operand:V4SI 0 "register_operand" "=v") 555 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 556 (match_operand:V8HI 2 "register_operand" "v") 557 (match_operand:V4SI 3 "register_operand" "v")] 68))] 558 "TARGET_ALTIVEC" 559 "vmsumshm %0, %1, %2, %3" 560 [(set_attr "type" "veccomplex")]) 561 562(define_insn "altivec_vmsumuhs" 563 [(set (match_operand:V4SI 0 "register_operand" "=v") 564 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 565 (match_operand:V8HI 2 "register_operand" "v") 566 (match_operand:V4SI 3 "register_operand" "v")] 69)) 567 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 568 "TARGET_ALTIVEC" 569 "vmsumuhs %0, %1, %2, %3" 570 [(set_attr "type" "veccomplex")]) 571 572(define_insn "altivec_vmsumshs" 573 [(set (match_operand:V4SI 0 "register_operand" "=v") 574 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 575 (match_operand:V8HI 2 "register_operand" "v") 576 (match_operand:V4SI 3 "register_operand" "v")] 70)) 577 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 578 "TARGET_ALTIVEC" 579 "vmsumshs %0, %1, %2, %3" 580 [(set_attr "type" "veccomplex")]) 581 582(define_insn "umaxv16qi3" 583 [(set (match_operand:V16QI 0 "register_operand" "=v") 584 (umax:V16QI (match_operand:V16QI 1 "register_operand" "v") 585 (match_operand:V16QI 2 "register_operand" "v")))] 586 "TARGET_ALTIVEC" 587 "vmaxub %0,%1,%2" 588 [(set_attr "type" "vecsimple")]) 589 590(define_insn "smaxv16qi3" 591 [(set (match_operand:V16QI 0 "register_operand" "=v") 592 (smax:V16QI (match_operand:V16QI 1 "register_operand" "v") 593 (match_operand:V16QI 2 "register_operand" "v")))] 594 "TARGET_ALTIVEC" 595 "vmaxsb %0,%1,%2" 596 [(set_attr "type" "vecsimple")]) 597 598(define_insn "umaxv8hi3" 599 [(set (match_operand:V8HI 0 "register_operand" "=v") 600 (umax:V8HI (match_operand:V8HI 1 "register_operand" "v") 601 (match_operand:V8HI 2 "register_operand" "v")))] 602 "TARGET_ALTIVEC" 603 "vmaxuh %0,%1,%2" 604 [(set_attr "type" "vecsimple")]) 605 606(define_insn "smaxv8hi3" 607 [(set (match_operand:V8HI 0 "register_operand" "=v") 608 (smax:V8HI (match_operand:V8HI 1 "register_operand" "v") 609 (match_operand:V8HI 2 "register_operand" "v")))] 610 "TARGET_ALTIVEC" 611 "vmaxsh %0,%1,%2" 612 [(set_attr "type" "vecsimple")]) 613 614(define_insn "umaxv4si3" 615 [(set (match_operand:V4SI 0 "register_operand" "=v") 616 (umax:V4SI (match_operand:V4SI 1 "register_operand" "v") 617 (match_operand:V4SI 2 "register_operand" "v")))] 618 "TARGET_ALTIVEC" 619 "vmaxuw %0,%1,%2" 620 [(set_attr "type" "vecsimple")]) 621 622(define_insn "smaxv4si3" 623 [(set (match_operand:V4SI 0 "register_operand" "=v") 624 (smax:V4SI (match_operand:V4SI 1 "register_operand" "v") 625 (match_operand:V4SI 2 "register_operand" "v")))] 626 "TARGET_ALTIVEC" 627 "vmaxsw %0,%1,%2" 628 [(set_attr "type" "vecsimple")]) 629 630(define_insn "smaxv4sf3" 631 [(set (match_operand:V4SF 0 "register_operand" "=v") 632 (smax:V4SF (match_operand:V4SF 1 "register_operand" "v") 633 (match_operand:V4SF 2 "register_operand" "v")))] 634 "TARGET_ALTIVEC" 635 "vmaxfp %0,%1,%2" 636 [(set_attr "type" "veccmp")]) 637 638(define_insn "altivec_vmhaddshs" 639 [(set (match_operand:V8HI 0 "register_operand" "=v") 640 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 641 (match_operand:V8HI 2 "register_operand" "v") 642 (match_operand:V8HI 3 "register_operand" "v")] 71)) 643 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 644 "TARGET_ALTIVEC" 645 "vmhaddshs %0, %1, %2, %3" 646 [(set_attr "type" "veccomplex")]) 647(define_insn "altivec_vmhraddshs" 648 [(set (match_operand:V8HI 0 "register_operand" "=v") 649 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 650 (match_operand:V8HI 2 "register_operand" "v") 651 (match_operand:V8HI 3 "register_operand" "v")] 72)) 652 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 653 "TARGET_ALTIVEC" 654 "vmhraddshs %0, %1, %2, %3" 655 [(set_attr "type" "veccomplex")]) 656(define_insn "altivec_vmladduhm" 657 [(set (match_operand:V8HI 0 "register_operand" "=v") 658 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 659 (match_operand:V8HI 2 "register_operand" "v") 660 (match_operand:V8HI 3 "register_operand" "v")] 73))] 661 "TARGET_ALTIVEC" 662 "vmladduhm %0, %1, %2, %3" 663 [(set_attr "type" "veccomplex")]) 664 665(define_insn "altivec_vmrghb" 666 [(set (match_operand:V16QI 0 "register_operand" "=v") 667 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v") 668 (parallel [(const_int 8) 669 (const_int 9) 670 (const_int 10) 671 (const_int 11) 672 (const_int 12) 673 (const_int 13) 674 (const_int 14) 675 (const_int 15) 676 (const_int 0) 677 (const_int 1) 678 (const_int 2) 679 (const_int 3) 680 (const_int 4) 681 (const_int 5) 682 (const_int 6) 683 (const_int 7)])) 684 (match_operand:V16QI 2 "register_operand" "v") 685 (const_int 255)))] 686 "TARGET_ALTIVEC" 687 "vmrghb %0,%1,%2" 688 [(set_attr "type" "vecperm")]) 689 690(define_insn "altivec_vmrghh" 691 [(set (match_operand:V8HI 0 "register_operand" "=v") 692 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v") 693 (parallel [(const_int 4) 694 (const_int 5) 695 (const_int 6) 696 (const_int 7) 697 (const_int 0) 698 (const_int 1) 699 (const_int 2) 700 (const_int 3)])) 701 (match_operand:V8HI 2 "register_operand" "v") 702 (const_int 15)))] 703 "TARGET_ALTIVEC" 704 "vmrghh %0,%1,%2" 705 [(set_attr "type" "vecperm")]) 706 707(define_insn "altivec_vmrghw" 708 [(set (match_operand:V4SI 0 "register_operand" "=v") 709 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v") 710 (parallel [(const_int 2) 711 (const_int 3) 712 (const_int 0) 713 (const_int 1)])) 714 (match_operand:V4SI 2 "register_operand" "v") 715 (const_int 12)))] 716 "TARGET_ALTIVEC" 717 "vmrghw %0,%1,%2" 718 [(set_attr "type" "vecperm")]) 719 720(define_insn "altivec_vmrglb" 721 [(set (match_operand:V16QI 0 "register_operand" "=v") 722 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v") 723 (parallel [(const_int 0) 724 (const_int 1) 725 (const_int 2) 726 (const_int 3) 727 (const_int 4) 728 (const_int 5) 729 (const_int 6) 730 (const_int 7) 731 (const_int 8) 732 (const_int 9) 733 (const_int 10) 734 (const_int 11) 735 (const_int 12) 736 (const_int 13) 737 (const_int 14) 738 (const_int 15)])) 739 (match_operand:V16QI 1 "register_operand" "v") 740 (const_int 255)))] 741 "TARGET_ALTIVEC" 742 "vmrglb %0,%1,%2" 743 [(set_attr "type" "vecperm")]) 744 745(define_insn "altivec_vmrglh" 746 [(set (match_operand:V8HI 0 "register_operand" "=v") 747 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v") 748 (parallel [(const_int 0) 749 (const_int 1) 750 (const_int 2) 751 (const_int 3) 752 (const_int 4) 753 (const_int 5) 754 (const_int 6) 755 (const_int 7)])) 756 (match_operand:V8HI 1 "register_operand" "v") 757 (const_int 15)))] 758 "TARGET_ALTIVEC" 759 "vmrglh %0,%1,%2" 760 [(set_attr "type" "vecperm")]) 761 762(define_insn "altivec_vmrglw" 763 [(set (match_operand:V4SI 0 "register_operand" "=v") 764 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v") 765 (parallel [(const_int 0) 766 (const_int 1) 767 (const_int 2) 768 (const_int 3)])) 769 (match_operand:V4SI 1 "register_operand" "v") 770 (const_int 12)))] 771 "TARGET_ALTIVEC" 772 "vmrglw %0,%1,%2" 773 [(set_attr "type" "vecperm")]) 774 775(define_insn "uminv16qi3" 776 [(set (match_operand:V16QI 0 "register_operand" "=v") 777 (umin:V16QI (match_operand:V16QI 1 "register_operand" "v") 778 (match_operand:V16QI 2 "register_operand" "v")))] 779 "TARGET_ALTIVEC" 780 "vminub %0,%1,%2" 781 [(set_attr "type" "vecsimple")]) 782 783(define_insn "sminv16qi3" 784 [(set (match_operand:V16QI 0 "register_operand" "=v") 785 (smin:V16QI (match_operand:V16QI 1 "register_operand" "v") 786 (match_operand:V16QI 2 "register_operand" "v")))] 787 "TARGET_ALTIVEC" 788 "vminsb %0,%1,%2" 789 [(set_attr "type" "vecsimple")]) 790 791(define_insn "uminv8hi3" 792 [(set (match_operand:V8HI 0 "register_operand" "=v") 793 (umin:V8HI (match_operand:V8HI 1 "register_operand" "v") 794 (match_operand:V8HI 2 "register_operand" "v")))] 795 "TARGET_ALTIVEC" 796 "vminuh %0,%1,%2" 797 [(set_attr "type" "vecsimple")]) 798 799(define_insn "sminv8hi3" 800 [(set (match_operand:V8HI 0 "register_operand" "=v") 801 (smin:V8HI (match_operand:V8HI 1 "register_operand" "v") 802 (match_operand:V8HI 2 "register_operand" "v")))] 803 "TARGET_ALTIVEC" 804 "vminsh %0,%1,%2" 805 [(set_attr "type" "vecsimple")]) 806 807(define_insn "uminv4si3" 808 [(set (match_operand:V4SI 0 "register_operand" "=v") 809 (umin:V4SI (match_operand:V4SI 1 "register_operand" "v") 810 (match_operand:V4SI 2 "register_operand" "v")))] 811 "TARGET_ALTIVEC" 812 "vminuw %0,%1,%2" 813 [(set_attr "type" "vecsimple")]) 814 815(define_insn "sminv4si3" 816 [(set (match_operand:V4SI 0 "register_operand" "=v") 817 (smin:V4SI (match_operand:V4SI 1 "register_operand" "v") 818 (match_operand:V4SI 2 "register_operand" "v")))] 819 "TARGET_ALTIVEC" 820 "vminsw %0,%1,%2" 821 [(set_attr "type" "vecsimple")]) 822 823(define_insn "sminv4sf3" 824 [(set (match_operand:V4SF 0 "register_operand" "=v") 825 (smin:V4SF (match_operand:V4SF 1 "register_operand" "v") 826 (match_operand:V4SF 2 "register_operand" "v")))] 827 "TARGET_ALTIVEC" 828 "vminfp %0,%1,%2" 829 [(set_attr "type" "veccmp")]) 830 831(define_insn "altivec_vmuleub" 832 [(set (match_operand:V8HI 0 "register_operand" "=v") 833 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") 834 (match_operand:V16QI 2 "register_operand" "v")] 83))] 835 "TARGET_ALTIVEC" 836 "vmuleub %0,%1,%2" 837 [(set_attr "type" "veccomplex")]) 838 839(define_insn "altivec_vmulesb" 840 [(set (match_operand:V8HI 0 "register_operand" "=v") 841 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") 842 (match_operand:V16QI 2 "register_operand" "v")] 84))] 843 "TARGET_ALTIVEC" 844 "vmulesb %0,%1,%2" 845 [(set_attr "type" "veccomplex")]) 846 847(define_insn "altivec_vmuleuh" 848 [(set (match_operand:V4SI 0 "register_operand" "=v") 849 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 850 (match_operand:V8HI 2 "register_operand" "v")] 85))] 851 "TARGET_ALTIVEC" 852 "vmuleuh %0,%1,%2" 853 [(set_attr "type" "veccomplex")]) 854 855(define_insn "altivec_vmulesh" 856 [(set (match_operand:V4SI 0 "register_operand" "=v") 857 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 858 (match_operand:V8HI 2 "register_operand" "v")] 86))] 859 "TARGET_ALTIVEC" 860 "vmulesh %0,%1,%2" 861 [(set_attr "type" "veccomplex")]) 862 863(define_insn "altivec_vmuloub" 864 [(set (match_operand:V8HI 0 "register_operand" "=v") 865 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") 866 (match_operand:V16QI 2 "register_operand" "v")] 87))] 867 "TARGET_ALTIVEC" 868 "vmuloub %0,%1,%2" 869 [(set_attr "type" "veccomplex")]) 870 871(define_insn "altivec_vmulosb" 872 [(set (match_operand:V8HI 0 "register_operand" "=v") 873 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") 874 (match_operand:V16QI 2 "register_operand" "v")] 88))] 875 "TARGET_ALTIVEC" 876 "vmulosb %0,%1,%2" 877 [(set_attr "type" "veccomplex")]) 878 879(define_insn "altivec_vmulouh" 880 [(set (match_operand:V4SI 0 "register_operand" "=v") 881 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 882 (match_operand:V8HI 2 "register_operand" "v")] 89))] 883 "TARGET_ALTIVEC" 884 "vmulouh %0,%1,%2" 885 [(set_attr "type" "veccomplex")]) 886 887(define_insn "altivec_vmulosh" 888 [(set (match_operand:V4SI 0 "register_operand" "=v") 889 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 890 (match_operand:V8HI 2 "register_operand" "v")] 90))] 891 "TARGET_ALTIVEC" 892 "vmulosh %0,%1,%2" 893 [(set_attr "type" "veccomplex")]) 894 895(define_insn "altivec_vnor" 896 [(set (match_operand:V4SI 0 "register_operand" "=v") 897 (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") 898 (match_operand:V4SI 2 "register_operand" "v"))))] 899 "TARGET_ALTIVEC" 900 "vnor %0,%1,%2" 901 [(set_attr "type" "vecsimple")]) 902 903(define_insn "iorv4si3" 904 [(set (match_operand:V4SI 0 "register_operand" "=v") 905 (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") 906 (match_operand:V4SI 2 "register_operand" "v")))] 907 "TARGET_ALTIVEC" 908 "vor %0,%1,%2" 909 [(set_attr "type" "vecsimple")]) 910 911(define_insn "altivec_vpkuhum" 912 [(set (match_operand:V16QI 0 "register_operand" "=v") 913 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 914 (match_operand:V8HI 2 "register_operand" "v")] 93))] 915 "TARGET_ALTIVEC" 916 "vpkuhum %0,%1,%2" 917 [(set_attr "type" "vecperm")]) 918 919(define_insn "altivec_vpkuwum" 920 [(set (match_operand:V8HI 0 "register_operand" "=v") 921 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 922 (match_operand:V4SI 2 "register_operand" "v")] 94))] 923 "TARGET_ALTIVEC" 924 "vpkuwum %0,%1,%2" 925 [(set_attr "type" "vecperm")]) 926 927(define_insn "altivec_vpkpx" 928 [(set (match_operand:V8HI 0 "register_operand" "=v") 929 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 930 (match_operand:V4SI 2 "register_operand" "v")] 95))] 931 "TARGET_ALTIVEC" 932 "vpkpx %0,%1,%2" 933 [(set_attr "type" "vecperm")]) 934 935(define_insn "altivec_vpkuhss" 936 [(set (match_operand:V16QI 0 "register_operand" "=v") 937 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 938 (match_operand:V8HI 2 "register_operand" "v")] 96)) 939 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 940 "TARGET_ALTIVEC" 941 "vpkuhss %0,%1,%2" 942 [(set_attr "type" "vecperm")]) 943 944(define_insn "altivec_vpkshss" 945 [(set (match_operand:V16QI 0 "register_operand" "=v") 946 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 947 (match_operand:V8HI 2 "register_operand" "v")] 97)) 948 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 949 "TARGET_ALTIVEC" 950 "vpkshss %0,%1,%2" 951 [(set_attr "type" "vecperm")]) 952 953(define_insn "altivec_vpkuwss" 954 [(set (match_operand:V8HI 0 "register_operand" "=v") 955 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 956 (match_operand:V4SI 2 "register_operand" "v")] 98)) 957 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 958 "TARGET_ALTIVEC" 959 "vpkuwss %0,%1,%2" 960 [(set_attr "type" "vecperm")]) 961 962(define_insn "altivec_vpkswss" 963 [(set (match_operand:V8HI 0 "register_operand" "=v") 964 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 965 (match_operand:V4SI 2 "register_operand" "v")] 99)) 966 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 967 "TARGET_ALTIVEC" 968 "vpkswss %0,%1,%2" 969 [(set_attr "type" "vecperm")]) 970 971(define_insn "altivec_vpkuhus" 972 [(set (match_operand:V16QI 0 "register_operand" "=v") 973 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 974 (match_operand:V8HI 2 "register_operand" "v")] 100)) 975 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 976 "TARGET_ALTIVEC" 977 "vpkuhus %0,%1,%2" 978 [(set_attr "type" "vecperm")]) 979 980(define_insn "altivec_vpkshus" 981 [(set (match_operand:V16QI 0 "register_operand" "=v") 982 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 983 (match_operand:V8HI 2 "register_operand" "v")] 101)) 984 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 985 "TARGET_ALTIVEC" 986 "vpkshus %0,%1,%2" 987 [(set_attr "type" "vecperm")]) 988 989(define_insn "altivec_vpkuwus" 990 [(set (match_operand:V8HI 0 "register_operand" "=v") 991 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 992 (match_operand:V4SI 2 "register_operand" "v")] 102)) 993 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 994 "TARGET_ALTIVEC" 995 "vpkuwus %0,%1,%2" 996 [(set_attr "type" "vecperm")]) 997 998(define_insn "altivec_vpkswus" 999 [(set (match_operand:V8HI 0 "register_operand" "=v") 1000 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 1001 (match_operand:V4SI 2 "register_operand" "v")] 103)) 1002 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1003 "TARGET_ALTIVEC" 1004 "vpkswus %0,%1,%2" 1005 [(set_attr "type" "vecperm")]) 1006 1007(define_insn "altivec_vrlb" 1008 [(set (match_operand:V16QI 0 "register_operand" "=v") 1009 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 1010 (match_operand:V16QI 2 "register_operand" "v")] 104))] 1011 "TARGET_ALTIVEC" 1012 "vrlb %0,%1,%2" 1013 [(set_attr "type" "vecsimple")]) 1014 1015(define_insn "altivec_vrlh" 1016 [(set (match_operand:V8HI 0 "register_operand" "=v") 1017 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 1018 (match_operand:V8HI 2 "register_operand" "v")] 105))] 1019 "TARGET_ALTIVEC" 1020 "vrlh %0,%1,%2" 1021 [(set_attr "type" "vecsimple")]) 1022 1023(define_insn "altivec_vrlw" 1024 [(set (match_operand:V4SI 0 "register_operand" "=v") 1025 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1026 (match_operand:V4SI 2 "register_operand" "v")] 106))] 1027 "TARGET_ALTIVEC" 1028 "vrlw %0,%1,%2" 1029 [(set_attr "type" "vecsimple")]) 1030 1031(define_insn "altivec_vslb" 1032 [(set (match_operand:V16QI 0 "register_operand" "=v") 1033 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 1034 (match_operand:V16QI 2 "register_operand" "v")] 107))] 1035 "TARGET_ALTIVEC" 1036 "vslb %0,%1,%2" 1037 [(set_attr "type" "vecsimple")]) 1038 1039(define_insn "altivec_vslh" 1040 [(set (match_operand:V8HI 0 "register_operand" "=v") 1041 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 1042 (match_operand:V8HI 2 "register_operand" "v")] 108))] 1043 "TARGET_ALTIVEC" 1044 "vslh %0,%1,%2" 1045 [(set_attr "type" "vecsimple")]) 1046 1047(define_insn "altivec_vslw" 1048 [(set (match_operand:V4SI 0 "register_operand" "=v") 1049 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1050 (match_operand:V4SI 2 "register_operand" "v")] 109))] 1051 "TARGET_ALTIVEC" 1052 "vslw %0,%1,%2" 1053 [(set_attr "type" "vecsimple")]) 1054 1055(define_insn "altivec_vslw_v4sf" 1056 [(set (match_operand:V4SF 0 "register_operand" "=v") 1057 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") 1058 (match_operand:V4SF 2 "register_operand" "v")] 109))] 1059 "TARGET_ALTIVEC" 1060 "vslw %0,%1,%2" 1061 [(set_attr "type" "vecsimple")]) 1062 1063(define_insn "altivec_vsl" 1064 [(set (match_operand:V4SI 0 "register_operand" "=v") 1065 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1066 (match_operand:V4SI 2 "register_operand" "v")] 110))] 1067 "TARGET_ALTIVEC" 1068 "vsl %0,%1,%2" 1069 [(set_attr "type" "vecperm")]) 1070 1071(define_insn "altivec_vslo" 1072 [(set (match_operand:V4SI 0 "register_operand" "=v") 1073 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1074 (match_operand:V4SI 2 "register_operand" "v")] 111))] 1075 "TARGET_ALTIVEC" 1076 "vslo %0,%1,%2" 1077 [(set_attr "type" "vecperm")]) 1078 1079(define_insn "altivec_vsrb" 1080 [(set (match_operand:V16QI 0 "register_operand" "=v") 1081 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 1082 (match_operand:V16QI 2 "register_operand" "v")] 112))] 1083 "TARGET_ALTIVEC" 1084 "vsrb %0,%1,%2" 1085 [(set_attr "type" "vecsimple")]) 1086 1087(define_insn "altivec_vsrh" 1088 [(set (match_operand:V8HI 0 "register_operand" "=v") 1089 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 1090 (match_operand:V8HI 2 "register_operand" "v")] 113))] 1091 "TARGET_ALTIVEC" 1092 "vsrh %0,%1,%2" 1093 [(set_attr "type" "vecsimple")]) 1094 1095(define_insn "altivec_vsrw" 1096 [(set (match_operand:V4SI 0 "register_operand" "=v") 1097 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1098 (match_operand:V4SI 2 "register_operand" "v")] 114))] 1099 "TARGET_ALTIVEC" 1100 "vsrw %0,%1,%2" 1101 [(set_attr "type" "vecsimple")]) 1102 1103(define_insn "altivec_vsrab" 1104 [(set (match_operand:V16QI 0 "register_operand" "=v") 1105 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 1106 (match_operand:V16QI 2 "register_operand" "v")] 115))] 1107 "TARGET_ALTIVEC" 1108 "vsrab %0,%1,%2" 1109 [(set_attr "type" "vecsimple")]) 1110 1111(define_insn "altivec_vsrah" 1112 [(set (match_operand:V8HI 0 "register_operand" "=v") 1113 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 1114 (match_operand:V8HI 2 "register_operand" "v")] 116))] 1115 "TARGET_ALTIVEC" 1116 "vsrah %0,%1,%2" 1117 [(set_attr "type" "vecsimple")]) 1118 1119(define_insn "altivec_vsraw" 1120 [(set (match_operand:V4SI 0 "register_operand" "=v") 1121 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1122 (match_operand:V4SI 2 "register_operand" "v")] 117))] 1123 "TARGET_ALTIVEC" 1124 "vsraw %0,%1,%2" 1125 [(set_attr "type" "vecsimple")]) 1126 1127(define_insn "altivec_vsr" 1128 [(set (match_operand:V4SI 0 "register_operand" "=v") 1129 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1130 (match_operand:V4SI 2 "register_operand" "v")] 118))] 1131 "TARGET_ALTIVEC" 1132 "vsr %0,%1,%2" 1133 [(set_attr "type" "vecperm")]) 1134 1135(define_insn "altivec_vsro" 1136 [(set (match_operand:V4SI 0 "register_operand" "=v") 1137 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1138 (match_operand:V4SI 2 "register_operand" "v")] 119))] 1139 "TARGET_ALTIVEC" 1140 "vsro %0,%1,%2" 1141 [(set_attr "type" "vecperm")]) 1142 1143(define_insn "subv16qi3" 1144 [(set (match_operand:V16QI 0 "register_operand" "=v") 1145 (minus:V16QI (match_operand:V16QI 1 "register_operand" "v") 1146 (match_operand:V16QI 2 "register_operand" "v")))] 1147 "TARGET_ALTIVEC" 1148 "vsububm %0,%1,%2" 1149 [(set_attr "type" "vecsimple")]) 1150 1151(define_insn "subv8hi3" 1152 [(set (match_operand:V8HI 0 "register_operand" "=v") 1153 (minus:V8HI (match_operand:V8HI 1 "register_operand" "v") 1154 (match_operand:V8HI 2 "register_operand" "v")))] 1155 "TARGET_ALTIVEC" 1156 "vsubuhm %0,%1,%2" 1157 [(set_attr "type" "vecsimple")]) 1158 1159(define_insn "subv4si3" 1160 [(set (match_operand:V4SI 0 "register_operand" "=v") 1161 (minus:V4SI (match_operand:V4SI 1 "register_operand" "v") 1162 (match_operand:V4SI 2 "register_operand" "v")))] 1163 "TARGET_ALTIVEC" 1164 "vsubuwm %0,%1,%2" 1165 [(set_attr "type" "vecsimple")]) 1166 1167(define_insn "subv4sf3" 1168 [(set (match_operand:V4SF 0 "register_operand" "=v") 1169 (minus:V4SF (match_operand:V4SF 1 "register_operand" "v") 1170 (match_operand:V4SF 2 "register_operand" "v")))] 1171 "TARGET_ALTIVEC" 1172 "vsubfp %0,%1,%2" 1173 [(set_attr "type" "vecfloat")]) 1174 1175(define_insn "altivec_vsubcuw" 1176 [(set (match_operand:V4SI 0 "register_operand" "=v") 1177 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1178 (match_operand:V4SI 2 "register_operand" "v")] 124))] 1179 "TARGET_ALTIVEC" 1180 "vsubcuw %0,%1,%2" 1181 [(set_attr "type" "vecsimple")]) 1182 1183(define_insn "altivec_vsububs" 1184 [(set (match_operand:V16QI 0 "register_operand" "=v") 1185 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 1186 (match_operand:V16QI 2 "register_operand" "v")] 125)) 1187 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1188 "TARGET_ALTIVEC" 1189 "vsububs %0,%1,%2" 1190 [(set_attr "type" "vecsimple")]) 1191 1192(define_insn "altivec_vsubsbs" 1193 [(set (match_operand:V16QI 0 "register_operand" "=v") 1194 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 1195 (match_operand:V16QI 2 "register_operand" "v")] 126)) 1196 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1197 "TARGET_ALTIVEC" 1198 "vsubsbs %0,%1,%2" 1199 [(set_attr "type" "vecsimple")]) 1200 1201(define_insn "altivec_vsubuhs" 1202 [(set (match_operand:V8HI 0 "register_operand" "=v") 1203 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 1204 (match_operand:V8HI 2 "register_operand" "v")] 127)) 1205 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1206 "TARGET_ALTIVEC" 1207 "vsubuhs %0,%1,%2" 1208 [(set_attr "type" "vecsimple")]) 1209 1210(define_insn "altivec_vsubshs" 1211 [(set (match_operand:V8HI 0 "register_operand" "=v") 1212 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 1213 (match_operand:V8HI 2 "register_operand" "v")] 128)) 1214 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1215 "TARGET_ALTIVEC" 1216 "vsubshs %0,%1,%2" 1217 [(set_attr "type" "vecsimple")]) 1218 1219(define_insn "altivec_vsubuws" 1220 [(set (match_operand:V4SI 0 "register_operand" "=v") 1221 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1222 (match_operand:V4SI 2 "register_operand" "v")] 129)) 1223 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1224 "TARGET_ALTIVEC" 1225 "vsubuws %0,%1,%2" 1226 [(set_attr "type" "vecsimple")]) 1227 1228(define_insn "altivec_vsubsws" 1229 [(set (match_operand:V4SI 0 "register_operand" "=v") 1230 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1231 (match_operand:V4SI 2 "register_operand" "v")] 130)) 1232 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1233 "TARGET_ALTIVEC" 1234 "vsubsws %0,%1,%2" 1235 [(set_attr "type" "vecsimple")]) 1236 1237(define_insn "altivec_vsum4ubs" 1238 [(set (match_operand:V4SI 0 "register_operand" "=v") 1239 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") 1240 (match_operand:V4SI 2 "register_operand" "v")] 131)) 1241 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1242 "TARGET_ALTIVEC" 1243 "vsum4ubs %0,%1,%2" 1244 [(set_attr "type" "veccomplex")]) 1245 1246(define_insn "altivec_vsum4sbs" 1247 [(set (match_operand:V4SI 0 "register_operand" "=v") 1248 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") 1249 (match_operand:V4SI 2 "register_operand" "v")] 132)) 1250 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1251 "TARGET_ALTIVEC" 1252 "vsum4sbs %0,%1,%2" 1253 [(set_attr "type" "veccomplex")]) 1254 1255(define_insn "altivec_vsum4shs" 1256 [(set (match_operand:V4SI 0 "register_operand" "=v") 1257 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 1258 (match_operand:V4SI 2 "register_operand" "v")] 133)) 1259 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1260 "TARGET_ALTIVEC" 1261 "vsum4shs %0,%1,%2" 1262 [(set_attr "type" "veccomplex")]) 1263 1264(define_insn "altivec_vsum2sws" 1265 [(set (match_operand:V4SI 0 "register_operand" "=v") 1266 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1267 (match_operand:V4SI 2 "register_operand" "v")] 134)) 1268 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1269 "TARGET_ALTIVEC" 1270 "vsum2sws %0,%1,%2" 1271 [(set_attr "type" "veccomplex")]) 1272 1273(define_insn "altivec_vsumsws" 1274 [(set (match_operand:V4SI 0 "register_operand" "=v") 1275 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1276 (match_operand:V4SI 2 "register_operand" "v")] 135)) 1277 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1278 "TARGET_ALTIVEC" 1279 "vsumsws %0,%1,%2" 1280 [(set_attr "type" "veccomplex")]) 1281 1282(define_insn "xorv4si3" 1283 [(set (match_operand:V4SI 0 "register_operand" "=v") 1284 (xor:V4SI (match_operand:V4SI 1 "register_operand" "v") 1285 (match_operand:V4SI 2 "register_operand" "v")))] 1286 "TARGET_ALTIVEC" 1287 "vxor %0,%1,%2" 1288 [(set_attr "type" "vecsimple")]) 1289 1290(define_insn "altivec_vspltb" 1291 [(set (match_operand:V16QI 0 "register_operand" "=v") 1292 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 1293 (match_operand:QI 2 "immediate_operand" "i")] 136))] 1294 "TARGET_ALTIVEC" 1295 "vspltb %0,%1,%2" 1296 [(set_attr "type" "vecperm")]) 1297 1298(define_insn "altivec_vsplth" 1299 [(set (match_operand:V8HI 0 "register_operand" "=v") 1300 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 1301 (match_operand:QI 2 "immediate_operand" "i")] 137))] 1302 "TARGET_ALTIVEC" 1303 "vsplth %0,%1,%2" 1304 [(set_attr "type" "vecperm")]) 1305 1306(define_insn "altivec_vspltw" 1307 [(set (match_operand:V4SI 0 "register_operand" "=v") 1308 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1309 (match_operand:QI 2 "immediate_operand" "i")] 138))] 1310 "TARGET_ALTIVEC" 1311 "vspltw %0,%1,%2" 1312 [(set_attr "type" "vecperm")]) 1313 1314(define_insn "altivec_vspltisb" 1315 [(set (match_operand:V16QI 0 "register_operand" "=v") 1316 (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")] 139))] 1317 "TARGET_ALTIVEC" 1318 "vspltisb %0, %1" 1319 [(set_attr "type" "vecsimple")]) 1320 1321 1322(define_insn "altivec_vspltish" 1323 [(set (match_operand:V8HI 0 "register_operand" "=v") 1324 (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")] 140))] 1325 "TARGET_ALTIVEC" 1326 "vspltish %0, %1" 1327 [(set_attr "type" "vecsimple")]) 1328 1329(define_insn "altivec_vspltisw" 1330 [(set (match_operand:V4SI 0 "register_operand" "=v") 1331 (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")] 141))] 1332 "TARGET_ALTIVEC" 1333 "vspltisw %0, %1" 1334 [(set_attr "type" "vecsimple")]) 1335 1336(define_insn "altivec_vspltisw_v4sf" 1337 [(set (match_operand:V4SF 0 "register_operand" "=v") 1338 (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))] 1339 "TARGET_ALTIVEC" 1340 "vspltisw %0, %1" 1341 [(set_attr "type" "vecsimple")]) 1342 1343(define_insn "ftruncv4sf2" 1344 [(set (match_operand:V4SF 0 "register_operand" "=v") 1345 (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))] 1346 "TARGET_ALTIVEC" 1347 "vrfiz %0, %1" 1348 [(set_attr "type" "vecfloat")]) 1349 1350(define_insn "altivec_vperm_4si" 1351 [(set (match_operand:V4SI 0 "register_operand" "=v") 1352 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1353 (match_operand:V4SI 2 "register_operand" "v") 1354 (match_operand:V16QI 3 "register_operand" "v")] 144))] 1355 "TARGET_ALTIVEC" 1356 "vperm %0,%1,%2,%3" 1357 [(set_attr "type" "vecperm")]) 1358 1359(define_insn "altivec_vperm_4sf" 1360 [(set (match_operand:V4SF 0 "register_operand" "=v") 1361 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") 1362 (match_operand:V4SF 2 "register_operand" "v") 1363 (match_operand:V16QI 3 "register_operand" "v")] 145))] 1364 "TARGET_ALTIVEC" 1365 "vperm %0,%1,%2,%3" 1366 [(set_attr "type" "vecperm")]) 1367 1368(define_insn "altivec_vperm_8hi" 1369 [(set (match_operand:V8HI 0 "register_operand" "=v") 1370 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 1371 (match_operand:V8HI 2 "register_operand" "v") 1372 (match_operand:V16QI 3 "register_operand" "v")] 146))] 1373 "TARGET_ALTIVEC" 1374 "vperm %0,%1,%2,%3" 1375 [(set_attr "type" "vecperm")]) 1376 1377(define_insn "altivec_vperm_16qi" 1378 [(set (match_operand:V16QI 0 "register_operand" "=v") 1379 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 1380 (match_operand:V16QI 2 "register_operand" "v") 1381 (match_operand:V16QI 3 "register_operand" "v")] 147))] 1382 "TARGET_ALTIVEC" 1383 "vperm %0,%1,%2,%3" 1384 [(set_attr "type" "vecperm")]) 1385 1386(define_insn "altivec_vrfip" 1387 [(set (match_operand:V4SF 0 "register_operand" "=v") 1388 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))] 1389 "TARGET_ALTIVEC" 1390 "vrfip %0, %1" 1391 [(set_attr "type" "vecfloat")]) 1392 1393(define_insn "altivec_vrfin" 1394 [(set (match_operand:V4SF 0 "register_operand" "=v") 1395 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))] 1396 "TARGET_ALTIVEC" 1397 "vrfin %0, %1" 1398 [(set_attr "type" "vecfloat")]) 1399 1400(define_insn "altivec_vrfim" 1401 [(set (match_operand:V4SF 0 "register_operand" "=v") 1402 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))] 1403 "TARGET_ALTIVEC" 1404 "vrfim %0, %1" 1405 [(set_attr "type" "vecfloat")]) 1406 1407(define_insn "altivec_vcfux" 1408 [(set (match_operand:V4SF 0 "register_operand" "=v") 1409 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") 1410 (match_operand:QI 2 "immediate_operand" "i")] 151))] 1411 "TARGET_ALTIVEC" 1412 "vcfux %0, %1, %2" 1413 [(set_attr "type" "vecfloat")]) 1414 1415(define_insn "altivec_vcfsx" 1416 [(set (match_operand:V4SF 0 "register_operand" "=v") 1417 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") 1418 (match_operand:QI 2 "immediate_operand" "i")] 152))] 1419 "TARGET_ALTIVEC" 1420 "vcfsx %0, %1, %2" 1421 [(set_attr "type" "vecfloat")]) 1422 1423(define_insn "altivec_vctuxs" 1424 [(set (match_operand:V4SI 0 "register_operand" "=v") 1425 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 1426 (match_operand:QI 2 "immediate_operand" "i")] 153)) 1427 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1428 "TARGET_ALTIVEC" 1429 "vctuxs %0, %1, %2" 1430 [(set_attr "type" "vecfloat")]) 1431 1432(define_insn "altivec_vctsxs" 1433 [(set (match_operand:V4SI 0 "register_operand" "=v") 1434 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 1435 (match_operand:QI 2 "immediate_operand" "i")] 154)) 1436 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] 1437 "TARGET_ALTIVEC" 1438 "vctsxs %0, %1, %2" 1439 [(set_attr "type" "vecfloat")]) 1440 1441(define_insn "altivec_vlogefp" 1442 [(set (match_operand:V4SF 0 "register_operand" "=v") 1443 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))] 1444 "TARGET_ALTIVEC" 1445 "vlogefp %0, %1" 1446 [(set_attr "type" "vecfloat")]) 1447 1448(define_insn "altivec_vexptefp" 1449 [(set (match_operand:V4SF 0 "register_operand" "=v") 1450 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))] 1451 "TARGET_ALTIVEC" 1452 "vexptefp %0, %1" 1453 [(set_attr "type" "vecfloat")]) 1454 1455(define_insn "altivec_vrsqrtefp" 1456 [(set (match_operand:V4SF 0 "register_operand" "=v") 1457 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))] 1458 "TARGET_ALTIVEC" 1459 "vrsqrtefp %0, %1" 1460 [(set_attr "type" "vecfloat")]) 1461 1462(define_insn "altivec_vrefp" 1463 [(set (match_operand:V4SF 0 "register_operand" "=v") 1464 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))] 1465 "TARGET_ALTIVEC" 1466 "vrefp %0, %1" 1467 [(set_attr "type" "vecfloat")]) 1468 1469(define_insn "altivec_vsel_4si" 1470 [(set (match_operand:V4SI 0 "register_operand" "=v") 1471 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1472 (match_operand:V4SI 2 "register_operand" "v") 1473 (match_operand:V4SI 3 "register_operand" "v")] 159))] 1474 "TARGET_ALTIVEC" 1475 "vsel %0,%1,%2,%3" 1476 [(set_attr "type" "vecperm")]) 1477 1478(define_insn "altivec_vsel_4sf" 1479 [(set (match_operand:V4SF 0 "register_operand" "=v") 1480 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") 1481 (match_operand:V4SF 2 "register_operand" "v") 1482 (match_operand:V4SI 3 "register_operand" "v")] 160))] 1483 "TARGET_ALTIVEC" 1484 "vsel %0,%1,%2,%3" 1485 [(set_attr "type" "vecperm")]) 1486 1487(define_insn "altivec_vsel_8hi" 1488 [(set (match_operand:V8HI 0 "register_operand" "=v") 1489 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 1490 (match_operand:V8HI 2 "register_operand" "v") 1491 (match_operand:V8HI 3 "register_operand" "v")] 161))] 1492 "TARGET_ALTIVEC" 1493 "vsel %0,%1,%2,%3" 1494 [(set_attr "type" "vecperm")]) 1495 1496(define_insn "altivec_vsel_16qi" 1497 [(set (match_operand:V16QI 0 "register_operand" "=v") 1498 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 1499 (match_operand:V16QI 2 "register_operand" "v") 1500 (match_operand:V16QI 3 "register_operand" "v")] 162))] 1501 "TARGET_ALTIVEC" 1502 "vsel %0,%1,%2,%3" 1503 [(set_attr "type" "vecperm")]) 1504 1505(define_insn "altivec_vsldoi_4si" 1506 [(set (match_operand:V4SI 0 "register_operand" "=v") 1507 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 1508 (match_operand:V4SI 2 "register_operand" "v") 1509 (match_operand:QI 3 "immediate_operand" "i")] 163))] 1510 "TARGET_ALTIVEC" 1511 "vsldoi %0, %1, %2, %3" 1512 [(set_attr "type" "vecperm")]) 1513 1514(define_insn "altivec_vsldoi_4sf" 1515 [(set (match_operand:V4SF 0 "register_operand" "=v") 1516 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") 1517 (match_operand:V4SF 2 "register_operand" "v") 1518 (match_operand:QI 3 "immediate_operand" "i")] 164))] 1519 "TARGET_ALTIVEC" 1520 "vsldoi %0, %1, %2, %3" 1521 [(set_attr "type" "vecperm")]) 1522 1523(define_insn "altivec_vsldoi_8hi" 1524 [(set (match_operand:V8HI 0 "register_operand" "=v") 1525 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 1526 (match_operand:V8HI 2 "register_operand" "v") 1527 (match_operand:QI 3 "immediate_operand" "i")] 165))] 1528 "TARGET_ALTIVEC" 1529 "vsldoi %0, %1, %2, %3" 1530 [(set_attr "type" "vecperm")]) 1531 1532(define_insn "altivec_vsldoi_16qi" 1533 [(set (match_operand:V16QI 0 "register_operand" "=v") 1534 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 1535 (match_operand:V16QI 2 "register_operand" "v") 1536 (match_operand:QI 3 "immediate_operand" "i")] 166))] 1537 "TARGET_ALTIVEC" 1538 "vsldoi %0, %1, %2, %3" 1539 [(set_attr "type" "vecperm")]) 1540 1541(define_insn "altivec_vupkhsb" 1542 [(set (match_operand:V8HI 0 "register_operand" "=v") 1543 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))] 1544 "TARGET_ALTIVEC" 1545 "vupkhsb %0, %1" 1546 [(set_attr "type" "vecperm")]) 1547 1548(define_insn "altivec_vupkhpx" 1549 [(set (match_operand:V4SI 0 "register_operand" "=v") 1550 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))] 1551 "TARGET_ALTIVEC" 1552 "vupkhpx %0, %1" 1553 [(set_attr "type" "vecperm")]) 1554 1555(define_insn "altivec_vupkhsh" 1556 [(set (match_operand:V4SI 0 "register_operand" "=v") 1557 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))] 1558 "TARGET_ALTIVEC" 1559 "vupkhsh %0, %1" 1560 [(set_attr "type" "vecperm")]) 1561 1562(define_insn "altivec_vupklsb" 1563 [(set (match_operand:V8HI 0 "register_operand" "=v") 1564 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))] 1565 "TARGET_ALTIVEC" 1566 "vupklsb %0, %1" 1567 [(set_attr "type" "vecperm")]) 1568 1569(define_insn "altivec_vupklpx" 1570 [(set (match_operand:V4SI 0 "register_operand" "=v") 1571 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))] 1572 "TARGET_ALTIVEC" 1573 "vupklpx %0, %1" 1574 [(set_attr "type" "vecperm")]) 1575 1576(define_insn "altivec_vupklsh" 1577 [(set (match_operand:V4SI 0 "register_operand" "=v") 1578 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))] 1579 "TARGET_ALTIVEC" 1580 "vupklsh %0, %1" 1581 [(set_attr "type" "vecperm")]) 1582 1583;; AltiVec predicates. 1584 1585(define_expand "cr6_test_for_zero" 1586 [(set (match_operand:SI 0 "register_operand" "=r") 1587 (eq:SI (reg:CC 74) 1588 (const_int 0)))] 1589 "TARGET_ALTIVEC" 1590 "") 1591 1592(define_expand "cr6_test_for_zero_reverse" 1593 [(set (match_operand:SI 0 "register_operand" "=r") 1594 (eq:SI (reg:CC 74) 1595 (const_int 0))) 1596 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] 1597 "TARGET_ALTIVEC" 1598 "") 1599 1600(define_expand "cr6_test_for_lt" 1601 [(set (match_operand:SI 0 "register_operand" "=r") 1602 (lt:SI (reg:CC 74) 1603 (const_int 0)))] 1604 "TARGET_ALTIVEC" 1605 "") 1606 1607(define_expand "cr6_test_for_lt_reverse" 1608 [(set (match_operand:SI 0 "register_operand" "=r") 1609 (lt:SI (reg:CC 74) 1610 (const_int 0))) 1611 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] 1612 "TARGET_ALTIVEC" 1613 "") 1614 1615;; We can get away with generating the opcode on the fly (%3 below) 1616;; because all the predicates have the same scheduling parameters. 1617 1618(define_insn "altivec_predicate_v4si" 1619 [(set (reg:CC 74) 1620 (unspec:CC [(match_operand:V4SI 1 "register_operand" "v") 1621 (match_operand:V4SI 2 "register_operand" "v") 1622 (match_operand 3 "any_operand" "")] 173)) 1623 (clobber (match_scratch:V4SI 0 "=v"))] 1624 "TARGET_ALTIVEC" 1625 "%3 %0,%1,%2" 1626[(set_attr "type" "veccmp")]) 1627 1628(define_insn "altivec_predicate_v4sf" 1629 [(set (reg:CC 74) 1630 (unspec:CC [(match_operand:V4SF 1 "register_operand" "v") 1631 (match_operand:V4SF 2 "register_operand" "v") 1632 (match_operand 3 "any_operand" "")] 174)) 1633 (clobber (match_scratch:V4SF 0 "=v"))] 1634 "TARGET_ALTIVEC" 1635 "%3 %0,%1,%2" 1636[(set_attr "type" "veccmp")]) 1637 1638(define_insn "altivec_predicate_v8hi" 1639 [(set (reg:CC 74) 1640 (unspec:CC [(match_operand:V8HI 1 "register_operand" "v") 1641 (match_operand:V8HI 2 "register_operand" "v") 1642 (match_operand 3 "any_operand" "")] 175)) 1643 (clobber (match_scratch:V8HI 0 "=v"))] 1644 "TARGET_ALTIVEC" 1645 "%3 %0,%1,%2" 1646[(set_attr "type" "veccmp")]) 1647 1648(define_insn "altivec_predicate_v16qi" 1649 [(set (reg:CC 74) 1650 (unspec:CC [(match_operand:V16QI 1 "register_operand" "v") 1651 (match_operand:V16QI 2 "register_operand" "v") 1652 (match_operand 3 "any_operand" "")] 175)) 1653 (clobber (match_scratch:V16QI 0 "=v"))] 1654 "TARGET_ALTIVEC" 1655 "%3 %0,%1,%2" 1656[(set_attr "type" "veccmp")]) 1657 1658(define_insn "altivec_mtvscr" 1659 [(set (reg:SI 110) 1660 (unspec_volatile:SI 1661 [(match_operand:V4SI 0 "register_operand" "v")] 186))] 1662 "TARGET_ALTIVEC" 1663 "mtvscr %0" 1664 [(set_attr "type" "vecsimple")]) 1665 1666(define_insn "altivec_mfvscr" 1667 [(set (match_operand:V8HI 0 "register_operand" "=v") 1668 (unspec_volatile:V8HI [(reg:SI 110)] 187))] 1669 "TARGET_ALTIVEC" 1670 "mfvscr %0" 1671 [(set_attr "type" "vecsimple")]) 1672 1673(define_insn "altivec_dssall" 1674 [(unspec [(const_int 0)] 188)] 1675 "TARGET_ALTIVEC" 1676 "dssall" 1677 [(set_attr "type" "vecsimple")]) 1678 1679(define_insn "altivec_dss" 1680 [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)] 1681 "TARGET_ALTIVEC" 1682 "dss %0" 1683 [(set_attr "type" "vecsimple")]) 1684 1685(define_insn "altivec_dst" 1686 [(unspec [(match_operand:SI 0 "register_operand" "b") 1687 (match_operand:SI 1 "register_operand" "r") 1688 (match_operand:QI 2 "immediate_operand" "i")] 190)] 1689 "TARGET_ALTIVEC" 1690 "dst %0,%1,%2" 1691 [(set_attr "type" "vecsimple")]) 1692 1693(define_insn "altivec_dstt" 1694 [(unspec [(match_operand:SI 0 "register_operand" "b") 1695 (match_operand:SI 1 "register_operand" "r") 1696 (match_operand:QI 2 "immediate_operand" "i")] 191)] 1697 "TARGET_ALTIVEC" 1698 "dstt %0,%1,%2" 1699 [(set_attr "type" "vecsimple")]) 1700 1701(define_insn "altivec_dstst" 1702 [(unspec [(match_operand:SI 0 "register_operand" "b") 1703 (match_operand:SI 1 "register_operand" "r") 1704 (match_operand:QI 2 "immediate_operand" "i")] 192)] 1705 "TARGET_ALTIVEC" 1706 "dstst %0,%1,%2" 1707 [(set_attr "type" "vecsimple")]) 1708 1709(define_insn "altivec_dststt" 1710 [(unspec [(match_operand:SI 0 "register_operand" "b") 1711 (match_operand:SI 1 "register_operand" "r") 1712 (match_operand:QI 2 "immediate_operand" "i")] 193)] 1713 "TARGET_ALTIVEC" 1714 "dststt %0,%1,%2" 1715 [(set_attr "type" "vecsimple")]) 1716 1717(define_insn "altivec_lvsl" 1718 [(set (match_operand:V16QI 0 "register_operand" "=v") 1719 (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") 1720 (match_operand:SI 2 "register_operand" "r")] 194))] 1721 "TARGET_ALTIVEC" 1722 "lvsl %0,%1,%2" 1723 [(set_attr "type" "vecload")]) 1724 1725(define_insn "altivec_lvsr" 1726 [(set (match_operand:V16QI 0 "register_operand" "=v") 1727 (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") 1728 (match_operand:SI 2 "register_operand" "r")] 195))] 1729 "TARGET_ALTIVEC" 1730 "lvsr %0,%1,%2" 1731 [(set_attr "type" "vecload")]) 1732 1733;; Parallel some of the LVE* and STV*'s with unspecs because some have 1734;; identical rtl but different instructions-- and gcc gets confused. 1735 1736(define_insn "altivec_lvebx" 1737 [(parallel 1738 [(set (match_operand:V16QI 0 "register_operand" "=v") 1739 (mem:V16QI (plus:SI (match_operand:SI 1 "register_operand" "b") 1740 (match_operand:SI 2 "register_operand" "r")))) 1741 (unspec [(const_int 0)] 196)])] 1742 "TARGET_ALTIVEC" 1743 "lvebx %0,%1,%2" 1744 [(set_attr "type" "vecload")]) 1745 1746(define_insn "altivec_lvehx" 1747 [(parallel 1748 [(set (match_operand:V8HI 0 "register_operand" "=v") 1749 (mem:V8HI 1750 (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") 1751 (match_operand:SI 2 "register_operand" "r")) 1752 (const_int -2)))) 1753 (unspec [(const_int 0)] 197)])] 1754 "TARGET_ALTIVEC" 1755 "lvehx %0,%1,%2" 1756 [(set_attr "type" "vecload")]) 1757 1758(define_insn "altivec_lvewx" 1759 [(parallel 1760 [(set (match_operand:V4SI 0 "register_operand" "=v") 1761 (mem:V4SI 1762 (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") 1763 (match_operand:SI 2 "register_operand" "r")) 1764 (const_int -4)))) 1765 (unspec [(const_int 0)] 198)])] 1766 "TARGET_ALTIVEC" 1767 "lvewx %0,%1,%2" 1768 [(set_attr "type" "vecload")]) 1769 1770(define_insn "altivec_lvxl" 1771 [(parallel 1772 [(set (match_operand:V4SI 0 "register_operand" "=v") 1773 (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") 1774 (match_operand:SI 2 "register_operand" "r")))) 1775 (unspec [(const_int 0)] 213)])] 1776 "TARGET_ALTIVEC" 1777 "lvxl %0,%1,%2" 1778 [(set_attr "type" "vecload")]) 1779 1780(define_insn "altivec_lvx" 1781 [(set (match_operand:V4SI 0 "register_operand" "=v") 1782 (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") 1783 (match_operand:SI 2 "register_operand" "r"))))] 1784 "TARGET_ALTIVEC" 1785 "lvx %0,%1,%2" 1786 [(set_attr "type" "vecload")]) 1787 1788(define_insn "altivec_stvx" 1789 [(parallel 1790 [(set (mem:V4SI 1791 (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") 1792 (match_operand:SI 1 "register_operand" "r")) 1793 (const_int -16))) 1794 (match_operand:V4SI 2 "register_operand" "v")) 1795 (unspec [(const_int 0)] 201)])] 1796 "TARGET_ALTIVEC" 1797 "stvx %2,%0,%1" 1798 [(set_attr "type" "vecstore")]) 1799 1800(define_insn "altivec_stvxl" 1801 [(parallel 1802 [(set (mem:V4SI 1803 (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") 1804 (match_operand:SI 1 "register_operand" "r")) 1805 (const_int -16))) 1806 (match_operand:V4SI 2 "register_operand" "v")) 1807 (unspec [(const_int 0)] 202)])] 1808 "TARGET_ALTIVEC" 1809 "stvxl %2,%0,%1" 1810 [(set_attr "type" "vecstore")]) 1811 1812(define_insn "altivec_stvebx" 1813 [(parallel 1814 [(set (mem:V16QI 1815 (plus:SI (match_operand:SI 0 "register_operand" "b") 1816 (match_operand:SI 1 "register_operand" "r"))) 1817 (match_operand:V16QI 2 "register_operand" "v")) 1818 (unspec [(const_int 0)] 203)])] 1819 "TARGET_ALTIVEC" 1820 "stvebx %2,%0,%1" 1821 [(set_attr "type" "vecstore")]) 1822 1823(define_insn "altivec_stvehx" 1824 [(parallel 1825 [(set (mem:V8HI 1826 (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") 1827 (match_operand:SI 1 "register_operand" "r")) 1828 (const_int -2))) 1829 (match_operand:V8HI 2 "register_operand" "v")) 1830 (unspec [(const_int 0)] 204)])] 1831 "TARGET_ALTIVEC" 1832 "stvehx %2,%0,%1" 1833 [(set_attr "type" "vecstore")]) 1834 1835(define_insn "altivec_stvewx" 1836 [(parallel 1837 [(set (mem:V4SI 1838 (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") 1839 (match_operand:SI 1 "register_operand" "r")) 1840 (const_int -4))) 1841 (match_operand:V4SI 2 "register_operand" "v")) 1842 (unspec [(const_int 0)] 205)])] 1843 "TARGET_ALTIVEC" 1844 "stvewx %2,%0,%1" 1845 [(set_attr "type" "vecstore")]) 1846 1847(define_insn "absv16qi2" 1848 [(set (match_operand:V16QI 0 "register_operand" "=v") 1849 (abs:V16QI (match_operand:V16QI 1 "register_operand" "v"))) 1850 (clobber (match_scratch:V16QI 2 "=&v")) 1851 (clobber (match_scratch:V16QI 3 "=&v"))] 1852 "TARGET_ALTIVEC" 1853 "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3" 1854 [(set_attr "type" "altivec") 1855 (set_attr "length" "12")]) 1856 1857(define_insn "absv8hi2" 1858 [(set (match_operand:V8HI 0 "register_operand" "=v") 1859 (abs:V8HI (match_operand:V8HI 1 "register_operand" "v"))) 1860 (clobber (match_scratch:V8HI 2 "=&v")) 1861 (clobber (match_scratch:V8HI 3 "=&v"))] 1862 "TARGET_ALTIVEC" 1863 "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3" 1864 [(set_attr "type" "altivec") 1865 (set_attr "length" "12")]) 1866 1867(define_insn "absv4si2" 1868 [(set (match_operand:V4SI 0 "register_operand" "=v") 1869 (abs:V4SI (match_operand:V4SI 1 "register_operand" "v"))) 1870 (clobber (match_scratch:V4SI 2 "=&v")) 1871 (clobber (match_scratch:V4SI 3 "=&v"))] 1872 "TARGET_ALTIVEC" 1873 "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3" 1874 [(set_attr "type" "altivec") 1875 (set_attr "length" "12")]) 1876 1877(define_insn "absv4sf2" 1878 [(set (match_operand:V4SF 0 "register_operand" "=v") 1879 (abs:V4SF (match_operand:V4SF 1 "register_operand" "v"))) 1880 (clobber (match_scratch:V4SF 2 "=&v")) 1881 (clobber (match_scratch:V4SF 3 "=&v"))] 1882 "TARGET_ALTIVEC" 1883 "vspltisw %2, -1\;vslw %3,%2,%2\;vandc %0,%1,%3" 1884 [(set_attr "type" "altivec") 1885 (set_attr "length" "12")]) 1886 1887(define_insn "altivec_abss_v16qi" 1888 [(set (match_operand:V16QI 0 "register_operand" "=v") 1889 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210)) 1890 (clobber (match_scratch:V16QI 2 "=&v")) 1891 (clobber (match_scratch:V16QI 3 "=&v"))] 1892 "TARGET_ALTIVEC" 1893 "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3" 1894 [(set_attr "type" "altivec") 1895 (set_attr "length" "12")]) 1896 1897(define_insn "altivec_abss_v8hi" 1898 [(set (match_operand:V8HI 0 "register_operand" "=v") 1899 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211)) 1900 (clobber (match_scratch:V8HI 2 "=&v")) 1901 (clobber (match_scratch:V8HI 3 "=&v"))] 1902 "TARGET_ALTIVEC" 1903 "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3" 1904 [(set_attr "type" "altivec") 1905 (set_attr "length" "12")]) 1906 1907(define_insn "altivec_abss_v4si" 1908 [(set (match_operand:V4SI 0 "register_operand" "=v") 1909 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212)) 1910 (clobber (match_scratch:V4SI 2 "=&v")) 1911 (clobber (match_scratch:V4SI 3 "=&v"))] 1912 "TARGET_ALTIVEC" 1913 "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3" 1914 [(set_attr "type" "altivec") 1915 (set_attr "length" "12")]) 1916