itanium2.md revision 132718
1;; Itanium2 DFA descriptions for insn scheduling and bundling. 2;; Copyright (C) 2002 Free Software Foundation, Inc. 3;; Contributed by Vladimir Makarov <vmakarov@redhat.com>. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 2, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING. If not, write to 19;; the Free Software Foundation, 59 Temple Place - Suite 330, 20;; Boston, MA 02111-1307, USA. */ 21;; 22 23/* This is description of pipeline hazards based on DFA. The 24 following constructions can be used for this: 25 26 o define_cpu_unit string [string]) describes a cpu functional unit 27 (separated by comma). 28 29 1st operand: Names of cpu function units. 30 2nd operand: Name of automaton (see comments for 31 DEFINE_AUTOMATON). 32 33 All define_reservations and define_cpu_units should have unique 34 names which can not be "nothing". 35 36 o (exclusion_set string string) means that each CPU function unit 37 in the first string can not be reserved simultaneously with each 38 unit whose name is in the second string and vise versa. CPU 39 units in the string are separated by commas. For example, it is 40 useful for description CPU with fully pipelined floating point 41 functional unit which can execute simultaneously only single 42 floating point insns or only double floating point insns. 43 44 o (presence_set string string) means that each CPU function unit in 45 the first string can not be reserved unless at least one of 46 pattern of units whose names are in the second string is 47 reserved. This is an asymmetric relation. CPU units or unit 48 patterns in the strings are separated by commas. Pattern is one 49 unit name or unit names separated by white-spaces. 50 51 For example, it is useful for description that slot1 is reserved 52 after slot0 reservation for a VLIW processor. We could describe 53 it by the following construction 54 55 (presence_set "slot1" "slot0") 56 57 Or slot1 is reserved only after slot0 and unit b0 reservation. 58 In this case we could write 59 60 (presence_set "slot1" "slot0 b0") 61 62 All CPU functional units in a set should belong to the same 63 automaton. 64 65 o (final_presence_set string string) is analogous to 66 `presence_set'. The difference between them is when checking is 67 done. When an instruction is issued in given automaton state 68 reflecting all current and planned unit reservations, the 69 automaton state is changed. The first state is a source state, 70 the second one is a result state. Checking for `presence_set' is 71 done on the source state reservation, checking for 72 `final_presence_set' is done on the result reservation. This 73 construction is useful to describe a reservation which is 74 actually two subsequent reservations. For example, if we use 75 76 (presence_set "slot1" "slot0") 77 78 the following insn will be never issued (because slot1 requires 79 slot0 which is absent in the source state). 80 81 (define_reservation "insn_and_nop" "slot0 + slot1") 82 83 but it can be issued if we use analogous `final_presence_set'. 84 85 o (absence_set string string) means that each CPU function unit in 86 the first string can be reserved only if each pattern of units 87 whose names are in the second string is not reserved. This is an 88 asymmetric relation (actually exclusion set is analogous to this 89 one but it is symmetric). CPU units or unit patterns in the 90 string are separated by commas. Pattern is one unit name or unit 91 names separated by white-spaces. 92 93 For example, it is useful for description that slot0 can not be 94 reserved after slot1 or slot2 reservation for a VLIW processor. 95 We could describe it by the following construction 96 97 (absence_set "slot2" "slot0, slot1") 98 99 Or slot2 can not be reserved if slot0 and unit b0 are reserved or 100 slot1 and unit b1 are reserved . In this case we could write 101 102 (absence_set "slot2" "slot0 b0, slot1 b1") 103 104 All CPU functional units in a set should to belong the same 105 automaton. 106 107 o (final_absence_set string string) is analogous to `absence_set' but 108 checking is done on the result (state) reservation. See comments 109 for final_presence_set. 110 111 o (define_bypass number out_insn_names in_insn_names) names bypass with 112 given latency (the first number) from insns given by the first 113 string (see define_insn_reservation) into insns given by the 114 second string. Insn names in the strings are separated by 115 commas. 116 117 o (define_automaton string) describes names of an automaton 118 generated and used for pipeline hazards recognition. The names 119 are separated by comma. Actually it is possibly to generate the 120 single automaton but unfortunately it can be very large. If we 121 use more one automata, the summary size of the automata usually 122 is less than the single one. The automaton name is used in 123 define_cpu_unit. All automata should have unique names. 124 125 o (automata_option string) describes option for generation of 126 automata. Currently there are the following options: 127 128 o "no-minimization" which makes no minimization of automata. 129 This is only worth to do when we are debugging the description 130 and need to look more accurately at reservations of states. 131 132 o "ndfa" which makes automata with nondetermenistic reservation 133 by insns. 134 135 o (define_reservation string string) names reservation (the first 136 string) of cpu functional units (the 2nd string). Sometimes unit 137 reservations for different insns contain common parts. In such 138 case, you describe common part and use one its name (the 1st 139 parameter) in regular expression in define_insn_reservation. All 140 define_reservations, define results and define_cpu_units should 141 have unique names which can not be "nothing". 142 143 o (define_insn_reservation name default_latency condition regexpr) 144 describes reservation of cpu functional units (the 3nd operand) 145 for instruction which is selected by the condition (the 2nd 146 parameter). The first parameter is used for output of debugging 147 information. The reservations are described by a regular 148 expression according the following syntax: 149 150 regexp = regexp "," oneof 151 | oneof 152 153 oneof = oneof "|" allof 154 | allof 155 156 allof = allof "+" repeat 157 | repeat 158 159 repeat = element "*" number 160 | element 161 162 element = cpu_function_name 163 | reservation_name 164 | result_name 165 | "nothing" 166 | "(" regexp ")" 167 168 1. "," is used for describing start of the next cycle in 169 reservation. 170 171 2. "|" is used for describing the reservation described by the 172 first regular expression *or* the reservation described by 173 the second regular expression *or* etc. 174 175 3. "+" is used for describing the reservation described by the 176 first regular expression *and* the reservation described by 177 the second regular expression *and* etc. 178 179 4. "*" is used for convenience and simply means sequence in 180 which the regular expression are repeated NUMBER times with 181 cycle advancing (see ","). 182 183 5. cpu function unit name which means reservation. 184 185 6. reservation name -- see define_reservation. 186 187 7. string "nothing" means no units reservation. 188 189*/ 190 191(define_automaton "two") 192 193;; All possible combinations of bundles/syllables 194(define_cpu_unit "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ 195 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx" "two") 196(define_cpu_unit "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\ 197 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx." "two") 198(define_cpu_unit "2_0mii., 2_0mmi., 2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\ 199 2_0mib., 2_0mmb., 2_0mfb." "two") 200 201(define_cpu_unit "2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\ 202 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx" "two") 203(define_cpu_unit "2_1mi.i, 2_1mm.i, 2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\ 204 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx." "two") 205(define_cpu_unit "2_1mii., 2_1mmi., 2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\ 206 2_1mib., 2_1mmb., 2_1mfb." "two") 207 208;; Slot 1 209(exclusion_set "2_0m.ii" "2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ 210 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") 211(exclusion_set "2_0m.mi" "2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb, 2_0m.ib,\ 212 2_0m.mb, 2_0m.fb, 2_0m.lx") 213(exclusion_set "2_0m.fi" "2_0m.mf, 2_0b.bb, 2_0m.bb, 2_0m.ib, 2_0m.mb,\ 214 2_0m.fb, 2_0m.lx") 215(exclusion_set "2_0m.mf" "2_0b.bb, 2_0m.bb, 2_0m.ib, 2_0m.mb, 2_0m.fb,\ 216 2_0m.lx") 217(exclusion_set "2_0b.bb" "2_0m.bb, 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") 218(exclusion_set "2_0m.bb" "2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") 219(exclusion_set "2_0m.ib" "2_0m.mb, 2_0m.fb, 2_0m.lx") 220(exclusion_set "2_0m.mb" "2_0m.fb, 2_0m.lx") 221(exclusion_set "2_0m.fb" "2_0m.lx") 222 223;; Slot 2 224(exclusion_set "2_0mi.i" "2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\ 225 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") 226(exclusion_set "2_0mm.i" "2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\ 227 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") 228(exclusion_set "2_0mf.i" "2_0mm.f, 2_0bb.b, 2_0mb.b, 2_0mi.b, 2_0mm.b,\ 229 2_0mf.b, 2_0mlx.") 230(exclusion_set "2_0mm.f" "2_0bb.b, 2_0mb.b, 2_0mi.b, 2_0mm.b, 2_0mf.b,\ 231 2_0mlx.") 232(exclusion_set "2_0bb.b" "2_0mb.b, 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") 233(exclusion_set "2_0mb.b" "2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") 234(exclusion_set "2_0mi.b" "2_0mm.b, 2_0mf.b, 2_0mlx.") 235(exclusion_set "2_0mm.b" "2_0mf.b, 2_0mlx.") 236(exclusion_set "2_0mf.b" "2_0mlx.") 237 238;; Slot 3 239(exclusion_set "2_0mii." "2_0mmi., 2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\ 240 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") 241(exclusion_set "2_0mmi." "2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\ 242 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") 243(exclusion_set "2_0mfi." "2_0mmf., 2_0bbb., 2_0mbb., 2_0mib., 2_0mmb.,\ 244 2_0mfb., 2_0mlx.") 245(exclusion_set "2_0mmf." "2_0bbb., 2_0mbb., 2_0mib., 2_0mmb., 2_0mfb.,\ 246 2_0mlx.") 247(exclusion_set "2_0bbb." "2_0mbb., 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") 248(exclusion_set "2_0mbb." "2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") 249(exclusion_set "2_0mib." "2_0mmb., 2_0mfb., 2_0mlx.") 250(exclusion_set "2_0mmb." "2_0mfb., 2_0mlx.") 251(exclusion_set "2_0mfb." "2_0mlx.") 252 253;; Slot 4 254(exclusion_set "2_1m.ii" "2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\ 255 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx") 256(exclusion_set "2_1m.mi" "2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb, 2_1m.ib,\ 257 2_1m.mb, 2_1m.fb, 2_1m.lx") 258(exclusion_set "2_1m.fi" "2_1m.mf, 2_1b.bb, 2_1m.bb, 2_1m.ib, 2_1m.mb,\ 259 2_1m.fb, 2_1m.lx") 260(exclusion_set "2_1m.mf" "2_1b.bb, 2_1m.bb, 2_1m.ib, 2_1m.mb, 2_1m.fb,\ 261 2_1m.lx") 262(exclusion_set "2_1b.bb" "2_1m.bb, 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx") 263(exclusion_set "2_1m.bb" "2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx") 264(exclusion_set "2_1m.ib" "2_1m.mb, 2_1m.fb, 2_1m.lx") 265(exclusion_set "2_1m.mb" "2_1m.fb, 2_1m.lx") 266(exclusion_set "2_1m.fb" "2_1m.lx") 267 268;; Slot 5 269(exclusion_set "2_1mi.i" "2_1mm.i, 2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\ 270 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") 271(exclusion_set "2_1mm.i" "2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\ 272 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") 273(exclusion_set "2_1mf.i" "2_1mm.f, 2_1bb.b, 2_1mb.b, 2_1mi.b, 2_1mm.b,\ 274 2_1mf.b, 2_1mlx.") 275(exclusion_set "2_1mm.f" "2_1bb.b, 2_1mb.b, 2_1mi.b, 2_1mm.b, 2_1mf.b,\ 276 2_1mlx.") 277(exclusion_set "2_1bb.b" "2_1mb.b, 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") 278(exclusion_set "2_1mb.b" "2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") 279(exclusion_set "2_1mi.b" "2_1mm.b, 2_1mf.b, 2_1mlx.") 280(exclusion_set "2_1mm.b" "2_1mf.b, 2_1mlx.") 281(exclusion_set "2_1mf.b" "2_1mlx.") 282 283;; Slot 6 284(exclusion_set "2_1mii." "2_1mmi., 2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\ 285 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") 286(exclusion_set "2_1mmi." "2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\ 287 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") 288(exclusion_set "2_1mfi." "2_1mmf., 2_1bbb., 2_1mbb., 2_1mib., 2_1mmb.,\ 289 2_1mfb., 2_1mlx.") 290(exclusion_set "2_1mmf." "2_1bbb., 2_1mbb., 2_1mib., 2_1mmb., 2_1mfb.,\ 291 2_1mlx.") 292(exclusion_set "2_1bbb." "2_1mbb., 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") 293(exclusion_set "2_1mbb." "2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") 294(exclusion_set "2_1mib." "2_1mmb., 2_1mfb., 2_1mlx.") 295(exclusion_set "2_1mmb." "2_1mfb., 2_1mlx.") 296(exclusion_set "2_1mfb." "2_1mlx.") 297 298(final_presence_set "2_0mi.i" "2_0m.ii") 299(final_presence_set "2_0mii." "2_0mi.i") 300(final_presence_set "2_1mi.i" "2_1m.ii") 301(final_presence_set "2_1mii." "2_1mi.i") 302 303(final_presence_set "2_0mm.i" "2_0m.mi") 304(final_presence_set "2_0mmi." "2_0mm.i") 305(final_presence_set "2_1mm.i" "2_1m.mi") 306(final_presence_set "2_1mmi." "2_1mm.i") 307 308(final_presence_set "2_0mf.i" "2_0m.fi") 309(final_presence_set "2_0mfi." "2_0mf.i") 310(final_presence_set "2_1mf.i" "2_1m.fi") 311(final_presence_set "2_1mfi." "2_1mf.i") 312 313(final_presence_set "2_0mm.f" "2_0m.mf") 314(final_presence_set "2_0mmf." "2_0mm.f") 315(final_presence_set "2_1mm.f" "2_1m.mf") 316(final_presence_set "2_1mmf." "2_1mm.f") 317 318(final_presence_set "2_0bb.b" "2_0b.bb") 319(final_presence_set "2_0bbb." "2_0bb.b") 320(final_presence_set "2_1bb.b" "2_1b.bb") 321(final_presence_set "2_1bbb." "2_1bb.b") 322 323(final_presence_set "2_0mb.b" "2_0m.bb") 324(final_presence_set "2_0mbb." "2_0mb.b") 325(final_presence_set "2_1mb.b" "2_1m.bb") 326(final_presence_set "2_1mbb." "2_1mb.b") 327 328(final_presence_set "2_0mi.b" "2_0m.ib") 329(final_presence_set "2_0mib." "2_0mi.b") 330(final_presence_set "2_1mi.b" "2_1m.ib") 331(final_presence_set "2_1mib." "2_1mi.b") 332 333(final_presence_set "2_0mm.b" "2_0m.mb") 334(final_presence_set "2_0mmb." "2_0mm.b") 335(final_presence_set "2_1mm.b" "2_1m.mb") 336(final_presence_set "2_1mmb." "2_1mm.b") 337 338(final_presence_set "2_0mf.b" "2_0m.fb") 339(final_presence_set "2_0mfb." "2_0mf.b") 340(final_presence_set "2_1mf.b" "2_1m.fb") 341(final_presence_set "2_1mfb." "2_1mf.b") 342 343(final_presence_set "2_0mlx." "2_0m.lx") 344(final_presence_set "2_1mlx." "2_1m.lx") 345 346;; The following reflects the dual issue bundle types table. 347;; We could place all possible combinations here because impossible 348;; combinations would go away by the subsequent constrains. 349(final_presence_set 350 "2_1m.lx" 351 "2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.") 352(final_presence_set "2_1b.bb" "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mlx.") 353(final_presence_set 354 "2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1m.bb,2_1m.ib,2_1m.mb,2_1m.fb" 355 "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.") 356 357;; Ports/units (nb means nop.b insn issued into given port): 358(define_cpu_unit 359 "2_um0, 2_um1, 2_um2, 2_um3, 2_ui0, 2_ui1, 2_uf0, 2_uf1,\ 360 2_ub0, 2_ub1, 2_ub2, 2_unb0, 2_unb1, 2_unb2" "two") 361 362(exclusion_set "2_ub0" "2_unb0") 363(exclusion_set "2_ub1" "2_unb1") 364(exclusion_set "2_ub2" "2_unb2") 365 366;; The following rules are used to decrease number of alternatives. 367;; They are consequences of Itanium2 microarchitecture. They also 368;; describe the following rules mentioned in Itanium2 369;; microarchitecture: rules mentioned in Itanium2 microarchitecture: 370;; o "BBB/MBB: Always splits issue after either of these bundles". 371;; o "MIB BBB: Split issue after the first bundle in this pair". 372(exclusion_set 373 "2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb." 374 "2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1b.bb,2_1m.bb,\ 375 2_1m.ib,2_1m.mb,2_1m.fb,2_1m.lx") 376(exclusion_set "2_0m.ib,2_0mi.b,2_0mib." "2_1b.bb") 377 378;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the 379;;; B-slot contains a nop.b or a brp instruction". 380;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or 381;;; nop.b, otherwise it disperses to B2". 382(final_absence_set 383 "2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\ 384 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx" 385 "2_0mib. 2_ub2, 2_0mfb. 2_ub2, 2_0mmb. 2_ub2") 386 387;; This is necessary to start new processor cycle when we meet stop bit. 388(define_cpu_unit "2_stop" "two") 389(final_absence_set 390 "2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\ 391 2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\ 392 2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\ 393 2_0m.lx,2_0mlx., \ 394 2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\ 395 2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\ 396 2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\ 397 2_1m.lx,2_1mlx." 398 "2_stop") 399 400;; The issue logic can reorder M slot insns between different subtypes 401;; but can not reorder insn within the same subtypes. The following 402;; constraint is enough to describe this. 403(final_presence_set "2_um1" "2_um0") 404(final_presence_set "2_um3" "2_um2") 405 406;; The insn in the 1st I slot of the two bundle issue group will issue 407;; to I0. The second I slot insn will issue to I1. 408(final_presence_set "2_ui1" "2_ui0") 409 410;; For exceptions of I insns: 411(define_cpu_unit "2_only_ui0" "two") 412(final_absence_set "2_only_ui0" "2_ui1") 413 414;; Insns 415 416(define_reservation "2_M0" 417 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ 418 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ 419 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ 420 +(2_um0|2_um1|2_um2|2_um3)") 421 422(define_reservation "2_M1" 423 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ 424 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ 425 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ 426 +(2_um0|2_um1|2_um2|2_um3)") 427 428(define_reservation "2_M" "2_M0|2_M1") 429 430(define_reservation "2_M0_only_um0" 431 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ 432 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ 433 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ 434 +2_um0") 435 436(define_reservation "2_M1_only_um0" 437 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ 438 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ 439 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ 440 +2_um0") 441 442(define_reservation "2_M_only_um0" "2_M0_only_um0|2_M1_only_um0") 443 444(define_reservation "2_M0_only_um2" 445 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ 446 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ 447 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ 448 +2_um2") 449 450(define_reservation "2_M1_only_um2" 451 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ 452 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ 453 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ 454 +2_um2") 455 456(define_reservation "2_M_only_um2" "2_M0_only_um2|2_M1_only_um2") 457 458(define_reservation "2_M0_only_um23" 459 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ 460 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ 461 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ 462 +(2_um2|2_um3)") 463 464(define_reservation "2_M1_only_um23" 465 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ 466 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ 467 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ 468 +(2_um2|2_um3)") 469 470(define_reservation "2_M_only_um23" "2_M0_only_um23|2_M1_only_um23") 471 472(define_reservation "2_M0_only_um01" 473 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ 474 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ 475 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ 476 +(2_um0|2_um1)") 477 478(define_reservation "2_M1_only_um01" 479 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ 480 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ 481 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ 482 +(2_um0|2_um1)") 483 484(define_reservation "2_M_only_um01" "2_M0_only_um01|2_M1_only_um01") 485 486;; I instruction is dispersed to the lowest numbered I unit 487;; not already in use. Remeber about possible splitting. 488(define_reservation "2_I0" 489 "2_0mi.i+2_ui0|2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0\ 490 |2_0mfi.+2_ui0|2_0mi.b+2_ui0|(2_1mi.i|2_1mi.b)+(2_ui0|2_ui1)\ 491 |(2_1mii.|2_1mmi.|2_1mfi.)+(2_ui0|2_ui1)") 492 493(define_reservation "2_I1" 494 "2_0m.ii+(2_um0|2_um1|2_um2|2_um3)+2_0mi.i+2_ui0\ 495 |2_0mm.i+(2_um0|2_um1|2_um2|2_um3)+2_0mmi.+2_ui0\ 496 |2_0mf.i+2_uf0+2_0mfi.+2_ui0\ 497 |2_0m.ib+(2_um0|2_um1|2_um2|2_um3)+2_0mi.b+2_ui0\ 498 |(2_1m.ii+2_1mi.i|2_1m.ib+2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)+(2_ui0|2_ui1)\ 499 |2_1mm.i+(2_um0|2_um1|2_um2|2_um3)+2_1mmi.+(2_ui0|2_ui1)\ 500 |2_1mf.i+2_uf1+2_1mfi.+(2_ui0|2_ui1)") 501 502(define_reservation "2_I" "2_I0|2_I1") 503 504;; "An F slot in the 1st bundle disperses to F0". 505;; "An F slot in the 2st bundle disperses to F1". 506(define_reservation "2_F0" 507 "2_0mf.i+2_uf0|2_0mmf.+2_uf0|2_0mf.b+2_uf0\ 508 |2_1mf.i+2_uf1|2_1mmf.+2_uf1|2_1mf.b+2_uf1") 509 510(define_reservation "2_F1" 511 "(2_0m.fi+2_0mf.i|2_0mm.f+2_0mmf.|2_0m.fb+2_0mf.b)\ 512 +(2_um0|2_um1|2_um2|2_um3)+2_uf0\ 513 |(2_1m.fi+2_1mf.i|2_1mm.f+2_1mmf.|2_1m.fb+2_1mf.b)\ 514 +(2_um0|2_um1|2_um2|2_um3)+2_uf1") 515 516(define_reservation "2_F2" 517 "(2_0m.mf+2_0mm.f+2_0mmf.+2_uf0|2_1m.mf+2_1mm.f+2_1mmf.+2_uf1)\ 518 +(2_um0|2_um1|2_um2|2_um3)+(2_um0|2_um1|2_um2|2_um3)\ 519 |(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0\ 520 |2_0mmf.+(2_um0|2_um1|2_um2|2_um3)\ 521 |2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0)\ 522 +(2_1m.fi+2_1mf.i|2_1m.fb+2_1mf.b)+(2_um0|2_um1|2_um2|2_um3)+2_uf1") 523 524(define_reservation "2_F" "2_F0|2_F1|2_F2") 525 526;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B 527;;; unit. That is, a B slot in 1st position is dispersed to B0. In the 528;;; 2nd position it is dispersed to B2". 529(define_reservation "2_NB" 530 "2_0b.bb+2_unb0|2_0bb.b+2_unb1|2_0bbb.+2_unb2\ 531 |2_0mb.b+2_unb1|2_0mbb.+2_unb2|2_0mib.+2_unb0\ 532 |2_0mmb.+2_unb0|2_0mfb.+2_unb0\ 533 |2_1b.bb+2_unb0|2_1bb.b+2_unb1 534 |2_1bbb.+2_unb2|2_1mb.b+2_unb1|2_1mbb.+2_unb2\ 535 |2_1mib.+2_unb0|2_1mmb.+2_unb0|2_1mfb.+2_unb0") 536 537(define_reservation "2_B0" 538 "2_0b.bb+2_ub0|2_0bb.b+2_ub1|2_0bbb.+2_ub2\ 539 |2_0mb.b+2_ub1|2_0mbb.+2_ub2|2_0mib.+2_ub2\ 540 |2_0mfb.+2_ub2|2_1b.bb+2_ub0|2_1bb.b+2_ub1\ 541 |2_1bbb.+2_ub2|2_1mb.b+2_ub1\ 542 |2_1mib.+2_ub2|2_1mmb.+2_ub2|2_1mfb.+2_ub2") 543 544(define_reservation "2_B1" 545 "2_0m.bb+(2_um0|2_um1|2_um2|2_um3)+2_0mb.b+2_ub1\ 546 |2_0mi.b+2_ui0+2_0mib.+2_ub2\ 547 |2_0mm.b+(2_um0|2_um1|2_um2|2_um3)+2_0mmb.+2_ub2\ 548 |2_0mf.b+2_uf0+2_0mfb.+2_ub2\ 549 |(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0)\ 550 +2_1b.bb+2_ub0\ 551 |2_1m.bb+(2_um0|2_um1|2_um2|2_um3)+2_1mb.b+2_ub1\ 552 |2_1mi.b+(2_ui0|2_ui1)+2_1mib.+2_ub2\ 553 |2_1mm.b+(2_um0|2_um1|2_um2|2_um3)+2_1mmb.+2_ub2\ 554 |2_1mf.b+2_uf1+2_1mfb.+2_ub2") 555 556(define_reservation "2_B" "2_B0|2_B1") 557 558;; MLX bunlde uses ports equivalent to MFI bundles. 559 560;; For the MLI template, the I slot insn is always assigned to port I0 561;; if it is in the first bundle or it is assigned to port I1 if it is in 562;; the second bundle. 563(define_reservation "2_L0" "2_0mlx.+2_ui0+2_uf0|2_1mlx.+2_ui1+2_uf1") 564 565(define_reservation "2_L1" 566 "2_0m.lx+(2_um0|2_um1|2_um2|2_um3)+2_0mlx.+2_ui0+2_uf0\ 567 |2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1") 568 569(define_reservation "2_L2" 570 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ 571 |2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0) 572 +2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1") 573 574(define_reservation "2_L" "2_L0|2_L1|2_L2") 575 576;; Should we describe that A insn in I slot can be issued into M 577;; ports? I think it is not necessary because of multipass 578;; scheduling. For example, the multipass scheduling could use 579;; MMI-MMI instead of MII-MII where the two last I slots contain A 580;; insns (even if the case is complicated by use-def conflicts). 581;; 582;; In any case we could describe it as 583;; (define_cpu_unit "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres" "two") 584;; (final_presence_set "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres" 585;; "2_ui1") 586;; (define_reservation "b_A" 587;; "b_M|b_I\ 588;; |(2_1mi.i|2_1mii.|2_1mmi.|2_1mfi.|2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)\ 589;; +(2_ui1_0pres|2_ui1_1pres|2_ui1_2pres|2_ui1_3pres)") 590 591(define_reservation "2_A" "2_M|2_I") 592 593;; We assume that there is no insn issued on the same cycle as the 594;; unknown insn. 595(define_cpu_unit "2_empty" "two") 596(exclusion_set "2_empty" 597 "2_0m.ii,2_0m.mi,2_0m.fi,2_0m.mf,2_0b.bb,2_0m.bb,2_0m.ib,2_0m.mb,2_0m.fb,\ 598 2_0m.lx") 599 600(define_cpu_unit 601 "2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs" 602 "two") 603(define_cpu_unit 604 "2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs" 605 "two") 606 607(define_cpu_unit "2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont, 2_mb_cont,\ 608 2_b_cont, 2_bb_cont" "two") 609 610;; For stop in the middle of the bundles. 611(define_cpu_unit "2_m_stop, 2_m0_stop, 2_m1_stop, 2_0mmi_cont" "two") 612(define_cpu_unit "2_mi_stop, 2_mi0_stop, 2_mi1_stop, 2_0mii_cont" "two") 613 614(final_presence_set "2_0m_bs" 615 "2_0m.ii, 2_0m.mi, 2_0m.mf, 2_0m.fi, 2_0m.bb,\ 616 2_0m.ib, 2_0m.fb, 2_0m.mb, 2_0m.lx") 617(final_presence_set "2_1m_bs" 618 "2_1m.ii, 2_1m.mi, 2_1m.mf, 2_1m.fi, 2_1m.bb,\ 619 2_1m.ib, 2_1m.fb, 2_1m.mb, 2_1m.lx") 620(final_presence_set "2_0mi_bs" "2_0mi.i, 2_0mi.i") 621(final_presence_set "2_1mi_bs" "2_1mi.i, 2_1mi.i") 622(final_presence_set "2_0mm_bs" "2_0mm.i, 2_0mm.f, 2_0mm.b") 623(final_presence_set "2_1mm_bs" "2_1mm.i, 2_1mm.f, 2_1mm.b") 624(final_presence_set "2_0mf_bs" "2_0mf.i, 2_0mf.b") 625(final_presence_set "2_1mf_bs" "2_1mf.i, 2_1mf.b") 626(final_presence_set "2_0b_bs" "2_0b.bb") 627(final_presence_set "2_1b_bs" "2_1b.bb") 628(final_presence_set "2_0bb_bs" "2_0bb.b") 629(final_presence_set "2_1bb_bs" "2_1bb.b") 630(final_presence_set "2_0mb_bs" "2_0mb.b") 631(final_presence_set "2_1mb_bs" "2_1mb.b") 632 633(exclusion_set "2_0m_bs" 634 "2_0mi.i, 2_0mm.i, 2_0mm.f, 2_0mf.i, 2_0mb.b,\ 635 2_0mi.b, 2_0mf.b, 2_0mm.b, 2_0mlx., 2_m0_stop") 636(exclusion_set "2_1m_bs" 637 "2_1mi.i, 2_1mm.i, 2_1mm.f, 2_1mf.i, 2_1mb.b,\ 638 2_1mi.b, 2_1mf.b, 2_1mm.b, 2_1mlx., 2_m1_stop") 639(exclusion_set "2_0mi_bs" "2_0mii., 2_0mib., 2_mi0_stop") 640(exclusion_set "2_1mi_bs" "2_1mii., 2_1mib., 2_mi1_stop") 641(exclusion_set "2_0mm_bs" "2_0mmi., 2_0mmf., 2_0mmb.") 642(exclusion_set "2_1mm_bs" "2_1mmi., 2_1mmf., 2_1mmb.") 643(exclusion_set "2_0mf_bs" "2_0mfi., 2_0mfb.") 644(exclusion_set "2_1mf_bs" "2_1mfi., 2_1mfb.") 645(exclusion_set "2_0b_bs" "2_0bb.b") 646(exclusion_set "2_1b_bs" "2_1bb.b") 647(exclusion_set "2_0bb_bs" "2_0bbb.") 648(exclusion_set "2_1bb_bs" "2_1bbb.") 649(exclusion_set "2_0mb_bs" "2_0mbb.") 650(exclusion_set "2_1mb_bs" "2_1mbb.") 651 652(exclusion_set 653 "2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs, 654 2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs" 655 "2_stop") 656 657(final_presence_set 658 "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0mb.b,\ 659 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx." 660 "2_m_cont") 661(final_presence_set "2_0mii., 2_0mib." "2_mi_cont") 662(final_presence_set "2_0mmi., 2_0mmf., 2_0mmb." "2_mm_cont") 663(final_presence_set "2_0mfi., 2_0mfb." "2_mf_cont") 664(final_presence_set "2_0bb.b" "2_b_cont") 665(final_presence_set "2_0bbb." "2_bb_cont") 666(final_presence_set "2_0mbb." "2_mb_cont") 667 668(exclusion_set 669 "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ 670 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx" 671 "2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont,\ 672 2_mb_cont, 2_b_cont, 2_bb_cont") 673 674(exclusion_set "2_empty" 675 "2_m_cont,2_mi_cont,2_mm_cont,2_mf_cont,\ 676 2_mb_cont,2_b_cont,2_bb_cont") 677 678;; For m;mi bundle 679(final_presence_set "2_m0_stop" "2_0m.mi") 680(final_presence_set "2_0mm.i" "2_0mmi_cont") 681(exclusion_set "2_0mmi_cont" 682 "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ 683 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") 684(exclusion_set "2_m0_stop" "2_0mm.i") 685(final_presence_set "2_m1_stop" "2_1m.mi") 686(exclusion_set "2_m1_stop" "2_1mm.i") 687(final_presence_set "2_m_stop" "2_m0_stop, 2_m1_stop") 688 689;; For mi;i bundle 690(final_presence_set "2_mi0_stop" "2_0mi.i") 691(final_presence_set "2_0mii." "2_0mii_cont") 692(exclusion_set "2_0mii_cont" 693 "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ 694 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") 695(exclusion_set "2_mi0_stop" "2_0mii.") 696(final_presence_set "2_mi1_stop" "2_1mi.i") 697(exclusion_set "2_mi1_stop" "2_1mii.") 698(final_presence_set "2_mi_stop" "2_mi0_stop, 2_mi1_stop") 699 700(final_absence_set 701 "2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\ 702 2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\ 703 2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\ 704 2_0m.lx,2_0mlx., \ 705 2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\ 706 2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\ 707 2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\ 708 2_1m.lx,2_1mlx." 709 "2_m0_stop,2_m1_stop,2_mi0_stop,2_mi1_stop") 710 711(define_insn_reservation "2_stop_bit" 0 712 (and (and (eq_attr "cpu" "itanium2") 713 (eq_attr "itanium_class" "stop_bit")) 714 (eq (symbol_ref "bundling_p") (const_int 0))) 715 "2_stop|2_m0_stop|2_m1_stop|2_mi0_stop|2_mi1_stop") 716 717(define_insn_reservation "2_br" 0 718 (and (and (eq_attr "cpu" "itanium2") 719 (eq_attr "itanium_class" "br")) 720 (eq (symbol_ref "bundling_p") (const_int 0))) "2_B") 721(define_insn_reservation "2_scall" 0 722 (and (and (eq_attr "cpu" "itanium2") 723 (eq_attr "itanium_class" "scall")) 724 (eq (symbol_ref "bundling_p") (const_int 0))) "2_B") 725(define_insn_reservation "2_fcmp" 2 726 (and (and (eq_attr "cpu" "itanium2") 727 (eq_attr "itanium_class" "fcmp")) 728 (eq (symbol_ref "bundling_p") (const_int 0))) "2_F") 729(define_insn_reservation "2_fcvtfx" 4 730 (and (and (eq_attr "cpu" "itanium2") 731 (eq_attr "itanium_class" "fcvtfx")) 732 (eq (symbol_ref "bundling_p") (const_int 0))) "2_F") 733(define_insn_reservation "2_fld" 6 734 (and (and (eq_attr "cpu" "itanium2") 735 (eq_attr "itanium_class" "fld")) 736 (eq (symbol_ref "bundling_p") (const_int 0))) "2_M") 737(define_insn_reservation "2_fmac" 4 738 (and (and (eq_attr "cpu" "itanium2") 739 (eq_attr "itanium_class" "fmac")) 740 (eq (symbol_ref "bundling_p") (const_int 0))) "2_F") 741(define_insn_reservation "2_fmisc" 4 742 (and (and (eq_attr "cpu" "itanium2") 743 (eq_attr "itanium_class" "fmisc")) 744 (eq (symbol_ref "bundling_p") (const_int 0))) "2_F") 745 746;; There is only one insn `mov = ar.bsp' for frar_i: 747;; Latency time ??? 748(define_insn_reservation "2_frar_i" 13 749 (and (and (eq_attr "cpu" "itanium2") 750 (eq_attr "itanium_class" "frar_i")) 751 (eq (symbol_ref "bundling_p") (const_int 0))) 752 "2_I+2_only_ui0") 753;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m: 754;; Latency time ??? 755(define_insn_reservation "2_frar_m" 6 756 (and (and (eq_attr "cpu" "itanium2") 757 (eq_attr "itanium_class" "frar_m")) 758 (eq (symbol_ref "bundling_p") (const_int 0))) 759 "2_M_only_um2") 760(define_insn_reservation "2_frbr" 2 761 (and (and (eq_attr "cpu" "itanium2") 762 (eq_attr "itanium_class" "frbr")) 763 (eq (symbol_ref "bundling_p") (const_int 0))) 764 "2_I+2_only_ui0") 765(define_insn_reservation "2_frfr" 5 766 (and (and (eq_attr "cpu" "itanium2") 767 (eq_attr "itanium_class" "frfr")) 768 (eq (symbol_ref "bundling_p") (const_int 0))) 769 "2_M_only_um2") 770(define_insn_reservation "2_frpr" 2 771 (and (and (eq_attr "cpu" "itanium2") 772 (eq_attr "itanium_class" "frpr")) 773 (eq (symbol_ref "bundling_p") (const_int 0))) 774 "2_I+2_only_ui0") 775 776(define_insn_reservation "2_ialu" 1 777 (and (and (eq_attr "cpu" "itanium2") 778 (eq_attr "itanium_class" "ialu")) 779 (eq (symbol_ref "bundling_p") (const_int 0))) 780 "2_A") 781(define_insn_reservation "2_icmp" 1 782 (and (and (eq_attr "cpu" "itanium2") 783 (eq_attr "itanium_class" "icmp")) 784 (eq (symbol_ref "bundling_p") (const_int 0))) "2_A") 785(define_insn_reservation "2_ilog" 1 786 (and (and (eq_attr "cpu" "itanium2") 787 (eq_attr "itanium_class" "ilog")) 788 (eq (symbol_ref "bundling_p") (const_int 0))) "2_A") 789;; Latency time ??? 790(define_insn_reservation "2_ishf" 1 791 (and (and (eq_attr "cpu" "itanium2") 792 (eq_attr "itanium_class" "ishf")) 793 (eq (symbol_ref "bundling_p") (const_int 0))) 794 "2_I+2_only_ui0") 795(define_insn_reservation "2_ld" 1 796 (and (and (eq_attr "cpu" "itanium2") 797 (eq_attr "itanium_class" "ld")) 798 (eq (symbol_ref "bundling_p") (const_int 0))) 799 "2_M_only_um01") 800(define_insn_reservation "2_long_i" 1 801 (and (and (eq_attr "cpu" "itanium2") 802 (eq_attr "itanium_class" "long_i")) 803 (eq (symbol_ref "bundling_p") (const_int 0))) "2_L") 804 805(define_insn_reservation "2_mmmul" 2 806 (and (and (eq_attr "cpu" "itanium2") 807 (eq_attr "itanium_class" "mmmul")) 808 (eq (symbol_ref "bundling_p") (const_int 0))) 809 "2_I+2_only_ui0") 810;; Latency time ??? 811(define_insn_reservation "2_mmshf" 2 812 (and (and (eq_attr "cpu" "itanium2") 813 (eq_attr "itanium_class" "mmshf")) 814 (eq (symbol_ref "bundling_p") (const_int 0))) "2_I") 815;; Latency time ??? 816(define_insn_reservation "2_mmshfi" 1 817 (and (and (eq_attr "cpu" "itanium2") 818 (eq_attr "itanium_class" "mmshfi")) 819 (eq (symbol_ref "bundling_p") (const_int 0))) "2_I") 820 821;; Now we have only one insn (flushrs) of such class. We assume that flushrs 822;; is the 1st syllable of the bundle after stop bit. 823(define_insn_reservation "2_rse_m" 0 824 (and (and (eq_attr "cpu" "itanium2") 825 (eq_attr "itanium_class" "rse_m")) 826 (eq (symbol_ref "bundling_p") (const_int 0))) 827 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb\ 828 |2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx)+2_um0") 829(define_insn_reservation "2_sem" 0 830 (and (and (eq_attr "cpu" "itanium2") 831 (eq_attr "itanium_class" "sem")) 832 (eq (symbol_ref "bundling_p") (const_int 0))) 833 "2_M_only_um23") 834 835(define_insn_reservation "2_stf" 1 836 (and (and (eq_attr "cpu" "itanium2") 837 (eq_attr "itanium_class" "stf")) 838 (eq (symbol_ref "bundling_p") (const_int 0))) 839 "2_M_only_um23") 840(define_insn_reservation "2_st" 1 841 (and (and (eq_attr "cpu" "itanium2") 842 (eq_attr "itanium_class" "st")) 843 (eq (symbol_ref "bundling_p") (const_int 0))) 844 "2_M_only_um23") 845(define_insn_reservation "2_syst_m0" 0 846 (and (and (eq_attr "cpu" "itanium2") 847 (eq_attr "itanium_class" "syst_m0")) 848 (eq (symbol_ref "bundling_p") (const_int 0))) 849 "2_M_only_um2") 850(define_insn_reservation "2_syst_m" 0 851 (and (and (eq_attr "cpu" "itanium2") 852 (eq_attr "itanium_class" "syst_m")) 853 (eq (symbol_ref "bundling_p") (const_int 0))) 854 "2_M_only_um0") 855;; Reservation??? 856(define_insn_reservation "2_tbit" 1 857 (and (and (eq_attr "cpu" "itanium2") 858 (eq_attr "itanium_class" "tbit")) 859 (eq (symbol_ref "bundling_p") (const_int 0))) 860 "2_I+2_only_ui0") 861 862;; There is only ony insn `mov ar.pfs =' for toar_i: 863(define_insn_reservation "2_toar_i" 0 864 (and (and (eq_attr "cpu" "itanium2") 865 (eq_attr "itanium_class" "toar_i")) 866 (eq (symbol_ref "bundling_p") (const_int 0))) 867 "2_I+2_only_ui0") 868;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m: 869;; Latency time ??? 870(define_insn_reservation "2_toar_m" 5 871 (and (and (eq_attr "cpu" "itanium2") 872 (eq_attr "itanium_class" "toar_m")) 873 (eq (symbol_ref "bundling_p") (const_int 0))) 874 "2_M_only_um2") 875;; Latency time ??? 876(define_insn_reservation "2_tobr" 1 877 (and (and (eq_attr "cpu" "itanium2") 878 (eq_attr "itanium_class" "tobr")) 879 (eq (symbol_ref "bundling_p") (const_int 0))) 880 "2_I+2_only_ui0") 881(define_insn_reservation "2_tofr" 5 882 (and (and (eq_attr "cpu" "itanium2") 883 (eq_attr "itanium_class" "tofr")) 884 (eq (symbol_ref "bundling_p") (const_int 0))) 885 "2_M_only_um23") 886;; Latency time ??? 887(define_insn_reservation "2_topr" 1 888 (and (and (eq_attr "cpu" "itanium2") 889 (eq_attr "itanium_class" "topr")) 890 (eq (symbol_ref "bundling_p") (const_int 0))) 891 "2_I+2_only_ui0") 892 893(define_insn_reservation "2_xmpy" 4 894 (and (and (eq_attr "cpu" "itanium2") 895 (eq_attr "itanium_class" "xmpy")) 896 (eq (symbol_ref "bundling_p") (const_int 0))) "2_F") 897;; Latency time ??? 898(define_insn_reservation "2_xtd" 1 899 (and (and (eq_attr "cpu" "itanium2") 900 (eq_attr "itanium_class" "xtd")) 901 (eq (symbol_ref "bundling_p") (const_int 0))) "2_I") 902 903(define_insn_reservation "2_chk_s" 0 904 (and (and (eq_attr "cpu" "itanium2") 905 (eq_attr "itanium_class" "chk_s")) 906 (eq (symbol_ref "bundling_p") (const_int 0))) 907 "2_I|2_M_only_um23") 908(define_insn_reservation "2_lfetch" 0 909 (and (and (eq_attr "cpu" "itanium2") 910 (eq_attr "itanium_class" "lfetch")) 911 (eq (symbol_ref "bundling_p") (const_int 0))) 912 "2_M_only_um01") 913 914(define_insn_reservation "2_nop_m" 0 915 (and (and (eq_attr "cpu" "itanium2") 916 (eq_attr "itanium_class" "nop_m")) 917 (eq (symbol_ref "bundling_p") (const_int 0))) "2_M0") 918(define_insn_reservation "2_nop_b" 0 919 (and (and (eq_attr "cpu" "itanium2") 920 (eq_attr "itanium_class" "nop_b")) 921 (eq (symbol_ref "bundling_p") (const_int 0))) "2_NB") 922(define_insn_reservation "2_nop_i" 0 923 (and (and (eq_attr "cpu" "itanium2") 924 (eq_attr "itanium_class" "nop_i")) 925 (eq (symbol_ref "bundling_p") (const_int 0))) "2_I0") 926(define_insn_reservation "2_nop_f" 0 927 (and (and (eq_attr "cpu" "itanium2") 928 (eq_attr "itanium_class" "nop_f")) 929 (eq (symbol_ref "bundling_p") (const_int 0))) "2_F0") 930(define_insn_reservation "2_nop_x" 0 931 (and (and (eq_attr "cpu" "itanium2") 932 (eq_attr "itanium_class" "nop_x")) 933 (eq (symbol_ref "bundling_p") (const_int 0))) "2_L0") 934 935(define_insn_reservation "2_unknown" 1 936 (and (and (eq_attr "cpu" "itanium2") 937 (eq_attr "itanium_class" "unknown")) 938 (eq (symbol_ref "bundling_p") (const_int 0))) "2_empty") 939 940(define_insn_reservation "2_nop" 0 941 (and (and (eq_attr "cpu" "itanium2") 942 (eq_attr "itanium_class" "nop")) 943 (eq (symbol_ref "bundling_p") (const_int 0))) 944 "2_M0|2_NB|2_I0|2_F0") 945 946(define_insn_reservation "2_ignore" 0 947 (and (and (eq_attr "cpu" "itanium2") 948 (eq_attr "itanium_class" "ignore")) 949 (eq (symbol_ref "bundling_p") (const_int 0))) "nothing") 950 951(define_cpu_unit "2_m_cont_only, 2_b_cont_only" "two") 952(define_cpu_unit "2_mi_cont_only, 2_mm_cont_only, 2_mf_cont_only" "two") 953(define_cpu_unit "2_mb_cont_only, 2_bb_cont_only" "two") 954 955(final_presence_set "2_m_cont_only" "2_m_cont") 956(exclusion_set "2_m_cont_only" 957 "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0mb.b,\ 958 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") 959 960(final_presence_set "2_b_cont_only" "2_b_cont") 961(exclusion_set "2_b_cont_only" "2_0bb.b") 962 963(final_presence_set "2_mi_cont_only" "2_mi_cont") 964(exclusion_set "2_mi_cont_only" "2_0mii., 2_0mib.") 965 966(final_presence_set "2_mm_cont_only" "2_mm_cont") 967(exclusion_set "2_mm_cont_only" "2_0mmi., 2_0mmf., 2_0mmb.") 968 969(final_presence_set "2_mf_cont_only" "2_mf_cont") 970(exclusion_set "2_mf_cont_only" "2_0mfi., 2_0mfb.") 971 972(final_presence_set "2_mb_cont_only" "2_mb_cont") 973(exclusion_set "2_mb_cont_only" "2_0mbb.") 974 975(final_presence_set "2_bb_cont_only" "2_bb_cont") 976(exclusion_set "2_bb_cont_only" "2_0bbb.") 977 978(define_insn_reservation "2_pre_cycle" 0 979 (and (and (eq_attr "cpu" "itanium2") 980 (eq_attr "itanium_class" "pre_cycle")) 981 (eq (symbol_ref "bundling_p") (const_int 0))) 982 "nothing") 983 984;;(define_insn_reservation "2_pre_cycle" 0 985;; (and (and (eq_attr "cpu" "itanium2") 986;; (eq_attr "itanium_class" "pre_cycle")) 987;; (eq (symbol_ref "bundling_p") (const_int 0))) 988;; "(2_0m_bs, 2_m_cont) \ 989;; | (2_0mi_bs, (2_mi_cont|nothing)) \ 990;; | (2_0mm_bs, 2_mm_cont) \ 991;; | (2_0mf_bs, (2_mf_cont|nothing)) \ 992;; | (2_0b_bs, (2_b_cont|nothing)) \ 993;; | (2_0bb_bs, (2_bb_cont|nothing)) \ 994;; | (2_0mb_bs, (2_mb_cont|nothing)) \ 995;; | (2_1m_bs, 2_m_cont) \ 996;; | (2_1mi_bs, (2_mi_cont|nothing)) \ 997;; | (2_1mm_bs, 2_mm_cont) \ 998;; | (2_1mf_bs, (2_mf_cont|nothing)) \ 999;; | (2_1b_bs, (2_b_cont|nothing)) \ 1000;; | (2_1bb_bs, (2_bb_cont|nothing)) \ 1001;; | (2_1mb_bs, (2_mb_cont|nothing)) \ 1002;; | (2_m_cont_only, (2_m_cont|nothing)) \ 1003;; | (2_b_cont_only, (2_b_cont|nothing)) \ 1004;; | (2_mi_cont_only, (2_mi_cont|nothing)) \ 1005;; | (2_mm_cont_only, (2_mm_cont|nothing)) \ 1006;; | (2_mf_cont_only, (2_mf_cont|nothing)) \ 1007;; | (2_mb_cont_only, (2_mb_cont|nothing)) \ 1008;; | (2_bb_cont_only, (2_bb_cont|nothing)) \ 1009;; | (2_m_stop, (2_0mmi_cont|nothing)) \ 1010;; | (2_mi_stop, (2_0mii_cont|nothing))") 1011 1012;; Bypasses: 1013 1014(define_bypass 1 "2_fcmp" "2_br,2_scall") 1015(define_bypass 0 "2_icmp" "2_br,2_scall") 1016(define_bypass 0 "2_tbit" "2_br,2_scall") 1017(define_bypass 2 "2_ld" "2_ld" "ia64_ld_address_bypass_p") 1018(define_bypass 2 "2_ld" "2_st" "ia64_st_address_bypass_p") 1019(define_bypass 2 "2_ld" "2_mmmul,2_mmshf") 1020(define_bypass 3 "2_ilog" "2_mmmul,2_mmshf") 1021(define_bypass 3 "2_ialu" "2_mmmul,2_mmshf") 1022(define_bypass 3 "2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld") 1023(define_bypass 6 "2_tofr" "2_frfr,2_stf") 1024(define_bypass 7 "2_fmac" "2_frfr,2_stf") 1025 1026;; We don't use here fcmp because scall may be predicated. 1027(define_bypass 0 "2_fcvtfx,2_fld,2_fmac,2_fmisc,2_frar_i,2_frar_m,\ 1028 2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_long_i,\ 1029 2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tofr,2_xmpy,2_xtd" 1030 "2_scall") 1031 1032(define_bypass 0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,\ 1033 2_fmac,2_fmisc,2_frar_i,2_frar_m,2_frbr,2_frfr,2_frpr,\ 1034 2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_chk_s,\ 1035 2_long_i,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\ 1036 2_nop_i,2_nop_m,2_nop_x,2_rse_m,2_scall,2_sem,2_stf,2_st,\ 1037 2_syst_m0,2_syst_m,2_tbit,2_toar_i,2_toar_m,2_tobr,2_tofr,\ 1038 2_topr,2_xmpy,2_xtd,2_lfetch" "2_ignore") 1039 1040 1041 1042;; Bundling 1043 1044(define_automaton "twob") 1045 1046;; Pseudo units for quicker searching for position in two packet window. */ 1047(define_query_cpu_unit "2_1,2_2,2_3,2_4,2_5,2_6" "twob") 1048 1049;; All possible combinations of bundles/syllables 1050(define_cpu_unit 1051 "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ 1052 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx" "twob") 1053(define_cpu_unit 1054 "2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\ 1055 2b_0mi.b, 2b_0mm.b, 2b_0mf.b" "twob") 1056(define_query_cpu_unit 1057 "2b_0mii., 2b_0mmi., 2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\ 1058 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx." "twob") 1059 1060(define_cpu_unit 1061 "2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\ 1062 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx" "twob") 1063(define_cpu_unit 1064 "2b_1mi.i, 2b_1mm.i, 2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\ 1065 2b_1mi.b, 2b_1mm.b, 2b_1mf.b" "twob") 1066(define_query_cpu_unit 1067 "2b_1mii., 2b_1mmi., 2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\ 1068 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx." "twob") 1069 1070;; Slot 1 1071(exclusion_set "2b_0m.ii" 1072 "2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ 1073 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1074(exclusion_set "2b_0m.mi" 1075 "2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb, 2b_0m.ib,\ 1076 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1077(exclusion_set "2b_0m.fi" 1078 "2b_0m.mf, 2b_0b.bb, 2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1079(exclusion_set "2b_0m.mf" 1080 "2b_0b.bb, 2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1081(exclusion_set "2b_0b.bb" "2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1082(exclusion_set "2b_0m.bb" "2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1083(exclusion_set "2b_0m.ib" "2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1084(exclusion_set "2b_0m.mb" "2b_0m.fb, 2b_0m.lx") 1085(exclusion_set "2b_0m.fb" "2b_0m.lx") 1086 1087;; Slot 2 1088(exclusion_set "2b_0mi.i" 1089 "2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\ 1090 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1091(exclusion_set "2b_0mm.i" 1092 "2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\ 1093 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1094(exclusion_set "2b_0mf.i" 1095 "2b_0mm.f, 2b_0bb.b, 2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1096(exclusion_set "2b_0mm.f" 1097 "2b_0bb.b, 2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1098(exclusion_set "2b_0bb.b" "2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1099(exclusion_set "2b_0mb.b" "2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1100(exclusion_set "2b_0mi.b" "2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1101(exclusion_set "2b_0mm.b" "2b_0mf.b, 2b_0mlx.") 1102(exclusion_set "2b_0mf.b" "2b_0mlx.") 1103 1104;; Slot 3 1105(exclusion_set "2b_0mii." 1106 "2b_0mmi., 2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\ 1107 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") 1108(exclusion_set "2b_0mmi." 1109 "2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\ 1110 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") 1111(exclusion_set "2b_0mfi." 1112 "2b_0mmf., 2b_0bbb., 2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") 1113(exclusion_set "2b_0mmf." 1114 "2b_0bbb., 2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") 1115(exclusion_set "2b_0bbb." "2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") 1116(exclusion_set "2b_0mbb." "2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") 1117(exclusion_set "2b_0mib." "2b_0mmb., 2b_0mfb., 2b_0mlx.") 1118(exclusion_set "2b_0mmb." "2b_0mfb., 2b_0mlx.") 1119(exclusion_set "2b_0mfb." "2b_0mlx.") 1120 1121;; Slot 4 1122(exclusion_set "2b_1m.ii" 1123 "2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\ 1124 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1125(exclusion_set "2b_1m.mi" 1126 "2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb, 2b_1m.ib,\ 1127 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1128(exclusion_set "2b_1m.fi" 1129 "2b_1m.mf, 2b_1b.bb, 2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1130(exclusion_set "2b_1m.mf" 1131 "2b_1b.bb, 2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1132(exclusion_set "2b_1b.bb" "2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1133(exclusion_set "2b_1m.bb" "2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1134(exclusion_set "2b_1m.ib" "2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1135(exclusion_set "2b_1m.mb" "2b_1m.fb, 2b_1m.lx") 1136(exclusion_set "2b_1m.fb" "2b_1m.lx") 1137 1138;; Slot 5 1139(exclusion_set "2b_1mi.i" 1140 "2b_1mm.i, 2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\ 1141 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1142(exclusion_set "2b_1mm.i" 1143 "2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\ 1144 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1145(exclusion_set "2b_1mf.i" 1146 "2b_1mm.f, 2b_1bb.b, 2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1147(exclusion_set "2b_1mm.f" 1148 "2b_1bb.b, 2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1149(exclusion_set "2b_1bb.b" "2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1150(exclusion_set "2b_1mb.b" "2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1151(exclusion_set "2b_1mi.b" "2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1152(exclusion_set "2b_1mm.b" "2b_1mf.b, 2b_1mlx.") 1153(exclusion_set "2b_1mf.b" "2b_1mlx.") 1154 1155;; Slot 6 1156(exclusion_set "2b_1mii." 1157 "2b_1mmi., 2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\ 1158 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") 1159(exclusion_set "2b_1mmi." 1160 "2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\ 1161 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") 1162(exclusion_set "2b_1mfi." 1163 "2b_1mmf., 2b_1bbb., 2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") 1164(exclusion_set "2b_1mmf." 1165 "2b_1bbb., 2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") 1166(exclusion_set "2b_1bbb." "2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") 1167(exclusion_set "2b_1mbb." "2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") 1168(exclusion_set "2b_1mib." "2b_1mmb., 2b_1mfb., 2b_1mlx.") 1169(exclusion_set "2b_1mmb." "2b_1mfb., 2b_1mlx.") 1170(exclusion_set "2b_1mfb." "2b_1mlx.") 1171 1172(final_presence_set "2b_0mi.i" "2b_0m.ii") 1173(final_presence_set "2b_0mii." "2b_0mi.i") 1174(final_presence_set "2b_1mi.i" "2b_1m.ii") 1175(final_presence_set "2b_1mii." "2b_1mi.i") 1176 1177(final_presence_set "2b_0mm.i" "2b_0m.mi") 1178(final_presence_set "2b_0mmi." "2b_0mm.i") 1179(final_presence_set "2b_1mm.i" "2b_1m.mi") 1180(final_presence_set "2b_1mmi." "2b_1mm.i") 1181 1182(final_presence_set "2b_0mf.i" "2b_0m.fi") 1183(final_presence_set "2b_0mfi." "2b_0mf.i") 1184(final_presence_set "2b_1mf.i" "2b_1m.fi") 1185(final_presence_set "2b_1mfi." "2b_1mf.i") 1186 1187(final_presence_set "2b_0mm.f" "2b_0m.mf") 1188(final_presence_set "2b_0mmf." "2b_0mm.f") 1189(final_presence_set "2b_1mm.f" "2b_1m.mf") 1190(final_presence_set "2b_1mmf." "2b_1mm.f") 1191 1192(final_presence_set "2b_0bb.b" "2b_0b.bb") 1193(final_presence_set "2b_0bbb." "2b_0bb.b") 1194(final_presence_set "2b_1bb.b" "2b_1b.bb") 1195(final_presence_set "2b_1bbb." "2b_1bb.b") 1196 1197(final_presence_set "2b_0mb.b" "2b_0m.bb") 1198(final_presence_set "2b_0mbb." "2b_0mb.b") 1199(final_presence_set "2b_1mb.b" "2b_1m.bb") 1200(final_presence_set "2b_1mbb." "2b_1mb.b") 1201 1202(final_presence_set "2b_0mi.b" "2b_0m.ib") 1203(final_presence_set "2b_0mib." "2b_0mi.b") 1204(final_presence_set "2b_1mi.b" "2b_1m.ib") 1205(final_presence_set "2b_1mib." "2b_1mi.b") 1206 1207(final_presence_set "2b_0mm.b" "2b_0m.mb") 1208(final_presence_set "2b_0mmb." "2b_0mm.b") 1209(final_presence_set "2b_1mm.b" "2b_1m.mb") 1210(final_presence_set "2b_1mmb." "2b_1mm.b") 1211 1212(final_presence_set "2b_0mf.b" "2b_0m.fb") 1213(final_presence_set "2b_0mfb." "2b_0mf.b") 1214(final_presence_set "2b_1mf.b" "2b_1m.fb") 1215(final_presence_set "2b_1mfb." "2b_1mf.b") 1216 1217(final_presence_set "2b_0mlx." "2b_0m.lx") 1218(final_presence_set "2b_1mlx." "2b_1m.lx") 1219 1220;; See the corresponding comment in non-bundling section above. 1221(final_presence_set 1222 "2b_1m.lx" 1223 "2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mib.,2b_0mmb.,2b_0mfb.,2b_0mlx.") 1224(final_presence_set "2b_1b.bb" "2b_0mii.,2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mlx.") 1225(final_presence_set 1226 "2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1m.bb,2b_1m.ib,2b_1m.mb,2b_1m.fb" 1227 "2b_0mii.,2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mib.,2b_0mmb.,2b_0mfb.,2b_0mlx.") 1228 1229;; Ports/units (nb means nop.b insn issued into given port): 1230(define_cpu_unit 1231 "2b_um0, 2b_um1, 2b_um2, 2b_um3, 2b_ui0, 2b_ui1, 2b_uf0, 2b_uf1,\ 1232 2b_ub0, 2b_ub1, 2b_ub2, 2b_unb0, 2b_unb1, 2b_unb2" "twob") 1233 1234(exclusion_set "2b_ub0" "2b_unb0") 1235(exclusion_set "2b_ub1" "2b_unb1") 1236(exclusion_set "2b_ub2" "2b_unb2") 1237 1238;; The following rules are used to decrease number of alternatives. 1239;; They are consequences of Itanium2 microarchitecture. They also 1240;; describe the following rules mentioned in Itanium2 1241;; microarchitecture: rules mentioned in Itanium2 microarchitecture: 1242;; o "BBB/MBB: Always splits issue after either of these bundles". 1243;; o "MIB BBB: Split issue after the first bundle in this pair". 1244(exclusion_set 1245 "2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb." 1246 "2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1b.bb,2b_1m.bb,\ 1247 2b_1m.ib,2b_1m.mb,2b_1m.fb,2b_1m.lx") 1248(exclusion_set "2b_0m.ib,2b_0mi.b,2b_0mib." "2b_1b.bb") 1249 1250;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the 1251;;; B-slot contains a nop.b or a brp instruction". 1252;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or 1253;;; nop.b, otherwise it disperses to B2". 1254(final_absence_set 1255 "2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\ 1256 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx" 1257 "2b_0mib. 2b_ub2, 2b_0mfb. 2b_ub2, 2b_0mmb. 2b_ub2") 1258 1259;; This is necessary to start new processor cycle when we meet stop bit. 1260(define_cpu_unit "2b_stop" "twob") 1261(final_absence_set 1262 "2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\ 1263 2b_0m.fi,2b_0mf.i,2b_0mfi.,\ 1264 2b_0m.mf,2b_0mm.f,2b_0mmf.,2b_0b.bb,2b_0bb.b,2b_0bbb.,\ 1265 2b_0m.bb,2b_0mb.b,2b_0mbb.,\ 1266 2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\ 1267 2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \ 1268 2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\ 1269 2b_1m.fi,2b_1mf.i,2b_1mfi.,\ 1270 2b_1m.mf,2b_1mm.f,2b_1mmf.,2b_1b.bb,2b_1bb.b,2b_1bbb.,\ 1271 2b_1m.bb,2b_1mb.b,2b_1mbb.,\ 1272 2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\ 1273 2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx." 1274 "2b_stop") 1275 1276;; The issue logic can reorder M slot insns between different subtypes 1277;; but can not reorder insn within the same subtypes. The following 1278;; constraint is enough to describe this. 1279(final_presence_set "2b_um1" "2b_um0") 1280(final_presence_set "2b_um3" "2b_um2") 1281 1282;; The insn in the 1st I slot of the two bundle issue group will issue 1283;; to I0. The second I slot insn will issue to I1. 1284(final_presence_set "2b_ui1" "2b_ui0") 1285 1286;; For exceptions of I insns: 1287(define_cpu_unit "2b_only_ui0" "twob") 1288(final_absence_set "2b_only_ui0" "2b_ui1") 1289 1290;; Insns 1291 1292(define_reservation "2b_M" 1293 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ 1294 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ 1295 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ 1296 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ 1297 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ 1298 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ 1299 +(2b_um0|2b_um1|2b_um2|2b_um3)") 1300 1301(define_reservation "2b_M_only_um0" 1302 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ 1303 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ 1304 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ 1305 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ 1306 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ 1307 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ 1308 +2b_um0") 1309 1310(define_reservation "2b_M_only_um2" 1311 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ 1312 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ 1313 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ 1314 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ 1315 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ 1316 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ 1317 +2b_um2") 1318 1319(define_reservation "2b_M_only_um01" 1320 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ 1321 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ 1322 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ 1323 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ 1324 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ 1325 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ 1326 +(2b_um0|2b_um1)") 1327 1328(define_reservation "2b_M_only_um23" 1329 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ 1330 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ 1331 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ 1332 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ 1333 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ 1334 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ 1335 +(2b_um2|2b_um3)") 1336 1337;; I instruction is dispersed to the lowest numbered I unit 1338;; not already in use. Remeber about possible splitting. 1339(define_reservation "2b_I" 1340 "2b_0mi.i+2_2+2b_ui0|2b_0mii.+2_3+(2b_ui0|2b_ui1)|2b_0mmi.+2_3+2b_ui0\ 1341 |2b_0mfi.+2_3+2b_ui0|2b_0mi.b+2_2+2b_ui0\ 1342 |(2b_1mi.i+2_5|2b_1mi.b+2_5)+(2b_ui0|2b_ui1)\ 1343 |(2b_1mii.|2b_1mmi.|2b_1mfi.)+2_6+(2b_ui0|2b_ui1)") 1344 1345;; "An F slot in the 1st bundle disperses to F0". 1346;; "An F slot in the 2st bundle disperses to F1". 1347(define_reservation "2b_F" 1348 "2b_0mf.i+2_2+2b_uf0|2b_0mmf.+2_3+2b_uf0|2b_0mf.b+2_2+2b_uf0\ 1349 |2b_1mf.i+2_5+2b_uf1|2b_1mmf.+2_6+2b_uf1|2b_1mf.b+2_5+2b_uf1") 1350 1351;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B 1352;;; unit. That is, a B slot in 1st position is dispersed to B0. In the 1353;;; 2nd position it is dispersed to B2". 1354(define_reservation "2b_NB" 1355 "2b_0b.bb+2_1+2b_unb0|2b_0bb.b+2_2+2b_unb1|2b_0bbb.+2_3+2b_unb2\ 1356 |2b_0mb.b+2_2+2b_unb1|2b_0mbb.+2_3+2b_unb2\ 1357 |2b_0mib.+2_3+2b_unb0|2b_0mmb.+2_3+2b_unb0|2b_0mfb.+2_3+2b_unb0\ 1358 |2b_1b.bb+2_4+2b_unb0|2b_1bb.b+2_5+2b_unb1\ 1359 |2b_1bbb.+2_6+2b_unb2|2b_1mb.b+2_5+2b_unb1|2b_1mbb.+2_6+2b_unb2\ 1360 |2b_1mib.+2_6+2b_unb0|2b_1mmb.+2_6+2b_unb0|2b_1mfb.+2_6+2b_unb0") 1361 1362(define_reservation "2b_B" 1363 "2b_0b.bb+2_1+2b_ub0|2b_0bb.b+2_2+2b_ub1|2b_0bbb.+2_3+2b_ub2\ 1364 |2b_0mb.b+2_2+2b_ub1|2b_0mbb.+2_3+2b_ub2|2b_0mib.+2_3+2b_ub2\ 1365 |2b_0mfb.+2_3+2b_ub2|2b_1b.bb+2_4+2b_ub0|2b_1bb.b+2_5+2b_ub1\ 1366 |2b_1bbb.+2_6+2b_ub2|2b_1mb.b+2_5+2b_ub1\ 1367 |2b_1mib.+2_6+2b_ub2|2b_1mmb.+2_6+2b_ub2|2b_1mfb.+2_6+2b_ub2") 1368 1369;; For the MLI template, the I slot insn is always assigned to port I0 1370;; if it is in the first bundle or it is assigned to port I1 if it is in 1371;; the second bundle. 1372(define_reservation "2b_L" 1373 "2b_0mlx.+2_3+2b_ui0+2b_uf0|2b_1mlx.+2_6+2b_ui1+2b_uf1") 1374 1375;; Should we describe that A insn in I slot can be issued into M 1376;; ports? I think it is not necessary because of multipass 1377;; scheduling. For example, the multipass scheduling could use 1378;; MMI-MMI instead of MII-MII where the two last I slots contain A 1379;; insns (even if the case is complicated by use-def conflicts). 1380;; 1381;; In any case we could describe it as 1382;; (define_cpu_unit "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres" 1383;; "twob") 1384;; (final_presence_set "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres" 1385;; "2b_ui1") 1386;; (define_reservation "b_A" 1387;; "b_M|b_I\ 1388;; |(2b_1mi.i+2_5|2b_1mii.+2_6|2b_1mmi.+2_6|2b_1mfi.+2_6|2b_1mi.b+2_5)\ 1389;; +(2b_um0|2b_um1|2b_um2|2b_um3)\ 1390;; +(2b_ui1_0pres|2b_ui1_1pres|2b_ui1_2pres|2b_ui1_3pres)") 1391 1392(define_reservation "2b_A" "2b_M|2b_I") 1393 1394;; We assume that there is no insn issued on the same cycle as the 1395;; unknown insn. 1396(define_cpu_unit "2b_empty" "twob") 1397(exclusion_set "2b_empty" 1398 "2b_0m.ii,2b_0m.mi,2b_0m.fi,2b_0m.mf,2b_0b.bb,2b_0m.bb,\ 1399 2b_0m.ib,2b_0m.mb,2b_0m.fb,2b_0m.lx,2b_0mm.i") 1400 1401(define_cpu_unit 1402 "2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs" 1403 "twob") 1404(define_cpu_unit 1405 "2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs" 1406 "twob") 1407 1408(define_cpu_unit "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont, 2b_mb_cont,\ 1409 2b_b_cont, 2b_bb_cont" "twob") 1410 1411;; For stop in the middle of the bundles. 1412(define_cpu_unit "2b_m_stop, 2b_m0_stop, 2b_m1_stop, 2b_0mmi_cont" "twob") 1413(define_cpu_unit "2b_mi_stop, 2b_mi0_stop, 2b_mi1_stop, 2b_0mii_cont" "twob") 1414 1415(final_presence_set "2b_0m_bs" 1416 "2b_0m.ii, 2b_0m.mi, 2b_0m.mf, 2b_0m.fi, 2b_0m.bb,\ 1417 2b_0m.ib, 2b_0m.fb, 2b_0m.mb, 2b_0m.lx") 1418(final_presence_set "2b_1m_bs" 1419 "2b_1m.ii, 2b_1m.mi, 2b_1m.mf, 2b_1m.fi, 2b_1m.bb,\ 1420 2b_1m.ib, 2b_1m.fb, 2b_1m.mb, 2b_1m.lx") 1421(final_presence_set "2b_0mi_bs" "2b_0mi.i, 2b_0mi.i") 1422(final_presence_set "2b_1mi_bs" "2b_1mi.i, 2b_1mi.i") 1423(final_presence_set "2b_0mm_bs" "2b_0mm.i, 2b_0mm.f, 2b_0mm.b") 1424(final_presence_set "2b_1mm_bs" "2b_1mm.i, 2b_1mm.f, 2b_1mm.b") 1425(final_presence_set "2b_0mf_bs" "2b_0mf.i, 2b_0mf.b") 1426(final_presence_set "2b_1mf_bs" "2b_1mf.i, 2b_1mf.b") 1427(final_presence_set "2b_0b_bs" "2b_0b.bb") 1428(final_presence_set "2b_1b_bs" "2b_1b.bb") 1429(final_presence_set "2b_0bb_bs" "2b_0bb.b") 1430(final_presence_set "2b_1bb_bs" "2b_1bb.b") 1431(final_presence_set "2b_0mb_bs" "2b_0mb.b") 1432(final_presence_set "2b_1mb_bs" "2b_1mb.b") 1433 1434(exclusion_set "2b_0m_bs" 1435 "2b_0mi.i, 2b_0mm.i, 2b_0mm.f, 2b_0mf.i, 2b_0mb.b,\ 1436 2b_0mi.b, 2b_0mf.b, 2b_0mm.b, 2b_0mlx., 2b_m0_stop") 1437(exclusion_set "2b_1m_bs" 1438 "2b_1mi.i, 2b_1mm.i, 2b_1mm.f, 2b_1mf.i, 2b_1mb.b,\ 1439 2b_1mi.b, 2b_1mf.b, 2b_1mm.b, 2b_1mlx., 2b_m1_stop") 1440(exclusion_set "2b_0mi_bs" "2b_0mii., 2b_0mib., 2b_mi0_stop") 1441(exclusion_set "2b_1mi_bs" "2b_1mii., 2b_1mib., 2b_mi1_stop") 1442(exclusion_set "2b_0mm_bs" "2b_0mmi., 2b_0mmf., 2b_0mmb.") 1443(exclusion_set "2b_1mm_bs" "2b_1mmi., 2b_1mmf., 2b_1mmb.") 1444(exclusion_set "2b_0mf_bs" "2b_0mfi., 2b_0mfb.") 1445(exclusion_set "2b_1mf_bs" "2b_1mfi., 2b_1mfb.") 1446(exclusion_set "2b_0b_bs" "2b_0bb.b") 1447(exclusion_set "2b_1b_bs" "2b_1bb.b") 1448(exclusion_set "2b_0bb_bs" "2b_0bbb.") 1449(exclusion_set "2b_1bb_bs" "2b_1bbb.") 1450(exclusion_set "2b_0mb_bs" "2b_0mbb.") 1451(exclusion_set "2b_1mb_bs" "2b_1mbb.") 1452 1453(exclusion_set 1454 "2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs, 1455 2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs" 1456 "2b_stop") 1457 1458(final_presence_set 1459 "2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0mb.b,\ 1460 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx." 1461 "2b_m_cont") 1462(final_presence_set "2b_0mii., 2b_0mib." "2b_mi_cont") 1463(final_presence_set "2b_0mmi., 2b_0mmf., 2b_0mmb." "2b_mm_cont") 1464(final_presence_set "2b_0mfi., 2b_0mfb." "2b_mf_cont") 1465(final_presence_set "2b_0bb.b" "2b_b_cont") 1466(final_presence_set "2b_0bbb." "2b_bb_cont") 1467(final_presence_set "2b_0mbb." "2b_mb_cont") 1468 1469(exclusion_set 1470 "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ 1471 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx" 1472 "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont,\ 1473 2b_mb_cont, 2b_b_cont, 2b_bb_cont") 1474 1475(exclusion_set "2b_empty" 1476 "2b_m_cont,2b_mi_cont,2b_mm_cont,2b_mf_cont,\ 1477 2b_mb_cont,2b_b_cont,2b_bb_cont") 1478 1479;; For m;mi bundle 1480(final_presence_set "2b_m0_stop" "2b_0m.mi") 1481(final_presence_set "2b_0mm.i" "2b_0mmi_cont") 1482(exclusion_set "2b_0mmi_cont" 1483 "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ 1484 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1485(exclusion_set "2b_m0_stop" "2b_0mm.i") 1486(final_presence_set "2b_m1_stop" "2b_1m.mi") 1487(exclusion_set "2b_m1_stop" "2b_1mm.i") 1488(final_presence_set "2b_m_stop" "2b_m0_stop, 2b_m1_stop") 1489 1490;; For mi;i bundle 1491(final_presence_set "2b_mi0_stop" "2b_0mi.i") 1492(final_presence_set "2b_0mii." "2b_0mii_cont") 1493(exclusion_set "2b_0mii_cont" 1494 "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ 1495 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1496(exclusion_set "2b_mi0_stop" "2b_0mii.") 1497(final_presence_set "2b_mi1_stop" "2b_1mi.i") 1498(exclusion_set "2b_mi1_stop" "2b_1mii.") 1499(final_presence_set "2b_mi_stop" "2b_mi0_stop, 2b_mi1_stop") 1500 1501(final_absence_set 1502 "2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\ 1503 2b_0m.fi,2b_0mf.i,2b_0mfi.,2b_0m.mf,2b_0mm.f,2b_0mmf.,\ 1504 2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb.,\ 1505 2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\ 1506 2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \ 1507 2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\ 1508 2b_1m.fi,2b_1mf.i,2b_1mfi.,2b_1m.mf,2b_1mm.f,2b_1mmf.,\ 1509 2b_1b.bb,2b_1bb.b,2b_1bbb.,2b_1m.bb,2b_1mb.b,2b_1mbb.,\ 1510 2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\ 1511 2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx." 1512 "2b_m0_stop,2b_m1_stop,2b_mi0_stop,2b_mi1_stop") 1513 1514(define_insn_reservation "2b_stop_bit" 0 1515 (and (and (eq_attr "cpu" "itanium2") 1516 (eq_attr "itanium_class" "stop_bit")) 1517 (ne (symbol_ref "bundling_p") (const_int 0))) 1518 "2b_stop|2b_m0_stop|2b_m1_stop|2b_mi0_stop|2b_mi1_stop") 1519(define_insn_reservation "2b_br" 0 1520 (and (and (eq_attr "cpu" "itanium2") 1521 (eq_attr "itanium_class" "br")) 1522 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_B") 1523(define_insn_reservation "2b_scall" 0 1524 (and (and (eq_attr "cpu" "itanium2") 1525 (eq_attr "itanium_class" "scall")) 1526 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_B") 1527(define_insn_reservation "2b_fcmp" 2 1528 (and (and (eq_attr "cpu" "itanium2") 1529 (eq_attr "itanium_class" "fcmp")) 1530 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") 1531(define_insn_reservation "2b_fcvtfx" 4 1532 (and (and (eq_attr "cpu" "itanium2") 1533 (eq_attr "itanium_class" "fcvtfx")) 1534 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") 1535(define_insn_reservation "2b_fld" 6 1536 (and (and (eq_attr "cpu" "itanium2") 1537 (eq_attr "itanium_class" "fld")) 1538 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_M") 1539(define_insn_reservation "2b_fmac" 4 1540 (and (and (eq_attr "cpu" "itanium2") 1541 (eq_attr "itanium_class" "fmac")) 1542 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") 1543(define_insn_reservation "2b_fmisc" 4 1544 (and (and (eq_attr "cpu" "itanium2") 1545 (eq_attr "itanium_class" "fmisc")) 1546 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") 1547 1548;; Latency time ??? 1549(define_insn_reservation "2b_frar_i" 13 1550 (and (and (eq_attr "cpu" "itanium2") 1551 (eq_attr "itanium_class" "frar_i")) 1552 (ne (symbol_ref "bundling_p") (const_int 0))) 1553 "2b_I+2b_only_ui0") 1554;; Latency time ??? 1555(define_insn_reservation "2b_frar_m" 6 1556 (and (and (eq_attr "cpu" "itanium2") 1557 (eq_attr "itanium_class" "frar_m")) 1558 (ne (symbol_ref "bundling_p") (const_int 0))) 1559 "2b_M_only_um2") 1560(define_insn_reservation "2b_frbr" 2 1561 (and (and (eq_attr "cpu" "itanium2") 1562 (eq_attr "itanium_class" "frbr")) 1563 (ne (symbol_ref "bundling_p") (const_int 0))) 1564 "2b_I+2b_only_ui0") 1565(define_insn_reservation "2b_frfr" 5 1566 (and (and (eq_attr "cpu" "itanium2") 1567 (eq_attr "itanium_class" "frfr")) 1568 (ne (symbol_ref "bundling_p") (const_int 0))) 1569 "2b_M_only_um2") 1570(define_insn_reservation "2b_frpr" 2 1571 (and (and (eq_attr "cpu" "itanium2") 1572 (eq_attr "itanium_class" "frpr")) 1573 (ne (symbol_ref "bundling_p") (const_int 0))) 1574 "2b_I+2b_only_ui0") 1575 1576(define_insn_reservation "2b_ialu" 1 1577 (and (and (eq_attr "cpu" "itanium2") 1578 (eq_attr "itanium_class" "ialu")) 1579 (ne (symbol_ref "bundling_p") (const_int 0))) 1580 "2b_A") 1581(define_insn_reservation "2b_icmp" 1 1582 (and (and (eq_attr "cpu" "itanium2") 1583 (eq_attr "itanium_class" "icmp")) 1584 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_A") 1585(define_insn_reservation "2b_ilog" 1 1586 (and (and (eq_attr "cpu" "itanium2") 1587 (eq_attr "itanium_class" "ilog")) 1588 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_A") 1589;; Latency time ??? 1590(define_insn_reservation "2b_ishf" 1 1591 (and (and (eq_attr "cpu" "itanium2") 1592 (eq_attr "itanium_class" "ishf")) 1593 (ne (symbol_ref "bundling_p") (const_int 0))) 1594 "2b_I+2b_only_ui0") 1595(define_insn_reservation "2b_ld" 1 1596 (and (and (eq_attr "cpu" "itanium2") 1597 (eq_attr "itanium_class" "ld")) 1598 (ne (symbol_ref "bundling_p") (const_int 0))) 1599 "2b_M_only_um01") 1600(define_insn_reservation "2b_long_i" 1 1601 (and (and (eq_attr "cpu" "itanium2") 1602 (eq_attr "itanium_class" "long_i")) 1603 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_L") 1604 1605;; Latency time ??? 1606(define_insn_reservation "2b_mmmul" 2 1607 (and (and (eq_attr "cpu" "itanium2") 1608 (eq_attr "itanium_class" "mmmul")) 1609 (ne (symbol_ref "bundling_p") (const_int 0))) 1610 "2b_I+2b_only_ui0") 1611;; Latency time ??? 1612(define_insn_reservation "2b_mmshf" 2 1613 (and (and (eq_attr "cpu" "itanium2") 1614 (eq_attr "itanium_class" "mmshf")) 1615 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I") 1616;; Latency time ??? 1617(define_insn_reservation "2b_mmshfi" 1 1618 (and (and (eq_attr "cpu" "itanium2") 1619 (eq_attr "itanium_class" "mmshfi")) 1620 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I") 1621 1622(define_insn_reservation "2b_rse_m" 0 1623 (and (and (eq_attr "cpu" "itanium2") 1624 (eq_attr "itanium_class" "rse_m")) 1625 (ne (symbol_ref "bundling_p") (const_int 0))) 1626 "(2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ 1627 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1+2b_um0") 1628(define_insn_reservation "2b_sem" 0 1629 (and (and (eq_attr "cpu" "itanium2") 1630 (eq_attr "itanium_class" "sem")) 1631 (ne (symbol_ref "bundling_p") (const_int 0))) 1632 "2b_M_only_um23") 1633 1634(define_insn_reservation "2b_stf" 1 1635 (and (and (eq_attr "cpu" "itanium2") 1636 (eq_attr "itanium_class" "stf")) 1637 (ne (symbol_ref "bundling_p") (const_int 0))) 1638 "2b_M_only_um23") 1639(define_insn_reservation "2b_st" 1 1640 (and (and (eq_attr "cpu" "itanium2") 1641 (eq_attr "itanium_class" "st")) 1642 (ne (symbol_ref "bundling_p") (const_int 0))) 1643 "2b_M_only_um23") 1644(define_insn_reservation "2b_syst_m0" 0 1645 (and (and (eq_attr "cpu" "itanium2") 1646 (eq_attr "itanium_class" "syst_m0")) 1647 (ne (symbol_ref "bundling_p") (const_int 0))) 1648 "2b_M_only_um2") 1649(define_insn_reservation "2b_syst_m" 0 1650 (and (and (eq_attr "cpu" "itanium2") 1651 (eq_attr "itanium_class" "syst_m")) 1652 (ne (symbol_ref "bundling_p") (const_int 0))) 1653 "2b_M_only_um0") 1654;; Reservation??? 1655(define_insn_reservation "2b_tbit" 1 1656 (and (and (eq_attr "cpu" "itanium2") 1657 (eq_attr "itanium_class" "tbit")) 1658 (ne (symbol_ref "bundling_p") (const_int 0))) 1659 "2b_I+2b_only_ui0") 1660(define_insn_reservation "2b_toar_i" 0 1661 (and (and (eq_attr "cpu" "itanium2") 1662 (eq_attr "itanium_class" "toar_i")) 1663 (ne (symbol_ref "bundling_p") (const_int 0))) 1664 "2b_I+2b_only_ui0") 1665;; Latency time ??? 1666(define_insn_reservation "2b_toar_m" 5 1667 (and (and (eq_attr "cpu" "itanium2") 1668 (eq_attr "itanium_class" "toar_m")) 1669 (ne (symbol_ref "bundling_p") (const_int 0))) 1670 "2b_M_only_um2") 1671;; Latency time ??? 1672(define_insn_reservation "2b_tobr" 1 1673 (and (and (eq_attr "cpu" "itanium2") 1674 (eq_attr "itanium_class" "tobr")) 1675 (ne (symbol_ref "bundling_p") (const_int 0))) 1676 "2b_I+2b_only_ui0") 1677(define_insn_reservation "2b_tofr" 5 1678 (and (and (eq_attr "cpu" "itanium2") 1679 (eq_attr "itanium_class" "tofr")) 1680 (ne (symbol_ref "bundling_p") (const_int 0))) 1681 "2b_M_only_um23") 1682;; Latency time ??? 1683(define_insn_reservation "2b_topr" 1 1684 (and (and (eq_attr "cpu" "itanium2") 1685 (eq_attr "itanium_class" "topr")) 1686 (ne (symbol_ref "bundling_p") (const_int 0))) 1687 "2b_I+2b_only_ui0") 1688 1689(define_insn_reservation "2b_xmpy" 4 1690 (and (and (eq_attr "cpu" "itanium2") 1691 (eq_attr "itanium_class" "xmpy")) 1692 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") 1693;; Latency time ??? 1694(define_insn_reservation "2b_xtd" 1 1695 (and (and (eq_attr "cpu" "itanium2") 1696 (eq_attr "itanium_class" "xtd")) 1697 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I") 1698(define_insn_reservation "2b_chk_s" 0 1699 (and (and (eq_attr "cpu" "itanium2") 1700 (eq_attr "itanium_class" "chk_s")) 1701 (ne (symbol_ref "bundling_p") (const_int 0))) 1702 "2b_I|2b_M_only_um23") 1703(define_insn_reservation "2b_lfetch" 0 1704 (and (and (eq_attr "cpu" "itanium2") 1705 (eq_attr "itanium_class" "lfetch")) 1706 (ne (symbol_ref "bundling_p") (const_int 0))) 1707 "2b_M_only_um01") 1708(define_insn_reservation "2b_nop_m" 0 1709 (and (and (eq_attr "cpu" "itanium2") 1710 (eq_attr "itanium_class" "nop_m")) 1711 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_M") 1712(define_insn_reservation "2b_nop_b" 0 1713 (and (and (eq_attr "cpu" "itanium2") 1714 (eq_attr "itanium_class" "nop_b")) 1715 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_NB") 1716(define_insn_reservation "2b_nop_i" 0 1717 (and (and (eq_attr "cpu" "itanium2") 1718 (eq_attr "itanium_class" "nop_i")) 1719 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I") 1720(define_insn_reservation "2b_nop_f" 0 1721 (and (and (eq_attr "cpu" "itanium2") 1722 (eq_attr "itanium_class" "nop_f")) 1723 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") 1724(define_insn_reservation "2b_nop_x" 0 1725 (and (and (eq_attr "cpu" "itanium2") 1726 (eq_attr "itanium_class" "nop_x")) 1727 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_L") 1728(define_insn_reservation "2b_unknown" 1 1729 (and (and (eq_attr "cpu" "itanium2") 1730 (eq_attr "itanium_class" "unknown")) 1731 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_empty") 1732(define_insn_reservation "2b_nop" 0 1733 (and (and (eq_attr "cpu" "itanium2") 1734 (eq_attr "itanium_class" "nop")) 1735 (ne (symbol_ref "bundling_p") (const_int 0))) 1736 "2b_M|2b_NB|2b_I|2b_F") 1737(define_insn_reservation "2b_ignore" 0 1738 (and (and (eq_attr "cpu" "itanium2") 1739 (eq_attr "itanium_class" "ignore")) 1740 (ne (symbol_ref "bundling_p") (const_int 0))) "nothing") 1741 1742(define_insn_reservation "2b_pre_cycle" 0 1743 (and (and (eq_attr "cpu" "itanium2") 1744 (eq_attr "itanium_class" "pre_cycle")) 1745 (ne (symbol_ref "bundling_p") (const_int 0))) 1746 "(2b_0m_bs, 2b_m_cont) \ 1747 | (2b_0mi_bs, 2b_mi_cont) \ 1748 | (2b_0mm_bs, 2b_mm_cont) \ 1749 | (2b_0mf_bs, 2b_mf_cont) \ 1750 | (2b_0b_bs, 2b_b_cont) \ 1751 | (2b_0bb_bs, 2b_bb_cont) \ 1752 | (2b_0mb_bs, 2b_mb_cont) \ 1753 | (2b_1m_bs, 2b_m_cont) \ 1754 | (2b_1mi_bs, 2b_mi_cont) \ 1755 | (2b_1mm_bs, 2b_mm_cont) \ 1756 | (2b_1mf_bs, 2b_mf_cont) \ 1757 | (2b_1b_bs, 2b_b_cont) \ 1758 | (2b_1bb_bs, 2b_bb_cont) \ 1759 | (2b_1mb_bs, 2b_mb_cont) \ 1760 | (2b_m_stop, 2b_0mmi_cont) \ 1761 | (2b_mi_stop, 2b_0mii_cont)") 1762 1763