i386.md revision 117404
1234027Sstas;; GCC machine description for IA-32 and x86-64. 2226031Sstas;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3226031Sstas;; 2001, 2002, 2003 4226031Sstas;; Free Software Foundation, Inc. 5226031Sstas;; Mostly by William Schelter. 6226031Sstas;; x86_64 support added by Jan Hubicka 7226031Sstas;; 8226031Sstas;; This file is part of GNU CC. 9226031Sstas;; 10226031Sstas;; GNU CC is free software; you can redistribute it and/or modify 11226031Sstas;; it under the terms of the GNU General Public License as published by 12226031Sstas;; the Free Software Foundation; either version 2, or (at your option) 13226031Sstas;; any later version. 14226031Sstas;; 15226031Sstas;; GNU CC is distributed in the hope that it will be useful, 16226031Sstas;; but WITHOUT ANY WARRANTY; without even the implied warranty of 17226031Sstas;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18226031Sstas;; GNU General Public License for more details. 19226031Sstas;; 20226031Sstas;; You should have received a copy of the GNU General Public License 21226031Sstas;; along with GNU CC; see the file COPYING. If not, write to 22226031Sstas;; the Free Software Foundation, 59 Temple Place - Suite 330, 23226031Sstas;; Boston, MA 02111-1307, USA. */ 24226031Sstas;; 25226031Sstas;; The original PO technology requires these to be ordered by speed, 26226031Sstas;; so that assigner will pick the fastest. 27226031Sstas;; 28226031Sstas;; See file "rtl.def" for documentation on define_insn, match_*, et. al. 29226031Sstas;; 30226031Sstas;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code 31226031Sstas;; updates for most instructions. 32226031Sstas;; 33226031Sstas;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register 34226031Sstas;; constraint letters. 35226031Sstas;; 36226031Sstas;; The special asm out single letter directives following a '%' are: 37226031Sstas;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of 38226031Sstas;; operands[1]. 39226031Sstas;; 'L' Print the opcode suffix for a 32-bit integer opcode. 40226031Sstas;; 'W' Print the opcode suffix for a 16-bit integer opcode. 41226031Sstas;; 'B' Print the opcode suffix for an 8-bit integer opcode. 42226031Sstas;; 'Q' Print the opcode suffix for a 64-bit float opcode. 43226031Sstas;; 'S' Print the opcode suffix for a 32-bit float opcode. 44226031Sstas;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode. 45226031Sstas;; 'J' Print the appropriate jump operand. 46226031Sstas;; 47226031Sstas;; 'b' Print the QImode name of the register for the indicated operand. 48226031Sstas;; %b0 would print %al if operands[0] is reg 0. 49226031Sstas;; 'w' Likewise, print the HImode name of the register. 50226031Sstas;; 'k' Likewise, print the SImode name of the register. 51226031Sstas;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh. 52226031Sstas;; 'y' Print "st(0)" instead of "st" as a register. 53226031Sstas 54226031Sstas;; UNSPEC usage: 55226031Sstas 56226031Sstas(define_constants 57226031Sstas [; Relocation specifiers 58226031Sstas (UNSPEC_GOT 0) 59226031Sstas (UNSPEC_GOTOFF 1) 60226031Sstas (UNSPEC_GOTPCREL 2) 61226031Sstas (UNSPEC_GOTTPOFF 3) 62226031Sstas (UNSPEC_TPOFF 4) 63226031Sstas (UNSPEC_NTPOFF 5) 64226031Sstas (UNSPEC_DTPOFF 6) 65226031Sstas (UNSPEC_GOTNTPOFF 7) 66226031Sstas (UNSPEC_INDNTPOFF 8) 67226031Sstas 68226031Sstas ; Prologue support 69226031Sstas (UNSPEC_STACK_PROBE 10) 70226031Sstas (UNSPEC_STACK_ALLOC 11) 71226031Sstas (UNSPEC_SET_GOT 12) 72226031Sstas (UNSPEC_SSE_PROLOGUE_SAVE 13) 73226031Sstas 74226031Sstas ; TLS support 75226031Sstas (UNSPEC_TP 15) 76226031Sstas (UNSPEC_TLS_GD 16) 77226031Sstas (UNSPEC_TLS_LD_BASE 17) 78226031Sstas 79226031Sstas ; Other random patterns 80226031Sstas (UNSPEC_SCAS 20) 81226031Sstas (UNSPEC_SIN 21) 82226031Sstas (UNSPEC_COS 22) 83226031Sstas (UNSPEC_BSF 23) 84226031Sstas (UNSPEC_FNSTSW 24) 85226031Sstas (UNSPEC_SAHF 25) 86226031Sstas (UNSPEC_FSTCW 26) 87226031Sstas (UNSPEC_ADD_CARRY 27) 88226031Sstas (UNSPEC_FLDCW 28) 89226031Sstas 90226031Sstas ; For SSE/MMX support: 91226031Sstas (UNSPEC_FIX 30) 92226031Sstas (UNSPEC_MASKMOV 32) 93226031Sstas (UNSPEC_MOVMSK 33) 94226031Sstas (UNSPEC_MOVNT 34) 95226031Sstas (UNSPEC_MOVA 38) 96226031Sstas (UNSPEC_MOVU 39) 97226031Sstas (UNSPEC_SHUFFLE 41) 98226031Sstas (UNSPEC_RCP 42) 99226031Sstas (UNSPEC_RSQRT 43) 100226031Sstas (UNSPEC_SFENCE 44) 101226031Sstas (UNSPEC_NOP 45) ; prevents combiner cleverness 102226031Sstas (UNSPEC_PAVGUSB 49) 103226031Sstas (UNSPEC_PFRCP 50) 104226031Sstas (UNSPEC_PFRCPIT1 51) 105226031Sstas (UNSPEC_PFRCPIT2 52) 106226031Sstas (UNSPEC_PFRSQRT 53) 107226031Sstas (UNSPEC_PFRSQIT1 54) 108226031Sstas (UNSPEC_PSHUFLW 55) 109226031Sstas (UNSPEC_PSHUFHW 56) 110226031Sstas (UNSPEC_MFENCE 59) 111226031Sstas (UNSPEC_LFENCE 60) 112226031Sstas (UNSPEC_PSADBW 61) 113226031Sstas ]) 114226031Sstas 115226031Sstas(define_constants 116226031Sstas [(UNSPECV_BLOCKAGE 0) 117226031Sstas (UNSPECV_EH_RETURN 13) 118226031Sstas (UNSPECV_EMMS 31) 119226031Sstas (UNSPECV_LDMXCSR 37) 120226031Sstas (UNSPECV_STMXCSR 40) 121226031Sstas (UNSPECV_FEMMS 46) 122226031Sstas (UNSPECV_CLFLUSH 57) 123226031Sstas ]) 124226031Sstas 125226031Sstas;; Insns whose names begin with "x86_" are emitted by gen_FOO calls 126226031Sstas;; from i386.c. 127226031Sstas 128226031Sstas;; In C guard expressions, put expressions which may be compile-time 129226031Sstas;; constants first. This allows for better optimization. For 130226031Sstas;; example, write "TARGET_64BIT && reload_completed", not 131226031Sstas;; "reload_completed && TARGET_64BIT". 132226031Sstas 133226031Sstas 134226031Sstas;; Processor type. This attribute must exactly match the processor_type 135226031Sstas;; enumeration in i386.h. 136226031Sstas(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4" 137226031Sstas (const (symbol_ref "ix86_cpu"))) 138226031Sstas 139226031Sstas;; A basic instruction type. Refinements due to arguments to be 140226031Sstas;; provided in other attributes. 141226031Sstas(define_attr "type" 142226031Sstas "other,multi, 143226031Sstas alu,alu1,negnot,imov,imovx,lea, 144226031Sstas incdec,ishift,ishift1,rotate,rotate1,imul,idiv, 145226031Sstas icmp,test,ibr,setcc,icmov, 146226031Sstas push,pop,call,callv, 147226031Sstas str,cld, 148226031Sstas fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp, 149226031Sstas sselog,sseiadd,sseishft,sseimul, 150226031Sstas sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv, 151226031Sstas mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft" 152226031Sstas (const_string "other")) 153226031Sstas 154226031Sstas;; Main data type used by the insn 155226031Sstas(define_attr "mode" 156226031Sstas "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI,V4SF,V2DF,V2SF" 157226031Sstas (const_string "unknown")) 158226031Sstas 159226031Sstas;; The CPU unit operations uses. 160226031Sstas(define_attr "unit" "integer,i387,sse,mmx,unknown" 161226031Sstas (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp") 162226031Sstas (const_string "i387") 163226031Sstas (eq_attr "type" "sselog,sseiadd,sseishft,sseimul, 164226031Sstas sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv") 165226031Sstas (const_string "sse") 166226031Sstas (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft") 167226031Sstas (const_string "mmx") 168226031Sstas (eq_attr "type" "other") 169226031Sstas (const_string "unknown")] 170226031Sstas (const_string "integer"))) 171226031Sstas 172226031Sstas;; The (bounding maximum) length of an instruction immediate. 173226031Sstas(define_attr "length_immediate" "" 174226031Sstas (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv") 175226031Sstas (const_int 0) 176226031Sstas (eq_attr "unit" "i387,sse,mmx") 177226031Sstas (const_int 0) 178226031Sstas (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1, 179226031Sstas imul,icmp,push,pop") 180226031Sstas (symbol_ref "ix86_attr_length_immediate_default(insn,1)") 181226031Sstas (eq_attr "type" "imov,test") 182226031Sstas (symbol_ref "ix86_attr_length_immediate_default(insn,0)") 183226031Sstas (eq_attr "type" "call") 184226031Sstas (if_then_else (match_operand 0 "constant_call_address_operand" "") 185226031Sstas (const_int 4) 186226031Sstas (const_int 0)) 187226031Sstas (eq_attr "type" "callv") 188226031Sstas (if_then_else (match_operand 1 "constant_call_address_operand" "") 189226031Sstas (const_int 4) 190226031Sstas (const_int 0)) 191226031Sstas ;; We don't know the size before shorten_branches. Expect 192226031Sstas ;; the instruction to fit for better scheduling. 193226031Sstas (eq_attr "type" "ibr") 194226031Sstas (const_int 1) 195226031Sstas ] 196226031Sstas (symbol_ref "/* Update immediate_length and other attributes! */ 197226031Sstas abort(),1"))) 198226031Sstas 199226031Sstas;; The (bounding maximum) length of an instruction address. 200226031Sstas(define_attr "length_address" "" 201226031Sstas (cond [(eq_attr "type" "str,cld,other,multi,fxch") 202226031Sstas (const_int 0) 203226031Sstas (and (eq_attr "type" "call") 204226031Sstas (match_operand 0 "constant_call_address_operand" "")) 205226031Sstas (const_int 0) 206226031Sstas (and (eq_attr "type" "callv") 207226031Sstas (match_operand 1 "constant_call_address_operand" "")) 208226031Sstas (const_int 0) 209226031Sstas ] 210226031Sstas (symbol_ref "ix86_attr_length_address_default (insn)"))) 211226031Sstas 212226031Sstas;; Set when length prefix is used. 213226031Sstas(define_attr "prefix_data16" "" 214226031Sstas (if_then_else (ior (eq_attr "mode" "HI") 215226031Sstas (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF"))) 216226031Sstas (const_int 1) 217226031Sstas (const_int 0))) 218226031Sstas 219226031Sstas;; Set when string REP prefix is used. 220226031Sstas(define_attr "prefix_rep" "" 221226031Sstas (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF")) 222226031Sstas (const_int 1) 223226031Sstas (const_int 0))) 224226031Sstas 225226031Sstas;; Set when 0f opcode prefix is used. 226226031Sstas(define_attr "prefix_0f" "" 227226031Sstas (if_then_else 228226031Sstas (eq_attr "type" 229226031Sstas "imovx,setcc,icmov, 230226031Sstas sselog,sseiadd,sseishft,sseimul, 231226031Sstas sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv, 232226031Sstas mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft") 233226031Sstas (const_int 1) 234226031Sstas (const_int 0))) 235226031Sstas 236226031Sstas;; Set when modrm byte is used. 237226031Sstas(define_attr "modrm" "" 238226031Sstas (cond [(eq_attr "type" "str,cld") 239226031Sstas (const_int 0) 240226031Sstas (eq_attr "unit" "i387") 241226031Sstas (const_int 0) 242226031Sstas (and (eq_attr "type" "incdec") 243226031Sstas (ior (match_operand:SI 1 "register_operand" "") 244226031Sstas (match_operand:HI 1 "register_operand" ""))) 245226031Sstas (const_int 0) 246226031Sstas (and (eq_attr "type" "push") 247226031Sstas (not (match_operand 1 "memory_operand" ""))) 248226031Sstas (const_int 0) 249226031Sstas (and (eq_attr "type" "pop") 250226031Sstas (not (match_operand 0 "memory_operand" ""))) 251226031Sstas (const_int 0) 252226031Sstas (and (eq_attr "type" "imov") 253226031Sstas (and (match_operand 0 "register_operand" "") 254226031Sstas (match_operand 1 "immediate_operand" ""))) 255226031Sstas (const_int 0) 256226031Sstas (and (eq_attr "type" "call") 257226031Sstas (match_operand 0 "constant_call_address_operand" "")) 258226031Sstas (const_int 0) 259226031Sstas (and (eq_attr "type" "callv") 260 (match_operand 1 "constant_call_address_operand" "")) 261 (const_int 0) 262 ] 263 (const_int 1))) 264 265;; The (bounding maximum) length of an instruction in bytes. 266;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want 267;; to split it and compute proper length as for other insns. 268(define_attr "length" "" 269 (cond [(eq_attr "type" "other,multi,fistp") 270 (const_int 16) 271 (eq_attr "type" "fcmp") 272 (const_int 4) 273 (eq_attr "unit" "i387") 274 (plus (const_int 2) 275 (plus (attr "prefix_data16") 276 (attr "length_address")))] 277 (plus (plus (attr "modrm") 278 (plus (attr "prefix_0f") 279 (const_int 1))) 280 (plus (attr "prefix_rep") 281 (plus (attr "prefix_data16") 282 (plus (attr "length_immediate") 283 (attr "length_address"))))))) 284 285;; The `memory' attribute is `none' if no memory is referenced, `load' or 286;; `store' if there is a simple memory reference therein, or `unknown' 287;; if the instruction is complex. 288 289(define_attr "memory" "none,load,store,both,unknown" 290 (cond [(eq_attr "type" "other,multi,str") 291 (const_string "unknown") 292 (eq_attr "type" "lea,fcmov,fpspc,cld") 293 (const_string "none") 294 (eq_attr "type" "fistp") 295 (const_string "both") 296 (eq_attr "type" "push") 297 (if_then_else (match_operand 1 "memory_operand" "") 298 (const_string "both") 299 (const_string "store")) 300 (eq_attr "type" "pop,setcc") 301 (if_then_else (match_operand 0 "memory_operand" "") 302 (const_string "both") 303 (const_string "load")) 304 (eq_attr "type" "icmp,test,ssecmp,mmxcmp,fcmp") 305 (if_then_else (ior (match_operand 0 "memory_operand" "") 306 (match_operand 1 "memory_operand" "")) 307 (const_string "load") 308 (const_string "none")) 309 (eq_attr "type" "ibr") 310 (if_then_else (match_operand 0 "memory_operand" "") 311 (const_string "load") 312 (const_string "none")) 313 (eq_attr "type" "call") 314 (if_then_else (match_operand 0 "constant_call_address_operand" "") 315 (const_string "none") 316 (const_string "load")) 317 (eq_attr "type" "callv") 318 (if_then_else (match_operand 1 "constant_call_address_operand" "") 319 (const_string "none") 320 (const_string "load")) 321 (and (eq_attr "type" "alu1,negnot") 322 (match_operand 1 "memory_operand" "")) 323 (const_string "both") 324 (and (match_operand 0 "memory_operand" "") 325 (match_operand 1 "memory_operand" "")) 326 (const_string "both") 327 (match_operand 0 "memory_operand" "") 328 (const_string "store") 329 (match_operand 1 "memory_operand" "") 330 (const_string "load") 331 (and (eq_attr "type" 332 "!alu1,negnot, 333 imov,imovx,icmp,test, 334 fmov,fcmp,fsgn, 335 sse,ssemov,ssecmp,ssecvt, 336 mmx,mmxmov,mmxcmp,mmxcvt") 337 (match_operand 2 "memory_operand" "")) 338 (const_string "load") 339 (and (eq_attr "type" "icmov") 340 (match_operand 3 "memory_operand" "")) 341 (const_string "load") 342 ] 343 (const_string "none"))) 344 345;; Indicates if an instruction has both an immediate and a displacement. 346 347(define_attr "imm_disp" "false,true,unknown" 348 (cond [(eq_attr "type" "other,multi") 349 (const_string "unknown") 350 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1") 351 (and (match_operand 0 "memory_displacement_operand" "") 352 (match_operand 1 "immediate_operand" ""))) 353 (const_string "true") 354 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv") 355 (and (match_operand 0 "memory_displacement_operand" "") 356 (match_operand 2 "immediate_operand" ""))) 357 (const_string "true") 358 ] 359 (const_string "false"))) 360 361;; Indicates if an FP operation has an integer source. 362 363(define_attr "fp_int_src" "false,true" 364 (const_string "false")) 365 366;; Describe a user's asm statement. 367(define_asm_attributes 368 [(set_attr "length" "128") 369 (set_attr "type" "multi")]) 370 371(include "pentium.md") 372(include "ppro.md") 373(include "k6.md") 374(include "athlon.md") 375 376;; Compare instructions. 377 378;; All compare insns have expanders that save the operands away without 379;; actually generating RTL. The bCOND or sCOND (emitted immediately 380;; after the cmp) will actually emit the cmpM. 381 382(define_expand "cmpdi" 383 [(set (reg:CC 17) 384 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "") 385 (match_operand:DI 1 "x86_64_general_operand" "")))] 386 "" 387{ 388 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 389 operands[0] = force_reg (DImode, operands[0]); 390 ix86_compare_op0 = operands[0]; 391 ix86_compare_op1 = operands[1]; 392 DONE; 393}) 394 395(define_expand "cmpsi" 396 [(set (reg:CC 17) 397 (compare:CC (match_operand:SI 0 "cmpsi_operand" "") 398 (match_operand:SI 1 "general_operand" "")))] 399 "" 400{ 401 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 402 operands[0] = force_reg (SImode, operands[0]); 403 ix86_compare_op0 = operands[0]; 404 ix86_compare_op1 = operands[1]; 405 DONE; 406}) 407 408(define_expand "cmphi" 409 [(set (reg:CC 17) 410 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "") 411 (match_operand:HI 1 "general_operand" "")))] 412 "" 413{ 414 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 415 operands[0] = force_reg (HImode, operands[0]); 416 ix86_compare_op0 = operands[0]; 417 ix86_compare_op1 = operands[1]; 418 DONE; 419}) 420 421(define_expand "cmpqi" 422 [(set (reg:CC 17) 423 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "") 424 (match_operand:QI 1 "general_operand" "")))] 425 "TARGET_QIMODE_MATH" 426{ 427 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 428 operands[0] = force_reg (QImode, operands[0]); 429 ix86_compare_op0 = operands[0]; 430 ix86_compare_op1 = operands[1]; 431 DONE; 432}) 433 434(define_insn "cmpdi_ccno_1_rex64" 435 [(set (reg 17) 436 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr") 437 (match_operand:DI 1 "const0_operand" "n,n")))] 438 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" 439 "@ 440 test{q}\t{%0, %0|%0, %0} 441 cmp{q}\t{%1, %0|%0, %1}" 442 [(set_attr "type" "test,icmp") 443 (set_attr "length_immediate" "0,1") 444 (set_attr "mode" "DI")]) 445 446(define_insn "*cmpdi_minus_1_rex64" 447 [(set (reg 17) 448 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r") 449 (match_operand:DI 1 "x86_64_general_operand" "re,mr")) 450 (const_int 0)))] 451 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)" 452 "cmp{q}\t{%1, %0|%0, %1}" 453 [(set_attr "type" "icmp") 454 (set_attr "mode" "DI")]) 455 456(define_expand "cmpdi_1_rex64" 457 [(set (reg:CC 17) 458 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "") 459 (match_operand:DI 1 "general_operand" "")))] 460 "TARGET_64BIT" 461 "") 462 463(define_insn "cmpdi_1_insn_rex64" 464 [(set (reg 17) 465 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r") 466 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))] 467 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" 468 "cmp{q}\t{%1, %0|%0, %1}" 469 [(set_attr "type" "icmp") 470 (set_attr "mode" "DI")]) 471 472 473(define_insn "*cmpsi_ccno_1" 474 [(set (reg 17) 475 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr") 476 (match_operand:SI 1 "const0_operand" "n,n")))] 477 "ix86_match_ccmode (insn, CCNOmode)" 478 "@ 479 test{l}\t{%0, %0|%0, %0} 480 cmp{l}\t{%1, %0|%0, %1}" 481 [(set_attr "type" "test,icmp") 482 (set_attr "length_immediate" "0,1") 483 (set_attr "mode" "SI")]) 484 485(define_insn "*cmpsi_minus_1" 486 [(set (reg 17) 487 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r") 488 (match_operand:SI 1 "general_operand" "ri,mr")) 489 (const_int 0)))] 490 "ix86_match_ccmode (insn, CCGOCmode)" 491 "cmp{l}\t{%1, %0|%0, %1}" 492 [(set_attr "type" "icmp") 493 (set_attr "mode" "SI")]) 494 495(define_expand "cmpsi_1" 496 [(set (reg:CC 17) 497 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r") 498 (match_operand:SI 1 "general_operand" "ri,mr")))] 499 "" 500 "") 501 502(define_insn "*cmpsi_1_insn" 503 [(set (reg 17) 504 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r") 505 (match_operand:SI 1 "general_operand" "ri,mr")))] 506 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 507 && ix86_match_ccmode (insn, CCmode)" 508 "cmp{l}\t{%1, %0|%0, %1}" 509 [(set_attr "type" "icmp") 510 (set_attr "mode" "SI")]) 511 512(define_insn "*cmphi_ccno_1" 513 [(set (reg 17) 514 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr") 515 (match_operand:HI 1 "const0_operand" "n,n")))] 516 "ix86_match_ccmode (insn, CCNOmode)" 517 "@ 518 test{w}\t{%0, %0|%0, %0} 519 cmp{w}\t{%1, %0|%0, %1}" 520 [(set_attr "type" "test,icmp") 521 (set_attr "length_immediate" "0,1") 522 (set_attr "mode" "HI")]) 523 524(define_insn "*cmphi_minus_1" 525 [(set (reg 17) 526 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r") 527 (match_operand:HI 1 "general_operand" "ri,mr")) 528 (const_int 0)))] 529 "ix86_match_ccmode (insn, CCGOCmode)" 530 "cmp{w}\t{%1, %0|%0, %1}" 531 [(set_attr "type" "icmp") 532 (set_attr "mode" "HI")]) 533 534(define_insn "*cmphi_1" 535 [(set (reg 17) 536 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r") 537 (match_operand:HI 1 "general_operand" "ri,mr")))] 538 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 539 && ix86_match_ccmode (insn, CCmode)" 540 "cmp{w}\t{%1, %0|%0, %1}" 541 [(set_attr "type" "icmp") 542 (set_attr "mode" "HI")]) 543 544(define_insn "*cmpqi_ccno_1" 545 [(set (reg 17) 546 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq") 547 (match_operand:QI 1 "const0_operand" "n,n")))] 548 "ix86_match_ccmode (insn, CCNOmode)" 549 "@ 550 test{b}\t{%0, %0|%0, %0} 551 cmp{b}\t{$0, %0|%0, 0}" 552 [(set_attr "type" "test,icmp") 553 (set_attr "length_immediate" "0,1") 554 (set_attr "mode" "QI")]) 555 556(define_insn "*cmpqi_1" 557 [(set (reg 17) 558 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q") 559 (match_operand:QI 1 "general_operand" "qi,mq")))] 560 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 561 && ix86_match_ccmode (insn, CCmode)" 562 "cmp{b}\t{%1, %0|%0, %1}" 563 [(set_attr "type" "icmp") 564 (set_attr "mode" "QI")]) 565 566(define_insn "*cmpqi_minus_1" 567 [(set (reg 17) 568 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q") 569 (match_operand:QI 1 "general_operand" "qi,mq")) 570 (const_int 0)))] 571 "ix86_match_ccmode (insn, CCGOCmode)" 572 "cmp{b}\t{%1, %0|%0, %1}" 573 [(set_attr "type" "icmp") 574 (set_attr "mode" "QI")]) 575 576(define_insn "*cmpqi_ext_1" 577 [(set (reg 17) 578 (compare 579 (match_operand:QI 0 "general_operand" "Qm") 580 (subreg:QI 581 (zero_extract:SI 582 (match_operand 1 "ext_register_operand" "Q") 583 (const_int 8) 584 (const_int 8)) 0)))] 585 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" 586 "cmp{b}\t{%h1, %0|%0, %h1}" 587 [(set_attr "type" "icmp") 588 (set_attr "mode" "QI")]) 589 590(define_insn "*cmpqi_ext_1_rex64" 591 [(set (reg 17) 592 (compare 593 (match_operand:QI 0 "register_operand" "Q") 594 (subreg:QI 595 (zero_extract:SI 596 (match_operand 1 "ext_register_operand" "Q") 597 (const_int 8) 598 (const_int 8)) 0)))] 599 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" 600 "cmp{b}\t{%h1, %0|%0, %h1}" 601 [(set_attr "type" "icmp") 602 (set_attr "mode" "QI")]) 603 604(define_insn "*cmpqi_ext_2" 605 [(set (reg 17) 606 (compare 607 (subreg:QI 608 (zero_extract:SI 609 (match_operand 0 "ext_register_operand" "Q") 610 (const_int 8) 611 (const_int 8)) 0) 612 (match_operand:QI 1 "const0_operand" "n")))] 613 "ix86_match_ccmode (insn, CCNOmode)" 614 "test{b}\t%h0, %h0" 615 [(set_attr "type" "test") 616 (set_attr "length_immediate" "0") 617 (set_attr "mode" "QI")]) 618 619(define_expand "cmpqi_ext_3" 620 [(set (reg:CC 17) 621 (compare:CC 622 (subreg:QI 623 (zero_extract:SI 624 (match_operand 0 "ext_register_operand" "") 625 (const_int 8) 626 (const_int 8)) 0) 627 (match_operand:QI 1 "general_operand" "")))] 628 "" 629 "") 630 631(define_insn "cmpqi_ext_3_insn" 632 [(set (reg 17) 633 (compare 634 (subreg:QI 635 (zero_extract:SI 636 (match_operand 0 "ext_register_operand" "Q") 637 (const_int 8) 638 (const_int 8)) 0) 639 (match_operand:QI 1 "general_operand" "Qmn")))] 640 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" 641 "cmp{b}\t{%1, %h0|%h0, %1}" 642 [(set_attr "type" "icmp") 643 (set_attr "mode" "QI")]) 644 645(define_insn "cmpqi_ext_3_insn_rex64" 646 [(set (reg 17) 647 (compare 648 (subreg:QI 649 (zero_extract:SI 650 (match_operand 0 "ext_register_operand" "Q") 651 (const_int 8) 652 (const_int 8)) 0) 653 (match_operand:QI 1 "nonmemory_operand" "Qn")))] 654 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" 655 "cmp{b}\t{%1, %h0|%h0, %1}" 656 [(set_attr "type" "icmp") 657 (set_attr "mode" "QI")]) 658 659(define_insn "*cmpqi_ext_4" 660 [(set (reg 17) 661 (compare 662 (subreg:QI 663 (zero_extract:SI 664 (match_operand 0 "ext_register_operand" "Q") 665 (const_int 8) 666 (const_int 8)) 0) 667 (subreg:QI 668 (zero_extract:SI 669 (match_operand 1 "ext_register_operand" "Q") 670 (const_int 8) 671 (const_int 8)) 0)))] 672 "ix86_match_ccmode (insn, CCmode)" 673 "cmp{b}\t{%h1, %h0|%h0, %h1}" 674 [(set_attr "type" "icmp") 675 (set_attr "mode" "QI")]) 676 677;; These implement float point compares. 678;; %%% See if we can get away with VOIDmode operands on the actual insns, 679;; which would allow mix and match FP modes on the compares. Which is what 680;; the old patterns did, but with many more of them. 681 682(define_expand "cmpxf" 683 [(set (reg:CC 17) 684 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "") 685 (match_operand:XF 1 "cmp_fp_expander_operand" "")))] 686 "!TARGET_64BIT && TARGET_80387" 687{ 688 ix86_compare_op0 = operands[0]; 689 ix86_compare_op1 = operands[1]; 690 DONE; 691}) 692 693(define_expand "cmptf" 694 [(set (reg:CC 17) 695 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "") 696 (match_operand:TF 1 "cmp_fp_expander_operand" "")))] 697 "TARGET_80387" 698{ 699 ix86_compare_op0 = operands[0]; 700 ix86_compare_op1 = operands[1]; 701 DONE; 702}) 703 704(define_expand "cmpdf" 705 [(set (reg:CC 17) 706 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "") 707 (match_operand:DF 1 "cmp_fp_expander_operand" "")))] 708 "TARGET_80387 || TARGET_SSE2" 709{ 710 ix86_compare_op0 = operands[0]; 711 ix86_compare_op1 = operands[1]; 712 DONE; 713}) 714 715(define_expand "cmpsf" 716 [(set (reg:CC 17) 717 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "") 718 (match_operand:SF 1 "cmp_fp_expander_operand" "")))] 719 "TARGET_80387 || TARGET_SSE" 720{ 721 ix86_compare_op0 = operands[0]; 722 ix86_compare_op1 = operands[1]; 723 DONE; 724}) 725 726;; FP compares, step 1: 727;; Set the FP condition codes. 728;; 729;; CCFPmode compare with exceptions 730;; CCFPUmode compare with no exceptions 731 732;; %%% It is an unfortunate fact that ftst has no non-popping variant, 733;; and that fp moves clobber the condition codes, and that there is 734;; currently no way to describe this fact to reg-stack. So there are 735;; no splitters yet for this. 736 737;; %%% YIKES! This scheme does not retain a strong connection between 738;; the real compare and the ultimate cc0 user, so CC_REVERSE does not 739;; work! Only allow tos/mem with tos in op 0. 740;; 741;; Hmm, of course, this is what the actual _hardware_ does. Perhaps 742;; things aren't as bad as they sound... 743 744(define_insn "*cmpfp_0" 745 [(set (match_operand:HI 0 "register_operand" "=a") 746 (unspec:HI 747 [(compare:CCFP (match_operand 1 "register_operand" "f") 748 (match_operand 2 "const0_operand" "X"))] 749 UNSPEC_FNSTSW))] 750 "TARGET_80387 751 && FLOAT_MODE_P (GET_MODE (operands[1])) 752 && GET_MODE (operands[1]) == GET_MODE (operands[2])" 753{ 754 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 755 return "ftst\;fnstsw\t%0\;fstp\t%y0"; 756 else 757 return "ftst\;fnstsw\t%0"; 758} 759 [(set_attr "type" "multi") 760 (set_attr "mode" "unknownfp")]) 761 762;; We may not use "#" to split and emit these, since the REG_DEAD notes 763;; used to manage the reg stack popping would not be preserved. 764 765(define_insn "*cmpfp_2_sf" 766 [(set (reg:CCFP 18) 767 (compare:CCFP 768 (match_operand:SF 0 "register_operand" "f") 769 (match_operand:SF 1 "nonimmediate_operand" "fm")))] 770 "TARGET_80387" 771 "* return output_fp_compare (insn, operands, 0, 0);" 772 [(set_attr "type" "fcmp") 773 (set_attr "mode" "SF")]) 774 775(define_insn "*cmpfp_2_sf_1" 776 [(set (match_operand:HI 0 "register_operand" "=a") 777 (unspec:HI 778 [(compare:CCFP 779 (match_operand:SF 1 "register_operand" "f") 780 (match_operand:SF 2 "nonimmediate_operand" "fm"))] 781 UNSPEC_FNSTSW))] 782 "TARGET_80387" 783 "* return output_fp_compare (insn, operands, 2, 0);" 784 [(set_attr "type" "fcmp") 785 (set_attr "mode" "SF")]) 786 787(define_insn "*cmpfp_2_df" 788 [(set (reg:CCFP 18) 789 (compare:CCFP 790 (match_operand:DF 0 "register_operand" "f") 791 (match_operand:DF 1 "nonimmediate_operand" "fm")))] 792 "TARGET_80387" 793 "* return output_fp_compare (insn, operands, 0, 0);" 794 [(set_attr "type" "fcmp") 795 (set_attr "mode" "DF")]) 796 797(define_insn "*cmpfp_2_df_1" 798 [(set (match_operand:HI 0 "register_operand" "=a") 799 (unspec:HI 800 [(compare:CCFP 801 (match_operand:DF 1 "register_operand" "f") 802 (match_operand:DF 2 "nonimmediate_operand" "fm"))] 803 UNSPEC_FNSTSW))] 804 "TARGET_80387" 805 "* return output_fp_compare (insn, operands, 2, 0);" 806 [(set_attr "type" "multi") 807 (set_attr "mode" "DF")]) 808 809(define_insn "*cmpfp_2_xf" 810 [(set (reg:CCFP 18) 811 (compare:CCFP 812 (match_operand:XF 0 "register_operand" "f") 813 (match_operand:XF 1 "register_operand" "f")))] 814 "!TARGET_64BIT && TARGET_80387" 815 "* return output_fp_compare (insn, operands, 0, 0);" 816 [(set_attr "type" "fcmp") 817 (set_attr "mode" "XF")]) 818 819(define_insn "*cmpfp_2_tf" 820 [(set (reg:CCFP 18) 821 (compare:CCFP 822 (match_operand:TF 0 "register_operand" "f") 823 (match_operand:TF 1 "register_operand" "f")))] 824 "TARGET_80387" 825 "* return output_fp_compare (insn, operands, 0, 0);" 826 [(set_attr "type" "fcmp") 827 (set_attr "mode" "XF")]) 828 829(define_insn "*cmpfp_2_xf_1" 830 [(set (match_operand:HI 0 "register_operand" "=a") 831 (unspec:HI 832 [(compare:CCFP 833 (match_operand:XF 1 "register_operand" "f") 834 (match_operand:XF 2 "register_operand" "f"))] 835 UNSPEC_FNSTSW))] 836 "!TARGET_64BIT && TARGET_80387" 837 "* return output_fp_compare (insn, operands, 2, 0);" 838 [(set_attr "type" "multi") 839 (set_attr "mode" "XF")]) 840 841(define_insn "*cmpfp_2_tf_1" 842 [(set (match_operand:HI 0 "register_operand" "=a") 843 (unspec:HI 844 [(compare:CCFP 845 (match_operand:TF 1 "register_operand" "f") 846 (match_operand:TF 2 "register_operand" "f"))] 847 UNSPEC_FNSTSW))] 848 "TARGET_80387" 849 "* return output_fp_compare (insn, operands, 2, 0);" 850 [(set_attr "type" "multi") 851 (set_attr "mode" "XF")]) 852 853(define_insn "*cmpfp_2u" 854 [(set (reg:CCFPU 18) 855 (compare:CCFPU 856 (match_operand 0 "register_operand" "f") 857 (match_operand 1 "register_operand" "f")))] 858 "TARGET_80387 859 && FLOAT_MODE_P (GET_MODE (operands[0])) 860 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 861 "* return output_fp_compare (insn, operands, 0, 1);" 862 [(set_attr "type" "fcmp") 863 (set_attr "mode" "unknownfp")]) 864 865(define_insn "*cmpfp_2u_1" 866 [(set (match_operand:HI 0 "register_operand" "=a") 867 (unspec:HI 868 [(compare:CCFPU 869 (match_operand 1 "register_operand" "f") 870 (match_operand 2 "register_operand" "f"))] 871 UNSPEC_FNSTSW))] 872 "TARGET_80387 873 && FLOAT_MODE_P (GET_MODE (operands[1])) 874 && GET_MODE (operands[1]) == GET_MODE (operands[2])" 875 "* return output_fp_compare (insn, operands, 2, 1);" 876 [(set_attr "type" "multi") 877 (set_attr "mode" "unknownfp")]) 878 879;; Patterns to match the SImode-in-memory ficom instructions. 880;; 881;; %%% Play games with accepting gp registers, as otherwise we have to 882;; force them to memory during rtl generation, which is no good. We 883;; can get rid of this once we teach reload to do memory input reloads 884;; via pushes. 885 886(define_insn "*ficom_1" 887 [(set (reg:CCFP 18) 888 (compare:CCFP 889 (match_operand 0 "register_operand" "f,f") 890 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))] 891 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0])) 892 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])" 893 "#") 894 895;; Split the not-really-implemented gp register case into a 896;; push-op-pop sequence. 897;; 898;; %%% This is most efficient, but am I gonna get in trouble 899;; for separating cc0_setter and cc0_user? 900 901(define_split 902 [(set (reg:CCFP 18) 903 (compare:CCFP 904 (match_operand:SF 0 "register_operand" "") 905 (float (match_operand:SI 1 "register_operand" ""))))] 906 "0 && TARGET_80387 && reload_completed" 907 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1)) 908 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2))) 909 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) 910 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] 911 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx); 912 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);") 913 914;; FP compares, step 2 915;; Move the fpsw to ax. 916 917(define_insn "x86_fnstsw_1" 918 [(set (match_operand:HI 0 "register_operand" "=a") 919 (unspec:HI [(reg 18)] UNSPEC_FNSTSW))] 920 "TARGET_80387" 921 "fnstsw\t%0" 922 [(set_attr "length" "2") 923 (set_attr "mode" "SI") 924 (set_attr "unit" "i387") 925 (set_attr "ppro_uops" "few")]) 926 927;; FP compares, step 3 928;; Get ax into flags, general case. 929 930(define_insn "x86_sahf_1" 931 [(set (reg:CC 17) 932 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))] 933 "!TARGET_64BIT" 934 "sahf" 935 [(set_attr "length" "1") 936 (set_attr "athlon_decode" "vector") 937 (set_attr "mode" "SI") 938 (set_attr "ppro_uops" "one")]) 939 940;; Pentium Pro can do steps 1 through 3 in one go. 941 942(define_insn "*cmpfp_i" 943 [(set (reg:CCFP 17) 944 (compare:CCFP (match_operand 0 "register_operand" "f") 945 (match_operand 1 "register_operand" "f")))] 946 "TARGET_80387 && TARGET_CMOVE 947 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0])) 948 && FLOAT_MODE_P (GET_MODE (operands[0])) 949 && GET_MODE (operands[0]) == GET_MODE (operands[0])" 950 "* return output_fp_compare (insn, operands, 1, 0);" 951 [(set_attr "type" "fcmp") 952 (set_attr "mode" "unknownfp") 953 (set_attr "athlon_decode" "vector")]) 954 955(define_insn "*cmpfp_i_sse" 956 [(set (reg:CCFP 17) 957 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f") 958 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))] 959 "TARGET_80387 960 && SSE_FLOAT_MODE_P (GET_MODE (operands[0])) 961 && GET_MODE (operands[0]) == GET_MODE (operands[0])" 962 "* return output_fp_compare (insn, operands, 1, 0);" 963 [(set_attr "type" "fcmp,ssecmp") 964 (set_attr "mode" "unknownfp") 965 (set_attr "athlon_decode" "vector")]) 966 967(define_insn "*cmpfp_i_sse_only" 968 [(set (reg:CCFP 17) 969 (compare:CCFP (match_operand 0 "register_operand" "x") 970 (match_operand 1 "nonimmediate_operand" "xm")))] 971 "SSE_FLOAT_MODE_P (GET_MODE (operands[0])) 972 && GET_MODE (operands[0]) == GET_MODE (operands[0])" 973 "* return output_fp_compare (insn, operands, 1, 0);" 974 [(set_attr "type" "ssecmp") 975 (set_attr "mode" "unknownfp") 976 (set_attr "athlon_decode" "vector")]) 977 978(define_insn "*cmpfp_iu" 979 [(set (reg:CCFPU 17) 980 (compare:CCFPU (match_operand 0 "register_operand" "f") 981 (match_operand 1 "register_operand" "f")))] 982 "TARGET_80387 && TARGET_CMOVE 983 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0])) 984 && FLOAT_MODE_P (GET_MODE (operands[0])) 985 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 986 "* return output_fp_compare (insn, operands, 1, 1);" 987 [(set_attr "type" "fcmp") 988 (set_attr "mode" "unknownfp") 989 (set_attr "athlon_decode" "vector")]) 990 991(define_insn "*cmpfp_iu_sse" 992 [(set (reg:CCFPU 17) 993 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f") 994 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))] 995 "TARGET_80387 996 && SSE_FLOAT_MODE_P (GET_MODE (operands[0])) 997 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 998 "* return output_fp_compare (insn, operands, 1, 1);" 999 [(set_attr "type" "fcmp,ssecmp") 1000 (set_attr "mode" "unknownfp") 1001 (set_attr "athlon_decode" "vector")]) 1002 1003(define_insn "*cmpfp_iu_sse_only" 1004 [(set (reg:CCFPU 17) 1005 (compare:CCFPU (match_operand 0 "register_operand" "x") 1006 (match_operand 1 "nonimmediate_operand" "xm")))] 1007 "SSE_FLOAT_MODE_P (GET_MODE (operands[0])) 1008 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 1009 "* return output_fp_compare (insn, operands, 1, 1);" 1010 [(set_attr "type" "ssecmp") 1011 (set_attr "mode" "unknownfp") 1012 (set_attr "athlon_decode" "vector")]) 1013 1014;; Move instructions. 1015 1016;; General case of fullword move. 1017 1018(define_expand "movsi" 1019 [(set (match_operand:SI 0 "nonimmediate_operand" "") 1020 (match_operand:SI 1 "general_operand" ""))] 1021 "" 1022 "ix86_expand_move (SImode, operands); DONE;") 1023 1024;; Push/pop instructions. They are separate since autoinc/dec is not a 1025;; general_operand. 1026;; 1027;; %%% We don't use a post-inc memory reference because x86 is not a 1028;; general AUTO_INC_DEC host, which impacts how it is treated in flow. 1029;; Changing this impacts compiler performance on other non-AUTO_INC_DEC 1030;; targets without our curiosities, and it is just as easy to represent 1031;; this differently. 1032 1033(define_insn "*pushsi2" 1034 [(set (match_operand:SI 0 "push_operand" "=<") 1035 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))] 1036 "!TARGET_64BIT" 1037 "push{l}\t%1" 1038 [(set_attr "type" "push") 1039 (set_attr "mode" "SI")]) 1040 1041;; For 64BIT abi we always round up to 8 bytes. 1042(define_insn "*pushsi2_rex64" 1043 [(set (match_operand:SI 0 "push_operand" "=X") 1044 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))] 1045 "TARGET_64BIT" 1046 "push{q}\t%q1" 1047 [(set_attr "type" "push") 1048 (set_attr "mode" "SI")]) 1049 1050(define_insn "*pushsi2_prologue" 1051 [(set (match_operand:SI 0 "push_operand" "=<") 1052 (match_operand:SI 1 "general_no_elim_operand" "ri*m")) 1053 (clobber (mem:BLK (scratch)))] 1054 "!TARGET_64BIT" 1055 "push{l}\t%1" 1056 [(set_attr "type" "push") 1057 (set_attr "mode" "SI")]) 1058 1059(define_insn "*popsi1_epilogue" 1060 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m") 1061 (mem:SI (reg:SI 7))) 1062 (set (reg:SI 7) 1063 (plus:SI (reg:SI 7) (const_int 4))) 1064 (clobber (mem:BLK (scratch)))] 1065 "!TARGET_64BIT" 1066 "pop{l}\t%0" 1067 [(set_attr "type" "pop") 1068 (set_attr "mode" "SI")]) 1069 1070(define_insn "popsi1" 1071 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m") 1072 (mem:SI (reg:SI 7))) 1073 (set (reg:SI 7) 1074 (plus:SI (reg:SI 7) (const_int 4)))] 1075 "!TARGET_64BIT" 1076 "pop{l}\t%0" 1077 [(set_attr "type" "pop") 1078 (set_attr "mode" "SI")]) 1079 1080(define_insn "*movsi_xor" 1081 [(set (match_operand:SI 0 "register_operand" "=r") 1082 (match_operand:SI 1 "const0_operand" "i")) 1083 (clobber (reg:CC 17))] 1084 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)" 1085 "xor{l}\t{%0, %0|%0, %0}" 1086 [(set_attr "type" "alu1") 1087 (set_attr "mode" "SI") 1088 (set_attr "length_immediate" "0")]) 1089 1090(define_insn "*movsi_or" 1091 [(set (match_operand:SI 0 "register_operand" "=r") 1092 (match_operand:SI 1 "immediate_operand" "i")) 1093 (clobber (reg:CC 17))] 1094 "reload_completed && GET_CODE (operands[1]) == CONST_INT 1095 && INTVAL (operands[1]) == -1 1096 && (TARGET_PENTIUM || optimize_size)" 1097{ 1098 operands[1] = constm1_rtx; 1099 return "or{l}\t{%1, %0|%0, %1}"; 1100} 1101 [(set_attr "type" "alu1") 1102 (set_attr "mode" "SI") 1103 (set_attr "length_immediate" "1")]) 1104 1105(define_insn "*movsi_1" 1106 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!*Y,!rm") 1107 (match_operand:SI 1 "general_operand" "rinm,rin,rm,*y,*y,*Y,rm,*Y"))] 1108 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" 1109{ 1110 switch (get_attr_type (insn)) 1111 { 1112 case TYPE_SSEMOV: 1113 if (get_attr_mode (insn) == MODE_TI) 1114 return "movdqa\t{%1, %0|%0, %1}"; 1115 return "movd\t{%1, %0|%0, %1}"; 1116 1117 case TYPE_MMXMOV: 1118 if (get_attr_mode (insn) == MODE_DI) 1119 return "movq\t{%1, %0|%0, %1}"; 1120 return "movd\t{%1, %0|%0, %1}"; 1121 1122 case TYPE_LEA: 1123 return "lea{l}\t{%1, %0|%0, %1}"; 1124 1125 default: 1126 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1])) 1127 abort(); 1128 return "mov{l}\t{%1, %0|%0, %1}"; 1129 } 1130} 1131 [(set (attr "type") 1132 (cond [(eq_attr "alternative" "2,3,4") 1133 (const_string "mmxmov") 1134 (eq_attr "alternative" "5,6,7") 1135 (const_string "ssemov") 1136 (and (ne (symbol_ref "flag_pic") (const_int 0)) 1137 (match_operand:SI 1 "symbolic_operand" "")) 1138 (const_string "lea") 1139 ] 1140 (const_string "imov"))) 1141 (set_attr "mode" "SI,SI,SI,SI,DI,TI,SI,SI")]) 1142 1143;; Stores and loads of ax to arbitary constant address. 1144;; We fake an second form of instruction to force reload to load address 1145;; into register when rax is not available 1146(define_insn "*movabssi_1_rex64" 1147 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) 1148 (match_operand:SI 1 "nonmemory_operand" "a,er"))] 1149 "TARGET_64BIT && ix86_check_movabs (insn, 0)" 1150 "@ 1151 movabs{l}\t{%1, %P0|%P0, %1} 1152 mov{l}\t{%1, %a0|%a0, %1}" 1153 [(set_attr "type" "imov") 1154 (set_attr "modrm" "0,*") 1155 (set_attr "length_address" "8,0") 1156 (set_attr "length_immediate" "0,*") 1157 (set_attr "memory" "store") 1158 (set_attr "mode" "SI")]) 1159 1160(define_insn "*movabssi_2_rex64" 1161 [(set (match_operand:SI 0 "register_operand" "=a,r") 1162 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] 1163 "TARGET_64BIT && ix86_check_movabs (insn, 1)" 1164 "@ 1165 movabs{l}\t{%P1, %0|%0, %P1} 1166 mov{l}\t{%a1, %0|%0, %a1}" 1167 [(set_attr "type" "imov") 1168 (set_attr "modrm" "0,*") 1169 (set_attr "length_address" "8,0") 1170 (set_attr "length_immediate" "0") 1171 (set_attr "memory" "load") 1172 (set_attr "mode" "SI")]) 1173 1174(define_insn "*swapsi" 1175 [(set (match_operand:SI 0 "register_operand" "+r") 1176 (match_operand:SI 1 "register_operand" "+r")) 1177 (set (match_dup 1) 1178 (match_dup 0))] 1179 "" 1180 "xchg{l}\t%1, %0" 1181 [(set_attr "type" "imov") 1182 (set_attr "pent_pair" "np") 1183 (set_attr "athlon_decode" "vector") 1184 (set_attr "mode" "SI") 1185 (set_attr "modrm" "0") 1186 (set_attr "ppro_uops" "few")]) 1187 1188(define_expand "movhi" 1189 [(set (match_operand:HI 0 "nonimmediate_operand" "") 1190 (match_operand:HI 1 "general_operand" ""))] 1191 "" 1192 "ix86_expand_move (HImode, operands); DONE;") 1193 1194(define_insn "*pushhi2" 1195 [(set (match_operand:HI 0 "push_operand" "=<,<") 1196 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))] 1197 "!TARGET_64BIT" 1198 "@ 1199 push{w}\t{|WORD PTR }%1 1200 push{w}\t%1" 1201 [(set_attr "type" "push") 1202 (set_attr "mode" "HI")]) 1203 1204;; For 64BIT abi we always round up to 8 bytes. 1205(define_insn "*pushhi2_rex64" 1206 [(set (match_operand:HI 0 "push_operand" "=X") 1207 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))] 1208 "TARGET_64BIT" 1209 "push{q}\t%q1" 1210 [(set_attr "type" "push") 1211 (set_attr "mode" "QI")]) 1212 1213(define_insn "*movhi_1" 1214 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") 1215 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))] 1216 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" 1217{ 1218 switch (get_attr_type (insn)) 1219 { 1220 case TYPE_IMOVX: 1221 /* movzwl is faster than movw on p2 due to partial word stalls, 1222 though not as fast as an aligned movl. */ 1223 return "movz{wl|x}\t{%1, %k0|%k0, %1}"; 1224 default: 1225 if (get_attr_mode (insn) == MODE_SI) 1226 return "mov{l}\t{%k1, %k0|%k0, %k1}"; 1227 else 1228 return "mov{w}\t{%1, %0|%0, %1}"; 1229 } 1230} 1231 [(set (attr "type") 1232 (cond [(and (eq_attr "alternative" "0") 1233 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL") 1234 (const_int 0)) 1235 (eq (symbol_ref "TARGET_HIMODE_MATH") 1236 (const_int 0)))) 1237 (const_string "imov") 1238 (and (eq_attr "alternative" "1,2") 1239 (match_operand:HI 1 "aligned_operand" "")) 1240 (const_string "imov") 1241 (and (ne (symbol_ref "TARGET_MOVX") 1242 (const_int 0)) 1243 (eq_attr "alternative" "0,2")) 1244 (const_string "imovx") 1245 ] 1246 (const_string "imov"))) 1247 (set (attr "mode") 1248 (cond [(eq_attr "type" "imovx") 1249 (const_string "SI") 1250 (and (eq_attr "alternative" "1,2") 1251 (match_operand:HI 1 "aligned_operand" "")) 1252 (const_string "SI") 1253 (and (eq_attr "alternative" "0") 1254 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL") 1255 (const_int 0)) 1256 (eq (symbol_ref "TARGET_HIMODE_MATH") 1257 (const_int 0)))) 1258 (const_string "SI") 1259 ] 1260 (const_string "HI")))]) 1261 1262;; Stores and loads of ax to arbitary constant address. 1263;; We fake an second form of instruction to force reload to load address 1264;; into register when rax is not available 1265(define_insn "*movabshi_1_rex64" 1266 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) 1267 (match_operand:HI 1 "nonmemory_operand" "a,er"))] 1268 "TARGET_64BIT && ix86_check_movabs (insn, 0)" 1269 "@ 1270 movabs{w}\t{%1, %P0|%P0, %1} 1271 mov{w}\t{%1, %a0|%a0, %1}" 1272 [(set_attr "type" "imov") 1273 (set_attr "modrm" "0,*") 1274 (set_attr "length_address" "8,0") 1275 (set_attr "length_immediate" "0,*") 1276 (set_attr "memory" "store") 1277 (set_attr "mode" "HI")]) 1278 1279(define_insn "*movabshi_2_rex64" 1280 [(set (match_operand:HI 0 "register_operand" "=a,r") 1281 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] 1282 "TARGET_64BIT && ix86_check_movabs (insn, 1)" 1283 "@ 1284 movabs{w}\t{%P1, %0|%0, %P1} 1285 mov{w}\t{%a1, %0|%0, %a1}" 1286 [(set_attr "type" "imov") 1287 (set_attr "modrm" "0,*") 1288 (set_attr "length_address" "8,0") 1289 (set_attr "length_immediate" "0") 1290 (set_attr "memory" "load") 1291 (set_attr "mode" "HI")]) 1292 1293(define_insn "*swaphi_1" 1294 [(set (match_operand:HI 0 "register_operand" "+r") 1295 (match_operand:HI 1 "register_operand" "+r")) 1296 (set (match_dup 1) 1297 (match_dup 0))] 1298 "TARGET_PARTIAL_REG_STALL" 1299 "xchg{w}\t%1, %0" 1300 [(set_attr "type" "imov") 1301 (set_attr "pent_pair" "np") 1302 (set_attr "mode" "HI") 1303 (set_attr "modrm" "0") 1304 (set_attr "ppro_uops" "few")]) 1305 1306(define_insn "*swaphi_2" 1307 [(set (match_operand:HI 0 "register_operand" "+r") 1308 (match_operand:HI 1 "register_operand" "+r")) 1309 (set (match_dup 1) 1310 (match_dup 0))] 1311 "! TARGET_PARTIAL_REG_STALL" 1312 "xchg{l}\t%k1, %k0" 1313 [(set_attr "type" "imov") 1314 (set_attr "pent_pair" "np") 1315 (set_attr "mode" "SI") 1316 (set_attr "modrm" "0") 1317 (set_attr "ppro_uops" "few")]) 1318 1319(define_expand "movstricthi" 1320 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "")) 1321 (match_operand:HI 1 "general_operand" ""))] 1322 "! TARGET_PARTIAL_REG_STALL || optimize_size" 1323{ 1324 /* Don't generate memory->memory moves, go through a register */ 1325 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 1326 operands[1] = force_reg (HImode, operands[1]); 1327}) 1328 1329(define_insn "*movstricthi_1" 1330 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r")) 1331 (match_operand:HI 1 "general_operand" "rn,m"))] 1332 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 1333 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 1334 "mov{w}\t{%1, %0|%0, %1}" 1335 [(set_attr "type" "imov") 1336 (set_attr "mode" "HI")]) 1337 1338(define_insn "*movstricthi_xor" 1339 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) 1340 (match_operand:HI 1 "const0_operand" "i")) 1341 (clobber (reg:CC 17))] 1342 "reload_completed 1343 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)" 1344 "xor{w}\t{%0, %0|%0, %0}" 1345 [(set_attr "type" "alu1") 1346 (set_attr "mode" "HI") 1347 (set_attr "length_immediate" "0")]) 1348 1349(define_expand "movqi" 1350 [(set (match_operand:QI 0 "nonimmediate_operand" "") 1351 (match_operand:QI 1 "general_operand" ""))] 1352 "" 1353 "ix86_expand_move (QImode, operands); DONE;") 1354 1355;; emit_push_insn when it calls move_by_pieces requires an insn to 1356;; "push a byte". But actually we use pushw, which has the effect 1357;; of rounding the amount pushed up to a halfword. 1358 1359(define_insn "*pushqi2" 1360 [(set (match_operand:QI 0 "push_operand" "=X,X") 1361 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))] 1362 "!TARGET_64BIT" 1363 "@ 1364 push{w}\t{|word ptr }%1 1365 push{w}\t%w1" 1366 [(set_attr "type" "push") 1367 (set_attr "mode" "HI")]) 1368 1369;; For 64BIT abi we always round up to 8 bytes. 1370(define_insn "*pushqi2_rex64" 1371 [(set (match_operand:QI 0 "push_operand" "=X") 1372 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))] 1373 "TARGET_64BIT" 1374 "push{q}\t%q1" 1375 [(set_attr "type" "push") 1376 (set_attr "mode" "QI")]) 1377 1378;; Situation is quite tricky about when to choose full sized (SImode) move 1379;; over QImode moves. For Q_REG -> Q_REG move we use full size only for 1380;; partial register dependency machines (such as AMD Athlon), where QImode 1381;; moves issue extra dependency and for partial register stalls machines 1382;; that don't use QImode patterns (and QImode move cause stall on the next 1383;; instruction). 1384;; 1385;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial 1386;; register stall machines with, where we use QImode instructions, since 1387;; partial register stall can be caused there. Then we use movzx. 1388(define_insn "*movqi_1" 1389 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m") 1390 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))] 1391 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" 1392{ 1393 switch (get_attr_type (insn)) 1394 { 1395 case TYPE_IMOVX: 1396 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM) 1397 abort (); 1398 return "movz{bl|x}\t{%1, %k0|%k0, %1}"; 1399 default: 1400 if (get_attr_mode (insn) == MODE_SI) 1401 return "mov{l}\t{%k1, %k0|%k0, %k1}"; 1402 else 1403 return "mov{b}\t{%1, %0|%0, %1}"; 1404 } 1405} 1406 [(set (attr "type") 1407 (cond [(and (eq_attr "alternative" "3") 1408 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL") 1409 (const_int 0)) 1410 (eq (symbol_ref "TARGET_QIMODE_MATH") 1411 (const_int 0)))) 1412 (const_string "imov") 1413 (eq_attr "alternative" "3,5") 1414 (const_string "imovx") 1415 (and (ne (symbol_ref "TARGET_MOVX") 1416 (const_int 0)) 1417 (eq_attr "alternative" "2")) 1418 (const_string "imovx") 1419 ] 1420 (const_string "imov"))) 1421 (set (attr "mode") 1422 (cond [(eq_attr "alternative" "3,4,5") 1423 (const_string "SI") 1424 (eq_attr "alternative" "6") 1425 (const_string "QI") 1426 (eq_attr "type" "imovx") 1427 (const_string "SI") 1428 (and (eq_attr "type" "imov") 1429 (and (eq_attr "alternative" "0,1,2") 1430 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY") 1431 (const_int 0)))) 1432 (const_string "SI") 1433 ;; Avoid partial register stalls when not using QImode arithmetic 1434 (and (eq_attr "type" "imov") 1435 (and (eq_attr "alternative" "0,1,2") 1436 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL") 1437 (const_int 0)) 1438 (eq (symbol_ref "TARGET_QIMODE_MATH") 1439 (const_int 0))))) 1440 (const_string "SI") 1441 ] 1442 (const_string "QI")))]) 1443 1444(define_expand "reload_outqi" 1445 [(parallel [(match_operand:QI 0 "" "=m") 1446 (match_operand:QI 1 "register_operand" "r") 1447 (match_operand:QI 2 "register_operand" "=&q")])] 1448 "" 1449{ 1450 rtx op0, op1, op2; 1451 op0 = operands[0]; op1 = operands[1]; op2 = operands[2]; 1452 1453 if (reg_overlap_mentioned_p (op2, op0)) 1454 abort (); 1455 if (! q_regs_operand (op1, QImode)) 1456 { 1457 emit_insn (gen_movqi (op2, op1)); 1458 op1 = op2; 1459 } 1460 emit_insn (gen_movqi (op0, op1)); 1461 DONE; 1462}) 1463 1464(define_insn "*swapqi" 1465 [(set (match_operand:QI 0 "register_operand" "+r") 1466 (match_operand:QI 1 "register_operand" "+r")) 1467 (set (match_dup 1) 1468 (match_dup 0))] 1469 "" 1470 "xchg{b}\t%1, %0" 1471 [(set_attr "type" "imov") 1472 (set_attr "pent_pair" "np") 1473 (set_attr "mode" "QI") 1474 (set_attr "modrm" "0") 1475 (set_attr "ppro_uops" "few")]) 1476 1477(define_expand "movstrictqi" 1478 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) 1479 (match_operand:QI 1 "general_operand" ""))] 1480 "! TARGET_PARTIAL_REG_STALL || optimize_size" 1481{ 1482 /* Don't generate memory->memory moves, go through a register. */ 1483 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 1484 operands[1] = force_reg (QImode, operands[1]); 1485}) 1486 1487(define_insn "*movstrictqi_1" 1488 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) 1489 (match_operand:QI 1 "general_operand" "*qn,m"))] 1490 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 1491 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 1492 "mov{b}\t{%1, %0|%0, %1}" 1493 [(set_attr "type" "imov") 1494 (set_attr "mode" "QI")]) 1495 1496(define_insn "*movstrictqi_xor" 1497 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q")) 1498 (match_operand:QI 1 "const0_operand" "i")) 1499 (clobber (reg:CC 17))] 1500 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)" 1501 "xor{b}\t{%0, %0|%0, %0}" 1502 [(set_attr "type" "alu1") 1503 (set_attr "mode" "QI") 1504 (set_attr "length_immediate" "0")]) 1505 1506(define_insn "*movsi_extv_1" 1507 [(set (match_operand:SI 0 "register_operand" "=R") 1508 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q") 1509 (const_int 8) 1510 (const_int 8)))] 1511 "" 1512 "movs{bl|x}\t{%h1, %0|%0, %h1}" 1513 [(set_attr "type" "imovx") 1514 (set_attr "mode" "SI")]) 1515 1516(define_insn "*movhi_extv_1" 1517 [(set (match_operand:HI 0 "register_operand" "=R") 1518 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q") 1519 (const_int 8) 1520 (const_int 8)))] 1521 "" 1522 "movs{bl|x}\t{%h1, %k0|%k0, %h1}" 1523 [(set_attr "type" "imovx") 1524 (set_attr "mode" "SI")]) 1525 1526(define_insn "*movqi_extv_1" 1527 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r") 1528 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q") 1529 (const_int 8) 1530 (const_int 8)))] 1531 "!TARGET_64BIT" 1532{ 1533 switch (get_attr_type (insn)) 1534 { 1535 case TYPE_IMOVX: 1536 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}"; 1537 default: 1538 return "mov{b}\t{%h1, %0|%0, %h1}"; 1539 } 1540} 1541 [(set (attr "type") 1542 (if_then_else (and (match_operand:QI 0 "register_operand" "") 1543 (ior (not (match_operand:QI 0 "q_regs_operand" "")) 1544 (ne (symbol_ref "TARGET_MOVX") 1545 (const_int 0)))) 1546 (const_string "imovx") 1547 (const_string "imov"))) 1548 (set (attr "mode") 1549 (if_then_else (eq_attr "type" "imovx") 1550 (const_string "SI") 1551 (const_string "QI")))]) 1552 1553(define_insn "*movqi_extv_1_rex64" 1554 [(set (match_operand:QI 0 "register_operand" "=Q,?R") 1555 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q") 1556 (const_int 8) 1557 (const_int 8)))] 1558 "TARGET_64BIT" 1559{ 1560 switch (get_attr_type (insn)) 1561 { 1562 case TYPE_IMOVX: 1563 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}"; 1564 default: 1565 return "mov{b}\t{%h1, %0|%0, %h1}"; 1566 } 1567} 1568 [(set (attr "type") 1569 (if_then_else (and (match_operand:QI 0 "register_operand" "") 1570 (ior (not (match_operand:QI 0 "q_regs_operand" "")) 1571 (ne (symbol_ref "TARGET_MOVX") 1572 (const_int 0)))) 1573 (const_string "imovx") 1574 (const_string "imov"))) 1575 (set (attr "mode") 1576 (if_then_else (eq_attr "type" "imovx") 1577 (const_string "SI") 1578 (const_string "QI")))]) 1579 1580;; Stores and loads of ax to arbitary constant address. 1581;; We fake an second form of instruction to force reload to load address 1582;; into register when rax is not available 1583(define_insn "*movabsqi_1_rex64" 1584 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) 1585 (match_operand:QI 1 "nonmemory_operand" "a,er"))] 1586 "TARGET_64BIT && ix86_check_movabs (insn, 0)" 1587 "@ 1588 movabs{b}\t{%1, %P0|%P0, %1} 1589 mov{b}\t{%1, %a0|%a0, %1}" 1590 [(set_attr "type" "imov") 1591 (set_attr "modrm" "0,*") 1592 (set_attr "length_address" "8,0") 1593 (set_attr "length_immediate" "0,*") 1594 (set_attr "memory" "store") 1595 (set_attr "mode" "QI")]) 1596 1597(define_insn "*movabsqi_2_rex64" 1598 [(set (match_operand:QI 0 "register_operand" "=a,r") 1599 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] 1600 "TARGET_64BIT && ix86_check_movabs (insn, 1)" 1601 "@ 1602 movabs{b}\t{%P1, %0|%0, %P1} 1603 mov{b}\t{%a1, %0|%0, %a1}" 1604 [(set_attr "type" "imov") 1605 (set_attr "modrm" "0,*") 1606 (set_attr "length_address" "8,0") 1607 (set_attr "length_immediate" "0") 1608 (set_attr "memory" "load") 1609 (set_attr "mode" "QI")]) 1610 1611(define_insn "*movsi_extzv_1" 1612 [(set (match_operand:SI 0 "register_operand" "=R") 1613 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") 1614 (const_int 8) 1615 (const_int 8)))] 1616 "" 1617 "movz{bl|x}\t{%h1, %0|%0, %h1}" 1618 [(set_attr "type" "imovx") 1619 (set_attr "mode" "SI")]) 1620 1621(define_insn "*movqi_extzv_2" 1622 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R") 1623 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q") 1624 (const_int 8) 1625 (const_int 8)) 0))] 1626 "!TARGET_64BIT" 1627{ 1628 switch (get_attr_type (insn)) 1629 { 1630 case TYPE_IMOVX: 1631 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}"; 1632 default: 1633 return "mov{b}\t{%h1, %0|%0, %h1}"; 1634 } 1635} 1636 [(set (attr "type") 1637 (if_then_else (and (match_operand:QI 0 "register_operand" "") 1638 (ior (not (match_operand:QI 0 "q_regs_operand" "")) 1639 (ne (symbol_ref "TARGET_MOVX") 1640 (const_int 0)))) 1641 (const_string "imovx") 1642 (const_string "imov"))) 1643 (set (attr "mode") 1644 (if_then_else (eq_attr "type" "imovx") 1645 (const_string "SI") 1646 (const_string "QI")))]) 1647 1648(define_insn "*movqi_extzv_2_rex64" 1649 [(set (match_operand:QI 0 "register_operand" "=Q,?R") 1650 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q") 1651 (const_int 8) 1652 (const_int 8)) 0))] 1653 "TARGET_64BIT" 1654{ 1655 switch (get_attr_type (insn)) 1656 { 1657 case TYPE_IMOVX: 1658 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}"; 1659 default: 1660 return "mov{b}\t{%h1, %0|%0, %h1}"; 1661 } 1662} 1663 [(set (attr "type") 1664 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" "")) 1665 (ne (symbol_ref "TARGET_MOVX") 1666 (const_int 0))) 1667 (const_string "imovx") 1668 (const_string "imov"))) 1669 (set (attr "mode") 1670 (if_then_else (eq_attr "type" "imovx") 1671 (const_string "SI") 1672 (const_string "QI")))]) 1673 1674(define_insn "movsi_insv_1" 1675 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") 1676 (const_int 8) 1677 (const_int 8)) 1678 (match_operand:SI 1 "general_operand" "Qmn"))] 1679 "!TARGET_64BIT" 1680 "mov{b}\t{%b1, %h0|%h0, %b1}" 1681 [(set_attr "type" "imov") 1682 (set_attr "mode" "QI")]) 1683 1684(define_insn "*movsi_insv_1_rex64" 1685 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") 1686 (const_int 8) 1687 (const_int 8)) 1688 (match_operand:SI 1 "nonmemory_operand" "Qn"))] 1689 "TARGET_64BIT" 1690 "mov{b}\t{%b1, %h0|%h0, %b1}" 1691 [(set_attr "type" "imov") 1692 (set_attr "mode" "QI")]) 1693 1694(define_insn "*movqi_insv_2" 1695 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") 1696 (const_int 8) 1697 (const_int 8)) 1698 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q") 1699 (const_int 8)) 1700 (const_int 255)))] 1701 "" 1702 "mov{b}\t{%h1, %h0|%h0, %h1}" 1703 [(set_attr "type" "imov") 1704 (set_attr "mode" "QI")]) 1705 1706(define_expand "movdi" 1707 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1708 (match_operand:DI 1 "general_operand" ""))] 1709 "" 1710 "ix86_expand_move (DImode, operands); DONE;") 1711 1712(define_insn "*pushdi" 1713 [(set (match_operand:DI 0 "push_operand" "=<") 1714 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))] 1715 "!TARGET_64BIT" 1716 "#") 1717 1718(define_insn "pushdi2_rex64" 1719 [(set (match_operand:DI 0 "push_operand" "=<,!<") 1720 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))] 1721 "TARGET_64BIT" 1722 "@ 1723 push{q}\t%1 1724 #" 1725 [(set_attr "type" "push,multi") 1726 (set_attr "mode" "DI")]) 1727 1728;; Convert impossible pushes of immediate to existing instructions. 1729;; First try to get scratch register and go through it. In case this 1730;; fails, push sign extended lower part first and then overwrite 1731;; upper part by 32bit move. 1732(define_peephole2 1733 [(match_scratch:DI 2 "r") 1734 (set (match_operand:DI 0 "push_operand" "") 1735 (match_operand:DI 1 "immediate_operand" ""))] 1736 "TARGET_64BIT && !symbolic_operand (operands[1], DImode) 1737 && !x86_64_immediate_operand (operands[1], DImode)" 1738 [(set (match_dup 2) (match_dup 1)) 1739 (set (match_dup 0) (match_dup 2))] 1740 "") 1741 1742;; We need to define this as both peepholer and splitter for case 1743;; peephole2 pass is not run. 1744(define_peephole2 1745 [(set (match_operand:DI 0 "push_operand" "") 1746 (match_operand:DI 1 "immediate_operand" ""))] 1747 "TARGET_64BIT && !symbolic_operand (operands[1], DImode) 1748 && !x86_64_immediate_operand (operands[1], DImode) && 1" 1749 [(set (match_dup 0) (match_dup 1)) 1750 (set (match_dup 2) (match_dup 3))] 1751 "split_di (operands + 1, 1, operands + 2, operands + 3); 1752 operands[1] = gen_lowpart (DImode, operands[2]); 1753 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx, 1754 GEN_INT (4))); 1755 ") 1756 1757(define_split 1758 [(set (match_operand:DI 0 "push_operand" "") 1759 (match_operand:DI 1 "immediate_operand" ""))] 1760 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2)) 1761 && !symbolic_operand (operands[1], DImode) 1762 && !x86_64_immediate_operand (operands[1], DImode)" 1763 [(set (match_dup 0) (match_dup 1)) 1764 (set (match_dup 2) (match_dup 3))] 1765 "split_di (operands + 1, 1, operands + 2, operands + 3); 1766 operands[1] = gen_lowpart (DImode, operands[2]); 1767 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx, 1768 GEN_INT (4))); 1769 ") 1770 1771(define_insn "*pushdi2_prologue_rex64" 1772 [(set (match_operand:DI 0 "push_operand" "=<") 1773 (match_operand:DI 1 "general_no_elim_operand" "re*m")) 1774 (clobber (mem:BLK (scratch)))] 1775 "TARGET_64BIT" 1776 "push{q}\t%1" 1777 [(set_attr "type" "push") 1778 (set_attr "mode" "DI")]) 1779 1780(define_insn "*popdi1_epilogue_rex64" 1781 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m") 1782 (mem:DI (reg:DI 7))) 1783 (set (reg:DI 7) 1784 (plus:DI (reg:DI 7) (const_int 8))) 1785 (clobber (mem:BLK (scratch)))] 1786 "TARGET_64BIT" 1787 "pop{q}\t%0" 1788 [(set_attr "type" "pop") 1789 (set_attr "mode" "DI")]) 1790 1791(define_insn "popdi1" 1792 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m") 1793 (mem:DI (reg:DI 7))) 1794 (set (reg:DI 7) 1795 (plus:DI (reg:DI 7) (const_int 8)))] 1796 "TARGET_64BIT" 1797 "pop{q}\t%0" 1798 [(set_attr "type" "pop") 1799 (set_attr "mode" "DI")]) 1800 1801(define_insn "*movdi_xor_rex64" 1802 [(set (match_operand:DI 0 "register_operand" "=r") 1803 (match_operand:DI 1 "const0_operand" "i")) 1804 (clobber (reg:CC 17))] 1805 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size) 1806 && reload_completed" 1807 "xor{l}\t{%k0, %k0|%k0, %k0}" 1808 [(set_attr "type" "alu1") 1809 (set_attr "mode" "SI") 1810 (set_attr "length_immediate" "0")]) 1811 1812(define_insn "*movdi_or_rex64" 1813 [(set (match_operand:DI 0 "register_operand" "=r") 1814 (match_operand:DI 1 "const_int_operand" "i")) 1815 (clobber (reg:CC 17))] 1816 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size) 1817 && reload_completed 1818 && GET_CODE (operands[1]) == CONST_INT 1819 && INTVAL (operands[1]) == -1" 1820{ 1821 operands[1] = constm1_rtx; 1822 return "or{q}\t{%1, %0|%0, %1}"; 1823} 1824 [(set_attr "type" "alu1") 1825 (set_attr "mode" "DI") 1826 (set_attr "length_immediate" "1")]) 1827 1828(define_insn "*movdi_2" 1829 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y") 1830 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))] 1831 "!TARGET_64BIT 1832 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 1833 "@ 1834 # 1835 # 1836 movq\t{%1, %0|%0, %1} 1837 movq\t{%1, %0|%0, %1} 1838 movq\t{%1, %0|%0, %1} 1839 movdqa\t{%1, %0|%0, %1} 1840 movq\t{%1, %0|%0, %1}" 1841 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov") 1842 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")]) 1843 1844(define_split 1845 [(set (match_operand:DI 0 "push_operand" "") 1846 (match_operand:DI 1 "general_operand" ""))] 1847 "!TARGET_64BIT && reload_completed 1848 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))" 1849 [(const_int 0)] 1850 "ix86_split_long_move (operands); DONE;") 1851 1852;; %%% This multiword shite has got to go. 1853(define_split 1854 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1855 (match_operand:DI 1 "general_operand" ""))] 1856 "!TARGET_64BIT && reload_completed 1857 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0])) 1858 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))" 1859 [(const_int 0)] 1860 "ix86_split_long_move (operands); DONE;") 1861 1862(define_insn "*movdi_1_rex64" 1863 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y") 1864 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))] 1865 "TARGET_64BIT 1866 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 1867{ 1868 switch (get_attr_type (insn)) 1869 { 1870 case TYPE_SSEMOV: 1871 if (register_operand (operands[0], DImode) 1872 && register_operand (operands[1], DImode)) 1873 return "movdqa\t{%1, %0|%0, %1}"; 1874 /* FALLTHRU */ 1875 case TYPE_MMXMOV: 1876 return "movq\t{%1, %0|%0, %1}"; 1877 case TYPE_MULTI: 1878 return "#"; 1879 case TYPE_LEA: 1880 return "lea{q}\t{%a1, %0|%0, %a1}"; 1881 default: 1882 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1])) 1883 abort (); 1884 if (get_attr_mode (insn) == MODE_SI) 1885 return "mov{l}\t{%k1, %k0|%k0, %k1}"; 1886 else if (which_alternative == 2) 1887 return "movabs{q}\t{%1, %0|%0, %1}"; 1888 else 1889 return "mov{q}\t{%1, %0|%0, %1}"; 1890 } 1891} 1892 [(set (attr "type") 1893 (cond [(eq_attr "alternative" "5,6") 1894 (const_string "mmxmov") 1895 (eq_attr "alternative" "7,8,9") 1896 (const_string "ssemov") 1897 (eq_attr "alternative" "4") 1898 (const_string "multi") 1899 (and (ne (symbol_ref "flag_pic") (const_int 0)) 1900 (match_operand:DI 1 "symbolic_operand" "")) 1901 (const_string "lea") 1902 ] 1903 (const_string "imov"))) 1904 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*") 1905 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*") 1906 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")]) 1907 1908;; Stores and loads of ax to arbitary constant address. 1909;; We fake an second form of instruction to force reload to load address 1910;; into register when rax is not available 1911(define_insn "*movabsdi_1_rex64" 1912 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) 1913 (match_operand:DI 1 "nonmemory_operand" "a,er"))] 1914 "TARGET_64BIT && ix86_check_movabs (insn, 0)" 1915 "@ 1916 movabs{q}\t{%1, %P0|%P0, %1} 1917 mov{q}\t{%1, %a0|%a0, %1}" 1918 [(set_attr "type" "imov") 1919 (set_attr "modrm" "0,*") 1920 (set_attr "length_address" "8,0") 1921 (set_attr "length_immediate" "0,*") 1922 (set_attr "memory" "store") 1923 (set_attr "mode" "DI")]) 1924 1925(define_insn "*movabsdi_2_rex64" 1926 [(set (match_operand:DI 0 "register_operand" "=a,r") 1927 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] 1928 "TARGET_64BIT && ix86_check_movabs (insn, 1)" 1929 "@ 1930 movabs{q}\t{%P1, %0|%0, %P1} 1931 mov{q}\t{%a1, %0|%0, %a1}" 1932 [(set_attr "type" "imov") 1933 (set_attr "modrm" "0,*") 1934 (set_attr "length_address" "8,0") 1935 (set_attr "length_immediate" "0") 1936 (set_attr "memory" "load") 1937 (set_attr "mode" "DI")]) 1938 1939;; Convert impossible stores of immediate to existing instructions. 1940;; First try to get scratch register and go through it. In case this 1941;; fails, move by 32bit parts. 1942(define_peephole2 1943 [(match_scratch:DI 2 "r") 1944 (set (match_operand:DI 0 "memory_operand" "") 1945 (match_operand:DI 1 "immediate_operand" ""))] 1946 "TARGET_64BIT && !symbolic_operand (operands[1], DImode) 1947 && !x86_64_immediate_operand (operands[1], DImode)" 1948 [(set (match_dup 2) (match_dup 1)) 1949 (set (match_dup 0) (match_dup 2))] 1950 "") 1951 1952;; We need to define this as both peepholer and splitter for case 1953;; peephole2 pass is not run. 1954(define_peephole2 1955 [(set (match_operand:DI 0 "memory_operand" "") 1956 (match_operand:DI 1 "immediate_operand" ""))] 1957 "TARGET_64BIT && !symbolic_operand (operands[1], DImode) 1958 && !x86_64_immediate_operand (operands[1], DImode) && 1" 1959 [(set (match_dup 2) (match_dup 3)) 1960 (set (match_dup 4) (match_dup 5))] 1961 "split_di (operands, 2, operands + 2, operands + 4);") 1962 1963(define_split 1964 [(set (match_operand:DI 0 "memory_operand" "") 1965 (match_operand:DI 1 "immediate_operand" ""))] 1966 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2)) 1967 && !symbolic_operand (operands[1], DImode) 1968 && !x86_64_immediate_operand (operands[1], DImode)" 1969 [(set (match_dup 2) (match_dup 3)) 1970 (set (match_dup 4) (match_dup 5))] 1971 "split_di (operands, 2, operands + 2, operands + 4);") 1972 1973(define_insn "*swapdi_rex64" 1974 [(set (match_operand:DI 0 "register_operand" "+r") 1975 (match_operand:DI 1 "register_operand" "+r")) 1976 (set (match_dup 1) 1977 (match_dup 0))] 1978 "TARGET_64BIT" 1979 "xchg{q}\t%1, %0" 1980 [(set_attr "type" "imov") 1981 (set_attr "pent_pair" "np") 1982 (set_attr "athlon_decode" "vector") 1983 (set_attr "mode" "DI") 1984 (set_attr "modrm" "0") 1985 (set_attr "ppro_uops" "few")]) 1986 1987 1988(define_expand "movsf" 1989 [(set (match_operand:SF 0 "nonimmediate_operand" "") 1990 (match_operand:SF 1 "general_operand" ""))] 1991 "" 1992 "ix86_expand_move (SFmode, operands); DONE;") 1993 1994(define_insn "*pushsf" 1995 [(set (match_operand:SF 0 "push_operand" "=<,<,<") 1996 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))] 1997 "!TARGET_64BIT" 1998{ 1999 switch (which_alternative) 2000 { 2001 case 0: 2002 /* %%% We loose REG_DEAD notes for controling pops if we split late. */ 2003 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx); 2004 operands[2] = stack_pointer_rtx; 2005 operands[3] = GEN_INT (4); 2006 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2007 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; 2008 else 2009 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; 2010 2011 case 1: 2012 return "push{l}\t%1"; 2013 case 2: 2014 return "#"; 2015 2016 default: 2017 abort (); 2018 } 2019} 2020 [(set_attr "type" "multi,push,multi") 2021 (set_attr "mode" "SF,SI,SF")]) 2022 2023(define_insn "*pushsf_rex64" 2024 [(set (match_operand:SF 0 "push_operand" "=X,X,X") 2025 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))] 2026 "TARGET_64BIT" 2027{ 2028 switch (which_alternative) 2029 { 2030 case 0: 2031 /* %%% We loose REG_DEAD notes for controling pops if we split late. */ 2032 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx); 2033 operands[2] = stack_pointer_rtx; 2034 operands[3] = GEN_INT (8); 2035 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2036 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; 2037 else 2038 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; 2039 2040 case 1: 2041 return "push{q}\t%q1"; 2042 2043 case 2: 2044 return "#"; 2045 2046 default: 2047 abort (); 2048 } 2049} 2050 [(set_attr "type" "multi,push,multi") 2051 (set_attr "mode" "SF,DI,SF")]) 2052 2053(define_split 2054 [(set (match_operand:SF 0 "push_operand" "") 2055 (match_operand:SF 1 "memory_operand" ""))] 2056 "reload_completed 2057 && GET_CODE (operands[1]) == MEM 2058 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF 2059 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))" 2060 [(set (match_dup 0) 2061 (match_dup 1))] 2062 "operands[1] = get_pool_constant (XEXP (operands[1], 0));") 2063 2064 2065;; %%% Kill this when call knows how to work this out. 2066(define_split 2067 [(set (match_operand:SF 0 "push_operand" "") 2068 (match_operand:SF 1 "any_fp_register_operand" ""))] 2069 "!TARGET_64BIT" 2070 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) 2071 (set (mem:SF (reg:SI 7)) (match_dup 1))]) 2072 2073(define_split 2074 [(set (match_operand:SF 0 "push_operand" "") 2075 (match_operand:SF 1 "any_fp_register_operand" ""))] 2076 "TARGET_64BIT" 2077 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) 2078 (set (mem:SF (reg:DI 7)) (match_dup 1))]) 2079 2080(define_insn "*movsf_1" 2081 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y") 2082 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))] 2083 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 2084 && (reload_in_progress || reload_completed 2085 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) 2086 || GET_CODE (operands[1]) != CONST_DOUBLE 2087 || memory_operand (operands[0], SFmode))" 2088{ 2089 switch (which_alternative) 2090 { 2091 case 0: 2092 if (REG_P (operands[1]) 2093 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2094 return "fstp\t%y0"; 2095 else if (STACK_TOP_P (operands[0])) 2096 return "fld%z1\t%y1"; 2097 else 2098 return "fst\t%y0"; 2099 2100 case 1: 2101 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2102 return "fstp%z0\t%y0"; 2103 else 2104 return "fst%z0\t%y0"; 2105 2106 case 2: 2107 switch (standard_80387_constant_p (operands[1])) 2108 { 2109 case 1: 2110 return "fldz"; 2111 case 2: 2112 return "fld1"; 2113 } 2114 abort(); 2115 2116 case 3: 2117 case 4: 2118 return "mov{l}\t{%1, %0|%0, %1}"; 2119 case 5: 2120 if (TARGET_SSE2 && !TARGET_ATHLON) 2121 return "pxor\t%0, %0"; 2122 else 2123 return "xorps\t%0, %0"; 2124 case 6: 2125 if (TARGET_PARTIAL_REG_DEPENDENCY) 2126 return "movaps\t{%1, %0|%0, %1}"; 2127 else 2128 return "movss\t{%1, %0|%0, %1}"; 2129 case 7: 2130 case 8: 2131 return "movss\t{%1, %0|%0, %1}"; 2132 2133 case 9: 2134 case 10: 2135 return "movd\t{%1, %0|%0, %1}"; 2136 2137 case 11: 2138 return "movq\t{%1, %0|%0, %1}"; 2139 2140 default: 2141 abort(); 2142 } 2143} 2144 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov") 2145 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")]) 2146 2147(define_insn "*swapsf" 2148 [(set (match_operand:SF 0 "register_operand" "+f") 2149 (match_operand:SF 1 "register_operand" "+f")) 2150 (set (match_dup 1) 2151 (match_dup 0))] 2152 "reload_completed || !TARGET_SSE" 2153{ 2154 if (STACK_TOP_P (operands[0])) 2155 return "fxch\t%1"; 2156 else 2157 return "fxch\t%0"; 2158} 2159 [(set_attr "type" "fxch") 2160 (set_attr "mode" "SF")]) 2161 2162(define_expand "movdf" 2163 [(set (match_operand:DF 0 "nonimmediate_operand" "") 2164 (match_operand:DF 1 "general_operand" ""))] 2165 "" 2166 "ix86_expand_move (DFmode, operands); DONE;") 2167 2168;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size. 2169;; Size of pushdf using integer insturctions is 2+2*memory operand size 2170;; On the average, pushdf using integers can be still shorter. Allow this 2171;; pattern for optimize_size too. 2172 2173(define_insn "*pushdf_nointeger" 2174 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<") 2175 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))] 2176 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES" 2177{ 2178 switch (which_alternative) 2179 { 2180 case 0: 2181 /* %%% We loose REG_DEAD notes for controling pops if we split late. */ 2182 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx); 2183 operands[2] = stack_pointer_rtx; 2184 operands[3] = GEN_INT (8); 2185 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2186 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; 2187 else 2188 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; 2189 2190 case 1: 2191 case 2: 2192 case 3: 2193 return "#"; 2194 2195 default: 2196 abort (); 2197 } 2198} 2199 [(set_attr "type" "multi") 2200 (set_attr "mode" "DF,SI,SI,DF")]) 2201 2202(define_insn "*pushdf_integer" 2203 [(set (match_operand:DF 0 "push_operand" "=<,<,<") 2204 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))] 2205 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES" 2206{ 2207 switch (which_alternative) 2208 { 2209 case 0: 2210 /* %%% We loose REG_DEAD notes for controling pops if we split late. */ 2211 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx); 2212 operands[2] = stack_pointer_rtx; 2213 operands[3] = GEN_INT (8); 2214 if (TARGET_64BIT) 2215 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2216 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; 2217 else 2218 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; 2219 else 2220 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2221 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; 2222 else 2223 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; 2224 2225 2226 case 1: 2227 case 2: 2228 return "#"; 2229 2230 default: 2231 abort (); 2232 } 2233} 2234 [(set_attr "type" "multi") 2235 (set_attr "mode" "DF,SI,DF")]) 2236 2237;; %%% Kill this when call knows how to work this out. 2238(define_split 2239 [(set (match_operand:DF 0 "push_operand" "") 2240 (match_operand:DF 1 "any_fp_register_operand" ""))] 2241 "!TARGET_64BIT && reload_completed" 2242 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) 2243 (set (mem:DF (reg:SI 7)) (match_dup 1))] 2244 "") 2245 2246(define_split 2247 [(set (match_operand:DF 0 "push_operand" "") 2248 (match_operand:DF 1 "any_fp_register_operand" ""))] 2249 "TARGET_64BIT && reload_completed" 2250 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) 2251 (set (mem:DF (reg:DI 7)) (match_dup 1))] 2252 "") 2253 2254(define_split 2255 [(set (match_operand:DF 0 "push_operand" "") 2256 (match_operand:DF 1 "general_operand" ""))] 2257 "reload_completed" 2258 [(const_int 0)] 2259 "ix86_split_long_move (operands); DONE;") 2260 2261;; Moving is usually shorter when only FP registers are used. This separate 2262;; movdf pattern avoids the use of integer registers for FP operations 2263;; when optimizing for size. 2264 2265(define_insn "*movdf_nointeger" 2266 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m") 2267 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))] 2268 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 2269 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES) 2270 && (reload_in_progress || reload_completed 2271 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) 2272 || GET_CODE (operands[1]) != CONST_DOUBLE 2273 || memory_operand (operands[0], DFmode))" 2274{ 2275 switch (which_alternative) 2276 { 2277 case 0: 2278 if (REG_P (operands[1]) 2279 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2280 return "fstp\t%y0"; 2281 else if (STACK_TOP_P (operands[0])) 2282 return "fld%z1\t%y1"; 2283 else 2284 return "fst\t%y0"; 2285 2286 case 1: 2287 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2288 return "fstp%z0\t%y0"; 2289 else 2290 return "fst%z0\t%y0"; 2291 2292 case 2: 2293 switch (standard_80387_constant_p (operands[1])) 2294 { 2295 case 1: 2296 return "fldz"; 2297 case 2: 2298 return "fld1"; 2299 } 2300 abort(); 2301 2302 case 3: 2303 case 4: 2304 return "#"; 2305 case 5: 2306 if (TARGET_ATHLON) 2307 return "xorpd\t%0, %0"; 2308 else 2309 return "pxor\t%0, %0"; 2310 case 6: 2311 if (TARGET_PARTIAL_REG_DEPENDENCY) 2312 return "movapd\t{%1, %0|%0, %1}"; 2313 else 2314 return "movsd\t{%1, %0|%0, %1}"; 2315 case 7: 2316 case 8: 2317 return "movsd\t{%1, %0|%0, %1}"; 2318 2319 default: 2320 abort(); 2321 } 2322} 2323 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov") 2324 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")]) 2325 2326(define_insn "*movdf_integer" 2327 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m") 2328 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))] 2329 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 2330 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES 2331 && (reload_in_progress || reload_completed 2332 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) 2333 || GET_CODE (operands[1]) != CONST_DOUBLE 2334 || memory_operand (operands[0], DFmode))" 2335{ 2336 switch (which_alternative) 2337 { 2338 case 0: 2339 if (REG_P (operands[1]) 2340 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2341 return "fstp\t%y0"; 2342 else if (STACK_TOP_P (operands[0])) 2343 return "fld%z1\t%y1"; 2344 else 2345 return "fst\t%y0"; 2346 2347 case 1: 2348 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2349 return "fstp%z0\t%y0"; 2350 else 2351 return "fst%z0\t%y0"; 2352 2353 case 2: 2354 switch (standard_80387_constant_p (operands[1])) 2355 { 2356 case 1: 2357 return "fldz"; 2358 case 2: 2359 return "fld1"; 2360 } 2361 abort(); 2362 2363 case 3: 2364 case 4: 2365 return "#"; 2366 2367 case 5: 2368 if (TARGET_ATHLON) 2369 return "xorpd\t%0, %0"; 2370 else 2371 return "pxor\t%0, %0"; 2372 case 6: 2373 if (TARGET_PARTIAL_REG_DEPENDENCY) 2374 return "movapd\t{%1, %0|%0, %1}"; 2375 else 2376 return "movsd\t{%1, %0|%0, %1}"; 2377 case 7: 2378 case 8: 2379 return "movsd\t{%1, %0|%0, %1}"; 2380 2381 default: 2382 abort(); 2383 } 2384} 2385 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov") 2386 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")]) 2387 2388(define_split 2389 [(set (match_operand:DF 0 "nonimmediate_operand" "") 2390 (match_operand:DF 1 "general_operand" ""))] 2391 "reload_completed 2392 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 2393 && ! (ANY_FP_REG_P (operands[0]) || 2394 (GET_CODE (operands[0]) == SUBREG 2395 && ANY_FP_REG_P (SUBREG_REG (operands[0])))) 2396 && ! (ANY_FP_REG_P (operands[1]) || 2397 (GET_CODE (operands[1]) == SUBREG 2398 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))" 2399 [(const_int 0)] 2400 "ix86_split_long_move (operands); DONE;") 2401 2402(define_insn "*swapdf" 2403 [(set (match_operand:DF 0 "register_operand" "+f") 2404 (match_operand:DF 1 "register_operand" "+f")) 2405 (set (match_dup 1) 2406 (match_dup 0))] 2407 "reload_completed || !TARGET_SSE2" 2408{ 2409 if (STACK_TOP_P (operands[0])) 2410 return "fxch\t%1"; 2411 else 2412 return "fxch\t%0"; 2413} 2414 [(set_attr "type" "fxch") 2415 (set_attr "mode" "DF")]) 2416 2417(define_expand "movxf" 2418 [(set (match_operand:XF 0 "nonimmediate_operand" "") 2419 (match_operand:XF 1 "general_operand" ""))] 2420 "!TARGET_64BIT" 2421 "ix86_expand_move (XFmode, operands); DONE;") 2422 2423(define_expand "movtf" 2424 [(set (match_operand:TF 0 "nonimmediate_operand" "") 2425 (match_operand:TF 1 "general_operand" ""))] 2426 "" 2427 "ix86_expand_move (TFmode, operands); DONE;") 2428 2429;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size. 2430;; Size of pushdf using integer insturctions is 3+3*memory operand size 2431;; Pushing using integer instructions is longer except for constants 2432;; and direct memory references. 2433;; (assuming that any given constant is pushed only once, but this ought to be 2434;; handled elsewhere). 2435 2436(define_insn "*pushxf_nointeger" 2437 [(set (match_operand:XF 0 "push_operand" "=X,X,X") 2438 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))] 2439 "!TARGET_64BIT && optimize_size" 2440{ 2441 switch (which_alternative) 2442 { 2443 case 0: 2444 /* %%% We loose REG_DEAD notes for controling pops if we split late. */ 2445 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx); 2446 operands[2] = stack_pointer_rtx; 2447 operands[3] = GEN_INT (12); 2448 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2449 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; 2450 else 2451 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; 2452 2453 case 1: 2454 case 2: 2455 return "#"; 2456 2457 default: 2458 abort (); 2459 } 2460} 2461 [(set_attr "type" "multi") 2462 (set_attr "mode" "XF,SI,SI")]) 2463 2464(define_insn "*pushtf_nointeger" 2465 [(set (match_operand:TF 0 "push_operand" "=<,<,<") 2466 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))] 2467 "optimize_size" 2468{ 2469 switch (which_alternative) 2470 { 2471 case 0: 2472 /* %%% We loose REG_DEAD notes for controling pops if we split late. */ 2473 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx); 2474 operands[2] = stack_pointer_rtx; 2475 operands[3] = GEN_INT (16); 2476 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2477 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; 2478 else 2479 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; 2480 2481 case 1: 2482 case 2: 2483 return "#"; 2484 2485 default: 2486 abort (); 2487 } 2488} 2489 [(set_attr "type" "multi") 2490 (set_attr "mode" "XF,SI,SI")]) 2491 2492(define_insn "*pushxf_integer" 2493 [(set (match_operand:XF 0 "push_operand" "=<,<") 2494 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))] 2495 "!TARGET_64BIT && !optimize_size" 2496{ 2497 switch (which_alternative) 2498 { 2499 case 0: 2500 /* %%% We loose REG_DEAD notes for controling pops if we split late. */ 2501 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx); 2502 operands[2] = stack_pointer_rtx; 2503 operands[3] = GEN_INT (12); 2504 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2505 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; 2506 else 2507 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; 2508 2509 case 1: 2510 return "#"; 2511 2512 default: 2513 abort (); 2514 } 2515} 2516 [(set_attr "type" "multi") 2517 (set_attr "mode" "XF,SI")]) 2518 2519(define_insn "*pushtf_integer" 2520 [(set (match_operand:TF 0 "push_operand" "=<,<") 2521 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))] 2522 "!optimize_size" 2523{ 2524 switch (which_alternative) 2525 { 2526 case 0: 2527 /* %%% We loose REG_DEAD notes for controling pops if we split late. */ 2528 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx); 2529 operands[2] = stack_pointer_rtx; 2530 operands[3] = GEN_INT (16); 2531 if (TARGET_64BIT) 2532 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2533 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; 2534 else 2535 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; 2536 else 2537 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2538 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; 2539 else 2540 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; 2541 2542 case 1: 2543 return "#"; 2544 2545 default: 2546 abort (); 2547 } 2548} 2549 [(set_attr "type" "multi") 2550 (set_attr "mode" "XF,SI")]) 2551 2552(define_split 2553 [(set (match_operand 0 "push_operand" "") 2554 (match_operand 1 "general_operand" ""))] 2555 "reload_completed 2556 && (GET_MODE (operands[0]) == XFmode 2557 || GET_MODE (operands[0]) == TFmode 2558 || GET_MODE (operands[0]) == DFmode) 2559 && !ANY_FP_REG_P (operands[1])" 2560 [(const_int 0)] 2561 "ix86_split_long_move (operands); DONE;") 2562 2563(define_split 2564 [(set (match_operand:XF 0 "push_operand" "") 2565 (match_operand:XF 1 "any_fp_register_operand" ""))] 2566 "!TARGET_64BIT" 2567 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12))) 2568 (set (mem:XF (reg:SI 7)) (match_dup 1))]) 2569 2570(define_split 2571 [(set (match_operand:TF 0 "push_operand" "") 2572 (match_operand:TF 1 "any_fp_register_operand" ""))] 2573 "!TARGET_64BIT" 2574 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) 2575 (set (mem:TF (reg:SI 7)) (match_dup 1))]) 2576 2577(define_split 2578 [(set (match_operand:TF 0 "push_operand" "") 2579 (match_operand:TF 1 "any_fp_register_operand" ""))] 2580 "TARGET_64BIT" 2581 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) 2582 (set (mem:TF (reg:DI 7)) (match_dup 1))]) 2583 2584;; Do not use integer registers when optimizing for size 2585(define_insn "*movxf_nointeger" 2586 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o") 2587 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))] 2588 "!TARGET_64BIT 2589 && optimize_size 2590 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 2591 && (reload_in_progress || reload_completed 2592 || GET_CODE (operands[1]) != CONST_DOUBLE 2593 || memory_operand (operands[0], XFmode))" 2594{ 2595 switch (which_alternative) 2596 { 2597 case 0: 2598 if (REG_P (operands[1]) 2599 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2600 return "fstp\t%y0"; 2601 else if (STACK_TOP_P (operands[0])) 2602 return "fld%z1\t%y1"; 2603 else 2604 return "fst\t%y0"; 2605 2606 case 1: 2607 /* There is no non-popping store to memory for XFmode. So if 2608 we need one, follow the store with a load. */ 2609 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2610 return "fstp%z0\t%y0\;fld%z0\t%y0"; 2611 else 2612 return "fstp%z0\t%y0"; 2613 2614 case 2: 2615 switch (standard_80387_constant_p (operands[1])) 2616 { 2617 case 1: 2618 return "fldz"; 2619 case 2: 2620 return "fld1"; 2621 } 2622 break; 2623 2624 case 3: case 4: 2625 return "#"; 2626 } 2627 abort(); 2628} 2629 [(set_attr "type" "fmov,fmov,fmov,multi,multi") 2630 (set_attr "mode" "XF,XF,XF,SI,SI")]) 2631 2632(define_insn "*movtf_nointeger" 2633 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o") 2634 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))] 2635 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 2636 && optimize_size 2637 && (reload_in_progress || reload_completed 2638 || GET_CODE (operands[1]) != CONST_DOUBLE 2639 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) 2640 || memory_operand (operands[0], TFmode))" 2641{ 2642 switch (which_alternative) 2643 { 2644 case 0: 2645 if (REG_P (operands[1]) 2646 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2647 return "fstp\t%y0"; 2648 else if (STACK_TOP_P (operands[0])) 2649 return "fld%z1\t%y1"; 2650 else 2651 return "fst\t%y0"; 2652 2653 case 1: 2654 /* There is no non-popping store to memory for XFmode. So if 2655 we need one, follow the store with a load. */ 2656 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2657 return "fstp%z0\t%y0\;fld%z0\t%y0"; 2658 else 2659 return "fstp%z0\t%y0"; 2660 2661 case 2: 2662 switch (standard_80387_constant_p (operands[1])) 2663 { 2664 case 1: 2665 return "fldz"; 2666 case 2: 2667 return "fld1"; 2668 } 2669 break; 2670 2671 case 3: case 4: 2672 return "#"; 2673 } 2674 abort(); 2675} 2676 [(set_attr "type" "fmov,fmov,fmov,multi,multi") 2677 (set_attr "mode" "XF,XF,XF,SI,SI")]) 2678 2679(define_insn "*movxf_integer" 2680 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o") 2681 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))] 2682 "!TARGET_64BIT 2683 && !optimize_size 2684 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 2685 && (reload_in_progress || reload_completed 2686 || GET_CODE (operands[1]) != CONST_DOUBLE 2687 || memory_operand (operands[0], XFmode))" 2688{ 2689 switch (which_alternative) 2690 { 2691 case 0: 2692 if (REG_P (operands[1]) 2693 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2694 return "fstp\t%y0"; 2695 else if (STACK_TOP_P (operands[0])) 2696 return "fld%z1\t%y1"; 2697 else 2698 return "fst\t%y0"; 2699 2700 case 1: 2701 /* There is no non-popping store to memory for XFmode. So if 2702 we need one, follow the store with a load. */ 2703 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2704 return "fstp%z0\t%y0\;fld%z0\t%y0"; 2705 else 2706 return "fstp%z0\t%y0"; 2707 2708 case 2: 2709 switch (standard_80387_constant_p (operands[1])) 2710 { 2711 case 1: 2712 return "fldz"; 2713 case 2: 2714 return "fld1"; 2715 } 2716 break; 2717 2718 case 3: case 4: 2719 return "#"; 2720 } 2721 abort(); 2722} 2723 [(set_attr "type" "fmov,fmov,fmov,multi,multi") 2724 (set_attr "mode" "XF,XF,XF,SI,SI")]) 2725 2726(define_insn "*movtf_integer" 2727 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o") 2728 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))] 2729 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 2730 && !optimize_size 2731 && (reload_in_progress || reload_completed 2732 || GET_CODE (operands[1]) != CONST_DOUBLE 2733 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) 2734 || memory_operand (operands[0], TFmode))" 2735{ 2736 switch (which_alternative) 2737 { 2738 case 0: 2739 if (REG_P (operands[1]) 2740 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2741 return "fstp\t%y0"; 2742 else if (STACK_TOP_P (operands[0])) 2743 return "fld%z1\t%y1"; 2744 else 2745 return "fst\t%y0"; 2746 2747 case 1: 2748 /* There is no non-popping store to memory for XFmode. So if 2749 we need one, follow the store with a load. */ 2750 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 2751 return "fstp%z0\t%y0\;fld%z0\t%y0"; 2752 else 2753 return "fstp%z0\t%y0"; 2754 2755 case 2: 2756 switch (standard_80387_constant_p (operands[1])) 2757 { 2758 case 1: 2759 return "fldz"; 2760 case 2: 2761 return "fld1"; 2762 } 2763 break; 2764 2765 case 3: case 4: 2766 return "#"; 2767 } 2768 abort(); 2769} 2770 [(set_attr "type" "fmov,fmov,fmov,multi,multi") 2771 (set_attr "mode" "XF,XF,XF,SI,SI")]) 2772 2773(define_split 2774 [(set (match_operand 0 "nonimmediate_operand" "") 2775 (match_operand 1 "general_operand" ""))] 2776 "reload_completed 2777 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 2778 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode) 2779 && ! (ANY_FP_REG_P (operands[0]) || 2780 (GET_CODE (operands[0]) == SUBREG 2781 && ANY_FP_REG_P (SUBREG_REG (operands[0])))) 2782 && ! (ANY_FP_REG_P (operands[1]) || 2783 (GET_CODE (operands[1]) == SUBREG 2784 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))" 2785 [(const_int 0)] 2786 "ix86_split_long_move (operands); DONE;") 2787 2788(define_split 2789 [(set (match_operand 0 "register_operand" "") 2790 (match_operand 1 "memory_operand" ""))] 2791 "reload_completed 2792 && GET_CODE (operands[1]) == MEM 2793 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode 2794 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode) 2795 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF 2796 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)) 2797 && (!(SSE_REG_P (operands[0]) || 2798 (GET_CODE (operands[0]) == SUBREG 2799 && SSE_REG_P (SUBREG_REG (operands[0])))) 2800 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0)))) 2801 && (!(FP_REG_P (operands[0]) || 2802 (GET_CODE (operands[0]) == SUBREG 2803 && FP_REG_P (SUBREG_REG (operands[0])))) 2804 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))" 2805 [(set (match_dup 0) 2806 (match_dup 1))] 2807 "operands[1] = get_pool_constant (XEXP (operands[1], 0));") 2808 2809(define_insn "swapxf" 2810 [(set (match_operand:XF 0 "register_operand" "+f") 2811 (match_operand:XF 1 "register_operand" "+f")) 2812 (set (match_dup 1) 2813 (match_dup 0))] 2814 "" 2815{ 2816 if (STACK_TOP_P (operands[0])) 2817 return "fxch\t%1"; 2818 else 2819 return "fxch\t%0"; 2820} 2821 [(set_attr "type" "fxch") 2822 (set_attr "mode" "XF")]) 2823 2824(define_insn "swaptf" 2825 [(set (match_operand:TF 0 "register_operand" "+f") 2826 (match_operand:TF 1 "register_operand" "+f")) 2827 (set (match_dup 1) 2828 (match_dup 0))] 2829 "" 2830{ 2831 if (STACK_TOP_P (operands[0])) 2832 return "fxch\t%1"; 2833 else 2834 return "fxch\t%0"; 2835} 2836 [(set_attr "type" "fxch") 2837 (set_attr "mode" "XF")]) 2838 2839;; Zero extension instructions 2840 2841(define_expand "zero_extendhisi2" 2842 [(set (match_operand:SI 0 "register_operand" "") 2843 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] 2844 "" 2845{ 2846 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) 2847 { 2848 operands[1] = force_reg (HImode, operands[1]); 2849 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1])); 2850 DONE; 2851 } 2852}) 2853 2854(define_insn "zero_extendhisi2_and" 2855 [(set (match_operand:SI 0 "register_operand" "=r") 2856 (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) 2857 (clobber (reg:CC 17))] 2858 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" 2859 "#" 2860 [(set_attr "type" "alu1") 2861 (set_attr "mode" "SI")]) 2862 2863(define_split 2864 [(set (match_operand:SI 0 "register_operand" "") 2865 (zero_extend:SI (match_operand:HI 1 "register_operand" ""))) 2866 (clobber (reg:CC 17))] 2867 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" 2868 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535))) 2869 (clobber (reg:CC 17))])] 2870 "") 2871 2872(define_insn "*zero_extendhisi2_movzwl" 2873 [(set (match_operand:SI 0 "register_operand" "=r") 2874 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] 2875 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" 2876 "movz{wl|x}\t{%1, %0|%0, %1}" 2877 [(set_attr "type" "imovx") 2878 (set_attr "mode" "SI")]) 2879 2880(define_expand "zero_extendqihi2" 2881 [(parallel 2882 [(set (match_operand:HI 0 "register_operand" "") 2883 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) 2884 (clobber (reg:CC 17))])] 2885 "" 2886 "") 2887 2888(define_insn "*zero_extendqihi2_and" 2889 [(set (match_operand:HI 0 "register_operand" "=r,?&q") 2890 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm"))) 2891 (clobber (reg:CC 17))] 2892 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" 2893 "#" 2894 [(set_attr "type" "alu1") 2895 (set_attr "mode" "HI")]) 2896 2897(define_insn "*zero_extendqihi2_movzbw_and" 2898 [(set (match_operand:HI 0 "register_operand" "=r,r") 2899 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0"))) 2900 (clobber (reg:CC 17))] 2901 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" 2902 "#" 2903 [(set_attr "type" "imovx,alu1") 2904 (set_attr "mode" "HI")]) 2905 2906(define_insn "*zero_extendqihi2_movzbw" 2907 [(set (match_operand:HI 0 "register_operand" "=r") 2908 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))] 2909 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed" 2910 "movz{bw|x}\t{%1, %0|%0, %1}" 2911 [(set_attr "type" "imovx") 2912 (set_attr "mode" "HI")]) 2913 2914;; For the movzbw case strip only the clobber 2915(define_split 2916 [(set (match_operand:HI 0 "register_operand" "") 2917 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) 2918 (clobber (reg:CC 17))] 2919 "reload_completed 2920 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) 2921 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))" 2922 [(set (match_operand:HI 0 "register_operand" "") 2923 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]) 2924 2925;; When source and destination does not overlap, clear destination 2926;; first and then do the movb 2927(define_split 2928 [(set (match_operand:HI 0 "register_operand" "") 2929 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) 2930 (clobber (reg:CC 17))] 2931 "reload_completed 2932 && ANY_QI_REG_P (operands[0]) 2933 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) 2934 && !reg_overlap_mentioned_p (operands[0], operands[1])" 2935 [(set (match_dup 0) (const_int 0)) 2936 (set (strict_low_part (match_dup 2)) (match_dup 1))] 2937 "operands[2] = gen_lowpart (QImode, operands[0]);") 2938 2939;; Rest is handled by single and. 2940(define_split 2941 [(set (match_operand:HI 0 "register_operand" "") 2942 (zero_extend:HI (match_operand:QI 1 "register_operand" ""))) 2943 (clobber (reg:CC 17))] 2944 "reload_completed 2945 && true_regnum (operands[0]) == true_regnum (operands[1])" 2946 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255))) 2947 (clobber (reg:CC 17))])] 2948 "") 2949 2950(define_expand "zero_extendqisi2" 2951 [(parallel 2952 [(set (match_operand:SI 0 "register_operand" "") 2953 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) 2954 (clobber (reg:CC 17))])] 2955 "" 2956 "") 2957 2958(define_insn "*zero_extendqisi2_and" 2959 [(set (match_operand:SI 0 "register_operand" "=r,?&q") 2960 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm"))) 2961 (clobber (reg:CC 17))] 2962 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" 2963 "#" 2964 [(set_attr "type" "alu1") 2965 (set_attr "mode" "SI")]) 2966 2967(define_insn "*zero_extendqisi2_movzbw_and" 2968 [(set (match_operand:SI 0 "register_operand" "=r,r") 2969 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0"))) 2970 (clobber (reg:CC 17))] 2971 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" 2972 "#" 2973 [(set_attr "type" "imovx,alu1") 2974 (set_attr "mode" "SI")]) 2975 2976(define_insn "*zero_extendqisi2_movzbw" 2977 [(set (match_operand:SI 0 "register_operand" "=r") 2978 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))] 2979 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed" 2980 "movz{bl|x}\t{%1, %0|%0, %1}" 2981 [(set_attr "type" "imovx") 2982 (set_attr "mode" "SI")]) 2983 2984;; For the movzbl case strip only the clobber 2985(define_split 2986 [(set (match_operand:SI 0 "register_operand" "") 2987 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) 2988 (clobber (reg:CC 17))] 2989 "reload_completed 2990 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) 2991 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))" 2992 [(set (match_dup 0) 2993 (zero_extend:SI (match_dup 1)))]) 2994 2995;; When source and destination does not overlap, clear destination 2996;; first and then do the movb 2997(define_split 2998 [(set (match_operand:SI 0 "register_operand" "") 2999 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) 3000 (clobber (reg:CC 17))] 3001 "reload_completed 3002 && ANY_QI_REG_P (operands[0]) 3003 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM) 3004 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) 3005 && !reg_overlap_mentioned_p (operands[0], operands[1])" 3006 [(set (match_dup 0) (const_int 0)) 3007 (set (strict_low_part (match_dup 2)) (match_dup 1))] 3008 "operands[2] = gen_lowpart (QImode, operands[0]);") 3009 3010;; Rest is handled by single and. 3011(define_split 3012 [(set (match_operand:SI 0 "register_operand" "") 3013 (zero_extend:SI (match_operand:QI 1 "register_operand" ""))) 3014 (clobber (reg:CC 17))] 3015 "reload_completed 3016 && true_regnum (operands[0]) == true_regnum (operands[1])" 3017 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255))) 3018 (clobber (reg:CC 17))])] 3019 "") 3020 3021;; %%% Kill me once multi-word ops are sane. 3022(define_expand "zero_extendsidi2" 3023 [(set (match_operand:DI 0 "register_operand" "=r") 3024 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))] 3025 "" 3026 "if (!TARGET_64BIT) 3027 { 3028 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1])); 3029 DONE; 3030 } 3031 ") 3032 3033(define_insn "zero_extendsidi2_32" 3034 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o") 3035 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r"))) 3036 (clobber (reg:CC 17))] 3037 "!TARGET_64BIT" 3038 "#" 3039 [(set_attr "mode" "SI")]) 3040 3041(define_insn "zero_extendsidi2_rex64" 3042 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") 3043 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))] 3044 "TARGET_64BIT" 3045 "@ 3046 mov\t{%k1, %k0|%k0, %k1} 3047 #" 3048 [(set_attr "type" "imovx,imov") 3049 (set_attr "mode" "SI,DI")]) 3050 3051(define_split 3052 [(set (match_operand:DI 0 "memory_operand" "") 3053 (zero_extend:DI (match_dup 0)))] 3054 "TARGET_64BIT" 3055 [(set (match_dup 4) (const_int 0))] 3056 "split_di (&operands[0], 1, &operands[3], &operands[4]);") 3057 3058(define_split 3059 [(set (match_operand:DI 0 "register_operand" "") 3060 (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) 3061 (clobber (reg:CC 17))] 3062 "!TARGET_64BIT && reload_completed 3063 && true_regnum (operands[0]) == true_regnum (operands[1])" 3064 [(set (match_dup 4) (const_int 0))] 3065 "split_di (&operands[0], 1, &operands[3], &operands[4]);") 3066 3067(define_split 3068 [(set (match_operand:DI 0 "nonimmediate_operand" "") 3069 (zero_extend:DI (match_operand:SI 1 "general_operand" ""))) 3070 (clobber (reg:CC 17))] 3071 "!TARGET_64BIT && reload_completed" 3072 [(set (match_dup 3) (match_dup 1)) 3073 (set (match_dup 4) (const_int 0))] 3074 "split_di (&operands[0], 1, &operands[3], &operands[4]);") 3075 3076(define_insn "zero_extendhidi2" 3077 [(set (match_operand:DI 0 "register_operand" "=r,r") 3078 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] 3079 "TARGET_64BIT" 3080 "@ 3081 movz{wl|x}\t{%1, %k0|%k0, %1} 3082 movz{wq|x}\t{%1, %0|%0, %1}" 3083 [(set_attr "type" "imovx") 3084 (set_attr "mode" "SI,DI")]) 3085 3086(define_insn "zero_extendqidi2" 3087 [(set (match_operand:DI 0 "register_operand" "=r,r") 3088 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))] 3089 "TARGET_64BIT" 3090 "@ 3091 movz{bl|x}\t{%1, %k0|%k0, %1} 3092 movz{bq|x}\t{%1, %0|%0, %1}" 3093 [(set_attr "type" "imovx") 3094 (set_attr "mode" "SI,DI")]) 3095 3096;; Sign extension instructions 3097 3098(define_expand "extendsidi2" 3099 [(parallel [(set (match_operand:DI 0 "register_operand" "") 3100 (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) 3101 (clobber (reg:CC 17)) 3102 (clobber (match_scratch:SI 2 ""))])] 3103 "" 3104{ 3105 if (TARGET_64BIT) 3106 { 3107 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1])); 3108 DONE; 3109 } 3110}) 3111 3112(define_insn "*extendsidi2_1" 3113 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o") 3114 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r"))) 3115 (clobber (reg:CC 17)) 3116 (clobber (match_scratch:SI 2 "=X,X,X,&r"))] 3117 "!TARGET_64BIT" 3118 "#") 3119 3120(define_insn "extendsidi2_rex64" 3121 [(set (match_operand:DI 0 "register_operand" "=*a,r") 3122 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))] 3123 "TARGET_64BIT" 3124 "@ 3125 {cltq|cdqe} 3126 movs{lq|x}\t{%1,%0|%0, %1}" 3127 [(set_attr "type" "imovx") 3128 (set_attr "mode" "DI") 3129 (set_attr "prefix_0f" "0") 3130 (set_attr "modrm" "0,1")]) 3131 3132(define_insn "extendhidi2" 3133 [(set (match_operand:DI 0 "register_operand" "=r") 3134 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))] 3135 "TARGET_64BIT" 3136 "movs{wq|x}\t{%1,%0|%0, %1}" 3137 [(set_attr "type" "imovx") 3138 (set_attr "mode" "DI")]) 3139 3140(define_insn "extendqidi2" 3141 [(set (match_operand:DI 0 "register_operand" "=r") 3142 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))] 3143 "TARGET_64BIT" 3144 "movs{bq|x}\t{%1,%0|%0, %1}" 3145 [(set_attr "type" "imovx") 3146 (set_attr "mode" "DI")]) 3147 3148;; Extend to memory case when source register does die. 3149(define_split 3150 [(set (match_operand:DI 0 "memory_operand" "") 3151 (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) 3152 (clobber (reg:CC 17)) 3153 (clobber (match_operand:SI 2 "register_operand" ""))] 3154 "(reload_completed 3155 && dead_or_set_p (insn, operands[1]) 3156 && !reg_mentioned_p (operands[1], operands[0]))" 3157 [(set (match_dup 3) (match_dup 1)) 3158 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31))) 3159 (clobber (reg:CC 17))]) 3160 (set (match_dup 4) (match_dup 1))] 3161 "split_di (&operands[0], 1, &operands[3], &operands[4]);") 3162 3163;; Extend to memory case when source register does not die. 3164(define_split 3165 [(set (match_operand:DI 0 "memory_operand" "") 3166 (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) 3167 (clobber (reg:CC 17)) 3168 (clobber (match_operand:SI 2 "register_operand" ""))] 3169 "reload_completed" 3170 [(const_int 0)] 3171{ 3172 split_di (&operands[0], 1, &operands[3], &operands[4]); 3173 3174 emit_move_insn (operands[3], operands[1]); 3175 3176 /* Generate a cltd if possible and doing so it profitable. */ 3177 if (true_regnum (operands[1]) == 0 3178 && true_regnum (operands[2]) == 1 3179 && (optimize_size || TARGET_USE_CLTD)) 3180 { 3181 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31))); 3182 } 3183 else 3184 { 3185 emit_move_insn (operands[2], operands[1]); 3186 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31))); 3187 } 3188 emit_move_insn (operands[4], operands[2]); 3189 DONE; 3190}) 3191 3192;; Extend to register case. Optimize case where source and destination 3193;; registers match and cases where we can use cltd. 3194(define_split 3195 [(set (match_operand:DI 0 "register_operand" "") 3196 (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) 3197 (clobber (reg:CC 17)) 3198 (clobber (match_scratch:SI 2 ""))] 3199 "reload_completed" 3200 [(const_int 0)] 3201{ 3202 split_di (&operands[0], 1, &operands[3], &operands[4]); 3203 3204 if (true_regnum (operands[3]) != true_regnum (operands[1])) 3205 emit_move_insn (operands[3], operands[1]); 3206 3207 /* Generate a cltd if possible and doing so it profitable. */ 3208 if (true_regnum (operands[3]) == 0 3209 && (optimize_size || TARGET_USE_CLTD)) 3210 { 3211 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31))); 3212 DONE; 3213 } 3214 3215 if (true_regnum (operands[4]) != true_regnum (operands[1])) 3216 emit_move_insn (operands[4], operands[1]); 3217 3218 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31))); 3219 DONE; 3220}) 3221 3222(define_insn "extendhisi2" 3223 [(set (match_operand:SI 0 "register_operand" "=*a,r") 3224 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))] 3225 "" 3226{ 3227 switch (get_attr_prefix_0f (insn)) 3228 { 3229 case 0: 3230 return "{cwtl|cwde}"; 3231 default: 3232 return "movs{wl|x}\t{%1,%0|%0, %1}"; 3233 } 3234} 3235 [(set_attr "type" "imovx") 3236 (set_attr "mode" "SI") 3237 (set (attr "prefix_0f") 3238 ;; movsx is short decodable while cwtl is vector decoded. 3239 (if_then_else (and (eq_attr "cpu" "!k6") 3240 (eq_attr "alternative" "0")) 3241 (const_string "0") 3242 (const_string "1"))) 3243 (set (attr "modrm") 3244 (if_then_else (eq_attr "prefix_0f" "0") 3245 (const_string "0") 3246 (const_string "1")))]) 3247 3248(define_insn "*extendhisi2_zext" 3249 [(set (match_operand:DI 0 "register_operand" "=*a,r") 3250 (zero_extend:DI 3251 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))] 3252 "TARGET_64BIT" 3253{ 3254 switch (get_attr_prefix_0f (insn)) 3255 { 3256 case 0: 3257 return "{cwtl|cwde}"; 3258 default: 3259 return "movs{wl|x}\t{%1,%k0|%k0, %1}"; 3260 } 3261} 3262 [(set_attr "type" "imovx") 3263 (set_attr "mode" "SI") 3264 (set (attr "prefix_0f") 3265 ;; movsx is short decodable while cwtl is vector decoded. 3266 (if_then_else (and (eq_attr "cpu" "!k6") 3267 (eq_attr "alternative" "0")) 3268 (const_string "0") 3269 (const_string "1"))) 3270 (set (attr "modrm") 3271 (if_then_else (eq_attr "prefix_0f" "0") 3272 (const_string "0") 3273 (const_string "1")))]) 3274 3275(define_insn "extendqihi2" 3276 [(set (match_operand:HI 0 "register_operand" "=*a,r") 3277 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))] 3278 "" 3279{ 3280 switch (get_attr_prefix_0f (insn)) 3281 { 3282 case 0: 3283 return "{cbtw|cbw}"; 3284 default: 3285 return "movs{bw|x}\t{%1,%0|%0, %1}"; 3286 } 3287} 3288 [(set_attr "type" "imovx") 3289 (set_attr "mode" "HI") 3290 (set (attr "prefix_0f") 3291 ;; movsx is short decodable while cwtl is vector decoded. 3292 (if_then_else (and (eq_attr "cpu" "!k6") 3293 (eq_attr "alternative" "0")) 3294 (const_string "0") 3295 (const_string "1"))) 3296 (set (attr "modrm") 3297 (if_then_else (eq_attr "prefix_0f" "0") 3298 (const_string "0") 3299 (const_string "1")))]) 3300 3301(define_insn "extendqisi2" 3302 [(set (match_operand:SI 0 "register_operand" "=r") 3303 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))] 3304 "" 3305 "movs{bl|x}\t{%1,%0|%0, %1}" 3306 [(set_attr "type" "imovx") 3307 (set_attr "mode" "SI")]) 3308 3309(define_insn "*extendqisi2_zext" 3310 [(set (match_operand:DI 0 "register_operand" "=r") 3311 (zero_extend:DI 3312 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))] 3313 "TARGET_64BIT" 3314 "movs{bl|x}\t{%1,%k0|%k0, %1}" 3315 [(set_attr "type" "imovx") 3316 (set_attr "mode" "SI")]) 3317 3318;; Conversions between float and double. 3319 3320;; These are all no-ops in the model used for the 80387. So just 3321;; emit moves. 3322 3323;; %%% Kill these when call knows how to work out a DFmode push earlier. 3324(define_insn "*dummy_extendsfdf2" 3325 [(set (match_operand:DF 0 "push_operand" "=<") 3326 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))] 3327 "0" 3328 "#") 3329 3330(define_split 3331 [(set (match_operand:DF 0 "push_operand" "") 3332 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))] 3333 "!TARGET_64BIT" 3334 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) 3335 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))]) 3336 3337(define_split 3338 [(set (match_operand:DF 0 "push_operand" "") 3339 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))] 3340 "TARGET_64BIT" 3341 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) 3342 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))]) 3343 3344(define_insn "*dummy_extendsfxf2" 3345 [(set (match_operand:XF 0 "push_operand" "=<") 3346 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))] 3347 "0" 3348 "#") 3349 3350(define_split 3351 [(set (match_operand:XF 0 "push_operand" "") 3352 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))] 3353 "!TARGET_64BIT" 3354 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12))) 3355 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))]) 3356 3357(define_insn "*dummy_extendsftf2" 3358 [(set (match_operand:TF 0 "push_operand" "=<") 3359 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))] 3360 "0" 3361 "#") 3362 3363(define_split 3364 [(set (match_operand:TF 0 "push_operand" "") 3365 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))] 3366 "!TARGET_64BIT" 3367 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) 3368 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))]) 3369 3370(define_split 3371 [(set (match_operand:TF 0 "push_operand" "") 3372 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))] 3373 "TARGET_64BIT" 3374 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) 3375 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))]) 3376 3377(define_insn "*dummy_extenddfxf2" 3378 [(set (match_operand:XF 0 "push_operand" "=<") 3379 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))] 3380 "0" 3381 "#") 3382 3383(define_split 3384 [(set (match_operand:XF 0 "push_operand" "") 3385 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))] 3386 "!TARGET_64BIT" 3387 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12))) 3388 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))]) 3389 3390(define_insn "*dummy_extenddftf2" 3391 [(set (match_operand:TF 0 "push_operand" "=<") 3392 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))] 3393 "0" 3394 "#") 3395 3396(define_split 3397 [(set (match_operand:TF 0 "push_operand" "") 3398 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))] 3399 "!TARGET_64BIT" 3400 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) 3401 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))]) 3402 3403(define_split 3404 [(set (match_operand:TF 0 "push_operand" "") 3405 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))] 3406 "TARGET_64BIT" 3407 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) 3408 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))]) 3409 3410(define_expand "extendsfdf2" 3411 [(set (match_operand:DF 0 "nonimmediate_operand" "") 3412 (float_extend:DF (match_operand:SF 1 "general_operand" "")))] 3413 "TARGET_80387 || TARGET_SSE2" 3414{ 3415 /* ??? Needed for compress_float_constant since all fp constants 3416 are LEGITIMATE_CONSTANT_P. */ 3417 if (GET_CODE (operands[1]) == CONST_DOUBLE) 3418 operands[1] = validize_mem (force_const_mem (SFmode, operands[1])); 3419 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 3420 operands[1] = force_reg (SFmode, operands[1]); 3421}) 3422 3423(define_insn "*extendsfdf2_1" 3424 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f") 3425 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))] 3426 "(TARGET_80387 || TARGET_SSE2) 3427 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 3428{ 3429 switch (which_alternative) 3430 { 3431 case 0: 3432 if (REG_P (operands[1]) 3433 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3434 return "fstp\t%y0"; 3435 else if (STACK_TOP_P (operands[0])) 3436 return "fld%z1\t%y1"; 3437 else 3438 return "fst\t%y0"; 3439 3440 case 1: 3441 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3442 return "fstp%z0\t%y0"; 3443 3444 else 3445 return "fst%z0\t%y0"; 3446 case 2: 3447 return "cvtss2sd\t{%1, %0|%0, %1}"; 3448 3449 default: 3450 abort (); 3451 } 3452} 3453 [(set_attr "type" "fmov,fmov,ssecvt") 3454 (set_attr "mode" "SF,XF,DF")]) 3455 3456(define_insn "*extendsfdf2_1_sse_only" 3457 [(set (match_operand:DF 0 "register_operand" "=Y") 3458 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))] 3459 "!TARGET_80387 && TARGET_SSE2 3460 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 3461 "cvtss2sd\t{%1, %0|%0, %1}" 3462 [(set_attr "type" "ssecvt") 3463 (set_attr "mode" "DF")]) 3464 3465(define_expand "extendsfxf2" 3466 [(set (match_operand:XF 0 "nonimmediate_operand" "") 3467 (float_extend:XF (match_operand:SF 1 "general_operand" "")))] 3468 "!TARGET_64BIT && TARGET_80387" 3469{ 3470 /* ??? Needed for compress_float_constant since all fp constants 3471 are LEGITIMATE_CONSTANT_P. */ 3472 if (GET_CODE (operands[1]) == CONST_DOUBLE) 3473 operands[1] = validize_mem (force_const_mem (SFmode, operands[1])); 3474 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 3475 operands[1] = force_reg (SFmode, operands[1]); 3476}) 3477 3478(define_insn "*extendsfxf2_1" 3479 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m") 3480 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))] 3481 "!TARGET_64BIT && TARGET_80387 3482 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 3483{ 3484 switch (which_alternative) 3485 { 3486 case 0: 3487 if (REG_P (operands[1]) 3488 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3489 return "fstp\t%y0"; 3490 else if (STACK_TOP_P (operands[0])) 3491 return "fld%z1\t%y1"; 3492 else 3493 return "fst\t%y0"; 3494 3495 case 1: 3496 /* There is no non-popping store to memory for XFmode. So if 3497 we need one, follow the store with a load. */ 3498 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3499 return "fstp%z0\t%y0\n\tfld%z0\t%y0"; 3500 else 3501 return "fstp%z0\t%y0"; 3502 3503 default: 3504 abort (); 3505 } 3506} 3507 [(set_attr "type" "fmov") 3508 (set_attr "mode" "SF,XF")]) 3509 3510(define_expand "extendsftf2" 3511 [(set (match_operand:TF 0 "nonimmediate_operand" "") 3512 (float_extend:TF (match_operand:SF 1 "general_operand" "")))] 3513 "TARGET_80387" 3514{ 3515 /* ??? Needed for compress_float_constant since all fp constants 3516 are LEGITIMATE_CONSTANT_P. */ 3517 if (GET_CODE (operands[1]) == CONST_DOUBLE) 3518 operands[1] = validize_mem (force_const_mem (SFmode, operands[1])); 3519 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 3520 operands[1] = force_reg (SFmode, operands[1]); 3521}) 3522 3523(define_insn "*extendsftf2_1" 3524 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m") 3525 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))] 3526 "TARGET_80387 3527 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 3528{ 3529 switch (which_alternative) 3530 { 3531 case 0: 3532 if (REG_P (operands[1]) 3533 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3534 return "fstp\t%y0"; 3535 else if (STACK_TOP_P (operands[0])) 3536 return "fld%z1\t%y1"; 3537 else 3538 return "fst\t%y0"; 3539 3540 case 1: 3541 /* There is no non-popping store to memory for XFmode. So if 3542 we need one, follow the store with a load. */ 3543 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3544 return "fstp%z0\t%y0\n\tfld%z0\t%y0"; 3545 else 3546 return "fstp%z0\t%y0"; 3547 3548 default: 3549 abort (); 3550 } 3551} 3552 [(set_attr "type" "fmov") 3553 (set_attr "mode" "SF,XF")]) 3554 3555(define_expand "extenddfxf2" 3556 [(set (match_operand:XF 0 "nonimmediate_operand" "") 3557 (float_extend:XF (match_operand:DF 1 "general_operand" "")))] 3558 "!TARGET_64BIT && TARGET_80387" 3559{ 3560 /* ??? Needed for compress_float_constant since all fp constants 3561 are LEGITIMATE_CONSTANT_P. */ 3562 if (GET_CODE (operands[1]) == CONST_DOUBLE) 3563 operands[1] = validize_mem (force_const_mem (DFmode, operands[1])); 3564 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 3565 operands[1] = force_reg (DFmode, operands[1]); 3566}) 3567 3568(define_insn "*extenddfxf2_1" 3569 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m") 3570 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))] 3571 "!TARGET_64BIT && TARGET_80387 3572 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 3573{ 3574 switch (which_alternative) 3575 { 3576 case 0: 3577 if (REG_P (operands[1]) 3578 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3579 return "fstp\t%y0"; 3580 else if (STACK_TOP_P (operands[0])) 3581 return "fld%z1\t%y1"; 3582 else 3583 return "fst\t%y0"; 3584 3585 case 1: 3586 /* There is no non-popping store to memory for XFmode. So if 3587 we need one, follow the store with a load. */ 3588 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3589 return "fstp%z0\t%y0\n\tfld%z0\t%y0"; 3590 else 3591 return "fstp%z0\t%y0"; 3592 3593 default: 3594 abort (); 3595 } 3596} 3597 [(set_attr "type" "fmov") 3598 (set_attr "mode" "DF,XF")]) 3599 3600(define_expand "extenddftf2" 3601 [(set (match_operand:TF 0 "nonimmediate_operand" "") 3602 (float_extend:TF (match_operand:DF 1 "general_operand" "")))] 3603 "TARGET_80387" 3604{ 3605 /* ??? Needed for compress_float_constant since all fp constants 3606 are LEGITIMATE_CONSTANT_P. */ 3607 if (GET_CODE (operands[1]) == CONST_DOUBLE) 3608 operands[1] = validize_mem (force_const_mem (DFmode, operands[1])); 3609 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 3610 operands[1] = force_reg (DFmode, operands[1]); 3611}) 3612 3613(define_insn "*extenddftf2_1" 3614 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m") 3615 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))] 3616 "TARGET_80387 3617 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 3618{ 3619 switch (which_alternative) 3620 { 3621 case 0: 3622 if (REG_P (operands[1]) 3623 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3624 return "fstp\t%y0"; 3625 else if (STACK_TOP_P (operands[0])) 3626 return "fld%z1\t%y1"; 3627 else 3628 return "fst\t%y0"; 3629 3630 case 1: 3631 /* There is no non-popping store to memory for XFmode. So if 3632 we need one, follow the store with a load. */ 3633 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3634 return "fstp%z0\t%y0\n\tfld%z0\t%y0"; 3635 else 3636 return "fstp%z0\t%y0"; 3637 3638 default: 3639 abort (); 3640 } 3641} 3642 [(set_attr "type" "fmov") 3643 (set_attr "mode" "DF,XF")]) 3644 3645;; %%% This seems bad bad news. 3646;; This cannot output into an f-reg because there is no way to be sure 3647;; of truncating in that case. Otherwise this is just like a simple move 3648;; insn. So we pretend we can output to a reg in order to get better 3649;; register preferencing, but we really use a stack slot. 3650 3651(define_expand "truncdfsf2" 3652 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") 3653 (float_truncate:SF 3654 (match_operand:DF 1 "register_operand" ""))) 3655 (clobber (match_dup 2))])] 3656 "TARGET_80387 || TARGET_SSE2" 3657 " 3658 if (TARGET_80387) 3659 operands[2] = assign_386_stack_local (SFmode, 0); 3660 else 3661 { 3662 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1])); 3663 DONE; 3664 } 3665") 3666 3667(define_insn "*truncdfsf2_1" 3668 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf") 3669 (float_truncate:SF 3670 (match_operand:DF 1 "register_operand" "f,f,f,f"))) 3671 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))] 3672 "TARGET_80387 && !TARGET_SSE2" 3673{ 3674 switch (which_alternative) 3675 { 3676 case 0: 3677 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3678 return "fstp%z0\t%y0"; 3679 else 3680 return "fst%z0\t%y0"; 3681 default: 3682 abort (); 3683 } 3684} 3685 [(set_attr "type" "fmov,multi,multi,multi") 3686 (set_attr "mode" "SF,SF,SF,SF")]) 3687 3688(define_insn "*truncdfsf2_1_sse" 3689 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,Y") 3690 (float_truncate:SF 3691 (match_operand:DF 1 "nonimmediate_operand" "f,f,f,f,mY"))) 3692 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))] 3693 "TARGET_80387 && TARGET_SSE2" 3694{ 3695 switch (which_alternative) 3696 { 3697 case 0: 3698 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3699 return "fstp%z0\t%y0"; 3700 else 3701 return "fst%z0\t%y0"; 3702 case 4: 3703 return "cvtsd2ss\t{%1, %0|%0, %1}"; 3704 default: 3705 abort (); 3706 } 3707} 3708 [(set_attr "type" "fmov,multi,multi,multi,ssecvt") 3709 (set_attr "mode" "SF,SF,SF,SF,DF")]) 3710 3711(define_insn "*truncdfsf2_2" 3712 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m") 3713 (float_truncate:SF 3714 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))] 3715 "TARGET_80387 && TARGET_SSE2 3716 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 3717{ 3718 switch (which_alternative) 3719 { 3720 case 0: 3721 return "cvtsd2ss\t{%1, %0|%0, %1}"; 3722 case 1: 3723 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3724 return "fstp%z0\t%y0"; 3725 else 3726 return "fst%z0\t%y0"; 3727 default: 3728 abort (); 3729 } 3730} 3731 [(set_attr "type" "ssecvt,fmov") 3732 (set_attr "mode" "DF,SF")]) 3733 3734(define_insn "truncdfsf2_3" 3735 [(set (match_operand:SF 0 "memory_operand" "=m") 3736 (float_truncate:SF 3737 (match_operand:DF 1 "register_operand" "f")))] 3738 "TARGET_80387" 3739{ 3740 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3741 return "fstp%z0\t%y0"; 3742 else 3743 return "fst%z0\t%y0"; 3744} 3745 [(set_attr "type" "fmov") 3746 (set_attr "mode" "SF")]) 3747 3748(define_insn "truncdfsf2_sse_only" 3749 [(set (match_operand:SF 0 "register_operand" "=Y") 3750 (float_truncate:SF 3751 (match_operand:DF 1 "nonimmediate_operand" "mY")))] 3752 "!TARGET_80387 && TARGET_SSE2" 3753 "cvtsd2ss\t{%1, %0|%0, %1}" 3754 [(set_attr "type" "ssecvt") 3755 (set_attr "mode" "DF")]) 3756 3757(define_split 3758 [(set (match_operand:SF 0 "memory_operand" "") 3759 (float_truncate:SF 3760 (match_operand:DF 1 "register_operand" ""))) 3761 (clobber (match_operand:SF 2 "memory_operand" ""))] 3762 "TARGET_80387" 3763 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] 3764 "") 3765 3766(define_split 3767 [(set (match_operand:SF 0 "nonimmediate_operand" "") 3768 (float_truncate:SF 3769 (match_operand:DF 1 "nonimmediate_operand" ""))) 3770 (clobber (match_operand 2 "" ""))] 3771 "TARGET_80387 && reload_completed 3772 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])" 3773 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] 3774 "") 3775 3776(define_split 3777 [(set (match_operand:SF 0 "register_operand" "") 3778 (float_truncate:SF 3779 (match_operand:DF 1 "fp_register_operand" ""))) 3780 (clobber (match_operand:SF 2 "memory_operand" ""))] 3781 "TARGET_80387 && reload_completed" 3782 [(set (match_dup 2) (float_truncate:SF (match_dup 1))) 3783 (set (match_dup 0) (match_dup 2))] 3784 "") 3785 3786(define_expand "truncxfsf2" 3787 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") 3788 (float_truncate:SF 3789 (match_operand:XF 1 "register_operand" ""))) 3790 (clobber (match_dup 2))])] 3791 "!TARGET_64BIT && TARGET_80387" 3792 "operands[2] = assign_386_stack_local (SFmode, 0);") 3793 3794(define_insn "*truncxfsf2_1" 3795 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf") 3796 (float_truncate:SF 3797 (match_operand:XF 1 "register_operand" "f,f,f,f"))) 3798 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))] 3799 "!TARGET_64BIT && TARGET_80387" 3800{ 3801 switch (which_alternative) 3802 { 3803 case 0: 3804 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3805 return "fstp%z0\t%y0"; 3806 else 3807 return "fst%z0\t%y0"; 3808 default: 3809 abort(); 3810 } 3811} 3812 [(set_attr "type" "fmov,multi,multi,multi") 3813 (set_attr "mode" "SF")]) 3814 3815(define_insn "*truncxfsf2_2" 3816 [(set (match_operand:SF 0 "memory_operand" "=m") 3817 (float_truncate:SF 3818 (match_operand:XF 1 "register_operand" "f")))] 3819 "!TARGET_64BIT && TARGET_80387" 3820{ 3821 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3822 return "fstp%z0\t%y0"; 3823 else 3824 return "fst%z0\t%y0"; 3825} 3826 [(set_attr "type" "fmov") 3827 (set_attr "mode" "SF")]) 3828 3829(define_split 3830 [(set (match_operand:SF 0 "memory_operand" "") 3831 (float_truncate:SF 3832 (match_operand:XF 1 "register_operand" ""))) 3833 (clobber (match_operand:SF 2 "memory_operand" ""))] 3834 "TARGET_80387" 3835 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] 3836 "") 3837 3838(define_split 3839 [(set (match_operand:SF 0 "register_operand" "") 3840 (float_truncate:SF 3841 (match_operand:XF 1 "register_operand" ""))) 3842 (clobber (match_operand:SF 2 "memory_operand" ""))] 3843 "TARGET_80387 && reload_completed" 3844 [(set (match_dup 2) (float_truncate:SF (match_dup 1))) 3845 (set (match_dup 0) (match_dup 2))] 3846 "") 3847 3848(define_expand "trunctfsf2" 3849 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") 3850 (float_truncate:SF 3851 (match_operand:TF 1 "register_operand" ""))) 3852 (clobber (match_dup 2))])] 3853 "TARGET_80387" 3854 "operands[2] = assign_386_stack_local (SFmode, 0);") 3855 3856(define_insn "*trunctfsf2_1" 3857 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf") 3858 (float_truncate:SF 3859 (match_operand:TF 1 "register_operand" "f,f,f,f"))) 3860 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))] 3861 "TARGET_80387" 3862{ 3863 switch (which_alternative) 3864 { 3865 case 0: 3866 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3867 return "fstp%z0\t%y0"; 3868 else 3869 return "fst%z0\t%y0"; 3870 default: 3871 abort(); 3872 } 3873} 3874 [(set_attr "type" "fmov,multi,multi,multi") 3875 (set_attr "mode" "SF")]) 3876 3877(define_insn "*trunctfsf2_2" 3878 [(set (match_operand:SF 0 "memory_operand" "=m") 3879 (float_truncate:SF 3880 (match_operand:TF 1 "register_operand" "f")))] 3881 "TARGET_80387" 3882{ 3883 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3884 return "fstp%z0\t%y0"; 3885 else 3886 return "fst%z0\t%y0"; 3887} 3888 [(set_attr "type" "fmov") 3889 (set_attr "mode" "SF")]) 3890 3891(define_split 3892 [(set (match_operand:SF 0 "memory_operand" "") 3893 (float_truncate:SF 3894 (match_operand:TF 1 "register_operand" ""))) 3895 (clobber (match_operand:SF 2 "memory_operand" ""))] 3896 "TARGET_80387" 3897 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] 3898 "") 3899 3900(define_split 3901 [(set (match_operand:SF 0 "register_operand" "") 3902 (float_truncate:SF 3903 (match_operand:TF 1 "register_operand" ""))) 3904 (clobber (match_operand:SF 2 "memory_operand" ""))] 3905 "TARGET_80387 && reload_completed" 3906 [(set (match_dup 2) (float_truncate:SF (match_dup 1))) 3907 (set (match_dup 0) (match_dup 2))] 3908 "") 3909 3910 3911(define_expand "truncxfdf2" 3912 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") 3913 (float_truncate:DF 3914 (match_operand:XF 1 "register_operand" ""))) 3915 (clobber (match_dup 2))])] 3916 "!TARGET_64BIT && TARGET_80387" 3917 "operands[2] = assign_386_stack_local (DFmode, 0);") 3918 3919(define_insn "*truncxfdf2_1" 3920 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf") 3921 (float_truncate:DF 3922 (match_operand:XF 1 "register_operand" "f,f,f,f"))) 3923 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))] 3924 "!TARGET_64BIT && TARGET_80387" 3925{ 3926 switch (which_alternative) 3927 { 3928 case 0: 3929 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3930 return "fstp%z0\t%y0"; 3931 else 3932 return "fst%z0\t%y0"; 3933 default: 3934 abort(); 3935 } 3936 abort (); 3937} 3938 [(set_attr "type" "fmov,multi,multi,multi") 3939 (set_attr "mode" "DF")]) 3940 3941(define_insn "*truncxfdf2_2" 3942 [(set (match_operand:DF 0 "memory_operand" "=m") 3943 (float_truncate:DF 3944 (match_operand:XF 1 "register_operand" "f")))] 3945 "!TARGET_64BIT && TARGET_80387" 3946{ 3947 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3948 return "fstp%z0\t%y0"; 3949 else 3950 return "fst%z0\t%y0"; 3951} 3952 [(set_attr "type" "fmov") 3953 (set_attr "mode" "DF")]) 3954 3955(define_split 3956 [(set (match_operand:DF 0 "memory_operand" "") 3957 (float_truncate:DF 3958 (match_operand:XF 1 "register_operand" ""))) 3959 (clobber (match_operand:DF 2 "memory_operand" ""))] 3960 "TARGET_80387" 3961 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))] 3962 "") 3963 3964(define_split 3965 [(set (match_operand:DF 0 "register_operand" "") 3966 (float_truncate:DF 3967 (match_operand:XF 1 "register_operand" ""))) 3968 (clobber (match_operand:DF 2 "memory_operand" ""))] 3969 "TARGET_80387 && reload_completed" 3970 [(set (match_dup 2) (float_truncate:DF (match_dup 1))) 3971 (set (match_dup 0) (match_dup 2))] 3972 "") 3973 3974(define_expand "trunctfdf2" 3975 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") 3976 (float_truncate:DF 3977 (match_operand:TF 1 "register_operand" ""))) 3978 (clobber (match_dup 2))])] 3979 "TARGET_80387" 3980 "operands[2] = assign_386_stack_local (DFmode, 0);") 3981 3982(define_insn "*trunctfdf2_1" 3983 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf") 3984 (float_truncate:DF 3985 (match_operand:TF 1 "register_operand" "f,f,f,f"))) 3986 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))] 3987 "TARGET_80387" 3988{ 3989 switch (which_alternative) 3990 { 3991 case 0: 3992 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3993 return "fstp%z0\t%y0"; 3994 else 3995 return "fst%z0\t%y0"; 3996 default: 3997 abort(); 3998 } 3999 abort (); 4000} 4001 [(set_attr "type" "fmov,multi,multi,multi") 4002 (set_attr "mode" "DF")]) 4003 4004 (define_insn "*trunctfdf2_2" 4005 [(set (match_operand:DF 0 "memory_operand" "=m") 4006 (float_truncate:DF 4007 (match_operand:TF 1 "register_operand" "f")))] 4008 "TARGET_80387" 4009{ 4010 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 4011 return "fstp%z0\t%y0"; 4012 else 4013 return "fst%z0\t%y0"; 4014} 4015 [(set_attr "type" "fmov") 4016 (set_attr "mode" "DF")]) 4017 4018(define_split 4019 [(set (match_operand:DF 0 "memory_operand" "") 4020 (float_truncate:DF 4021 (match_operand:TF 1 "register_operand" ""))) 4022 (clobber (match_operand:DF 2 "memory_operand" ""))] 4023 "TARGET_80387" 4024 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))] 4025 "") 4026 4027(define_split 4028 [(set (match_operand:DF 0 "register_operand" "") 4029 (float_truncate:DF 4030 (match_operand:TF 1 "register_operand" ""))) 4031 (clobber (match_operand:DF 2 "memory_operand" ""))] 4032 "TARGET_80387 && reload_completed" 4033 [(set (match_dup 2) (float_truncate:DF (match_dup 1))) 4034 (set (match_dup 0) (match_dup 2))] 4035 "") 4036 4037 4038;; %%% Break up all these bad boys. 4039 4040;; Signed conversion to DImode. 4041 4042(define_expand "fix_truncxfdi2" 4043 [(set (match_operand:DI 0 "nonimmediate_operand" "") 4044 (fix:DI (match_operand:XF 1 "register_operand" "")))] 4045 "!TARGET_64BIT && TARGET_80387" 4046 "") 4047 4048(define_expand "fix_trunctfdi2" 4049 [(set (match_operand:DI 0 "nonimmediate_operand" "") 4050 (fix:DI (match_operand:TF 1 "register_operand" "")))] 4051 "TARGET_80387" 4052 "") 4053 4054(define_expand "fix_truncdfdi2" 4055 [(set (match_operand:DI 0 "nonimmediate_operand" "") 4056 (fix:DI (match_operand:DF 1 "register_operand" "")))] 4057 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)" 4058{ 4059 if (TARGET_64BIT && TARGET_SSE2) 4060 { 4061 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode); 4062 emit_insn (gen_fix_truncdfdi_sse (out, operands[1])); 4063 if (out != operands[0]) 4064 emit_move_insn (operands[0], out); 4065 DONE; 4066 } 4067}) 4068 4069(define_expand "fix_truncsfdi2" 4070 [(set (match_operand:DI 0 "nonimmediate_operand" "") 4071 (fix:DI (match_operand:SF 1 "register_operand" "")))] 4072 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)" 4073{ 4074 if (TARGET_SSE && TARGET_64BIT) 4075 { 4076 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode); 4077 emit_insn (gen_fix_truncsfdi_sse (out, operands[1])); 4078 if (out != operands[0]) 4079 emit_move_insn (operands[0], out); 4080 DONE; 4081 } 4082}) 4083 4084;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description 4085;; of the machinery. 4086(define_insn_and_split "*fix_truncdi_1" 4087 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r") 4088 (fix:DI (match_operand 1 "register_operand" "f,f")))] 4089 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) 4090 && !reload_completed && !reload_in_progress 4091 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" 4092 "#" 4093 "&& 1" 4094 [(const_int 0)] 4095{ 4096 operands[2] = assign_386_stack_local (HImode, 1); 4097 operands[3] = assign_386_stack_local (HImode, 2); 4098 if (memory_operand (operands[0], VOIDmode)) 4099 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1], 4100 operands[2], operands[3])); 4101 else 4102 { 4103 operands[4] = assign_386_stack_local (DImode, 0); 4104 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1], 4105 operands[2], operands[3], 4106 operands[4])); 4107 } 4108 DONE; 4109} 4110 [(set_attr "type" "fistp")]) 4111 4112(define_insn "fix_truncdi_nomemory" 4113 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r") 4114 (fix:DI (match_operand 1 "register_operand" "f,f"))) 4115 (use (match_operand:HI 2 "memory_operand" "m,m")) 4116 (use (match_operand:HI 3 "memory_operand" "m,m")) 4117 (clobber (match_operand:DI 4 "memory_operand" "=m,m")) 4118 (clobber (match_scratch:DF 5 "=&1f,&1f"))] 4119 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) 4120 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" 4121 "#" 4122 [(set_attr "type" "fistp")]) 4123 4124(define_insn "fix_truncdi_memory" 4125 [(set (match_operand:DI 0 "memory_operand" "=m") 4126 (fix:DI (match_operand 1 "register_operand" "f"))) 4127 (use (match_operand:HI 2 "memory_operand" "m")) 4128 (use (match_operand:HI 3 "memory_operand" "m")) 4129 (clobber (match_scratch:DF 4 "=&1f"))] 4130 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) 4131 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" 4132 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);" 4133 [(set_attr "type" "fistp")]) 4134 4135(define_split 4136 [(set (match_operand:DI 0 "register_operand" "") 4137 (fix:DI (match_operand 1 "register_operand" ""))) 4138 (use (match_operand:HI 2 "memory_operand" "")) 4139 (use (match_operand:HI 3 "memory_operand" "")) 4140 (clobber (match_operand:DI 4 "memory_operand" "")) 4141 (clobber (match_scratch 5 ""))] 4142 "reload_completed" 4143 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1))) 4144 (use (match_dup 2)) 4145 (use (match_dup 3)) 4146 (clobber (match_dup 5))]) 4147 (set (match_dup 0) (match_dup 4))] 4148 "") 4149 4150(define_split 4151 [(set (match_operand:DI 0 "memory_operand" "") 4152 (fix:DI (match_operand 1 "register_operand" ""))) 4153 (use (match_operand:HI 2 "memory_operand" "")) 4154 (use (match_operand:HI 3 "memory_operand" "")) 4155 (clobber (match_operand:DI 4 "memory_operand" "")) 4156 (clobber (match_scratch 5 ""))] 4157 "reload_completed" 4158 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1))) 4159 (use (match_dup 2)) 4160 (use (match_dup 3)) 4161 (clobber (match_dup 5))])] 4162 "") 4163 4164;; When SSE available, it is always faster to use it! 4165(define_insn "fix_truncsfdi_sse" 4166 [(set (match_operand:DI 0 "register_operand" "=r") 4167 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))] 4168 "TARGET_64BIT && TARGET_SSE" 4169 "cvttss2si{q}\t{%1, %0|%0, %1}" 4170 [(set_attr "type" "ssecvt")]) 4171 4172(define_insn "fix_truncdfdi_sse" 4173 [(set (match_operand:DI 0 "register_operand" "=r") 4174 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))] 4175 "TARGET_64BIT && TARGET_SSE2" 4176 "cvttsd2si{q}\t{%1, %0|%0, %1}" 4177 [(set_attr "type" "ssecvt")]) 4178 4179;; Signed conversion to SImode. 4180 4181(define_expand "fix_truncxfsi2" 4182 [(set (match_operand:SI 0 "nonimmediate_operand" "") 4183 (fix:SI (match_operand:XF 1 "register_operand" "")))] 4184 "!TARGET_64BIT && TARGET_80387" 4185 "") 4186 4187(define_expand "fix_trunctfsi2" 4188 [(set (match_operand:SI 0 "nonimmediate_operand" "") 4189 (fix:SI (match_operand:TF 1 "register_operand" "")))] 4190 "TARGET_80387" 4191 "") 4192 4193(define_expand "fix_truncdfsi2" 4194 [(set (match_operand:SI 0 "nonimmediate_operand" "") 4195 (fix:SI (match_operand:DF 1 "register_operand" "")))] 4196 "TARGET_80387 || TARGET_SSE2" 4197{ 4198 if (TARGET_SSE2) 4199 { 4200 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode); 4201 emit_insn (gen_fix_truncdfsi_sse (out, operands[1])); 4202 if (out != operands[0]) 4203 emit_move_insn (operands[0], out); 4204 DONE; 4205 } 4206}) 4207 4208(define_expand "fix_truncsfsi2" 4209 [(set (match_operand:SI 0 "nonimmediate_operand" "") 4210 (fix:SI (match_operand:SF 1 "register_operand" "")))] 4211 "TARGET_80387 || TARGET_SSE" 4212{ 4213 if (TARGET_SSE) 4214 { 4215 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode); 4216 emit_insn (gen_fix_truncsfsi_sse (out, operands[1])); 4217 if (out != operands[0]) 4218 emit_move_insn (operands[0], out); 4219 DONE; 4220 } 4221}) 4222 4223;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description 4224;; of the machinery. 4225(define_insn_and_split "*fix_truncsi_1" 4226 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r") 4227 (fix:SI (match_operand 1 "register_operand" "f,f")))] 4228 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) 4229 && !reload_completed && !reload_in_progress 4230 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" 4231 "#" 4232 "&& 1" 4233 [(const_int 0)] 4234{ 4235 operands[2] = assign_386_stack_local (HImode, 1); 4236 operands[3] = assign_386_stack_local (HImode, 2); 4237 if (memory_operand (operands[0], VOIDmode)) 4238 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1], 4239 operands[2], operands[3])); 4240 else 4241 { 4242 operands[4] = assign_386_stack_local (SImode, 0); 4243 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1], 4244 operands[2], operands[3], 4245 operands[4])); 4246 } 4247 DONE; 4248} 4249 [(set_attr "type" "fistp")]) 4250 4251(define_insn "fix_truncsi_nomemory" 4252 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r") 4253 (fix:SI (match_operand 1 "register_operand" "f,f"))) 4254 (use (match_operand:HI 2 "memory_operand" "m,m")) 4255 (use (match_operand:HI 3 "memory_operand" "m,m")) 4256 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))] 4257 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) 4258 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" 4259 "#" 4260 [(set_attr "type" "fistp")]) 4261 4262(define_insn "fix_truncsi_memory" 4263 [(set (match_operand:SI 0 "memory_operand" "=m") 4264 (fix:SI (match_operand 1 "register_operand" "f"))) 4265 (use (match_operand:HI 2 "memory_operand" "m")) 4266 (use (match_operand:HI 3 "memory_operand" "m"))] 4267 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) 4268 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" 4269 "* return output_fix_trunc (insn, operands);" 4270 [(set_attr "type" "fistp")]) 4271 4272;; When SSE available, it is always faster to use it! 4273(define_insn "fix_truncsfsi_sse" 4274 [(set (match_operand:SI 0 "register_operand" "=r") 4275 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))] 4276 "TARGET_SSE" 4277 "cvttss2si\t{%1, %0|%0, %1}" 4278 [(set_attr "type" "ssecvt")]) 4279 4280(define_insn "fix_truncdfsi_sse" 4281 [(set (match_operand:SI 0 "register_operand" "=r") 4282 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))] 4283 "TARGET_SSE2" 4284 "cvttsd2si\t{%1, %0|%0, %1}" 4285 [(set_attr "type" "ssecvt")]) 4286 4287(define_split 4288 [(set (match_operand:SI 0 "register_operand" "") 4289 (fix:SI (match_operand 1 "register_operand" ""))) 4290 (use (match_operand:HI 2 "memory_operand" "")) 4291 (use (match_operand:HI 3 "memory_operand" "")) 4292 (clobber (match_operand:SI 4 "memory_operand" ""))] 4293 "reload_completed" 4294 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1))) 4295 (use (match_dup 2)) 4296 (use (match_dup 3))]) 4297 (set (match_dup 0) (match_dup 4))] 4298 "") 4299 4300(define_split 4301 [(set (match_operand:SI 0 "memory_operand" "") 4302 (fix:SI (match_operand 1 "register_operand" ""))) 4303 (use (match_operand:HI 2 "memory_operand" "")) 4304 (use (match_operand:HI 3 "memory_operand" "")) 4305 (clobber (match_operand:SI 4 "memory_operand" ""))] 4306 "reload_completed" 4307 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1))) 4308 (use (match_dup 2)) 4309 (use (match_dup 3))])] 4310 "") 4311 4312;; Signed conversion to HImode. 4313 4314(define_expand "fix_truncxfhi2" 4315 [(set (match_operand:HI 0 "nonimmediate_operand" "") 4316 (fix:HI (match_operand:XF 1 "register_operand" "")))] 4317 "!TARGET_64BIT && TARGET_80387" 4318 "") 4319 4320(define_expand "fix_trunctfhi2" 4321 [(set (match_operand:HI 0 "nonimmediate_operand" "") 4322 (fix:HI (match_operand:TF 1 "register_operand" "")))] 4323 "TARGET_80387" 4324 "") 4325 4326(define_expand "fix_truncdfhi2" 4327 [(set (match_operand:HI 0 "nonimmediate_operand" "") 4328 (fix:HI (match_operand:DF 1 "register_operand" "")))] 4329 "TARGET_80387 && !TARGET_SSE2" 4330 "") 4331 4332(define_expand "fix_truncsfhi2" 4333 [(set (match_operand:HI 0 "nonimmediate_operand" "") 4334 (fix:HI (match_operand:SF 1 "register_operand" "")))] 4335 "TARGET_80387 && !TARGET_SSE" 4336 "") 4337 4338;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description 4339;; of the machinery. 4340(define_insn_and_split "*fix_trunchi_1" 4341 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r") 4342 (fix:HI (match_operand 1 "register_operand" "f,f")))] 4343 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) 4344 && !reload_completed && !reload_in_progress 4345 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" 4346 "#" 4347 "" 4348 [(const_int 0)] 4349{ 4350 operands[2] = assign_386_stack_local (HImode, 1); 4351 operands[3] = assign_386_stack_local (HImode, 2); 4352 if (memory_operand (operands[0], VOIDmode)) 4353 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1], 4354 operands[2], operands[3])); 4355 else 4356 { 4357 operands[4] = assign_386_stack_local (HImode, 0); 4358 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1], 4359 operands[2], operands[3], 4360 operands[4])); 4361 } 4362 DONE; 4363} 4364 [(set_attr "type" "fistp")]) 4365 4366(define_insn "fix_trunchi_nomemory" 4367 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r") 4368 (fix:HI (match_operand 1 "register_operand" "f,f"))) 4369 (use (match_operand:HI 2 "memory_operand" "m,m")) 4370 (use (match_operand:HI 3 "memory_operand" "m,m")) 4371 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))] 4372 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) 4373 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" 4374 "#" 4375 [(set_attr "type" "fistp")]) 4376 4377(define_insn "fix_trunchi_memory" 4378 [(set (match_operand:HI 0 "memory_operand" "=m") 4379 (fix:HI (match_operand 1 "register_operand" "f"))) 4380 (use (match_operand:HI 2 "memory_operand" "m")) 4381 (use (match_operand:HI 3 "memory_operand" "m"))] 4382 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) 4383 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" 4384 "* return output_fix_trunc (insn, operands);" 4385 [(set_attr "type" "fistp")]) 4386 4387(define_split 4388 [(set (match_operand:HI 0 "memory_operand" "") 4389 (fix:HI (match_operand 1 "register_operand" ""))) 4390 (use (match_operand:HI 2 "memory_operand" "")) 4391 (use (match_operand:HI 3 "memory_operand" "")) 4392 (clobber (match_operand:HI 4 "memory_operand" ""))] 4393 "reload_completed" 4394 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1))) 4395 (use (match_dup 2)) 4396 (use (match_dup 3))])] 4397 "") 4398 4399(define_split 4400 [(set (match_operand:HI 0 "register_operand" "") 4401 (fix:HI (match_operand 1 "register_operand" ""))) 4402 (use (match_operand:HI 2 "memory_operand" "")) 4403 (use (match_operand:HI 3 "memory_operand" "")) 4404 (clobber (match_operand:HI 4 "memory_operand" ""))] 4405 "reload_completed" 4406 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1))) 4407 (use (match_dup 2)) 4408 (use (match_dup 3)) 4409 (clobber (match_dup 4))]) 4410 (set (match_dup 0) (match_dup 4))] 4411 "") 4412 4413;; %% Not used yet. 4414(define_insn "x86_fnstcw_1" 4415 [(set (match_operand:HI 0 "memory_operand" "=m") 4416 (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))] 4417 "TARGET_80387" 4418 "fnstcw\t%0" 4419 [(set_attr "length" "2") 4420 (set_attr "mode" "HI") 4421 (set_attr "unit" "i387") 4422 (set_attr "ppro_uops" "few")]) 4423 4424(define_insn "x86_fldcw_1" 4425 [(set (reg:HI 18) 4426 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))] 4427 "TARGET_80387" 4428 "fldcw\t%0" 4429 [(set_attr "length" "2") 4430 (set_attr "mode" "HI") 4431 (set_attr "unit" "i387") 4432 (set_attr "athlon_decode" "vector") 4433 (set_attr "ppro_uops" "few")]) 4434 4435;; Conversion between fixed point and floating point. 4436 4437;; Even though we only accept memory inputs, the backend _really_ 4438;; wants to be able to do this between registers. 4439 4440(define_insn "floathisf2" 4441 [(set (match_operand:SF 0 "register_operand" "=f,f") 4442 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] 4443 "TARGET_80387 && !TARGET_SSE" 4444 "@ 4445 fild%z1\t%1 4446 #" 4447 [(set_attr "type" "fmov,multi") 4448 (set_attr "mode" "SF") 4449 (set_attr "fp_int_src" "true")]) 4450 4451(define_expand "floatsisf2" 4452 [(set (match_operand:SF 0 "register_operand" "") 4453 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] 4454 "TARGET_SSE || TARGET_80387" 4455 "") 4456 4457(define_insn "*floatsisf2_i387" 4458 [(set (match_operand:SF 0 "register_operand" "=f,?f,x") 4459 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))] 4460 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)" 4461 "@ 4462 fild%z1\t%1 4463 # 4464 cvtsi2ss\t{%1, %0|%0, %1}" 4465 [(set_attr "type" "fmov,multi,ssecvt") 4466 (set_attr "mode" "SF") 4467 (set_attr "fp_int_src" "true")]) 4468 4469(define_insn "*floatsisf2_sse" 4470 [(set (match_operand:SF 0 "register_operand" "=x") 4471 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))] 4472 "TARGET_SSE" 4473 "cvtsi2ss\t{%1, %0|%0, %1}" 4474 [(set_attr "type" "ssecvt") 4475 (set_attr "mode" "SF") 4476 (set_attr "fp_int_src" "true")]) 4477 4478(define_expand "floatdisf2" 4479 [(set (match_operand:SF 0 "register_operand" "") 4480 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))] 4481 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387" 4482 "") 4483 4484(define_insn "*floatdisf2_i387_only" 4485 [(set (match_operand:SF 0 "register_operand" "=f,?f") 4486 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] 4487 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)" 4488 "@ 4489 fild%z1\t%1 4490 #" 4491 [(set_attr "type" "fmov,multi") 4492 (set_attr "mode" "SF") 4493 (set_attr "fp_int_src" "true")]) 4494 4495(define_insn "*floatdisf2_i387" 4496 [(set (match_operand:SF 0 "register_operand" "=f,?f,x") 4497 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))] 4498 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)" 4499 "@ 4500 fild%z1\t%1 4501 # 4502 cvtsi2ss{q}\t{%1, %0|%0, %1}" 4503 [(set_attr "type" "fmov,multi,ssecvt") 4504 (set_attr "mode" "SF") 4505 (set_attr "fp_int_src" "true")]) 4506 4507(define_insn "*floatdisf2_sse" 4508 [(set (match_operand:SF 0 "register_operand" "=x") 4509 (float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))] 4510 "TARGET_64BIT && TARGET_SSE" 4511 "cvtsi2ss{q}\t{%1, %0|%0, %1}" 4512 [(set_attr "type" "ssecvt") 4513 (set_attr "mode" "SF") 4514 (set_attr "fp_int_src" "true")]) 4515 4516(define_insn "floathidf2" 4517 [(set (match_operand:DF 0 "register_operand" "=f,f") 4518 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] 4519 "TARGET_80387 && !TARGET_SSE2" 4520 "@ 4521 fild%z1\t%1 4522 #" 4523 [(set_attr "type" "fmov,multi") 4524 (set_attr "mode" "DF") 4525 (set_attr "fp_int_src" "true")]) 4526 4527(define_expand "floatsidf2" 4528 [(set (match_operand:DF 0 "register_operand" "") 4529 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))] 4530 "TARGET_80387 || TARGET_SSE2" 4531 "") 4532 4533(define_insn "*floatsidf2_i387" 4534 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y") 4535 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))] 4536 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" 4537 "@ 4538 fild%z1\t%1 4539 # 4540 cvtsi2sd\t{%1, %0|%0, %1}" 4541 [(set_attr "type" "fmov,multi,ssecvt") 4542 (set_attr "mode" "DF") 4543 (set_attr "fp_int_src" "true")]) 4544 4545(define_insn "*floatsidf2_sse" 4546 [(set (match_operand:DF 0 "register_operand" "=Y") 4547 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))] 4548 "TARGET_SSE2" 4549 "cvtsi2sd\t{%1, %0|%0, %1}" 4550 [(set_attr "type" "ssecvt") 4551 (set_attr "mode" "DF") 4552 (set_attr "fp_int_src" "true")]) 4553 4554(define_expand "floatdidf2" 4555 [(set (match_operand:DF 0 "register_operand" "") 4556 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))] 4557 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387" 4558 "") 4559 4560(define_insn "*floatdidf2_i387_only" 4561 [(set (match_operand:DF 0 "register_operand" "=f,?f") 4562 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] 4563 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)" 4564 "@ 4565 fild%z1\t%1 4566 #" 4567 [(set_attr "type" "fmov,multi") 4568 (set_attr "mode" "DF") 4569 (set_attr "fp_int_src" "true")]) 4570 4571(define_insn "*floatdidf2_i387" 4572 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y") 4573 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))] 4574 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" 4575 "@ 4576 fild%z1\t%1 4577 # 4578 cvtsi2sd{q}\t{%1, %0|%0, %1}" 4579 [(set_attr "type" "fmov,multi,ssecvt") 4580 (set_attr "mode" "DF") 4581 (set_attr "fp_int_src" "true")]) 4582 4583(define_insn "*floatdidf2_sse" 4584 [(set (match_operand:DF 0 "register_operand" "=Y") 4585 (float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))] 4586 "TARGET_SSE2" 4587 "cvtsi2sd{q}\t{%1, %0|%0, %1}" 4588 [(set_attr "type" "ssecvt") 4589 (set_attr "mode" "DF") 4590 (set_attr "fp_int_src" "true")]) 4591 4592(define_insn "floathixf2" 4593 [(set (match_operand:XF 0 "register_operand" "=f,f") 4594 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] 4595 "!TARGET_64BIT && TARGET_80387" 4596 "@ 4597 fild%z1\t%1 4598 #" 4599 [(set_attr "type" "fmov,multi") 4600 (set_attr "mode" "XF") 4601 (set_attr "fp_int_src" "true")]) 4602 4603(define_insn "floathitf2" 4604 [(set (match_operand:TF 0 "register_operand" "=f,f") 4605 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] 4606 "TARGET_80387" 4607 "@ 4608 fild%z1\t%1 4609 #" 4610 [(set_attr "type" "fmov,multi") 4611 (set_attr "mode" "XF") 4612 (set_attr "fp_int_src" "true")]) 4613 4614(define_insn "floatsixf2" 4615 [(set (match_operand:XF 0 "register_operand" "=f,f") 4616 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))] 4617 "!TARGET_64BIT && TARGET_80387" 4618 "@ 4619 fild%z1\t%1 4620 #" 4621 [(set_attr "type" "fmov,multi") 4622 (set_attr "mode" "XF") 4623 (set_attr "fp_int_src" "true")]) 4624 4625(define_insn "floatsitf2" 4626 [(set (match_operand:TF 0 "register_operand" "=f,f") 4627 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))] 4628 "TARGET_80387" 4629 "@ 4630 fild%z1\t%1 4631 #" 4632 [(set_attr "type" "fmov,multi") 4633 (set_attr "mode" "XF") 4634 (set_attr "fp_int_src" "true")]) 4635 4636(define_insn "floatdixf2" 4637 [(set (match_operand:XF 0 "register_operand" "=f,f") 4638 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] 4639 "!TARGET_64BIT && TARGET_80387" 4640 "@ 4641 fild%z1\t%1 4642 #" 4643 [(set_attr "type" "fmov,multi") 4644 (set_attr "mode" "XF") 4645 (set_attr "fp_int_src" "true")]) 4646 4647(define_insn "floatditf2" 4648 [(set (match_operand:TF 0 "register_operand" "=f,f") 4649 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] 4650 "TARGET_80387" 4651 "@ 4652 fild%z1\t%1 4653 #" 4654 [(set_attr "type" "fmov,multi") 4655 (set_attr "mode" "XF") 4656 (set_attr "fp_int_src" "true")]) 4657 4658;; %%% Kill these when reload knows how to do it. 4659(define_split 4660 [(set (match_operand 0 "fp_register_operand" "") 4661 (float (match_operand 1 "register_operand" "")))] 4662 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))" 4663 [(const_int 0)] 4664{ 4665 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]); 4666 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]); 4667 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2])); 4668 ix86_free_from_memory (GET_MODE (operands[1])); 4669 DONE; 4670}) 4671 4672;; Add instructions 4673 4674;; %%% splits for addsidi3 4675; [(set (match_operand:DI 0 "nonimmediate_operand" "") 4676; (plus:DI (match_operand:DI 1 "general_operand" "") 4677; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))] 4678 4679(define_expand "adddi3" 4680 [(set (match_operand:DI 0 "nonimmediate_operand" "") 4681 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") 4682 (match_operand:DI 2 "x86_64_general_operand" ""))) 4683 (clobber (reg:CC 17))] 4684 "" 4685 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;") 4686 4687(define_insn "*adddi3_1" 4688 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") 4689 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 4690 (match_operand:DI 2 "general_operand" "roiF,riF"))) 4691 (clobber (reg:CC 17))] 4692 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" 4693 "#") 4694 4695(define_split 4696 [(set (match_operand:DI 0 "nonimmediate_operand" "") 4697 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") 4698 (match_operand:DI 2 "general_operand" ""))) 4699 (clobber (reg:CC 17))] 4700 "!TARGET_64BIT && reload_completed" 4701 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 4702 UNSPEC_ADD_CARRY)) 4703 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) 4704 (parallel [(set (match_dup 3) 4705 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) 4706 (match_dup 4)) 4707 (match_dup 5))) 4708 (clobber (reg:CC 17))])] 4709 "split_di (operands+0, 1, operands+0, operands+3); 4710 split_di (operands+1, 1, operands+1, operands+4); 4711 split_di (operands+2, 1, operands+2, operands+5);") 4712 4713(define_insn "*adddi3_carry_rex64" 4714 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") 4715 (plus:DI (plus:DI (ltu:DI (reg:CC 17) (const_int 0)) 4716 (match_operand:DI 1 "nonimmediate_operand" "%0,0")) 4717 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) 4718 (clobber (reg:CC 17))] 4719 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" 4720 "adc{q}\t{%2, %0|%0, %2}" 4721 [(set_attr "type" "alu") 4722 (set_attr "pent_pair" "pu") 4723 (set_attr "mode" "DI") 4724 (set_attr "ppro_uops" "few")]) 4725 4726(define_insn "*adddi3_cc_rex64" 4727 [(set (reg:CC 17) 4728 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0") 4729 (match_operand:DI 2 "x86_64_general_operand" "re,rm")] 4730 UNSPEC_ADD_CARRY)) 4731 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") 4732 (plus:DI (match_dup 1) (match_dup 2)))] 4733 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" 4734 "add{q}\t{%2, %0|%0, %2}" 4735 [(set_attr "type" "alu") 4736 (set_attr "mode" "DI")]) 4737 4738(define_insn "*addsi3_carry" 4739 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 4740 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) 4741 (match_operand:SI 1 "nonimmediate_operand" "%0,0")) 4742 (match_operand:SI 2 "general_operand" "ri,rm"))) 4743 (clobber (reg:CC 17))] 4744 "ix86_binary_operator_ok (PLUS, SImode, operands)" 4745 "adc{l}\t{%2, %0|%0, %2}" 4746 [(set_attr "type" "alu") 4747 (set_attr "pent_pair" "pu") 4748 (set_attr "mode" "SI") 4749 (set_attr "ppro_uops" "few")]) 4750 4751(define_insn "*addsi3_carry_zext" 4752 [(set (match_operand:DI 0 "register_operand" "=r") 4753 (zero_extend:DI 4754 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) 4755 (match_operand:SI 1 "nonimmediate_operand" "%0")) 4756 (match_operand:SI 2 "general_operand" "rim")))) 4757 (clobber (reg:CC 17))] 4758 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" 4759 "adc{l}\t{%2, %k0|%k0, %2}" 4760 [(set_attr "type" "alu") 4761 (set_attr "pent_pair" "pu") 4762 (set_attr "mode" "SI") 4763 (set_attr "ppro_uops" "few")]) 4764 4765(define_insn "*addsi3_cc" 4766 [(set (reg:CC 17) 4767 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0") 4768 (match_operand:SI 2 "general_operand" "ri,rm")] 4769 UNSPEC_ADD_CARRY)) 4770 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 4771 (plus:SI (match_dup 1) (match_dup 2)))] 4772 "ix86_binary_operator_ok (PLUS, SImode, operands)" 4773 "add{l}\t{%2, %0|%0, %2}" 4774 [(set_attr "type" "alu") 4775 (set_attr "mode" "SI")]) 4776 4777(define_insn "addqi3_cc" 4778 [(set (reg:CC 17) 4779 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0") 4780 (match_operand:QI 2 "general_operand" "qi,qm")] 4781 UNSPEC_ADD_CARRY)) 4782 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") 4783 (plus:QI (match_dup 1) (match_dup 2)))] 4784 "ix86_binary_operator_ok (PLUS, QImode, operands)" 4785 "add{b}\t{%2, %0|%0, %2}" 4786 [(set_attr "type" "alu") 4787 (set_attr "mode" "QI")]) 4788 4789(define_expand "addsi3" 4790 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") 4791 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") 4792 (match_operand:SI 2 "general_operand" ""))) 4793 (clobber (reg:CC 17))])] 4794 "" 4795 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;") 4796 4797(define_insn "*lea_1" 4798 [(set (match_operand:SI 0 "register_operand" "=r") 4799 (match_operand:SI 1 "address_operand" "p"))] 4800 "!TARGET_64BIT" 4801 "lea{l}\t{%a1, %0|%0, %a1}" 4802 [(set_attr "type" "lea") 4803 (set_attr "mode" "SI")]) 4804 4805(define_insn "*lea_1_rex64" 4806 [(set (match_operand:SI 0 "register_operand" "=r") 4807 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))] 4808 "TARGET_64BIT" 4809 "lea{l}\t{%a1, %0|%0, %a1}" 4810 [(set_attr "type" "lea") 4811 (set_attr "mode" "SI")]) 4812 4813(define_insn "*lea_1_zext" 4814 [(set (match_operand:DI 0 "register_operand" "=r") 4815 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))] 4816 "TARGET_64BIT" 4817 "lea{l}\t{%a1, %k0|%k0, %a1}" 4818 [(set_attr "type" "lea") 4819 (set_attr "mode" "SI")]) 4820 4821(define_insn "*lea_2_rex64" 4822 [(set (match_operand:DI 0 "register_operand" "=r") 4823 (match_operand:DI 1 "address_operand" "p"))] 4824 "TARGET_64BIT" 4825 "lea{q}\t{%a1, %0|%0, %a1}" 4826 [(set_attr "type" "lea") 4827 (set_attr "mode" "DI")]) 4828 4829;; The lea patterns for non-Pmodes needs to be matched by several 4830;; insns converted to real lea by splitters. 4831 4832(define_insn_and_split "*lea_general_1" 4833 [(set (match_operand 0 "register_operand" "=r") 4834 (plus (plus (match_operand 1 "index_register_operand" "r") 4835 (match_operand 2 "register_operand" "r")) 4836 (match_operand 3 "immediate_operand" "i")))] 4837 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode 4838 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode)) 4839 && (!TARGET_PARTIAL_REG_STALL || optimize_size) 4840 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 4841 && GET_MODE (operands[0]) == GET_MODE (operands[2]) 4842 && (GET_MODE (operands[0]) == GET_MODE (operands[3]) 4843 || GET_MODE (operands[3]) == VOIDmode)" 4844 "#" 4845 "&& reload_completed" 4846 [(const_int 0)] 4847{ 4848 rtx pat; 4849 operands[0] = gen_lowpart (SImode, operands[0]); 4850 operands[1] = gen_lowpart (Pmode, operands[1]); 4851 operands[2] = gen_lowpart (Pmode, operands[2]); 4852 operands[3] = gen_lowpart (Pmode, operands[3]); 4853 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]), 4854 operands[3]); 4855 if (Pmode != SImode) 4856 pat = gen_rtx_SUBREG (SImode, pat, 0); 4857 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); 4858 DONE; 4859} 4860 [(set_attr "type" "lea") 4861 (set_attr "mode" "SI")]) 4862 4863(define_insn_and_split "*lea_general_1_zext" 4864 [(set (match_operand:DI 0 "register_operand" "=r") 4865 (zero_extend:DI 4866 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r") 4867 (match_operand:SI 2 "register_operand" "r")) 4868 (match_operand:SI 3 "immediate_operand" "i"))))] 4869 "TARGET_64BIT" 4870 "#" 4871 "&& reload_completed" 4872 [(set (match_dup 0) 4873 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1) 4874 (match_dup 2)) 4875 (match_dup 3)) 0)))] 4876{ 4877 operands[1] = gen_lowpart (Pmode, operands[1]); 4878 operands[2] = gen_lowpart (Pmode, operands[2]); 4879 operands[3] = gen_lowpart (Pmode, operands[3]); 4880} 4881 [(set_attr "type" "lea") 4882 (set_attr "mode" "SI")]) 4883 4884(define_insn_and_split "*lea_general_2" 4885 [(set (match_operand 0 "register_operand" "=r") 4886 (plus (mult (match_operand 1 "index_register_operand" "r") 4887 (match_operand 2 "const248_operand" "i")) 4888 (match_operand 3 "nonmemory_operand" "ri")))] 4889 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode 4890 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode)) 4891 && (!TARGET_PARTIAL_REG_STALL || optimize_size) 4892 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 4893 && (GET_MODE (operands[0]) == GET_MODE (operands[3]) 4894 || GET_MODE (operands[3]) == VOIDmode)" 4895 "#" 4896 "&& reload_completed" 4897 [(const_int 0)] 4898{ 4899 rtx pat; 4900 operands[0] = gen_lowpart (SImode, operands[0]); 4901 operands[1] = gen_lowpart (Pmode, operands[1]); 4902 operands[3] = gen_lowpart (Pmode, operands[3]); 4903 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]), 4904 operands[3]); 4905 if (Pmode != SImode) 4906 pat = gen_rtx_SUBREG (SImode, pat, 0); 4907 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); 4908 DONE; 4909} 4910 [(set_attr "type" "lea") 4911 (set_attr "mode" "SI")]) 4912 4913(define_insn_and_split "*lea_general_2_zext" 4914 [(set (match_operand:DI 0 "register_operand" "=r") 4915 (zero_extend:DI 4916 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r") 4917 (match_operand:SI 2 "const248_operand" "n")) 4918 (match_operand:SI 3 "nonmemory_operand" "ri"))))] 4919 "TARGET_64BIT" 4920 "#" 4921 "&& reload_completed" 4922 [(set (match_dup 0) 4923 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1) 4924 (match_dup 2)) 4925 (match_dup 3)) 0)))] 4926{ 4927 operands[1] = gen_lowpart (Pmode, operands[1]); 4928 operands[3] = gen_lowpart (Pmode, operands[3]); 4929} 4930 [(set_attr "type" "lea") 4931 (set_attr "mode" "SI")]) 4932 4933(define_insn_and_split "*lea_general_3" 4934 [(set (match_operand 0 "register_operand" "=r") 4935 (plus (plus (mult (match_operand 1 "index_register_operand" "r") 4936 (match_operand 2 "const248_operand" "i")) 4937 (match_operand 3 "register_operand" "r")) 4938 (match_operand 4 "immediate_operand" "i")))] 4939 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode 4940 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode)) 4941 && (!TARGET_PARTIAL_REG_STALL || optimize_size) 4942 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 4943 && GET_MODE (operands[0]) == GET_MODE (operands[3])" 4944 "#" 4945 "&& reload_completed" 4946 [(const_int 0)] 4947{ 4948 rtx pat; 4949 operands[0] = gen_lowpart (SImode, operands[0]); 4950 operands[1] = gen_lowpart (Pmode, operands[1]); 4951 operands[3] = gen_lowpart (Pmode, operands[3]); 4952 operands[4] = gen_lowpart (Pmode, operands[4]); 4953 pat = gen_rtx_PLUS (Pmode, 4954 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], 4955 operands[2]), 4956 operands[3]), 4957 operands[4]); 4958 if (Pmode != SImode) 4959 pat = gen_rtx_SUBREG (SImode, pat, 0); 4960 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); 4961 DONE; 4962} 4963 [(set_attr "type" "lea") 4964 (set_attr "mode" "SI")]) 4965 4966(define_insn_and_split "*lea_general_3_zext" 4967 [(set (match_operand:DI 0 "register_operand" "=r") 4968 (zero_extend:DI 4969 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r") 4970 (match_operand:SI 2 "const248_operand" "n")) 4971 (match_operand:SI 3 "register_operand" "r")) 4972 (match_operand:SI 4 "immediate_operand" "i"))))] 4973 "TARGET_64BIT" 4974 "#" 4975 "&& reload_completed" 4976 [(set (match_dup 0) 4977 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1) 4978 (match_dup 2)) 4979 (match_dup 3)) 4980 (match_dup 4)) 0)))] 4981{ 4982 operands[1] = gen_lowpart (Pmode, operands[1]); 4983 operands[3] = gen_lowpart (Pmode, operands[3]); 4984 operands[4] = gen_lowpart (Pmode, operands[4]); 4985} 4986 [(set_attr "type" "lea") 4987 (set_attr "mode" "SI")]) 4988 4989(define_insn "*adddi_1_rex64" 4990 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r") 4991 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r") 4992 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re"))) 4993 (clobber (reg:CC 17))] 4994 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" 4995{ 4996 switch (get_attr_type (insn)) 4997 { 4998 case TYPE_LEA: 4999 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); 5000 return "lea{q}\t{%a2, %0|%0, %a2}"; 5001 5002 case TYPE_INCDEC: 5003 if (! rtx_equal_p (operands[0], operands[1])) 5004 abort (); 5005 if (operands[2] == const1_rtx) 5006 return "inc{q}\t%0"; 5007 else if (operands[2] == constm1_rtx) 5008 return "dec{q}\t%0"; 5009 else 5010 abort (); 5011 5012 default: 5013 if (! rtx_equal_p (operands[0], operands[1])) 5014 abort (); 5015 5016 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5017 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5018 if (GET_CODE (operands[2]) == CONST_INT 5019 /* Avoid overflows. */ 5020 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))) 5021 && (INTVAL (operands[2]) == 128 5022 || (INTVAL (operands[2]) < 0 5023 && INTVAL (operands[2]) != -128))) 5024 { 5025 operands[2] = GEN_INT (-INTVAL (operands[2])); 5026 return "sub{q}\t{%2, %0|%0, %2}"; 5027 } 5028 return "add{q}\t{%2, %0|%0, %2}"; 5029 } 5030} 5031 [(set (attr "type") 5032 (cond [(eq_attr "alternative" "2") 5033 (const_string "lea") 5034 ; Current assemblers are broken and do not allow @GOTOFF in 5035 ; ought but a memory context. 5036 (match_operand:DI 2 "pic_symbolic_operand" "") 5037 (const_string "lea") 5038 (match_operand:DI 2 "incdec_operand" "") 5039 (const_string "incdec") 5040 ] 5041 (const_string "alu"))) 5042 (set_attr "mode" "DI")]) 5043 5044;; Convert lea to the lea pattern to avoid flags dependency. 5045(define_split 5046 [(set (match_operand:DI 0 "register_operand" "") 5047 (plus:DI (match_operand:DI 1 "register_operand" "") 5048 (match_operand:DI 2 "x86_64_nonmemory_operand" ""))) 5049 (clobber (reg:CC 17))] 5050 "TARGET_64BIT && reload_completed 5051 && true_regnum (operands[0]) != true_regnum (operands[1])" 5052 [(set (match_dup 0) 5053 (plus:DI (match_dup 1) 5054 (match_dup 2)))] 5055 "") 5056 5057(define_insn "*adddi_2_rex64" 5058 [(set (reg 17) 5059 (compare 5060 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 5061 (match_operand:DI 2 "x86_64_general_operand" "rme,re")) 5062 (const_int 0))) 5063 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") 5064 (plus:DI (match_dup 1) (match_dup 2)))] 5065 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 5066 && ix86_binary_operator_ok (PLUS, DImode, operands) 5067 /* Current assemblers are broken and do not allow @GOTOFF in 5068 ought but a memory context. */ 5069 && ! pic_symbolic_operand (operands[2], VOIDmode)" 5070{ 5071 switch (get_attr_type (insn)) 5072 { 5073 case TYPE_INCDEC: 5074 if (! rtx_equal_p (operands[0], operands[1])) 5075 abort (); 5076 if (operands[2] == const1_rtx) 5077 return "inc{q}\t%0"; 5078 else if (operands[2] == constm1_rtx) 5079 return "dec{q}\t%0"; 5080 else 5081 abort (); 5082 5083 default: 5084 if (! rtx_equal_p (operands[0], operands[1])) 5085 abort (); 5086 /* ???? We ought to handle there the 32bit case too 5087 - do we need new constrant? */ 5088 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5089 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5090 if (GET_CODE (operands[2]) == CONST_INT 5091 /* Avoid overflows. */ 5092 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))) 5093 && (INTVAL (operands[2]) == 128 5094 || (INTVAL (operands[2]) < 0 5095 && INTVAL (operands[2]) != -128))) 5096 { 5097 operands[2] = GEN_INT (-INTVAL (operands[2])); 5098 return "sub{q}\t{%2, %0|%0, %2}"; 5099 } 5100 return "add{q}\t{%2, %0|%0, %2}"; 5101 } 5102} 5103 [(set (attr "type") 5104 (if_then_else (match_operand:DI 2 "incdec_operand" "") 5105 (const_string "incdec") 5106 (const_string "alu"))) 5107 (set_attr "mode" "DI")]) 5108 5109(define_insn "*adddi_3_rex64" 5110 [(set (reg 17) 5111 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme")) 5112 (match_operand:DI 1 "x86_64_general_operand" "%0"))) 5113 (clobber (match_scratch:DI 0 "=r"))] 5114 "TARGET_64BIT 5115 && ix86_match_ccmode (insn, CCZmode) 5116 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) 5117 /* Current assemblers are broken and do not allow @GOTOFF in 5118 ought but a memory context. */ 5119 && ! pic_symbolic_operand (operands[2], VOIDmode)" 5120{ 5121 switch (get_attr_type (insn)) 5122 { 5123 case TYPE_INCDEC: 5124 if (! rtx_equal_p (operands[0], operands[1])) 5125 abort (); 5126 if (operands[2] == const1_rtx) 5127 return "inc{q}\t%0"; 5128 else if (operands[2] == constm1_rtx) 5129 return "dec{q}\t%0"; 5130 else 5131 abort (); 5132 5133 default: 5134 if (! rtx_equal_p (operands[0], operands[1])) 5135 abort (); 5136 /* ???? We ought to handle there the 32bit case too 5137 - do we need new constrant? */ 5138 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5139 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5140 if (GET_CODE (operands[2]) == CONST_INT 5141 /* Avoid overflows. */ 5142 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))) 5143 && (INTVAL (operands[2]) == 128 5144 || (INTVAL (operands[2]) < 0 5145 && INTVAL (operands[2]) != -128))) 5146 { 5147 operands[2] = GEN_INT (-INTVAL (operands[2])); 5148 return "sub{q}\t{%2, %0|%0, %2}"; 5149 } 5150 return "add{q}\t{%2, %0|%0, %2}"; 5151 } 5152} 5153 [(set (attr "type") 5154 (if_then_else (match_operand:DI 2 "incdec_operand" "") 5155 (const_string "incdec") 5156 (const_string "alu"))) 5157 (set_attr "mode" "DI")]) 5158 5159; For comparisons against 1, -1 and 128, we may generate better code 5160; by converting cmp to add, inc or dec as done by peephole2. This pattern 5161; is matched then. We can't accept general immediate, because for 5162; case of overflows, the result is messed up. 5163; This pattern also don't hold of 0x8000000000000000, since the value overflows 5164; when negated. 5165; Also carry flag is reversed compared to cmp, so this conversion is valid 5166; only for comparisons not depending on it. 5167(define_insn "*adddi_4_rex64" 5168 [(set (reg 17) 5169 (compare (match_operand:DI 1 "nonimmediate_operand" "0") 5170 (match_operand:DI 2 "x86_64_immediate_operand" "e"))) 5171 (clobber (match_scratch:DI 0 "=rm"))] 5172 "TARGET_64BIT 5173 && ix86_match_ccmode (insn, CCGCmode)" 5174{ 5175 switch (get_attr_type (insn)) 5176 { 5177 case TYPE_INCDEC: 5178 if (operands[2] == constm1_rtx) 5179 return "inc{q}\t%0"; 5180 else if (operands[2] == const1_rtx) 5181 return "dec{q}\t%0"; 5182 else 5183 abort(); 5184 5185 default: 5186 if (! rtx_equal_p (operands[0], operands[1])) 5187 abort (); 5188 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5189 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5190 if ((INTVAL (operands[2]) == -128 5191 || (INTVAL (operands[2]) > 0 5192 && INTVAL (operands[2]) != 128)) 5193 /* Avoid overflows. */ 5194 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))) 5195 return "sub{q}\t{%2, %0|%0, %2}"; 5196 operands[2] = GEN_INT (-INTVAL (operands[2])); 5197 return "add{q}\t{%2, %0|%0, %2}"; 5198 } 5199} 5200 [(set (attr "type") 5201 (if_then_else (match_operand:DI 2 "incdec_operand" "") 5202 (const_string "incdec") 5203 (const_string "alu"))) 5204 (set_attr "mode" "DI")]) 5205 5206(define_insn "*adddi_5_rex64" 5207 [(set (reg 17) 5208 (compare 5209 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") 5210 (match_operand:DI 2 "x86_64_general_operand" "rme")) 5211 (const_int 0))) 5212 (clobber (match_scratch:DI 0 "=r"))] 5213 "TARGET_64BIT 5214 && ix86_match_ccmode (insn, CCGOCmode) 5215 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) 5216 /* Current assemblers are broken and do not allow @GOTOFF in 5217 ought but a memory context. */ 5218 && ! pic_symbolic_operand (operands[2], VOIDmode)" 5219{ 5220 switch (get_attr_type (insn)) 5221 { 5222 case TYPE_INCDEC: 5223 if (! rtx_equal_p (operands[0], operands[1])) 5224 abort (); 5225 if (operands[2] == const1_rtx) 5226 return "inc{q}\t%0"; 5227 else if (operands[2] == constm1_rtx) 5228 return "dec{q}\t%0"; 5229 else 5230 abort(); 5231 5232 default: 5233 if (! rtx_equal_p (operands[0], operands[1])) 5234 abort (); 5235 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5236 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5237 if (GET_CODE (operands[2]) == CONST_INT 5238 /* Avoid overflows. */ 5239 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))) 5240 && (INTVAL (operands[2]) == 128 5241 || (INTVAL (operands[2]) < 0 5242 && INTVAL (operands[2]) != -128))) 5243 { 5244 operands[2] = GEN_INT (-INTVAL (operands[2])); 5245 return "sub{q}\t{%2, %0|%0, %2}"; 5246 } 5247 return "add{q}\t{%2, %0|%0, %2}"; 5248 } 5249} 5250 [(set (attr "type") 5251 (if_then_else (match_operand:DI 2 "incdec_operand" "") 5252 (const_string "incdec") 5253 (const_string "alu"))) 5254 (set_attr "mode" "DI")]) 5255 5256 5257(define_insn "*addsi_1" 5258 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r") 5259 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r") 5260 (match_operand:SI 2 "general_operand" "rmni,rni,rni"))) 5261 (clobber (reg:CC 17))] 5262 "ix86_binary_operator_ok (PLUS, SImode, operands)" 5263{ 5264 switch (get_attr_type (insn)) 5265 { 5266 case TYPE_LEA: 5267 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); 5268 return "lea{l}\t{%a2, %0|%0, %a2}"; 5269 5270 case TYPE_INCDEC: 5271 if (! rtx_equal_p (operands[0], operands[1])) 5272 abort (); 5273 if (operands[2] == const1_rtx) 5274 return "inc{l}\t%0"; 5275 else if (operands[2] == constm1_rtx) 5276 return "dec{l}\t%0"; 5277 else 5278 abort(); 5279 5280 default: 5281 if (! rtx_equal_p (operands[0], operands[1])) 5282 abort (); 5283 5284 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5285 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5286 if (GET_CODE (operands[2]) == CONST_INT 5287 && (INTVAL (operands[2]) == 128 5288 || (INTVAL (operands[2]) < 0 5289 && INTVAL (operands[2]) != -128))) 5290 { 5291 operands[2] = GEN_INT (-INTVAL (operands[2])); 5292 return "sub{l}\t{%2, %0|%0, %2}"; 5293 } 5294 return "add{l}\t{%2, %0|%0, %2}"; 5295 } 5296} 5297 [(set (attr "type") 5298 (cond [(eq_attr "alternative" "2") 5299 (const_string "lea") 5300 ; Current assemblers are broken and do not allow @GOTOFF in 5301 ; ought but a memory context. 5302 (match_operand:SI 2 "pic_symbolic_operand" "") 5303 (const_string "lea") 5304 (match_operand:SI 2 "incdec_operand" "") 5305 (const_string "incdec") 5306 ] 5307 (const_string "alu"))) 5308 (set_attr "mode" "SI")]) 5309 5310;; Convert lea to the lea pattern to avoid flags dependency. 5311(define_split 5312 [(set (match_operand 0 "register_operand" "") 5313 (plus (match_operand 1 "register_operand" "") 5314 (match_operand 2 "nonmemory_operand" ""))) 5315 (clobber (reg:CC 17))] 5316 "reload_completed 5317 && true_regnum (operands[0]) != true_regnum (operands[1])" 5318 [(const_int 0)] 5319{ 5320 rtx pat; 5321 /* In -fPIC mode the constructs like (const (unspec [symbol_ref])) 5322 may confuse gen_lowpart. */ 5323 if (GET_MODE (operands[0]) != Pmode) 5324 { 5325 operands[1] = gen_lowpart (Pmode, operands[1]); 5326 operands[2] = gen_lowpart (Pmode, operands[2]); 5327 } 5328 operands[0] = gen_lowpart (SImode, operands[0]); 5329 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]); 5330 if (Pmode != SImode) 5331 pat = gen_rtx_SUBREG (SImode, pat, 0); 5332 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); 5333 DONE; 5334}) 5335 5336;; It may seem that nonimmediate operand is proper one for operand 1. 5337;; The addsi_1 pattern allows nonimmediate operand at that place and 5338;; we take care in ix86_binary_operator_ok to not allow two memory 5339;; operands so proper swapping will be done in reload. This allow 5340;; patterns constructed from addsi_1 to match. 5341(define_insn "addsi_1_zext" 5342 [(set (match_operand:DI 0 "register_operand" "=r,r") 5343 (zero_extend:DI 5344 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r") 5345 (match_operand:SI 2 "general_operand" "rmni,rni")))) 5346 (clobber (reg:CC 17))] 5347 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" 5348{ 5349 switch (get_attr_type (insn)) 5350 { 5351 case TYPE_LEA: 5352 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); 5353 return "lea{l}\t{%a2, %k0|%k0, %a2}"; 5354 5355 case TYPE_INCDEC: 5356 if (operands[2] == const1_rtx) 5357 return "inc{l}\t%k0"; 5358 else if (operands[2] == constm1_rtx) 5359 return "dec{l}\t%k0"; 5360 else 5361 abort(); 5362 5363 default: 5364 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5365 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5366 if (GET_CODE (operands[2]) == CONST_INT 5367 && (INTVAL (operands[2]) == 128 5368 || (INTVAL (operands[2]) < 0 5369 && INTVAL (operands[2]) != -128))) 5370 { 5371 operands[2] = GEN_INT (-INTVAL (operands[2])); 5372 return "sub{l}\t{%2, %k0|%k0, %2}"; 5373 } 5374 return "add{l}\t{%2, %k0|%k0, %2}"; 5375 } 5376} 5377 [(set (attr "type") 5378 (cond [(eq_attr "alternative" "1") 5379 (const_string "lea") 5380 ; Current assemblers are broken and do not allow @GOTOFF in 5381 ; ought but a memory context. 5382 (match_operand:SI 2 "pic_symbolic_operand" "") 5383 (const_string "lea") 5384 (match_operand:SI 2 "incdec_operand" "") 5385 (const_string "incdec") 5386 ] 5387 (const_string "alu"))) 5388 (set_attr "mode" "SI")]) 5389 5390;; Convert lea to the lea pattern to avoid flags dependency. 5391(define_split 5392 [(set (match_operand:DI 0 "register_operand" "") 5393 (zero_extend:DI 5394 (plus:SI (match_operand:SI 1 "register_operand" "") 5395 (match_operand:SI 2 "nonmemory_operand" "")))) 5396 (clobber (reg:CC 17))] 5397 "reload_completed 5398 && true_regnum (operands[0]) != true_regnum (operands[1])" 5399 [(set (match_dup 0) 5400 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))] 5401{ 5402 operands[1] = gen_lowpart (Pmode, operands[1]); 5403 operands[2] = gen_lowpart (Pmode, operands[2]); 5404}) 5405 5406(define_insn "*addsi_2" 5407 [(set (reg 17) 5408 (compare 5409 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 5410 (match_operand:SI 2 "general_operand" "rmni,rni")) 5411 (const_int 0))) 5412 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") 5413 (plus:SI (match_dup 1) (match_dup 2)))] 5414 "ix86_match_ccmode (insn, CCGOCmode) 5415 && ix86_binary_operator_ok (PLUS, SImode, operands) 5416 /* Current assemblers are broken and do not allow @GOTOFF in 5417 ought but a memory context. */ 5418 && ! pic_symbolic_operand (operands[2], VOIDmode)" 5419{ 5420 switch (get_attr_type (insn)) 5421 { 5422 case TYPE_INCDEC: 5423 if (! rtx_equal_p (operands[0], operands[1])) 5424 abort (); 5425 if (operands[2] == const1_rtx) 5426 return "inc{l}\t%0"; 5427 else if (operands[2] == constm1_rtx) 5428 return "dec{l}\t%0"; 5429 else 5430 abort(); 5431 5432 default: 5433 if (! rtx_equal_p (operands[0], operands[1])) 5434 abort (); 5435 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5436 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5437 if (GET_CODE (operands[2]) == CONST_INT 5438 && (INTVAL (operands[2]) == 128 5439 || (INTVAL (operands[2]) < 0 5440 && INTVAL (operands[2]) != -128))) 5441 { 5442 operands[2] = GEN_INT (-INTVAL (operands[2])); 5443 return "sub{l}\t{%2, %0|%0, %2}"; 5444 } 5445 return "add{l}\t{%2, %0|%0, %2}"; 5446 } 5447} 5448 [(set (attr "type") 5449 (if_then_else (match_operand:SI 2 "incdec_operand" "") 5450 (const_string "incdec") 5451 (const_string "alu"))) 5452 (set_attr "mode" "SI")]) 5453 5454;; See comment for addsi_1_zext why we do use nonimmediate_operand 5455(define_insn "*addsi_2_zext" 5456 [(set (reg 17) 5457 (compare 5458 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0") 5459 (match_operand:SI 2 "general_operand" "rmni")) 5460 (const_int 0))) 5461 (set (match_operand:DI 0 "register_operand" "=r") 5462 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] 5463 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 5464 && ix86_binary_operator_ok (PLUS, SImode, operands) 5465 /* Current assemblers are broken and do not allow @GOTOFF in 5466 ought but a memory context. */ 5467 && ! pic_symbolic_operand (operands[2], VOIDmode)" 5468{ 5469 switch (get_attr_type (insn)) 5470 { 5471 case TYPE_INCDEC: 5472 if (operands[2] == const1_rtx) 5473 return "inc{l}\t%k0"; 5474 else if (operands[2] == constm1_rtx) 5475 return "dec{l}\t%k0"; 5476 else 5477 abort(); 5478 5479 default: 5480 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5481 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5482 if (GET_CODE (operands[2]) == CONST_INT 5483 && (INTVAL (operands[2]) == 128 5484 || (INTVAL (operands[2]) < 0 5485 && INTVAL (operands[2]) != -128))) 5486 { 5487 operands[2] = GEN_INT (-INTVAL (operands[2])); 5488 return "sub{l}\t{%2, %k0|%k0, %2}"; 5489 } 5490 return "add{l}\t{%2, %k0|%k0, %2}"; 5491 } 5492} 5493 [(set (attr "type") 5494 (if_then_else (match_operand:SI 2 "incdec_operand" "") 5495 (const_string "incdec") 5496 (const_string "alu"))) 5497 (set_attr "mode" "SI")]) 5498 5499(define_insn "*addsi_3" 5500 [(set (reg 17) 5501 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni")) 5502 (match_operand:SI 1 "nonimmediate_operand" "%0"))) 5503 (clobber (match_scratch:SI 0 "=r"))] 5504 "ix86_match_ccmode (insn, CCZmode) 5505 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) 5506 /* Current assemblers are broken and do not allow @GOTOFF in 5507 ought but a memory context. */ 5508 && ! pic_symbolic_operand (operands[2], VOIDmode)" 5509{ 5510 switch (get_attr_type (insn)) 5511 { 5512 case TYPE_INCDEC: 5513 if (! rtx_equal_p (operands[0], operands[1])) 5514 abort (); 5515 if (operands[2] == const1_rtx) 5516 return "inc{l}\t%0"; 5517 else if (operands[2] == constm1_rtx) 5518 return "dec{l}\t%0"; 5519 else 5520 abort(); 5521 5522 default: 5523 if (! rtx_equal_p (operands[0], operands[1])) 5524 abort (); 5525 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5526 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5527 if (GET_CODE (operands[2]) == CONST_INT 5528 && (INTVAL (operands[2]) == 128 5529 || (INTVAL (operands[2]) < 0 5530 && INTVAL (operands[2]) != -128))) 5531 { 5532 operands[2] = GEN_INT (-INTVAL (operands[2])); 5533 return "sub{l}\t{%2, %0|%0, %2}"; 5534 } 5535 return "add{l}\t{%2, %0|%0, %2}"; 5536 } 5537} 5538 [(set (attr "type") 5539 (if_then_else (match_operand:SI 2 "incdec_operand" "") 5540 (const_string "incdec") 5541 (const_string "alu"))) 5542 (set_attr "mode" "SI")]) 5543 5544;; See comment for addsi_1_zext why we do use nonimmediate_operand 5545(define_insn "*addsi_3_zext" 5546 [(set (reg 17) 5547 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni")) 5548 (match_operand:SI 1 "nonimmediate_operand" "%0"))) 5549 (set (match_operand:DI 0 "register_operand" "=r") 5550 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] 5551 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode) 5552 && ix86_binary_operator_ok (PLUS, SImode, operands) 5553 /* Current assemblers are broken and do not allow @GOTOFF in 5554 ought but a memory context. */ 5555 && ! pic_symbolic_operand (operands[2], VOIDmode)" 5556{ 5557 switch (get_attr_type (insn)) 5558 { 5559 case TYPE_INCDEC: 5560 if (operands[2] == const1_rtx) 5561 return "inc{l}\t%k0"; 5562 else if (operands[2] == constm1_rtx) 5563 return "dec{l}\t%k0"; 5564 else 5565 abort(); 5566 5567 default: 5568 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5569 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5570 if (GET_CODE (operands[2]) == CONST_INT 5571 && (INTVAL (operands[2]) == 128 5572 || (INTVAL (operands[2]) < 0 5573 && INTVAL (operands[2]) != -128))) 5574 { 5575 operands[2] = GEN_INT (-INTVAL (operands[2])); 5576 return "sub{l}\t{%2, %k0|%k0, %2}"; 5577 } 5578 return "add{l}\t{%2, %k0|%k0, %2}"; 5579 } 5580} 5581 [(set (attr "type") 5582 (if_then_else (match_operand:SI 2 "incdec_operand" "") 5583 (const_string "incdec") 5584 (const_string "alu"))) 5585 (set_attr "mode" "SI")]) 5586 5587; For comparisons agains 1, -1 and 128, we may generate better code 5588; by converting cmp to add, inc or dec as done by peephole2. This pattern 5589; is matched then. We can't accept general immediate, because for 5590; case of overflows, the result is messed up. 5591; This pattern also don't hold of 0x80000000, since the value overflows 5592; when negated. 5593; Also carry flag is reversed compared to cmp, so this conversion is valid 5594; only for comparisons not depending on it. 5595(define_insn "*addsi_4" 5596 [(set (reg 17) 5597 (compare (match_operand:SI 1 "nonimmediate_operand" "0") 5598 (match_operand:SI 2 "const_int_operand" "n"))) 5599 (clobber (match_scratch:SI 0 "=rm"))] 5600 "ix86_match_ccmode (insn, CCGCmode) 5601 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000" 5602{ 5603 switch (get_attr_type (insn)) 5604 { 5605 case TYPE_INCDEC: 5606 if (operands[2] == constm1_rtx) 5607 return "inc{l}\t%0"; 5608 else if (operands[2] == const1_rtx) 5609 return "dec{l}\t%0"; 5610 else 5611 abort(); 5612 5613 default: 5614 if (! rtx_equal_p (operands[0], operands[1])) 5615 abort (); 5616 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5617 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5618 if ((INTVAL (operands[2]) == -128 5619 || (INTVAL (operands[2]) > 0 5620 && INTVAL (operands[2]) != 128))) 5621 return "sub{l}\t{%2, %0|%0, %2}"; 5622 operands[2] = GEN_INT (-INTVAL (operands[2])); 5623 return "add{l}\t{%2, %0|%0, %2}"; 5624 } 5625} 5626 [(set (attr "type") 5627 (if_then_else (match_operand:SI 2 "incdec_operand" "") 5628 (const_string "incdec") 5629 (const_string "alu"))) 5630 (set_attr "mode" "SI")]) 5631 5632(define_insn "*addsi_5" 5633 [(set (reg 17) 5634 (compare 5635 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0") 5636 (match_operand:SI 2 "general_operand" "rmni")) 5637 (const_int 0))) 5638 (clobber (match_scratch:SI 0 "=r"))] 5639 "ix86_match_ccmode (insn, CCGOCmode) 5640 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) 5641 /* Current assemblers are broken and do not allow @GOTOFF in 5642 ought but a memory context. */ 5643 && ! pic_symbolic_operand (operands[2], VOIDmode)" 5644{ 5645 switch (get_attr_type (insn)) 5646 { 5647 case TYPE_INCDEC: 5648 if (! rtx_equal_p (operands[0], operands[1])) 5649 abort (); 5650 if (operands[2] == const1_rtx) 5651 return "inc{l}\t%0"; 5652 else if (operands[2] == constm1_rtx) 5653 return "dec{l}\t%0"; 5654 else 5655 abort(); 5656 5657 default: 5658 if (! rtx_equal_p (operands[0], operands[1])) 5659 abort (); 5660 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5661 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5662 if (GET_CODE (operands[2]) == CONST_INT 5663 && (INTVAL (operands[2]) == 128 5664 || (INTVAL (operands[2]) < 0 5665 && INTVAL (operands[2]) != -128))) 5666 { 5667 operands[2] = GEN_INT (-INTVAL (operands[2])); 5668 return "sub{l}\t{%2, %0|%0, %2}"; 5669 } 5670 return "add{l}\t{%2, %0|%0, %2}"; 5671 } 5672} 5673 [(set (attr "type") 5674 (if_then_else (match_operand:SI 2 "incdec_operand" "") 5675 (const_string "incdec") 5676 (const_string "alu"))) 5677 (set_attr "mode" "SI")]) 5678 5679(define_expand "addhi3" 5680 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") 5681 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "") 5682 (match_operand:HI 2 "general_operand" ""))) 5683 (clobber (reg:CC 17))])] 5684 "TARGET_HIMODE_MATH" 5685 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;") 5686 5687;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah 5688;; type optimizations enabled by define-splits. This is not important 5689;; for PII, and in fact harmful because of partial register stalls. 5690 5691(define_insn "*addhi_1_lea" 5692 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r") 5693 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r") 5694 (match_operand:HI 2 "general_operand" "ri,rm,rni"))) 5695 (clobber (reg:CC 17))] 5696 "!TARGET_PARTIAL_REG_STALL 5697 && ix86_binary_operator_ok (PLUS, HImode, operands)" 5698{ 5699 switch (get_attr_type (insn)) 5700 { 5701 case TYPE_LEA: 5702 return "#"; 5703 case TYPE_INCDEC: 5704 if (operands[2] == const1_rtx) 5705 return "inc{w}\t%0"; 5706 else if (operands[2] == constm1_rtx) 5707 return "dec{w}\t%0"; 5708 abort(); 5709 5710 default: 5711 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5712 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5713 if (GET_CODE (operands[2]) == CONST_INT 5714 && (INTVAL (operands[2]) == 128 5715 || (INTVAL (operands[2]) < 0 5716 && INTVAL (operands[2]) != -128))) 5717 { 5718 operands[2] = GEN_INT (-INTVAL (operands[2])); 5719 return "sub{w}\t{%2, %0|%0, %2}"; 5720 } 5721 return "add{w}\t{%2, %0|%0, %2}"; 5722 } 5723} 5724 [(set (attr "type") 5725 (if_then_else (eq_attr "alternative" "2") 5726 (const_string "lea") 5727 (if_then_else (match_operand:HI 2 "incdec_operand" "") 5728 (const_string "incdec") 5729 (const_string "alu")))) 5730 (set_attr "mode" "HI,HI,SI")]) 5731 5732(define_insn "*addhi_1" 5733 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") 5734 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") 5735 (match_operand:HI 2 "general_operand" "ri,rm"))) 5736 (clobber (reg:CC 17))] 5737 "TARGET_PARTIAL_REG_STALL 5738 && ix86_binary_operator_ok (PLUS, HImode, operands)" 5739{ 5740 switch (get_attr_type (insn)) 5741 { 5742 case TYPE_INCDEC: 5743 if (operands[2] == const1_rtx) 5744 return "inc{w}\t%0"; 5745 else if (operands[2] == constm1_rtx) 5746 return "dec{w}\t%0"; 5747 abort(); 5748 5749 default: 5750 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5751 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5752 if (GET_CODE (operands[2]) == CONST_INT 5753 && (INTVAL (operands[2]) == 128 5754 || (INTVAL (operands[2]) < 0 5755 && INTVAL (operands[2]) != -128))) 5756 { 5757 operands[2] = GEN_INT (-INTVAL (operands[2])); 5758 return "sub{w}\t{%2, %0|%0, %2}"; 5759 } 5760 return "add{w}\t{%2, %0|%0, %2}"; 5761 } 5762} 5763 [(set (attr "type") 5764 (if_then_else (match_operand:HI 2 "incdec_operand" "") 5765 (const_string "incdec") 5766 (const_string "alu"))) 5767 (set_attr "mode" "HI")]) 5768 5769(define_insn "*addhi_2" 5770 [(set (reg 17) 5771 (compare 5772 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") 5773 (match_operand:HI 2 "general_operand" "rmni,rni")) 5774 (const_int 0))) 5775 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") 5776 (plus:HI (match_dup 1) (match_dup 2)))] 5777 "ix86_match_ccmode (insn, CCGOCmode) 5778 && ix86_binary_operator_ok (PLUS, HImode, operands)" 5779{ 5780 switch (get_attr_type (insn)) 5781 { 5782 case TYPE_INCDEC: 5783 if (operands[2] == const1_rtx) 5784 return "inc{w}\t%0"; 5785 else if (operands[2] == constm1_rtx) 5786 return "dec{w}\t%0"; 5787 abort(); 5788 5789 default: 5790 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5791 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5792 if (GET_CODE (operands[2]) == CONST_INT 5793 && (INTVAL (operands[2]) == 128 5794 || (INTVAL (operands[2]) < 0 5795 && INTVAL (operands[2]) != -128))) 5796 { 5797 operands[2] = GEN_INT (-INTVAL (operands[2])); 5798 return "sub{w}\t{%2, %0|%0, %2}"; 5799 } 5800 return "add{w}\t{%2, %0|%0, %2}"; 5801 } 5802} 5803 [(set (attr "type") 5804 (if_then_else (match_operand:HI 2 "incdec_operand" "") 5805 (const_string "incdec") 5806 (const_string "alu"))) 5807 (set_attr "mode" "HI")]) 5808 5809(define_insn "*addhi_3" 5810 [(set (reg 17) 5811 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni")) 5812 (match_operand:HI 1 "nonimmediate_operand" "%0"))) 5813 (clobber (match_scratch:HI 0 "=r"))] 5814 "ix86_match_ccmode (insn, CCZmode) 5815 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 5816{ 5817 switch (get_attr_type (insn)) 5818 { 5819 case TYPE_INCDEC: 5820 if (operands[2] == const1_rtx) 5821 return "inc{w}\t%0"; 5822 else if (operands[2] == constm1_rtx) 5823 return "dec{w}\t%0"; 5824 abort(); 5825 5826 default: 5827 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5828 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5829 if (GET_CODE (operands[2]) == CONST_INT 5830 && (INTVAL (operands[2]) == 128 5831 || (INTVAL (operands[2]) < 0 5832 && INTVAL (operands[2]) != -128))) 5833 { 5834 operands[2] = GEN_INT (-INTVAL (operands[2])); 5835 return "sub{w}\t{%2, %0|%0, %2}"; 5836 } 5837 return "add{w}\t{%2, %0|%0, %2}"; 5838 } 5839} 5840 [(set (attr "type") 5841 (if_then_else (match_operand:HI 2 "incdec_operand" "") 5842 (const_string "incdec") 5843 (const_string "alu"))) 5844 (set_attr "mode" "HI")]) 5845 5846; See comments above addsi_3_imm for details. 5847(define_insn "*addhi_4" 5848 [(set (reg 17) 5849 (compare (match_operand:HI 1 "nonimmediate_operand" "0") 5850 (match_operand:HI 2 "const_int_operand" "n"))) 5851 (clobber (match_scratch:HI 0 "=rm"))] 5852 "ix86_match_ccmode (insn, CCGCmode) 5853 && (INTVAL (operands[2]) & 0xffff) != 0x8000" 5854{ 5855 switch (get_attr_type (insn)) 5856 { 5857 case TYPE_INCDEC: 5858 if (operands[2] == constm1_rtx) 5859 return "inc{w}\t%0"; 5860 else if (operands[2] == const1_rtx) 5861 return "dec{w}\t%0"; 5862 else 5863 abort(); 5864 5865 default: 5866 if (! rtx_equal_p (operands[0], operands[1])) 5867 abort (); 5868 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5869 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5870 if ((INTVAL (operands[2]) == -128 5871 || (INTVAL (operands[2]) > 0 5872 && INTVAL (operands[2]) != 128))) 5873 return "sub{w}\t{%2, %0|%0, %2}"; 5874 operands[2] = GEN_INT (-INTVAL (operands[2])); 5875 return "add{w}\t{%2, %0|%0, %2}"; 5876 } 5877} 5878 [(set (attr "type") 5879 (if_then_else (match_operand:HI 2 "incdec_operand" "") 5880 (const_string "incdec") 5881 (const_string "alu"))) 5882 (set_attr "mode" "SI")]) 5883 5884 5885(define_insn "*addhi_5" 5886 [(set (reg 17) 5887 (compare 5888 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0") 5889 (match_operand:HI 2 "general_operand" "rmni")) 5890 (const_int 0))) 5891 (clobber (match_scratch:HI 0 "=r"))] 5892 "ix86_match_ccmode (insn, CCGOCmode) 5893 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 5894{ 5895 switch (get_attr_type (insn)) 5896 { 5897 case TYPE_INCDEC: 5898 if (operands[2] == const1_rtx) 5899 return "inc{w}\t%0"; 5900 else if (operands[2] == constm1_rtx) 5901 return "dec{w}\t%0"; 5902 abort(); 5903 5904 default: 5905 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5906 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5907 if (GET_CODE (operands[2]) == CONST_INT 5908 && (INTVAL (operands[2]) == 128 5909 || (INTVAL (operands[2]) < 0 5910 && INTVAL (operands[2]) != -128))) 5911 { 5912 operands[2] = GEN_INT (-INTVAL (operands[2])); 5913 return "sub{w}\t{%2, %0|%0, %2}"; 5914 } 5915 return "add{w}\t{%2, %0|%0, %2}"; 5916 } 5917} 5918 [(set (attr "type") 5919 (if_then_else (match_operand:HI 2 "incdec_operand" "") 5920 (const_string "incdec") 5921 (const_string "alu"))) 5922 (set_attr "mode" "HI")]) 5923 5924(define_expand "addqi3" 5925 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "") 5926 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "") 5927 (match_operand:QI 2 "general_operand" ""))) 5928 (clobber (reg:CC 17))])] 5929 "TARGET_QIMODE_MATH" 5930 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;") 5931 5932;; %%% Potential partial reg stall on alternative 2. What to do? 5933(define_insn "*addqi_1_lea" 5934 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r") 5935 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r") 5936 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn"))) 5937 (clobber (reg:CC 17))] 5938 "!TARGET_PARTIAL_REG_STALL 5939 && ix86_binary_operator_ok (PLUS, QImode, operands)" 5940{ 5941 int widen = (which_alternative == 2); 5942 switch (get_attr_type (insn)) 5943 { 5944 case TYPE_LEA: 5945 return "#"; 5946 case TYPE_INCDEC: 5947 if (operands[2] == const1_rtx) 5948 return widen ? "inc{l}\t%k0" : "inc{b}\t%0"; 5949 else if (operands[2] == constm1_rtx) 5950 return widen ? "dec{l}\t%k0" : "dec{b}\t%0"; 5951 abort(); 5952 5953 default: 5954 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 5955 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 5956 if (GET_CODE (operands[2]) == CONST_INT 5957 && (INTVAL (operands[2]) == 128 5958 || (INTVAL (operands[2]) < 0 5959 && INTVAL (operands[2]) != -128))) 5960 { 5961 operands[2] = GEN_INT (-INTVAL (operands[2])); 5962 if (widen) 5963 return "sub{l}\t{%2, %k0|%k0, %2}"; 5964 else 5965 return "sub{b}\t{%2, %0|%0, %2}"; 5966 } 5967 if (widen) 5968 return "add{l}\t{%k2, %k0|%k0, %k2}"; 5969 else 5970 return "add{b}\t{%2, %0|%0, %2}"; 5971 } 5972} 5973 [(set (attr "type") 5974 (if_then_else (eq_attr "alternative" "3") 5975 (const_string "lea") 5976 (if_then_else (match_operand:QI 2 "incdec_operand" "") 5977 (const_string "incdec") 5978 (const_string "alu")))) 5979 (set_attr "mode" "QI,QI,SI,SI")]) 5980 5981(define_insn "*addqi_1" 5982 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") 5983 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") 5984 (match_operand:QI 2 "general_operand" "qn,qmn,rn"))) 5985 (clobber (reg:CC 17))] 5986 "TARGET_PARTIAL_REG_STALL 5987 && ix86_binary_operator_ok (PLUS, QImode, operands)" 5988{ 5989 int widen = (which_alternative == 2); 5990 switch (get_attr_type (insn)) 5991 { 5992 case TYPE_INCDEC: 5993 if (operands[2] == const1_rtx) 5994 return widen ? "inc{l}\t%k0" : "inc{b}\t%0"; 5995 else if (operands[2] == constm1_rtx) 5996 return widen ? "dec{l}\t%k0" : "dec{b}\t%0"; 5997 abort(); 5998 5999 default: 6000 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. 6001 Exceptions: -128 encodes smaller than 128, so swap sign and op. */ 6002 if (GET_CODE (operands[2]) == CONST_INT 6003 && (INTVAL (operands[2]) == 128 6004 || (INTVAL (operands[2]) < 0 6005 && INTVAL (operands[2]) != -128))) 6006 { 6007 operands[2] = GEN_INT (-INTVAL (operands[2])); 6008 if (widen) 6009 return "sub{l}\t{%2, %k0|%k0, %2}"; 6010 else 6011 return "sub{b}\t{%2, %0|%0, %2}"; 6012 } 6013 if (widen) 6014 return "add{l}\t{%k2, %k0|%k0, %k2}"; 6015 else 6016 return "add{b}\t{%2, %0|%0, %2}"; 6017 } 6018} 6019 [(set (attr "type") 6020 (if_then_else (match_operand:QI 2 "incdec_operand" "") 6021 (const_string "incdec") 6022 (const_string "alu"))) 6023 (set_attr "mode" "QI,QI,SI")]) 6024 6025(define_insn "*addqi_1_slp" 6026 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) 6027 (plus:QI (match_dup 0) 6028 (match_operand:QI 1 "general_operand" "qn,qnm"))) 6029 (clobber (reg:CC 17))] 6030 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 6031 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 6032{ 6033 switch (get_attr_type (insn)) 6034 { 6035 case TYPE_INCDEC: 6036 if (operands[1] == const1_rtx) 6037 return "inc{b}\t%0"; 6038 else if (operands[1] == constm1_rtx) 6039 return "dec{b}\t%0"; 6040 abort(); 6041 6042 default: 6043 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */ 6044 if (GET_CODE (operands[1]) == CONST_INT 6045 && INTVAL (operands[1]) < 0) 6046 { 6047 operands[2] = GEN_INT (-INTVAL (operands[2])); 6048 return "sub{b}\t{%1, %0|%0, %1}"; 6049 } 6050 return "add{b}\t{%1, %0|%0, %1}"; 6051 } 6052} 6053 [(set (attr "type") 6054 (if_then_else (match_operand:QI 2 "incdec_operand" "") 6055 (const_string "incdec") 6056 (const_string "alu1"))) 6057 (set_attr "mode" "QI")]) 6058 6059(define_insn "*addqi_2" 6060 [(set (reg 17) 6061 (compare 6062 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") 6063 (match_operand:QI 2 "general_operand" "qmni,qni")) 6064 (const_int 0))) 6065 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm") 6066 (plus:QI (match_dup 1) (match_dup 2)))] 6067 "ix86_match_ccmode (insn, CCGOCmode) 6068 && ix86_binary_operator_ok (PLUS, QImode, operands)" 6069{ 6070 switch (get_attr_type (insn)) 6071 { 6072 case TYPE_INCDEC: 6073 if (operands[2] == const1_rtx) 6074 return "inc{b}\t%0"; 6075 else if (operands[2] == constm1_rtx 6076 || (GET_CODE (operands[2]) == CONST_INT 6077 && INTVAL (operands[2]) == 255)) 6078 return "dec{b}\t%0"; 6079 abort(); 6080 6081 default: 6082 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */ 6083 if (GET_CODE (operands[2]) == CONST_INT 6084 && INTVAL (operands[2]) < 0) 6085 { 6086 operands[2] = GEN_INT (-INTVAL (operands[2])); 6087 return "sub{b}\t{%2, %0|%0, %2}"; 6088 } 6089 return "add{b}\t{%2, %0|%0, %2}"; 6090 } 6091} 6092 [(set (attr "type") 6093 (if_then_else (match_operand:QI 2 "incdec_operand" "") 6094 (const_string "incdec") 6095 (const_string "alu"))) 6096 (set_attr "mode" "QI")]) 6097 6098(define_insn "*addqi_3" 6099 [(set (reg 17) 6100 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni")) 6101 (match_operand:QI 1 "nonimmediate_operand" "%0"))) 6102 (clobber (match_scratch:QI 0 "=q"))] 6103 "ix86_match_ccmode (insn, CCZmode) 6104 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6105{ 6106 switch (get_attr_type (insn)) 6107 { 6108 case TYPE_INCDEC: 6109 if (operands[2] == const1_rtx) 6110 return "inc{b}\t%0"; 6111 else if (operands[2] == constm1_rtx 6112 || (GET_CODE (operands[2]) == CONST_INT 6113 && INTVAL (operands[2]) == 255)) 6114 return "dec{b}\t%0"; 6115 abort(); 6116 6117 default: 6118 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */ 6119 if (GET_CODE (operands[2]) == CONST_INT 6120 && INTVAL (operands[2]) < 0) 6121 { 6122 operands[2] = GEN_INT (-INTVAL (operands[2])); 6123 return "sub{b}\t{%2, %0|%0, %2}"; 6124 } 6125 return "add{b}\t{%2, %0|%0, %2}"; 6126 } 6127} 6128 [(set (attr "type") 6129 (if_then_else (match_operand:QI 2 "incdec_operand" "") 6130 (const_string "incdec") 6131 (const_string "alu"))) 6132 (set_attr "mode" "QI")]) 6133 6134; See comments above addsi_3_imm for details. 6135(define_insn "*addqi_4" 6136 [(set (reg 17) 6137 (compare (match_operand:QI 1 "nonimmediate_operand" "0") 6138 (match_operand:QI 2 "const_int_operand" "n"))) 6139 (clobber (match_scratch:QI 0 "=qm"))] 6140 "ix86_match_ccmode (insn, CCGCmode) 6141 && (INTVAL (operands[2]) & 0xff) != 0x80" 6142{ 6143 switch (get_attr_type (insn)) 6144 { 6145 case TYPE_INCDEC: 6146 if (operands[2] == constm1_rtx 6147 || (GET_CODE (operands[2]) == CONST_INT 6148 && INTVAL (operands[2]) == 255)) 6149 return "inc{b}\t%0"; 6150 else if (operands[2] == const1_rtx) 6151 return "dec{b}\t%0"; 6152 else 6153 abort(); 6154 6155 default: 6156 if (! rtx_equal_p (operands[0], operands[1])) 6157 abort (); 6158 if (INTVAL (operands[2]) < 0) 6159 { 6160 operands[2] = GEN_INT (-INTVAL (operands[2])); 6161 return "add{b}\t{%2, %0|%0, %2}"; 6162 } 6163 return "sub{b}\t{%2, %0|%0, %2}"; 6164 } 6165} 6166 [(set (attr "type") 6167 (if_then_else (match_operand:HI 2 "incdec_operand" "") 6168 (const_string "incdec") 6169 (const_string "alu"))) 6170 (set_attr "mode" "QI")]) 6171 6172 6173(define_insn "*addqi_5" 6174 [(set (reg 17) 6175 (compare 6176 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0") 6177 (match_operand:QI 2 "general_operand" "qmni")) 6178 (const_int 0))) 6179 (clobber (match_scratch:QI 0 "=q"))] 6180 "ix86_match_ccmode (insn, CCGOCmode) 6181 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6182{ 6183 switch (get_attr_type (insn)) 6184 { 6185 case TYPE_INCDEC: 6186 if (operands[2] == const1_rtx) 6187 return "inc{b}\t%0"; 6188 else if (operands[2] == constm1_rtx 6189 || (GET_CODE (operands[2]) == CONST_INT 6190 && INTVAL (operands[2]) == 255)) 6191 return "dec{b}\t%0"; 6192 abort(); 6193 6194 default: 6195 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */ 6196 if (GET_CODE (operands[2]) == CONST_INT 6197 && INTVAL (operands[2]) < 0) 6198 { 6199 operands[2] = GEN_INT (-INTVAL (operands[2])); 6200 return "sub{b}\t{%2, %0|%0, %2}"; 6201 } 6202 return "add{b}\t{%2, %0|%0, %2}"; 6203 } 6204} 6205 [(set (attr "type") 6206 (if_then_else (match_operand:QI 2 "incdec_operand" "") 6207 (const_string "incdec") 6208 (const_string "alu"))) 6209 (set_attr "mode" "QI")]) 6210 6211 6212(define_insn "addqi_ext_1" 6213 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 6214 (const_int 8) 6215 (const_int 8)) 6216 (plus:SI 6217 (zero_extract:SI 6218 (match_operand 1 "ext_register_operand" "0") 6219 (const_int 8) 6220 (const_int 8)) 6221 (match_operand:QI 2 "general_operand" "Qmn"))) 6222 (clobber (reg:CC 17))] 6223 "!TARGET_64BIT" 6224{ 6225 switch (get_attr_type (insn)) 6226 { 6227 case TYPE_INCDEC: 6228 if (operands[2] == const1_rtx) 6229 return "inc{b}\t%h0"; 6230 else if (operands[2] == constm1_rtx 6231 || (GET_CODE (operands[2]) == CONST_INT 6232 && INTVAL (operands[2]) == 255)) 6233 return "dec{b}\t%h0"; 6234 abort(); 6235 6236 default: 6237 return "add{b}\t{%2, %h0|%h0, %2}"; 6238 } 6239} 6240 [(set (attr "type") 6241 (if_then_else (match_operand:QI 2 "incdec_operand" "") 6242 (const_string "incdec") 6243 (const_string "alu"))) 6244 (set_attr "mode" "QI")]) 6245 6246(define_insn "*addqi_ext_1_rex64" 6247 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 6248 (const_int 8) 6249 (const_int 8)) 6250 (plus:SI 6251 (zero_extract:SI 6252 (match_operand 1 "ext_register_operand" "0") 6253 (const_int 8) 6254 (const_int 8)) 6255 (match_operand:QI 2 "nonmemory_operand" "Qn"))) 6256 (clobber (reg:CC 17))] 6257 "TARGET_64BIT" 6258{ 6259 switch (get_attr_type (insn)) 6260 { 6261 case TYPE_INCDEC: 6262 if (operands[2] == const1_rtx) 6263 return "inc{b}\t%h0"; 6264 else if (operands[2] == constm1_rtx 6265 || (GET_CODE (operands[2]) == CONST_INT 6266 && INTVAL (operands[2]) == 255)) 6267 return "dec{b}\t%h0"; 6268 abort(); 6269 6270 default: 6271 return "add{b}\t{%2, %h0|%h0, %2}"; 6272 } 6273} 6274 [(set (attr "type") 6275 (if_then_else (match_operand:QI 2 "incdec_operand" "") 6276 (const_string "incdec") 6277 (const_string "alu"))) 6278 (set_attr "mode" "QI")]) 6279 6280(define_insn "*addqi_ext_2" 6281 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 6282 (const_int 8) 6283 (const_int 8)) 6284 (plus:SI 6285 (zero_extract:SI 6286 (match_operand 1 "ext_register_operand" "%0") 6287 (const_int 8) 6288 (const_int 8)) 6289 (zero_extract:SI 6290 (match_operand 2 "ext_register_operand" "Q") 6291 (const_int 8) 6292 (const_int 8)))) 6293 (clobber (reg:CC 17))] 6294 "" 6295 "add{b}\t{%h2, %h0|%h0, %h2}" 6296 [(set_attr "type" "alu") 6297 (set_attr "mode" "QI")]) 6298 6299;; The patterns that match these are at the end of this file. 6300 6301(define_expand "addxf3" 6302 [(set (match_operand:XF 0 "register_operand" "") 6303 (plus:XF (match_operand:XF 1 "register_operand" "") 6304 (match_operand:XF 2 "register_operand" "")))] 6305 "!TARGET_64BIT && TARGET_80387" 6306 "") 6307 6308(define_expand "addtf3" 6309 [(set (match_operand:TF 0 "register_operand" "") 6310 (plus:TF (match_operand:TF 1 "register_operand" "") 6311 (match_operand:TF 2 "register_operand" "")))] 6312 "TARGET_80387" 6313 "") 6314 6315(define_expand "adddf3" 6316 [(set (match_operand:DF 0 "register_operand" "") 6317 (plus:DF (match_operand:DF 1 "register_operand" "") 6318 (match_operand:DF 2 "nonimmediate_operand" "")))] 6319 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" 6320 "") 6321 6322(define_expand "addsf3" 6323 [(set (match_operand:SF 0 "register_operand" "") 6324 (plus:SF (match_operand:SF 1 "register_operand" "") 6325 (match_operand:SF 2 "nonimmediate_operand" "")))] 6326 "TARGET_80387 || TARGET_SSE_MATH" 6327 "") 6328 6329;; Subtract instructions 6330 6331;; %%% splits for subsidi3 6332 6333(define_expand "subdi3" 6334 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") 6335 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "") 6336 (match_operand:DI 2 "x86_64_general_operand" ""))) 6337 (clobber (reg:CC 17))])] 6338 "" 6339 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;") 6340 6341(define_insn "*subdi3_1" 6342 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") 6343 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") 6344 (match_operand:DI 2 "general_operand" "roiF,riF"))) 6345 (clobber (reg:CC 17))] 6346 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)" 6347 "#") 6348 6349(define_split 6350 [(set (match_operand:DI 0 "nonimmediate_operand" "") 6351 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "") 6352 (match_operand:DI 2 "general_operand" ""))) 6353 (clobber (reg:CC 17))] 6354 "!TARGET_64BIT && reload_completed" 6355 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2))) 6356 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) 6357 (parallel [(set (match_dup 3) 6358 (minus:SI (match_dup 4) 6359 (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) 6360 (match_dup 5)))) 6361 (clobber (reg:CC 17))])] 6362 "split_di (operands+0, 1, operands+0, operands+3); 6363 split_di (operands+1, 1, operands+1, operands+4); 6364 split_di (operands+2, 1, operands+2, operands+5);") 6365 6366(define_insn "subdi3_carry_rex64" 6367 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") 6368 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") 6369 (plus:DI (ltu:DI (reg:CC 17) (const_int 0)) 6370 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))) 6371 (clobber (reg:CC 17))] 6372 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)" 6373 "sbb{q}\t{%2, %0|%0, %2}" 6374 [(set_attr "type" "alu") 6375 (set_attr "pent_pair" "pu") 6376 (set_attr "ppro_uops" "few") 6377 (set_attr "mode" "DI")]) 6378 6379(define_insn "*subdi_1_rex64" 6380 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") 6381 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") 6382 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) 6383 (clobber (reg:CC 17))] 6384 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)" 6385 "sub{q}\t{%2, %0|%0, %2}" 6386 [(set_attr "type" "alu") 6387 (set_attr "mode" "DI")]) 6388 6389(define_insn "*subdi_2_rex64" 6390 [(set (reg 17) 6391 (compare 6392 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") 6393 (match_operand:DI 2 "x86_64_general_operand" "re,rm")) 6394 (const_int 0))) 6395 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") 6396 (minus:DI (match_dup 1) (match_dup 2)))] 6397 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 6398 && ix86_binary_operator_ok (MINUS, DImode, operands)" 6399 "sub{q}\t{%2, %0|%0, %2}" 6400 [(set_attr "type" "alu") 6401 (set_attr "mode" "DI")]) 6402 6403(define_insn "*subdi_3_rex63" 6404 [(set (reg 17) 6405 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0") 6406 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) 6407 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") 6408 (minus:DI (match_dup 1) (match_dup 2)))] 6409 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode) 6410 && ix86_binary_operator_ok (MINUS, SImode, operands)" 6411 "sub{q}\t{%2, %0|%0, %2}" 6412 [(set_attr "type" "alu") 6413 (set_attr "mode" "DI")]) 6414 6415 6416(define_insn "subsi3_carry" 6417 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 6418 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") 6419 (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) 6420 (match_operand:SI 2 "general_operand" "ri,rm")))) 6421 (clobber (reg:CC 17))] 6422 "ix86_binary_operator_ok (MINUS, SImode, operands)" 6423 "sbb{l}\t{%2, %0|%0, %2}" 6424 [(set_attr "type" "alu") 6425 (set_attr "pent_pair" "pu") 6426 (set_attr "ppro_uops" "few") 6427 (set_attr "mode" "SI")]) 6428 6429(define_insn "subsi3_carry_zext" 6430 [(set (match_operand:DI 0 "register_operand" "=rm,r") 6431 (zero_extend:DI 6432 (minus:SI (match_operand:SI 1 "register_operand" "0,0") 6433 (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) 6434 (match_operand:SI 2 "general_operand" "ri,rm"))))) 6435 (clobber (reg:CC 17))] 6436 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)" 6437 "sbb{l}\t{%2, %k0|%k0, %2}" 6438 [(set_attr "type" "alu") 6439 (set_attr "pent_pair" "pu") 6440 (set_attr "ppro_uops" "few") 6441 (set_attr "mode" "SI")]) 6442 6443(define_expand "subsi3" 6444 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") 6445 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "") 6446 (match_operand:SI 2 "general_operand" ""))) 6447 (clobber (reg:CC 17))])] 6448 "" 6449 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;") 6450 6451(define_insn "*subsi_1" 6452 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 6453 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") 6454 (match_operand:SI 2 "general_operand" "ri,rm"))) 6455 (clobber (reg:CC 17))] 6456 "ix86_binary_operator_ok (MINUS, SImode, operands)" 6457 "sub{l}\t{%2, %0|%0, %2}" 6458 [(set_attr "type" "alu") 6459 (set_attr "mode" "SI")]) 6460 6461(define_insn "*subsi_1_zext" 6462 [(set (match_operand:DI 0 "register_operand" "=r") 6463 (zero_extend:DI 6464 (minus:SI (match_operand:SI 1 "register_operand" "0") 6465 (match_operand:SI 2 "general_operand" "rim")))) 6466 (clobber (reg:CC 17))] 6467 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)" 6468 "sub{l}\t{%2, %k0|%k0, %2}" 6469 [(set_attr "type" "alu") 6470 (set_attr "mode" "SI")]) 6471 6472(define_insn "*subsi_2" 6473 [(set (reg 17) 6474 (compare 6475 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") 6476 (match_operand:SI 2 "general_operand" "ri,rm")) 6477 (const_int 0))) 6478 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 6479 (minus:SI (match_dup 1) (match_dup 2)))] 6480 "ix86_match_ccmode (insn, CCGOCmode) 6481 && ix86_binary_operator_ok (MINUS, SImode, operands)" 6482 "sub{l}\t{%2, %0|%0, %2}" 6483 [(set_attr "type" "alu") 6484 (set_attr "mode" "SI")]) 6485 6486(define_insn "*subsi_2_zext" 6487 [(set (reg 17) 6488 (compare 6489 (minus:SI (match_operand:SI 1 "register_operand" "0") 6490 (match_operand:SI 2 "general_operand" "rim")) 6491 (const_int 0))) 6492 (set (match_operand:DI 0 "register_operand" "=r") 6493 (zero_extend:DI 6494 (minus:SI (match_dup 1) 6495 (match_dup 2))))] 6496 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 6497 && ix86_binary_operator_ok (MINUS, SImode, operands)" 6498 "sub{l}\t{%2, %k0|%k0, %2}" 6499 [(set_attr "type" "alu") 6500 (set_attr "mode" "SI")]) 6501 6502(define_insn "*subsi_3" 6503 [(set (reg 17) 6504 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0") 6505 (match_operand:SI 2 "general_operand" "ri,rm"))) 6506 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 6507 (minus:SI (match_dup 1) (match_dup 2)))] 6508 "ix86_match_ccmode (insn, CCmode) 6509 && ix86_binary_operator_ok (MINUS, SImode, operands)" 6510 "sub{l}\t{%2, %0|%0, %2}" 6511 [(set_attr "type" "alu") 6512 (set_attr "mode" "SI")]) 6513 6514(define_insn "*subsi_3_zext" 6515 [(set (reg 17) 6516 (compare (match_operand:SI 1 "nonimmediate_operand" "0") 6517 (match_operand:SI 2 "general_operand" "rim"))) 6518 (set (match_operand:DI 0 "register_operand" "=r") 6519 (zero_extend:DI 6520 (minus:SI (match_dup 1) 6521 (match_dup 2))))] 6522 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode) 6523 && ix86_binary_operator_ok (MINUS, SImode, operands)" 6524 "sub{q}\t{%2, %0|%0, %2}" 6525 [(set_attr "type" "alu") 6526 (set_attr "mode" "DI")]) 6527 6528(define_expand "subhi3" 6529 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") 6530 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "") 6531 (match_operand:HI 2 "general_operand" ""))) 6532 (clobber (reg:CC 17))])] 6533 "TARGET_HIMODE_MATH" 6534 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;") 6535 6536(define_insn "*subhi_1" 6537 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") 6538 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") 6539 (match_operand:HI 2 "general_operand" "ri,rm"))) 6540 (clobber (reg:CC 17))] 6541 "ix86_binary_operator_ok (MINUS, HImode, operands)" 6542 "sub{w}\t{%2, %0|%0, %2}" 6543 [(set_attr "type" "alu") 6544 (set_attr "mode" "HI")]) 6545 6546(define_insn "*subhi_2" 6547 [(set (reg 17) 6548 (compare 6549 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") 6550 (match_operand:HI 2 "general_operand" "ri,rm")) 6551 (const_int 0))) 6552 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") 6553 (minus:HI (match_dup 1) (match_dup 2)))] 6554 "ix86_match_ccmode (insn, CCGOCmode) 6555 && ix86_binary_operator_ok (MINUS, HImode, operands)" 6556 "sub{w}\t{%2, %0|%0, %2}" 6557 [(set_attr "type" "alu") 6558 (set_attr "mode" "HI")]) 6559 6560(define_insn "*subhi_3" 6561 [(set (reg 17) 6562 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0") 6563 (match_operand:HI 2 "general_operand" "ri,rm"))) 6564 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") 6565 (minus:HI (match_dup 1) (match_dup 2)))] 6566 "ix86_match_ccmode (insn, CCmode) 6567 && ix86_binary_operator_ok (MINUS, HImode, operands)" 6568 "sub{w}\t{%2, %0|%0, %2}" 6569 [(set_attr "type" "alu") 6570 (set_attr "mode" "HI")]) 6571 6572(define_expand "subqi3" 6573 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "") 6574 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "") 6575 (match_operand:QI 2 "general_operand" ""))) 6576 (clobber (reg:CC 17))])] 6577 "TARGET_QIMODE_MATH" 6578 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;") 6579 6580(define_insn "*subqi_1" 6581 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") 6582 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") 6583 (match_operand:QI 2 "general_operand" "qn,qmn"))) 6584 (clobber (reg:CC 17))] 6585 "ix86_binary_operator_ok (MINUS, QImode, operands)" 6586 "sub{b}\t{%2, %0|%0, %2}" 6587 [(set_attr "type" "alu") 6588 (set_attr "mode" "QI")]) 6589 6590(define_insn "*subqi_1_slp" 6591 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) 6592 (minus:QI (match_dup 0) 6593 (match_operand:QI 1 "general_operand" "qn,qmn"))) 6594 (clobber (reg:CC 17))] 6595 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 6596 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 6597 "sub{b}\t{%1, %0|%0, %1}" 6598 [(set_attr "type" "alu1") 6599 (set_attr "mode" "QI")]) 6600 6601(define_insn "*subqi_2" 6602 [(set (reg 17) 6603 (compare 6604 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") 6605 (match_operand:QI 2 "general_operand" "qi,qm")) 6606 (const_int 0))) 6607 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q") 6608 (minus:HI (match_dup 1) (match_dup 2)))] 6609 "ix86_match_ccmode (insn, CCGOCmode) 6610 && ix86_binary_operator_ok (MINUS, QImode, operands)" 6611 "sub{b}\t{%2, %0|%0, %2}" 6612 [(set_attr "type" "alu") 6613 (set_attr "mode" "QI")]) 6614 6615(define_insn "*subqi_3" 6616 [(set (reg 17) 6617 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0") 6618 (match_operand:QI 2 "general_operand" "qi,qm"))) 6619 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q") 6620 (minus:HI (match_dup 1) (match_dup 2)))] 6621 "ix86_match_ccmode (insn, CCmode) 6622 && ix86_binary_operator_ok (MINUS, QImode, operands)" 6623 "sub{b}\t{%2, %0|%0, %2}" 6624 [(set_attr "type" "alu") 6625 (set_attr "mode" "QI")]) 6626 6627;; The patterns that match these are at the end of this file. 6628 6629(define_expand "subxf3" 6630 [(set (match_operand:XF 0 "register_operand" "") 6631 (minus:XF (match_operand:XF 1 "register_operand" "") 6632 (match_operand:XF 2 "register_operand" "")))] 6633 "!TARGET_64BIT && TARGET_80387" 6634 "") 6635 6636(define_expand "subtf3" 6637 [(set (match_operand:TF 0 "register_operand" "") 6638 (minus:TF (match_operand:TF 1 "register_operand" "") 6639 (match_operand:TF 2 "register_operand" "")))] 6640 "TARGET_80387" 6641 "") 6642 6643(define_expand "subdf3" 6644 [(set (match_operand:DF 0 "register_operand" "") 6645 (minus:DF (match_operand:DF 1 "register_operand" "") 6646 (match_operand:DF 2 "nonimmediate_operand" "")))] 6647 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" 6648 "") 6649 6650(define_expand "subsf3" 6651 [(set (match_operand:SF 0 "register_operand" "") 6652 (minus:SF (match_operand:SF 1 "register_operand" "") 6653 (match_operand:SF 2 "nonimmediate_operand" "")))] 6654 "TARGET_80387 || TARGET_SSE_MATH" 6655 "") 6656 6657;; Multiply instructions 6658 6659(define_expand "muldi3" 6660 [(parallel [(set (match_operand:DI 0 "register_operand" "") 6661 (mult:DI (match_operand:DI 1 "register_operand" "") 6662 (match_operand:DI 2 "x86_64_general_operand" ""))) 6663 (clobber (reg:CC 17))])] 6664 "TARGET_64BIT" 6665 "") 6666 6667(define_insn "*muldi3_1_rex64" 6668 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 6669 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0") 6670 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr"))) 6671 (clobber (reg:CC 17))] 6672 "TARGET_64BIT 6673 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6674 "@ 6675 imul{q}\t{%2, %1, %0|%0, %1, %2} 6676 imul{q}\t{%2, %1, %0|%0, %1, %2} 6677 imul{q}\t{%2, %0|%0, %2}" 6678 [(set_attr "type" "imul") 6679 (set_attr "prefix_0f" "0,0,1") 6680 (set_attr "mode" "DI")]) 6681 6682(define_expand "mulsi3" 6683 [(parallel [(set (match_operand:SI 0 "register_operand" "") 6684 (mult:SI (match_operand:SI 1 "register_operand" "") 6685 (match_operand:SI 2 "general_operand" ""))) 6686 (clobber (reg:CC 17))])] 6687 "" 6688 "") 6689 6690(define_insn "*mulsi3_1" 6691 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 6692 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0") 6693 (match_operand:SI 2 "general_operand" "K,i,mr"))) 6694 (clobber (reg:CC 17))] 6695 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" 6696 ; For the {r,0,i} alternative (i.e., register <- register * immediate), 6697 ; there are two ways of writing the exact same machine instruction 6698 ; in assembly language. One, for example, is: 6699 ; 6700 ; imul $12, %eax 6701 ; 6702 ; while the other is: 6703 ; 6704 ; imul $12, %eax, %eax 6705 ; 6706 ; The first is simply short-hand for the latter. But, some assemblers, 6707 ; like the SCO OSR5 COFF assembler, don't handle the first form. 6708 "@ 6709 imul{l}\t{%2, %1, %0|%0, %1, %2} 6710 imul{l}\t{%2, %1, %0|%0, %1, %2} 6711 imul{l}\t{%2, %0|%0, %2}" 6712 [(set_attr "type" "imul") 6713 (set_attr "prefix_0f" "0,0,1") 6714 (set_attr "mode" "SI")]) 6715 6716(define_insn "*mulsi3_1_zext" 6717 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 6718 (zero_extend:DI 6719 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0") 6720 (match_operand:SI 2 "general_operand" "K,i,mr")))) 6721 (clobber (reg:CC 17))] 6722 "TARGET_64BIT 6723 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6724 ; For the {r,0,i} alternative (i.e., register <- register * immediate), 6725 ; there are two ways of writing the exact same machine instruction 6726 ; in assembly language. One, for example, is: 6727 ; 6728 ; imul $12, %eax 6729 ; 6730 ; while the other is: 6731 ; 6732 ; imul $12, %eax, %eax 6733 ; 6734 ; The first is simply short-hand for the latter. But, some assemblers, 6735 ; like the SCO OSR5 COFF assembler, don't handle the first form. 6736 "@ 6737 imul{l}\t{%2, %1, %k0|%k0, %1, %2} 6738 imul{l}\t{%2, %1, %k0|%k0, %1, %2} 6739 imul{l}\t{%2, %k0|%k0, %2}" 6740 [(set_attr "type" "imul") 6741 (set_attr "prefix_0f" "0,0,1") 6742 (set_attr "mode" "SI")]) 6743 6744(define_expand "mulhi3" 6745 [(parallel [(set (match_operand:HI 0 "register_operand" "") 6746 (mult:HI (match_operand:HI 1 "register_operand" "") 6747 (match_operand:HI 2 "general_operand" ""))) 6748 (clobber (reg:CC 17))])] 6749 "TARGET_HIMODE_MATH" 6750 "") 6751 6752(define_insn "*mulhi3_1" 6753 [(set (match_operand:HI 0 "register_operand" "=r,r,r") 6754 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0") 6755 (match_operand:HI 2 "general_operand" "K,i,mr"))) 6756 (clobber (reg:CC 17))] 6757 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" 6758 ; %%% There was a note about "Assembler has weird restrictions", 6759 ; concerning alternative 1 when op1 == op0. True? 6760 "@ 6761 imul{w}\t{%2, %1, %0|%0, %1, %2} 6762 imul{w}\t{%2, %1, %0|%0, %1, %2} 6763 imul{w}\t{%2, %0|%0, %2}" 6764 [(set_attr "type" "imul") 6765 (set_attr "prefix_0f" "0,0,1") 6766 (set_attr "mode" "HI")]) 6767 6768(define_expand "mulqi3" 6769 [(parallel [(set (match_operand:QI 0 "register_operand" "") 6770 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "") 6771 (match_operand:QI 2 "register_operand" ""))) 6772 (clobber (reg:CC 17))])] 6773 "TARGET_QIMODE_MATH" 6774 "") 6775 6776(define_insn "*mulqi3_1" 6777 [(set (match_operand:QI 0 "register_operand" "=a") 6778 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0") 6779 (match_operand:QI 2 "nonimmediate_operand" "qm"))) 6780 (clobber (reg:CC 17))] 6781 "TARGET_QIMODE_MATH 6782 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6783 "mul{b}\t%2" 6784 [(set_attr "type" "imul") 6785 (set_attr "length_immediate" "0") 6786 (set_attr "mode" "QI")]) 6787 6788(define_expand "umulqihi3" 6789 [(parallel [(set (match_operand:HI 0 "register_operand" "") 6790 (mult:HI (zero_extend:HI 6791 (match_operand:QI 1 "nonimmediate_operand" "")) 6792 (zero_extend:HI 6793 (match_operand:QI 2 "register_operand" "")))) 6794 (clobber (reg:CC 17))])] 6795 "TARGET_QIMODE_MATH" 6796 "") 6797 6798(define_insn "*umulqihi3_1" 6799 [(set (match_operand:HI 0 "register_operand" "=a") 6800 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) 6801 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) 6802 (clobber (reg:CC 17))] 6803 "TARGET_QIMODE_MATH 6804 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6805 "mul{b}\t%2" 6806 [(set_attr "type" "imul") 6807 (set_attr "length_immediate" "0") 6808 (set_attr "mode" "QI")]) 6809 6810(define_expand "mulqihi3" 6811 [(parallel [(set (match_operand:HI 0 "register_operand" "") 6812 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")) 6813 (sign_extend:HI (match_operand:QI 2 "register_operand" "")))) 6814 (clobber (reg:CC 17))])] 6815 "TARGET_QIMODE_MATH" 6816 "") 6817 6818(define_insn "*mulqihi3_insn" 6819 [(set (match_operand:HI 0 "register_operand" "=a") 6820 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) 6821 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) 6822 (clobber (reg:CC 17))] 6823 "TARGET_QIMODE_MATH 6824 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6825 "imul{b}\t%2" 6826 [(set_attr "type" "imul") 6827 (set_attr "length_immediate" "0") 6828 (set_attr "mode" "QI")]) 6829 6830(define_expand "umulditi3" 6831 [(parallel [(set (match_operand:TI 0 "register_operand" "") 6832 (mult:TI (zero_extend:TI 6833 (match_operand:DI 1 "nonimmediate_operand" "")) 6834 (zero_extend:TI 6835 (match_operand:DI 2 "register_operand" "")))) 6836 (clobber (reg:CC 17))])] 6837 "TARGET_64BIT" 6838 "") 6839 6840(define_insn "*umulditi3_insn" 6841 [(set (match_operand:TI 0 "register_operand" "=A") 6842 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0")) 6843 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) 6844 (clobber (reg:CC 17))] 6845 "TARGET_64BIT 6846 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6847 "mul{q}\t%2" 6848 [(set_attr "type" "imul") 6849 (set_attr "ppro_uops" "few") 6850 (set_attr "length_immediate" "0") 6851 (set_attr "mode" "DI")]) 6852 6853;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers 6854(define_expand "umulsidi3" 6855 [(parallel [(set (match_operand:DI 0 "register_operand" "") 6856 (mult:DI (zero_extend:DI 6857 (match_operand:SI 1 "nonimmediate_operand" "")) 6858 (zero_extend:DI 6859 (match_operand:SI 2 "register_operand" "")))) 6860 (clobber (reg:CC 17))])] 6861 "!TARGET_64BIT" 6862 "") 6863 6864(define_insn "*umulsidi3_insn" 6865 [(set (match_operand:DI 0 "register_operand" "=A") 6866 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0")) 6867 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) 6868 (clobber (reg:CC 17))] 6869 "!TARGET_64BIT 6870 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6871 "mul{l}\t%2" 6872 [(set_attr "type" "imul") 6873 (set_attr "ppro_uops" "few") 6874 (set_attr "length_immediate" "0") 6875 (set_attr "mode" "SI")]) 6876 6877(define_expand "mulditi3" 6878 [(parallel [(set (match_operand:TI 0 "register_operand" "") 6879 (mult:TI (sign_extend:TI 6880 (match_operand:DI 1 "nonimmediate_operand" "")) 6881 (sign_extend:TI 6882 (match_operand:DI 2 "register_operand" "")))) 6883 (clobber (reg:CC 17))])] 6884 "TARGET_64BIT" 6885 "") 6886 6887(define_insn "*mulditi3_insn" 6888 [(set (match_operand:TI 0 "register_operand" "=A") 6889 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0")) 6890 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) 6891 (clobber (reg:CC 17))] 6892 "TARGET_64BIT 6893 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6894 "imul{q}\t%2" 6895 [(set_attr "type" "imul") 6896 (set_attr "length_immediate" "0") 6897 (set_attr "mode" "DI")]) 6898 6899(define_expand "mulsidi3" 6900 [(parallel [(set (match_operand:DI 0 "register_operand" "") 6901 (mult:DI (sign_extend:DI 6902 (match_operand:SI 1 "nonimmediate_operand" "")) 6903 (sign_extend:DI 6904 (match_operand:SI 2 "register_operand" "")))) 6905 (clobber (reg:CC 17))])] 6906 "!TARGET_64BIT" 6907 "") 6908 6909(define_insn "*mulsidi3_insn" 6910 [(set (match_operand:DI 0 "register_operand" "=A") 6911 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0")) 6912 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) 6913 (clobber (reg:CC 17))] 6914 "!TARGET_64BIT 6915 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6916 "imul{l}\t%2" 6917 [(set_attr "type" "imul") 6918 (set_attr "length_immediate" "0") 6919 (set_attr "mode" "SI")]) 6920 6921(define_expand "umuldi3_highpart" 6922 [(parallel [(set (match_operand:DI 0 "register_operand" "") 6923 (truncate:DI 6924 (lshiftrt:TI 6925 (mult:TI (zero_extend:TI 6926 (match_operand:DI 1 "nonimmediate_operand" "")) 6927 (zero_extend:TI 6928 (match_operand:DI 2 "register_operand" ""))) 6929 (const_int 64)))) 6930 (clobber (match_scratch:DI 3 "")) 6931 (clobber (reg:CC 17))])] 6932 "TARGET_64BIT" 6933 "") 6934 6935(define_insn "*umuldi3_highpart_rex64" 6936 [(set (match_operand:DI 0 "register_operand" "=d") 6937 (truncate:DI 6938 (lshiftrt:TI 6939 (mult:TI (zero_extend:TI 6940 (match_operand:DI 1 "nonimmediate_operand" "%a")) 6941 (zero_extend:TI 6942 (match_operand:DI 2 "nonimmediate_operand" "rm"))) 6943 (const_int 64)))) 6944 (clobber (match_scratch:DI 3 "=1")) 6945 (clobber (reg:CC 17))] 6946 "TARGET_64BIT 6947 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6948 "mul{q}\t%2" 6949 [(set_attr "type" "imul") 6950 (set_attr "ppro_uops" "few") 6951 (set_attr "length_immediate" "0") 6952 (set_attr "mode" "DI")]) 6953 6954(define_expand "umulsi3_highpart" 6955 [(parallel [(set (match_operand:SI 0 "register_operand" "") 6956 (truncate:SI 6957 (lshiftrt:DI 6958 (mult:DI (zero_extend:DI 6959 (match_operand:SI 1 "nonimmediate_operand" "")) 6960 (zero_extend:DI 6961 (match_operand:SI 2 "register_operand" ""))) 6962 (const_int 32)))) 6963 (clobber (match_scratch:SI 3 "")) 6964 (clobber (reg:CC 17))])] 6965 "" 6966 "") 6967 6968(define_insn "*umulsi3_highpart_insn" 6969 [(set (match_operand:SI 0 "register_operand" "=d") 6970 (truncate:SI 6971 (lshiftrt:DI 6972 (mult:DI (zero_extend:DI 6973 (match_operand:SI 1 "nonimmediate_operand" "%a")) 6974 (zero_extend:DI 6975 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 6976 (const_int 32)))) 6977 (clobber (match_scratch:SI 3 "=1")) 6978 (clobber (reg:CC 17))] 6979 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" 6980 "mul{l}\t%2" 6981 [(set_attr "type" "imul") 6982 (set_attr "ppro_uops" "few") 6983 (set_attr "length_immediate" "0") 6984 (set_attr "mode" "SI")]) 6985 6986(define_insn "*umulsi3_highpart_zext" 6987 [(set (match_operand:DI 0 "register_operand" "=d") 6988 (zero_extend:DI (truncate:SI 6989 (lshiftrt:DI 6990 (mult:DI (zero_extend:DI 6991 (match_operand:SI 1 "nonimmediate_operand" "%a")) 6992 (zero_extend:DI 6993 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 6994 (const_int 32))))) 6995 (clobber (match_scratch:SI 3 "=1")) 6996 (clobber (reg:CC 17))] 6997 "TARGET_64BIT 6998 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 6999 "mul{l}\t%2" 7000 [(set_attr "type" "imul") 7001 (set_attr "ppro_uops" "few") 7002 (set_attr "length_immediate" "0") 7003 (set_attr "mode" "SI")]) 7004 7005(define_expand "smuldi3_highpart" 7006 [(parallel [(set (match_operand:DI 0 "register_operand" "=d") 7007 (truncate:DI 7008 (lshiftrt:TI 7009 (mult:TI (sign_extend:TI 7010 (match_operand:DI 1 "nonimmediate_operand" "")) 7011 (sign_extend:TI 7012 (match_operand:DI 2 "register_operand" ""))) 7013 (const_int 64)))) 7014 (clobber (match_scratch:DI 3 "")) 7015 (clobber (reg:CC 17))])] 7016 "TARGET_64BIT" 7017 "") 7018 7019(define_insn "*smuldi3_highpart_rex64" 7020 [(set (match_operand:DI 0 "register_operand" "=d") 7021 (truncate:DI 7022 (lshiftrt:TI 7023 (mult:TI (sign_extend:TI 7024 (match_operand:DI 1 "nonimmediate_operand" "%a")) 7025 (sign_extend:TI 7026 (match_operand:DI 2 "nonimmediate_operand" "rm"))) 7027 (const_int 64)))) 7028 (clobber (match_scratch:DI 3 "=1")) 7029 (clobber (reg:CC 17))] 7030 "TARGET_64BIT 7031 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7032 "imul{q}\t%2" 7033 [(set_attr "type" "imul") 7034 (set_attr "ppro_uops" "few") 7035 (set_attr "mode" "DI")]) 7036 7037(define_expand "smulsi3_highpart" 7038 [(parallel [(set (match_operand:SI 0 "register_operand" "") 7039 (truncate:SI 7040 (lshiftrt:DI 7041 (mult:DI (sign_extend:DI 7042 (match_operand:SI 1 "nonimmediate_operand" "")) 7043 (sign_extend:DI 7044 (match_operand:SI 2 "register_operand" ""))) 7045 (const_int 32)))) 7046 (clobber (match_scratch:SI 3 "")) 7047 (clobber (reg:CC 17))])] 7048 "" 7049 "") 7050 7051(define_insn "*smulsi3_highpart_insn" 7052 [(set (match_operand:SI 0 "register_operand" "=d") 7053 (truncate:SI 7054 (lshiftrt:DI 7055 (mult:DI (sign_extend:DI 7056 (match_operand:SI 1 "nonimmediate_operand" "%a")) 7057 (sign_extend:DI 7058 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 7059 (const_int 32)))) 7060 (clobber (match_scratch:SI 3 "=1")) 7061 (clobber (reg:CC 17))] 7062 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" 7063 "imul{l}\t%2" 7064 [(set_attr "type" "imul") 7065 (set_attr "ppro_uops" "few") 7066 (set_attr "mode" "SI")]) 7067 7068(define_insn "*smulsi3_highpart_zext" 7069 [(set (match_operand:DI 0 "register_operand" "=d") 7070 (zero_extend:DI (truncate:SI 7071 (lshiftrt:DI 7072 (mult:DI (sign_extend:DI 7073 (match_operand:SI 1 "nonimmediate_operand" "%a")) 7074 (sign_extend:DI 7075 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 7076 (const_int 32))))) 7077 (clobber (match_scratch:SI 3 "=1")) 7078 (clobber (reg:CC 17))] 7079 "TARGET_64BIT 7080 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 7081 "imul{l}\t%2" 7082 [(set_attr "type" "imul") 7083 (set_attr "ppro_uops" "few") 7084 (set_attr "mode" "SI")]) 7085 7086;; The patterns that match these are at the end of this file. 7087 7088(define_expand "mulxf3" 7089 [(set (match_operand:XF 0 "register_operand" "") 7090 (mult:XF (match_operand:XF 1 "register_operand" "") 7091 (match_operand:XF 2 "register_operand" "")))] 7092 "!TARGET_64BIT && TARGET_80387" 7093 "") 7094 7095(define_expand "multf3" 7096 [(set (match_operand:TF 0 "register_operand" "") 7097 (mult:TF (match_operand:TF 1 "register_operand" "") 7098 (match_operand:TF 2 "register_operand" "")))] 7099 "TARGET_80387" 7100 "") 7101 7102(define_expand "muldf3" 7103 [(set (match_operand:DF 0 "register_operand" "") 7104 (mult:DF (match_operand:DF 1 "register_operand" "") 7105 (match_operand:DF 2 "nonimmediate_operand" "")))] 7106 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" 7107 "") 7108 7109(define_expand "mulsf3" 7110 [(set (match_operand:SF 0 "register_operand" "") 7111 (mult:SF (match_operand:SF 1 "register_operand" "") 7112 (match_operand:SF 2 "nonimmediate_operand" "")))] 7113 "TARGET_80387 || TARGET_SSE_MATH" 7114 "") 7115 7116;; Divide instructions 7117 7118(define_insn "divqi3" 7119 [(set (match_operand:QI 0 "register_operand" "=a") 7120 (div:QI (match_operand:HI 1 "register_operand" "0") 7121 (match_operand:QI 2 "nonimmediate_operand" "qm"))) 7122 (clobber (reg:CC 17))] 7123 "TARGET_QIMODE_MATH" 7124 "idiv{b}\t%2" 7125 [(set_attr "type" "idiv") 7126 (set_attr "mode" "QI") 7127 (set_attr "ppro_uops" "few")]) 7128 7129(define_insn "udivqi3" 7130 [(set (match_operand:QI 0 "register_operand" "=a") 7131 (udiv:QI (match_operand:HI 1 "register_operand" "0") 7132 (match_operand:QI 2 "nonimmediate_operand" "qm"))) 7133 (clobber (reg:CC 17))] 7134 "TARGET_QIMODE_MATH" 7135 "div{b}\t%2" 7136 [(set_attr "type" "idiv") 7137 (set_attr "mode" "QI") 7138 (set_attr "ppro_uops" "few")]) 7139 7140;; The patterns that match these are at the end of this file. 7141 7142(define_expand "divxf3" 7143 [(set (match_operand:XF 0 "register_operand" "") 7144 (div:XF (match_operand:XF 1 "register_operand" "") 7145 (match_operand:XF 2 "register_operand" "")))] 7146 "!TARGET_64BIT && TARGET_80387" 7147 "") 7148 7149(define_expand "divtf3" 7150 [(set (match_operand:TF 0 "register_operand" "") 7151 (div:TF (match_operand:TF 1 "register_operand" "") 7152 (match_operand:TF 2 "register_operand" "")))] 7153 "TARGET_80387" 7154 "") 7155 7156(define_expand "divdf3" 7157 [(set (match_operand:DF 0 "register_operand" "") 7158 (div:DF (match_operand:DF 1 "register_operand" "") 7159 (match_operand:DF 2 "nonimmediate_operand" "")))] 7160 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" 7161 "") 7162 7163(define_expand "divsf3" 7164 [(set (match_operand:SF 0 "register_operand" "") 7165 (div:SF (match_operand:SF 1 "register_operand" "") 7166 (match_operand:SF 2 "nonimmediate_operand" "")))] 7167 "TARGET_80387 || TARGET_SSE_MATH" 7168 "") 7169 7170;; Remainder instructions. 7171 7172(define_expand "divmoddi4" 7173 [(parallel [(set (match_operand:DI 0 "register_operand" "") 7174 (div:DI (match_operand:DI 1 "register_operand" "") 7175 (match_operand:DI 2 "nonimmediate_operand" ""))) 7176 (set (match_operand:DI 3 "register_operand" "") 7177 (mod:DI (match_dup 1) (match_dup 2))) 7178 (clobber (reg:CC 17))])] 7179 "TARGET_64BIT" 7180 "") 7181 7182;; Allow to come the parameter in eax or edx to avoid extra moves. 7183;; Penalize eax case sligthly because it results in worse scheduling 7184;; of code. 7185(define_insn "*divmoddi4_nocltd_rex64" 7186 [(set (match_operand:DI 0 "register_operand" "=&a,?a") 7187 (div:DI (match_operand:DI 2 "register_operand" "1,0") 7188 (match_operand:DI 3 "nonimmediate_operand" "rm,rm"))) 7189 (set (match_operand:DI 1 "register_operand" "=&d,&d") 7190 (mod:DI (match_dup 2) (match_dup 3))) 7191 (clobber (reg:CC 17))] 7192 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD" 7193 "#" 7194 [(set_attr "type" "multi")]) 7195 7196(define_insn "*divmoddi4_cltd_rex64" 7197 [(set (match_operand:DI 0 "register_operand" "=a") 7198 (div:DI (match_operand:DI 2 "register_operand" "a") 7199 (match_operand:DI 3 "nonimmediate_operand" "rm"))) 7200 (set (match_operand:DI 1 "register_operand" "=&d") 7201 (mod:DI (match_dup 2) (match_dup 3))) 7202 (clobber (reg:CC 17))] 7203 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)" 7204 "#" 7205 [(set_attr "type" "multi")]) 7206 7207(define_insn "*divmoddi_noext_rex64" 7208 [(set (match_operand:DI 0 "register_operand" "=a") 7209 (div:DI (match_operand:DI 1 "register_operand" "0") 7210 (match_operand:DI 2 "nonimmediate_operand" "rm"))) 7211 (set (match_operand:DI 3 "register_operand" "=d") 7212 (mod:DI (match_dup 1) (match_dup 2))) 7213 (use (match_operand:DI 4 "register_operand" "3")) 7214 (clobber (reg:CC 17))] 7215 "TARGET_64BIT" 7216 "idiv{q}\t%2" 7217 [(set_attr "type" "idiv") 7218 (set_attr "mode" "DI") 7219 (set_attr "ppro_uops" "few")]) 7220 7221(define_split 7222 [(set (match_operand:DI 0 "register_operand" "") 7223 (div:DI (match_operand:DI 1 "register_operand" "") 7224 (match_operand:DI 2 "nonimmediate_operand" ""))) 7225 (set (match_operand:DI 3 "register_operand" "") 7226 (mod:DI (match_dup 1) (match_dup 2))) 7227 (clobber (reg:CC 17))] 7228 "TARGET_64BIT && reload_completed" 7229 [(parallel [(set (match_dup 3) 7230 (ashiftrt:DI (match_dup 4) (const_int 63))) 7231 (clobber (reg:CC 17))]) 7232 (parallel [(set (match_dup 0) 7233 (div:DI (reg:DI 0) (match_dup 2))) 7234 (set (match_dup 3) 7235 (mod:DI (reg:DI 0) (match_dup 2))) 7236 (use (match_dup 3)) 7237 (clobber (reg:CC 17))])] 7238{ 7239 /* Avoid use of cltd in favor of a mov+shift. */ 7240 if (!TARGET_USE_CLTD && !optimize_size) 7241 { 7242 if (true_regnum (operands[1])) 7243 emit_move_insn (operands[0], operands[1]); 7244 else 7245 emit_move_insn (operands[3], operands[1]); 7246 operands[4] = operands[3]; 7247 } 7248 else 7249 { 7250 if (true_regnum (operands[1])) 7251 abort(); 7252 operands[4] = operands[1]; 7253 } 7254}) 7255 7256 7257(define_expand "divmodsi4" 7258 [(parallel [(set (match_operand:SI 0 "register_operand" "") 7259 (div:SI (match_operand:SI 1 "register_operand" "") 7260 (match_operand:SI 2 "nonimmediate_operand" ""))) 7261 (set (match_operand:SI 3 "register_operand" "") 7262 (mod:SI (match_dup 1) (match_dup 2))) 7263 (clobber (reg:CC 17))])] 7264 "" 7265 "") 7266 7267;; Allow to come the parameter in eax or edx to avoid extra moves. 7268;; Penalize eax case sligthly because it results in worse scheduling 7269;; of code. 7270(define_insn "*divmodsi4_nocltd" 7271 [(set (match_operand:SI 0 "register_operand" "=&a,?a") 7272 (div:SI (match_operand:SI 2 "register_operand" "1,0") 7273 (match_operand:SI 3 "nonimmediate_operand" "rm,rm"))) 7274 (set (match_operand:SI 1 "register_operand" "=&d,&d") 7275 (mod:SI (match_dup 2) (match_dup 3))) 7276 (clobber (reg:CC 17))] 7277 "!optimize_size && !TARGET_USE_CLTD" 7278 "#" 7279 [(set_attr "type" "multi")]) 7280 7281(define_insn "*divmodsi4_cltd" 7282 [(set (match_operand:SI 0 "register_operand" "=a") 7283 (div:SI (match_operand:SI 2 "register_operand" "a") 7284 (match_operand:SI 3 "nonimmediate_operand" "rm"))) 7285 (set (match_operand:SI 1 "register_operand" "=&d") 7286 (mod:SI (match_dup 2) (match_dup 3))) 7287 (clobber (reg:CC 17))] 7288 "optimize_size || TARGET_USE_CLTD" 7289 "#" 7290 [(set_attr "type" "multi")]) 7291 7292(define_insn "*divmodsi_noext" 7293 [(set (match_operand:SI 0 "register_operand" "=a") 7294 (div:SI (match_operand:SI 1 "register_operand" "0") 7295 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 7296 (set (match_operand:SI 3 "register_operand" "=d") 7297 (mod:SI (match_dup 1) (match_dup 2))) 7298 (use (match_operand:SI 4 "register_operand" "3")) 7299 (clobber (reg:CC 17))] 7300 "" 7301 "idiv{l}\t%2" 7302 [(set_attr "type" "idiv") 7303 (set_attr "mode" "SI") 7304 (set_attr "ppro_uops" "few")]) 7305 7306(define_split 7307 [(set (match_operand:SI 0 "register_operand" "") 7308 (div:SI (match_operand:SI 1 "register_operand" "") 7309 (match_operand:SI 2 "nonimmediate_operand" ""))) 7310 (set (match_operand:SI 3 "register_operand" "") 7311 (mod:SI (match_dup 1) (match_dup 2))) 7312 (clobber (reg:CC 17))] 7313 "reload_completed" 7314 [(parallel [(set (match_dup 3) 7315 (ashiftrt:SI (match_dup 4) (const_int 31))) 7316 (clobber (reg:CC 17))]) 7317 (parallel [(set (match_dup 0) 7318 (div:SI (reg:SI 0) (match_dup 2))) 7319 (set (match_dup 3) 7320 (mod:SI (reg:SI 0) (match_dup 2))) 7321 (use (match_dup 3)) 7322 (clobber (reg:CC 17))])] 7323{ 7324 /* Avoid use of cltd in favor of a mov+shift. */ 7325 if (!TARGET_USE_CLTD && !optimize_size) 7326 { 7327 if (true_regnum (operands[1])) 7328 emit_move_insn (operands[0], operands[1]); 7329 else 7330 emit_move_insn (operands[3], operands[1]); 7331 operands[4] = operands[3]; 7332 } 7333 else 7334 { 7335 if (true_regnum (operands[1])) 7336 abort(); 7337 operands[4] = operands[1]; 7338 } 7339}) 7340;; %%% Split me. 7341(define_insn "divmodhi4" 7342 [(set (match_operand:HI 0 "register_operand" "=a") 7343 (div:HI (match_operand:HI 1 "register_operand" "0") 7344 (match_operand:HI 2 "nonimmediate_operand" "rm"))) 7345 (set (match_operand:HI 3 "register_operand" "=&d") 7346 (mod:HI (match_dup 1) (match_dup 2))) 7347 (clobber (reg:CC 17))] 7348 "TARGET_HIMODE_MATH" 7349 "cwtd\;idiv{w}\t%2" 7350 [(set_attr "type" "multi") 7351 (set_attr "length_immediate" "0") 7352 (set_attr "mode" "SI")]) 7353 7354(define_insn "udivmoddi4" 7355 [(set (match_operand:DI 0 "register_operand" "=a") 7356 (udiv:DI (match_operand:DI 1 "register_operand" "0") 7357 (match_operand:DI 2 "nonimmediate_operand" "rm"))) 7358 (set (match_operand:DI 3 "register_operand" "=&d") 7359 (umod:DI (match_dup 1) (match_dup 2))) 7360 (clobber (reg:CC 17))] 7361 "TARGET_64BIT" 7362 "xor{q}\t%3, %3\;div{q}\t%2" 7363 [(set_attr "type" "multi") 7364 (set_attr "length_immediate" "0") 7365 (set_attr "mode" "DI")]) 7366 7367(define_insn "*udivmoddi4_noext" 7368 [(set (match_operand:DI 0 "register_operand" "=a") 7369 (udiv:DI (match_operand:DI 1 "register_operand" "0") 7370 (match_operand:DI 2 "nonimmediate_operand" "rm"))) 7371 (set (match_operand:DI 3 "register_operand" "=d") 7372 (umod:DI (match_dup 1) (match_dup 2))) 7373 (use (match_dup 3)) 7374 (clobber (reg:CC 17))] 7375 "TARGET_64BIT" 7376 "div{q}\t%2" 7377 [(set_attr "type" "idiv") 7378 (set_attr "ppro_uops" "few") 7379 (set_attr "mode" "DI")]) 7380 7381(define_split 7382 [(set (match_operand:DI 0 "register_operand" "") 7383 (udiv:DI (match_operand:DI 1 "register_operand" "") 7384 (match_operand:DI 2 "nonimmediate_operand" ""))) 7385 (set (match_operand:DI 3 "register_operand" "") 7386 (umod:DI (match_dup 1) (match_dup 2))) 7387 (clobber (reg:CC 17))] 7388 "TARGET_64BIT && reload_completed" 7389 [(set (match_dup 3) (const_int 0)) 7390 (parallel [(set (match_dup 0) 7391 (udiv:DI (match_dup 1) (match_dup 2))) 7392 (set (match_dup 3) 7393 (umod:DI (match_dup 1) (match_dup 2))) 7394 (use (match_dup 3)) 7395 (clobber (reg:CC 17))])] 7396 "") 7397 7398(define_insn "udivmodsi4" 7399 [(set (match_operand:SI 0 "register_operand" "=a") 7400 (udiv:SI (match_operand:SI 1 "register_operand" "0") 7401 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 7402 (set (match_operand:SI 3 "register_operand" "=&d") 7403 (umod:SI (match_dup 1) (match_dup 2))) 7404 (clobber (reg:CC 17))] 7405 "" 7406 "xor{l}\t%3, %3\;div{l}\t%2" 7407 [(set_attr "type" "multi") 7408 (set_attr "length_immediate" "0") 7409 (set_attr "mode" "SI")]) 7410 7411(define_insn "*udivmodsi4_noext" 7412 [(set (match_operand:SI 0 "register_operand" "=a") 7413 (udiv:SI (match_operand:SI 1 "register_operand" "0") 7414 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 7415 (set (match_operand:SI 3 "register_operand" "=d") 7416 (umod:SI (match_dup 1) (match_dup 2))) 7417 (use (match_dup 3)) 7418 (clobber (reg:CC 17))] 7419 "" 7420 "div{l}\t%2" 7421 [(set_attr "type" "idiv") 7422 (set_attr "ppro_uops" "few") 7423 (set_attr "mode" "SI")]) 7424 7425(define_split 7426 [(set (match_operand:SI 0 "register_operand" "") 7427 (udiv:SI (match_operand:SI 1 "register_operand" "") 7428 (match_operand:SI 2 "nonimmediate_operand" ""))) 7429 (set (match_operand:SI 3 "register_operand" "") 7430 (umod:SI (match_dup 1) (match_dup 2))) 7431 (clobber (reg:CC 17))] 7432 "reload_completed" 7433 [(set (match_dup 3) (const_int 0)) 7434 (parallel [(set (match_dup 0) 7435 (udiv:SI (match_dup 1) (match_dup 2))) 7436 (set (match_dup 3) 7437 (umod:SI (match_dup 1) (match_dup 2))) 7438 (use (match_dup 3)) 7439 (clobber (reg:CC 17))])] 7440 "") 7441 7442(define_expand "udivmodhi4" 7443 [(set (match_dup 4) (const_int 0)) 7444 (parallel [(set (match_operand:HI 0 "register_operand" "") 7445 (udiv:HI (match_operand:HI 1 "register_operand" "") 7446 (match_operand:HI 2 "nonimmediate_operand" ""))) 7447 (set (match_operand:HI 3 "register_operand" "") 7448 (umod:HI (match_dup 1) (match_dup 2))) 7449 (use (match_dup 4)) 7450 (clobber (reg:CC 17))])] 7451 "TARGET_HIMODE_MATH" 7452 "operands[4] = gen_reg_rtx (HImode);") 7453 7454(define_insn "*udivmodhi_noext" 7455 [(set (match_operand:HI 0 "register_operand" "=a") 7456 (udiv:HI (match_operand:HI 1 "register_operand" "0") 7457 (match_operand:HI 2 "nonimmediate_operand" "rm"))) 7458 (set (match_operand:HI 3 "register_operand" "=d") 7459 (umod:HI (match_dup 1) (match_dup 2))) 7460 (use (match_operand:HI 4 "register_operand" "3")) 7461 (clobber (reg:CC 17))] 7462 "" 7463 "div{w}\t%2" 7464 [(set_attr "type" "idiv") 7465 (set_attr "mode" "HI") 7466 (set_attr "ppro_uops" "few")]) 7467 7468;; We can not use div/idiv for double division, because it causes 7469;; "division by zero" on the overflow and that's not what we expect 7470;; from truncate. Because true (non truncating) double division is 7471;; never generated, we can't create this insn anyway. 7472; 7473;(define_insn "" 7474; [(set (match_operand:SI 0 "register_operand" "=a") 7475; (truncate:SI 7476; (udiv:DI (match_operand:DI 1 "register_operand" "A") 7477; (zero_extend:DI 7478; (match_operand:SI 2 "nonimmediate_operand" "rm"))))) 7479; (set (match_operand:SI 3 "register_operand" "=d") 7480; (truncate:SI 7481; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2))))) 7482; (clobber (reg:CC 17))] 7483; "" 7484; "div{l}\t{%2, %0|%0, %2}" 7485; [(set_attr "type" "idiv") 7486; (set_attr "ppro_uops" "few")]) 7487 7488;;- Logical AND instructions 7489 7490;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al. 7491;; Note that this excludes ah. 7492 7493(define_insn "*testdi_1_rex64" 7494 [(set (reg 17) 7495 (compare 7496 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm") 7497 (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re")) 7498 (const_int 0)))] 7499 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" 7500 "@ 7501 test{l}\t{%k1, %k0|%k0, %k1} 7502 test{l}\t{%k1, %k0|%k0, %k1} 7503 test{q}\t{%1, %0|%0, %1} 7504 test{q}\t{%1, %0|%0, %1} 7505 test{q}\t{%1, %0|%0, %1}" 7506 [(set_attr "type" "test") 7507 (set_attr "modrm" "0,1,0,1,1") 7508 (set_attr "mode" "SI,SI,DI,DI,DI") 7509 (set_attr "pent_pair" "uv,np,uv,np,uv")]) 7510 7511(define_insn "testsi_1" 7512 [(set (reg 17) 7513 (compare 7514 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm") 7515 (match_operand:SI 1 "nonmemory_operand" "in,in,rin")) 7516 (const_int 0)))] 7517 "ix86_match_ccmode (insn, CCNOmode)" 7518 "test{l}\t{%1, %0|%0, %1}" 7519 [(set_attr "type" "test") 7520 (set_attr "modrm" "0,1,1") 7521 (set_attr "mode" "SI") 7522 (set_attr "pent_pair" "uv,np,uv")]) 7523 7524(define_expand "testsi_ccno_1" 7525 [(set (reg:CCNO 17) 7526 (compare:CCNO 7527 (and:SI (match_operand:SI 0 "nonimmediate_operand" "") 7528 (match_operand:SI 1 "nonmemory_operand" "")) 7529 (const_int 0)))] 7530 "" 7531 "") 7532 7533(define_insn "*testhi_1" 7534 [(set (reg 17) 7535 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm") 7536 (match_operand:HI 1 "nonmemory_operand" "n,n,rn")) 7537 (const_int 0)))] 7538 "ix86_match_ccmode (insn, CCNOmode)" 7539 "test{w}\t{%1, %0|%0, %1}" 7540 [(set_attr "type" "test") 7541 (set_attr "modrm" "0,1,1") 7542 (set_attr "mode" "HI") 7543 (set_attr "pent_pair" "uv,np,uv")]) 7544 7545(define_expand "testqi_ccz_1" 7546 [(set (reg:CCZ 17) 7547 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "") 7548 (match_operand:QI 1 "nonmemory_operand" "")) 7549 (const_int 0)))] 7550 "" 7551 "") 7552 7553(define_insn "*testqi_1" 7554 [(set (reg 17) 7555 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r") 7556 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n")) 7557 (const_int 0)))] 7558 "ix86_match_ccmode (insn, CCNOmode)" 7559{ 7560 if (which_alternative == 3) 7561 { 7562 if (GET_CODE (operands[1]) == CONST_INT 7563 && (INTVAL (operands[1]) & 0xffffff00)) 7564 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); 7565 return "test{l}\t{%1, %k0|%k0, %1}"; 7566 } 7567 return "test{b}\t{%1, %0|%0, %1}"; 7568} 7569 [(set_attr "type" "test") 7570 (set_attr "modrm" "0,1,1,1") 7571 (set_attr "mode" "QI,QI,QI,SI") 7572 (set_attr "pent_pair" "uv,np,uv,np")]) 7573 7574(define_expand "testqi_ext_ccno_0" 7575 [(set (reg:CCNO 17) 7576 (compare:CCNO 7577 (and:SI 7578 (zero_extract:SI 7579 (match_operand 0 "ext_register_operand" "") 7580 (const_int 8) 7581 (const_int 8)) 7582 (match_operand 1 "const_int_operand" "")) 7583 (const_int 0)))] 7584 "" 7585 "") 7586 7587(define_insn "*testqi_ext_0" 7588 [(set (reg 17) 7589 (compare 7590 (and:SI 7591 (zero_extract:SI 7592 (match_operand 0 "ext_register_operand" "Q") 7593 (const_int 8) 7594 (const_int 8)) 7595 (match_operand 1 "const_int_operand" "n")) 7596 (const_int 0)))] 7597 "ix86_match_ccmode (insn, CCNOmode)" 7598 "test{b}\t{%1, %h0|%h0, %1}" 7599 [(set_attr "type" "test") 7600 (set_attr "mode" "QI") 7601 (set_attr "length_immediate" "1") 7602 (set_attr "pent_pair" "np")]) 7603 7604(define_insn "*testqi_ext_1" 7605 [(set (reg 17) 7606 (compare 7607 (and:SI 7608 (zero_extract:SI 7609 (match_operand 0 "ext_register_operand" "Q") 7610 (const_int 8) 7611 (const_int 8)) 7612 (zero_extend:SI 7613 (match_operand:QI 1 "nonimmediate_operand" "Qm"))) 7614 (const_int 0)))] 7615 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" 7616 "test{b}\t{%1, %h0|%h0, %1}" 7617 [(set_attr "type" "test") 7618 (set_attr "mode" "QI")]) 7619 7620(define_insn "*testqi_ext_1_rex64" 7621 [(set (reg 17) 7622 (compare 7623 (and:SI 7624 (zero_extract:SI 7625 (match_operand 0 "ext_register_operand" "Q") 7626 (const_int 8) 7627 (const_int 8)) 7628 (zero_extend:SI 7629 (match_operand:QI 1 "register_operand" "Q"))) 7630 (const_int 0)))] 7631 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" 7632 "test{b}\t{%1, %h0|%h0, %1}" 7633 [(set_attr "type" "test") 7634 (set_attr "mode" "QI")]) 7635 7636(define_insn "*testqi_ext_2" 7637 [(set (reg 17) 7638 (compare 7639 (and:SI 7640 (zero_extract:SI 7641 (match_operand 0 "ext_register_operand" "Q") 7642 (const_int 8) 7643 (const_int 8)) 7644 (zero_extract:SI 7645 (match_operand 1 "ext_register_operand" "Q") 7646 (const_int 8) 7647 (const_int 8))) 7648 (const_int 0)))] 7649 "ix86_match_ccmode (insn, CCNOmode)" 7650 "test{b}\t{%h1, %h0|%h0, %h1}" 7651 [(set_attr "type" "test") 7652 (set_attr "mode" "QI")]) 7653 7654;; Combine likes to form bit extractions for some tests. Humor it. 7655(define_insn "*testqi_ext_3" 7656 [(set (reg 17) 7657 (compare (zero_extract:SI 7658 (match_operand 0 "nonimmediate_operand" "rm") 7659 (match_operand:SI 1 "const_int_operand" "") 7660 (match_operand:SI 2 "const_int_operand" "")) 7661 (const_int 0)))] 7662 "ix86_match_ccmode (insn, CCNOmode) 7663 && (GET_MODE (operands[0]) == SImode 7664 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode) 7665 || GET_MODE (operands[0]) == HImode 7666 || GET_MODE (operands[0]) == QImode)" 7667 "#") 7668 7669(define_insn "*testqi_ext_3_rex64" 7670 [(set (reg 17) 7671 (compare (zero_extract:DI 7672 (match_operand 0 "nonimmediate_operand" "rm") 7673 (match_operand:DI 1 "const_int_operand" "") 7674 (match_operand:DI 2 "const_int_operand" "")) 7675 (const_int 0)))] 7676 "TARGET_64BIT 7677 && ix86_match_ccmode (insn, CCNOmode) 7678 /* The code below cannot deal with constants outside HOST_WIDE_INT. */ 7679 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT 7680 /* Ensure that resulting mask is zero or sign extended operand. */ 7681 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 7682 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64 7683 && INTVAL (operands[1]) > 32)) 7684 && (GET_MODE (operands[0]) == SImode 7685 || GET_MODE (operands[0]) == DImode 7686 || GET_MODE (operands[0]) == HImode 7687 || GET_MODE (operands[0]) == QImode)" 7688 "#") 7689 7690(define_split 7691 [(set (reg 17) 7692 (compare (zero_extract 7693 (match_operand 0 "nonimmediate_operand" "") 7694 (match_operand 1 "const_int_operand" "") 7695 (match_operand 2 "const_int_operand" "")) 7696 (const_int 0)))] 7697 "ix86_match_ccmode (insn, CCNOmode)" 7698 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))] 7699{ 7700 HOST_WIDE_INT len = INTVAL (operands[1]); 7701 HOST_WIDE_INT pos = INTVAL (operands[2]); 7702 HOST_WIDE_INT mask; 7703 enum machine_mode mode, submode; 7704 7705 mode = GET_MODE (operands[0]); 7706 if (GET_CODE (operands[0]) == MEM) 7707 { 7708 /* ??? Combine likes to put non-volatile mem extractions in QImode 7709 no matter the size of the test. So find a mode that works. */ 7710 if (! MEM_VOLATILE_P (operands[0])) 7711 { 7712 mode = smallest_mode_for_size (pos + len, MODE_INT); 7713 operands[0] = adjust_address (operands[0], mode, 0); 7714 } 7715 } 7716 else if (GET_CODE (operands[0]) == SUBREG 7717 && (submode = GET_MODE (SUBREG_REG (operands[0])), 7718 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode)) 7719 && pos + len <= GET_MODE_BITSIZE (submode)) 7720 { 7721 /* Narrow a paradoxical subreg to prevent partial register stalls. */ 7722 mode = submode; 7723 operands[0] = SUBREG_REG (operands[0]); 7724 } 7725 else if (mode == HImode && pos + len <= 8) 7726 { 7727 /* Small HImode tests can be converted to QImode. */ 7728 mode = QImode; 7729 operands[0] = gen_lowpart (QImode, operands[0]); 7730 } 7731 7732 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1; 7733 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1); 7734 7735 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode)); 7736}) 7737 7738;; Convert HImode/SImode test instructions with immediate to QImode ones. 7739;; i386 does not allow to encode test with 8bit sign extended immediate, so 7740;; this is relatively important trick. 7741;; Do the converison only post-reload to avoid limiting of the register class 7742;; to QI regs. 7743(define_split 7744 [(set (reg 17) 7745 (compare 7746 (and (match_operand 0 "register_operand" "") 7747 (match_operand 1 "const_int_operand" "")) 7748 (const_int 0)))] 7749 "reload_completed 7750 && QI_REG_P (operands[0]) 7751 && ((ix86_match_ccmode (insn, CCZmode) 7752 && !(INTVAL (operands[1]) & ~(255 << 8))) 7753 || (ix86_match_ccmode (insn, CCNOmode) 7754 && !(INTVAL (operands[1]) & ~(127 << 8)))) 7755 && GET_MODE (operands[0]) != QImode" 7756 [(set (reg:CCNO 17) 7757 (compare:CCNO 7758 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) 7759 (match_dup 1)) 7760 (const_int 0)))] 7761 "operands[0] = gen_lowpart (SImode, operands[0]); 7762 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);") 7763 7764(define_split 7765 [(set (reg 17) 7766 (compare 7767 (and (match_operand 0 "nonimmediate_operand" "") 7768 (match_operand 1 "const_int_operand" "")) 7769 (const_int 0)))] 7770 "reload_completed 7771 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0])) 7772 && ((ix86_match_ccmode (insn, CCZmode) 7773 && !(INTVAL (operands[1]) & ~255)) 7774 || (ix86_match_ccmode (insn, CCNOmode) 7775 && !(INTVAL (operands[1]) & ~127))) 7776 && GET_MODE (operands[0]) != QImode" 7777 [(set (reg:CCNO 17) 7778 (compare:CCNO 7779 (and:QI (match_dup 0) 7780 (match_dup 1)) 7781 (const_int 0)))] 7782 "operands[0] = gen_lowpart (QImode, operands[0]); 7783 operands[1] = gen_lowpart (QImode, operands[1]);") 7784 7785 7786;; %%% This used to optimize known byte-wide and operations to memory, 7787;; and sometimes to QImode registers. If this is considered useful, 7788;; it should be done with splitters. 7789 7790(define_expand "anddi3" 7791 [(set (match_operand:DI 0 "nonimmediate_operand" "") 7792 (and:DI (match_operand:DI 1 "nonimmediate_operand" "") 7793 (match_operand:DI 2 "x86_64_szext_general_operand" ""))) 7794 (clobber (reg:CC 17))] 7795 "TARGET_64BIT" 7796 "ix86_expand_binary_operator (AND, DImode, operands); DONE;") 7797 7798(define_insn "*anddi_1_rex64" 7799 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r") 7800 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm") 7801 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L"))) 7802 (clobber (reg:CC 17))] 7803 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)" 7804{ 7805 switch (get_attr_type (insn)) 7806 { 7807 case TYPE_IMOVX: 7808 { 7809 enum machine_mode mode; 7810 7811 if (GET_CODE (operands[2]) != CONST_INT) 7812 abort (); 7813 if (INTVAL (operands[2]) == 0xff) 7814 mode = QImode; 7815 else if (INTVAL (operands[2]) == 0xffff) 7816 mode = HImode; 7817 else 7818 abort (); 7819 7820 operands[1] = gen_lowpart (mode, operands[1]); 7821 if (mode == QImode) 7822 return "movz{bq|x}\t{%1,%0|%0, %1}"; 7823 else 7824 return "movz{wq|x}\t{%1,%0|%0, %1}"; 7825 } 7826 7827 default: 7828 if (! rtx_equal_p (operands[0], operands[1])) 7829 abort (); 7830 if (get_attr_mode (insn) == MODE_SI) 7831 return "and{l}\t{%k2, %k0|%k0, %k2}"; 7832 else 7833 return "and{q}\t{%2, %0|%0, %2}"; 7834 } 7835} 7836 [(set_attr "type" "alu,alu,alu,imovx") 7837 (set_attr "length_immediate" "*,*,*,0") 7838 (set_attr "mode" "SI,DI,DI,DI")]) 7839 7840(define_insn "*anddi_2" 7841 [(set (reg 17) 7842 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") 7843 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re")) 7844 (const_int 0))) 7845 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm") 7846 (and:DI (match_dup 1) (match_dup 2)))] 7847 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) 7848 && ix86_binary_operator_ok (AND, DImode, operands)" 7849 "@ 7850 and{l}\t{%k2, %k0|%k0, %k2} 7851 and{q}\t{%2, %0|%0, %2} 7852 and{q}\t{%2, %0|%0, %2}" 7853 [(set_attr "type" "alu") 7854 (set_attr "mode" "SI,DI,DI")]) 7855 7856(define_expand "andsi3" 7857 [(set (match_operand:SI 0 "nonimmediate_operand" "") 7858 (and:SI (match_operand:SI 1 "nonimmediate_operand" "") 7859 (match_operand:SI 2 "general_operand" ""))) 7860 (clobber (reg:CC 17))] 7861 "" 7862 "ix86_expand_binary_operator (AND, SImode, operands); DONE;") 7863 7864(define_insn "*andsi_1" 7865 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r") 7866 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm") 7867 (match_operand:SI 2 "general_operand" "ri,rm,L"))) 7868 (clobber (reg:CC 17))] 7869 "ix86_binary_operator_ok (AND, SImode, operands)" 7870{ 7871 switch (get_attr_type (insn)) 7872 { 7873 case TYPE_IMOVX: 7874 { 7875 enum machine_mode mode; 7876 7877 if (GET_CODE (operands[2]) != CONST_INT) 7878 abort (); 7879 if (INTVAL (operands[2]) == 0xff) 7880 mode = QImode; 7881 else if (INTVAL (operands[2]) == 0xffff) 7882 mode = HImode; 7883 else 7884 abort (); 7885 7886 operands[1] = gen_lowpart (mode, operands[1]); 7887 if (mode == QImode) 7888 return "movz{bl|x}\t{%1,%0|%0, %1}"; 7889 else 7890 return "movz{wl|x}\t{%1,%0|%0, %1}"; 7891 } 7892 7893 default: 7894 if (! rtx_equal_p (operands[0], operands[1])) 7895 abort (); 7896 return "and{l}\t{%2, %0|%0, %2}"; 7897 } 7898} 7899 [(set_attr "type" "alu,alu,imovx") 7900 (set_attr "length_immediate" "*,*,0") 7901 (set_attr "mode" "SI")]) 7902 7903(define_split 7904 [(set (match_operand 0 "register_operand" "") 7905 (and (match_dup 0) 7906 (const_int -65536))) 7907 (clobber (reg:CC 17))] 7908 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)" 7909 [(set (strict_low_part (match_dup 1)) (const_int 0))] 7910 "operands[1] = gen_lowpart (HImode, operands[0]);") 7911 7912(define_split 7913 [(set (match_operand 0 "ext_register_operand" "") 7914 (and (match_dup 0) 7915 (const_int -256))) 7916 (clobber (reg:CC 17))] 7917 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed" 7918 [(set (strict_low_part (match_dup 1)) (const_int 0))] 7919 "operands[1] = gen_lowpart (QImode, operands[0]);") 7920 7921(define_split 7922 [(set (match_operand 0 "ext_register_operand" "") 7923 (and (match_dup 0) 7924 (const_int -65281))) 7925 (clobber (reg:CC 17))] 7926 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed" 7927 [(parallel [(set (zero_extract:SI (match_dup 0) 7928 (const_int 8) 7929 (const_int 8)) 7930 (xor:SI 7931 (zero_extract:SI (match_dup 0) 7932 (const_int 8) 7933 (const_int 8)) 7934 (zero_extract:SI (match_dup 0) 7935 (const_int 8) 7936 (const_int 8)))) 7937 (clobber (reg:CC 17))])] 7938 "operands[0] = gen_lowpart (SImode, operands[0]);") 7939 7940;; See comment for addsi_1_zext why we do use nonimmediate_operand 7941(define_insn "*andsi_1_zext" 7942 [(set (match_operand:DI 0 "register_operand" "=r") 7943 (zero_extend:DI 7944 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0") 7945 (match_operand:SI 2 "general_operand" "rim")))) 7946 (clobber (reg:CC 17))] 7947 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)" 7948 "and{l}\t{%2, %k0|%k0, %2}" 7949 [(set_attr "type" "alu") 7950 (set_attr "mode" "SI")]) 7951 7952(define_insn "*andsi_2" 7953 [(set (reg 17) 7954 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 7955 (match_operand:SI 2 "general_operand" "rim,ri")) 7956 (const_int 0))) 7957 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") 7958 (and:SI (match_dup 1) (match_dup 2)))] 7959 "ix86_match_ccmode (insn, CCNOmode) 7960 && ix86_binary_operator_ok (AND, SImode, operands)" 7961 "and{l}\t{%2, %0|%0, %2}" 7962 [(set_attr "type" "alu") 7963 (set_attr "mode" "SI")]) 7964 7965;; See comment for addsi_1_zext why we do use nonimmediate_operand 7966(define_insn "*andsi_2_zext" 7967 [(set (reg 17) 7968 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0") 7969 (match_operand:SI 2 "general_operand" "rim")) 7970 (const_int 0))) 7971 (set (match_operand:DI 0 "register_operand" "=r") 7972 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))] 7973 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) 7974 && ix86_binary_operator_ok (AND, SImode, operands)" 7975 "and{l}\t{%2, %k0|%k0, %2}" 7976 [(set_attr "type" "alu") 7977 (set_attr "mode" "SI")]) 7978 7979(define_expand "andhi3" 7980 [(set (match_operand:HI 0 "nonimmediate_operand" "") 7981 (and:HI (match_operand:HI 1 "nonimmediate_operand" "") 7982 (match_operand:HI 2 "general_operand" ""))) 7983 (clobber (reg:CC 17))] 7984 "TARGET_HIMODE_MATH" 7985 "ix86_expand_binary_operator (AND, HImode, operands); DONE;") 7986 7987(define_insn "*andhi_1" 7988 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r") 7989 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm") 7990 (match_operand:HI 2 "general_operand" "ri,rm,L"))) 7991 (clobber (reg:CC 17))] 7992 "ix86_binary_operator_ok (AND, HImode, operands)" 7993{ 7994 switch (get_attr_type (insn)) 7995 { 7996 case TYPE_IMOVX: 7997 if (GET_CODE (operands[2]) != CONST_INT) 7998 abort (); 7999 if (INTVAL (operands[2]) == 0xff) 8000 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}"; 8001 abort (); 8002 8003 default: 8004 if (! rtx_equal_p (operands[0], operands[1])) 8005 abort (); 8006 8007 return "and{w}\t{%2, %0|%0, %2}"; 8008 } 8009} 8010 [(set_attr "type" "alu,alu,imovx") 8011 (set_attr "length_immediate" "*,*,0") 8012 (set_attr "mode" "HI,HI,SI")]) 8013 8014(define_insn "*andhi_2" 8015 [(set (reg 17) 8016 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") 8017 (match_operand:HI 2 "general_operand" "rim,ri")) 8018 (const_int 0))) 8019 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") 8020 (and:HI (match_dup 1) (match_dup 2)))] 8021 "ix86_match_ccmode (insn, CCNOmode) 8022 && ix86_binary_operator_ok (AND, HImode, operands)" 8023 "and{w}\t{%2, %0|%0, %2}" 8024 [(set_attr "type" "alu") 8025 (set_attr "mode" "HI")]) 8026 8027(define_expand "andqi3" 8028 [(set (match_operand:QI 0 "nonimmediate_operand" "") 8029 (and:QI (match_operand:QI 1 "nonimmediate_operand" "") 8030 (match_operand:QI 2 "general_operand" ""))) 8031 (clobber (reg:CC 17))] 8032 "TARGET_QIMODE_MATH" 8033 "ix86_expand_binary_operator (AND, QImode, operands); DONE;") 8034 8035;; %%% Potential partial reg stall on alternative 2. What to do? 8036(define_insn "*andqi_1" 8037 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") 8038 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") 8039 (match_operand:QI 2 "general_operand" "qi,qmi,ri"))) 8040 (clobber (reg:CC 17))] 8041 "ix86_binary_operator_ok (AND, QImode, operands)" 8042 "@ 8043 and{b}\t{%2, %0|%0, %2} 8044 and{b}\t{%2, %0|%0, %2} 8045 and{l}\t{%k2, %k0|%k0, %k2}" 8046 [(set_attr "type" "alu") 8047 (set_attr "mode" "QI,QI,SI")]) 8048 8049(define_insn "*andqi_1_slp" 8050 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) 8051 (and:QI (match_dup 0) 8052 (match_operand:QI 1 "general_operand" "qi,qmi"))) 8053 (clobber (reg:CC 17))] 8054 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 8055 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 8056 "and{b}\t{%1, %0|%0, %1}" 8057 [(set_attr "type" "alu1") 8058 (set_attr "mode" "QI")]) 8059 8060(define_insn "*andqi_2" 8061 [(set (reg 17) 8062 (compare (and:QI 8063 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") 8064 (match_operand:QI 2 "general_operand" "qim,qi,i")) 8065 (const_int 0))) 8066 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r") 8067 (and:QI (match_dup 1) (match_dup 2)))] 8068 "ix86_match_ccmode (insn, CCNOmode) 8069 && ix86_binary_operator_ok (AND, QImode, operands)" 8070{ 8071 if (which_alternative == 2) 8072 { 8073 if (GET_CODE (operands[2]) == CONST_INT 8074 && (INTVAL (operands[2]) & 0xffffff00)) 8075 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); 8076 return "and{l}\t{%2, %k0|%k0, %2}"; 8077 } 8078 return "and{b}\t{%2, %0|%0, %2}"; 8079} 8080 [(set_attr "type" "alu") 8081 (set_attr "mode" "QI,QI,SI")]) 8082 8083(define_insn "*andqi_2_slp" 8084 [(set (reg 17) 8085 (compare (and:QI 8086 (match_operand:QI 0 "nonimmediate_operand" "+q,qm") 8087 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi")) 8088 (const_int 0))) 8089 (set (strict_low_part (match_dup 0)) 8090 (and:QI (match_dup 0) (match_dup 1)))] 8091 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 8092 && ix86_match_ccmode (insn, CCNOmode) 8093 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 8094 "and{b}\t{%1, %0|%0, %1}" 8095 [(set_attr "type" "alu1") 8096 (set_attr "mode" "QI")]) 8097 8098;; ??? A bug in recog prevents it from recognizing a const_int as an 8099;; operand to zero_extend in andqi_ext_1. It was checking explicitly 8100;; for a QImode operand, which of course failed. 8101 8102(define_insn "andqi_ext_0" 8103 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8104 (const_int 8) 8105 (const_int 8)) 8106 (and:SI 8107 (zero_extract:SI 8108 (match_operand 1 "ext_register_operand" "0") 8109 (const_int 8) 8110 (const_int 8)) 8111 (match_operand 2 "const_int_operand" "n"))) 8112 (clobber (reg:CC 17))] 8113 "" 8114 "and{b}\t{%2, %h0|%h0, %2}" 8115 [(set_attr "type" "alu") 8116 (set_attr "length_immediate" "1") 8117 (set_attr "mode" "QI")]) 8118 8119;; Generated by peephole translating test to and. This shows up 8120;; often in fp comparisons. 8121 8122(define_insn "*andqi_ext_0_cc" 8123 [(set (reg 17) 8124 (compare 8125 (and:SI 8126 (zero_extract:SI 8127 (match_operand 1 "ext_register_operand" "0") 8128 (const_int 8) 8129 (const_int 8)) 8130 (match_operand 2 "const_int_operand" "n")) 8131 (const_int 0))) 8132 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8133 (const_int 8) 8134 (const_int 8)) 8135 (and:SI 8136 (zero_extract:SI 8137 (match_dup 1) 8138 (const_int 8) 8139 (const_int 8)) 8140 (match_dup 2)))] 8141 "ix86_match_ccmode (insn, CCNOmode)" 8142 "and{b}\t{%2, %h0|%h0, %2}" 8143 [(set_attr "type" "alu") 8144 (set_attr "length_immediate" "1") 8145 (set_attr "mode" "QI")]) 8146 8147(define_insn "*andqi_ext_1" 8148 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8149 (const_int 8) 8150 (const_int 8)) 8151 (and:SI 8152 (zero_extract:SI 8153 (match_operand 1 "ext_register_operand" "0") 8154 (const_int 8) 8155 (const_int 8)) 8156 (zero_extend:SI 8157 (match_operand:QI 2 "general_operand" "Qm")))) 8158 (clobber (reg:CC 17))] 8159 "!TARGET_64BIT" 8160 "and{b}\t{%2, %h0|%h0, %2}" 8161 [(set_attr "type" "alu") 8162 (set_attr "length_immediate" "0") 8163 (set_attr "mode" "QI")]) 8164 8165(define_insn "*andqi_ext_1_rex64" 8166 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8167 (const_int 8) 8168 (const_int 8)) 8169 (and:SI 8170 (zero_extract:SI 8171 (match_operand 1 "ext_register_operand" "0") 8172 (const_int 8) 8173 (const_int 8)) 8174 (zero_extend:SI 8175 (match_operand 2 "ext_register_operand" "Q")))) 8176 (clobber (reg:CC 17))] 8177 "TARGET_64BIT" 8178 "and{b}\t{%2, %h0|%h0, %2}" 8179 [(set_attr "type" "alu") 8180 (set_attr "length_immediate" "0") 8181 (set_attr "mode" "QI")]) 8182 8183(define_insn "*andqi_ext_2" 8184 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8185 (const_int 8) 8186 (const_int 8)) 8187 (and:SI 8188 (zero_extract:SI 8189 (match_operand 1 "ext_register_operand" "%0") 8190 (const_int 8) 8191 (const_int 8)) 8192 (zero_extract:SI 8193 (match_operand 2 "ext_register_operand" "Q") 8194 (const_int 8) 8195 (const_int 8)))) 8196 (clobber (reg:CC 17))] 8197 "" 8198 "and{b}\t{%h2, %h0|%h0, %h2}" 8199 [(set_attr "type" "alu") 8200 (set_attr "length_immediate" "0") 8201 (set_attr "mode" "QI")]) 8202 8203;; Convert wide AND instructions with immediate operand to shorter QImode 8204;; equivalents when possible. 8205;; Don't do the splitting with memory operands, since it intoduces risc 8206;; of memory mismatch stalls. We may want to do the splitting for optimizing 8207;; for size, but that can (should?) be handled by generic code instead. 8208(define_split 8209 [(set (match_operand 0 "register_operand" "") 8210 (and (match_operand 1 "register_operand" "") 8211 (match_operand 2 "const_int_operand" ""))) 8212 (clobber (reg:CC 17))] 8213 "reload_completed 8214 && QI_REG_P (operands[0]) 8215 && (!TARGET_PARTIAL_REG_STALL || optimize_size) 8216 && !(~INTVAL (operands[2]) & ~(255 << 8)) 8217 && GET_MODE (operands[0]) != QImode" 8218 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) 8219 (and:SI (zero_extract:SI (match_dup 1) 8220 (const_int 8) (const_int 8)) 8221 (match_dup 2))) 8222 (clobber (reg:CC 17))])] 8223 "operands[0] = gen_lowpart (SImode, operands[0]); 8224 operands[1] = gen_lowpart (SImode, operands[1]); 8225 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") 8226 8227;; Since AND can be encoded with sign extended immediate, this is only 8228;; profitable when 7th bit is not set. 8229(define_split 8230 [(set (match_operand 0 "register_operand" "") 8231 (and (match_operand 1 "general_operand" "") 8232 (match_operand 2 "const_int_operand" ""))) 8233 (clobber (reg:CC 17))] 8234 "reload_completed 8235 && ANY_QI_REG_P (operands[0]) 8236 && (!TARGET_PARTIAL_REG_STALL || optimize_size) 8237 && !(~INTVAL (operands[2]) & ~255) 8238 && !(INTVAL (operands[2]) & 128) 8239 && GET_MODE (operands[0]) != QImode" 8240 [(parallel [(set (strict_low_part (match_dup 0)) 8241 (and:QI (match_dup 1) 8242 (match_dup 2))) 8243 (clobber (reg:CC 17))])] 8244 "operands[0] = gen_lowpart (QImode, operands[0]); 8245 operands[1] = gen_lowpart (QImode, operands[1]); 8246 operands[2] = gen_lowpart (QImode, operands[2]);") 8247 8248;; Logical inclusive OR instructions 8249 8250;; %%% This used to optimize known byte-wide and operations to memory. 8251;; If this is considered useful, it should be done with splitters. 8252 8253(define_expand "iordi3" 8254 [(set (match_operand:DI 0 "nonimmediate_operand" "") 8255 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") 8256 (match_operand:DI 2 "x86_64_general_operand" ""))) 8257 (clobber (reg:CC 17))] 8258 "TARGET_64BIT" 8259 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;") 8260 8261(define_insn "*iordi_1_rex64" 8262 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") 8263 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 8264 (match_operand:DI 2 "x86_64_general_operand" "re,rme"))) 8265 (clobber (reg:CC 17))] 8266 "TARGET_64BIT 8267 && ix86_binary_operator_ok (IOR, DImode, operands)" 8268 "or{q}\t{%2, %0|%0, %2}" 8269 [(set_attr "type" "alu") 8270 (set_attr "mode" "DI")]) 8271 8272(define_insn "*iordi_2_rex64" 8273 [(set (reg 17) 8274 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 8275 (match_operand:DI 2 "x86_64_general_operand" "rem,re")) 8276 (const_int 0))) 8277 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") 8278 (ior:DI (match_dup 1) (match_dup 2)))] 8279 "TARGET_64BIT 8280 && ix86_match_ccmode (insn, CCNOmode) 8281 && ix86_binary_operator_ok (IOR, DImode, operands)" 8282 "or{q}\t{%2, %0|%0, %2}" 8283 [(set_attr "type" "alu") 8284 (set_attr "mode" "DI")]) 8285 8286(define_insn "*iordi_3_rex64" 8287 [(set (reg 17) 8288 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0") 8289 (match_operand:DI 2 "x86_64_general_operand" "rem")) 8290 (const_int 0))) 8291 (clobber (match_scratch:DI 0 "=r"))] 8292 "TARGET_64BIT 8293 && ix86_match_ccmode (insn, CCNOmode) 8294 && ix86_binary_operator_ok (IOR, DImode, operands)" 8295 "or{q}\t{%2, %0|%0, %2}" 8296 [(set_attr "type" "alu") 8297 (set_attr "mode" "DI")]) 8298 8299 8300(define_expand "iorsi3" 8301 [(set (match_operand:SI 0 "nonimmediate_operand" "") 8302 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") 8303 (match_operand:SI 2 "general_operand" ""))) 8304 (clobber (reg:CC 17))] 8305 "" 8306 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;") 8307 8308(define_insn "*iorsi_1" 8309 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 8310 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 8311 (match_operand:SI 2 "general_operand" "ri,rmi"))) 8312 (clobber (reg:CC 17))] 8313 "ix86_binary_operator_ok (IOR, SImode, operands)" 8314 "or{l}\t{%2, %0|%0, %2}" 8315 [(set_attr "type" "alu") 8316 (set_attr "mode" "SI")]) 8317 8318;; See comment for addsi_1_zext why we do use nonimmediate_operand 8319(define_insn "*iorsi_1_zext" 8320 [(set (match_operand:DI 0 "register_operand" "=rm") 8321 (zero_extend:DI 8322 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") 8323 (match_operand:SI 2 "general_operand" "rim")))) 8324 (clobber (reg:CC 17))] 8325 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)" 8326 "or{l}\t{%2, %k0|%k0, %2}" 8327 [(set_attr "type" "alu") 8328 (set_attr "mode" "SI")]) 8329 8330(define_insn "*iorsi_1_zext_imm" 8331 [(set (match_operand:DI 0 "register_operand" "=rm") 8332 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) 8333 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z"))) 8334 (clobber (reg:CC 17))] 8335 "TARGET_64BIT" 8336 "or{l}\t{%2, %k0|%k0, %2}" 8337 [(set_attr "type" "alu") 8338 (set_attr "mode" "SI")]) 8339 8340(define_insn "*iorsi_2" 8341 [(set (reg 17) 8342 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 8343 (match_operand:SI 2 "general_operand" "rim,ri")) 8344 (const_int 0))) 8345 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") 8346 (ior:SI (match_dup 1) (match_dup 2)))] 8347 "ix86_match_ccmode (insn, CCNOmode) 8348 && ix86_binary_operator_ok (IOR, SImode, operands)" 8349 "or{l}\t{%2, %0|%0, %2}" 8350 [(set_attr "type" "alu") 8351 (set_attr "mode" "SI")]) 8352 8353;; See comment for addsi_1_zext why we do use nonimmediate_operand 8354;; ??? Special case for immediate operand is missing - it is tricky. 8355(define_insn "*iorsi_2_zext" 8356 [(set (reg 17) 8357 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") 8358 (match_operand:SI 2 "general_operand" "rim")) 8359 (const_int 0))) 8360 (set (match_operand:DI 0 "register_operand" "=r") 8361 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))] 8362 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) 8363 && ix86_binary_operator_ok (IOR, SImode, operands)" 8364 "or{l}\t{%2, %k0|%k0, %2}" 8365 [(set_attr "type" "alu") 8366 (set_attr "mode" "SI")]) 8367 8368(define_insn "*iorsi_2_zext_imm" 8369 [(set (reg 17) 8370 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") 8371 (match_operand 2 "x86_64_zext_immediate_operand" "Z")) 8372 (const_int 0))) 8373 (set (match_operand:DI 0 "register_operand" "=r") 8374 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] 8375 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) 8376 && ix86_binary_operator_ok (IOR, SImode, operands)" 8377 "or{l}\t{%2, %k0|%k0, %2}" 8378 [(set_attr "type" "alu") 8379 (set_attr "mode" "SI")]) 8380 8381(define_insn "*iorsi_3" 8382 [(set (reg 17) 8383 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") 8384 (match_operand:SI 2 "general_operand" "rim")) 8385 (const_int 0))) 8386 (clobber (match_scratch:SI 0 "=r"))] 8387 "ix86_match_ccmode (insn, CCNOmode) 8388 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 8389 "or{l}\t{%2, %0|%0, %2}" 8390 [(set_attr "type" "alu") 8391 (set_attr "mode" "SI")]) 8392 8393(define_expand "iorhi3" 8394 [(set (match_operand:HI 0 "nonimmediate_operand" "") 8395 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") 8396 (match_operand:HI 2 "general_operand" ""))) 8397 (clobber (reg:CC 17))] 8398 "TARGET_HIMODE_MATH" 8399 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;") 8400 8401(define_insn "*iorhi_1" 8402 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m") 8403 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") 8404 (match_operand:HI 2 "general_operand" "rmi,ri"))) 8405 (clobber (reg:CC 17))] 8406 "ix86_binary_operator_ok (IOR, HImode, operands)" 8407 "or{w}\t{%2, %0|%0, %2}" 8408 [(set_attr "type" "alu") 8409 (set_attr "mode" "HI")]) 8410 8411(define_insn "*iorhi_2" 8412 [(set (reg 17) 8413 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") 8414 (match_operand:HI 2 "general_operand" "rim,ri")) 8415 (const_int 0))) 8416 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") 8417 (ior:HI (match_dup 1) (match_dup 2)))] 8418 "ix86_match_ccmode (insn, CCNOmode) 8419 && ix86_binary_operator_ok (IOR, HImode, operands)" 8420 "or{w}\t{%2, %0|%0, %2}" 8421 [(set_attr "type" "alu") 8422 (set_attr "mode" "HI")]) 8423 8424(define_insn "*iorhi_3" 8425 [(set (reg 17) 8426 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0") 8427 (match_operand:HI 2 "general_operand" "rim")) 8428 (const_int 0))) 8429 (clobber (match_scratch:HI 0 "=r"))] 8430 "ix86_match_ccmode (insn, CCNOmode) 8431 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 8432 "or{w}\t{%2, %0|%0, %2}" 8433 [(set_attr "type" "alu") 8434 (set_attr "mode" "HI")]) 8435 8436(define_expand "iorqi3" 8437 [(set (match_operand:QI 0 "nonimmediate_operand" "") 8438 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") 8439 (match_operand:QI 2 "general_operand" ""))) 8440 (clobber (reg:CC 17))] 8441 "TARGET_QIMODE_MATH" 8442 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;") 8443 8444;; %%% Potential partial reg stall on alternative 2. What to do? 8445(define_insn "*iorqi_1" 8446 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r") 8447 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") 8448 (match_operand:QI 2 "general_operand" "qmi,qi,ri"))) 8449 (clobber (reg:CC 17))] 8450 "ix86_binary_operator_ok (IOR, QImode, operands)" 8451 "@ 8452 or{b}\t{%2, %0|%0, %2} 8453 or{b}\t{%2, %0|%0, %2} 8454 or{l}\t{%k2, %k0|%k0, %k2}" 8455 [(set_attr "type" "alu") 8456 (set_attr "mode" "QI,QI,SI")]) 8457 8458(define_insn "*iorqi_1_slp" 8459 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m")) 8460 (ior:QI (match_dup 0) 8461 (match_operand:QI 1 "general_operand" "qmi,qi"))) 8462 (clobber (reg:CC 17))] 8463 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 8464 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 8465 "or{b}\t{%1, %0|%0, %1}" 8466 [(set_attr "type" "alu1") 8467 (set_attr "mode" "QI")]) 8468 8469(define_insn "*iorqi_2" 8470 [(set (reg 17) 8471 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") 8472 (match_operand:QI 2 "general_operand" "qim,qi")) 8473 (const_int 0))) 8474 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm") 8475 (ior:QI (match_dup 1) (match_dup 2)))] 8476 "ix86_match_ccmode (insn, CCNOmode) 8477 && ix86_binary_operator_ok (IOR, QImode, operands)" 8478 "or{b}\t{%2, %0|%0, %2}" 8479 [(set_attr "type" "alu") 8480 (set_attr "mode" "QI")]) 8481 8482(define_insn "*iorqi_2_slp" 8483 [(set (reg 17) 8484 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm") 8485 (match_operand:QI 1 "general_operand" "qim,qi")) 8486 (const_int 0))) 8487 (set (strict_low_part (match_dup 0)) 8488 (ior:QI (match_dup 0) (match_dup 1)))] 8489 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 8490 && ix86_match_ccmode (insn, CCNOmode) 8491 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 8492 "or{b}\t{%1, %0|%0, %1}" 8493 [(set_attr "type" "alu1") 8494 (set_attr "mode" "QI")]) 8495 8496(define_insn "*iorqi_3" 8497 [(set (reg 17) 8498 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0") 8499 (match_operand:QI 2 "general_operand" "qim")) 8500 (const_int 0))) 8501 (clobber (match_scratch:QI 0 "=q"))] 8502 "ix86_match_ccmode (insn, CCNOmode) 8503 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 8504 "or{b}\t{%2, %0|%0, %2}" 8505 [(set_attr "type" "alu") 8506 (set_attr "mode" "QI")]) 8507 8508(define_insn "iorqi_ext_0" 8509 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8510 (const_int 8) 8511 (const_int 8)) 8512 (ior:SI 8513 (zero_extract:SI 8514 (match_operand 1 "ext_register_operand" "0") 8515 (const_int 8) 8516 (const_int 8)) 8517 (match_operand 2 "const_int_operand" "n"))) 8518 (clobber (reg:CC 17))] 8519 "(!TARGET_PARTIAL_REG_STALL || optimize_size)" 8520 "or{b}\t{%2, %h0|%h0, %2}" 8521 [(set_attr "type" "alu") 8522 (set_attr "length_immediate" "1") 8523 (set_attr "mode" "QI")]) 8524 8525(define_insn "*iorqi_ext_1" 8526 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8527 (const_int 8) 8528 (const_int 8)) 8529 (ior:SI 8530 (zero_extract:SI 8531 (match_operand 1 "ext_register_operand" "0") 8532 (const_int 8) 8533 (const_int 8)) 8534 (zero_extend:SI 8535 (match_operand:QI 2 "general_operand" "Qm")))) 8536 (clobber (reg:CC 17))] 8537 "!TARGET_64BIT 8538 && (!TARGET_PARTIAL_REG_STALL || optimize_size)" 8539 "or{b}\t{%2, %h0|%h0, %2}" 8540 [(set_attr "type" "alu") 8541 (set_attr "length_immediate" "0") 8542 (set_attr "mode" "QI")]) 8543 8544(define_insn "*iorqi_ext_1_rex64" 8545 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8546 (const_int 8) 8547 (const_int 8)) 8548 (ior:SI 8549 (zero_extract:SI 8550 (match_operand 1 "ext_register_operand" "0") 8551 (const_int 8) 8552 (const_int 8)) 8553 (zero_extend:SI 8554 (match_operand 2 "ext_register_operand" "Q")))) 8555 (clobber (reg:CC 17))] 8556 "TARGET_64BIT 8557 && (!TARGET_PARTIAL_REG_STALL || optimize_size)" 8558 "or{b}\t{%2, %h0|%h0, %2}" 8559 [(set_attr "type" "alu") 8560 (set_attr "length_immediate" "0") 8561 (set_attr "mode" "QI")]) 8562 8563(define_insn "*iorqi_ext_2" 8564 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8565 (const_int 8) 8566 (const_int 8)) 8567 (ior:SI 8568 (zero_extract:SI (match_operand 1 "ext_register_operand" "0") 8569 (const_int 8) 8570 (const_int 8)) 8571 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q") 8572 (const_int 8) 8573 (const_int 8)))) 8574 (clobber (reg:CC 17))] 8575 "(!TARGET_PARTIAL_REG_STALL || optimize_size)" 8576 "ior{b}\t{%h2, %h0|%h0, %h2}" 8577 [(set_attr "type" "alu") 8578 (set_attr "length_immediate" "0") 8579 (set_attr "mode" "QI")]) 8580 8581(define_split 8582 [(set (match_operand 0 "register_operand" "") 8583 (ior (match_operand 1 "register_operand" "") 8584 (match_operand 2 "const_int_operand" ""))) 8585 (clobber (reg:CC 17))] 8586 "reload_completed 8587 && QI_REG_P (operands[0]) 8588 && (!TARGET_PARTIAL_REG_STALL || optimize_size) 8589 && !(INTVAL (operands[2]) & ~(255 << 8)) 8590 && GET_MODE (operands[0]) != QImode" 8591 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) 8592 (ior:SI (zero_extract:SI (match_dup 1) 8593 (const_int 8) (const_int 8)) 8594 (match_dup 2))) 8595 (clobber (reg:CC 17))])] 8596 "operands[0] = gen_lowpart (SImode, operands[0]); 8597 operands[1] = gen_lowpart (SImode, operands[1]); 8598 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") 8599 8600;; Since OR can be encoded with sign extended immediate, this is only 8601;; profitable when 7th bit is set. 8602(define_split 8603 [(set (match_operand 0 "register_operand" "") 8604 (ior (match_operand 1 "general_operand" "") 8605 (match_operand 2 "const_int_operand" ""))) 8606 (clobber (reg:CC 17))] 8607 "reload_completed 8608 && ANY_QI_REG_P (operands[0]) 8609 && (!TARGET_PARTIAL_REG_STALL || optimize_size) 8610 && !(INTVAL (operands[2]) & ~255) 8611 && (INTVAL (operands[2]) & 128) 8612 && GET_MODE (operands[0]) != QImode" 8613 [(parallel [(set (strict_low_part (match_dup 0)) 8614 (ior:QI (match_dup 1) 8615 (match_dup 2))) 8616 (clobber (reg:CC 17))])] 8617 "operands[0] = gen_lowpart (QImode, operands[0]); 8618 operands[1] = gen_lowpart (QImode, operands[1]); 8619 operands[2] = gen_lowpart (QImode, operands[2]);") 8620 8621;; Logical XOR instructions 8622 8623;; %%% This used to optimize known byte-wide and operations to memory. 8624;; If this is considered useful, it should be done with splitters. 8625 8626(define_expand "xordi3" 8627 [(set (match_operand:DI 0 "nonimmediate_operand" "") 8628 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") 8629 (match_operand:DI 2 "x86_64_general_operand" ""))) 8630 (clobber (reg:CC 17))] 8631 "TARGET_64BIT" 8632 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;") 8633 8634(define_insn "*xordi_1_rex64" 8635 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") 8636 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 8637 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) 8638 (clobber (reg:CC 17))] 8639 "TARGET_64BIT 8640 && ix86_binary_operator_ok (XOR, DImode, operands)" 8641 "@ 8642 xor{q}\t{%2, %0|%0, %2} 8643 xor{q}\t{%2, %0|%0, %2}" 8644 [(set_attr "type" "alu") 8645 (set_attr "mode" "DI,DI")]) 8646 8647(define_insn "*xordi_2_rex64" 8648 [(set (reg 17) 8649 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") 8650 (match_operand:DI 2 "x86_64_general_operand" "rem,re")) 8651 (const_int 0))) 8652 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") 8653 (xor:DI (match_dup 1) (match_dup 2)))] 8654 "TARGET_64BIT 8655 && ix86_match_ccmode (insn, CCNOmode) 8656 && ix86_binary_operator_ok (XOR, DImode, operands)" 8657 "@ 8658 xor{q}\t{%2, %0|%0, %2} 8659 xor{q}\t{%2, %0|%0, %2}" 8660 [(set_attr "type" "alu") 8661 (set_attr "mode" "DI,DI")]) 8662 8663(define_insn "*xordi_3_rex64" 8664 [(set (reg 17) 8665 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0") 8666 (match_operand:DI 2 "x86_64_general_operand" "rem")) 8667 (const_int 0))) 8668 (clobber (match_scratch:DI 0 "=r"))] 8669 "TARGET_64BIT 8670 && ix86_match_ccmode (insn, CCNOmode) 8671 && ix86_binary_operator_ok (XOR, DImode, operands)" 8672 "xor{q}\t{%2, %0|%0, %2}" 8673 [(set_attr "type" "alu") 8674 (set_attr "mode" "DI")]) 8675 8676(define_expand "xorsi3" 8677 [(set (match_operand:SI 0 "nonimmediate_operand" "") 8678 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "") 8679 (match_operand:SI 2 "general_operand" ""))) 8680 (clobber (reg:CC 17))] 8681 "" 8682 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;") 8683 8684(define_insn "*xorsi_1" 8685 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 8686 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 8687 (match_operand:SI 2 "general_operand" "ri,rm"))) 8688 (clobber (reg:CC 17))] 8689 "ix86_binary_operator_ok (XOR, SImode, operands)" 8690 "xor{l}\t{%2, %0|%0, %2}" 8691 [(set_attr "type" "alu") 8692 (set_attr "mode" "SI")]) 8693 8694;; See comment for addsi_1_zext why we do use nonimmediate_operand 8695;; Add speccase for immediates 8696(define_insn "*xorsi_1_zext" 8697 [(set (match_operand:DI 0 "register_operand" "=r") 8698 (zero_extend:DI 8699 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") 8700 (match_operand:SI 2 "general_operand" "rim")))) 8701 (clobber (reg:CC 17))] 8702 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)" 8703 "xor{l}\t{%2, %k0|%k0, %2}" 8704 [(set_attr "type" "alu") 8705 (set_attr "mode" "SI")]) 8706 8707(define_insn "*xorsi_1_zext_imm" 8708 [(set (match_operand:DI 0 "register_operand" "=r") 8709 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) 8710 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z"))) 8711 (clobber (reg:CC 17))] 8712 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)" 8713 "xor{l}\t{%2, %k0|%k0, %2}" 8714 [(set_attr "type" "alu") 8715 (set_attr "mode" "SI")]) 8716 8717(define_insn "*xorsi_2" 8718 [(set (reg 17) 8719 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") 8720 (match_operand:SI 2 "general_operand" "rim,ri")) 8721 (const_int 0))) 8722 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") 8723 (xor:SI (match_dup 1) (match_dup 2)))] 8724 "ix86_match_ccmode (insn, CCNOmode) 8725 && ix86_binary_operator_ok (XOR, SImode, operands)" 8726 "xor{l}\t{%2, %0|%0, %2}" 8727 [(set_attr "type" "alu") 8728 (set_attr "mode" "SI")]) 8729 8730;; See comment for addsi_1_zext why we do use nonimmediate_operand 8731;; ??? Special case for immediate operand is missing - it is tricky. 8732(define_insn "*xorsi_2_zext" 8733 [(set (reg 17) 8734 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") 8735 (match_operand:SI 2 "general_operand" "rim")) 8736 (const_int 0))) 8737 (set (match_operand:DI 0 "register_operand" "=r") 8738 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))] 8739 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) 8740 && ix86_binary_operator_ok (XOR, SImode, operands)" 8741 "xor{l}\t{%2, %k0|%k0, %2}" 8742 [(set_attr "type" "alu") 8743 (set_attr "mode" "SI")]) 8744 8745(define_insn "*xorsi_2_zext_imm" 8746 [(set (reg 17) 8747 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") 8748 (match_operand 2 "x86_64_zext_immediate_operand" "Z")) 8749 (const_int 0))) 8750 (set (match_operand:DI 0 "register_operand" "=r") 8751 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] 8752 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) 8753 && ix86_binary_operator_ok (XOR, SImode, operands)" 8754 "xor{l}\t{%2, %k0|%k0, %2}" 8755 [(set_attr "type" "alu") 8756 (set_attr "mode" "SI")]) 8757 8758(define_insn "*xorsi_3" 8759 [(set (reg 17) 8760 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") 8761 (match_operand:SI 2 "general_operand" "rim")) 8762 (const_int 0))) 8763 (clobber (match_scratch:SI 0 "=r"))] 8764 "ix86_match_ccmode (insn, CCNOmode) 8765 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 8766 "xor{l}\t{%2, %0|%0, %2}" 8767 [(set_attr "type" "alu") 8768 (set_attr "mode" "SI")]) 8769 8770(define_expand "xorhi3" 8771 [(set (match_operand:HI 0 "nonimmediate_operand" "") 8772 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") 8773 (match_operand:HI 2 "general_operand" ""))) 8774 (clobber (reg:CC 17))] 8775 "TARGET_HIMODE_MATH" 8776 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;") 8777 8778(define_insn "*xorhi_1" 8779 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m") 8780 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") 8781 (match_operand:HI 2 "general_operand" "rmi,ri"))) 8782 (clobber (reg:CC 17))] 8783 "ix86_binary_operator_ok (XOR, HImode, operands)" 8784 "xor{w}\t{%2, %0|%0, %2}" 8785 [(set_attr "type" "alu") 8786 (set_attr "mode" "HI")]) 8787 8788(define_insn "*xorhi_2" 8789 [(set (reg 17) 8790 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") 8791 (match_operand:HI 2 "general_operand" "rim,ri")) 8792 (const_int 0))) 8793 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") 8794 (xor:HI (match_dup 1) (match_dup 2)))] 8795 "ix86_match_ccmode (insn, CCNOmode) 8796 && ix86_binary_operator_ok (XOR, HImode, operands)" 8797 "xor{w}\t{%2, %0|%0, %2}" 8798 [(set_attr "type" "alu") 8799 (set_attr "mode" "HI")]) 8800 8801(define_insn "*xorhi_3" 8802 [(set (reg 17) 8803 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0") 8804 (match_operand:HI 2 "general_operand" "rim")) 8805 (const_int 0))) 8806 (clobber (match_scratch:HI 0 "=r"))] 8807 "ix86_match_ccmode (insn, CCNOmode) 8808 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 8809 "xor{w}\t{%2, %0|%0, %2}" 8810 [(set_attr "type" "alu") 8811 (set_attr "mode" "HI")]) 8812 8813(define_expand "xorqi3" 8814 [(set (match_operand:QI 0 "nonimmediate_operand" "") 8815 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") 8816 (match_operand:QI 2 "general_operand" ""))) 8817 (clobber (reg:CC 17))] 8818 "TARGET_QIMODE_MATH" 8819 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;") 8820 8821;; %%% Potential partial reg stall on alternative 2. What to do? 8822(define_insn "*xorqi_1" 8823 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r") 8824 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") 8825 (match_operand:QI 2 "general_operand" "qmi,qi,ri"))) 8826 (clobber (reg:CC 17))] 8827 "ix86_binary_operator_ok (XOR, QImode, operands)" 8828 "@ 8829 xor{b}\t{%2, %0|%0, %2} 8830 xor{b}\t{%2, %0|%0, %2} 8831 xor{l}\t{%k2, %k0|%k0, %k2}" 8832 [(set_attr "type" "alu") 8833 (set_attr "mode" "QI,QI,SI")]) 8834 8835(define_insn "*xorqi_1_slp" 8836 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) 8837 (xor:QI (match_dup 0) 8838 (match_operand:QI 1 "general_operand" "qi,qmi"))) 8839 (clobber (reg:CC 17))] 8840 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 8841 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 8842 "xor{b}\t{%1, %0|%0, %1}" 8843 [(set_attr "type" "alu1") 8844 (set_attr "mode" "QI")]) 8845 8846(define_insn "xorqi_ext_0" 8847 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8848 (const_int 8) 8849 (const_int 8)) 8850 (xor:SI 8851 (zero_extract:SI 8852 (match_operand 1 "ext_register_operand" "0") 8853 (const_int 8) 8854 (const_int 8)) 8855 (match_operand 2 "const_int_operand" "n"))) 8856 (clobber (reg:CC 17))] 8857 "(!TARGET_PARTIAL_REG_STALL || optimize_size)" 8858 "xor{b}\t{%2, %h0|%h0, %2}" 8859 [(set_attr "type" "alu") 8860 (set_attr "length_immediate" "1") 8861 (set_attr "mode" "QI")]) 8862 8863(define_insn "*xorqi_ext_1" 8864 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8865 (const_int 8) 8866 (const_int 8)) 8867 (xor:SI 8868 (zero_extract:SI 8869 (match_operand 1 "ext_register_operand" "0") 8870 (const_int 8) 8871 (const_int 8)) 8872 (zero_extend:SI 8873 (match_operand:QI 2 "general_operand" "Qm")))) 8874 (clobber (reg:CC 17))] 8875 "!TARGET_64BIT 8876 && (!TARGET_PARTIAL_REG_STALL || optimize_size)" 8877 "xor{b}\t{%2, %h0|%h0, %2}" 8878 [(set_attr "type" "alu") 8879 (set_attr "length_immediate" "0") 8880 (set_attr "mode" "QI")]) 8881 8882(define_insn "*xorqi_ext_1_rex64" 8883 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8884 (const_int 8) 8885 (const_int 8)) 8886 (xor:SI 8887 (zero_extract:SI 8888 (match_operand 1 "ext_register_operand" "0") 8889 (const_int 8) 8890 (const_int 8)) 8891 (zero_extend:SI 8892 (match_operand 2 "ext_register_operand" "Q")))) 8893 (clobber (reg:CC 17))] 8894 "TARGET_64BIT 8895 && (!TARGET_PARTIAL_REG_STALL || optimize_size)" 8896 "xor{b}\t{%2, %h0|%h0, %2}" 8897 [(set_attr "type" "alu") 8898 (set_attr "length_immediate" "0") 8899 (set_attr "mode" "QI")]) 8900 8901(define_insn "*xorqi_ext_2" 8902 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8903 (const_int 8) 8904 (const_int 8)) 8905 (xor:SI 8906 (zero_extract:SI (match_operand 1 "ext_register_operand" "0") 8907 (const_int 8) 8908 (const_int 8)) 8909 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q") 8910 (const_int 8) 8911 (const_int 8)))) 8912 (clobber (reg:CC 17))] 8913 "(!TARGET_PARTIAL_REG_STALL || optimize_size)" 8914 "xor{b}\t{%h2, %h0|%h0, %h2}" 8915 [(set_attr "type" "alu") 8916 (set_attr "length_immediate" "0") 8917 (set_attr "mode" "QI")]) 8918 8919(define_insn "*xorqi_cc_1" 8920 [(set (reg 17) 8921 (compare 8922 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") 8923 (match_operand:QI 2 "general_operand" "qim,qi")) 8924 (const_int 0))) 8925 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm") 8926 (xor:QI (match_dup 1) (match_dup 2)))] 8927 "ix86_match_ccmode (insn, CCNOmode) 8928 && ix86_binary_operator_ok (XOR, QImode, operands)" 8929 "xor{b}\t{%2, %0|%0, %2}" 8930 [(set_attr "type" "alu") 8931 (set_attr "mode" "QI")]) 8932 8933(define_insn "*xorqi_2_slp" 8934 [(set (reg 17) 8935 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm") 8936 (match_operand:QI 1 "general_operand" "qim,qi")) 8937 (const_int 0))) 8938 (set (strict_low_part (match_dup 0)) 8939 (xor:QI (match_dup 0) (match_dup 1)))] 8940 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 8941 && ix86_match_ccmode (insn, CCNOmode) 8942 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 8943 "xor{b}\t{%1, %0|%0, %1}" 8944 [(set_attr "type" "alu1") 8945 (set_attr "mode" "QI")]) 8946 8947(define_insn "*xorqi_cc_2" 8948 [(set (reg 17) 8949 (compare 8950 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0") 8951 (match_operand:QI 2 "general_operand" "qim")) 8952 (const_int 0))) 8953 (clobber (match_scratch:QI 0 "=q"))] 8954 "ix86_match_ccmode (insn, CCNOmode) 8955 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 8956 "xor{b}\t{%2, %0|%0, %2}" 8957 [(set_attr "type" "alu") 8958 (set_attr "mode" "QI")]) 8959 8960(define_insn "*xorqi_cc_ext_1" 8961 [(set (reg 17) 8962 (compare 8963 (xor:SI 8964 (zero_extract:SI 8965 (match_operand 1 "ext_register_operand" "0") 8966 (const_int 8) 8967 (const_int 8)) 8968 (match_operand:QI 2 "general_operand" "qmn")) 8969 (const_int 0))) 8970 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q") 8971 (const_int 8) 8972 (const_int 8)) 8973 (xor:SI 8974 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8)) 8975 (match_dup 2)))] 8976 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" 8977 "xor{b}\t{%2, %h0|%h0, %2}" 8978 [(set_attr "type" "alu") 8979 (set_attr "mode" "QI")]) 8980 8981(define_insn "*xorqi_cc_ext_1_rex64" 8982 [(set (reg 17) 8983 (compare 8984 (xor:SI 8985 (zero_extract:SI 8986 (match_operand 1 "ext_register_operand" "0") 8987 (const_int 8) 8988 (const_int 8)) 8989 (match_operand:QI 2 "nonmemory_operand" "Qn")) 8990 (const_int 0))) 8991 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") 8992 (const_int 8) 8993 (const_int 8)) 8994 (xor:SI 8995 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8)) 8996 (match_dup 2)))] 8997 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" 8998 "xor{b}\t{%2, %h0|%h0, %2}" 8999 [(set_attr "type" "alu") 9000 (set_attr "mode" "QI")]) 9001 9002(define_expand "xorqi_cc_ext_1" 9003 [(parallel [ 9004 (set (reg:CCNO 17) 9005 (compare:CCNO 9006 (xor:SI 9007 (zero_extract:SI 9008 (match_operand 1 "ext_register_operand" "") 9009 (const_int 8) 9010 (const_int 8)) 9011 (match_operand:QI 2 "general_operand" "")) 9012 (const_int 0))) 9013 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "") 9014 (const_int 8) 9015 (const_int 8)) 9016 (xor:SI 9017 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8)) 9018 (match_dup 2)))])] 9019 "" 9020 "") 9021 9022(define_split 9023 [(set (match_operand 0 "register_operand" "") 9024 (xor (match_operand 1 "register_operand" "") 9025 (match_operand 2 "const_int_operand" ""))) 9026 (clobber (reg:CC 17))] 9027 "reload_completed 9028 && QI_REG_P (operands[0]) 9029 && (!TARGET_PARTIAL_REG_STALL || optimize_size) 9030 && !(INTVAL (operands[2]) & ~(255 << 8)) 9031 && GET_MODE (operands[0]) != QImode" 9032 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) 9033 (xor:SI (zero_extract:SI (match_dup 1) 9034 (const_int 8) (const_int 8)) 9035 (match_dup 2))) 9036 (clobber (reg:CC 17))])] 9037 "operands[0] = gen_lowpart (SImode, operands[0]); 9038 operands[1] = gen_lowpart (SImode, operands[1]); 9039 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") 9040 9041;; Since XOR can be encoded with sign extended immediate, this is only 9042;; profitable when 7th bit is set. 9043(define_split 9044 [(set (match_operand 0 "register_operand" "") 9045 (xor (match_operand 1 "general_operand" "") 9046 (match_operand 2 "const_int_operand" ""))) 9047 (clobber (reg:CC 17))] 9048 "reload_completed 9049 && ANY_QI_REG_P (operands[0]) 9050 && (!TARGET_PARTIAL_REG_STALL || optimize_size) 9051 && !(INTVAL (operands[2]) & ~255) 9052 && (INTVAL (operands[2]) & 128) 9053 && GET_MODE (operands[0]) != QImode" 9054 [(parallel [(set (strict_low_part (match_dup 0)) 9055 (xor:QI (match_dup 1) 9056 (match_dup 2))) 9057 (clobber (reg:CC 17))])] 9058 "operands[0] = gen_lowpart (QImode, operands[0]); 9059 operands[1] = gen_lowpart (QImode, operands[1]); 9060 operands[2] = gen_lowpart (QImode, operands[2]);") 9061 9062;; Negation instructions 9063 9064(define_expand "negdi2" 9065 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") 9066 (neg:DI (match_operand:DI 1 "nonimmediate_operand" ""))) 9067 (clobber (reg:CC 17))])] 9068 "" 9069 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;") 9070 9071(define_insn "*negdi2_1" 9072 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro") 9073 (neg:DI (match_operand:DI 1 "general_operand" "0"))) 9074 (clobber (reg:CC 17))] 9075 "!TARGET_64BIT 9076 && ix86_unary_operator_ok (NEG, DImode, operands)" 9077 "#") 9078 9079(define_split 9080 [(set (match_operand:DI 0 "nonimmediate_operand" "") 9081 (neg:DI (match_operand:DI 1 "general_operand" ""))) 9082 (clobber (reg:CC 17))] 9083 "!TARGET_64BIT && reload_completed" 9084 [(parallel 9085 [(set (reg:CCZ 17) 9086 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0))) 9087 (set (match_dup 0) (neg:SI (match_dup 2)))]) 9088 (parallel 9089 [(set (match_dup 1) 9090 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) 9091 (match_dup 3)) 9092 (const_int 0))) 9093 (clobber (reg:CC 17))]) 9094 (parallel 9095 [(set (match_dup 1) 9096 (neg:SI (match_dup 1))) 9097 (clobber (reg:CC 17))])] 9098 "split_di (operands+1, 1, operands+2, operands+3); 9099 split_di (operands+0, 1, operands+0, operands+1);") 9100 9101(define_insn "*negdi2_1_rex64" 9102 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") 9103 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))) 9104 (clobber (reg:CC 17))] 9105 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)" 9106 "neg{q}\t%0" 9107 [(set_attr "type" "negnot") 9108 (set_attr "mode" "DI")]) 9109 9110;; The problem with neg is that it does not perform (compare x 0), 9111;; it really performs (compare 0 x), which leaves us with the zero 9112;; flag being the only useful item. 9113 9114(define_insn "*negdi2_cmpz_rex64" 9115 [(set (reg:CCZ 17) 9116 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")) 9117 (const_int 0))) 9118 (set (match_operand:DI 0 "nonimmediate_operand" "=rm") 9119 (neg:DI (match_dup 1)))] 9120 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)" 9121 "neg{q}\t%0" 9122 [(set_attr "type" "negnot") 9123 (set_attr "mode" "DI")]) 9124 9125 9126(define_expand "negsi2" 9127 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") 9128 (neg:SI (match_operand:SI 1 "nonimmediate_operand" ""))) 9129 (clobber (reg:CC 17))])] 9130 "" 9131 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;") 9132 9133(define_insn "*negsi2_1" 9134 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 9135 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))) 9136 (clobber (reg:CC 17))] 9137 "ix86_unary_operator_ok (NEG, SImode, operands)" 9138 "neg{l}\t%0" 9139 [(set_attr "type" "negnot") 9140 (set_attr "mode" "SI")]) 9141 9142;; Combine is quite creative about this pattern. 9143(define_insn "*negsi2_1_zext" 9144 [(set (match_operand:DI 0 "register_operand" "=r") 9145 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0") 9146 (const_int 32))) 9147 (const_int 32))) 9148 (clobber (reg:CC 17))] 9149 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)" 9150 "neg{l}\t%k0" 9151 [(set_attr "type" "negnot") 9152 (set_attr "mode" "SI")]) 9153 9154;; The problem with neg is that it does not perform (compare x 0), 9155;; it really performs (compare 0 x), which leaves us with the zero 9156;; flag being the only useful item. 9157 9158(define_insn "*negsi2_cmpz" 9159 [(set (reg:CCZ 17) 9160 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")) 9161 (const_int 0))) 9162 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 9163 (neg:SI (match_dup 1)))] 9164 "ix86_unary_operator_ok (NEG, SImode, operands)" 9165 "neg{l}\t%0" 9166 [(set_attr "type" "negnot") 9167 (set_attr "mode" "SI")]) 9168 9169(define_insn "*negsi2_cmpz_zext" 9170 [(set (reg:CCZ 17) 9171 (compare:CCZ (lshiftrt:DI 9172 (neg:DI (ashift:DI 9173 (match_operand:DI 1 "register_operand" "0") 9174 (const_int 32))) 9175 (const_int 32)) 9176 (const_int 0))) 9177 (set (match_operand:DI 0 "register_operand" "=r") 9178 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1) 9179 (const_int 32))) 9180 (const_int 32)))] 9181 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)" 9182 "neg{l}\t%k0" 9183 [(set_attr "type" "negnot") 9184 (set_attr "mode" "SI")]) 9185 9186(define_expand "neghi2" 9187 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") 9188 (neg:HI (match_operand:HI 1 "nonimmediate_operand" ""))) 9189 (clobber (reg:CC 17))])] 9190 "TARGET_HIMODE_MATH" 9191 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;") 9192 9193(define_insn "*neghi2_1" 9194 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 9195 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))) 9196 (clobber (reg:CC 17))] 9197 "ix86_unary_operator_ok (NEG, HImode, operands)" 9198 "neg{w}\t%0" 9199 [(set_attr "type" "negnot") 9200 (set_attr "mode" "HI")]) 9201 9202(define_insn "*neghi2_cmpz" 9203 [(set (reg:CCZ 17) 9204 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")) 9205 (const_int 0))) 9206 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 9207 (neg:HI (match_dup 1)))] 9208 "ix86_unary_operator_ok (NEG, HImode, operands)" 9209 "neg{w}\t%0" 9210 [(set_attr "type" "negnot") 9211 (set_attr "mode" "HI")]) 9212 9213(define_expand "negqi2" 9214 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "") 9215 (neg:QI (match_operand:QI 1 "nonimmediate_operand" ""))) 9216 (clobber (reg:CC 17))])] 9217 "TARGET_QIMODE_MATH" 9218 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;") 9219 9220(define_insn "*negqi2_1" 9221 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 9222 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))) 9223 (clobber (reg:CC 17))] 9224 "ix86_unary_operator_ok (NEG, QImode, operands)" 9225 "neg{b}\t%0" 9226 [(set_attr "type" "negnot") 9227 (set_attr "mode" "QI")]) 9228 9229(define_insn "*negqi2_cmpz" 9230 [(set (reg:CCZ 17) 9231 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")) 9232 (const_int 0))) 9233 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") 9234 (neg:QI (match_dup 1)))] 9235 "ix86_unary_operator_ok (NEG, QImode, operands)" 9236 "neg{b}\t%0" 9237 [(set_attr "type" "negnot") 9238 (set_attr "mode" "QI")]) 9239 9240;; Changing of sign for FP values is doable using integer unit too. 9241 9242(define_expand "negsf2" 9243 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") 9244 (neg:SF (match_operand:SF 1 "nonimmediate_operand" ""))) 9245 (clobber (reg:CC 17))])] 9246 "TARGET_80387" 9247 "if (TARGET_SSE) 9248 { 9249 /* In case operand is in memory, we will not use SSE. */ 9250 if (memory_operand (operands[0], VOIDmode) 9251 && rtx_equal_p (operands[0], operands[1])) 9252 emit_insn (gen_negsf2_memory (operands[0], operands[1])); 9253 else 9254 { 9255 /* Using SSE is tricky, since we need bitwise negation of -0 9256 in register. */ 9257 rtx reg = gen_reg_rtx (SFmode); 9258 rtx dest = operands[0]; 9259 9260 operands[1] = force_reg (SFmode, operands[1]); 9261 operands[0] = force_reg (SFmode, operands[0]); 9262 emit_move_insn (reg, 9263 gen_lowpart (SFmode, 9264 gen_int_mode (0x80000000, SImode))); 9265 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg)); 9266 if (dest != operands[0]) 9267 emit_move_insn (dest, operands[0]); 9268 } 9269 DONE; 9270 } 9271 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;") 9272 9273(define_insn "negsf2_memory" 9274 [(set (match_operand:SF 0 "memory_operand" "=m") 9275 (neg:SF (match_operand:SF 1 "memory_operand" "0"))) 9276 (clobber (reg:CC 17))] 9277 "ix86_unary_operator_ok (NEG, SFmode, operands)" 9278 "#") 9279 9280(define_insn "negsf2_ifs" 9281 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf") 9282 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0"))) 9283 (use (match_operand:SF 2 "nonmemory_operand" "x,0#x,*g#x,*g#x")) 9284 (clobber (reg:CC 17))] 9285 "TARGET_SSE 9286 && (reload_in_progress || reload_completed 9287 || (register_operand (operands[0], VOIDmode) 9288 && register_operand (operands[1], VOIDmode)))" 9289 "#") 9290 9291(define_split 9292 [(set (match_operand:SF 0 "memory_operand" "") 9293 (neg:SF (match_operand:SF 1 "memory_operand" ""))) 9294 (use (match_operand:SF 2 "" "")) 9295 (clobber (reg:CC 17))] 9296 "" 9297 [(parallel [(set (match_dup 0) 9298 (neg:SF (match_dup 1))) 9299 (clobber (reg:CC 17))])]) 9300 9301(define_split 9302 [(set (match_operand:SF 0 "register_operand" "") 9303 (neg:SF (match_operand:SF 1 "register_operand" ""))) 9304 (use (match_operand:SF 2 "" "")) 9305 (clobber (reg:CC 17))] 9306 "reload_completed && !SSE_REG_P (operands[0])" 9307 [(parallel [(set (match_dup 0) 9308 (neg:SF (match_dup 1))) 9309 (clobber (reg:CC 17))])]) 9310 9311(define_split 9312 [(set (match_operand:SF 0 "register_operand" "") 9313 (neg:SF (match_operand:SF 1 "register_operand" ""))) 9314 (use (match_operand:SF 2 "register_operand" "")) 9315 (clobber (reg:CC 17))] 9316 "reload_completed && SSE_REG_P (operands[0])" 9317 [(set (subreg:TI (match_dup 0) 0) 9318 (xor:TI (subreg:TI (match_dup 1) 0) 9319 (subreg:TI (match_dup 2) 0)))] 9320{ 9321 if (operands_match_p (operands[0], operands[2])) 9322 { 9323 rtx tmp; 9324 tmp = operands[1]; 9325 operands[1] = operands[2]; 9326 operands[2] = tmp; 9327 } 9328}) 9329 9330 9331;; Keep 'f' and 'r' in separate alternatives to avoid reload problems 9332;; because of secondary memory needed to reload from class FLOAT_INT_REGS 9333;; to itself. 9334(define_insn "*negsf2_if" 9335 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f") 9336 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0"))) 9337 (clobber (reg:CC 17))] 9338 "TARGET_80387 && !TARGET_SSE 9339 && ix86_unary_operator_ok (NEG, SFmode, operands)" 9340 "#") 9341 9342(define_split 9343 [(set (match_operand:SF 0 "fp_register_operand" "") 9344 (neg:SF (match_operand:SF 1 "register_operand" ""))) 9345 (clobber (reg:CC 17))] 9346 "TARGET_80387 && reload_completed" 9347 [(set (match_dup 0) 9348 (neg:SF (match_dup 1)))] 9349 "") 9350 9351(define_split 9352 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "") 9353 (neg:SF (match_operand:SF 1 "register_operand" ""))) 9354 (clobber (reg:CC 17))] 9355 "TARGET_80387 && reload_completed" 9356 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) 9357 (clobber (reg:CC 17))])] 9358 "operands[1] = gen_int_mode (0x80000000, SImode); 9359 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));") 9360 9361(define_split 9362 [(set (match_operand 0 "memory_operand" "") 9363 (neg (match_operand 1 "memory_operand" ""))) 9364 (clobber (reg:CC 17))] 9365 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))" 9366 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) 9367 (clobber (reg:CC 17))])] 9368{ 9369 int size = GET_MODE_SIZE (GET_MODE (operands[1])); 9370 9371 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */ 9372 if (size >= 12) 9373 size = 10; 9374 operands[0] = adjust_address (operands[0], QImode, size - 1); 9375 operands[1] = gen_int_mode (0x80, QImode); 9376}) 9377 9378(define_expand "negdf2" 9379 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") 9380 (neg:DF (match_operand:DF 1 "nonimmediate_operand" ""))) 9381 (clobber (reg:CC 17))])] 9382 "TARGET_80387" 9383 "if (TARGET_SSE2) 9384 { 9385 /* In case operand is in memory, we will not use SSE. */ 9386 if (memory_operand (operands[0], VOIDmode) 9387 && rtx_equal_p (operands[0], operands[1])) 9388 emit_insn (gen_negdf2_memory (operands[0], operands[1])); 9389 else 9390 { 9391 /* Using SSE is tricky, since we need bitwise negation of -0 9392 in register. */ 9393 rtx reg = gen_reg_rtx (DFmode); 9394#if HOST_BITS_PER_WIDE_INT >= 64 9395 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode); 9396#else 9397 rtx imm = immed_double_const (0, 0x80000000, DImode); 9398#endif 9399 rtx dest = operands[0]; 9400 9401 operands[1] = force_reg (DFmode, operands[1]); 9402 operands[0] = force_reg (DFmode, operands[0]); 9403 emit_move_insn (reg, gen_lowpart (DFmode, imm)); 9404 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg)); 9405 if (dest != operands[0]) 9406 emit_move_insn (dest, operands[0]); 9407 } 9408 DONE; 9409 } 9410 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;") 9411 9412(define_insn "negdf2_memory" 9413 [(set (match_operand:DF 0 "memory_operand" "=m") 9414 (neg:DF (match_operand:DF 1 "memory_operand" "0"))) 9415 (clobber (reg:CC 17))] 9416 "ix86_unary_operator_ok (NEG, DFmode, operands)" 9417 "#") 9418 9419(define_insn "negdf2_ifs" 9420 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf") 9421 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0"))) 9422 (use (match_operand:DF 2 "nonmemory_operand" "Y,0,*g#Y,*g#Y")) 9423 (clobber (reg:CC 17))] 9424 "!TARGET_64BIT && TARGET_SSE2 9425 && (reload_in_progress || reload_completed 9426 || (register_operand (operands[0], VOIDmode) 9427 && register_operand (operands[1], VOIDmode)))" 9428 "#") 9429 9430(define_insn "*negdf2_ifs_rex64" 9431 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y") 9432 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#f,0"))) 9433 (use (match_operand:DF 2 "general_operand" "Y,0,*g#Y*r")) 9434 (clobber (reg:CC 17))] 9435 "TARGET_64BIT && TARGET_SSE2 9436 && (reload_in_progress || reload_completed 9437 || (register_operand (operands[0], VOIDmode) 9438 && register_operand (operands[1], VOIDmode)))" 9439 "#") 9440 9441(define_split 9442 [(set (match_operand:DF 0 "memory_operand" "") 9443 (neg:DF (match_operand:DF 1 "memory_operand" ""))) 9444 (use (match_operand:DF 2 "" "")) 9445 (clobber (reg:CC 17))] 9446 "" 9447 [(parallel [(set (match_dup 0) 9448 (neg:DF (match_dup 1))) 9449 (clobber (reg:CC 17))])]) 9450 9451(define_split 9452 [(set (match_operand:DF 0 "register_operand" "") 9453 (neg:DF (match_operand:DF 1 "register_operand" ""))) 9454 (use (match_operand:DF 2 "" "")) 9455 (clobber (reg:CC 17))] 9456 "reload_completed && !SSE_REG_P (operands[0]) 9457 && (!TARGET_64BIT || FP_REG_P (operands[0]))" 9458 [(parallel [(set (match_dup 0) 9459 (neg:DF (match_dup 1))) 9460 (clobber (reg:CC 17))])]) 9461 9462(define_split 9463 [(set (match_operand:DF 0 "register_operand" "") 9464 (neg:DF (match_operand:DF 1 "register_operand" ""))) 9465 (use (match_operand:DF 2 "" "")) 9466 (clobber (reg:CC 17))] 9467 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])" 9468 [(parallel [(set (match_dup 0) 9469 (xor:DI (match_dup 1) (match_dup 2))) 9470 (clobber (reg:CC 17))])] 9471 "operands[0] = gen_lowpart (DImode, operands[0]); 9472 operands[1] = gen_lowpart (DImode, operands[1]); 9473 operands[2] = gen_lowpart (DImode, operands[2]);") 9474 9475(define_split 9476 [(set (match_operand:DF 0 "register_operand" "") 9477 (neg:DF (match_operand:DF 1 "register_operand" ""))) 9478 (use (match_operand:DF 2 "register_operand" "")) 9479 (clobber (reg:CC 17))] 9480 "reload_completed && SSE_REG_P (operands[0])" 9481 [(set (subreg:TI (match_dup 0) 0) 9482 (xor:TI (subreg:TI (match_dup 1) 0) 9483 (subreg:TI (match_dup 2) 0)))] 9484{ 9485 if (operands_match_p (operands[0], operands[2])) 9486 { 9487 rtx tmp; 9488 tmp = operands[1]; 9489 operands[1] = operands[2]; 9490 operands[2] = tmp; 9491 } 9492}) 9493 9494;; Keep 'f' and 'r' in separate alternatives to avoid reload problems 9495;; because of secondary memory needed to reload from class FLOAT_INT_REGS 9496;; to itself. 9497(define_insn "*negdf2_if" 9498 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f") 9499 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) 9500 (clobber (reg:CC 17))] 9501 "!TARGET_64BIT && TARGET_80387 9502 && ix86_unary_operator_ok (NEG, DFmode, operands)" 9503 "#") 9504 9505;; FIXME: We should to allow integer registers here. Problem is that 9506;; we need another scratch register to get constant from. 9507;; Forcing constant to mem if no register available in peep2 should be 9508;; safe even for PIC mode, because of RIP relative addressing. 9509(define_insn "*negdf2_if_rex64" 9510 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf") 9511 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) 9512 (clobber (reg:CC 17))] 9513 "TARGET_64BIT && TARGET_80387 9514 && ix86_unary_operator_ok (NEG, DFmode, operands)" 9515 "#") 9516 9517(define_split 9518 [(set (match_operand:DF 0 "fp_register_operand" "") 9519 (neg:DF (match_operand:DF 1 "register_operand" ""))) 9520 (clobber (reg:CC 17))] 9521 "TARGET_80387 && reload_completed" 9522 [(set (match_dup 0) 9523 (neg:DF (match_dup 1)))] 9524 "") 9525 9526(define_split 9527 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "") 9528 (neg:DF (match_operand:DF 1 "register_operand" ""))) 9529 (clobber (reg:CC 17))] 9530 "!TARGET_64BIT && TARGET_80387 && reload_completed" 9531 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4))) 9532 (clobber (reg:CC 17))])] 9533 "operands[4] = gen_int_mode (0x80000000, SImode); 9534 split_di (operands+0, 1, operands+2, operands+3);") 9535 9536(define_expand "negxf2" 9537 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "") 9538 (neg:XF (match_operand:XF 1 "nonimmediate_operand" ""))) 9539 (clobber (reg:CC 17))])] 9540 "!TARGET_64BIT && TARGET_80387" 9541 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;") 9542 9543(define_expand "negtf2" 9544 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") 9545 (neg:TF (match_operand:TF 1 "nonimmediate_operand" ""))) 9546 (clobber (reg:CC 17))])] 9547 "TARGET_80387" 9548 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;") 9549 9550;; Keep 'f' and 'r' in separate alternatives to avoid reload problems 9551;; because of secondary memory needed to reload from class FLOAT_INT_REGS 9552;; to itself. 9553(define_insn "*negxf2_if" 9554 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f") 9555 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0"))) 9556 (clobber (reg:CC 17))] 9557 "!TARGET_64BIT && TARGET_80387 9558 && ix86_unary_operator_ok (NEG, XFmode, operands)" 9559 "#") 9560 9561(define_split 9562 [(set (match_operand:XF 0 "fp_register_operand" "") 9563 (neg:XF (match_operand:XF 1 "register_operand" ""))) 9564 (clobber (reg:CC 17))] 9565 "TARGET_80387 && reload_completed" 9566 [(set (match_dup 0) 9567 (neg:XF (match_dup 1)))] 9568 "") 9569 9570(define_split 9571 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "") 9572 (neg:XF (match_operand:XF 1 "register_operand" ""))) 9573 (clobber (reg:CC 17))] 9574 "TARGET_80387 && reload_completed" 9575 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) 9576 (clobber (reg:CC 17))])] 9577 "operands[1] = GEN_INT (0x8000); 9578 operands[0] = gen_rtx_REG (SImode, 9579 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") 9580 9581;; Keep 'f' and 'r' in separate alternatives to avoid reload problems 9582;; because of secondary memory needed to reload from class FLOAT_INT_REGS 9583;; to itself. 9584(define_insn "*negtf2_if" 9585 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f") 9586 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0"))) 9587 (clobber (reg:CC 17))] 9588 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)" 9589 "#") 9590 9591(define_split 9592 [(set (match_operand:TF 0 "fp_register_operand" "") 9593 (neg:TF (match_operand:TF 1 "register_operand" ""))) 9594 (clobber (reg:CC 17))] 9595 "TARGET_80387 && reload_completed" 9596 [(set (match_dup 0) 9597 (neg:TF (match_dup 1)))] 9598 "") 9599 9600(define_split 9601 [(set (match_operand:TF 0 "register_and_not_fp_reg_operand" "") 9602 (neg:TF (match_operand:TF 1 "register_operand" ""))) 9603 (clobber (reg:CC 17))] 9604 "TARGET_80387 && reload_completed" 9605 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) 9606 (clobber (reg:CC 17))])] 9607 "operands[1] = GEN_INT (0x8000); 9608 operands[0] = gen_rtx_REG (SImode, 9609 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") 9610 9611;; Conditionize these after reload. If they matches before reload, we 9612;; lose the clobber and ability to use integer instructions. 9613 9614(define_insn "*negsf2_1" 9615 [(set (match_operand:SF 0 "register_operand" "=f") 9616 (neg:SF (match_operand:SF 1 "register_operand" "0")))] 9617 "TARGET_80387 && reload_completed" 9618 "fchs" 9619 [(set_attr "type" "fsgn") 9620 (set_attr "mode" "SF") 9621 (set_attr "ppro_uops" "few")]) 9622 9623(define_insn "*negdf2_1" 9624 [(set (match_operand:DF 0 "register_operand" "=f") 9625 (neg:DF (match_operand:DF 1 "register_operand" "0")))] 9626 "TARGET_80387 && reload_completed" 9627 "fchs" 9628 [(set_attr "type" "fsgn") 9629 (set_attr "mode" "DF") 9630 (set_attr "ppro_uops" "few")]) 9631 9632(define_insn "*negextendsfdf2" 9633 [(set (match_operand:DF 0 "register_operand" "=f") 9634 (neg:DF (float_extend:DF 9635 (match_operand:SF 1 "register_operand" "0"))))] 9636 "TARGET_80387" 9637 "fchs" 9638 [(set_attr "type" "fsgn") 9639 (set_attr "mode" "DF") 9640 (set_attr "ppro_uops" "few")]) 9641 9642(define_insn "*negxf2_1" 9643 [(set (match_operand:XF 0 "register_operand" "=f") 9644 (neg:XF (match_operand:XF 1 "register_operand" "0")))] 9645 "!TARGET_64BIT && TARGET_80387 && reload_completed" 9646 "fchs" 9647 [(set_attr "type" "fsgn") 9648 (set_attr "mode" "XF") 9649 (set_attr "ppro_uops" "few")]) 9650 9651(define_insn "*negextenddfxf2" 9652 [(set (match_operand:XF 0 "register_operand" "=f") 9653 (neg:XF (float_extend:XF 9654 (match_operand:DF 1 "register_operand" "0"))))] 9655 "!TARGET_64BIT && TARGET_80387" 9656 "fchs" 9657 [(set_attr "type" "fsgn") 9658 (set_attr "mode" "XF") 9659 (set_attr "ppro_uops" "few")]) 9660 9661(define_insn "*negextendsfxf2" 9662 [(set (match_operand:XF 0 "register_operand" "=f") 9663 (neg:XF (float_extend:XF 9664 (match_operand:SF 1 "register_operand" "0"))))] 9665 "!TARGET_64BIT && TARGET_80387" 9666 "fchs" 9667 [(set_attr "type" "fsgn") 9668 (set_attr "mode" "XF") 9669 (set_attr "ppro_uops" "few")]) 9670 9671(define_insn "*negtf2_1" 9672 [(set (match_operand:TF 0 "register_operand" "=f") 9673 (neg:TF (match_operand:TF 1 "register_operand" "0")))] 9674 "TARGET_80387 && reload_completed" 9675 "fchs" 9676 [(set_attr "type" "fsgn") 9677 (set_attr "mode" "XF") 9678 (set_attr "ppro_uops" "few")]) 9679 9680(define_insn "*negextenddftf2" 9681 [(set (match_operand:TF 0 "register_operand" "=f") 9682 (neg:TF (float_extend:TF 9683 (match_operand:DF 1 "register_operand" "0"))))] 9684 "TARGET_80387" 9685 "fchs" 9686 [(set_attr "type" "fsgn") 9687 (set_attr "mode" "XF") 9688 (set_attr "ppro_uops" "few")]) 9689 9690(define_insn "*negextendsftf2" 9691 [(set (match_operand:TF 0 "register_operand" "=f") 9692 (neg:TF (float_extend:TF 9693 (match_operand:SF 1 "register_operand" "0"))))] 9694 "TARGET_80387" 9695 "fchs" 9696 [(set_attr "type" "fsgn") 9697 (set_attr "mode" "XF") 9698 (set_attr "ppro_uops" "few")]) 9699 9700;; Absolute value instructions 9701 9702(define_expand "abssf2" 9703 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") 9704 (neg:SF (match_operand:SF 1 "nonimmediate_operand" ""))) 9705 (clobber (reg:CC 17))])] 9706 "TARGET_80387" 9707 "if (TARGET_SSE) 9708 { 9709 /* In case operand is in memory, we will not use SSE. */ 9710 if (memory_operand (operands[0], VOIDmode) 9711 && rtx_equal_p (operands[0], operands[1])) 9712 emit_insn (gen_abssf2_memory (operands[0], operands[1])); 9713 else 9714 { 9715 /* Using SSE is tricky, since we need bitwise negation of -0 9716 in register. */ 9717 rtx reg = gen_reg_rtx (SFmode); 9718 rtx dest = operands[0]; 9719 9720 operands[1] = force_reg (SFmode, operands[1]); 9721 operands[0] = force_reg (SFmode, operands[0]); 9722 emit_move_insn (reg, 9723 gen_lowpart (SFmode, 9724 gen_int_mode (0x80000000, SImode))); 9725 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg)); 9726 if (dest != operands[0]) 9727 emit_move_insn (dest, operands[0]); 9728 } 9729 DONE; 9730 } 9731 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;") 9732 9733(define_insn "abssf2_memory" 9734 [(set (match_operand:SF 0 "memory_operand" "=m") 9735 (abs:SF (match_operand:SF 1 "memory_operand" "0"))) 9736 (clobber (reg:CC 17))] 9737 "ix86_unary_operator_ok (ABS, SFmode, operands)" 9738 "#") 9739 9740(define_insn "abssf2_ifs" 9741 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,rm#xf") 9742 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0"))) 9743 (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*g#x,*g#x")) 9744 (clobber (reg:CC 17))] 9745 "TARGET_SSE 9746 && (reload_in_progress || reload_completed 9747 || (register_operand (operands[0], VOIDmode) 9748 && register_operand (operands[1], VOIDmode)))" 9749 "#") 9750 9751(define_split 9752 [(set (match_operand:SF 0 "memory_operand" "") 9753 (abs:SF (match_operand:SF 1 "memory_operand" ""))) 9754 (use (match_operand:SF 2 "" "")) 9755 (clobber (reg:CC 17))] 9756 "" 9757 [(parallel [(set (match_dup 0) 9758 (abs:SF (match_dup 1))) 9759 (clobber (reg:CC 17))])]) 9760 9761(define_split 9762 [(set (match_operand:SF 0 "register_operand" "") 9763 (abs:SF (match_operand:SF 1 "register_operand" ""))) 9764 (use (match_operand:SF 2 "" "")) 9765 (clobber (reg:CC 17))] 9766 "reload_completed && !SSE_REG_P (operands[0])" 9767 [(parallel [(set (match_dup 0) 9768 (abs:SF (match_dup 1))) 9769 (clobber (reg:CC 17))])]) 9770 9771(define_split 9772 [(set (match_operand:SF 0 "register_operand" "") 9773 (abs:SF (match_operand:SF 1 "register_operand" ""))) 9774 (use (match_operand:SF 2 "register_operand" "")) 9775 (clobber (reg:CC 17))] 9776 "reload_completed && SSE_REG_P (operands[0])" 9777 [(set (subreg:TI (match_dup 0) 0) 9778 (and:TI (not:TI (subreg:TI (match_dup 2) 0)) 9779 (subreg:TI (match_dup 1) 0)))]) 9780 9781;; Keep 'f' and 'r' in separate alternatives to avoid reload problems 9782;; because of secondary memory needed to reload from class FLOAT_INT_REGS 9783;; to itself. 9784(define_insn "*abssf2_if" 9785 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f") 9786 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0"))) 9787 (clobber (reg:CC 17))] 9788 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE" 9789 "#") 9790 9791(define_split 9792 [(set (match_operand:SF 0 "fp_register_operand" "") 9793 (abs:SF (match_operand:SF 1 "register_operand" ""))) 9794 (clobber (reg:CC 17))] 9795 "TARGET_80387" 9796 [(set (match_dup 0) 9797 (abs:SF (match_dup 1)))] 9798 "") 9799 9800(define_split 9801 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "") 9802 (abs:SF (match_operand:SF 1 "register_operand" ""))) 9803 (clobber (reg:CC 17))] 9804 "TARGET_80387 && reload_completed" 9805 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1))) 9806 (clobber (reg:CC 17))])] 9807 "operands[1] = gen_int_mode (~0x80000000, SImode); 9808 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));") 9809 9810(define_split 9811 [(set (match_operand 0 "memory_operand" "") 9812 (abs (match_operand 1 "memory_operand" ""))) 9813 (clobber (reg:CC 17))] 9814 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))" 9815 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) 9816 (clobber (reg:CC 17))])] 9817{ 9818 int size = GET_MODE_SIZE (GET_MODE (operands[1])); 9819 9820 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */ 9821 if (size >= 12) 9822 size = 10; 9823 operands[0] = adjust_address (operands[0], QImode, size - 1); 9824 operands[1] = gen_int_mode (~0x80, QImode); 9825}) 9826 9827(define_expand "absdf2" 9828 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") 9829 (neg:DF (match_operand:DF 1 "nonimmediate_operand" ""))) 9830 (clobber (reg:CC 17))])] 9831 "TARGET_80387" 9832 "if (TARGET_SSE2) 9833 { 9834 /* In case operand is in memory, we will not use SSE. */ 9835 if (memory_operand (operands[0], VOIDmode) 9836 && rtx_equal_p (operands[0], operands[1])) 9837 emit_insn (gen_absdf2_memory (operands[0], operands[1])); 9838 else 9839 { 9840 /* Using SSE is tricky, since we need bitwise negation of -0 9841 in register. */ 9842 rtx reg = gen_reg_rtx (DFmode); 9843#if HOST_BITS_PER_WIDE_INT >= 64 9844 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode); 9845#else 9846 rtx imm = immed_double_const (0, 0x80000000, DImode); 9847#endif 9848 rtx dest = operands[0]; 9849 9850 operands[1] = force_reg (DFmode, operands[1]); 9851 operands[0] = force_reg (DFmode, operands[0]); 9852 emit_move_insn (reg, gen_lowpart (DFmode, imm)); 9853 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg)); 9854 if (dest != operands[0]) 9855 emit_move_insn (dest, operands[0]); 9856 } 9857 DONE; 9858 } 9859 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;") 9860 9861(define_insn "absdf2_memory" 9862 [(set (match_operand:DF 0 "memory_operand" "=m") 9863 (abs:DF (match_operand:DF 1 "memory_operand" "0"))) 9864 (clobber (reg:CC 17))] 9865 "ix86_unary_operator_ok (ABS, DFmode, operands)" 9866 "#") 9867 9868(define_insn "absdf2_ifs" 9869 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr,mr#Yf") 9870 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0"))) 9871 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y,*g#Y")) 9872 (clobber (reg:CC 17))] 9873 "!TARGET_64BIT && TARGET_SSE2 9874 && (reload_in_progress || reload_completed 9875 || (register_operand (operands[0], VOIDmode) 9876 && register_operand (operands[1], VOIDmode)))" 9877 "#") 9878 9879(define_insn "*absdf2_ifs_rex64" 9880 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr") 9881 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0"))) 9882 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y")) 9883 (clobber (reg:CC 17))] 9884 "TARGET_64BIT && TARGET_SSE2 9885 && (reload_in_progress || reload_completed 9886 || (register_operand (operands[0], VOIDmode) 9887 && register_operand (operands[1], VOIDmode)))" 9888 "#") 9889 9890(define_split 9891 [(set (match_operand:DF 0 "memory_operand" "") 9892 (abs:DF (match_operand:DF 1 "memory_operand" ""))) 9893 (use (match_operand:DF 2 "" "")) 9894 (clobber (reg:CC 17))] 9895 "" 9896 [(parallel [(set (match_dup 0) 9897 (abs:DF (match_dup 1))) 9898 (clobber (reg:CC 17))])]) 9899 9900(define_split 9901 [(set (match_operand:DF 0 "register_operand" "") 9902 (abs:DF (match_operand:DF 1 "register_operand" ""))) 9903 (use (match_operand:DF 2 "" "")) 9904 (clobber (reg:CC 17))] 9905 "reload_completed && !SSE_REG_P (operands[0])" 9906 [(parallel [(set (match_dup 0) 9907 (abs:DF (match_dup 1))) 9908 (clobber (reg:CC 17))])]) 9909 9910(define_split 9911 [(set (match_operand:DF 0 "register_operand" "") 9912 (abs:DF (match_operand:DF 1 "register_operand" ""))) 9913 (use (match_operand:DF 2 "register_operand" "")) 9914 (clobber (reg:CC 17))] 9915 "reload_completed && SSE_REG_P (operands[0])" 9916 [(set (subreg:TI (match_dup 0) 0) 9917 (and:TI (not:TI (subreg:TI (match_dup 2) 0)) 9918 (subreg:TI (match_dup 1) 0)))]) 9919 9920 9921;; Keep 'f' and 'r' in separate alternatives to avoid reload problems 9922;; because of secondary memory needed to reload from class FLOAT_INT_REGS 9923;; to itself. 9924(define_insn "*absdf2_if" 9925 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f") 9926 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) 9927 (clobber (reg:CC 17))] 9928 "!TARGET_64BIT && TARGET_80387 9929 && ix86_unary_operator_ok (ABS, DFmode, operands)" 9930 "#") 9931 9932;; FIXME: We should to allow integer registers here. Problem is that 9933;; we need another scratch register to get constant from. 9934;; Forcing constant to mem if no register available in peep2 should be 9935;; safe even for PIC mode, because of RIP relative addressing. 9936(define_insn "*absdf2_if_rex64" 9937 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf") 9938 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) 9939 (clobber (reg:CC 17))] 9940 "TARGET_64BIT && TARGET_80387 9941 && ix86_unary_operator_ok (ABS, DFmode, operands)" 9942 "#") 9943 9944(define_split 9945 [(set (match_operand:DF 0 "fp_register_operand" "") 9946 (abs:DF (match_operand:DF 1 "register_operand" ""))) 9947 (clobber (reg:CC 17))] 9948 "TARGET_80387 && reload_completed" 9949 [(set (match_dup 0) 9950 (abs:DF (match_dup 1)))] 9951 "") 9952 9953(define_split 9954 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "") 9955 (abs:DF (match_operand:DF 1 "register_operand" ""))) 9956 (clobber (reg:CC 17))] 9957 "!TARGET_64BIT && TARGET_80387 && reload_completed" 9958 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4))) 9959 (clobber (reg:CC 17))])] 9960 "operands[4] = gen_int_mode (~0x80000000, SImode); 9961 split_di (operands+0, 1, operands+2, operands+3);") 9962 9963(define_expand "absxf2" 9964 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "") 9965 (neg:XF (match_operand:XF 1 "nonimmediate_operand" ""))) 9966 (clobber (reg:CC 17))])] 9967 "!TARGET_64BIT && TARGET_80387" 9968 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;") 9969 9970(define_expand "abstf2" 9971 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") 9972 (neg:TF (match_operand:TF 1 "nonimmediate_operand" ""))) 9973 (clobber (reg:CC 17))])] 9974 "TARGET_80387" 9975 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;") 9976 9977;; Keep 'f' and 'r' in separate alternatives to avoid reload problems 9978;; because of secondary memory needed to reload from class FLOAT_INT_REGS 9979;; to itself. 9980(define_insn "*absxf2_if" 9981 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f") 9982 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0"))) 9983 (clobber (reg:CC 17))] 9984 "!TARGET_64BIT && TARGET_80387 9985 && ix86_unary_operator_ok (ABS, XFmode, operands)" 9986 "#") 9987 9988(define_split 9989 [(set (match_operand:XF 0 "fp_register_operand" "") 9990 (abs:XF (match_operand:XF 1 "register_operand" ""))) 9991 (clobber (reg:CC 17))] 9992 "TARGET_80387 && reload_completed" 9993 [(set (match_dup 0) 9994 (abs:XF (match_dup 1)))] 9995 "") 9996 9997(define_split 9998 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "") 9999 (abs:XF (match_operand:XF 1 "register_operand" ""))) 10000 (clobber (reg:CC 17))] 10001 "TARGET_80387 && reload_completed" 10002 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1))) 10003 (clobber (reg:CC 17))])] 10004 "operands[1] = GEN_INT (~0x8000); 10005 operands[0] = gen_rtx_REG (SImode, 10006 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") 10007 10008(define_insn "*abstf2_if" 10009 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f") 10010 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0"))) 10011 (clobber (reg:CC 17))] 10012 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)" 10013 "#") 10014 10015(define_split 10016 [(set (match_operand:TF 0 "fp_register_operand" "") 10017 (abs:TF (match_operand:TF 1 "register_operand" ""))) 10018 (clobber (reg:CC 17))] 10019 "TARGET_80387 && reload_completed" 10020 [(set (match_dup 0) 10021 (abs:TF (match_dup 1)))] 10022 "") 10023 10024(define_split 10025 [(set (match_operand:TF 0 "register_and_not_any_fp_reg_operand" "") 10026 (abs:TF (match_operand:TF 1 "register_operand" ""))) 10027 (clobber (reg:CC 17))] 10028 "TARGET_80387 && reload_completed" 10029 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1))) 10030 (clobber (reg:CC 17))])] 10031 "operands[1] = GEN_INT (~0x8000); 10032 operands[0] = gen_rtx_REG (SImode, 10033 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") 10034 10035(define_insn "*abssf2_1" 10036 [(set (match_operand:SF 0 "register_operand" "=f") 10037 (abs:SF (match_operand:SF 1 "register_operand" "0")))] 10038 "TARGET_80387 && reload_completed" 10039 "fabs" 10040 [(set_attr "type" "fsgn") 10041 (set_attr "mode" "SF")]) 10042 10043(define_insn "*absdf2_1" 10044 [(set (match_operand:DF 0 "register_operand" "=f") 10045 (abs:DF (match_operand:DF 1 "register_operand" "0")))] 10046 "TARGET_80387 && reload_completed" 10047 "fabs" 10048 [(set_attr "type" "fsgn") 10049 (set_attr "mode" "DF")]) 10050 10051(define_insn "*absextendsfdf2" 10052 [(set (match_operand:DF 0 "register_operand" "=f") 10053 (abs:DF (float_extend:DF 10054 (match_operand:SF 1 "register_operand" "0"))))] 10055 "TARGET_80387" 10056 "fabs" 10057 [(set_attr "type" "fsgn") 10058 (set_attr "mode" "DF")]) 10059 10060(define_insn "*absxf2_1" 10061 [(set (match_operand:XF 0 "register_operand" "=f") 10062 (abs:XF (match_operand:XF 1 "register_operand" "0")))] 10063 "!TARGET_64BIT && TARGET_80387 && reload_completed" 10064 "fabs" 10065 [(set_attr "type" "fsgn") 10066 (set_attr "mode" "DF")]) 10067 10068(define_insn "*absextenddfxf2" 10069 [(set (match_operand:XF 0 "register_operand" "=f") 10070 (abs:XF (float_extend:XF 10071 (match_operand:DF 1 "register_operand" "0"))))] 10072 "!TARGET_64BIT && TARGET_80387" 10073 "fabs" 10074 [(set_attr "type" "fsgn") 10075 (set_attr "mode" "XF")]) 10076 10077(define_insn "*absextendsfxf2" 10078 [(set (match_operand:XF 0 "register_operand" "=f") 10079 (abs:XF (float_extend:XF 10080 (match_operand:SF 1 "register_operand" "0"))))] 10081 "!TARGET_64BIT && TARGET_80387" 10082 "fabs" 10083 [(set_attr "type" "fsgn") 10084 (set_attr "mode" "XF")]) 10085 10086(define_insn "*abstf2_1" 10087 [(set (match_operand:TF 0 "register_operand" "=f") 10088 (abs:TF (match_operand:TF 1 "register_operand" "0")))] 10089 "TARGET_80387 && reload_completed" 10090 "fabs" 10091 [(set_attr "type" "fsgn") 10092 (set_attr "mode" "DF")]) 10093 10094(define_insn "*absextenddftf2" 10095 [(set (match_operand:TF 0 "register_operand" "=f") 10096 (abs:TF (float_extend:TF 10097 (match_operand:DF 1 "register_operand" "0"))))] 10098 "TARGET_80387" 10099 "fabs" 10100 [(set_attr "type" "fsgn") 10101 (set_attr "mode" "XF")]) 10102 10103(define_insn "*absextendsftf2" 10104 [(set (match_operand:TF 0 "register_operand" "=f") 10105 (abs:TF (float_extend:TF 10106 (match_operand:SF 1 "register_operand" "0"))))] 10107 "TARGET_80387" 10108 "fabs" 10109 [(set_attr "type" "fsgn") 10110 (set_attr "mode" "XF")]) 10111 10112;; One complement instructions 10113 10114(define_expand "one_cmpldi2" 10115 [(set (match_operand:DI 0 "nonimmediate_operand" "") 10116 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))] 10117 "TARGET_64BIT" 10118 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;") 10119 10120(define_insn "*one_cmpldi2_1_rex64" 10121 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") 10122 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))] 10123 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)" 10124 "not{q}\t%0" 10125 [(set_attr "type" "negnot") 10126 (set_attr "mode" "DI")]) 10127 10128(define_insn "*one_cmpldi2_2_rex64" 10129 [(set (reg 17) 10130 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")) 10131 (const_int 0))) 10132 (set (match_operand:DI 0 "nonimmediate_operand" "=rm") 10133 (not:DI (match_dup 1)))] 10134 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) 10135 && ix86_unary_operator_ok (NOT, DImode, operands)" 10136 "#" 10137 [(set_attr "type" "alu1") 10138 (set_attr "mode" "DI")]) 10139 10140(define_split 10141 [(set (reg 17) 10142 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "")) 10143 (const_int 0))) 10144 (set (match_operand:DI 0 "nonimmediate_operand" "") 10145 (not:DI (match_dup 1)))] 10146 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" 10147 [(parallel [(set (reg:CCNO 17) 10148 (compare:CCNO (xor:DI (match_dup 1) (const_int -1)) 10149 (const_int 0))) 10150 (set (match_dup 0) 10151 (xor:DI (match_dup 1) (const_int -1)))])] 10152 "") 10153 10154(define_expand "one_cmplsi2" 10155 [(set (match_operand:SI 0 "nonimmediate_operand" "") 10156 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))] 10157 "" 10158 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;") 10159 10160(define_insn "*one_cmplsi2_1" 10161 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 10162 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))] 10163 "ix86_unary_operator_ok (NOT, SImode, operands)" 10164 "not{l}\t%0" 10165 [(set_attr "type" "negnot") 10166 (set_attr "mode" "SI")]) 10167 10168;; ??? Currently never generated - xor is used instead. 10169(define_insn "*one_cmplsi2_1_zext" 10170 [(set (match_operand:DI 0 "register_operand" "=r") 10171 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))] 10172 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)" 10173 "not{l}\t%k0" 10174 [(set_attr "type" "negnot") 10175 (set_attr "mode" "SI")]) 10176 10177(define_insn "*one_cmplsi2_2" 10178 [(set (reg 17) 10179 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")) 10180 (const_int 0))) 10181 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 10182 (not:SI (match_dup 1)))] 10183 "ix86_match_ccmode (insn, CCNOmode) 10184 && ix86_unary_operator_ok (NOT, SImode, operands)" 10185 "#" 10186 [(set_attr "type" "alu1") 10187 (set_attr "mode" "SI")]) 10188 10189(define_split 10190 [(set (reg 17) 10191 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "")) 10192 (const_int 0))) 10193 (set (match_operand:SI 0 "nonimmediate_operand" "") 10194 (not:SI (match_dup 1)))] 10195 "ix86_match_ccmode (insn, CCNOmode)" 10196 [(parallel [(set (reg:CCNO 17) 10197 (compare:CCNO (xor:SI (match_dup 1) (const_int -1)) 10198 (const_int 0))) 10199 (set (match_dup 0) 10200 (xor:SI (match_dup 1) (const_int -1)))])] 10201 "") 10202 10203;; ??? Currently never generated - xor is used instead. 10204(define_insn "*one_cmplsi2_2_zext" 10205 [(set (reg 17) 10206 (compare (not:SI (match_operand:SI 1 "register_operand" "0")) 10207 (const_int 0))) 10208 (set (match_operand:DI 0 "register_operand" "=r") 10209 (zero_extend:DI (not:SI (match_dup 1))))] 10210 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) 10211 && ix86_unary_operator_ok (NOT, SImode, operands)" 10212 "#" 10213 [(set_attr "type" "alu1") 10214 (set_attr "mode" "SI")]) 10215 10216(define_split 10217 [(set (reg 17) 10218 (compare (not:SI (match_operand:SI 1 "register_operand" "")) 10219 (const_int 0))) 10220 (set (match_operand:DI 0 "register_operand" "") 10221 (zero_extend:DI (not:SI (match_dup 1))))] 10222 "ix86_match_ccmode (insn, CCNOmode)" 10223 [(parallel [(set (reg:CCNO 17) 10224 (compare:CCNO (xor:SI (match_dup 1) (const_int -1)) 10225 (const_int 0))) 10226 (set (match_dup 0) 10227 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])] 10228 "") 10229 10230(define_expand "one_cmplhi2" 10231 [(set (match_operand:HI 0 "nonimmediate_operand" "") 10232 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))] 10233 "TARGET_HIMODE_MATH" 10234 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;") 10235 10236(define_insn "*one_cmplhi2_1" 10237 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 10238 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))] 10239 "ix86_unary_operator_ok (NOT, HImode, operands)" 10240 "not{w}\t%0" 10241 [(set_attr "type" "negnot") 10242 (set_attr "mode" "HI")]) 10243 10244(define_insn "*one_cmplhi2_2" 10245 [(set (reg 17) 10246 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")) 10247 (const_int 0))) 10248 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 10249 (not:HI (match_dup 1)))] 10250 "ix86_match_ccmode (insn, CCNOmode) 10251 && ix86_unary_operator_ok (NEG, HImode, operands)" 10252 "#" 10253 [(set_attr "type" "alu1") 10254 (set_attr "mode" "HI")]) 10255 10256(define_split 10257 [(set (reg 17) 10258 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "")) 10259 (const_int 0))) 10260 (set (match_operand:HI 0 "nonimmediate_operand" "") 10261 (not:HI (match_dup 1)))] 10262 "ix86_match_ccmode (insn, CCNOmode)" 10263 [(parallel [(set (reg:CCNO 17) 10264 (compare:CCNO (xor:HI (match_dup 1) (const_int -1)) 10265 (const_int 0))) 10266 (set (match_dup 0) 10267 (xor:HI (match_dup 1) (const_int -1)))])] 10268 "") 10269 10270;; %%% Potential partial reg stall on alternative 1. What to do? 10271(define_expand "one_cmplqi2" 10272 [(set (match_operand:QI 0 "nonimmediate_operand" "") 10273 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))] 10274 "TARGET_QIMODE_MATH" 10275 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;") 10276 10277(define_insn "*one_cmplqi2_1" 10278 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r") 10279 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))] 10280 "ix86_unary_operator_ok (NOT, QImode, operands)" 10281 "@ 10282 not{b}\t%0 10283 not{l}\t%k0" 10284 [(set_attr "type" "negnot") 10285 (set_attr "mode" "QI,SI")]) 10286 10287(define_insn "*one_cmplqi2_2" 10288 [(set (reg 17) 10289 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")) 10290 (const_int 0))) 10291 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") 10292 (not:QI (match_dup 1)))] 10293 "ix86_match_ccmode (insn, CCNOmode) 10294 && ix86_unary_operator_ok (NOT, QImode, operands)" 10295 "#" 10296 [(set_attr "type" "alu1") 10297 (set_attr "mode" "QI")]) 10298 10299(define_split 10300 [(set (reg 17) 10301 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "")) 10302 (const_int 0))) 10303 (set (match_operand:QI 0 "nonimmediate_operand" "") 10304 (not:QI (match_dup 1)))] 10305 "ix86_match_ccmode (insn, CCNOmode)" 10306 [(parallel [(set (reg:CCNO 17) 10307 (compare:CCNO (xor:QI (match_dup 1) (const_int -1)) 10308 (const_int 0))) 10309 (set (match_dup 0) 10310 (xor:QI (match_dup 1) (const_int -1)))])] 10311 "") 10312 10313;; Arithmetic shift instructions 10314 10315;; DImode shifts are implemented using the i386 "shift double" opcode, 10316;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count 10317;; is variable, then the count is in %cl and the "imm" operand is dropped 10318;; from the assembler input. 10319;; 10320;; This instruction shifts the target reg/mem as usual, but instead of 10321;; shifting in zeros, bits are shifted in from reg operand. If the insn 10322;; is a left shift double, bits are taken from the high order bits of 10323;; reg, else if the insn is a shift right double, bits are taken from the 10324;; low order bits of reg. So if %eax is "1234" and %edx is "5678", 10325;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345". 10326;; 10327;; Since sh[lr]d does not change the `reg' operand, that is done 10328;; separately, making all shifts emit pairs of shift double and normal 10329;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to 10330;; support a 63 bit shift, each shift where the count is in a reg expands 10331;; to a pair of shifts, a branch, a shift by 32 and a label. 10332;; 10333;; If the shift count is a constant, we need never emit more than one 10334;; shift pair, instead using moves and sign extension for counts greater 10335;; than 31. 10336 10337(define_expand "ashldi3" 10338 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "") 10339 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "") 10340 (match_operand:QI 2 "nonmemory_operand" ""))) 10341 (clobber (reg:CC 17))])] 10342 "" 10343{ 10344 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode)) 10345 { 10346 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2])); 10347 DONE; 10348 } 10349 ix86_expand_binary_operator (ASHIFT, DImode, operands); 10350 DONE; 10351}) 10352 10353(define_insn "*ashldi3_1_rex64" 10354 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") 10355 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r") 10356 (match_operand:QI 2 "nonmemory_operand" "cJ,M"))) 10357 (clobber (reg:CC 17))] 10358 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)" 10359{ 10360 switch (get_attr_type (insn)) 10361 { 10362 case TYPE_ALU: 10363 if (operands[2] != const1_rtx) 10364 abort (); 10365 if (!rtx_equal_p (operands[0], operands[1])) 10366 abort (); 10367 return "add{q}\t{%0, %0|%0, %0}"; 10368 10369 case TYPE_LEA: 10370 if (GET_CODE (operands[2]) != CONST_INT 10371 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3) 10372 abort (); 10373 operands[1] = gen_rtx_MULT (DImode, operands[1], 10374 GEN_INT (1 << INTVAL (operands[2]))); 10375 return "lea{q}\t{%a1, %0|%0, %a1}"; 10376 10377 default: 10378 if (REG_P (operands[2])) 10379 return "sal{q}\t{%b2, %0|%0, %b2}"; 10380 else if (GET_CODE (operands[2]) == CONST_INT 10381 && INTVAL (operands[2]) == 1 10382 && (TARGET_SHIFT1 || optimize_size)) 10383 return "sal{q}\t%0"; 10384 else 10385 return "sal{q}\t{%2, %0|%0, %2}"; 10386 } 10387} 10388 [(set (attr "type") 10389 (cond [(eq_attr "alternative" "1") 10390 (const_string "lea") 10391 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") 10392 (const_int 0)) 10393 (match_operand 0 "register_operand" "")) 10394 (match_operand 2 "const1_operand" "")) 10395 (const_string "alu") 10396 ] 10397 (const_string "ishift"))) 10398 (set_attr "mode" "DI")]) 10399 10400;; Convert lea to the lea pattern to avoid flags dependency. 10401(define_split 10402 [(set (match_operand:DI 0 "register_operand" "") 10403 (ashift:DI (match_operand:DI 1 "register_operand" "") 10404 (match_operand:QI 2 "immediate_operand" ""))) 10405 (clobber (reg:CC 17))] 10406 "TARGET_64BIT && reload_completed 10407 && true_regnum (operands[0]) != true_regnum (operands[1])" 10408 [(set (match_dup 0) 10409 (mult:DI (match_dup 1) 10410 (match_dup 2)))] 10411 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);") 10412 10413;; This pattern can't accept a variable shift count, since shifts by 10414;; zero don't affect the flags. We assume that shifts by constant 10415;; zero are optimized away. 10416(define_insn "*ashldi3_cmp_rex64" 10417 [(set (reg 17) 10418 (compare 10419 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0") 10420 (match_operand:QI 2 "immediate_operand" "e")) 10421 (const_int 0))) 10422 (set (match_operand:DI 0 "nonimmediate_operand" "=rm") 10423 (ashift:DI (match_dup 1) (match_dup 2)))] 10424 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 10425 && ix86_binary_operator_ok (ASHIFT, DImode, operands)" 10426{ 10427 switch (get_attr_type (insn)) 10428 { 10429 case TYPE_ALU: 10430 if (operands[2] != const1_rtx) 10431 abort (); 10432 return "add{q}\t{%0, %0|%0, %0}"; 10433 10434 default: 10435 if (REG_P (operands[2])) 10436 return "sal{q}\t{%b2, %0|%0, %b2}"; 10437 else if (GET_CODE (operands[2]) == CONST_INT 10438 && INTVAL (operands[2]) == 1 10439 && (TARGET_SHIFT1 || optimize_size)) 10440 return "sal{q}\t%0"; 10441 else 10442 return "sal{q}\t{%2, %0|%0, %2}"; 10443 } 10444} 10445 [(set (attr "type") 10446 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") 10447 (const_int 0)) 10448 (match_operand 0 "register_operand" "")) 10449 (match_operand 2 "const1_operand" "")) 10450 (const_string "alu") 10451 ] 10452 (const_string "ishift"))) 10453 (set_attr "mode" "DI")]) 10454 10455(define_insn "ashldi3_1" 10456 [(set (match_operand:DI 0 "register_operand" "=r") 10457 (ashift:DI (match_operand:DI 1 "register_operand" "0") 10458 (match_operand:QI 2 "nonmemory_operand" "Jc"))) 10459 (clobber (match_scratch:SI 3 "=&r")) 10460 (clobber (reg:CC 17))] 10461 "!TARGET_64BIT && TARGET_CMOVE" 10462 "#" 10463 [(set_attr "type" "multi")]) 10464 10465(define_insn "*ashldi3_2" 10466 [(set (match_operand:DI 0 "register_operand" "=r") 10467 (ashift:DI (match_operand:DI 1 "register_operand" "0") 10468 (match_operand:QI 2 "nonmemory_operand" "Jc"))) 10469 (clobber (reg:CC 17))] 10470 "!TARGET_64BIT" 10471 "#" 10472 [(set_attr "type" "multi")]) 10473 10474(define_split 10475 [(set (match_operand:DI 0 "register_operand" "") 10476 (ashift:DI (match_operand:DI 1 "register_operand" "") 10477 (match_operand:QI 2 "nonmemory_operand" ""))) 10478 (clobber (match_scratch:SI 3 "")) 10479 (clobber (reg:CC 17))] 10480 "!TARGET_64BIT && TARGET_CMOVE && reload_completed" 10481 [(const_int 0)] 10482 "ix86_split_ashldi (operands, operands[3]); DONE;") 10483 10484(define_split 10485 [(set (match_operand:DI 0 "register_operand" "") 10486 (ashift:DI (match_operand:DI 1 "register_operand" "") 10487 (match_operand:QI 2 "nonmemory_operand" ""))) 10488 (clobber (reg:CC 17))] 10489 "!TARGET_64BIT && reload_completed" 10490 [(const_int 0)] 10491 "ix86_split_ashldi (operands, NULL_RTX); DONE;") 10492 10493(define_insn "x86_shld_1" 10494 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m") 10495 (ior:SI (ashift:SI (match_dup 0) 10496 (match_operand:QI 2 "nonmemory_operand" "I,c")) 10497 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r") 10498 (minus:QI (const_int 32) (match_dup 2))))) 10499 (clobber (reg:CC 17))] 10500 "" 10501 "@ 10502 shld{l}\t{%2, %1, %0|%0, %1, %2} 10503 shld{l}\t{%s2%1, %0|%0, %1, %2}" 10504 [(set_attr "type" "ishift") 10505 (set_attr "prefix_0f" "1") 10506 (set_attr "mode" "SI") 10507 (set_attr "pent_pair" "np") 10508 (set_attr "athlon_decode" "vector") 10509 (set_attr "ppro_uops" "few")]) 10510 10511(define_expand "x86_shift_adj_1" 10512 [(set (reg:CCZ 17) 10513 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "") 10514 (const_int 32)) 10515 (const_int 0))) 10516 (set (match_operand:SI 0 "register_operand" "") 10517 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0)) 10518 (match_operand:SI 1 "register_operand" "") 10519 (match_dup 0))) 10520 (set (match_dup 1) 10521 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0)) 10522 (match_operand:SI 3 "register_operand" "r") 10523 (match_dup 1)))] 10524 "TARGET_CMOVE" 10525 "") 10526 10527(define_expand "x86_shift_adj_2" 10528 [(use (match_operand:SI 0 "register_operand" "")) 10529 (use (match_operand:SI 1 "register_operand" "")) 10530 (use (match_operand:QI 2 "register_operand" ""))] 10531 "" 10532{ 10533 rtx label = gen_label_rtx (); 10534 rtx tmp; 10535 10536 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32))); 10537 10538 tmp = gen_rtx_REG (CCZmode, FLAGS_REG); 10539 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); 10540 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 10541 gen_rtx_LABEL_REF (VOIDmode, label), 10542 pc_rtx); 10543 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); 10544 JUMP_LABEL (tmp) = label; 10545 10546 emit_move_insn (operands[0], operands[1]); 10547 emit_move_insn (operands[1], const0_rtx); 10548 10549 emit_label (label); 10550 LABEL_NUSES (label) = 1; 10551 10552 DONE; 10553}) 10554 10555(define_expand "ashlsi3" 10556 [(set (match_operand:SI 0 "nonimmediate_operand" "") 10557 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "") 10558 (match_operand:QI 2 "nonmemory_operand" ""))) 10559 (clobber (reg:CC 17))] 10560 "" 10561 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;") 10562 10563(define_insn "*ashlsi3_1" 10564 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") 10565 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r") 10566 (match_operand:QI 2 "nonmemory_operand" "cI,M"))) 10567 (clobber (reg:CC 17))] 10568 "ix86_binary_operator_ok (ASHIFT, SImode, operands)" 10569{ 10570 switch (get_attr_type (insn)) 10571 { 10572 case TYPE_ALU: 10573 if (operands[2] != const1_rtx) 10574 abort (); 10575 if (!rtx_equal_p (operands[0], operands[1])) 10576 abort (); 10577 return "add{l}\t{%0, %0|%0, %0}"; 10578 10579 case TYPE_LEA: 10580 return "#"; 10581 10582 default: 10583 if (REG_P (operands[2])) 10584 return "sal{l}\t{%b2, %0|%0, %b2}"; 10585 else if (GET_CODE (operands[2]) == CONST_INT 10586 && INTVAL (operands[2]) == 1 10587 && (TARGET_SHIFT1 || optimize_size)) 10588 return "sal{l}\t%0"; 10589 else 10590 return "sal{l}\t{%2, %0|%0, %2}"; 10591 } 10592} 10593 [(set (attr "type") 10594 (cond [(eq_attr "alternative" "1") 10595 (const_string "lea") 10596 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") 10597 (const_int 0)) 10598 (match_operand 0 "register_operand" "")) 10599 (match_operand 2 "const1_operand" "")) 10600 (const_string "alu") 10601 ] 10602 (const_string "ishift"))) 10603 (set_attr "mode" "SI")]) 10604 10605;; Convert lea to the lea pattern to avoid flags dependency. 10606(define_split 10607 [(set (match_operand 0 "register_operand" "") 10608 (ashift (match_operand 1 "index_register_operand" "") 10609 (match_operand:QI 2 "const_int_operand" ""))) 10610 (clobber (reg:CC 17))] 10611 "reload_completed 10612 && true_regnum (operands[0]) != true_regnum (operands[1])" 10613 [(const_int 0)] 10614{ 10615 rtx pat; 10616 operands[0] = gen_lowpart (SImode, operands[0]); 10617 operands[1] = gen_lowpart (Pmode, operands[1]); 10618 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode); 10619 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]); 10620 if (Pmode != SImode) 10621 pat = gen_rtx_SUBREG (SImode, pat, 0); 10622 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); 10623 DONE; 10624}) 10625 10626;; Rare case of shifting RSP is handled by generating move and shift 10627(define_split 10628 [(set (match_operand 0 "register_operand" "") 10629 (ashift (match_operand 1 "register_operand" "") 10630 (match_operand:QI 2 "const_int_operand" ""))) 10631 (clobber (reg:CC 17))] 10632 "reload_completed 10633 && true_regnum (operands[0]) != true_regnum (operands[1])" 10634 [(const_int 0)] 10635{ 10636 rtx pat, clob; 10637 emit_move_insn (operands[1], operands[0]); 10638 pat = gen_rtx_SET (VOIDmode, operands[0], 10639 gen_rtx_ASHIFT (GET_MODE (operands[0]), 10640 operands[0], operands[2])); 10641 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG)); 10642 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob))); 10643 DONE; 10644}) 10645 10646(define_insn "*ashlsi3_1_zext" 10647 [(set (match_operand:DI 0 "register_operand" "=r,r") 10648 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r") 10649 (match_operand:QI 2 "nonmemory_operand" "cI,M")))) 10650 (clobber (reg:CC 17))] 10651 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)" 10652{ 10653 switch (get_attr_type (insn)) 10654 { 10655 case TYPE_ALU: 10656 if (operands[2] != const1_rtx) 10657 abort (); 10658 return "add{l}\t{%k0, %k0|%k0, %k0}"; 10659 10660 case TYPE_LEA: 10661 return "#"; 10662 10663 default: 10664 if (REG_P (operands[2])) 10665 return "sal{l}\t{%b2, %k0|%k0, %b2}"; 10666 else if (GET_CODE (operands[2]) == CONST_INT 10667 && INTVAL (operands[2]) == 1 10668 && (TARGET_SHIFT1 || optimize_size)) 10669 return "sal{l}\t%k0"; 10670 else 10671 return "sal{l}\t{%2, %k0|%k0, %2}"; 10672 } 10673} 10674 [(set (attr "type") 10675 (cond [(eq_attr "alternative" "1") 10676 (const_string "lea") 10677 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") 10678 (const_int 0)) 10679 (match_operand 2 "const1_operand" "")) 10680 (const_string "alu") 10681 ] 10682 (const_string "ishift"))) 10683 (set_attr "mode" "SI")]) 10684 10685;; Convert lea to the lea pattern to avoid flags dependency. 10686(define_split 10687 [(set (match_operand:DI 0 "register_operand" "") 10688 (zero_extend:DI (ashift (match_operand 1 "register_operand" "") 10689 (match_operand:QI 2 "const_int_operand" "")))) 10690 (clobber (reg:CC 17))] 10691 "reload_completed 10692 && true_regnum (operands[0]) != true_regnum (operands[1])" 10693 [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))] 10694{ 10695 operands[1] = gen_lowpart (Pmode, operands[1]); 10696 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode); 10697}) 10698 10699;; This pattern can't accept a variable shift count, since shifts by 10700;; zero don't affect the flags. We assume that shifts by constant 10701;; zero are optimized away. 10702(define_insn "*ashlsi3_cmp" 10703 [(set (reg 17) 10704 (compare 10705 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0") 10706 (match_operand:QI 2 "const_int_1_31_operand" "I")) 10707 (const_int 0))) 10708 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 10709 (ashift:SI (match_dup 1) (match_dup 2)))] 10710 "ix86_match_ccmode (insn, CCGOCmode) 10711 && ix86_binary_operator_ok (ASHIFT, SImode, operands)" 10712{ 10713 switch (get_attr_type (insn)) 10714 { 10715 case TYPE_ALU: 10716 if (operands[2] != const1_rtx) 10717 abort (); 10718 return "add{l}\t{%0, %0|%0, %0}"; 10719 10720 default: 10721 if (REG_P (operands[2])) 10722 return "sal{l}\t{%b2, %0|%0, %b2}"; 10723 else if (GET_CODE (operands[2]) == CONST_INT 10724 && INTVAL (operands[2]) == 1 10725 && (TARGET_SHIFT1 || optimize_size)) 10726 return "sal{l}\t%0"; 10727 else 10728 return "sal{l}\t{%2, %0|%0, %2}"; 10729 } 10730} 10731 [(set (attr "type") 10732 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") 10733 (const_int 0)) 10734 (match_operand 0 "register_operand" "")) 10735 (match_operand 2 "const1_operand" "")) 10736 (const_string "alu") 10737 ] 10738 (const_string "ishift"))) 10739 (set_attr "mode" "SI")]) 10740 10741(define_insn "*ashlsi3_cmp_zext" 10742 [(set (reg 17) 10743 (compare 10744 (ashift:SI (match_operand:SI 1 "register_operand" "0") 10745 (match_operand:QI 2 "const_int_1_31_operand" "I")) 10746 (const_int 0))) 10747 (set (match_operand:DI 0 "register_operand" "=r") 10748 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))] 10749 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 10750 && ix86_binary_operator_ok (ASHIFT, SImode, operands)" 10751{ 10752 switch (get_attr_type (insn)) 10753 { 10754 case TYPE_ALU: 10755 if (operands[2] != const1_rtx) 10756 abort (); 10757 return "add{l}\t{%k0, %k0|%k0, %k0}"; 10758 10759 default: 10760 if (REG_P (operands[2])) 10761 return "sal{l}\t{%b2, %k0|%k0, %b2}"; 10762 else if (GET_CODE (operands[2]) == CONST_INT 10763 && INTVAL (operands[2]) == 1 10764 && (TARGET_SHIFT1 || optimize_size)) 10765 return "sal{l}\t%k0"; 10766 else 10767 return "sal{l}\t{%2, %k0|%k0, %2}"; 10768 } 10769} 10770 [(set (attr "type") 10771 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") 10772 (const_int 0)) 10773 (match_operand 2 "const1_operand" "")) 10774 (const_string "alu") 10775 ] 10776 (const_string "ishift"))) 10777 (set_attr "mode" "SI")]) 10778 10779(define_expand "ashlhi3" 10780 [(set (match_operand:HI 0 "nonimmediate_operand" "") 10781 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "") 10782 (match_operand:QI 2 "nonmemory_operand" ""))) 10783 (clobber (reg:CC 17))] 10784 "TARGET_HIMODE_MATH" 10785 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;") 10786 10787(define_insn "*ashlhi3_1_lea" 10788 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") 10789 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r") 10790 (match_operand:QI 2 "nonmemory_operand" "cI,M"))) 10791 (clobber (reg:CC 17))] 10792 "!TARGET_PARTIAL_REG_STALL 10793 && ix86_binary_operator_ok (ASHIFT, HImode, operands)" 10794{ 10795 switch (get_attr_type (insn)) 10796 { 10797 case TYPE_LEA: 10798 return "#"; 10799 case TYPE_ALU: 10800 if (operands[2] != const1_rtx) 10801 abort (); 10802 return "add{w}\t{%0, %0|%0, %0}"; 10803 10804 default: 10805 if (REG_P (operands[2])) 10806 return "sal{w}\t{%b2, %0|%0, %b2}"; 10807 else if (GET_CODE (operands[2]) == CONST_INT 10808 && INTVAL (operands[2]) == 1 10809 && (TARGET_SHIFT1 || optimize_size)) 10810 return "sal{w}\t%0"; 10811 else 10812 return "sal{w}\t{%2, %0|%0, %2}"; 10813 } 10814} 10815 [(set (attr "type") 10816 (cond [(eq_attr "alternative" "1") 10817 (const_string "lea") 10818 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") 10819 (const_int 0)) 10820 (match_operand 0 "register_operand" "")) 10821 (match_operand 2 "const1_operand" "")) 10822 (const_string "alu") 10823 ] 10824 (const_string "ishift"))) 10825 (set_attr "mode" "HI,SI")]) 10826 10827(define_insn "*ashlhi3_1" 10828 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 10829 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0") 10830 (match_operand:QI 2 "nonmemory_operand" "cI"))) 10831 (clobber (reg:CC 17))] 10832 "TARGET_PARTIAL_REG_STALL 10833 && ix86_binary_operator_ok (ASHIFT, HImode, operands)" 10834{ 10835 switch (get_attr_type (insn)) 10836 { 10837 case TYPE_ALU: 10838 if (operands[2] != const1_rtx) 10839 abort (); 10840 return "add{w}\t{%0, %0|%0, %0}"; 10841 10842 default: 10843 if (REG_P (operands[2])) 10844 return "sal{w}\t{%b2, %0|%0, %b2}"; 10845 else if (GET_CODE (operands[2]) == CONST_INT 10846 && INTVAL (operands[2]) == 1 10847 && (TARGET_SHIFT1 || optimize_size)) 10848 return "sal{w}\t%0"; 10849 else 10850 return "sal{w}\t{%2, %0|%0, %2}"; 10851 } 10852} 10853 [(set (attr "type") 10854 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") 10855 (const_int 0)) 10856 (match_operand 0 "register_operand" "")) 10857 (match_operand 2 "const1_operand" "")) 10858 (const_string "alu") 10859 ] 10860 (const_string "ishift"))) 10861 (set_attr "mode" "HI")]) 10862 10863;; This pattern can't accept a variable shift count, since shifts by 10864;; zero don't affect the flags. We assume that shifts by constant 10865;; zero are optimized away. 10866(define_insn "*ashlhi3_cmp" 10867 [(set (reg 17) 10868 (compare 10869 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0") 10870 (match_operand:QI 2 "const_int_1_31_operand" "I")) 10871 (const_int 0))) 10872 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 10873 (ashift:HI (match_dup 1) (match_dup 2)))] 10874 "ix86_match_ccmode (insn, CCGOCmode) 10875 && ix86_binary_operator_ok (ASHIFT, HImode, operands)" 10876{ 10877 switch (get_attr_type (insn)) 10878 { 10879 case TYPE_ALU: 10880 if (operands[2] != const1_rtx) 10881 abort (); 10882 return "add{w}\t{%0, %0|%0, %0}"; 10883 10884 default: 10885 if (REG_P (operands[2])) 10886 return "sal{w}\t{%b2, %0|%0, %b2}"; 10887 else if (GET_CODE (operands[2]) == CONST_INT 10888 && INTVAL (operands[2]) == 1 10889 && (TARGET_SHIFT1 || optimize_size)) 10890 return "sal{w}\t%0"; 10891 else 10892 return "sal{w}\t{%2, %0|%0, %2}"; 10893 } 10894} 10895 [(set (attr "type") 10896 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") 10897 (const_int 0)) 10898 (match_operand 0 "register_operand" "")) 10899 (match_operand 2 "const1_operand" "")) 10900 (const_string "alu") 10901 ] 10902 (const_string "ishift"))) 10903 (set_attr "mode" "HI")]) 10904 10905(define_expand "ashlqi3" 10906 [(set (match_operand:QI 0 "nonimmediate_operand" "") 10907 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "") 10908 (match_operand:QI 2 "nonmemory_operand" ""))) 10909 (clobber (reg:CC 17))] 10910 "TARGET_QIMODE_MATH" 10911 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;") 10912 10913;; %%% Potential partial reg stall on alternative 2. What to do? 10914 10915(define_insn "*ashlqi3_1_lea" 10916 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r") 10917 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r") 10918 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M"))) 10919 (clobber (reg:CC 17))] 10920 "!TARGET_PARTIAL_REG_STALL 10921 && ix86_binary_operator_ok (ASHIFT, QImode, operands)" 10922{ 10923 switch (get_attr_type (insn)) 10924 { 10925 case TYPE_LEA: 10926 return "#"; 10927 case TYPE_ALU: 10928 if (operands[2] != const1_rtx) 10929 abort (); 10930 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1])) 10931 return "add{l}\t{%k0, %k0|%k0, %k0}"; 10932 else 10933 return "add{b}\t{%0, %0|%0, %0}"; 10934 10935 default: 10936 if (REG_P (operands[2])) 10937 { 10938 if (get_attr_mode (insn) == MODE_SI) 10939 return "sal{l}\t{%b2, %k0|%k0, %b2}"; 10940 else 10941 return "sal{b}\t{%b2, %0|%0, %b2}"; 10942 } 10943 else if (GET_CODE (operands[2]) == CONST_INT 10944 && INTVAL (operands[2]) == 1 10945 && (TARGET_SHIFT1 || optimize_size)) 10946 { 10947 if (get_attr_mode (insn) == MODE_SI) 10948 return "sal{l}\t%0"; 10949 else 10950 return "sal{b}\t%0"; 10951 } 10952 else 10953 { 10954 if (get_attr_mode (insn) == MODE_SI) 10955 return "sal{l}\t{%2, %k0|%k0, %2}"; 10956 else 10957 return "sal{b}\t{%2, %0|%0, %2}"; 10958 } 10959 } 10960} 10961 [(set (attr "type") 10962 (cond [(eq_attr "alternative" "2") 10963 (const_string "lea") 10964 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") 10965 (const_int 0)) 10966 (match_operand 0 "register_operand" "")) 10967 (match_operand 2 "const1_operand" "")) 10968 (const_string "alu") 10969 ] 10970 (const_string "ishift"))) 10971 (set_attr "mode" "QI,SI,SI")]) 10972 10973(define_insn "*ashlqi3_1" 10974 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r") 10975 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") 10976 (match_operand:QI 2 "nonmemory_operand" "cI,cI"))) 10977 (clobber (reg:CC 17))] 10978 "TARGET_PARTIAL_REG_STALL 10979 && ix86_binary_operator_ok (ASHIFT, QImode, operands)" 10980{ 10981 switch (get_attr_type (insn)) 10982 { 10983 case TYPE_ALU: 10984 if (operands[2] != const1_rtx) 10985 abort (); 10986 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1])) 10987 return "add{l}\t{%k0, %k0|%k0, %k0}"; 10988 else 10989 return "add{b}\t{%0, %0|%0, %0}"; 10990 10991 default: 10992 if (REG_P (operands[2])) 10993 { 10994 if (get_attr_mode (insn) == MODE_SI) 10995 return "sal{l}\t{%b2, %k0|%k0, %b2}"; 10996 else 10997 return "sal{b}\t{%b2, %0|%0, %b2}"; 10998 } 10999 else if (GET_CODE (operands[2]) == CONST_INT 11000 && INTVAL (operands[2]) == 1 11001 && (TARGET_SHIFT1 || optimize_size)) 11002 { 11003 if (get_attr_mode (insn) == MODE_SI) 11004 return "sal{l}\t%0"; 11005 else 11006 return "sal{b}\t%0"; 11007 } 11008 else 11009 { 11010 if (get_attr_mode (insn) == MODE_SI) 11011 return "sal{l}\t{%2, %k0|%k0, %2}"; 11012 else 11013 return "sal{b}\t{%2, %0|%0, %2}"; 11014 } 11015 } 11016} 11017 [(set (attr "type") 11018 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") 11019 (const_int 0)) 11020 (match_operand 0 "register_operand" "")) 11021 (match_operand 2 "const1_operand" "")) 11022 (const_string "alu") 11023 ] 11024 (const_string "ishift"))) 11025 (set_attr "mode" "QI,SI")]) 11026 11027;; This pattern can't accept a variable shift count, since shifts by 11028;; zero don't affect the flags. We assume that shifts by constant 11029;; zero are optimized away. 11030(define_insn "*ashlqi3_cmp" 11031 [(set (reg 17) 11032 (compare 11033 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0") 11034 (match_operand:QI 2 "const_int_1_31_operand" "I")) 11035 (const_int 0))) 11036 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") 11037 (ashift:QI (match_dup 1) (match_dup 2)))] 11038 "ix86_match_ccmode (insn, CCGOCmode) 11039 && ix86_binary_operator_ok (ASHIFT, QImode, operands)" 11040{ 11041 switch (get_attr_type (insn)) 11042 { 11043 case TYPE_ALU: 11044 if (operands[2] != const1_rtx) 11045 abort (); 11046 return "add{b}\t{%0, %0|%0, %0}"; 11047 11048 default: 11049 if (REG_P (operands[2])) 11050 return "sal{b}\t{%b2, %0|%0, %b2}"; 11051 else if (GET_CODE (operands[2]) == CONST_INT 11052 && INTVAL (operands[2]) == 1 11053 && (TARGET_SHIFT1 || optimize_size)) 11054 return "sal{b}\t%0"; 11055 else 11056 return "sal{b}\t{%2, %0|%0, %2}"; 11057 } 11058} 11059 [(set (attr "type") 11060 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") 11061 (const_int 0)) 11062 (match_operand 0 "register_operand" "")) 11063 (match_operand 2 "const1_operand" "")) 11064 (const_string "alu") 11065 ] 11066 (const_string "ishift"))) 11067 (set_attr "mode" "QI")]) 11068 11069;; See comment above `ashldi3' about how this works. 11070 11071(define_expand "ashrdi3" 11072 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "") 11073 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "") 11074 (match_operand:QI 2 "nonmemory_operand" ""))) 11075 (clobber (reg:CC 17))])] 11076 "" 11077{ 11078 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode)) 11079 { 11080 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2])); 11081 DONE; 11082 } 11083 ix86_expand_binary_operator (ASHIFTRT, DImode, operands); 11084 DONE; 11085}) 11086 11087(define_insn "ashrdi3_63_rex64" 11088 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm") 11089 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0") 11090 (match_operand:DI 2 "const_int_operand" "i,i"))) 11091 (clobber (reg:CC 17))] 11092 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size) 11093 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" 11094 "@ 11095 {cqto|cqo} 11096 sar{q}\t{%2, %0|%0, %2}" 11097 [(set_attr "type" "imovx,ishift") 11098 (set_attr "prefix_0f" "0,*") 11099 (set_attr "length_immediate" "0,*") 11100 (set_attr "modrm" "0,1") 11101 (set_attr "mode" "DI")]) 11102 11103(define_insn "*ashrdi3_1_one_bit_rex64" 11104 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") 11105 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") 11106 (match_operand:QI 2 "const_int_1_operand" ""))) 11107 (clobber (reg:CC 17))] 11108 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands) 11109 && (TARGET_SHIFT1 || optimize_size)" 11110 "sar{q}\t%0" 11111 [(set_attr "type" "ishift") 11112 (set (attr "length") 11113 (if_then_else (match_operand:DI 0 "register_operand" "") 11114 (const_string "2") 11115 (const_string "*")))]) 11116 11117(define_insn "*ashrdi3_1_rex64" 11118 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") 11119 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") 11120 (match_operand:QI 2 "nonmemory_operand" "J,c"))) 11121 (clobber (reg:CC 17))] 11122 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" 11123 "@ 11124 sar{q}\t{%2, %0|%0, %2} 11125 sar{q}\t{%b2, %0|%0, %b2}" 11126 [(set_attr "type" "ishift") 11127 (set_attr "mode" "DI")]) 11128 11129;; This pattern can't accept a variable shift count, since shifts by 11130;; zero don't affect the flags. We assume that shifts by constant 11131;; zero are optimized away. 11132(define_insn "*ashrdi3_one_bit_cmp_rex64" 11133 [(set (reg 17) 11134 (compare 11135 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") 11136 (match_operand:QI 2 "const_int_1_operand" "")) 11137 (const_int 0))) 11138 (set (match_operand:DI 0 "nonimmediate_operand" "=rm") 11139 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 11140 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 11141 && (TARGET_SHIFT1 || optimize_size) 11142 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" 11143 "sar{q}\t%0" 11144 [(set_attr "type" "ishift") 11145 (set (attr "length") 11146 (if_then_else (match_operand:DI 0 "register_operand" "") 11147 (const_string "2") 11148 (const_string "*")))]) 11149 11150;; This pattern can't accept a variable shift count, since shifts by 11151;; zero don't affect the flags. We assume that shifts by constant 11152;; zero are optimized away. 11153(define_insn "*ashrdi3_cmp_rex64" 11154 [(set (reg 17) 11155 (compare 11156 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") 11157 (match_operand:QI 2 "const_int_operand" "n")) 11158 (const_int 0))) 11159 (set (match_operand:DI 0 "nonimmediate_operand" "=rm") 11160 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 11161 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 11162 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" 11163 "sar{q}\t{%2, %0|%0, %2}" 11164 [(set_attr "type" "ishift") 11165 (set_attr "mode" "DI")]) 11166 11167 11168(define_insn "ashrdi3_1" 11169 [(set (match_operand:DI 0 "register_operand" "=r") 11170 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 11171 (match_operand:QI 2 "nonmemory_operand" "Jc"))) 11172 (clobber (match_scratch:SI 3 "=&r")) 11173 (clobber (reg:CC 17))] 11174 "!TARGET_64BIT && TARGET_CMOVE" 11175 "#" 11176 [(set_attr "type" "multi")]) 11177 11178(define_insn "*ashrdi3_2" 11179 [(set (match_operand:DI 0 "register_operand" "=r") 11180 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 11181 (match_operand:QI 2 "nonmemory_operand" "Jc"))) 11182 (clobber (reg:CC 17))] 11183 "!TARGET_64BIT" 11184 "#" 11185 [(set_attr "type" "multi")]) 11186 11187(define_split 11188 [(set (match_operand:DI 0 "register_operand" "") 11189 (ashiftrt:DI (match_operand:DI 1 "register_operand" "") 11190 (match_operand:QI 2 "nonmemory_operand" ""))) 11191 (clobber (match_scratch:SI 3 "")) 11192 (clobber (reg:CC 17))] 11193 "!TARGET_64BIT && TARGET_CMOVE && reload_completed" 11194 [(const_int 0)] 11195 "ix86_split_ashrdi (operands, operands[3]); DONE;") 11196 11197(define_split 11198 [(set (match_operand:DI 0 "register_operand" "") 11199 (ashiftrt:DI (match_operand:DI 1 "register_operand" "") 11200 (match_operand:QI 2 "nonmemory_operand" ""))) 11201 (clobber (reg:CC 17))] 11202 "!TARGET_64BIT && reload_completed" 11203 [(const_int 0)] 11204 "ix86_split_ashrdi (operands, NULL_RTX); DONE;") 11205 11206(define_insn "x86_shrd_1" 11207 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m") 11208 (ior:SI (ashiftrt:SI (match_dup 0) 11209 (match_operand:QI 2 "nonmemory_operand" "I,c")) 11210 (ashift:SI (match_operand:SI 1 "register_operand" "r,r") 11211 (minus:QI (const_int 32) (match_dup 2))))) 11212 (clobber (reg:CC 17))] 11213 "" 11214 "@ 11215 shrd{l}\t{%2, %1, %0|%0, %1, %2} 11216 shrd{l}\t{%s2%1, %0|%0, %1, %2}" 11217 [(set_attr "type" "ishift") 11218 (set_attr "prefix_0f" "1") 11219 (set_attr "pent_pair" "np") 11220 (set_attr "ppro_uops" "few") 11221 (set_attr "mode" "SI")]) 11222 11223(define_expand "x86_shift_adj_3" 11224 [(use (match_operand:SI 0 "register_operand" "")) 11225 (use (match_operand:SI 1 "register_operand" "")) 11226 (use (match_operand:QI 2 "register_operand" ""))] 11227 "" 11228{ 11229 rtx label = gen_label_rtx (); 11230 rtx tmp; 11231 11232 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32))); 11233 11234 tmp = gen_rtx_REG (CCZmode, FLAGS_REG); 11235 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); 11236 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 11237 gen_rtx_LABEL_REF (VOIDmode, label), 11238 pc_rtx); 11239 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); 11240 JUMP_LABEL (tmp) = label; 11241 11242 emit_move_insn (operands[0], operands[1]); 11243 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31))); 11244 11245 emit_label (label); 11246 LABEL_NUSES (label) = 1; 11247 11248 DONE; 11249}) 11250 11251(define_insn "ashrsi3_31" 11252 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm") 11253 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0") 11254 (match_operand:SI 2 "const_int_operand" "i,i"))) 11255 (clobber (reg:CC 17))] 11256 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size) 11257 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" 11258 "@ 11259 {cltd|cdq} 11260 sar{l}\t{%2, %0|%0, %2}" 11261 [(set_attr "type" "imovx,ishift") 11262 (set_attr "prefix_0f" "0,*") 11263 (set_attr "length_immediate" "0,*") 11264 (set_attr "modrm" "0,1") 11265 (set_attr "mode" "SI")]) 11266 11267(define_insn "*ashrsi3_31_zext" 11268 [(set (match_operand:DI 0 "register_operand" "=*d,r") 11269 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0") 11270 (match_operand:SI 2 "const_int_operand" "i,i")))) 11271 (clobber (reg:CC 17))] 11272 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size) 11273 && INTVAL (operands[2]) == 31 11274 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" 11275 "@ 11276 {cltd|cdq} 11277 sar{l}\t{%2, %k0|%k0, %2}" 11278 [(set_attr "type" "imovx,ishift") 11279 (set_attr "prefix_0f" "0,*") 11280 (set_attr "length_immediate" "0,*") 11281 (set_attr "modrm" "0,1") 11282 (set_attr "mode" "SI")]) 11283 11284(define_expand "ashrsi3" 11285 [(set (match_operand:SI 0 "nonimmediate_operand" "") 11286 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "") 11287 (match_operand:QI 2 "nonmemory_operand" ""))) 11288 (clobber (reg:CC 17))] 11289 "" 11290 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;") 11291 11292(define_insn "*ashrsi3_1_one_bit" 11293 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 11294 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") 11295 (match_operand:QI 2 "const_int_1_operand" ""))) 11296 (clobber (reg:CC 17))] 11297 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands) 11298 && (TARGET_SHIFT1 || optimize_size)" 11299 "sar{l}\t%0" 11300 [(set_attr "type" "ishift") 11301 (set (attr "length") 11302 (if_then_else (match_operand:SI 0 "register_operand" "") 11303 (const_string "2") 11304 (const_string "*")))]) 11305 11306(define_insn "*ashrsi3_1_one_bit_zext" 11307 [(set (match_operand:DI 0 "register_operand" "=r") 11308 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 11309 (match_operand:QI 2 "const_int_1_operand" "")))) 11310 (clobber (reg:CC 17))] 11311 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands) 11312 && (TARGET_SHIFT1 || optimize_size)" 11313 "sar{l}\t%k0" 11314 [(set_attr "type" "ishift") 11315 (set_attr "length" "2")]) 11316 11317(define_insn "*ashrsi3_1" 11318 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") 11319 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") 11320 (match_operand:QI 2 "nonmemory_operand" "I,c"))) 11321 (clobber (reg:CC 17))] 11322 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" 11323 "@ 11324 sar{l}\t{%2, %0|%0, %2} 11325 sar{l}\t{%b2, %0|%0, %b2}" 11326 [(set_attr "type" "ishift") 11327 (set_attr "mode" "SI")]) 11328 11329(define_insn "*ashrsi3_1_zext" 11330 [(set (match_operand:DI 0 "register_operand" "=r,r") 11331 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") 11332 (match_operand:QI 2 "nonmemory_operand" "I,c")))) 11333 (clobber (reg:CC 17))] 11334 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" 11335 "@ 11336 sar{l}\t{%2, %k0|%k0, %2} 11337 sar{l}\t{%b2, %k0|%k0, %b2}" 11338 [(set_attr "type" "ishift") 11339 (set_attr "mode" "SI")]) 11340 11341;; This pattern can't accept a variable shift count, since shifts by 11342;; zero don't affect the flags. We assume that shifts by constant 11343;; zero are optimized away. 11344(define_insn "*ashrsi3_one_bit_cmp" 11345 [(set (reg 17) 11346 (compare 11347 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") 11348 (match_operand:QI 2 "const_int_1_operand" "")) 11349 (const_int 0))) 11350 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 11351 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 11352 "ix86_match_ccmode (insn, CCGOCmode) 11353 && (TARGET_SHIFT1 || optimize_size) 11354 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" 11355 "sar{l}\t%0" 11356 [(set_attr "type" "ishift") 11357 (set (attr "length") 11358 (if_then_else (match_operand:SI 0 "register_operand" "") 11359 (const_string "2") 11360 (const_string "*")))]) 11361 11362(define_insn "*ashrsi3_one_bit_cmp_zext" 11363 [(set (reg 17) 11364 (compare 11365 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 11366 (match_operand:QI 2 "const_int_1_operand" "")) 11367 (const_int 0))) 11368 (set (match_operand:DI 0 "register_operand" "=r") 11369 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))] 11370 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode) 11371 && (TARGET_SHIFT1 || optimize_size) 11372 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" 11373 "sar{l}\t%k0" 11374 [(set_attr "type" "ishift") 11375 (set_attr "length" "2")]) 11376 11377;; This pattern can't accept a variable shift count, since shifts by 11378;; zero don't affect the flags. We assume that shifts by constant 11379;; zero are optimized away. 11380(define_insn "*ashrsi3_cmp" 11381 [(set (reg 17) 11382 (compare 11383 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") 11384 (match_operand:QI 2 "const_int_1_31_operand" "I")) 11385 (const_int 0))) 11386 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 11387 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 11388 "ix86_match_ccmode (insn, CCGOCmode) 11389 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" 11390 "sar{l}\t{%2, %0|%0, %2}" 11391 [(set_attr "type" "ishift") 11392 (set_attr "mode" "SI")]) 11393 11394(define_insn "*ashrsi3_cmp_zext" 11395 [(set (reg 17) 11396 (compare 11397 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 11398 (match_operand:QI 2 "const_int_1_31_operand" "I")) 11399 (const_int 0))) 11400 (set (match_operand:DI 0 "register_operand" "=r") 11401 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))] 11402 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 11403 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" 11404 "sar{l}\t{%2, %k0|%k0, %2}" 11405 [(set_attr "type" "ishift") 11406 (set_attr "mode" "SI")]) 11407 11408(define_expand "ashrhi3" 11409 [(set (match_operand:HI 0 "nonimmediate_operand" "") 11410 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "") 11411 (match_operand:QI 2 "nonmemory_operand" ""))) 11412 (clobber (reg:CC 17))] 11413 "TARGET_HIMODE_MATH" 11414 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;") 11415 11416(define_insn "*ashrhi3_1_one_bit" 11417 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 11418 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") 11419 (match_operand:QI 2 "const_int_1_operand" ""))) 11420 (clobber (reg:CC 17))] 11421 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands) 11422 && (TARGET_SHIFT1 || optimize_size)" 11423 "sar{w}\t%0" 11424 [(set_attr "type" "ishift") 11425 (set (attr "length") 11426 (if_then_else (match_operand 0 "register_operand" "") 11427 (const_string "2") 11428 (const_string "*")))]) 11429 11430(define_insn "*ashrhi3_1" 11431 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") 11432 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") 11433 (match_operand:QI 2 "nonmemory_operand" "I,c"))) 11434 (clobber (reg:CC 17))] 11435 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" 11436 "@ 11437 sar{w}\t{%2, %0|%0, %2} 11438 sar{w}\t{%b2, %0|%0, %b2}" 11439 [(set_attr "type" "ishift") 11440 (set_attr "mode" "HI")]) 11441 11442;; This pattern can't accept a variable shift count, since shifts by 11443;; zero don't affect the flags. We assume that shifts by constant 11444;; zero are optimized away. 11445(define_insn "*ashrhi3_one_bit_cmp" 11446 [(set (reg 17) 11447 (compare 11448 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") 11449 (match_operand:QI 2 "const_int_1_operand" "")) 11450 (const_int 0))) 11451 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 11452 (ashiftrt:HI (match_dup 1) (match_dup 2)))] 11453 "ix86_match_ccmode (insn, CCGOCmode) 11454 && (TARGET_SHIFT1 || optimize_size) 11455 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" 11456 "sar{w}\t%0" 11457 [(set_attr "type" "ishift") 11458 (set (attr "length") 11459 (if_then_else (match_operand 0 "register_operand" "") 11460 (const_string "2") 11461 (const_string "*")))]) 11462 11463;; This pattern can't accept a variable shift count, since shifts by 11464;; zero don't affect the flags. We assume that shifts by constant 11465;; zero are optimized away. 11466(define_insn "*ashrhi3_cmp" 11467 [(set (reg 17) 11468 (compare 11469 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") 11470 (match_operand:QI 2 "const_int_1_31_operand" "I")) 11471 (const_int 0))) 11472 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 11473 (ashiftrt:HI (match_dup 1) (match_dup 2)))] 11474 "ix86_match_ccmode (insn, CCGOCmode) 11475 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" 11476 "sar{w}\t{%2, %0|%0, %2}" 11477 [(set_attr "type" "ishift") 11478 (set_attr "mode" "HI")]) 11479 11480(define_expand "ashrqi3" 11481 [(set (match_operand:QI 0 "nonimmediate_operand" "") 11482 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "") 11483 (match_operand:QI 2 "nonmemory_operand" ""))) 11484 (clobber (reg:CC 17))] 11485 "TARGET_QIMODE_MATH" 11486 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;") 11487 11488(define_insn "*ashrqi3_1_one_bit" 11489 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 11490 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") 11491 (match_operand:QI 2 "const_int_1_operand" ""))) 11492 (clobber (reg:CC 17))] 11493 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands) 11494 && (TARGET_SHIFT1 || optimize_size)" 11495 "sar{b}\t%0" 11496 [(set_attr "type" "ishift") 11497 (set (attr "length") 11498 (if_then_else (match_operand 0 "register_operand" "") 11499 (const_string "2") 11500 (const_string "*")))]) 11501 11502(define_insn "*ashrqi3_1_one_bit_slp" 11503 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) 11504 (ashiftrt:QI (match_dup 0) 11505 (match_operand:QI 1 "const_int_1_operand" ""))) 11506 (clobber (reg:CC 17))] 11507 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands) 11508 && (! TARGET_PARTIAL_REG_STALL || optimize_size) 11509 && (TARGET_SHIFT1 || optimize_size)" 11510 "sar{b}\t%0" 11511 [(set_attr "type" "ishift1") 11512 (set (attr "length") 11513 (if_then_else (match_operand 0 "register_operand" "") 11514 (const_string "2") 11515 (const_string "*")))]) 11516 11517(define_insn "*ashrqi3_1" 11518 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") 11519 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") 11520 (match_operand:QI 2 "nonmemory_operand" "I,c"))) 11521 (clobber (reg:CC 17))] 11522 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" 11523 "@ 11524 sar{b}\t{%2, %0|%0, %2} 11525 sar{b}\t{%b2, %0|%0, %b2}" 11526 [(set_attr "type" "ishift") 11527 (set_attr "mode" "QI")]) 11528 11529(define_insn "*ashrqi3_1_slp" 11530 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) 11531 (ashiftrt:QI (match_dup 0) 11532 (match_operand:QI 1 "nonmemory_operand" "I,c"))) 11533 (clobber (reg:CC 17))] 11534 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 11535 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 11536 "@ 11537 sar{b}\t{%1, %0|%0, %1} 11538 sar{b}\t{%b1, %0|%0, %b1}" 11539 [(set_attr "type" "ishift1") 11540 (set_attr "mode" "QI")]) 11541 11542;; This pattern can't accept a variable shift count, since shifts by 11543;; zero don't affect the flags. We assume that shifts by constant 11544;; zero are optimized away. 11545(define_insn "*ashrqi3_one_bit_cmp" 11546 [(set (reg 17) 11547 (compare 11548 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") 11549 (match_operand:QI 2 "const_int_1_operand" "I")) 11550 (const_int 0))) 11551 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") 11552 (ashiftrt:QI (match_dup 1) (match_dup 2)))] 11553 "ix86_match_ccmode (insn, CCGOCmode) 11554 && (TARGET_SHIFT1 || optimize_size) 11555 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" 11556 "sar{b}\t%0" 11557 [(set_attr "type" "ishift") 11558 (set (attr "length") 11559 (if_then_else (match_operand 0 "register_operand" "") 11560 (const_string "2") 11561 (const_string "*")))]) 11562 11563;; This pattern can't accept a variable shift count, since shifts by 11564;; zero don't affect the flags. We assume that shifts by constant 11565;; zero are optimized away. 11566(define_insn "*ashrqi3_cmp" 11567 [(set (reg 17) 11568 (compare 11569 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") 11570 (match_operand:QI 2 "const_int_1_31_operand" "I")) 11571 (const_int 0))) 11572 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") 11573 (ashiftrt:QI (match_dup 1) (match_dup 2)))] 11574 "ix86_match_ccmode (insn, CCGOCmode) 11575 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" 11576 "sar{b}\t{%2, %0|%0, %2}" 11577 [(set_attr "type" "ishift") 11578 (set_attr "mode" "QI")]) 11579 11580;; Logical shift instructions 11581 11582;; See comment above `ashldi3' about how this works. 11583 11584(define_expand "lshrdi3" 11585 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "") 11586 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "") 11587 (match_operand:QI 2 "nonmemory_operand" ""))) 11588 (clobber (reg:CC 17))])] 11589 "" 11590{ 11591 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode)) 11592 { 11593 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2])); 11594 DONE; 11595 } 11596 ix86_expand_binary_operator (LSHIFTRT, DImode, operands); 11597 DONE; 11598}) 11599 11600(define_insn "*lshrdi3_1_one_bit_rex64" 11601 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") 11602 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") 11603 (match_operand:QI 2 "const_int_1_operand" ""))) 11604 (clobber (reg:CC 17))] 11605 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) 11606 && (TARGET_SHIFT1 || optimize_size)" 11607 "shr{q}\t%0" 11608 [(set_attr "type" "ishift") 11609 (set (attr "length") 11610 (if_then_else (match_operand:DI 0 "register_operand" "") 11611 (const_string "2") 11612 (const_string "*")))]) 11613 11614(define_insn "*lshrdi3_1_rex64" 11615 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") 11616 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") 11617 (match_operand:QI 2 "nonmemory_operand" "J,c"))) 11618 (clobber (reg:CC 17))] 11619 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 11620 "@ 11621 shr{q}\t{%2, %0|%0, %2} 11622 shr{q}\t{%b2, %0|%0, %b2}" 11623 [(set_attr "type" "ishift") 11624 (set_attr "mode" "DI")]) 11625 11626;; This pattern can't accept a variable shift count, since shifts by 11627;; zero don't affect the flags. We assume that shifts by constant 11628;; zero are optimized away. 11629(define_insn "*lshrdi3_cmp_one_bit_rex64" 11630 [(set (reg 17) 11631 (compare 11632 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") 11633 (match_operand:QI 2 "const_int_1_operand" "")) 11634 (const_int 0))) 11635 (set (match_operand:DI 0 "nonimmediate_operand" "=rm") 11636 (lshiftrt:DI (match_dup 1) (match_dup 2)))] 11637 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 11638 && (TARGET_SHIFT1 || optimize_size) 11639 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 11640 "shr{q}\t%0" 11641 [(set_attr "type" "ishift") 11642 (set (attr "length") 11643 (if_then_else (match_operand:DI 0 "register_operand" "") 11644 (const_string "2") 11645 (const_string "*")))]) 11646 11647;; This pattern can't accept a variable shift count, since shifts by 11648;; zero don't affect the flags. We assume that shifts by constant 11649;; zero are optimized away. 11650(define_insn "*lshrdi3_cmp_rex64" 11651 [(set (reg 17) 11652 (compare 11653 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") 11654 (match_operand:QI 2 "const_int_operand" "e")) 11655 (const_int 0))) 11656 (set (match_operand:DI 0 "nonimmediate_operand" "=rm") 11657 (lshiftrt:DI (match_dup 1) (match_dup 2)))] 11658 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 11659 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 11660 "shr{q}\t{%2, %0|%0, %2}" 11661 [(set_attr "type" "ishift") 11662 (set_attr "mode" "DI")]) 11663 11664(define_insn "lshrdi3_1" 11665 [(set (match_operand:DI 0 "register_operand" "=r") 11666 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") 11667 (match_operand:QI 2 "nonmemory_operand" "Jc"))) 11668 (clobber (match_scratch:SI 3 "=&r")) 11669 (clobber (reg:CC 17))] 11670 "!TARGET_64BIT && TARGET_CMOVE" 11671 "#" 11672 [(set_attr "type" "multi")]) 11673 11674(define_insn "*lshrdi3_2" 11675 [(set (match_operand:DI 0 "register_operand" "=r") 11676 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") 11677 (match_operand:QI 2 "nonmemory_operand" "Jc"))) 11678 (clobber (reg:CC 17))] 11679 "!TARGET_64BIT" 11680 "#" 11681 [(set_attr "type" "multi")]) 11682 11683(define_split 11684 [(set (match_operand:DI 0 "register_operand" "") 11685 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 11686 (match_operand:QI 2 "nonmemory_operand" ""))) 11687 (clobber (match_scratch:SI 3 "")) 11688 (clobber (reg:CC 17))] 11689 "!TARGET_64BIT && TARGET_CMOVE && reload_completed" 11690 [(const_int 0)] 11691 "ix86_split_lshrdi (operands, operands[3]); DONE;") 11692 11693(define_split 11694 [(set (match_operand:DI 0 "register_operand" "") 11695 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 11696 (match_operand:QI 2 "nonmemory_operand" ""))) 11697 (clobber (reg:CC 17))] 11698 "!TARGET_64BIT && reload_completed" 11699 [(const_int 0)] 11700 "ix86_split_lshrdi (operands, NULL_RTX); DONE;") 11701 11702(define_expand "lshrsi3" 11703 [(set (match_operand:SI 0 "nonimmediate_operand" "") 11704 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "") 11705 (match_operand:QI 2 "nonmemory_operand" ""))) 11706 (clobber (reg:CC 17))] 11707 "" 11708 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;") 11709 11710(define_insn "*lshrsi3_1_one_bit" 11711 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 11712 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") 11713 (match_operand:QI 2 "const_int_1_operand" ""))) 11714 (clobber (reg:CC 17))] 11715 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands) 11716 && (TARGET_SHIFT1 || optimize_size)" 11717 "shr{l}\t%0" 11718 [(set_attr "type" "ishift") 11719 (set (attr "length") 11720 (if_then_else (match_operand:SI 0 "register_operand" "") 11721 (const_string "2") 11722 (const_string "*")))]) 11723 11724(define_insn "*lshrsi3_1_one_bit_zext" 11725 [(set (match_operand:DI 0 "register_operand" "=r") 11726 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0")) 11727 (match_operand:QI 2 "const_int_1_operand" ""))) 11728 (clobber (reg:CC 17))] 11729 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) 11730 && (TARGET_SHIFT1 || optimize_size)" 11731 "shr{l}\t%k0" 11732 [(set_attr "type" "ishift") 11733 (set_attr "length" "2")]) 11734 11735(define_insn "*lshrsi3_1" 11736 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") 11737 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") 11738 (match_operand:QI 2 "nonmemory_operand" "I,c"))) 11739 (clobber (reg:CC 17))] 11740 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 11741 "@ 11742 shr{l}\t{%2, %0|%0, %2} 11743 shr{l}\t{%b2, %0|%0, %b2}" 11744 [(set_attr "type" "ishift") 11745 (set_attr "mode" "SI")]) 11746 11747(define_insn "*lshrsi3_1_zext" 11748 [(set (match_operand:DI 0 "register_operand" "=r,r") 11749 (zero_extend:DI 11750 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") 11751 (match_operand:QI 2 "nonmemory_operand" "I,c")))) 11752 (clobber (reg:CC 17))] 11753 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 11754 "@ 11755 shr{l}\t{%2, %k0|%k0, %2} 11756 shr{l}\t{%b2, %k0|%k0, %b2}" 11757 [(set_attr "type" "ishift") 11758 (set_attr "mode" "SI")]) 11759 11760;; This pattern can't accept a variable shift count, since shifts by 11761;; zero don't affect the flags. We assume that shifts by constant 11762;; zero are optimized away. 11763(define_insn "*lshrsi3_one_bit_cmp" 11764 [(set (reg 17) 11765 (compare 11766 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") 11767 (match_operand:QI 2 "const_int_1_operand" "")) 11768 (const_int 0))) 11769 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 11770 (lshiftrt:SI (match_dup 1) (match_dup 2)))] 11771 "ix86_match_ccmode (insn, CCGOCmode) 11772 && (TARGET_SHIFT1 || optimize_size) 11773 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 11774 "shr{l}\t%0" 11775 [(set_attr "type" "ishift") 11776 (set (attr "length") 11777 (if_then_else (match_operand:SI 0 "register_operand" "") 11778 (const_string "2") 11779 (const_string "*")))]) 11780 11781(define_insn "*lshrsi3_cmp_one_bit_zext" 11782 [(set (reg 17) 11783 (compare 11784 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 11785 (match_operand:QI 2 "const_int_1_operand" "")) 11786 (const_int 0))) 11787 (set (match_operand:DI 0 "register_operand" "=r") 11788 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] 11789 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 11790 && (TARGET_SHIFT1 || optimize_size) 11791 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 11792 "shr{l}\t%k0" 11793 [(set_attr "type" "ishift") 11794 (set_attr "length" "2")]) 11795 11796;; This pattern can't accept a variable shift count, since shifts by 11797;; zero don't affect the flags. We assume that shifts by constant 11798;; zero are optimized away. 11799(define_insn "*lshrsi3_cmp" 11800 [(set (reg 17) 11801 (compare 11802 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") 11803 (match_operand:QI 2 "const_int_1_31_operand" "I")) 11804 (const_int 0))) 11805 (set (match_operand:SI 0 "nonimmediate_operand" "=rm") 11806 (lshiftrt:SI (match_dup 1) (match_dup 2)))] 11807 "ix86_match_ccmode (insn, CCGOCmode) 11808 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 11809 "shr{l}\t{%2, %0|%0, %2}" 11810 [(set_attr "type" "ishift") 11811 (set_attr "mode" "SI")]) 11812 11813(define_insn "*lshrsi3_cmp_zext" 11814 [(set (reg 17) 11815 (compare 11816 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 11817 (match_operand:QI 2 "const_int_1_31_operand" "I")) 11818 (const_int 0))) 11819 (set (match_operand:DI 0 "register_operand" "=r") 11820 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] 11821 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) 11822 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 11823 "shr{l}\t{%2, %k0|%k0, %2}" 11824 [(set_attr "type" "ishift") 11825 (set_attr "mode" "SI")]) 11826 11827(define_expand "lshrhi3" 11828 [(set (match_operand:HI 0 "nonimmediate_operand" "") 11829 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "") 11830 (match_operand:QI 2 "nonmemory_operand" ""))) 11831 (clobber (reg:CC 17))] 11832 "TARGET_HIMODE_MATH" 11833 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;") 11834 11835(define_insn "*lshrhi3_1_one_bit" 11836 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 11837 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") 11838 (match_operand:QI 2 "const_int_1_operand" ""))) 11839 (clobber (reg:CC 17))] 11840 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands) 11841 && (TARGET_SHIFT1 || optimize_size)" 11842 "shr{w}\t%0" 11843 [(set_attr "type" "ishift") 11844 (set (attr "length") 11845 (if_then_else (match_operand 0 "register_operand" "") 11846 (const_string "2") 11847 (const_string "*")))]) 11848 11849(define_insn "*lshrhi3_1" 11850 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") 11851 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") 11852 (match_operand:QI 2 "nonmemory_operand" "I,c"))) 11853 (clobber (reg:CC 17))] 11854 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 11855 "@ 11856 shr{w}\t{%2, %0|%0, %2} 11857 shr{w}\t{%b2, %0|%0, %b2}" 11858 [(set_attr "type" "ishift") 11859 (set_attr "mode" "HI")]) 11860 11861;; This pattern can't accept a variable shift count, since shifts by 11862;; zero don't affect the flags. We assume that shifts by constant 11863;; zero are optimized away. 11864(define_insn "*lshrhi3_one_bit_cmp" 11865 [(set (reg 17) 11866 (compare 11867 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") 11868 (match_operand:QI 2 "const_int_1_operand" "")) 11869 (const_int 0))) 11870 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 11871 (lshiftrt:HI (match_dup 1) (match_dup 2)))] 11872 "ix86_match_ccmode (insn, CCGOCmode) 11873 && (TARGET_SHIFT1 || optimize_size) 11874 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 11875 "shr{w}\t%0" 11876 [(set_attr "type" "ishift") 11877 (set (attr "length") 11878 (if_then_else (match_operand:SI 0 "register_operand" "") 11879 (const_string "2") 11880 (const_string "*")))]) 11881 11882;; This pattern can't accept a variable shift count, since shifts by 11883;; zero don't affect the flags. We assume that shifts by constant 11884;; zero are optimized away. 11885(define_insn "*lshrhi3_cmp" 11886 [(set (reg 17) 11887 (compare 11888 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") 11889 (match_operand:QI 2 "const_int_1_31_operand" "I")) 11890 (const_int 0))) 11891 (set (match_operand:HI 0 "nonimmediate_operand" "=rm") 11892 (lshiftrt:HI (match_dup 1) (match_dup 2)))] 11893 "ix86_match_ccmode (insn, CCGOCmode) 11894 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" 11895 "shr{w}\t{%2, %0|%0, %2}" 11896 [(set_attr "type" "ishift") 11897 (set_attr "mode" "HI")]) 11898 11899(define_expand "lshrqi3" 11900 [(set (match_operand:QI 0 "nonimmediate_operand" "") 11901 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "") 11902 (match_operand:QI 2 "nonmemory_operand" ""))) 11903 (clobber (reg:CC 17))] 11904 "TARGET_QIMODE_MATH" 11905 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;") 11906 11907(define_insn "*lshrqi3_1_one_bit" 11908 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 11909 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") 11910 (match_operand:QI 2 "const_int_1_operand" ""))) 11911 (clobber (reg:CC 17))] 11912 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands) 11913 && (TARGET_SHIFT1 || optimize_size)" 11914 "shr{b}\t%0" 11915 [(set_attr "type" "ishift") 11916 (set (attr "length") 11917 (if_then_else (match_operand 0 "register_operand" "") 11918 (const_string "2") 11919 (const_string "*")))]) 11920 11921(define_insn "*lshrqi3_1_one_bit_slp" 11922 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) 11923 (lshiftrt:QI (match_dup 0) 11924 (match_operand:QI 1 "const_int_1_operand" ""))) 11925 (clobber (reg:CC 17))] 11926 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 11927 && (TARGET_SHIFT1 || optimize_size)" 11928 "shr{b}\t%0" 11929 [(set_attr "type" "ishift1") 11930 (set (attr "length") 11931 (if_then_else (match_operand 0 "register_operand" "") 11932 (const_string "2") 11933 (const_string "*")))]) 11934 11935(define_insn "*lshrqi3_1" 11936 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") 11937 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") 11938 (match_operand:QI 2 "nonmemory_operand" "I,c"))) 11939 (clobber (reg:CC 17))] 11940 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" 11941 "@ 11942 shr{b}\t{%2, %0|%0, %2} 11943 shr{b}\t{%b2, %0|%0, %b2}" 11944 [(set_attr "type" "ishift") 11945 (set_attr "mode" "QI")]) 11946 11947(define_insn "*lshrqi3_1_slp" 11948 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) 11949 (lshiftrt:QI (match_dup 0) 11950 (match_operand:QI 1 "nonmemory_operand" "I,c"))) 11951 (clobber (reg:CC 17))] 11952 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 11953 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 11954 "@ 11955 shr{b}\t{%1, %0|%0, %1} 11956 shr{b}\t{%b1, %0|%0, %b1}" 11957 [(set_attr "type" "ishift1") 11958 (set_attr "mode" "QI")]) 11959 11960;; This pattern can't accept a variable shift count, since shifts by 11961;; zero don't affect the flags. We assume that shifts by constant 11962;; zero are optimized away. 11963(define_insn "*lshrqi2_one_bit_cmp" 11964 [(set (reg 17) 11965 (compare 11966 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") 11967 (match_operand:QI 2 "const_int_1_operand" "")) 11968 (const_int 0))) 11969 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") 11970 (lshiftrt:QI (match_dup 1) (match_dup 2)))] 11971 "ix86_match_ccmode (insn, CCGOCmode) 11972 && (TARGET_SHIFT1 || optimize_size) 11973 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" 11974 "shr{b}\t%0" 11975 [(set_attr "type" "ishift") 11976 (set (attr "length") 11977 (if_then_else (match_operand:SI 0 "register_operand" "") 11978 (const_string "2") 11979 (const_string "*")))]) 11980 11981;; This pattern can't accept a variable shift count, since shifts by 11982;; zero don't affect the flags. We assume that shifts by constant 11983;; zero are optimized away. 11984(define_insn "*lshrqi2_cmp" 11985 [(set (reg 17) 11986 (compare 11987 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") 11988 (match_operand:QI 2 "const_int_1_31_operand" "I")) 11989 (const_int 0))) 11990 (set (match_operand:QI 0 "nonimmediate_operand" "=qm") 11991 (lshiftrt:QI (match_dup 1) (match_dup 2)))] 11992 "ix86_match_ccmode (insn, CCGOCmode) 11993 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" 11994 "shr{b}\t{%2, %0|%0, %2}" 11995 [(set_attr "type" "ishift") 11996 (set_attr "mode" "QI")]) 11997 11998;; Rotate instructions 11999 12000(define_expand "rotldi3" 12001 [(set (match_operand:DI 0 "nonimmediate_operand" "") 12002 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "") 12003 (match_operand:QI 2 "nonmemory_operand" ""))) 12004 (clobber (reg:CC 17))] 12005 "TARGET_64BIT" 12006 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;") 12007 12008(define_insn "*rotlsi3_1_one_bit_rex64" 12009 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") 12010 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0") 12011 (match_operand:QI 2 "const_int_1_operand" ""))) 12012 (clobber (reg:CC 17))] 12013 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands) 12014 && (TARGET_SHIFT1 || optimize_size)" 12015 "rol{q}\t%0" 12016 [(set_attr "type" "rotate") 12017 (set (attr "length") 12018 (if_then_else (match_operand:DI 0 "register_operand" "") 12019 (const_string "2") 12020 (const_string "*")))]) 12021 12022(define_insn "*rotldi3_1_rex64" 12023 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") 12024 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") 12025 (match_operand:QI 2 "nonmemory_operand" "e,c"))) 12026 (clobber (reg:CC 17))] 12027 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)" 12028 "@ 12029 rol{q}\t{%2, %0|%0, %2} 12030 rol{q}\t{%b2, %0|%0, %b2}" 12031 [(set_attr "type" "rotate") 12032 (set_attr "mode" "DI")]) 12033 12034(define_expand "rotlsi3" 12035 [(set (match_operand:SI 0 "nonimmediate_operand" "") 12036 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "") 12037 (match_operand:QI 2 "nonmemory_operand" ""))) 12038 (clobber (reg:CC 17))] 12039 "" 12040 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;") 12041 12042(define_insn "*rotlsi3_1_one_bit" 12043 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 12044 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0") 12045 (match_operand:QI 2 "const_int_1_operand" ""))) 12046 (clobber (reg:CC 17))] 12047 "ix86_binary_operator_ok (ROTATE, SImode, operands) 12048 && (TARGET_SHIFT1 || optimize_size)" 12049 "rol{l}\t%0" 12050 [(set_attr "type" "rotate") 12051 (set (attr "length") 12052 (if_then_else (match_operand:SI 0 "register_operand" "") 12053 (const_string "2") 12054 (const_string "*")))]) 12055 12056(define_insn "*rotlsi3_1_one_bit_zext" 12057 [(set (match_operand:DI 0 "register_operand" "=r") 12058 (zero_extend:DI 12059 (rotate:SI (match_operand:SI 1 "register_operand" "0") 12060 (match_operand:QI 2 "const_int_1_operand" "")))) 12061 (clobber (reg:CC 17))] 12062 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands) 12063 && (TARGET_SHIFT1 || optimize_size)" 12064 "rol{l}\t%k0" 12065 [(set_attr "type" "rotate") 12066 (set_attr "length" "2")]) 12067 12068(define_insn "*rotlsi3_1" 12069 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") 12070 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") 12071 (match_operand:QI 2 "nonmemory_operand" "I,c"))) 12072 (clobber (reg:CC 17))] 12073 "ix86_binary_operator_ok (ROTATE, SImode, operands)" 12074 "@ 12075 rol{l}\t{%2, %0|%0, %2} 12076 rol{l}\t{%b2, %0|%0, %b2}" 12077 [(set_attr "type" "rotate") 12078 (set_attr "mode" "SI")]) 12079 12080(define_insn "*rotlsi3_1_zext" 12081 [(set (match_operand:DI 0 "register_operand" "=r,r") 12082 (zero_extend:DI 12083 (rotate:SI (match_operand:SI 1 "register_operand" "0,0") 12084 (match_operand:QI 2 "nonmemory_operand" "I,c")))) 12085 (clobber (reg:CC 17))] 12086 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)" 12087 "@ 12088 rol{l}\t{%2, %k0|%k0, %2} 12089 rol{l}\t{%b2, %k0|%k0, %b2}" 12090 [(set_attr "type" "rotate") 12091 (set_attr "mode" "SI")]) 12092 12093(define_expand "rotlhi3" 12094 [(set (match_operand:HI 0 "nonimmediate_operand" "") 12095 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "") 12096 (match_operand:QI 2 "nonmemory_operand" ""))) 12097 (clobber (reg:CC 17))] 12098 "TARGET_HIMODE_MATH" 12099 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;") 12100 12101(define_insn "*rotlhi3_1_one_bit" 12102 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 12103 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0") 12104 (match_operand:QI 2 "const_int_1_operand" ""))) 12105 (clobber (reg:CC 17))] 12106 "ix86_binary_operator_ok (ROTATE, HImode, operands) 12107 && (TARGET_SHIFT1 || optimize_size)" 12108 "rol{w}\t%0" 12109 [(set_attr "type" "rotate") 12110 (set (attr "length") 12111 (if_then_else (match_operand 0 "register_operand" "") 12112 (const_string "2") 12113 (const_string "*")))]) 12114 12115(define_insn "*rotlhi3_1" 12116 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") 12117 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") 12118 (match_operand:QI 2 "nonmemory_operand" "I,c"))) 12119 (clobber (reg:CC 17))] 12120 "ix86_binary_operator_ok (ROTATE, HImode, operands)" 12121 "@ 12122 rol{w}\t{%2, %0|%0, %2} 12123 rol{w}\t{%b2, %0|%0, %b2}" 12124 [(set_attr "type" "rotate") 12125 (set_attr "mode" "HI")]) 12126 12127(define_expand "rotlqi3" 12128 [(set (match_operand:QI 0 "nonimmediate_operand" "") 12129 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "") 12130 (match_operand:QI 2 "nonmemory_operand" ""))) 12131 (clobber (reg:CC 17))] 12132 "TARGET_QIMODE_MATH" 12133 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;") 12134 12135(define_insn "*rotlqi3_1_one_bit_slp" 12136 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) 12137 (rotate:QI (match_dup 0) 12138 (match_operand:QI 1 "const_int_1_operand" ""))) 12139 (clobber (reg:CC 17))] 12140 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 12141 && (TARGET_SHIFT1 || optimize_size)" 12142 "rol{b}\t%0" 12143 [(set_attr "type" "rotate1") 12144 (set (attr "length") 12145 (if_then_else (match_operand 0 "register_operand" "") 12146 (const_string "2") 12147 (const_string "*")))]) 12148 12149(define_insn "*rotlqi3_1_one_bit" 12150 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 12151 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0") 12152 (match_operand:QI 2 "const_int_1_operand" ""))) 12153 (clobber (reg:CC 17))] 12154 "ix86_binary_operator_ok (ROTATE, QImode, operands) 12155 && (TARGET_SHIFT1 || optimize_size)" 12156 "rol{b}\t%0" 12157 [(set_attr "type" "rotate") 12158 (set (attr "length") 12159 (if_then_else (match_operand 0 "register_operand" "") 12160 (const_string "2") 12161 (const_string "*")))]) 12162 12163(define_insn "*rotlqi3_1_slp" 12164 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) 12165 (rotate:QI (match_dup 0) 12166 (match_operand:QI 1 "nonmemory_operand" "I,c"))) 12167 (clobber (reg:CC 17))] 12168 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 12169 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 12170 "@ 12171 rol{b}\t{%1, %0|%0, %1} 12172 rol{b}\t{%b1, %0|%0, %b1}" 12173 [(set_attr "type" "rotate1") 12174 (set_attr "mode" "QI")]) 12175 12176(define_insn "*rotlqi3_1" 12177 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") 12178 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") 12179 (match_operand:QI 2 "nonmemory_operand" "I,c"))) 12180 (clobber (reg:CC 17))] 12181 "ix86_binary_operator_ok (ROTATE, QImode, operands)" 12182 "@ 12183 rol{b}\t{%2, %0|%0, %2} 12184 rol{b}\t{%b2, %0|%0, %b2}" 12185 [(set_attr "type" "rotate") 12186 (set_attr "mode" "QI")]) 12187 12188(define_expand "rotrdi3" 12189 [(set (match_operand:DI 0 "nonimmediate_operand" "") 12190 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "") 12191 (match_operand:QI 2 "nonmemory_operand" ""))) 12192 (clobber (reg:CC 17))] 12193 "TARGET_64BIT" 12194 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;") 12195 12196(define_insn "*rotrdi3_1_one_bit_rex64" 12197 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") 12198 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0") 12199 (match_operand:QI 2 "const_int_1_operand" ""))) 12200 (clobber (reg:CC 17))] 12201 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands) 12202 && (TARGET_SHIFT1 || optimize_size)" 12203 "ror{q}\t%0" 12204 [(set_attr "type" "rotate") 12205 (set (attr "length") 12206 (if_then_else (match_operand:DI 0 "register_operand" "") 12207 (const_string "2") 12208 (const_string "*")))]) 12209 12210(define_insn "*rotrdi3_1_rex64" 12211 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") 12212 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") 12213 (match_operand:QI 2 "nonmemory_operand" "J,c"))) 12214 (clobber (reg:CC 17))] 12215 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)" 12216 "@ 12217 ror{q}\t{%2, %0|%0, %2} 12218 ror{q}\t{%b2, %0|%0, %b2}" 12219 [(set_attr "type" "rotate") 12220 (set_attr "mode" "DI")]) 12221 12222(define_expand "rotrsi3" 12223 [(set (match_operand:SI 0 "nonimmediate_operand" "") 12224 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "") 12225 (match_operand:QI 2 "nonmemory_operand" ""))) 12226 (clobber (reg:CC 17))] 12227 "" 12228 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;") 12229 12230(define_insn "*rotrsi3_1_one_bit" 12231 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 12232 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0") 12233 (match_operand:QI 2 "const_int_1_operand" ""))) 12234 (clobber (reg:CC 17))] 12235 "ix86_binary_operator_ok (ROTATERT, SImode, operands) 12236 && (TARGET_SHIFT1 || optimize_size)" 12237 "ror{l}\t%0" 12238 [(set_attr "type" "rotate") 12239 (set (attr "length") 12240 (if_then_else (match_operand:SI 0 "register_operand" "") 12241 (const_string "2") 12242 (const_string "*")))]) 12243 12244(define_insn "*rotrsi3_1_one_bit_zext" 12245 [(set (match_operand:DI 0 "register_operand" "=r") 12246 (zero_extend:DI 12247 (rotatert:SI (match_operand:SI 1 "register_operand" "0") 12248 (match_operand:QI 2 "const_int_1_operand" "")))) 12249 (clobber (reg:CC 17))] 12250 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands) 12251 && (TARGET_SHIFT1 || optimize_size)" 12252 "ror{l}\t%k0" 12253 [(set_attr "type" "rotate") 12254 (set (attr "length") 12255 (if_then_else (match_operand:SI 0 "register_operand" "") 12256 (const_string "2") 12257 (const_string "*")))]) 12258 12259(define_insn "*rotrsi3_1" 12260 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") 12261 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") 12262 (match_operand:QI 2 "nonmemory_operand" "I,c"))) 12263 (clobber (reg:CC 17))] 12264 "ix86_binary_operator_ok (ROTATERT, SImode, operands)" 12265 "@ 12266 ror{l}\t{%2, %0|%0, %2} 12267 ror{l}\t{%b2, %0|%0, %b2}" 12268 [(set_attr "type" "rotate") 12269 (set_attr "mode" "SI")]) 12270 12271(define_insn "*rotrsi3_1_zext" 12272 [(set (match_operand:DI 0 "register_operand" "=r,r") 12273 (zero_extend:DI 12274 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0") 12275 (match_operand:QI 2 "nonmemory_operand" "I,c")))) 12276 (clobber (reg:CC 17))] 12277 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)" 12278 "@ 12279 ror{l}\t{%2, %k0|%k0, %2} 12280 ror{l}\t{%b2, %k0|%k0, %b2}" 12281 [(set_attr "type" "rotate") 12282 (set_attr "mode" "SI")]) 12283 12284(define_expand "rotrhi3" 12285 [(set (match_operand:HI 0 "nonimmediate_operand" "") 12286 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "") 12287 (match_operand:QI 2 "nonmemory_operand" ""))) 12288 (clobber (reg:CC 17))] 12289 "TARGET_HIMODE_MATH" 12290 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;") 12291 12292(define_insn "*rotrhi3_one_bit" 12293 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 12294 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0") 12295 (match_operand:QI 2 "const_int_1_operand" ""))) 12296 (clobber (reg:CC 17))] 12297 "ix86_binary_operator_ok (ROTATERT, HImode, operands) 12298 && (TARGET_SHIFT1 || optimize_size)" 12299 "ror{w}\t%0" 12300 [(set_attr "type" "rotate") 12301 (set (attr "length") 12302 (if_then_else (match_operand 0 "register_operand" "") 12303 (const_string "2") 12304 (const_string "*")))]) 12305 12306(define_insn "*rotrhi3" 12307 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") 12308 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") 12309 (match_operand:QI 2 "nonmemory_operand" "I,c"))) 12310 (clobber (reg:CC 17))] 12311 "ix86_binary_operator_ok (ROTATERT, HImode, operands)" 12312 "@ 12313 ror{w}\t{%2, %0|%0, %2} 12314 ror{w}\t{%b2, %0|%0, %b2}" 12315 [(set_attr "type" "rotate") 12316 (set_attr "mode" "HI")]) 12317 12318(define_expand "rotrqi3" 12319 [(set (match_operand:QI 0 "nonimmediate_operand" "") 12320 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "") 12321 (match_operand:QI 2 "nonmemory_operand" ""))) 12322 (clobber (reg:CC 17))] 12323 "TARGET_QIMODE_MATH" 12324 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;") 12325 12326(define_insn "*rotrqi3_1_one_bit" 12327 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 12328 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0") 12329 (match_operand:QI 2 "const_int_1_operand" ""))) 12330 (clobber (reg:CC 17))] 12331 "ix86_binary_operator_ok (ROTATERT, QImode, operands) 12332 && (TARGET_SHIFT1 || optimize_size)" 12333 "ror{b}\t%0" 12334 [(set_attr "type" "rotate") 12335 (set (attr "length") 12336 (if_then_else (match_operand 0 "register_operand" "") 12337 (const_string "2") 12338 (const_string "*")))]) 12339 12340(define_insn "*rotrqi3_1_one_bit_slp" 12341 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) 12342 (rotatert:QI (match_dup 0) 12343 (match_operand:QI 1 "const_int_1_operand" ""))) 12344 (clobber (reg:CC 17))] 12345 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 12346 && (TARGET_SHIFT1 || optimize_size)" 12347 "ror{b}\t%0" 12348 [(set_attr "type" "rotate1") 12349 (set (attr "length") 12350 (if_then_else (match_operand 0 "register_operand" "") 12351 (const_string "2") 12352 (const_string "*")))]) 12353 12354(define_insn "*rotrqi3_1" 12355 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") 12356 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") 12357 (match_operand:QI 2 "nonmemory_operand" "I,c"))) 12358 (clobber (reg:CC 17))] 12359 "ix86_binary_operator_ok (ROTATERT, QImode, operands)" 12360 "@ 12361 ror{b}\t{%2, %0|%0, %2} 12362 ror{b}\t{%b2, %0|%0, %b2}" 12363 [(set_attr "type" "rotate") 12364 (set_attr "mode" "QI")]) 12365 12366(define_insn "*rotrqi3_1_slp" 12367 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) 12368 (rotatert:QI (match_dup 0) 12369 (match_operand:QI 1 "nonmemory_operand" "I,c"))) 12370 (clobber (reg:CC 17))] 12371 "(! TARGET_PARTIAL_REG_STALL || optimize_size) 12372 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 12373 "@ 12374 ror{b}\t{%1, %0|%0, %1} 12375 ror{b}\t{%b1, %0|%0, %b1}" 12376 [(set_attr "type" "rotate1") 12377 (set_attr "mode" "QI")]) 12378 12379;; Bit set / bit test instructions 12380 12381(define_expand "extv" 12382 [(set (match_operand:SI 0 "register_operand" "") 12383 (sign_extract:SI (match_operand:SI 1 "register_operand" "") 12384 (match_operand:SI 2 "immediate_operand" "") 12385 (match_operand:SI 3 "immediate_operand" "")))] 12386 "" 12387{ 12388 /* Handle extractions from %ah et al. */ 12389 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8) 12390 FAIL; 12391 12392 /* From mips.md: extract_bit_field doesn't verify that our source 12393 matches the predicate, so check it again here. */ 12394 if (! register_operand (operands[1], VOIDmode)) 12395 FAIL; 12396}) 12397 12398(define_expand "extzv" 12399 [(set (match_operand:SI 0 "register_operand" "") 12400 (zero_extract:SI (match_operand 1 "ext_register_operand" "") 12401 (match_operand:SI 2 "immediate_operand" "") 12402 (match_operand:SI 3 "immediate_operand" "")))] 12403 "" 12404{ 12405 /* Handle extractions from %ah et al. */ 12406 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8) 12407 FAIL; 12408 12409 /* From mips.md: extract_bit_field doesn't verify that our source 12410 matches the predicate, so check it again here. */ 12411 if (! register_operand (operands[1], VOIDmode)) 12412 FAIL; 12413}) 12414 12415(define_expand "insv" 12416 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "") 12417 (match_operand:SI 1 "immediate_operand" "") 12418 (match_operand:SI 2 "immediate_operand" "")) 12419 (match_operand:SI 3 "register_operand" ""))] 12420 "" 12421{ 12422 /* Handle extractions from %ah et al. */ 12423 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8) 12424 FAIL; 12425 12426 /* From mips.md: insert_bit_field doesn't verify that our source 12427 matches the predicate, so check it again here. */ 12428 if (! register_operand (operands[0], VOIDmode)) 12429 FAIL; 12430}) 12431 12432;; %%% bts, btr, btc, bt. 12433 12434;; Store-flag instructions. 12435 12436;; For all sCOND expanders, also expand the compare or test insn that 12437;; generates cc0. Generate an equality comparison if `seq' or `sne'. 12438 12439;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way 12440;; to avoid partial register stalls. Otherwise do things the setcc+movzx 12441;; way, which can later delete the movzx if only QImode is needed. 12442 12443(define_expand "seq" 12444 [(set (match_operand:QI 0 "register_operand" "") 12445 (eq:QI (reg:CC 17) (const_int 0)))] 12446 "" 12447 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;") 12448 12449(define_expand "sne" 12450 [(set (match_operand:QI 0 "register_operand" "") 12451 (ne:QI (reg:CC 17) (const_int 0)))] 12452 "" 12453 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;") 12454 12455(define_expand "sgt" 12456 [(set (match_operand:QI 0 "register_operand" "") 12457 (gt:QI (reg:CC 17) (const_int 0)))] 12458 "" 12459 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;") 12460 12461(define_expand "sgtu" 12462 [(set (match_operand:QI 0 "register_operand" "") 12463 (gtu:QI (reg:CC 17) (const_int 0)))] 12464 "" 12465 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;") 12466 12467(define_expand "slt" 12468 [(set (match_operand:QI 0 "register_operand" "") 12469 (lt:QI (reg:CC 17) (const_int 0)))] 12470 "" 12471 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;") 12472 12473(define_expand "sltu" 12474 [(set (match_operand:QI 0 "register_operand" "") 12475 (ltu:QI (reg:CC 17) (const_int 0)))] 12476 "" 12477 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;") 12478 12479(define_expand "sge" 12480 [(set (match_operand:QI 0 "register_operand" "") 12481 (ge:QI (reg:CC 17) (const_int 0)))] 12482 "" 12483 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;") 12484 12485(define_expand "sgeu" 12486 [(set (match_operand:QI 0 "register_operand" "") 12487 (geu:QI (reg:CC 17) (const_int 0)))] 12488 "" 12489 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;") 12490 12491(define_expand "sle" 12492 [(set (match_operand:QI 0 "register_operand" "") 12493 (le:QI (reg:CC 17) (const_int 0)))] 12494 "" 12495 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;") 12496 12497(define_expand "sleu" 12498 [(set (match_operand:QI 0 "register_operand" "") 12499 (leu:QI (reg:CC 17) (const_int 0)))] 12500 "" 12501 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;") 12502 12503(define_expand "sunordered" 12504 [(set (match_operand:QI 0 "register_operand" "") 12505 (unordered:QI (reg:CC 17) (const_int 0)))] 12506 "TARGET_80387 || TARGET_SSE" 12507 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;") 12508 12509(define_expand "sordered" 12510 [(set (match_operand:QI 0 "register_operand" "") 12511 (ordered:QI (reg:CC 17) (const_int 0)))] 12512 "TARGET_80387" 12513 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;") 12514 12515(define_expand "suneq" 12516 [(set (match_operand:QI 0 "register_operand" "") 12517 (uneq:QI (reg:CC 17) (const_int 0)))] 12518 "TARGET_80387 || TARGET_SSE" 12519 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;") 12520 12521(define_expand "sunge" 12522 [(set (match_operand:QI 0 "register_operand" "") 12523 (unge:QI (reg:CC 17) (const_int 0)))] 12524 "TARGET_80387 || TARGET_SSE" 12525 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;") 12526 12527(define_expand "sungt" 12528 [(set (match_operand:QI 0 "register_operand" "") 12529 (ungt:QI (reg:CC 17) (const_int 0)))] 12530 "TARGET_80387 || TARGET_SSE" 12531 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;") 12532 12533(define_expand "sunle" 12534 [(set (match_operand:QI 0 "register_operand" "") 12535 (unle:QI (reg:CC 17) (const_int 0)))] 12536 "TARGET_80387 || TARGET_SSE" 12537 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;") 12538 12539(define_expand "sunlt" 12540 [(set (match_operand:QI 0 "register_operand" "") 12541 (unlt:QI (reg:CC 17) (const_int 0)))] 12542 "TARGET_80387 || TARGET_SSE" 12543 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;") 12544 12545(define_expand "sltgt" 12546 [(set (match_operand:QI 0 "register_operand" "") 12547 (ltgt:QI (reg:CC 17) (const_int 0)))] 12548 "TARGET_80387 || TARGET_SSE" 12549 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;") 12550 12551(define_insn "*setcc_1" 12552 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") 12553 (match_operator:QI 1 "ix86_comparison_operator" 12554 [(reg 17) (const_int 0)]))] 12555 "" 12556 "set%C1\t%0" 12557 [(set_attr "type" "setcc") 12558 (set_attr "mode" "QI")]) 12559 12560(define_insn "setcc_2" 12561 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) 12562 (match_operator:QI 1 "ix86_comparison_operator" 12563 [(reg 17) (const_int 0)]))] 12564 "" 12565 "set%C1\t%0" 12566 [(set_attr "type" "setcc") 12567 (set_attr "mode" "QI")]) 12568 12569;; In general it is not safe to assume too much about CCmode registers, 12570;; so simplify-rtx stops when it sees a second one. Under certain 12571;; conditions this is safe on x86, so help combine not create 12572;; 12573;; seta %al 12574;; testb %al, %al 12575;; sete %al 12576 12577(define_split 12578 [(set (match_operand:QI 0 "nonimmediate_operand" "") 12579 (ne:QI (match_operator 1 "ix86_comparison_operator" 12580 [(reg 17) (const_int 0)]) 12581 (const_int 0)))] 12582 "" 12583 [(set (match_dup 0) (match_dup 1))] 12584{ 12585 PUT_MODE (operands[1], QImode); 12586}) 12587 12588(define_split 12589 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) 12590 (ne:QI (match_operator 1 "ix86_comparison_operator" 12591 [(reg 17) (const_int 0)]) 12592 (const_int 0)))] 12593 "" 12594 [(set (match_dup 0) (match_dup 1))] 12595{ 12596 PUT_MODE (operands[1], QImode); 12597}) 12598 12599(define_split 12600 [(set (match_operand:QI 0 "nonimmediate_operand" "") 12601 (eq:QI (match_operator 1 "ix86_comparison_operator" 12602 [(reg 17) (const_int 0)]) 12603 (const_int 0)))] 12604 "" 12605 [(set (match_dup 0) (match_dup 1))] 12606{ 12607 rtx new_op1 = copy_rtx (operands[1]); 12608 operands[1] = new_op1; 12609 PUT_MODE (new_op1, QImode); 12610 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1), 12611 GET_MODE (XEXP (new_op1, 0)))); 12612 12613 /* Make sure that (a) the CCmode we have for the flags is strong 12614 enough for the reversed compare or (b) we have a valid FP compare. */ 12615 if (! ix86_comparison_operator (new_op1, VOIDmode)) 12616 FAIL; 12617}) 12618 12619(define_split 12620 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) 12621 (eq:QI (match_operator 1 "ix86_comparison_operator" 12622 [(reg 17) (const_int 0)]) 12623 (const_int 0)))] 12624 "" 12625 [(set (match_dup 0) (match_dup 1))] 12626{ 12627 rtx new_op1 = copy_rtx (operands[1]); 12628 operands[1] = new_op1; 12629 PUT_MODE (new_op1, QImode); 12630 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1), 12631 GET_MODE (XEXP (new_op1, 0)))); 12632 12633 /* Make sure that (a) the CCmode we have for the flags is strong 12634 enough for the reversed compare or (b) we have a valid FP compare. */ 12635 if (! ix86_comparison_operator (new_op1, VOIDmode)) 12636 FAIL; 12637}) 12638 12639;; The SSE store flag instructions saves 0 or 0xffffffff to the result. 12640;; subsequent logical operations are used to imitate conditional moves. 12641;; 0xffffffff is NaN, but not in normalized form, so we can't represent 12642;; it directly. Futher holding this value in pseudo register might bring 12643;; problem in implicit normalization in spill code. 12644;; So we don't define FLOAT_STORE_FLAG_VALUE and create these 12645;; instructions after reload by splitting the conditional move patterns. 12646 12647(define_insn "*sse_setccsf" 12648 [(set (match_operand:SF 0 "register_operand" "=x") 12649 (match_operator:SF 1 "sse_comparison_operator" 12650 [(match_operand:SF 2 "register_operand" "0") 12651 (match_operand:SF 3 "nonimmediate_operand" "xm")]))] 12652 "TARGET_SSE && reload_completed" 12653 "cmp%D1ss\t{%3, %0|%0, %3}" 12654 [(set_attr "type" "ssecmp") 12655 (set_attr "mode" "SF")]) 12656 12657(define_insn "*sse_setccdf" 12658 [(set (match_operand:DF 0 "register_operand" "=Y") 12659 (match_operator:DF 1 "sse_comparison_operator" 12660 [(match_operand:DF 2 "register_operand" "0") 12661 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))] 12662 "TARGET_SSE2 && reload_completed" 12663 "cmp%D1sd\t{%3, %0|%0, %3}" 12664 [(set_attr "type" "ssecmp") 12665 (set_attr "mode" "DF")]) 12666 12667;; Basic conditional jump instructions. 12668;; We ignore the overflow flag for signed branch instructions. 12669 12670;; For all bCOND expanders, also expand the compare or test insn that 12671;; generates reg 17. Generate an equality comparison if `beq' or `bne'. 12672 12673(define_expand "beq" 12674 [(set (pc) 12675 (if_then_else (match_dup 1) 12676 (label_ref (match_operand 0 "" "")) 12677 (pc)))] 12678 "" 12679 "ix86_expand_branch (EQ, operands[0]); DONE;") 12680 12681(define_expand "bne" 12682 [(set (pc) 12683 (if_then_else (match_dup 1) 12684 (label_ref (match_operand 0 "" "")) 12685 (pc)))] 12686 "" 12687 "ix86_expand_branch (NE, operands[0]); DONE;") 12688 12689(define_expand "bgt" 12690 [(set (pc) 12691 (if_then_else (match_dup 1) 12692 (label_ref (match_operand 0 "" "")) 12693 (pc)))] 12694 "" 12695 "ix86_expand_branch (GT, operands[0]); DONE;") 12696 12697(define_expand "bgtu" 12698 [(set (pc) 12699 (if_then_else (match_dup 1) 12700 (label_ref (match_operand 0 "" "")) 12701 (pc)))] 12702 "" 12703 "ix86_expand_branch (GTU, operands[0]); DONE;") 12704 12705(define_expand "blt" 12706 [(set (pc) 12707 (if_then_else (match_dup 1) 12708 (label_ref (match_operand 0 "" "")) 12709 (pc)))] 12710 "" 12711 "ix86_expand_branch (LT, operands[0]); DONE;") 12712 12713(define_expand "bltu" 12714 [(set (pc) 12715 (if_then_else (match_dup 1) 12716 (label_ref (match_operand 0 "" "")) 12717 (pc)))] 12718 "" 12719 "ix86_expand_branch (LTU, operands[0]); DONE;") 12720 12721(define_expand "bge" 12722 [(set (pc) 12723 (if_then_else (match_dup 1) 12724 (label_ref (match_operand 0 "" "")) 12725 (pc)))] 12726 "" 12727 "ix86_expand_branch (GE, operands[0]); DONE;") 12728 12729(define_expand "bgeu" 12730 [(set (pc) 12731 (if_then_else (match_dup 1) 12732 (label_ref (match_operand 0 "" "")) 12733 (pc)))] 12734 "" 12735 "ix86_expand_branch (GEU, operands[0]); DONE;") 12736 12737(define_expand "ble" 12738 [(set (pc) 12739 (if_then_else (match_dup 1) 12740 (label_ref (match_operand 0 "" "")) 12741 (pc)))] 12742 "" 12743 "ix86_expand_branch (LE, operands[0]); DONE;") 12744 12745(define_expand "bleu" 12746 [(set (pc) 12747 (if_then_else (match_dup 1) 12748 (label_ref (match_operand 0 "" "")) 12749 (pc)))] 12750 "" 12751 "ix86_expand_branch (LEU, operands[0]); DONE;") 12752 12753(define_expand "bunordered" 12754 [(set (pc) 12755 (if_then_else (match_dup 1) 12756 (label_ref (match_operand 0 "" "")) 12757 (pc)))] 12758 "TARGET_80387 || TARGET_SSE" 12759 "ix86_expand_branch (UNORDERED, operands[0]); DONE;") 12760 12761(define_expand "bordered" 12762 [(set (pc) 12763 (if_then_else (match_dup 1) 12764 (label_ref (match_operand 0 "" "")) 12765 (pc)))] 12766 "TARGET_80387 || TARGET_SSE" 12767 "ix86_expand_branch (ORDERED, operands[0]); DONE;") 12768 12769(define_expand "buneq" 12770 [(set (pc) 12771 (if_then_else (match_dup 1) 12772 (label_ref (match_operand 0 "" "")) 12773 (pc)))] 12774 "TARGET_80387 || TARGET_SSE" 12775 "ix86_expand_branch (UNEQ, operands[0]); DONE;") 12776 12777(define_expand "bunge" 12778 [(set (pc) 12779 (if_then_else (match_dup 1) 12780 (label_ref (match_operand 0 "" "")) 12781 (pc)))] 12782 "TARGET_80387 || TARGET_SSE" 12783 "ix86_expand_branch (UNGE, operands[0]); DONE;") 12784 12785(define_expand "bungt" 12786 [(set (pc) 12787 (if_then_else (match_dup 1) 12788 (label_ref (match_operand 0 "" "")) 12789 (pc)))] 12790 "TARGET_80387 || TARGET_SSE" 12791 "ix86_expand_branch (UNGT, operands[0]); DONE;") 12792 12793(define_expand "bunle" 12794 [(set (pc) 12795 (if_then_else (match_dup 1) 12796 (label_ref (match_operand 0 "" "")) 12797 (pc)))] 12798 "TARGET_80387 || TARGET_SSE" 12799 "ix86_expand_branch (UNLE, operands[0]); DONE;") 12800 12801(define_expand "bunlt" 12802 [(set (pc) 12803 (if_then_else (match_dup 1) 12804 (label_ref (match_operand 0 "" "")) 12805 (pc)))] 12806 "TARGET_80387 || TARGET_SSE" 12807 "ix86_expand_branch (UNLT, operands[0]); DONE;") 12808 12809(define_expand "bltgt" 12810 [(set (pc) 12811 (if_then_else (match_dup 1) 12812 (label_ref (match_operand 0 "" "")) 12813 (pc)))] 12814 "TARGET_80387 || TARGET_SSE" 12815 "ix86_expand_branch (LTGT, operands[0]); DONE;") 12816 12817(define_insn "*jcc_1" 12818 [(set (pc) 12819 (if_then_else (match_operator 1 "ix86_comparison_operator" 12820 [(reg 17) (const_int 0)]) 12821 (label_ref (match_operand 0 "" "")) 12822 (pc)))] 12823 "" 12824 "%+j%C1\t%l0" 12825 [(set_attr "type" "ibr") 12826 (set_attr "modrm" "0") 12827 (set (attr "length") 12828 (if_then_else (and (ge (minus (match_dup 0) (pc)) 12829 (const_int -126)) 12830 (lt (minus (match_dup 0) (pc)) 12831 (const_int 128))) 12832 (const_int 2) 12833 (const_int 6)))]) 12834 12835(define_insn "*jcc_2" 12836 [(set (pc) 12837 (if_then_else (match_operator 1 "ix86_comparison_operator" 12838 [(reg 17) (const_int 0)]) 12839 (pc) 12840 (label_ref (match_operand 0 "" ""))))] 12841 "" 12842 "%+j%c1\t%l0" 12843 [(set_attr "type" "ibr") 12844 (set_attr "modrm" "0") 12845 (set (attr "length") 12846 (if_then_else (and (ge (minus (match_dup 0) (pc)) 12847 (const_int -126)) 12848 (lt (minus (match_dup 0) (pc)) 12849 (const_int 128))) 12850 (const_int 2) 12851 (const_int 6)))]) 12852 12853;; In general it is not safe to assume too much about CCmode registers, 12854;; so simplify-rtx stops when it sees a second one. Under certain 12855;; conditions this is safe on x86, so help combine not create 12856;; 12857;; seta %al 12858;; testb %al, %al 12859;; je Lfoo 12860 12861(define_split 12862 [(set (pc) 12863 (if_then_else (ne (match_operator 0 "ix86_comparison_operator" 12864 [(reg 17) (const_int 0)]) 12865 (const_int 0)) 12866 (label_ref (match_operand 1 "" "")) 12867 (pc)))] 12868 "" 12869 [(set (pc) 12870 (if_then_else (match_dup 0) 12871 (label_ref (match_dup 1)) 12872 (pc)))] 12873{ 12874 PUT_MODE (operands[0], VOIDmode); 12875}) 12876 12877(define_split 12878 [(set (pc) 12879 (if_then_else (eq (match_operator 0 "ix86_comparison_operator" 12880 [(reg 17) (const_int 0)]) 12881 (const_int 0)) 12882 (label_ref (match_operand 1 "" "")) 12883 (pc)))] 12884 "" 12885 [(set (pc) 12886 (if_then_else (match_dup 0) 12887 (label_ref (match_dup 1)) 12888 (pc)))] 12889{ 12890 rtx new_op0 = copy_rtx (operands[0]); 12891 operands[0] = new_op0; 12892 PUT_MODE (new_op0, VOIDmode); 12893 PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0), 12894 GET_MODE (XEXP (new_op0, 0)))); 12895 12896 /* Make sure that (a) the CCmode we have for the flags is strong 12897 enough for the reversed compare or (b) we have a valid FP compare. */ 12898 if (! ix86_comparison_operator (new_op0, VOIDmode)) 12899 FAIL; 12900}) 12901 12902;; Define combination compare-and-branch fp compare instructions to use 12903;; during early optimization. Splitting the operation apart early makes 12904;; for bad code when we want to reverse the operation. 12905 12906(define_insn "*fp_jcc_1" 12907 [(set (pc) 12908 (if_then_else (match_operator 0 "comparison_operator" 12909 [(match_operand 1 "register_operand" "f") 12910 (match_operand 2 "register_operand" "f")]) 12911 (label_ref (match_operand 3 "" "")) 12912 (pc))) 12913 (clobber (reg:CCFP 18)) 12914 (clobber (reg:CCFP 17))] 12915 "TARGET_CMOVE && TARGET_80387 12916 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1])) 12917 && FLOAT_MODE_P (GET_MODE (operands[1])) 12918 && GET_MODE (operands[1]) == GET_MODE (operands[2]) 12919 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" 12920 "#") 12921 12922(define_insn "*fp_jcc_1_sse" 12923 [(set (pc) 12924 (if_then_else (match_operator 0 "comparison_operator" 12925 [(match_operand 1 "register_operand" "f#x,x#f") 12926 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")]) 12927 (label_ref (match_operand 3 "" "")) 12928 (pc))) 12929 (clobber (reg:CCFP 18)) 12930 (clobber (reg:CCFP 17))] 12931 "TARGET_80387 12932 && SSE_FLOAT_MODE_P (GET_MODE (operands[1])) 12933 && GET_MODE (operands[1]) == GET_MODE (operands[2]) 12934 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" 12935 "#") 12936 12937(define_insn "*fp_jcc_1_sse_only" 12938 [(set (pc) 12939 (if_then_else (match_operator 0 "comparison_operator" 12940 [(match_operand 1 "register_operand" "x") 12941 (match_operand 2 "nonimmediate_operand" "xm")]) 12942 (label_ref (match_operand 3 "" "")) 12943 (pc))) 12944 (clobber (reg:CCFP 18)) 12945 (clobber (reg:CCFP 17))] 12946 "SSE_FLOAT_MODE_P (GET_MODE (operands[1])) 12947 && GET_MODE (operands[1]) == GET_MODE (operands[2]) 12948 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" 12949 "#") 12950 12951(define_insn "*fp_jcc_2" 12952 [(set (pc) 12953 (if_then_else (match_operator 0 "comparison_operator" 12954 [(match_operand 1 "register_operand" "f") 12955 (match_operand 2 "register_operand" "f")]) 12956 (pc) 12957 (label_ref (match_operand 3 "" "")))) 12958 (clobber (reg:CCFP 18)) 12959 (clobber (reg:CCFP 17))] 12960 "TARGET_CMOVE && TARGET_80387 12961 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1])) 12962 && FLOAT_MODE_P (GET_MODE (operands[1])) 12963 && GET_MODE (operands[1]) == GET_MODE (operands[2]) 12964 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" 12965 "#") 12966 12967(define_insn "*fp_jcc_2_sse" 12968 [(set (pc) 12969 (if_then_else (match_operator 0 "comparison_operator" 12970 [(match_operand 1 "register_operand" "f#x,x#f") 12971 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")]) 12972 (pc) 12973 (label_ref (match_operand 3 "" "")))) 12974 (clobber (reg:CCFP 18)) 12975 (clobber (reg:CCFP 17))] 12976 "TARGET_80387 12977 && SSE_FLOAT_MODE_P (GET_MODE (operands[1])) 12978 && GET_MODE (operands[1]) == GET_MODE (operands[2]) 12979 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" 12980 "#") 12981 12982(define_insn "*fp_jcc_2_sse_only" 12983 [(set (pc) 12984 (if_then_else (match_operator 0 "comparison_operator" 12985 [(match_operand 1 "register_operand" "x") 12986 (match_operand 2 "nonimmediate_operand" "xm")]) 12987 (pc) 12988 (label_ref (match_operand 3 "" "")))) 12989 (clobber (reg:CCFP 18)) 12990 (clobber (reg:CCFP 17))] 12991 "SSE_FLOAT_MODE_P (GET_MODE (operands[1])) 12992 && GET_MODE (operands[1]) == GET_MODE (operands[2]) 12993 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" 12994 "#") 12995 12996(define_insn "*fp_jcc_3" 12997 [(set (pc) 12998 (if_then_else (match_operator 0 "comparison_operator" 12999 [(match_operand 1 "register_operand" "f") 13000 (match_operand 2 "nonimmediate_operand" "fm")]) 13001 (label_ref (match_operand 3 "" "")) 13002 (pc))) 13003 (clobber (reg:CCFP 18)) 13004 (clobber (reg:CCFP 17)) 13005 (clobber (match_scratch:HI 4 "=a"))] 13006 "TARGET_80387 13007 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode) 13008 && GET_MODE (operands[1]) == GET_MODE (operands[2]) 13009 && !ix86_use_fcomi_compare (GET_CODE (operands[0])) 13010 && SELECT_CC_MODE (GET_CODE (operands[0]), 13011 operands[1], operands[2]) == CCFPmode 13012 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" 13013 "#") 13014 13015(define_insn "*fp_jcc_4" 13016 [(set (pc) 13017 (if_then_else (match_operator 0 "comparison_operator" 13018 [(match_operand 1 "register_operand" "f") 13019 (match_operand 2 "nonimmediate_operand" "fm")]) 13020 (pc) 13021 (label_ref (match_operand 3 "" "")))) 13022 (clobber (reg:CCFP 18)) 13023 (clobber (reg:CCFP 17)) 13024 (clobber (match_scratch:HI 4 "=a"))] 13025 "TARGET_80387 13026 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode) 13027 && GET_MODE (operands[1]) == GET_MODE (operands[2]) 13028 && !ix86_use_fcomi_compare (GET_CODE (operands[0])) 13029 && SELECT_CC_MODE (GET_CODE (operands[0]), 13030 operands[1], operands[2]) == CCFPmode 13031 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" 13032 "#") 13033 13034(define_insn "*fp_jcc_5" 13035 [(set (pc) 13036 (if_then_else (match_operator 0 "comparison_operator" 13037 [(match_operand 1 "register_operand" "f") 13038 (match_operand 2 "register_operand" "f")]) 13039 (label_ref (match_operand 3 "" "")) 13040 (pc))) 13041 (clobber (reg:CCFP 18)) 13042 (clobber (reg:CCFP 17)) 13043 (clobber (match_scratch:HI 4 "=a"))] 13044 "TARGET_80387 13045 && FLOAT_MODE_P (GET_MODE (operands[1])) 13046 && GET_MODE (operands[1]) == GET_MODE (operands[2]) 13047 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" 13048 "#") 13049 13050(define_insn "*fp_jcc_6" 13051 [(set (pc) 13052 (if_then_else (match_operator 0 "comparison_operator" 13053 [(match_operand 1 "register_operand" "f") 13054 (match_operand 2 "register_operand" "f")]) 13055 (pc) 13056 (label_ref (match_operand 3 "" "")))) 13057 (clobber (reg:CCFP 18)) 13058 (clobber (reg:CCFP 17)) 13059 (clobber (match_scratch:HI 4 "=a"))] 13060 "TARGET_80387 13061 && FLOAT_MODE_P (GET_MODE (operands[1])) 13062 && GET_MODE (operands[1]) == GET_MODE (operands[2]) 13063 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" 13064 "#") 13065 13066(define_split 13067 [(set (pc) 13068 (if_then_else (match_operator 0 "comparison_operator" 13069 [(match_operand 1 "register_operand" "") 13070 (match_operand 2 "nonimmediate_operand" "")]) 13071 (match_operand 3 "" "") 13072 (match_operand 4 "" ""))) 13073 (clobber (reg:CCFP 18)) 13074 (clobber (reg:CCFP 17))] 13075 "reload_completed" 13076 [(const_int 0)] 13077{ 13078 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2], 13079 operands[3], operands[4], NULL_RTX); 13080 DONE; 13081}) 13082 13083(define_split 13084 [(set (pc) 13085 (if_then_else (match_operator 0 "comparison_operator" 13086 [(match_operand 1 "register_operand" "") 13087 (match_operand 2 "nonimmediate_operand" "")]) 13088 (match_operand 3 "" "") 13089 (match_operand 4 "" ""))) 13090 (clobber (reg:CCFP 18)) 13091 (clobber (reg:CCFP 17)) 13092 (clobber (match_scratch:HI 5 "=a"))] 13093 "reload_completed" 13094 [(set (pc) 13095 (if_then_else (match_dup 6) 13096 (match_dup 3) 13097 (match_dup 4)))] 13098{ 13099 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2], 13100 operands[3], operands[4], operands[5]); 13101 DONE; 13102}) 13103 13104;; Unconditional and other jump instructions 13105 13106(define_insn "jump" 13107 [(set (pc) 13108 (label_ref (match_operand 0 "" "")))] 13109 "" 13110 "jmp\t%l0" 13111 [(set_attr "type" "ibr") 13112 (set (attr "length") 13113 (if_then_else (and (ge (minus (match_dup 0) (pc)) 13114 (const_int -126)) 13115 (lt (minus (match_dup 0) (pc)) 13116 (const_int 128))) 13117 (const_int 2) 13118 (const_int 5))) 13119 (set_attr "modrm" "0")]) 13120 13121(define_expand "indirect_jump" 13122 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))] 13123 "" 13124 "") 13125 13126(define_insn "*indirect_jump" 13127 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))] 13128 "!TARGET_64BIT" 13129 "jmp\t%A0" 13130 [(set_attr "type" "ibr") 13131 (set_attr "length_immediate" "0")]) 13132 13133(define_insn "*indirect_jump_rtx64" 13134 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))] 13135 "TARGET_64BIT" 13136 "jmp\t%A0" 13137 [(set_attr "type" "ibr") 13138 (set_attr "length_immediate" "0")]) 13139 13140(define_expand "tablejump" 13141 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm")) 13142 (use (label_ref (match_operand 1 "" "")))])] 13143 "" 13144{ 13145 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit) 13146 relative. Convert the relative address to an absolute address. */ 13147 if (flag_pic) 13148 { 13149 rtx op0, op1; 13150 enum rtx_code code; 13151 13152 if (TARGET_64BIT) 13153 { 13154 code = PLUS; 13155 op0 = operands[0]; 13156 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]); 13157 } 13158 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA) 13159 { 13160 code = PLUS; 13161 op0 = operands[0]; 13162 op1 = pic_offset_table_rtx; 13163 } 13164 else 13165 { 13166 code = MINUS; 13167 op0 = pic_offset_table_rtx; 13168 op1 = operands[0]; 13169 } 13170 13171 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0, 13172 OPTAB_DIRECT); 13173 } 13174}) 13175 13176(define_insn "*tablejump_1" 13177 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm")) 13178 (use (label_ref (match_operand 1 "" "")))] 13179 "!TARGET_64BIT" 13180 "jmp\t%A0" 13181 [(set_attr "type" "ibr") 13182 (set_attr "length_immediate" "0")]) 13183 13184(define_insn "*tablejump_1_rtx64" 13185 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm")) 13186 (use (label_ref (match_operand 1 "" "")))] 13187 "TARGET_64BIT" 13188 "jmp\t%A0" 13189 [(set_attr "type" "ibr") 13190 (set_attr "length_immediate" "0")]) 13191 13192;; Loop instruction 13193;; 13194;; This is all complicated by the fact that since this is a jump insn 13195;; we must handle our own reloads. 13196 13197(define_expand "doloop_end" 13198 [(use (match_operand 0 "" "")) ; loop pseudo 13199 (use (match_operand 1 "" "")) ; iterations; zero if unknown 13200 (use (match_operand 2 "" "")) ; max iterations 13201 (use (match_operand 3 "" "")) ; loop level 13202 (use (match_operand 4 "" ""))] ; label 13203 "!TARGET_64BIT && TARGET_USE_LOOP" 13204 " 13205{ 13206 /* Only use cloop on innermost loops. */ 13207 if (INTVAL (operands[3]) > 1) 13208 FAIL; 13209 if (GET_MODE (operands[0]) != SImode) 13210 FAIL; 13211 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0], 13212 operands[0])); 13213 DONE; 13214}") 13215 13216(define_insn "doloop_end_internal" 13217 [(set (pc) 13218 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r") 13219 (const_int 1)) 13220 (label_ref (match_operand 0 "" "")) 13221 (pc))) 13222 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r") 13223 (plus:SI (match_dup 1) 13224 (const_int -1))) 13225 (clobber (match_scratch:SI 3 "=X,X,r")) 13226 (clobber (reg:CC 17))] 13227 "!TARGET_64BIT && TARGET_USE_LOOP" 13228{ 13229 if (which_alternative != 0) 13230 return "#"; 13231 if (get_attr_length (insn) == 2) 13232 return "%+loop\t%l0"; 13233 else 13234 return "dec{l}\t%1\;%+jne\t%l0"; 13235} 13236 [(set_attr "ppro_uops" "many") 13237 (set (attr "length") 13238 (if_then_else (and (eq_attr "alternative" "0") 13239 (and (ge (minus (match_dup 0) (pc)) 13240 (const_int -126)) 13241 (lt (minus (match_dup 0) (pc)) 13242 (const_int 128)))) 13243 (const_int 2) 13244 (const_int 16))) 13245 ;; We don't know the type before shorten branches. Optimistically expect 13246 ;; the loop instruction to match. 13247 (set (attr "type") (const_string "ibr"))]) 13248 13249(define_split 13250 [(set (pc) 13251 (if_then_else (ne (match_operand:SI 1 "register_operand" "") 13252 (const_int 1)) 13253 (match_operand 0 "" "") 13254 (pc))) 13255 (set (match_dup 1) 13256 (plus:SI (match_dup 1) 13257 (const_int -1))) 13258 (clobber (match_scratch:SI 2 "")) 13259 (clobber (reg:CC 17))] 13260 "!TARGET_64BIT && TARGET_USE_LOOP 13261 && reload_completed 13262 && REGNO (operands[1]) != 2" 13263 [(parallel [(set (reg:CCZ 17) 13264 (compare:CCZ (plus:SI (match_dup 1) (const_int -1)) 13265 (const_int 0))) 13266 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))]) 13267 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0)) 13268 (match_dup 0) 13269 (pc)))] 13270 "") 13271 13272(define_split 13273 [(set (pc) 13274 (if_then_else (ne (match_operand:SI 1 "register_operand" "") 13275 (const_int 1)) 13276 (match_operand 0 "" "") 13277 (pc))) 13278 (set (match_operand:SI 2 "nonimmediate_operand" "") 13279 (plus:SI (match_dup 1) 13280 (const_int -1))) 13281 (clobber (match_scratch:SI 3 "")) 13282 (clobber (reg:CC 17))] 13283 "!TARGET_64BIT && TARGET_USE_LOOP 13284 && reload_completed 13285 && (! REG_P (operands[2]) 13286 || ! rtx_equal_p (operands[1], operands[2]))" 13287 [(set (match_dup 3) (match_dup 1)) 13288 (parallel [(set (reg:CCZ 17) 13289 (compare:CCZ (plus:SI (match_dup 3) (const_int -1)) 13290 (const_int 0))) 13291 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) 13292 (set (match_dup 2) (match_dup 3)) 13293 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0)) 13294 (match_dup 0) 13295 (pc)))] 13296 "") 13297 13298;; Convert setcc + movzbl to xor + setcc if operands don't overlap. 13299 13300(define_peephole2 13301 [(set (reg 17) (match_operand 0 "" "")) 13302 (set (match_operand:QI 1 "register_operand" "") 13303 (match_operator:QI 2 "ix86_comparison_operator" 13304 [(reg 17) (const_int 0)])) 13305 (set (match_operand 3 "q_regs_operand" "") 13306 (zero_extend (match_dup 1)))] 13307 "(peep2_reg_dead_p (3, operands[1]) 13308 || operands_match_p (operands[1], operands[3])) 13309 && ! reg_overlap_mentioned_p (operands[3], operands[0])" 13310 [(set (match_dup 4) (match_dup 0)) 13311 (set (strict_low_part (match_dup 5)) 13312 (match_dup 2))] 13313{ 13314 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17); 13315 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3])); 13316 ix86_expand_clear (operands[3]); 13317}) 13318 13319;; Similar, but match zero_extendhisi2_and, which adds a clobber. 13320 13321(define_peephole2 13322 [(set (reg 17) (match_operand 0 "" "")) 13323 (set (match_operand:QI 1 "register_operand" "") 13324 (match_operator:QI 2 "ix86_comparison_operator" 13325 [(reg 17) (const_int 0)])) 13326 (parallel [(set (match_operand 3 "q_regs_operand" "") 13327 (zero_extend (match_dup 1))) 13328 (clobber (reg:CC 17))])] 13329 "(peep2_reg_dead_p (3, operands[1]) 13330 || operands_match_p (operands[1], operands[3])) 13331 && ! reg_overlap_mentioned_p (operands[3], operands[0])" 13332 [(set (match_dup 4) (match_dup 0)) 13333 (set (strict_low_part (match_dup 5)) 13334 (match_dup 2))] 13335{ 13336 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17); 13337 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3])); 13338 ix86_expand_clear (operands[3]); 13339}) 13340 13341;; Call instructions. 13342 13343;; The predicates normally associated with named expanders are not properly 13344;; checked for calls. This is a bug in the generic code, but it isn't that 13345;; easy to fix. Ignore it for now and be prepared to fix things up. 13346 13347;; Call subroutine returning no value. 13348 13349(define_expand "call_pop" 13350 [(parallel [(call (match_operand:QI 0 "" "") 13351 (match_operand:SI 1 "" "")) 13352 (set (reg:SI 7) 13353 (plus:SI (reg:SI 7) 13354 (match_operand:SI 3 "" "")))])] 13355 "!TARGET_64BIT" 13356{ 13357 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3]); 13358 DONE; 13359}) 13360 13361(define_insn "*call_pop_0" 13362 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" "")) 13363 (match_operand:SI 1 "" "")) 13364 (set (reg:SI 7) (plus:SI (reg:SI 7) 13365 (match_operand:SI 2 "immediate_operand" "")))] 13366 "!TARGET_64BIT" 13367{ 13368 if (SIBLING_CALL_P (insn)) 13369 return "jmp\t%P0"; 13370 else 13371 return "call\t%P0"; 13372} 13373 [(set_attr "type" "call")]) 13374 13375(define_insn "*call_pop_1" 13376 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm")) 13377 (match_operand:SI 1 "" "")) 13378 (set (reg:SI 7) (plus:SI (reg:SI 7) 13379 (match_operand:SI 2 "immediate_operand" "i")))] 13380 "!TARGET_64BIT" 13381{ 13382 if (constant_call_address_operand (operands[0], Pmode)) 13383 { 13384 if (SIBLING_CALL_P (insn)) 13385 return "jmp\t%P0"; 13386 else 13387 return "call\t%P0"; 13388 } 13389 if (SIBLING_CALL_P (insn)) 13390 return "jmp\t%A0"; 13391 else 13392 return "call\t%A0"; 13393} 13394 [(set_attr "type" "call")]) 13395 13396(define_expand "call" 13397 [(call (match_operand:QI 0 "" "") 13398 (match_operand 1 "" "")) 13399 (use (match_operand 2 "" ""))] 13400 "" 13401{ 13402 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL); 13403 DONE; 13404}) 13405 13406(define_insn "*call_0" 13407 [(call (mem:QI (match_operand 0 "constant_call_address_operand" "")) 13408 (match_operand 1 "" ""))] 13409 "" 13410{ 13411 if (SIBLING_CALL_P (insn)) 13412 return "jmp\t%P0"; 13413 else 13414 return "call\t%P0"; 13415} 13416 [(set_attr "type" "call")]) 13417 13418(define_insn "*call_1" 13419 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm")) 13420 (match_operand 1 "" ""))] 13421 "!TARGET_64BIT" 13422{ 13423 if (constant_call_address_operand (operands[0], QImode)) 13424 { 13425 if (SIBLING_CALL_P (insn)) 13426 return "jmp\t%P0"; 13427 else 13428 return "call\t%P0"; 13429 } 13430 if (SIBLING_CALL_P (insn)) 13431 return "jmp\t%A0"; 13432 else 13433 return "call\t%A0"; 13434} 13435 [(set_attr "type" "call")]) 13436 13437(define_insn "*call_1_rex64" 13438 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm")) 13439 (match_operand 1 "" ""))] 13440 "TARGET_64BIT" 13441{ 13442 if (constant_call_address_operand (operands[0], QImode)) 13443 { 13444 if (SIBLING_CALL_P (insn)) 13445 return "jmp\t%P0"; 13446 else 13447 return "call\t%P0"; 13448 } 13449 if (SIBLING_CALL_P (insn)) 13450 return "jmp\t%A0"; 13451 else 13452 return "call\t%A0"; 13453} 13454 [(set_attr "type" "call")]) 13455 13456;; Call subroutine, returning value in operand 0 13457 13458(define_expand "call_value_pop" 13459 [(parallel [(set (match_operand 0 "" "") 13460 (call (match_operand:QI 1 "" "") 13461 (match_operand:SI 2 "" ""))) 13462 (set (reg:SI 7) 13463 (plus:SI (reg:SI 7) 13464 (match_operand:SI 4 "" "")))])] 13465 "!TARGET_64BIT" 13466{ 13467 ix86_expand_call (operands[0], operands[1], operands[2], 13468 operands[3], operands[4]); 13469 DONE; 13470}) 13471 13472(define_expand "call_value" 13473 [(set (match_operand 0 "" "") 13474 (call (match_operand:QI 1 "" "") 13475 (match_operand:SI 2 "" ""))) 13476 (use (match_operand:SI 3 "" ""))] 13477 ;; Operand 2 not used on the i386. 13478 "" 13479{ 13480 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL); 13481 DONE; 13482}) 13483 13484;; Call subroutine returning any type. 13485 13486(define_expand "untyped_call" 13487 [(parallel [(call (match_operand 0 "" "") 13488 (const_int 0)) 13489 (match_operand 1 "" "") 13490 (match_operand 2 "" "")])] 13491 "" 13492{ 13493 int i; 13494 13495 /* In order to give reg-stack an easier job in validating two 13496 coprocessor registers as containing a possible return value, 13497 simply pretend the untyped call returns a complex long double 13498 value. */ 13499 13500 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387 13501 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL), 13502 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1), 13503 NULL); 13504 13505 for (i = 0; i < XVECLEN (operands[2], 0); i++) 13506 { 13507 rtx set = XVECEXP (operands[2], 0, i); 13508 emit_move_insn (SET_DEST (set), SET_SRC (set)); 13509 } 13510 13511 /* The optimizer does not know that the call sets the function value 13512 registers we stored in the result block. We avoid problems by 13513 claiming that all hard registers are used and clobbered at this 13514 point. */ 13515 emit_insn (gen_blockage (const0_rtx)); 13516 13517 DONE; 13518}) 13519 13520;; Prologue and epilogue instructions 13521 13522;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 13523;; all of memory. This blocks insns from being moved across this point. 13524 13525(define_insn "blockage" 13526 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)] 13527 "" 13528 "" 13529 [(set_attr "length" "0")]) 13530 13531;; Insn emitted into the body of a function to return from a function. 13532;; This is only done if the function's epilogue is known to be simple. 13533;; See comments for ix86_can_use_return_insn_p in i386.c. 13534 13535(define_expand "return" 13536 [(return)] 13537 "ix86_can_use_return_insn_p ()" 13538{ 13539 if (current_function_pops_args) 13540 { 13541 rtx popc = GEN_INT (current_function_pops_args); 13542 emit_jump_insn (gen_return_pop_internal (popc)); 13543 DONE; 13544 } 13545}) 13546 13547(define_insn "return_internal" 13548 [(return)] 13549 "reload_completed" 13550 "ret" 13551 [(set_attr "length" "1") 13552 (set_attr "length_immediate" "0") 13553 (set_attr "modrm" "0")]) 13554 13555(define_insn "return_pop_internal" 13556 [(return) 13557 (use (match_operand:SI 0 "const_int_operand" ""))] 13558 "reload_completed" 13559 "ret\t%0" 13560 [(set_attr "length" "3") 13561 (set_attr "length_immediate" "2") 13562 (set_attr "modrm" "0")]) 13563 13564(define_insn "return_indirect_internal" 13565 [(return) 13566 (use (match_operand:SI 0 "register_operand" "r"))] 13567 "reload_completed" 13568 "jmp\t%A0" 13569 [(set_attr "type" "ibr") 13570 (set_attr "length_immediate" "0")]) 13571 13572(define_insn "nop" 13573 [(const_int 0)] 13574 "" 13575 "nop" 13576 [(set_attr "length" "1") 13577 (set_attr "length_immediate" "0") 13578 (set_attr "modrm" "0") 13579 (set_attr "ppro_uops" "one")]) 13580 13581(define_expand "prologue" 13582 [(const_int 1)] 13583 "" 13584 "ix86_expand_prologue (); DONE;") 13585 13586(define_insn "set_got" 13587 [(set (match_operand:SI 0 "register_operand" "=r") 13588 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT)) 13589 (clobber (reg:CC 17))] 13590 "!TARGET_64BIT" 13591 { return output_set_got (operands[0]); } 13592 [(set_attr "type" "multi") 13593 (set_attr "length" "12")]) 13594 13595(define_expand "epilogue" 13596 [(const_int 1)] 13597 "" 13598 "ix86_expand_epilogue (1); DONE;") 13599 13600(define_expand "sibcall_epilogue" 13601 [(const_int 1)] 13602 "" 13603 "ix86_expand_epilogue (0); DONE;") 13604 13605(define_expand "eh_return" 13606 [(use (match_operand 0 "register_operand" ""))] 13607 "" 13608{ 13609 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0]; 13610 13611 /* Tricky bit: we write the address of the handler to which we will 13612 be returning into someone else's stack frame, one word below the 13613 stack address we wish to restore. */ 13614 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa); 13615 tmp = plus_constant (tmp, -UNITS_PER_WORD); 13616 tmp = gen_rtx_MEM (Pmode, tmp); 13617 emit_move_insn (tmp, ra); 13618 13619 if (Pmode == SImode) 13620 emit_insn (gen_eh_return_si (sa)); 13621 else 13622 emit_insn (gen_eh_return_di (sa)); 13623 emit_barrier (); 13624 DONE; 13625}) 13626 13627(define_insn_and_split "eh_return_si" 13628 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")] 13629 UNSPECV_EH_RETURN)] 13630 "!TARGET_64BIT" 13631 "#" 13632 "reload_completed" 13633 [(const_int 1)] 13634 "ix86_expand_epilogue (2); DONE;") 13635 13636(define_insn_and_split "eh_return_di" 13637 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 13638 UNSPECV_EH_RETURN)] 13639 "TARGET_64BIT" 13640 "#" 13641 "reload_completed" 13642 [(const_int 1)] 13643 "ix86_expand_epilogue (2); DONE;") 13644 13645(define_insn "leave" 13646 [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4))) 13647 (set (reg:SI 6) (mem:SI (reg:SI 6))) 13648 (clobber (mem:BLK (scratch)))] 13649 "!TARGET_64BIT" 13650 "leave" 13651 [(set_attr "length_immediate" "0") 13652 (set_attr "length" "1") 13653 (set_attr "modrm" "0") 13654 (set_attr "athlon_decode" "vector") 13655 (set_attr "ppro_uops" "few")]) 13656 13657(define_insn "leave_rex64" 13658 [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8))) 13659 (set (reg:DI 6) (mem:DI (reg:DI 6))) 13660 (clobber (mem:BLK (scratch)))] 13661 "TARGET_64BIT" 13662 "leave" 13663 [(set_attr "length_immediate" "0") 13664 (set_attr "length" "1") 13665 (set_attr "modrm" "0") 13666 (set_attr "athlon_decode" "vector") 13667 (set_attr "ppro_uops" "few")]) 13668 13669(define_expand "ffssi2" 13670 [(set (match_operand:SI 0 "nonimmediate_operand" "") 13671 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))] 13672 "" 13673{ 13674 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode); 13675 rtx in = operands[1]; 13676 13677 if (TARGET_CMOVE) 13678 { 13679 emit_move_insn (tmp, constm1_rtx); 13680 emit_insn (gen_ffssi_1 (out, in)); 13681 emit_insn (gen_rtx_SET (VOIDmode, out, 13682 gen_rtx_IF_THEN_ELSE (SImode, 13683 gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG), 13684 const0_rtx), 13685 tmp, 13686 out))); 13687 emit_insn (gen_addsi3 (out, out, const1_rtx)); 13688 emit_move_insn (operands[0], out); 13689 } 13690 13691 /* Pentium bsf instruction is extremly slow. The following code is 13692 recommended by the Intel Optimizing Manual as a reasonable replacement: 13693 TEST EAX,EAX 13694 JZ SHORT BS2 13695 XOR ECX,ECX 13696 MOV DWORD PTR [TEMP+4],ECX 13697 SUB ECX,EAX 13698 AND EAX,ECX 13699 MOV DWORD PTR [TEMP],EAX 13700 FILD QWORD PTR [TEMP] 13701 FSTP QWORD PTR [TEMP] 13702 WAIT ; WAIT only needed for compatibility with 13703 ; earlier processors 13704 MOV ECX, DWORD PTR [TEMP+4] 13705 SHR ECX,20 13706 SUB ECX,3FFH 13707 TEST EAX,EAX ; clear zero flag 13708 BS2: 13709 Following piece of code expand ffs to similar beast. 13710 */ 13711 13712 else if (TARGET_PENTIUM && !optimize_size && TARGET_80387) 13713 { 13714 rtx label = gen_label_rtx (); 13715 rtx lo, hi; 13716 rtx mem = assign_386_stack_local (DImode, 0); 13717 rtx fptmp = gen_reg_rtx (DFmode); 13718 split_di (&mem, 1, &lo, &hi); 13719 13720 emit_move_insn (out, const0_rtx); 13721 13722 emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, label); 13723 13724 emit_move_insn (hi, out); 13725 emit_insn (gen_subsi3 (out, out, in)); 13726 emit_insn (gen_andsi3 (out, out, in)); 13727 emit_move_insn (lo, out); 13728 emit_insn (gen_floatdidf2 (fptmp,mem)); 13729 emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp); 13730 emit_move_insn (out, hi); 13731 emit_insn (gen_lshrsi3 (out, out, GEN_INT (20))); 13732 emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1))); 13733 13734 emit_label (label); 13735 LABEL_NUSES (label) = 1; 13736 13737 emit_move_insn (operands[0], out); 13738 } 13739 else 13740 { 13741 emit_move_insn (tmp, const0_rtx); 13742 emit_insn (gen_ffssi_1 (out, in)); 13743 emit_insn (gen_rtx_SET (VOIDmode, 13744 gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)), 13745 gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG), 13746 const0_rtx))); 13747 emit_insn (gen_negsi2 (tmp, tmp)); 13748 emit_insn (gen_iorsi3 (out, out, tmp)); 13749 emit_insn (gen_addsi3 (out, out, const1_rtx)); 13750 emit_move_insn (operands[0], out); 13751 } 13752 DONE; 13753}) 13754 13755(define_insn "ffssi_1" 13756 [(set (reg:CCZ 17) 13757 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm") 13758 (const_int 0))) 13759 (set (match_operand:SI 0 "register_operand" "=r") 13760 (unspec:SI [(match_dup 1)] UNSPEC_BSF))] 13761 "" 13762 "bsf{l}\t{%1, %0|%0, %1}" 13763 [(set_attr "prefix_0f" "1") 13764 (set_attr "ppro_uops" "few")]) 13765 13766;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger 13767;; and slower than the two-byte movzx insn needed to do the work in SImode. 13768 13769;; Thread-local storage patterns for ELF. 13770;; 13771;; Note that these code sequences must appear exactly as shown 13772;; in order to allow linker relaxation. 13773 13774(define_insn "*tls_global_dynamic_32_gnu" 13775 [(set (match_operand:SI 0 "register_operand" "=a") 13776 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 13777 (match_operand:SI 2 "tls_symbolic_operand" "") 13778 (match_operand:SI 3 "call_insn_operand" "")] 13779 UNSPEC_TLS_GD)) 13780 (clobber (match_scratch:SI 4 "=d")) 13781 (clobber (match_scratch:SI 5 "=c")) 13782 (clobber (reg:CC 17))] 13783 "!TARGET_64BIT && TARGET_GNU_TLS" 13784 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3" 13785 [(set_attr "type" "multi") 13786 (set_attr "length" "12")]) 13787 13788(define_insn "*tls_global_dynamic_32_sun" 13789 [(set (match_operand:SI 0 "register_operand" "=a") 13790 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 13791 (match_operand:SI 2 "tls_symbolic_operand" "") 13792 (match_operand:SI 3 "call_insn_operand" "")] 13793 UNSPEC_TLS_GD)) 13794 (clobber (match_scratch:SI 4 "=d")) 13795 (clobber (match_scratch:SI 5 "=c")) 13796 (clobber (reg:CC 17))] 13797 "!TARGET_64BIT && TARGET_SUN_TLS" 13798 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]} 13799 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop" 13800 [(set_attr "type" "multi") 13801 (set_attr "length" "14")]) 13802 13803(define_expand "tls_global_dynamic_32" 13804 [(parallel [(set (match_operand:SI 0 "register_operand" "") 13805 (unspec:SI 13806 [(match_dup 2) 13807 (match_operand:SI 1 "tls_symbolic_operand" "") 13808 (match_dup 3)] 13809 UNSPEC_TLS_GD)) 13810 (clobber (match_scratch:SI 4 "")) 13811 (clobber (match_scratch:SI 5 "")) 13812 (clobber (reg:CC 17))])] 13813 "" 13814{ 13815 if (flag_pic) 13816 operands[2] = pic_offset_table_rtx; 13817 else 13818 { 13819 operands[2] = gen_reg_rtx (Pmode); 13820 emit_insn (gen_set_got (operands[2])); 13821 } 13822 operands[3] = ix86_tls_get_addr (); 13823}) 13824 13825(define_insn "*tls_global_dynamic_64" 13826 [(set (match_operand:DI 0 "register_operand" "=a") 13827 (call (mem:QI (match_operand:DI 2 "call_insn_operand" "")) 13828 (match_operand:DI 3 "" ""))) 13829 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")] 13830 UNSPEC_TLS_GD)] 13831 "TARGET_64BIT" 13832 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2" 13833 [(set_attr "type" "multi") 13834 (set_attr "length" "16")]) 13835 13836(define_expand "tls_global_dynamic_64" 13837 [(parallel [(set (match_operand:DI 0 "register_operand" "") 13838 (call (mem:QI (match_dup 2)) (const_int 0))) 13839 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")] 13840 UNSPEC_TLS_GD)])] 13841 "" 13842{ 13843 operands[2] = ix86_tls_get_addr (); 13844}) 13845 13846(define_insn "*tls_local_dynamic_base_32_gnu" 13847 [(set (match_operand:SI 0 "register_operand" "=a") 13848 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 13849 (match_operand:SI 2 "call_insn_operand" "")] 13850 UNSPEC_TLS_LD_BASE)) 13851 (clobber (match_scratch:SI 3 "=d")) 13852 (clobber (match_scratch:SI 4 "=c")) 13853 (clobber (reg:CC 17))] 13854 "!TARGET_64BIT && TARGET_GNU_TLS" 13855 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2" 13856 [(set_attr "type" "multi") 13857 (set_attr "length" "11")]) 13858 13859(define_insn "*tls_local_dynamic_base_32_sun" 13860 [(set (match_operand:SI 0 "register_operand" "=a") 13861 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 13862 (match_operand:SI 2 "call_insn_operand" "")] 13863 UNSPEC_TLS_LD_BASE)) 13864 (clobber (match_scratch:SI 3 "=d")) 13865 (clobber (match_scratch:SI 4 "=c")) 13866 (clobber (reg:CC 17))] 13867 "!TARGET_64BIT && TARGET_SUN_TLS" 13868 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]} 13869 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3" 13870 [(set_attr "type" "multi") 13871 (set_attr "length" "13")]) 13872 13873(define_expand "tls_local_dynamic_base_32" 13874 [(parallel [(set (match_operand:SI 0 "register_operand" "") 13875 (unspec:SI [(match_dup 1) (match_dup 2)] 13876 UNSPEC_TLS_LD_BASE)) 13877 (clobber (match_scratch:SI 3 "")) 13878 (clobber (match_scratch:SI 4 "")) 13879 (clobber (reg:CC 17))])] 13880 "" 13881{ 13882 if (flag_pic) 13883 operands[1] = pic_offset_table_rtx; 13884 else 13885 { 13886 operands[1] = gen_reg_rtx (Pmode); 13887 emit_insn (gen_set_got (operands[1])); 13888 } 13889 operands[2] = ix86_tls_get_addr (); 13890}) 13891 13892(define_insn "*tls_local_dynamic_base_64" 13893 [(set (match_operand:DI 0 "register_operand" "=a") 13894 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "")) 13895 (match_operand:DI 2 "" ""))) 13896 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)] 13897 "TARGET_64BIT" 13898 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1" 13899 [(set_attr "type" "multi") 13900 (set_attr "length" "12")]) 13901 13902(define_expand "tls_local_dynamic_base_64" 13903 [(parallel [(set (match_operand:DI 0 "register_operand" "") 13904 (call (mem:QI (match_dup 1)) (const_int 0))) 13905 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])] 13906 "" 13907{ 13908 operands[1] = ix86_tls_get_addr (); 13909}) 13910 13911;; Local dynamic of a single variable is a lose. Show combine how 13912;; to convert that back to global dynamic. 13913 13914(define_insn_and_split "*tls_local_dynamic_32_once" 13915 [(set (match_operand:SI 0 "register_operand" "=a") 13916 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b") 13917 (match_operand:SI 2 "call_insn_operand" "")] 13918 UNSPEC_TLS_LD_BASE) 13919 (const:SI (unspec:SI 13920 [(match_operand:SI 3 "tls_symbolic_operand" "")] 13921 UNSPEC_DTPOFF)))) 13922 (clobber (match_scratch:SI 4 "=d")) 13923 (clobber (match_scratch:SI 5 "=c")) 13924 (clobber (reg:CC 17))] 13925 "" 13926 "#" 13927 "" 13928 [(parallel [(set (match_dup 0) 13929 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)] 13930 UNSPEC_TLS_GD)) 13931 (clobber (match_dup 4)) 13932 (clobber (match_dup 5)) 13933 (clobber (reg:CC 17))])] 13934 "") 13935 13936;; These patterns match the binary 387 instructions for addM3, subM3, 13937;; mulM3 and divM3. There are three patterns for each of DFmode and 13938;; SFmode. The first is the normal insn, the second the same insn but 13939;; with one operand a conversion, and the third the same insn but with 13940;; the other operand a conversion. The conversion may be SFmode or 13941;; SImode if the target mode DFmode, but only SImode if the target mode 13942;; is SFmode. 13943 13944;; Gcc is slightly more smart about handling normal two address instructions 13945;; so use special patterns for add and mull. 13946(define_insn "*fop_sf_comm_nosse" 13947 [(set (match_operand:SF 0 "register_operand" "=f") 13948 (match_operator:SF 3 "binary_fp_operator" 13949 [(match_operand:SF 1 "nonimmediate_operand" "%0") 13950 (match_operand:SF 2 "nonimmediate_operand" "fm")]))] 13951 "TARGET_80387 && !TARGET_SSE_MATH 13952 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' 13953 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 13954 "* return output_387_binary_op (insn, operands);" 13955 [(set (attr "type") 13956 (if_then_else (match_operand:SF 3 "mult_operator" "") 13957 (const_string "fmul") 13958 (const_string "fop"))) 13959 (set_attr "mode" "SF")]) 13960 13961(define_insn "*fop_sf_comm" 13962 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f") 13963 (match_operator:SF 3 "binary_fp_operator" 13964 [(match_operand:SF 1 "nonimmediate_operand" "%0,0") 13965 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))] 13966 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387 13967 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' 13968 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 13969 "* return output_387_binary_op (insn, operands);" 13970 [(set (attr "type") 13971 (if_then_else (eq_attr "alternative" "1") 13972 (if_then_else (match_operand:SF 3 "mult_operator" "") 13973 (const_string "ssemul") 13974 (const_string "sseadd")) 13975 (if_then_else (match_operand:SF 3 "mult_operator" "") 13976 (const_string "fmul") 13977 (const_string "fop")))) 13978 (set_attr "mode" "SF")]) 13979 13980(define_insn "*fop_sf_comm_sse" 13981 [(set (match_operand:SF 0 "register_operand" "=x") 13982 (match_operator:SF 3 "binary_fp_operator" 13983 [(match_operand:SF 1 "nonimmediate_operand" "%0") 13984 (match_operand:SF 2 "nonimmediate_operand" "xm")]))] 13985 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' 13986 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 13987 "* return output_387_binary_op (insn, operands);" 13988 [(set (attr "type") 13989 (if_then_else (match_operand:SF 3 "mult_operator" "") 13990 (const_string "ssemul") 13991 (const_string "sseadd"))) 13992 (set_attr "mode" "SF")]) 13993 13994(define_insn "*fop_df_comm_nosse" 13995 [(set (match_operand:DF 0 "register_operand" "=f") 13996 (match_operator:DF 3 "binary_fp_operator" 13997 [(match_operand:DF 1 "nonimmediate_operand" "%0") 13998 (match_operand:DF 2 "nonimmediate_operand" "fm")]))] 13999 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH) 14000 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' 14001 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 14002 "* return output_387_binary_op (insn, operands);" 14003 [(set (attr "type") 14004 (if_then_else (match_operand:SF 3 "mult_operator" "") 14005 (const_string "fmul") 14006 (const_string "fop"))) 14007 (set_attr "mode" "DF")]) 14008 14009(define_insn "*fop_df_comm" 14010 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f") 14011 (match_operator:DF 3 "binary_fp_operator" 14012 [(match_operand:DF 1 "nonimmediate_operand" "%0,0") 14013 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))] 14014 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387 14015 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' 14016 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 14017 "* return output_387_binary_op (insn, operands);" 14018 [(set (attr "type") 14019 (if_then_else (eq_attr "alternative" "1") 14020 (if_then_else (match_operand:SF 3 "mult_operator" "") 14021 (const_string "ssemul") 14022 (const_string "sseadd")) 14023 (if_then_else (match_operand:SF 3 "mult_operator" "") 14024 (const_string "fmul") 14025 (const_string "fop")))) 14026 (set_attr "mode" "DF")]) 14027 14028(define_insn "*fop_df_comm_sse" 14029 [(set (match_operand:DF 0 "register_operand" "=Y") 14030 (match_operator:DF 3 "binary_fp_operator" 14031 [(match_operand:DF 1 "nonimmediate_operand" "%0") 14032 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))] 14033 "TARGET_SSE2 && TARGET_SSE_MATH 14034 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' 14035 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 14036 "* return output_387_binary_op (insn, operands);" 14037 [(set (attr "type") 14038 (if_then_else (match_operand:SF 3 "mult_operator" "") 14039 (const_string "ssemul") 14040 (const_string "sseadd"))) 14041 (set_attr "mode" "DF")]) 14042 14043(define_insn "*fop_xf_comm" 14044 [(set (match_operand:XF 0 "register_operand" "=f") 14045 (match_operator:XF 3 "binary_fp_operator" 14046 [(match_operand:XF 1 "register_operand" "%0") 14047 (match_operand:XF 2 "register_operand" "f")]))] 14048 "!TARGET_64BIT && TARGET_80387 14049 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" 14050 "* return output_387_binary_op (insn, operands);" 14051 [(set (attr "type") 14052 (if_then_else (match_operand:XF 3 "mult_operator" "") 14053 (const_string "fmul") 14054 (const_string "fop"))) 14055 (set_attr "mode" "XF")]) 14056 14057(define_insn "*fop_tf_comm" 14058 [(set (match_operand:TF 0 "register_operand" "=f") 14059 (match_operator:TF 3 "binary_fp_operator" 14060 [(match_operand:TF 1 "register_operand" "%0") 14061 (match_operand:TF 2 "register_operand" "f")]))] 14062 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" 14063 "* return output_387_binary_op (insn, operands);" 14064 [(set (attr "type") 14065 (if_then_else (match_operand:TF 3 "mult_operator" "") 14066 (const_string "fmul") 14067 (const_string "fop"))) 14068 (set_attr "mode" "XF")]) 14069 14070(define_insn "*fop_sf_1_nosse" 14071 [(set (match_operand:SF 0 "register_operand" "=f,f") 14072 (match_operator:SF 3 "binary_fp_operator" 14073 [(match_operand:SF 1 "nonimmediate_operand" "0,fm") 14074 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))] 14075 "TARGET_80387 && !TARGET_SSE_MATH 14076 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c' 14077 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 14078 "* return output_387_binary_op (insn, operands);" 14079 [(set (attr "type") 14080 (cond [(match_operand:SF 3 "mult_operator" "") 14081 (const_string "fmul") 14082 (match_operand:SF 3 "div_operator" "") 14083 (const_string "fdiv") 14084 ] 14085 (const_string "fop"))) 14086 (set_attr "mode" "SF")]) 14087 14088(define_insn "*fop_sf_1" 14089 [(set (match_operand:SF 0 "register_operand" "=f,f,x") 14090 (match_operator:SF 3 "binary_fp_operator" 14091 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0") 14092 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))] 14093 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387 14094 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c' 14095 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 14096 "* return output_387_binary_op (insn, operands);" 14097 [(set (attr "type") 14098 (cond [(and (eq_attr "alternative" "2") 14099 (match_operand:SF 3 "mult_operator" "")) 14100 (const_string "ssemul") 14101 (and (eq_attr "alternative" "2") 14102 (match_operand:SF 3 "div_operator" "")) 14103 (const_string "ssediv") 14104 (eq_attr "alternative" "2") 14105 (const_string "sseadd") 14106 (match_operand:SF 3 "mult_operator" "") 14107 (const_string "fmul") 14108 (match_operand:SF 3 "div_operator" "") 14109 (const_string "fdiv") 14110 ] 14111 (const_string "fop"))) 14112 (set_attr "mode" "SF")]) 14113 14114(define_insn "*fop_sf_1_sse" 14115 [(set (match_operand:SF 0 "register_operand" "=x") 14116 (match_operator:SF 3 "binary_fp_operator" 14117 [(match_operand:SF 1 "register_operand" "0") 14118 (match_operand:SF 2 "nonimmediate_operand" "xm")]))] 14119 "TARGET_SSE_MATH 14120 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" 14121 "* return output_387_binary_op (insn, operands);" 14122 [(set (attr "type") 14123 (cond [(match_operand:SF 3 "mult_operator" "") 14124 (const_string "ssemul") 14125 (match_operand:SF 3 "div_operator" "") 14126 (const_string "ssediv") 14127 ] 14128 (const_string "sseadd"))) 14129 (set_attr "mode" "SF")]) 14130 14131;; ??? Add SSE splitters for these! 14132(define_insn "*fop_sf_2" 14133 [(set (match_operand:SF 0 "register_operand" "=f,f") 14134 (match_operator:SF 3 "binary_fp_operator" 14135 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) 14136 (match_operand:SF 2 "register_operand" "0,0")]))] 14137 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH" 14138 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" 14139 [(set (attr "type") 14140 (cond [(match_operand:SF 3 "mult_operator" "") 14141 (const_string "fmul") 14142 (match_operand:SF 3 "div_operator" "") 14143 (const_string "fdiv") 14144 ] 14145 (const_string "fop"))) 14146 (set_attr "fp_int_src" "true") 14147 (set_attr "ppro_uops" "many") 14148 (set_attr "mode" "SI")]) 14149 14150(define_insn "*fop_sf_3" 14151 [(set (match_operand:SF 0 "register_operand" "=f,f") 14152 (match_operator:SF 3 "binary_fp_operator" 14153 [(match_operand:SF 1 "register_operand" "0,0") 14154 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] 14155 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH" 14156 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" 14157 [(set (attr "type") 14158 (cond [(match_operand:SF 3 "mult_operator" "") 14159 (const_string "fmul") 14160 (match_operand:SF 3 "div_operator" "") 14161 (const_string "fdiv") 14162 ] 14163 (const_string "fop"))) 14164 (set_attr "fp_int_src" "true") 14165 (set_attr "ppro_uops" "many") 14166 (set_attr "mode" "SI")]) 14167 14168(define_insn "*fop_df_1_nosse" 14169 [(set (match_operand:DF 0 "register_operand" "=f,f") 14170 (match_operator:DF 3 "binary_fp_operator" 14171 [(match_operand:DF 1 "nonimmediate_operand" "0,fm") 14172 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))] 14173 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH) 14174 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c' 14175 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 14176 "* return output_387_binary_op (insn, operands);" 14177 [(set (attr "type") 14178 (cond [(match_operand:DF 3 "mult_operator" "") 14179 (const_string "fmul") 14180 (match_operand:DF 3 "div_operator" "") 14181 (const_string "fdiv") 14182 ] 14183 (const_string "fop"))) 14184 (set_attr "mode" "DF")]) 14185 14186 14187(define_insn "*fop_df_1" 14188 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f") 14189 (match_operator:DF 3 "binary_fp_operator" 14190 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0") 14191 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))] 14192 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387 14193 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c' 14194 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 14195 "* return output_387_binary_op (insn, operands);" 14196 [(set (attr "type") 14197 (cond [(and (eq_attr "alternative" "2") 14198 (match_operand:SF 3 "mult_operator" "")) 14199 (const_string "ssemul") 14200 (and (eq_attr "alternative" "2") 14201 (match_operand:SF 3 "div_operator" "")) 14202 (const_string "ssediv") 14203 (eq_attr "alternative" "2") 14204 (const_string "sseadd") 14205 (match_operand:DF 3 "mult_operator" "") 14206 (const_string "fmul") 14207 (match_operand:DF 3 "div_operator" "") 14208 (const_string "fdiv") 14209 ] 14210 (const_string "fop"))) 14211 (set_attr "mode" "DF")]) 14212 14213(define_insn "*fop_df_1_sse" 14214 [(set (match_operand:DF 0 "register_operand" "=Y") 14215 (match_operator:DF 3 "binary_fp_operator" 14216 [(match_operand:DF 1 "register_operand" "0") 14217 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))] 14218 "TARGET_SSE2 && TARGET_SSE_MATH 14219 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" 14220 "* return output_387_binary_op (insn, operands);" 14221 [(set_attr "mode" "DF") 14222 (set (attr "type") 14223 (cond [(match_operand:SF 3 "mult_operator" "") 14224 (const_string "ssemul") 14225 (match_operand:SF 3 "div_operator" "") 14226 (const_string "ssediv") 14227 ] 14228 (const_string "sseadd")))]) 14229 14230;; ??? Add SSE splitters for these! 14231(define_insn "*fop_df_2" 14232 [(set (match_operand:DF 0 "register_operand" "=f,f") 14233 (match_operator:DF 3 "binary_fp_operator" 14234 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) 14235 (match_operand:DF 2 "register_operand" "0,0")]))] 14236 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)" 14237 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" 14238 [(set (attr "type") 14239 (cond [(match_operand:DF 3 "mult_operator" "") 14240 (const_string "fmul") 14241 (match_operand:DF 3 "div_operator" "") 14242 (const_string "fdiv") 14243 ] 14244 (const_string "fop"))) 14245 (set_attr "fp_int_src" "true") 14246 (set_attr "ppro_uops" "many") 14247 (set_attr "mode" "SI")]) 14248 14249(define_insn "*fop_df_3" 14250 [(set (match_operand:DF 0 "register_operand" "=f,f") 14251 (match_operator:DF 3 "binary_fp_operator" 14252 [(match_operand:DF 1 "register_operand" "0,0") 14253 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] 14254 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)" 14255 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" 14256 [(set (attr "type") 14257 (cond [(match_operand:DF 3 "mult_operator" "") 14258 (const_string "fmul") 14259 (match_operand:DF 3 "div_operator" "") 14260 (const_string "fdiv") 14261 ] 14262 (const_string "fop"))) 14263 (set_attr "fp_int_src" "true") 14264 (set_attr "ppro_uops" "many") 14265 (set_attr "mode" "SI")]) 14266 14267(define_insn "*fop_df_4" 14268 [(set (match_operand:DF 0 "register_operand" "=f,f") 14269 (match_operator:DF 3 "binary_fp_operator" 14270 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0")) 14271 (match_operand:DF 2 "register_operand" "0,f")]))] 14272 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH) 14273 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 14274 "* return output_387_binary_op (insn, operands);" 14275 [(set (attr "type") 14276 (cond [(match_operand:DF 3 "mult_operator" "") 14277 (const_string "fmul") 14278 (match_operand:DF 3 "div_operator" "") 14279 (const_string "fdiv") 14280 ] 14281 (const_string "fop"))) 14282 (set_attr "mode" "SF")]) 14283 14284(define_insn "*fop_df_5" 14285 [(set (match_operand:DF 0 "register_operand" "=f,f") 14286 (match_operator:DF 3 "binary_fp_operator" 14287 [(match_operand:DF 1 "register_operand" "0,f") 14288 (float_extend:DF 14289 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] 14290 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)" 14291 "* return output_387_binary_op (insn, operands);" 14292 [(set (attr "type") 14293 (cond [(match_operand:DF 3 "mult_operator" "") 14294 (const_string "fmul") 14295 (match_operand:DF 3 "div_operator" "") 14296 (const_string "fdiv") 14297 ] 14298 (const_string "fop"))) 14299 (set_attr "mode" "SF")]) 14300 14301(define_insn "*fop_xf_1" 14302 [(set (match_operand:XF 0 "register_operand" "=f,f") 14303 (match_operator:XF 3 "binary_fp_operator" 14304 [(match_operand:XF 1 "register_operand" "0,f") 14305 (match_operand:XF 2 "register_operand" "f,0")]))] 14306 "!TARGET_64BIT && TARGET_80387 14307 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" 14308 "* return output_387_binary_op (insn, operands);" 14309 [(set (attr "type") 14310 (cond [(match_operand:XF 3 "mult_operator" "") 14311 (const_string "fmul") 14312 (match_operand:XF 3 "div_operator" "") 14313 (const_string "fdiv") 14314 ] 14315 (const_string "fop"))) 14316 (set_attr "mode" "XF")]) 14317 14318(define_insn "*fop_tf_1" 14319 [(set (match_operand:TF 0 "register_operand" "=f,f") 14320 (match_operator:TF 3 "binary_fp_operator" 14321 [(match_operand:TF 1 "register_operand" "0,f") 14322 (match_operand:TF 2 "register_operand" "f,0")]))] 14323 "TARGET_80387 14324 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" 14325 "* return output_387_binary_op (insn, operands);" 14326 [(set (attr "type") 14327 (cond [(match_operand:TF 3 "mult_operator" "") 14328 (const_string "fmul") 14329 (match_operand:TF 3 "div_operator" "") 14330 (const_string "fdiv") 14331 ] 14332 (const_string "fop"))) 14333 (set_attr "mode" "XF")]) 14334 14335(define_insn "*fop_xf_2" 14336 [(set (match_operand:XF 0 "register_operand" "=f,f") 14337 (match_operator:XF 3 "binary_fp_operator" 14338 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) 14339 (match_operand:XF 2 "register_operand" "0,0")]))] 14340 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP" 14341 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" 14342 [(set (attr "type") 14343 (cond [(match_operand:XF 3 "mult_operator" "") 14344 (const_string "fmul") 14345 (match_operand:XF 3 "div_operator" "") 14346 (const_string "fdiv") 14347 ] 14348 (const_string "fop"))) 14349 (set_attr "fp_int_src" "true") 14350 (set_attr "mode" "SI") 14351 (set_attr "ppro_uops" "many")]) 14352 14353(define_insn "*fop_tf_2" 14354 [(set (match_operand:TF 0 "register_operand" "=f,f") 14355 (match_operator:TF 3 "binary_fp_operator" 14356 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) 14357 (match_operand:TF 2 "register_operand" "0,0")]))] 14358 "TARGET_80387 && TARGET_USE_FIOP" 14359 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" 14360 [(set (attr "type") 14361 (cond [(match_operand:TF 3 "mult_operator" "") 14362 (const_string "fmul") 14363 (match_operand:TF 3 "div_operator" "") 14364 (const_string "fdiv") 14365 ] 14366 (const_string "fop"))) 14367 (set_attr "fp_int_src" "true") 14368 (set_attr "mode" "SI") 14369 (set_attr "ppro_uops" "many")]) 14370 14371(define_insn "*fop_xf_3" 14372 [(set (match_operand:XF 0 "register_operand" "=f,f") 14373 (match_operator:XF 3 "binary_fp_operator" 14374 [(match_operand:XF 1 "register_operand" "0,0") 14375 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] 14376 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP" 14377 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" 14378 [(set (attr "type") 14379 (cond [(match_operand:XF 3 "mult_operator" "") 14380 (const_string "fmul") 14381 (match_operand:XF 3 "div_operator" "") 14382 (const_string "fdiv") 14383 ] 14384 (const_string "fop"))) 14385 (set_attr "fp_int_src" "true") 14386 (set_attr "mode" "SI") 14387 (set_attr "ppro_uops" "many")]) 14388 14389(define_insn "*fop_tf_3" 14390 [(set (match_operand:TF 0 "register_operand" "=f,f") 14391 (match_operator:TF 3 "binary_fp_operator" 14392 [(match_operand:TF 1 "register_operand" "0,0") 14393 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] 14394 "TARGET_80387 && TARGET_USE_FIOP" 14395 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" 14396 [(set (attr "type") 14397 (cond [(match_operand:TF 3 "mult_operator" "") 14398 (const_string "fmul") 14399 (match_operand:TF 3 "div_operator" "") 14400 (const_string "fdiv") 14401 ] 14402 (const_string "fop"))) 14403 (set_attr "fp_int_src" "true") 14404 (set_attr "mode" "SI") 14405 (set_attr "ppro_uops" "many")]) 14406 14407(define_insn "*fop_xf_4" 14408 [(set (match_operand:XF 0 "register_operand" "=f,f") 14409 (match_operator:XF 3 "binary_fp_operator" 14410 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0")) 14411 (match_operand:XF 2 "register_operand" "0,f")]))] 14412 "!TARGET_64BIT && TARGET_80387" 14413 "* return output_387_binary_op (insn, operands);" 14414 [(set (attr "type") 14415 (cond [(match_operand:XF 3 "mult_operator" "") 14416 (const_string "fmul") 14417 (match_operand:XF 3 "div_operator" "") 14418 (const_string "fdiv") 14419 ] 14420 (const_string "fop"))) 14421 (set_attr "mode" "SF")]) 14422 14423(define_insn "*fop_tf_4" 14424 [(set (match_operand:TF 0 "register_operand" "=f,f") 14425 (match_operator:TF 3 "binary_fp_operator" 14426 [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0")) 14427 (match_operand:TF 2 "register_operand" "0,f")]))] 14428 "TARGET_80387" 14429 "* return output_387_binary_op (insn, operands);" 14430 [(set (attr "type") 14431 (cond [(match_operand:TF 3 "mult_operator" "") 14432 (const_string "fmul") 14433 (match_operand:TF 3 "div_operator" "") 14434 (const_string "fdiv") 14435 ] 14436 (const_string "fop"))) 14437 (set_attr "mode" "SF")]) 14438 14439(define_insn "*fop_xf_5" 14440 [(set (match_operand:XF 0 "register_operand" "=f,f") 14441 (match_operator:XF 3 "binary_fp_operator" 14442 [(match_operand:XF 1 "register_operand" "0,f") 14443 (float_extend:XF 14444 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] 14445 "!TARGET_64BIT && TARGET_80387" 14446 "* return output_387_binary_op (insn, operands);" 14447 [(set (attr "type") 14448 (cond [(match_operand:XF 3 "mult_operator" "") 14449 (const_string "fmul") 14450 (match_operand:XF 3 "div_operator" "") 14451 (const_string "fdiv") 14452 ] 14453 (const_string "fop"))) 14454 (set_attr "mode" "SF")]) 14455 14456(define_insn "*fop_tf_5" 14457 [(set (match_operand:TF 0 "register_operand" "=f,f") 14458 (match_operator:TF 3 "binary_fp_operator" 14459 [(match_operand:TF 1 "register_operand" "0,f") 14460 (float_extend:TF 14461 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] 14462 "TARGET_80387" 14463 "* return output_387_binary_op (insn, operands);" 14464 [(set (attr "type") 14465 (cond [(match_operand:TF 3 "mult_operator" "") 14466 (const_string "fmul") 14467 (match_operand:TF 3 "div_operator" "") 14468 (const_string "fdiv") 14469 ] 14470 (const_string "fop"))) 14471 (set_attr "mode" "SF")]) 14472 14473(define_insn "*fop_xf_6" 14474 [(set (match_operand:XF 0 "register_operand" "=f,f") 14475 (match_operator:XF 3 "binary_fp_operator" 14476 [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0")) 14477 (match_operand:XF 2 "register_operand" "0,f")]))] 14478 "!TARGET_64BIT && TARGET_80387" 14479 "* return output_387_binary_op (insn, operands);" 14480 [(set (attr "type") 14481 (cond [(match_operand:XF 3 "mult_operator" "") 14482 (const_string "fmul") 14483 (match_operand:XF 3 "div_operator" "") 14484 (const_string "fdiv") 14485 ] 14486 (const_string "fop"))) 14487 (set_attr "mode" "DF")]) 14488 14489(define_insn "*fop_tf_6" 14490 [(set (match_operand:TF 0 "register_operand" "=f,f") 14491 (match_operator:TF 3 "binary_fp_operator" 14492 [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0")) 14493 (match_operand:TF 2 "register_operand" "0,f")]))] 14494 "TARGET_80387" 14495 "* return output_387_binary_op (insn, operands);" 14496 [(set (attr "type") 14497 (cond [(match_operand:TF 3 "mult_operator" "") 14498 (const_string "fmul") 14499 (match_operand:TF 3 "div_operator" "") 14500 (const_string "fdiv") 14501 ] 14502 (const_string "fop"))) 14503 (set_attr "mode" "DF")]) 14504 14505(define_insn "*fop_xf_7" 14506 [(set (match_operand:XF 0 "register_operand" "=f,f") 14507 (match_operator:XF 3 "binary_fp_operator" 14508 [(match_operand:XF 1 "register_operand" "0,f") 14509 (float_extend:XF 14510 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))] 14511 "!TARGET_64BIT && TARGET_80387" 14512 "* return output_387_binary_op (insn, operands);" 14513 [(set (attr "type") 14514 (cond [(match_operand:XF 3 "mult_operator" "") 14515 (const_string "fmul") 14516 (match_operand:XF 3 "div_operator" "") 14517 (const_string "fdiv") 14518 ] 14519 (const_string "fop"))) 14520 (set_attr "mode" "DF")]) 14521 14522(define_insn "*fop_tf_7" 14523 [(set (match_operand:TF 0 "register_operand" "=f,f") 14524 (match_operator:TF 3 "binary_fp_operator" 14525 [(match_operand:TF 1 "register_operand" "0,f") 14526 (float_extend:TF 14527 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))] 14528 "TARGET_80387" 14529 "* return output_387_binary_op (insn, operands);" 14530 [(set (attr "type") 14531 (cond [(match_operand:TF 3 "mult_operator" "") 14532 (const_string "fmul") 14533 (match_operand:TF 3 "div_operator" "") 14534 (const_string "fdiv") 14535 ] 14536 (const_string "fop"))) 14537 (set_attr "mode" "DF")]) 14538 14539(define_split 14540 [(set (match_operand 0 "register_operand" "") 14541 (match_operator 3 "binary_fp_operator" 14542 [(float (match_operand:SI 1 "register_operand" "")) 14543 (match_operand 2 "register_operand" "")]))] 14544 "TARGET_80387 && reload_completed 14545 && FLOAT_MODE_P (GET_MODE (operands[0]))" 14546 [(const_int 0)] 14547{ 14548 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]); 14549 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]); 14550 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 14551 gen_rtx_fmt_ee (GET_CODE (operands[3]), 14552 GET_MODE (operands[3]), 14553 operands[4], 14554 operands[2]))); 14555 ix86_free_from_memory (GET_MODE (operands[1])); 14556 DONE; 14557}) 14558 14559(define_split 14560 [(set (match_operand 0 "register_operand" "") 14561 (match_operator 3 "binary_fp_operator" 14562 [(match_operand 1 "register_operand" "") 14563 (float (match_operand:SI 2 "register_operand" ""))]))] 14564 "TARGET_80387 && reload_completed 14565 && FLOAT_MODE_P (GET_MODE (operands[0]))" 14566 [(const_int 0)] 14567{ 14568 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]); 14569 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]); 14570 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 14571 gen_rtx_fmt_ee (GET_CODE (operands[3]), 14572 GET_MODE (operands[3]), 14573 operands[1], 14574 operands[4]))); 14575 ix86_free_from_memory (GET_MODE (operands[2])); 14576 DONE; 14577}) 14578 14579;; FPU special functions. 14580 14581(define_expand "sqrtsf2" 14582 [(set (match_operand:SF 0 "register_operand" "") 14583 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))] 14584 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH" 14585{ 14586 if (!TARGET_SSE_MATH) 14587 operands[1] = force_reg (SFmode, operands[1]); 14588}) 14589 14590(define_insn "sqrtsf2_1" 14591 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f") 14592 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))] 14593 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14594 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)" 14595 "@ 14596 fsqrt 14597 sqrtss\t{%1, %0|%0, %1}" 14598 [(set_attr "type" "fpspc,sse") 14599 (set_attr "mode" "SF,SF") 14600 (set_attr "athlon_decode" "direct,*")]) 14601 14602(define_insn "sqrtsf2_1_sse_only" 14603 [(set (match_operand:SF 0 "register_operand" "=x") 14604 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))] 14605 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)" 14606 "sqrtss\t{%1, %0|%0, %1}" 14607 [(set_attr "type" "sse") 14608 (set_attr "mode" "SF") 14609 (set_attr "athlon_decode" "*")]) 14610 14611(define_insn "sqrtsf2_i387" 14612 [(set (match_operand:SF 0 "register_operand" "=f") 14613 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))] 14614 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14615 && !TARGET_SSE_MATH" 14616 "fsqrt" 14617 [(set_attr "type" "fpspc") 14618 (set_attr "mode" "SF") 14619 (set_attr "athlon_decode" "direct")]) 14620 14621(define_expand "sqrtdf2" 14622 [(set (match_operand:DF 0 "register_operand" "") 14623 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))] 14624 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) 14625 || (TARGET_SSE2 && TARGET_SSE_MATH)" 14626{ 14627 if (!TARGET_SSE2 || !TARGET_SSE_MATH) 14628 operands[1] = force_reg (DFmode, operands[1]); 14629}) 14630 14631(define_insn "sqrtdf2_1" 14632 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f") 14633 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))] 14634 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14635 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)" 14636 "@ 14637 fsqrt 14638 sqrtsd\t{%1, %0|%0, %1}" 14639 [(set_attr "type" "fpspc,sse") 14640 (set_attr "mode" "DF,DF") 14641 (set_attr "athlon_decode" "direct,*")]) 14642 14643(define_insn "sqrtdf2_1_sse_only" 14644 [(set (match_operand:DF 0 "register_operand" "=Y") 14645 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))] 14646 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)" 14647 "sqrtsd\t{%1, %0|%0, %1}" 14648 [(set_attr "type" "sse") 14649 (set_attr "mode" "DF") 14650 (set_attr "athlon_decode" "*")]) 14651 14652(define_insn "sqrtdf2_i387" 14653 [(set (match_operand:DF 0 "register_operand" "=f") 14654 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))] 14655 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14656 && (!TARGET_SSE2 || !TARGET_SSE_MATH)" 14657 "fsqrt" 14658 [(set_attr "type" "fpspc") 14659 (set_attr "mode" "DF") 14660 (set_attr "athlon_decode" "direct")]) 14661 14662(define_insn "*sqrtextendsfdf2" 14663 [(set (match_operand:DF 0 "register_operand" "=f") 14664 (sqrt:DF (float_extend:DF 14665 (match_operand:SF 1 "register_operand" "0"))))] 14666 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14667 && !(TARGET_SSE2 && TARGET_SSE_MATH)" 14668 "fsqrt" 14669 [(set_attr "type" "fpspc") 14670 (set_attr "mode" "DF") 14671 (set_attr "athlon_decode" "direct")]) 14672 14673(define_insn "sqrtxf2" 14674 [(set (match_operand:XF 0 "register_operand" "=f") 14675 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))] 14676 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 14677 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) " 14678 "fsqrt" 14679 [(set_attr "type" "fpspc") 14680 (set_attr "mode" "XF") 14681 (set_attr "athlon_decode" "direct")]) 14682 14683(define_insn "sqrttf2" 14684 [(set (match_operand:TF 0 "register_operand" "=f") 14685 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))] 14686 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14687 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) " 14688 "fsqrt" 14689 [(set_attr "type" "fpspc") 14690 (set_attr "mode" "XF") 14691 (set_attr "athlon_decode" "direct")]) 14692 14693(define_insn "*sqrtextenddfxf2" 14694 [(set (match_operand:XF 0 "register_operand" "=f") 14695 (sqrt:XF (float_extend:XF 14696 (match_operand:DF 1 "register_operand" "0"))))] 14697 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387" 14698 "fsqrt" 14699 [(set_attr "type" "fpspc") 14700 (set_attr "mode" "XF") 14701 (set_attr "athlon_decode" "direct")]) 14702 14703(define_insn "*sqrtextenddftf2" 14704 [(set (match_operand:TF 0 "register_operand" "=f") 14705 (sqrt:TF (float_extend:TF 14706 (match_operand:DF 1 "register_operand" "0"))))] 14707 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387" 14708 "fsqrt" 14709 [(set_attr "type" "fpspc") 14710 (set_attr "mode" "XF") 14711 (set_attr "athlon_decode" "direct")]) 14712 14713(define_insn "*sqrtextendsfxf2" 14714 [(set (match_operand:XF 0 "register_operand" "=f") 14715 (sqrt:XF (float_extend:XF 14716 (match_operand:SF 1 "register_operand" "0"))))] 14717 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387" 14718 "fsqrt" 14719 [(set_attr "type" "fpspc") 14720 (set_attr "mode" "XF") 14721 (set_attr "athlon_decode" "direct")]) 14722 14723(define_insn "*sqrtextendsftf2" 14724 [(set (match_operand:TF 0 "register_operand" "=f") 14725 (sqrt:TF (float_extend:TF 14726 (match_operand:SF 1 "register_operand" "0"))))] 14727 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387" 14728 "fsqrt" 14729 [(set_attr "type" "fpspc") 14730 (set_attr "mode" "XF") 14731 (set_attr "athlon_decode" "direct")]) 14732 14733(define_insn "sindf2" 14734 [(set (match_operand:DF 0 "register_operand" "=f") 14735 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))] 14736 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14737 && flag_unsafe_math_optimizations" 14738 "fsin" 14739 [(set_attr "type" "fpspc") 14740 (set_attr "mode" "DF")]) 14741 14742(define_insn "sinsf2" 14743 [(set (match_operand:SF 0 "register_operand" "=f") 14744 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))] 14745 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14746 && flag_unsafe_math_optimizations" 14747 "fsin" 14748 [(set_attr "type" "fpspc") 14749 (set_attr "mode" "SF")]) 14750 14751(define_insn "*sinextendsfdf2" 14752 [(set (match_operand:DF 0 "register_operand" "=f") 14753 (unspec:DF [(float_extend:DF 14754 (match_operand:SF 1 "register_operand" "0"))] 14755 UNSPEC_SIN))] 14756 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14757 && flag_unsafe_math_optimizations" 14758 "fsin" 14759 [(set_attr "type" "fpspc") 14760 (set_attr "mode" "DF")]) 14761 14762(define_insn "sinxf2" 14763 [(set (match_operand:XF 0 "register_operand" "=f") 14764 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))] 14765 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 14766 && flag_unsafe_math_optimizations" 14767 "fsin" 14768 [(set_attr "type" "fpspc") 14769 (set_attr "mode" "XF")]) 14770 14771(define_insn "sintf2" 14772 [(set (match_operand:TF 0 "register_operand" "=f") 14773 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))] 14774 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14775 && flag_unsafe_math_optimizations" 14776 "fsin" 14777 [(set_attr "type" "fpspc") 14778 (set_attr "mode" "XF")]) 14779 14780(define_insn "cosdf2" 14781 [(set (match_operand:DF 0 "register_operand" "=f") 14782 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))] 14783 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14784 && flag_unsafe_math_optimizations" 14785 "fcos" 14786 [(set_attr "type" "fpspc") 14787 (set_attr "mode" "DF")]) 14788 14789(define_insn "cossf2" 14790 [(set (match_operand:SF 0 "register_operand" "=f") 14791 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))] 14792 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14793 && flag_unsafe_math_optimizations" 14794 "fcos" 14795 [(set_attr "type" "fpspc") 14796 (set_attr "mode" "SF")]) 14797 14798(define_insn "*cosextendsfdf2" 14799 [(set (match_operand:DF 0 "register_operand" "=f") 14800 (unspec:DF [(float_extend:DF 14801 (match_operand:SF 1 "register_operand" "0"))] 14802 UNSPEC_COS))] 14803 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14804 && flag_unsafe_math_optimizations" 14805 "fcos" 14806 [(set_attr "type" "fpspc") 14807 (set_attr "mode" "DF")]) 14808 14809(define_insn "cosxf2" 14810 [(set (match_operand:XF 0 "register_operand" "=f") 14811 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))] 14812 "!TARGET_64BIT && ! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14813 && flag_unsafe_math_optimizations" 14814 "fcos" 14815 [(set_attr "type" "fpspc") 14816 (set_attr "mode" "XF")]) 14817 14818(define_insn "costf2" 14819 [(set (match_operand:TF 0 "register_operand" "=f") 14820 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))] 14821 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 14822 && flag_unsafe_math_optimizations" 14823 "fcos" 14824 [(set_attr "type" "fpspc") 14825 (set_attr "mode" "XF")]) 14826 14827;; Block operation instructions 14828 14829(define_insn "cld" 14830 [(set (reg:SI 19) (const_int 0))] 14831 "" 14832 "cld" 14833 [(set_attr "type" "cld")]) 14834 14835(define_expand "movstrsi" 14836 [(use (match_operand:BLK 0 "memory_operand" "")) 14837 (use (match_operand:BLK 1 "memory_operand" "")) 14838 (use (match_operand:SI 2 "nonmemory_operand" "")) 14839 (use (match_operand:SI 3 "const_int_operand" ""))] 14840 "" 14841{ 14842 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3])) 14843 DONE; 14844 else 14845 FAIL; 14846}) 14847 14848(define_expand "movstrdi" 14849 [(use (match_operand:BLK 0 "memory_operand" "")) 14850 (use (match_operand:BLK 1 "memory_operand" "")) 14851 (use (match_operand:DI 2 "nonmemory_operand" "")) 14852 (use (match_operand:DI 3 "const_int_operand" ""))] 14853 "TARGET_64BIT" 14854{ 14855 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3])) 14856 DONE; 14857 else 14858 FAIL; 14859}) 14860 14861;; Most CPUs don't like single string operations 14862;; Handle this case here to simplify previous expander. 14863 14864(define_expand "strmovdi_rex64" 14865 [(set (match_dup 2) 14866 (mem:DI (match_operand:DI 1 "register_operand" ""))) 14867 (set (mem:DI (match_operand:DI 0 "register_operand" "")) 14868 (match_dup 2)) 14869 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8))) 14870 (clobber (reg:CC 17))]) 14871 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8))) 14872 (clobber (reg:CC 17))])] 14873 "TARGET_64BIT" 14874{ 14875 if (TARGET_SINGLE_STRINGOP || optimize_size) 14876 { 14877 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0], 14878 operands[1])); 14879 DONE; 14880 } 14881 else 14882 operands[2] = gen_reg_rtx (DImode); 14883}) 14884 14885 14886(define_expand "strmovsi" 14887 [(set (match_dup 2) 14888 (mem:SI (match_operand:SI 1 "register_operand" ""))) 14889 (set (mem:SI (match_operand:SI 0 "register_operand" "")) 14890 (match_dup 2)) 14891 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4))) 14892 (clobber (reg:CC 17))]) 14893 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4))) 14894 (clobber (reg:CC 17))])] 14895 "" 14896{ 14897 if (TARGET_64BIT) 14898 { 14899 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1])); 14900 DONE; 14901 } 14902 if (TARGET_SINGLE_STRINGOP || optimize_size) 14903 { 14904 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0], 14905 operands[1])); 14906 DONE; 14907 } 14908 else 14909 operands[2] = gen_reg_rtx (SImode); 14910}) 14911 14912(define_expand "strmovsi_rex64" 14913 [(set (match_dup 2) 14914 (mem:SI (match_operand:DI 1 "register_operand" ""))) 14915 (set (mem:SI (match_operand:DI 0 "register_operand" "")) 14916 (match_dup 2)) 14917 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4))) 14918 (clobber (reg:CC 17))]) 14919 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4))) 14920 (clobber (reg:CC 17))])] 14921 "TARGET_64BIT" 14922{ 14923 if (TARGET_SINGLE_STRINGOP || optimize_size) 14924 { 14925 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0], 14926 operands[1])); 14927 DONE; 14928 } 14929 else 14930 operands[2] = gen_reg_rtx (SImode); 14931}) 14932 14933(define_expand "strmovhi" 14934 [(set (match_dup 2) 14935 (mem:HI (match_operand:SI 1 "register_operand" ""))) 14936 (set (mem:HI (match_operand:SI 0 "register_operand" "")) 14937 (match_dup 2)) 14938 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2))) 14939 (clobber (reg:CC 17))]) 14940 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2))) 14941 (clobber (reg:CC 17))])] 14942 "" 14943{ 14944 if (TARGET_64BIT) 14945 { 14946 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1])); 14947 DONE; 14948 } 14949 if (TARGET_SINGLE_STRINGOP || optimize_size) 14950 { 14951 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0], 14952 operands[1])); 14953 DONE; 14954 } 14955 else 14956 operands[2] = gen_reg_rtx (HImode); 14957}) 14958 14959(define_expand "strmovhi_rex64" 14960 [(set (match_dup 2) 14961 (mem:HI (match_operand:DI 1 "register_operand" ""))) 14962 (set (mem:HI (match_operand:DI 0 "register_operand" "")) 14963 (match_dup 2)) 14964 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2))) 14965 (clobber (reg:CC 17))]) 14966 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2))) 14967 (clobber (reg:CC 17))])] 14968 "TARGET_64BIT" 14969{ 14970 if (TARGET_SINGLE_STRINGOP || optimize_size) 14971 { 14972 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0], 14973 operands[1])); 14974 DONE; 14975 } 14976 else 14977 operands[2] = gen_reg_rtx (HImode); 14978}) 14979 14980(define_expand "strmovqi" 14981 [(set (match_dup 2) 14982 (mem:QI (match_operand:SI 1 "register_operand" ""))) 14983 (set (mem:QI (match_operand:SI 0 "register_operand" "")) 14984 (match_dup 2)) 14985 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))) 14986 (clobber (reg:CC 17))]) 14987 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1))) 14988 (clobber (reg:CC 17))])] 14989 "" 14990{ 14991 if (TARGET_64BIT) 14992 { 14993 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1])); 14994 DONE; 14995 } 14996 if (TARGET_SINGLE_STRINGOP || optimize_size) 14997 { 14998 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0], 14999 operands[1])); 15000 DONE; 15001 } 15002 else 15003 operands[2] = gen_reg_rtx (QImode); 15004}) 15005 15006(define_expand "strmovqi_rex64" 15007 [(set (match_dup 2) 15008 (mem:QI (match_operand:DI 1 "register_operand" ""))) 15009 (set (mem:QI (match_operand:DI 0 "register_operand" "")) 15010 (match_dup 2)) 15011 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1))) 15012 (clobber (reg:CC 17))]) 15013 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1))) 15014 (clobber (reg:CC 17))])] 15015 "TARGET_64BIT" 15016{ 15017 if (TARGET_SINGLE_STRINGOP || optimize_size) 15018 { 15019 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0], 15020 operands[1])); 15021 DONE; 15022 } 15023 else 15024 operands[2] = gen_reg_rtx (QImode); 15025}) 15026 15027(define_insn "strmovdi_rex_1" 15028 [(set (mem:DI (match_operand:DI 2 "register_operand" "0")) 15029 (mem:DI (match_operand:DI 3 "register_operand" "1"))) 15030 (set (match_operand:DI 0 "register_operand" "=D") 15031 (plus:DI (match_dup 2) 15032 (const_int 8))) 15033 (set (match_operand:DI 1 "register_operand" "=S") 15034 (plus:DI (match_dup 3) 15035 (const_int 8))) 15036 (use (reg:SI 19))] 15037 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15038 "movsq" 15039 [(set_attr "type" "str") 15040 (set_attr "mode" "DI") 15041 (set_attr "memory" "both")]) 15042 15043(define_insn "strmovsi_1" 15044 [(set (mem:SI (match_operand:SI 2 "register_operand" "0")) 15045 (mem:SI (match_operand:SI 3 "register_operand" "1"))) 15046 (set (match_operand:SI 0 "register_operand" "=D") 15047 (plus:SI (match_dup 2) 15048 (const_int 4))) 15049 (set (match_operand:SI 1 "register_operand" "=S") 15050 (plus:SI (match_dup 3) 15051 (const_int 4))) 15052 (use (reg:SI 19))] 15053 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15054 "{movsl|movsd}" 15055 [(set_attr "type" "str") 15056 (set_attr "mode" "SI") 15057 (set_attr "memory" "both")]) 15058 15059(define_insn "strmovsi_rex_1" 15060 [(set (mem:SI (match_operand:DI 2 "register_operand" "0")) 15061 (mem:SI (match_operand:DI 3 "register_operand" "1"))) 15062 (set (match_operand:DI 0 "register_operand" "=D") 15063 (plus:DI (match_dup 2) 15064 (const_int 4))) 15065 (set (match_operand:DI 1 "register_operand" "=S") 15066 (plus:DI (match_dup 3) 15067 (const_int 4))) 15068 (use (reg:SI 19))] 15069 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15070 "{movsl|movsd}" 15071 [(set_attr "type" "str") 15072 (set_attr "mode" "SI") 15073 (set_attr "memory" "both")]) 15074 15075(define_insn "strmovhi_1" 15076 [(set (mem:HI (match_operand:SI 2 "register_operand" "0")) 15077 (mem:HI (match_operand:SI 3 "register_operand" "1"))) 15078 (set (match_operand:SI 0 "register_operand" "=D") 15079 (plus:SI (match_dup 2) 15080 (const_int 2))) 15081 (set (match_operand:SI 1 "register_operand" "=S") 15082 (plus:SI (match_dup 3) 15083 (const_int 2))) 15084 (use (reg:SI 19))] 15085 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15086 "movsw" 15087 [(set_attr "type" "str") 15088 (set_attr "memory" "both") 15089 (set_attr "mode" "HI")]) 15090 15091(define_insn "strmovhi_rex_1" 15092 [(set (mem:HI (match_operand:DI 2 "register_operand" "0")) 15093 (mem:HI (match_operand:DI 3 "register_operand" "1"))) 15094 (set (match_operand:DI 0 "register_operand" "=D") 15095 (plus:DI (match_dup 2) 15096 (const_int 2))) 15097 (set (match_operand:DI 1 "register_operand" "=S") 15098 (plus:DI (match_dup 3) 15099 (const_int 2))) 15100 (use (reg:SI 19))] 15101 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15102 "movsw" 15103 [(set_attr "type" "str") 15104 (set_attr "memory" "both") 15105 (set_attr "mode" "HI")]) 15106 15107(define_insn "strmovqi_1" 15108 [(set (mem:QI (match_operand:SI 2 "register_operand" "0")) 15109 (mem:QI (match_operand:SI 3 "register_operand" "1"))) 15110 (set (match_operand:SI 0 "register_operand" "=D") 15111 (plus:SI (match_dup 2) 15112 (const_int 1))) 15113 (set (match_operand:SI 1 "register_operand" "=S") 15114 (plus:SI (match_dup 3) 15115 (const_int 1))) 15116 (use (reg:SI 19))] 15117 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15118 "movsb" 15119 [(set_attr "type" "str") 15120 (set_attr "memory" "both") 15121 (set_attr "mode" "QI")]) 15122 15123(define_insn "strmovqi_rex_1" 15124 [(set (mem:QI (match_operand:DI 2 "register_operand" "0")) 15125 (mem:QI (match_operand:DI 3 "register_operand" "1"))) 15126 (set (match_operand:DI 0 "register_operand" "=D") 15127 (plus:DI (match_dup 2) 15128 (const_int 1))) 15129 (set (match_operand:DI 1 "register_operand" "=S") 15130 (plus:DI (match_dup 3) 15131 (const_int 1))) 15132 (use (reg:SI 19))] 15133 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15134 "movsb" 15135 [(set_attr "type" "str") 15136 (set_attr "memory" "both") 15137 (set_attr "mode" "QI")]) 15138 15139(define_insn "rep_movdi_rex64" 15140 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0)) 15141 (set (match_operand:DI 0 "register_operand" "=D") 15142 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2") 15143 (const_int 3)) 15144 (match_operand:DI 3 "register_operand" "0"))) 15145 (set (match_operand:DI 1 "register_operand" "=S") 15146 (plus:DI (ashift:DI (match_dup 5) (const_int 3)) 15147 (match_operand:DI 4 "register_operand" "1"))) 15148 (set (mem:BLK (match_dup 3)) 15149 (mem:BLK (match_dup 4))) 15150 (use (match_dup 5)) 15151 (use (reg:SI 19))] 15152 "TARGET_64BIT" 15153 "{rep\;movsq|rep movsq}" 15154 [(set_attr "type" "str") 15155 (set_attr "prefix_rep" "1") 15156 (set_attr "memory" "both") 15157 (set_attr "mode" "DI")]) 15158 15159(define_insn "rep_movsi" 15160 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0)) 15161 (set (match_operand:SI 0 "register_operand" "=D") 15162 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2") 15163 (const_int 2)) 15164 (match_operand:SI 3 "register_operand" "0"))) 15165 (set (match_operand:SI 1 "register_operand" "=S") 15166 (plus:SI (ashift:SI (match_dup 5) (const_int 2)) 15167 (match_operand:SI 4 "register_operand" "1"))) 15168 (set (mem:BLK (match_dup 3)) 15169 (mem:BLK (match_dup 4))) 15170 (use (match_dup 5)) 15171 (use (reg:SI 19))] 15172 "!TARGET_64BIT" 15173 "{rep\;movsl|rep movsd}" 15174 [(set_attr "type" "str") 15175 (set_attr "prefix_rep" "1") 15176 (set_attr "memory" "both") 15177 (set_attr "mode" "SI")]) 15178 15179(define_insn "rep_movsi_rex64" 15180 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0)) 15181 (set (match_operand:DI 0 "register_operand" "=D") 15182 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2") 15183 (const_int 2)) 15184 (match_operand:DI 3 "register_operand" "0"))) 15185 (set (match_operand:DI 1 "register_operand" "=S") 15186 (plus:DI (ashift:DI (match_dup 5) (const_int 2)) 15187 (match_operand:DI 4 "register_operand" "1"))) 15188 (set (mem:BLK (match_dup 3)) 15189 (mem:BLK (match_dup 4))) 15190 (use (match_dup 5)) 15191 (use (reg:SI 19))] 15192 "TARGET_64BIT" 15193 "{rep\;movsl|rep movsd}" 15194 [(set_attr "type" "str") 15195 (set_attr "prefix_rep" "1") 15196 (set_attr "memory" "both") 15197 (set_attr "mode" "SI")]) 15198 15199(define_insn "rep_movqi" 15200 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0)) 15201 (set (match_operand:SI 0 "register_operand" "=D") 15202 (plus:SI (match_operand:SI 3 "register_operand" "0") 15203 (match_operand:SI 5 "register_operand" "2"))) 15204 (set (match_operand:SI 1 "register_operand" "=S") 15205 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5))) 15206 (set (mem:BLK (match_dup 3)) 15207 (mem:BLK (match_dup 4))) 15208 (use (match_dup 5)) 15209 (use (reg:SI 19))] 15210 "!TARGET_64BIT" 15211 "{rep\;movsb|rep movsb}" 15212 [(set_attr "type" "str") 15213 (set_attr "prefix_rep" "1") 15214 (set_attr "memory" "both") 15215 (set_attr "mode" "SI")]) 15216 15217(define_insn "rep_movqi_rex64" 15218 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0)) 15219 (set (match_operand:DI 0 "register_operand" "=D") 15220 (plus:DI (match_operand:DI 3 "register_operand" "0") 15221 (match_operand:DI 5 "register_operand" "2"))) 15222 (set (match_operand:DI 1 "register_operand" "=S") 15223 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5))) 15224 (set (mem:BLK (match_dup 3)) 15225 (mem:BLK (match_dup 4))) 15226 (use (match_dup 5)) 15227 (use (reg:SI 19))] 15228 "TARGET_64BIT" 15229 "{rep\;movsb|rep movsb}" 15230 [(set_attr "type" "str") 15231 (set_attr "prefix_rep" "1") 15232 (set_attr "memory" "both") 15233 (set_attr "mode" "SI")]) 15234 15235(define_expand "clrstrsi" 15236 [(use (match_operand:BLK 0 "memory_operand" "")) 15237 (use (match_operand:SI 1 "nonmemory_operand" "")) 15238 (use (match_operand 2 "const_int_operand" ""))] 15239 "" 15240{ 15241 if (ix86_expand_clrstr (operands[0], operands[1], operands[2])) 15242 DONE; 15243 else 15244 FAIL; 15245}) 15246 15247(define_expand "clrstrdi" 15248 [(use (match_operand:BLK 0 "memory_operand" "")) 15249 (use (match_operand:DI 1 "nonmemory_operand" "")) 15250 (use (match_operand 2 "const_int_operand" ""))] 15251 "TARGET_64BIT" 15252{ 15253 if (ix86_expand_clrstr (operands[0], operands[1], operands[2])) 15254 DONE; 15255 else 15256 FAIL; 15257}) 15258 15259;; Most CPUs don't like single string operations 15260;; Handle this case here to simplify previous expander. 15261 15262(define_expand "strsetdi_rex64" 15263 [(set (mem:DI (match_operand:DI 0 "register_operand" "")) 15264 (match_operand:DI 1 "register_operand" "")) 15265 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8))) 15266 (clobber (reg:CC 17))])] 15267 "TARGET_64BIT" 15268{ 15269 if (TARGET_SINGLE_STRINGOP || optimize_size) 15270 { 15271 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1])); 15272 DONE; 15273 } 15274}) 15275 15276(define_expand "strsetsi" 15277 [(set (mem:SI (match_operand:SI 0 "register_operand" "")) 15278 (match_operand:SI 1 "register_operand" "")) 15279 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4))) 15280 (clobber (reg:CC 17))])] 15281 "" 15282{ 15283 if (TARGET_64BIT) 15284 { 15285 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1])); 15286 DONE; 15287 } 15288 else if (TARGET_SINGLE_STRINGOP || optimize_size) 15289 { 15290 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1])); 15291 DONE; 15292 } 15293}) 15294 15295(define_expand "strsetsi_rex64" 15296 [(set (mem:SI (match_operand:DI 0 "register_operand" "")) 15297 (match_operand:SI 1 "register_operand" "")) 15298 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4))) 15299 (clobber (reg:CC 17))])] 15300 "TARGET_64BIT" 15301{ 15302 if (TARGET_SINGLE_STRINGOP || optimize_size) 15303 { 15304 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1])); 15305 DONE; 15306 } 15307}) 15308 15309(define_expand "strsethi" 15310 [(set (mem:HI (match_operand:SI 0 "register_operand" "")) 15311 (match_operand:HI 1 "register_operand" "")) 15312 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2))) 15313 (clobber (reg:CC 17))])] 15314 "" 15315{ 15316 if (TARGET_64BIT) 15317 { 15318 emit_insn (gen_strsethi_rex64 (operands[0], operands[1])); 15319 DONE; 15320 } 15321 else if (TARGET_SINGLE_STRINGOP || optimize_size) 15322 { 15323 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1])); 15324 DONE; 15325 } 15326}) 15327 15328(define_expand "strsethi_rex64" 15329 [(set (mem:HI (match_operand:DI 0 "register_operand" "")) 15330 (match_operand:HI 1 "register_operand" "")) 15331 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2))) 15332 (clobber (reg:CC 17))])] 15333 "TARGET_64BIT" 15334{ 15335 if (TARGET_SINGLE_STRINGOP || optimize_size) 15336 { 15337 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1])); 15338 DONE; 15339 } 15340}) 15341 15342(define_expand "strsetqi" 15343 [(set (mem:QI (match_operand:SI 0 "register_operand" "")) 15344 (match_operand:QI 1 "register_operand" "")) 15345 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))) 15346 (clobber (reg:CC 17))])] 15347 "" 15348{ 15349 if (TARGET_64BIT) 15350 { 15351 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1])); 15352 DONE; 15353 } 15354 else if (TARGET_SINGLE_STRINGOP || optimize_size) 15355 { 15356 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1])); 15357 DONE; 15358 } 15359}) 15360 15361(define_expand "strsetqi_rex64" 15362 [(set (mem:QI (match_operand:DI 0 "register_operand" "")) 15363 (match_operand:QI 1 "register_operand" "")) 15364 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1))) 15365 (clobber (reg:CC 17))])] 15366 "TARGET_64BIT" 15367{ 15368 if (TARGET_SINGLE_STRINGOP || optimize_size) 15369 { 15370 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1])); 15371 DONE; 15372 } 15373}) 15374 15375(define_insn "strsetdi_rex_1" 15376 [(set (mem:SI (match_operand:DI 1 "register_operand" "0")) 15377 (match_operand:SI 2 "register_operand" "a")) 15378 (set (match_operand:DI 0 "register_operand" "=D") 15379 (plus:DI (match_dup 1) 15380 (const_int 8))) 15381 (use (reg:SI 19))] 15382 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15383 "stosq" 15384 [(set_attr "type" "str") 15385 (set_attr "memory" "store") 15386 (set_attr "mode" "DI")]) 15387 15388(define_insn "strsetsi_1" 15389 [(set (mem:SI (match_operand:SI 1 "register_operand" "0")) 15390 (match_operand:SI 2 "register_operand" "a")) 15391 (set (match_operand:SI 0 "register_operand" "=D") 15392 (plus:SI (match_dup 1) 15393 (const_int 4))) 15394 (use (reg:SI 19))] 15395 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15396 "{stosl|stosd}" 15397 [(set_attr "type" "str") 15398 (set_attr "memory" "store") 15399 (set_attr "mode" "SI")]) 15400 15401(define_insn "strsetsi_rex_1" 15402 [(set (mem:SI (match_operand:DI 1 "register_operand" "0")) 15403 (match_operand:SI 2 "register_operand" "a")) 15404 (set (match_operand:DI 0 "register_operand" "=D") 15405 (plus:DI (match_dup 1) 15406 (const_int 4))) 15407 (use (reg:SI 19))] 15408 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15409 "{stosl|stosd}" 15410 [(set_attr "type" "str") 15411 (set_attr "memory" "store") 15412 (set_attr "mode" "SI")]) 15413 15414(define_insn "strsethi_1" 15415 [(set (mem:HI (match_operand:SI 1 "register_operand" "0")) 15416 (match_operand:HI 2 "register_operand" "a")) 15417 (set (match_operand:SI 0 "register_operand" "=D") 15418 (plus:SI (match_dup 1) 15419 (const_int 2))) 15420 (use (reg:SI 19))] 15421 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15422 "stosw" 15423 [(set_attr "type" "str") 15424 (set_attr "memory" "store") 15425 (set_attr "mode" "HI")]) 15426 15427(define_insn "strsethi_rex_1" 15428 [(set (mem:HI (match_operand:DI 1 "register_operand" "0")) 15429 (match_operand:HI 2 "register_operand" "a")) 15430 (set (match_operand:DI 0 "register_operand" "=D") 15431 (plus:DI (match_dup 1) 15432 (const_int 2))) 15433 (use (reg:SI 19))] 15434 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15435 "stosw" 15436 [(set_attr "type" "str") 15437 (set_attr "memory" "store") 15438 (set_attr "mode" "HI")]) 15439 15440(define_insn "strsetqi_1" 15441 [(set (mem:QI (match_operand:SI 1 "register_operand" "0")) 15442 (match_operand:QI 2 "register_operand" "a")) 15443 (set (match_operand:SI 0 "register_operand" "=D") 15444 (plus:SI (match_dup 1) 15445 (const_int 1))) 15446 (use (reg:SI 19))] 15447 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15448 "stosb" 15449 [(set_attr "type" "str") 15450 (set_attr "memory" "store") 15451 (set_attr "mode" "QI")]) 15452 15453(define_insn "strsetqi_rex_1" 15454 [(set (mem:QI (match_operand:DI 1 "register_operand" "0")) 15455 (match_operand:QI 2 "register_operand" "a")) 15456 (set (match_operand:DI 0 "register_operand" "=D") 15457 (plus:DI (match_dup 1) 15458 (const_int 1))) 15459 (use (reg:SI 19))] 15460 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" 15461 "stosb" 15462 [(set_attr "type" "str") 15463 (set_attr "memory" "store") 15464 (set_attr "mode" "QI")]) 15465 15466(define_insn "rep_stosdi_rex64" 15467 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0)) 15468 (set (match_operand:DI 0 "register_operand" "=D") 15469 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1") 15470 (const_int 3)) 15471 (match_operand:DI 3 "register_operand" "0"))) 15472 (set (mem:BLK (match_dup 3)) 15473 (const_int 0)) 15474 (use (match_operand:DI 2 "register_operand" "a")) 15475 (use (match_dup 4)) 15476 (use (reg:SI 19))] 15477 "TARGET_64BIT" 15478 "{rep\;stosq|rep stosq}" 15479 [(set_attr "type" "str") 15480 (set_attr "prefix_rep" "1") 15481 (set_attr "memory" "store") 15482 (set_attr "mode" "DI")]) 15483 15484(define_insn "rep_stossi" 15485 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0)) 15486 (set (match_operand:SI 0 "register_operand" "=D") 15487 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1") 15488 (const_int 2)) 15489 (match_operand:SI 3 "register_operand" "0"))) 15490 (set (mem:BLK (match_dup 3)) 15491 (const_int 0)) 15492 (use (match_operand:SI 2 "register_operand" "a")) 15493 (use (match_dup 4)) 15494 (use (reg:SI 19))] 15495 "!TARGET_64BIT" 15496 "{rep\;stosl|rep stosd}" 15497 [(set_attr "type" "str") 15498 (set_attr "prefix_rep" "1") 15499 (set_attr "memory" "store") 15500 (set_attr "mode" "SI")]) 15501 15502(define_insn "rep_stossi_rex64" 15503 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0)) 15504 (set (match_operand:DI 0 "register_operand" "=D") 15505 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1") 15506 (const_int 2)) 15507 (match_operand:DI 3 "register_operand" "0"))) 15508 (set (mem:BLK (match_dup 3)) 15509 (const_int 0)) 15510 (use (match_operand:SI 2 "register_operand" "a")) 15511 (use (match_dup 4)) 15512 (use (reg:SI 19))] 15513 "TARGET_64BIT" 15514 "{rep\;stosl|rep stosd}" 15515 [(set_attr "type" "str") 15516 (set_attr "prefix_rep" "1") 15517 (set_attr "memory" "store") 15518 (set_attr "mode" "SI")]) 15519 15520(define_insn "rep_stosqi" 15521 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0)) 15522 (set (match_operand:SI 0 "register_operand" "=D") 15523 (plus:SI (match_operand:SI 3 "register_operand" "0") 15524 (match_operand:SI 4 "register_operand" "1"))) 15525 (set (mem:BLK (match_dup 3)) 15526 (const_int 0)) 15527 (use (match_operand:QI 2 "register_operand" "a")) 15528 (use (match_dup 4)) 15529 (use (reg:SI 19))] 15530 "!TARGET_64BIT" 15531 "{rep\;stosb|rep stosb}" 15532 [(set_attr "type" "str") 15533 (set_attr "prefix_rep" "1") 15534 (set_attr "memory" "store") 15535 (set_attr "mode" "QI")]) 15536 15537(define_insn "rep_stosqi_rex64" 15538 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0)) 15539 (set (match_operand:DI 0 "register_operand" "=D") 15540 (plus:DI (match_operand:DI 3 "register_operand" "0") 15541 (match_operand:DI 4 "register_operand" "1"))) 15542 (set (mem:BLK (match_dup 3)) 15543 (const_int 0)) 15544 (use (match_operand:QI 2 "register_operand" "a")) 15545 (use (match_dup 4)) 15546 (use (reg:DI 19))] 15547 "TARGET_64BIT" 15548 "{rep\;stosb|rep stosb}" 15549 [(set_attr "type" "str") 15550 (set_attr "prefix_rep" "1") 15551 (set_attr "memory" "store") 15552 (set_attr "mode" "QI")]) 15553 15554(define_expand "cmpstrsi" 15555 [(set (match_operand:SI 0 "register_operand" "") 15556 (compare:SI (match_operand:BLK 1 "general_operand" "") 15557 (match_operand:BLK 2 "general_operand" ""))) 15558 (use (match_operand 3 "general_operand" "")) 15559 (use (match_operand 4 "immediate_operand" ""))] 15560 "" 15561{ 15562 rtx addr1, addr2, out, outlow, count, countreg, align; 15563 15564 out = operands[0]; 15565 if (GET_CODE (out) != REG) 15566 out = gen_reg_rtx (SImode); 15567 15568 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); 15569 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0)); 15570 15571 count = operands[3]; 15572 countreg = ix86_zero_extend_to_Pmode (count); 15573 15574 /* %%% Iff we are testing strict equality, we can use known alignment 15575 to good advantage. This may be possible with combine, particularly 15576 once cc0 is dead. */ 15577 align = operands[4]; 15578 15579 emit_insn (gen_cld ()); 15580 if (GET_CODE (count) == CONST_INT) 15581 { 15582 if (INTVAL (count) == 0) 15583 { 15584 emit_move_insn (operands[0], const0_rtx); 15585 DONE; 15586 } 15587 if (TARGET_64BIT) 15588 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align, 15589 addr1, addr2, countreg)); 15590 else 15591 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align, 15592 addr1, addr2, countreg)); 15593 } 15594 else 15595 { 15596 if (TARGET_64BIT) 15597 { 15598 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg)); 15599 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align, 15600 addr1, addr2, countreg)); 15601 } 15602 else 15603 { 15604 emit_insn (gen_cmpsi_1 (countreg, countreg)); 15605 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align, 15606 addr1, addr2, countreg)); 15607 } 15608 } 15609 15610 outlow = gen_lowpart (QImode, out); 15611 emit_insn (gen_cmpintqi (outlow)); 15612 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow)); 15613 15614 if (operands[0] != out) 15615 emit_move_insn (operands[0], out); 15616 15617 DONE; 15618}) 15619 15620;; Produce a tri-state integer (-1, 0, 1) from condition codes. 15621 15622(define_expand "cmpintqi" 15623 [(set (match_dup 1) 15624 (gtu:QI (reg:CC 17) (const_int 0))) 15625 (set (match_dup 2) 15626 (ltu:QI (reg:CC 17) (const_int 0))) 15627 (parallel [(set (match_operand:QI 0 "register_operand" "") 15628 (minus:QI (match_dup 1) 15629 (match_dup 2))) 15630 (clobber (reg:CC 17))])] 15631 "" 15632 "operands[1] = gen_reg_rtx (QImode); 15633 operands[2] = gen_reg_rtx (QImode);") 15634 15635;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is 15636;; zero. Emit extra code to make sure that a zero-length compare is EQ. 15637 15638(define_insn "cmpstrqi_nz_1" 15639 [(set (reg:CC 17) 15640 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0")) 15641 (mem:BLK (match_operand:SI 5 "register_operand" "1")))) 15642 (use (match_operand:SI 6 "register_operand" "2")) 15643 (use (match_operand:SI 3 "immediate_operand" "i")) 15644 (use (reg:SI 19)) 15645 (clobber (match_operand:SI 0 "register_operand" "=S")) 15646 (clobber (match_operand:SI 1 "register_operand" "=D")) 15647 (clobber (match_operand:SI 2 "register_operand" "=c"))] 15648 "!TARGET_64BIT" 15649 "repz{\;| }cmpsb" 15650 [(set_attr "type" "str") 15651 (set_attr "mode" "QI") 15652 (set_attr "prefix_rep" "1")]) 15653 15654(define_insn "cmpstrqi_nz_rex_1" 15655 [(set (reg:CC 17) 15656 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0")) 15657 (mem:BLK (match_operand:DI 5 "register_operand" "1")))) 15658 (use (match_operand:DI 6 "register_operand" "2")) 15659 (use (match_operand:SI 3 "immediate_operand" "i")) 15660 (use (reg:SI 19)) 15661 (clobber (match_operand:DI 0 "register_operand" "=S")) 15662 (clobber (match_operand:DI 1 "register_operand" "=D")) 15663 (clobber (match_operand:DI 2 "register_operand" "=c"))] 15664 "TARGET_64BIT" 15665 "repz{\;| }cmpsb" 15666 [(set_attr "type" "str") 15667 (set_attr "mode" "QI") 15668 (set_attr "prefix_rep" "1")]) 15669 15670;; The same, but the count is not known to not be zero. 15671 15672(define_insn "cmpstrqi_1" 15673 [(set (reg:CC 17) 15674 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2") 15675 (const_int 0)) 15676 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0")) 15677 (mem:BLK (match_operand:SI 5 "register_operand" "1"))) 15678 (const_int 0))) 15679 (use (match_operand:SI 3 "immediate_operand" "i")) 15680 (use (reg:CC 17)) 15681 (use (reg:SI 19)) 15682 (clobber (match_operand:SI 0 "register_operand" "=S")) 15683 (clobber (match_operand:SI 1 "register_operand" "=D")) 15684 (clobber (match_operand:SI 2 "register_operand" "=c"))] 15685 "!TARGET_64BIT" 15686 "repz{\;| }cmpsb" 15687 [(set_attr "type" "str") 15688 (set_attr "mode" "QI") 15689 (set_attr "prefix_rep" "1")]) 15690 15691(define_insn "cmpstrqi_rex_1" 15692 [(set (reg:CC 17) 15693 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2") 15694 (const_int 0)) 15695 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0")) 15696 (mem:BLK (match_operand:DI 5 "register_operand" "1"))) 15697 (const_int 0))) 15698 (use (match_operand:SI 3 "immediate_operand" "i")) 15699 (use (reg:CC 17)) 15700 (use (reg:SI 19)) 15701 (clobber (match_operand:DI 0 "register_operand" "=S")) 15702 (clobber (match_operand:DI 1 "register_operand" "=D")) 15703 (clobber (match_operand:DI 2 "register_operand" "=c"))] 15704 "TARGET_64BIT" 15705 "repz{\;| }cmpsb" 15706 [(set_attr "type" "str") 15707 (set_attr "mode" "QI") 15708 (set_attr "prefix_rep" "1")]) 15709 15710(define_expand "strlensi" 15711 [(set (match_operand:SI 0 "register_operand" "") 15712 (unspec:SI [(match_operand:BLK 1 "general_operand" "") 15713 (match_operand:QI 2 "immediate_operand" "") 15714 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))] 15715 "" 15716{ 15717 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3])) 15718 DONE; 15719 else 15720 FAIL; 15721}) 15722 15723(define_expand "strlendi" 15724 [(set (match_operand:DI 0 "register_operand" "") 15725 (unspec:DI [(match_operand:BLK 1 "general_operand" "") 15726 (match_operand:QI 2 "immediate_operand" "") 15727 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))] 15728 "" 15729{ 15730 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3])) 15731 DONE; 15732 else 15733 FAIL; 15734}) 15735 15736(define_insn "strlenqi_1" 15737 [(set (match_operand:SI 0 "register_operand" "=&c") 15738 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1")) 15739 (match_operand:QI 2 "register_operand" "a") 15740 (match_operand:SI 3 "immediate_operand" "i") 15741 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS)) 15742 (use (reg:SI 19)) 15743 (clobber (match_operand:SI 1 "register_operand" "=D")) 15744 (clobber (reg:CC 17))] 15745 "!TARGET_64BIT" 15746 "repnz{\;| }scasb" 15747 [(set_attr "type" "str") 15748 (set_attr "mode" "QI") 15749 (set_attr "prefix_rep" "1")]) 15750 15751(define_insn "strlenqi_rex_1" 15752 [(set (match_operand:DI 0 "register_operand" "=&c") 15753 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1")) 15754 (match_operand:QI 2 "register_operand" "a") 15755 (match_operand:DI 3 "immediate_operand" "i") 15756 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS)) 15757 (use (reg:SI 19)) 15758 (clobber (match_operand:DI 1 "register_operand" "=D")) 15759 (clobber (reg:CC 17))] 15760 "TARGET_64BIT" 15761 "repnz{\;| }scasb" 15762 [(set_attr "type" "str") 15763 (set_attr "mode" "QI") 15764 (set_attr "prefix_rep" "1")]) 15765 15766;; Peephole optimizations to clean up after cmpstr*. This should be 15767;; handled in combine, but it is not currently up to the task. 15768;; When used for their truth value, the cmpstr* expanders generate 15769;; code like this: 15770;; 15771;; repz cmpsb 15772;; seta %al 15773;; setb %dl 15774;; cmpb %al, %dl 15775;; jcc label 15776;; 15777;; The intermediate three instructions are unnecessary. 15778 15779;; This one handles cmpstr*_nz_1... 15780(define_peephole2 15781 [(parallel[ 15782 (set (reg:CC 17) 15783 (compare:CC (mem:BLK (match_operand 4 "register_operand" "")) 15784 (mem:BLK (match_operand 5 "register_operand" "")))) 15785 (use (match_operand 6 "register_operand" "")) 15786 (use (match_operand:SI 3 "immediate_operand" "")) 15787 (use (reg:SI 19)) 15788 (clobber (match_operand 0 "register_operand" "")) 15789 (clobber (match_operand 1 "register_operand" "")) 15790 (clobber (match_operand 2 "register_operand" ""))]) 15791 (set (match_operand:QI 7 "register_operand" "") 15792 (gtu:QI (reg:CC 17) (const_int 0))) 15793 (set (match_operand:QI 8 "register_operand" "") 15794 (ltu:QI (reg:CC 17) (const_int 0))) 15795 (set (reg 17) 15796 (compare (match_dup 7) (match_dup 8))) 15797 ] 15798 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])" 15799 [(parallel[ 15800 (set (reg:CC 17) 15801 (compare:CC (mem:BLK (match_dup 4)) 15802 (mem:BLK (match_dup 5)))) 15803 (use (match_dup 6)) 15804 (use (match_dup 3)) 15805 (use (reg:SI 19)) 15806 (clobber (match_dup 0)) 15807 (clobber (match_dup 1)) 15808 (clobber (match_dup 2))])] 15809 "") 15810 15811;; ...and this one handles cmpstr*_1. 15812(define_peephole2 15813 [(parallel[ 15814 (set (reg:CC 17) 15815 (if_then_else:CC (ne (match_operand 6 "register_operand" "") 15816 (const_int 0)) 15817 (compare:CC (mem:BLK (match_operand 4 "register_operand" "")) 15818 (mem:BLK (match_operand 5 "register_operand" ""))) 15819 (const_int 0))) 15820 (use (match_operand:SI 3 "immediate_operand" "")) 15821 (use (reg:CC 17)) 15822 (use (reg:SI 19)) 15823 (clobber (match_operand 0 "register_operand" "")) 15824 (clobber (match_operand 1 "register_operand" "")) 15825 (clobber (match_operand 2 "register_operand" ""))]) 15826 (set (match_operand:QI 7 "register_operand" "") 15827 (gtu:QI (reg:CC 17) (const_int 0))) 15828 (set (match_operand:QI 8 "register_operand" "") 15829 (ltu:QI (reg:CC 17) (const_int 0))) 15830 (set (reg 17) 15831 (compare (match_dup 7) (match_dup 8))) 15832 ] 15833 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])" 15834 [(parallel[ 15835 (set (reg:CC 17) 15836 (if_then_else:CC (ne (match_dup 6) 15837 (const_int 0)) 15838 (compare:CC (mem:BLK (match_dup 4)) 15839 (mem:BLK (match_dup 5))) 15840 (const_int 0))) 15841 (use (match_dup 3)) 15842 (use (reg:CC 17)) 15843 (use (reg:SI 19)) 15844 (clobber (match_dup 0)) 15845 (clobber (match_dup 1)) 15846 (clobber (match_dup 2))])] 15847 "") 15848 15849 15850 15851;; Conditional move instructions. 15852 15853(define_expand "movdicc" 15854 [(set (match_operand:DI 0 "register_operand" "") 15855 (if_then_else:DI (match_operand 1 "comparison_operator" "") 15856 (match_operand:DI 2 "general_operand" "") 15857 (match_operand:DI 3 "general_operand" "")))] 15858 "TARGET_64BIT" 15859 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;") 15860 15861(define_insn "x86_movdicc_0_m1_rex64" 15862 [(set (match_operand:DI 0 "register_operand" "=r") 15863 (if_then_else:DI (ltu (reg:CC 17) (const_int 0)) 15864 (const_int -1) 15865 (const_int 0))) 15866 (clobber (reg:CC 17))] 15867 "TARGET_64BIT" 15868 "sbb{q}\t%0, %0" 15869 ; Since we don't have the proper number of operands for an alu insn, 15870 ; fill in all the blanks. 15871 [(set_attr "type" "alu") 15872 (set_attr "pent_pair" "pu") 15873 (set_attr "memory" "none") 15874 (set_attr "imm_disp" "false") 15875 (set_attr "mode" "DI") 15876 (set_attr "length_immediate" "0")]) 15877 15878(define_insn "*movdicc_c_rex64" 15879 [(set (match_operand:DI 0 "register_operand" "=r,r") 15880 (if_then_else:DI (match_operator 1 "ix86_comparison_operator" 15881 [(reg 17) (const_int 0)]) 15882 (match_operand:DI 2 "nonimmediate_operand" "rm,0") 15883 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))] 15884 "TARGET_64BIT && TARGET_CMOVE 15885 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 15886 "@ 15887 cmov%O2%C1\t{%2, %0|%0, %2} 15888 cmov%O2%c1\t{%3, %0|%0, %3}" 15889 [(set_attr "type" "icmov") 15890 (set_attr "mode" "DI")]) 15891 15892(define_expand "movsicc" 15893 [(set (match_operand:SI 0 "register_operand" "") 15894 (if_then_else:SI (match_operand 1 "comparison_operator" "") 15895 (match_operand:SI 2 "general_operand" "") 15896 (match_operand:SI 3 "general_operand" "")))] 15897 "" 15898 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;") 15899 15900;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing 15901;; the register first winds up with `sbbl $0,reg', which is also weird. 15902;; So just document what we're doing explicitly. 15903 15904(define_insn "x86_movsicc_0_m1" 15905 [(set (match_operand:SI 0 "register_operand" "=r") 15906 (if_then_else:SI (ltu (reg:CC 17) (const_int 0)) 15907 (const_int -1) 15908 (const_int 0))) 15909 (clobber (reg:CC 17))] 15910 "" 15911 "sbb{l}\t%0, %0" 15912 ; Since we don't have the proper number of operands for an alu insn, 15913 ; fill in all the blanks. 15914 [(set_attr "type" "alu") 15915 (set_attr "pent_pair" "pu") 15916 (set_attr "memory" "none") 15917 (set_attr "imm_disp" "false") 15918 (set_attr "mode" "SI") 15919 (set_attr "length_immediate" "0")]) 15920 15921(define_insn "*movsicc_noc" 15922 [(set (match_operand:SI 0 "register_operand" "=r,r") 15923 (if_then_else:SI (match_operator 1 "ix86_comparison_operator" 15924 [(reg 17) (const_int 0)]) 15925 (match_operand:SI 2 "nonimmediate_operand" "rm,0") 15926 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))] 15927 "TARGET_CMOVE 15928 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 15929 "@ 15930 cmov%O2%C1\t{%2, %0|%0, %2} 15931 cmov%O2%c1\t{%3, %0|%0, %3}" 15932 [(set_attr "type" "icmov") 15933 (set_attr "mode" "SI")]) 15934 15935(define_expand "movhicc" 15936 [(set (match_operand:HI 0 "register_operand" "") 15937 (if_then_else:HI (match_operand 1 "comparison_operator" "") 15938 (match_operand:HI 2 "nonimmediate_operand" "") 15939 (match_operand:HI 3 "nonimmediate_operand" "")))] 15940 "TARGET_CMOVE && TARGET_HIMODE_MATH" 15941 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;") 15942 15943(define_insn "*movhicc_noc" 15944 [(set (match_operand:HI 0 "register_operand" "=r,r") 15945 (if_then_else:HI (match_operator 1 "ix86_comparison_operator" 15946 [(reg 17) (const_int 0)]) 15947 (match_operand:HI 2 "nonimmediate_operand" "rm,0") 15948 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))] 15949 "TARGET_CMOVE 15950 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 15951 "@ 15952 cmov%O2%C1\t{%2, %0|%0, %2} 15953 cmov%O2%c1\t{%3, %0|%0, %3}" 15954 [(set_attr "type" "icmov") 15955 (set_attr "mode" "HI")]) 15956 15957(define_expand "movsfcc" 15958 [(set (match_operand:SF 0 "register_operand" "") 15959 (if_then_else:SF (match_operand 1 "comparison_operator" "") 15960 (match_operand:SF 2 "register_operand" "") 15961 (match_operand:SF 3 "register_operand" "")))] 15962 "TARGET_CMOVE" 15963 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") 15964 15965(define_insn "*movsfcc_1" 15966 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r") 15967 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 15968 [(reg 17) (const_int 0)]) 15969 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0") 15970 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))] 15971 "TARGET_CMOVE 15972 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 15973 "@ 15974 fcmov%F1\t{%2, %0|%0, %2} 15975 fcmov%f1\t{%3, %0|%0, %3} 15976 cmov%O2%C1\t{%2, %0|%0, %2} 15977 cmov%O2%c1\t{%3, %0|%0, %3}" 15978 [(set_attr "type" "fcmov,fcmov,icmov,icmov") 15979 (set_attr "mode" "SF,SF,SI,SI")]) 15980 15981(define_expand "movdfcc" 15982 [(set (match_operand:DF 0 "register_operand" "") 15983 (if_then_else:DF (match_operand 1 "comparison_operator" "") 15984 (match_operand:DF 2 "register_operand" "") 15985 (match_operand:DF 3 "register_operand" "")))] 15986 "TARGET_CMOVE" 15987 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") 15988 15989(define_insn "*movdfcc_1" 15990 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r") 15991 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 15992 [(reg 17) (const_int 0)]) 15993 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0") 15994 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))] 15995 "!TARGET_64BIT && TARGET_CMOVE 15996 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 15997 "@ 15998 fcmov%F1\t{%2, %0|%0, %2} 15999 fcmov%f1\t{%3, %0|%0, %3} 16000 # 16001 #" 16002 [(set_attr "type" "fcmov,fcmov,multi,multi") 16003 (set_attr "mode" "DF")]) 16004 16005(define_insn "*movdfcc_1_rex64" 16006 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r") 16007 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 16008 [(reg 17) (const_int 0)]) 16009 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0") 16010 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))] 16011 "TARGET_64BIT && TARGET_CMOVE 16012 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 16013 "@ 16014 fcmov%F1\t{%2, %0|%0, %2} 16015 fcmov%f1\t{%3, %0|%0, %3} 16016 cmov%O2%C1\t{%2, %0|%0, %2} 16017 cmov%O2%c1\t{%3, %0|%0, %3}" 16018 [(set_attr "type" "fcmov,fcmov,icmov,icmov") 16019 (set_attr "mode" "DF")]) 16020 16021(define_split 16022 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "") 16023 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 16024 [(match_operand 4 "" "") (const_int 0)]) 16025 (match_operand:DF 2 "nonimmediate_operand" "") 16026 (match_operand:DF 3 "nonimmediate_operand" "")))] 16027 "!TARGET_64BIT && reload_completed" 16028 [(set (match_dup 2) 16029 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)]) 16030 (match_dup 5) 16031 (match_dup 7))) 16032 (set (match_dup 3) 16033 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)]) 16034 (match_dup 6) 16035 (match_dup 8)))] 16036 "split_di (operands+2, 1, operands+5, operands+6); 16037 split_di (operands+3, 1, operands+7, operands+8); 16038 split_di (operands, 1, operands+2, operands+3);") 16039 16040(define_expand "movxfcc" 16041 [(set (match_operand:XF 0 "register_operand" "") 16042 (if_then_else:XF (match_operand 1 "comparison_operator" "") 16043 (match_operand:XF 2 "register_operand" "") 16044 (match_operand:XF 3 "register_operand" "")))] 16045 "!TARGET_64BIT && TARGET_CMOVE" 16046 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") 16047 16048(define_expand "movtfcc" 16049 [(set (match_operand:TF 0 "register_operand" "") 16050 (if_then_else:TF (match_operand 1 "comparison_operator" "") 16051 (match_operand:TF 2 "register_operand" "") 16052 (match_operand:TF 3 "register_operand" "")))] 16053 "TARGET_CMOVE" 16054 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") 16055 16056(define_insn "*movxfcc_1" 16057 [(set (match_operand:XF 0 "register_operand" "=f,f") 16058 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator" 16059 [(reg 17) (const_int 0)]) 16060 (match_operand:XF 2 "register_operand" "f,0") 16061 (match_operand:XF 3 "register_operand" "0,f")))] 16062 "!TARGET_64BIT && TARGET_CMOVE" 16063 "@ 16064 fcmov%F1\t{%2, %0|%0, %2} 16065 fcmov%f1\t{%3, %0|%0, %3}" 16066 [(set_attr "type" "fcmov") 16067 (set_attr "mode" "XF")]) 16068 16069(define_insn "*movtfcc_1" 16070 [(set (match_operand:TF 0 "register_operand" "=f,f") 16071 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator" 16072 [(reg 17) (const_int 0)]) 16073 (match_operand:TF 2 "register_operand" "f,0") 16074 (match_operand:TF 3 "register_operand" "0,f")))] 16075 "TARGET_CMOVE" 16076 "@ 16077 fcmov%F1\t{%2, %0|%0, %2} 16078 fcmov%f1\t{%3, %0|%0, %3}" 16079 [(set_attr "type" "fcmov") 16080 (set_attr "mode" "XF")]) 16081 16082(define_expand "minsf3" 16083 [(parallel [ 16084 (set (match_operand:SF 0 "register_operand" "") 16085 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "") 16086 (match_operand:SF 2 "nonimmediate_operand" "")) 16087 (match_dup 1) 16088 (match_dup 2))) 16089 (clobber (reg:CC 17))])] 16090 "TARGET_SSE" 16091 "") 16092 16093(define_insn "*minsf" 16094 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x") 16095 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x") 16096 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0")) 16097 (match_dup 1) 16098 (match_dup 2))) 16099 (clobber (reg:CC 17))] 16100 "TARGET_SSE && TARGET_IEEE_FP" 16101 "#") 16102 16103(define_insn "*minsf_nonieee" 16104 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x") 16105 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0") 16106 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) 16107 (match_dup 1) 16108 (match_dup 2))) 16109 (clobber (reg:CC 17))] 16110 "TARGET_SSE && !TARGET_IEEE_FP 16111 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 16112 "#") 16113 16114(define_split 16115 [(set (match_operand:SF 0 "register_operand" "") 16116 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "") 16117 (match_operand:SF 2 "nonimmediate_operand" "")) 16118 (match_operand:SF 3 "register_operand" "") 16119 (match_operand:SF 4 "nonimmediate_operand" ""))) 16120 (clobber (reg:CC 17))] 16121 "SSE_REG_P (operands[0]) && reload_completed 16122 && ((operands_match_p (operands[1], operands[3]) 16123 && operands_match_p (operands[2], operands[4])) 16124 || (operands_match_p (operands[1], operands[4]) 16125 && operands_match_p (operands[2], operands[3])))" 16126 [(set (match_dup 0) 16127 (if_then_else:SF (lt (match_dup 1) 16128 (match_dup 2)) 16129 (match_dup 1) 16130 (match_dup 2)))]) 16131 16132;; We can't represent the LT test directly. Do this by swapping the operands. 16133 16134(define_split 16135 [(set (match_operand:SF 0 "fp_register_operand" "") 16136 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "") 16137 (match_operand:SF 2 "register_operand" "")) 16138 (match_operand:SF 3 "register_operand" "") 16139 (match_operand:SF 4 "register_operand" ""))) 16140 (clobber (reg:CC 17))] 16141 "reload_completed 16142 && ((operands_match_p (operands[1], operands[3]) 16143 && operands_match_p (operands[2], operands[4])) 16144 || (operands_match_p (operands[1], operands[4]) 16145 && operands_match_p (operands[2], operands[3])))" 16146 [(set (reg:CCFP 17) 16147 (compare:CCFP (match_dup 2) 16148 (match_dup 1))) 16149 (set (match_dup 0) 16150 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0)) 16151 (match_dup 1) 16152 (match_dup 2)))]) 16153 16154(define_insn "*minsf_sse" 16155 [(set (match_operand:SF 0 "register_operand" "=x") 16156 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0") 16157 (match_operand:SF 2 "nonimmediate_operand" "xm")) 16158 (match_dup 1) 16159 (match_dup 2)))] 16160 "TARGET_SSE && reload_completed" 16161 "minss\t{%2, %0|%0, %2}" 16162 [(set_attr "type" "sse") 16163 (set_attr "mode" "SF")]) 16164 16165(define_expand "mindf3" 16166 [(parallel [ 16167 (set (match_operand:DF 0 "register_operand" "") 16168 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "") 16169 (match_operand:DF 2 "nonimmediate_operand" "")) 16170 (match_dup 1) 16171 (match_dup 2))) 16172 (clobber (reg:CC 17))])] 16173 "TARGET_SSE2 && TARGET_SSE_MATH" 16174 "#") 16175 16176(define_insn "*mindf" 16177 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y") 16178 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y") 16179 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0")) 16180 (match_dup 1) 16181 (match_dup 2))) 16182 (clobber (reg:CC 17))] 16183 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH" 16184 "#") 16185 16186(define_insn "*mindf_nonieee" 16187 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y") 16188 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0") 16189 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) 16190 (match_dup 1) 16191 (match_dup 2))) 16192 (clobber (reg:CC 17))] 16193 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP 16194 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 16195 "#") 16196 16197(define_split 16198 [(set (match_operand:DF 0 "register_operand" "") 16199 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "") 16200 (match_operand:DF 2 "nonimmediate_operand" "")) 16201 (match_operand:DF 3 "register_operand" "") 16202 (match_operand:DF 4 "nonimmediate_operand" ""))) 16203 (clobber (reg:CC 17))] 16204 "SSE_REG_P (operands[0]) && reload_completed 16205 && ((operands_match_p (operands[1], operands[3]) 16206 && operands_match_p (operands[2], operands[4])) 16207 || (operands_match_p (operands[1], operands[4]) 16208 && operands_match_p (operands[2], operands[3])))" 16209 [(set (match_dup 0) 16210 (if_then_else:DF (lt (match_dup 1) 16211 (match_dup 2)) 16212 (match_dup 1) 16213 (match_dup 2)))]) 16214 16215;; We can't represent the LT test directly. Do this by swapping the operands. 16216(define_split 16217 [(set (match_operand:DF 0 "fp_register_operand" "") 16218 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "") 16219 (match_operand:DF 2 "register_operand" "")) 16220 (match_operand:DF 3 "register_operand" "") 16221 (match_operand:DF 4 "register_operand" ""))) 16222 (clobber (reg:CC 17))] 16223 "reload_completed 16224 && ((operands_match_p (operands[1], operands[3]) 16225 && operands_match_p (operands[2], operands[4])) 16226 || (operands_match_p (operands[1], operands[4]) 16227 && operands_match_p (operands[2], operands[3])))" 16228 [(set (reg:CCFP 17) 16229 (compare:CCFP (match_dup 2) 16230 (match_dup 2))) 16231 (set (match_dup 0) 16232 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0)) 16233 (match_dup 1) 16234 (match_dup 2)))]) 16235 16236(define_insn "*mindf_sse" 16237 [(set (match_operand:DF 0 "register_operand" "=Y") 16238 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0") 16239 (match_operand:DF 2 "nonimmediate_operand" "Ym")) 16240 (match_dup 1) 16241 (match_dup 2)))] 16242 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed" 16243 "minsd\t{%2, %0|%0, %2}" 16244 [(set_attr "type" "sse") 16245 (set_attr "mode" "DF")]) 16246 16247(define_expand "maxsf3" 16248 [(parallel [ 16249 (set (match_operand:SF 0 "register_operand" "") 16250 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "") 16251 (match_operand:SF 2 "nonimmediate_operand" "")) 16252 (match_dup 1) 16253 (match_dup 2))) 16254 (clobber (reg:CC 17))])] 16255 "TARGET_SSE" 16256 "#") 16257 16258(define_insn "*maxsf" 16259 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x") 16260 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x") 16261 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0")) 16262 (match_dup 1) 16263 (match_dup 2))) 16264 (clobber (reg:CC 17))] 16265 "TARGET_SSE && TARGET_IEEE_FP" 16266 "#") 16267 16268(define_insn "*maxsf_nonieee" 16269 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x") 16270 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0") 16271 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) 16272 (match_dup 1) 16273 (match_dup 2))) 16274 (clobber (reg:CC 17))] 16275 "TARGET_SSE && !TARGET_IEEE_FP 16276 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 16277 "#") 16278 16279(define_split 16280 [(set (match_operand:SF 0 "register_operand" "") 16281 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "") 16282 (match_operand:SF 2 "nonimmediate_operand" "")) 16283 (match_operand:SF 3 "register_operand" "") 16284 (match_operand:SF 4 "nonimmediate_operand" ""))) 16285 (clobber (reg:CC 17))] 16286 "SSE_REG_P (operands[0]) && reload_completed 16287 && ((operands_match_p (operands[1], operands[3]) 16288 && operands_match_p (operands[2], operands[4])) 16289 || (operands_match_p (operands[1], operands[4]) 16290 && operands_match_p (operands[2], operands[3])))" 16291 [(set (match_dup 0) 16292 (if_then_else:SF (gt (match_dup 1) 16293 (match_dup 2)) 16294 (match_dup 1) 16295 (match_dup 2)))]) 16296 16297(define_split 16298 [(set (match_operand:SF 0 "fp_register_operand" "") 16299 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "") 16300 (match_operand:SF 2 "register_operand" "")) 16301 (match_operand:SF 3 "register_operand" "") 16302 (match_operand:SF 4 "register_operand" ""))) 16303 (clobber (reg:CC 17))] 16304 "reload_completed 16305 && ((operands_match_p (operands[1], operands[3]) 16306 && operands_match_p (operands[2], operands[4])) 16307 || (operands_match_p (operands[1], operands[4]) 16308 && operands_match_p (operands[2], operands[3])))" 16309 [(set (reg:CCFP 17) 16310 (compare:CCFP (match_dup 1) 16311 (match_dup 2))) 16312 (set (match_dup 0) 16313 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0)) 16314 (match_dup 1) 16315 (match_dup 2)))]) 16316 16317(define_insn "*maxsf_sse" 16318 [(set (match_operand:SF 0 "register_operand" "=x") 16319 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0") 16320 (match_operand:SF 2 "nonimmediate_operand" "xm")) 16321 (match_dup 1) 16322 (match_dup 2)))] 16323 "TARGET_SSE && reload_completed" 16324 "maxss\t{%2, %0|%0, %2}" 16325 [(set_attr "type" "sse") 16326 (set_attr "mode" "SF")]) 16327 16328(define_expand "maxdf3" 16329 [(parallel [ 16330 (set (match_operand:DF 0 "register_operand" "") 16331 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "") 16332 (match_operand:DF 2 "nonimmediate_operand" "")) 16333 (match_dup 1) 16334 (match_dup 2))) 16335 (clobber (reg:CC 17))])] 16336 "TARGET_SSE2 && TARGET_SSE_MATH" 16337 "#") 16338 16339(define_insn "*maxdf" 16340 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y") 16341 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y") 16342 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0")) 16343 (match_dup 1) 16344 (match_dup 2))) 16345 (clobber (reg:CC 17))] 16346 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP" 16347 "#") 16348 16349(define_insn "*maxdf_nonieee" 16350 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y") 16351 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0") 16352 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) 16353 (match_dup 1) 16354 (match_dup 2))) 16355 (clobber (reg:CC 17))] 16356 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP 16357 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 16358 "#") 16359 16360(define_split 16361 [(set (match_operand:DF 0 "register_operand" "") 16362 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "") 16363 (match_operand:DF 2 "nonimmediate_operand" "")) 16364 (match_operand:DF 3 "register_operand" "") 16365 (match_operand:DF 4 "nonimmediate_operand" ""))) 16366 (clobber (reg:CC 17))] 16367 "SSE_REG_P (operands[0]) && reload_completed 16368 && ((operands_match_p (operands[1], operands[3]) 16369 && operands_match_p (operands[2], operands[4])) 16370 || (operands_match_p (operands[1], operands[4]) 16371 && operands_match_p (operands[2], operands[3])))" 16372 [(set (match_dup 0) 16373 (if_then_else:DF (gt (match_dup 1) 16374 (match_dup 2)) 16375 (match_dup 1) 16376 (match_dup 2)))]) 16377 16378(define_split 16379 [(set (match_operand:DF 0 "fp_register_operand" "") 16380 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "") 16381 (match_operand:DF 2 "register_operand" "")) 16382 (match_operand:DF 3 "register_operand" "") 16383 (match_operand:DF 4 "register_operand" ""))) 16384 (clobber (reg:CC 17))] 16385 "reload_completed 16386 && ((operands_match_p (operands[1], operands[3]) 16387 && operands_match_p (operands[2], operands[4])) 16388 || (operands_match_p (operands[1], operands[4]) 16389 && operands_match_p (operands[2], operands[3])))" 16390 [(set (reg:CCFP 17) 16391 (compare:CCFP (match_dup 1) 16392 (match_dup 2))) 16393 (set (match_dup 0) 16394 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0)) 16395 (match_dup 1) 16396 (match_dup 2)))]) 16397 16398(define_insn "*maxdf_sse" 16399 [(set (match_operand:DF 0 "register_operand" "=Y") 16400 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0") 16401 (match_operand:DF 2 "nonimmediate_operand" "Ym")) 16402 (match_dup 1) 16403 (match_dup 2)))] 16404 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed" 16405 "maxsd\t{%2, %0|%0, %2}" 16406 [(set_attr "type" "sse") 16407 (set_attr "mode" "DF")]) 16408 16409;; Misc patterns (?) 16410 16411;; This pattern exists to put a dependency on all ebp-based memory accesses. 16412;; Otherwise there will be nothing to keep 16413;; 16414;; [(set (reg ebp) (reg esp))] 16415;; [(set (reg esp) (plus (reg esp) (const_int -160000))) 16416;; (clobber (eflags)] 16417;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))] 16418;; 16419;; in proper program order. 16420(define_expand "pro_epilogue_adjust_stack" 16421 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r") 16422 (plus:SI (match_operand:SI 1 "register_operand" "0,r") 16423 (match_operand:SI 2 "immediate_operand" "i,i"))) 16424 (clobber (reg:CC 17)) 16425 (clobber (mem:BLK (scratch)))])] 16426 "" 16427{ 16428 if (TARGET_64BIT) 16429 { 16430 emit_insn (gen_pro_epilogue_adjust_stack_rex64 16431 (operands[0], operands[1], operands[2])); 16432 DONE; 16433 } 16434}) 16435 16436(define_insn "*pro_epilogue_adjust_stack_1" 16437 [(set (match_operand:SI 0 "register_operand" "=r,r") 16438 (plus:SI (match_operand:SI 1 "register_operand" "0,r") 16439 (match_operand:SI 2 "immediate_operand" "i,i"))) 16440 (clobber (reg:CC 17)) 16441 (clobber (mem:BLK (scratch)))] 16442 "!TARGET_64BIT" 16443{ 16444 switch (get_attr_type (insn)) 16445 { 16446 case TYPE_IMOV: 16447 return "mov{l}\t{%1, %0|%0, %1}"; 16448 16449 case TYPE_ALU: 16450 if (GET_CODE (operands[2]) == CONST_INT 16451 && (INTVAL (operands[2]) == 128 16452 || (INTVAL (operands[2]) < 0 16453 && INTVAL (operands[2]) != -128))) 16454 { 16455 operands[2] = GEN_INT (-INTVAL (operands[2])); 16456 return "sub{l}\t{%2, %0|%0, %2}"; 16457 } 16458 return "add{l}\t{%2, %0|%0, %2}"; 16459 16460 case TYPE_LEA: 16461 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); 16462 return "lea{l}\t{%a2, %0|%0, %a2}"; 16463 16464 default: 16465 abort (); 16466 } 16467} 16468 [(set (attr "type") 16469 (cond [(eq_attr "alternative" "0") 16470 (const_string "alu") 16471 (match_operand:SI 2 "const0_operand" "") 16472 (const_string "imov") 16473 ] 16474 (const_string "lea"))) 16475 (set_attr "mode" "SI")]) 16476 16477(define_insn "pro_epilogue_adjust_stack_rex64" 16478 [(set (match_operand:DI 0 "register_operand" "=r,r") 16479 (plus:DI (match_operand:DI 1 "register_operand" "0,r") 16480 (match_operand:DI 2 "x86_64_immediate_operand" "e,e"))) 16481 (clobber (reg:CC 17)) 16482 (clobber (mem:BLK (scratch)))] 16483 "TARGET_64BIT" 16484{ 16485 switch (get_attr_type (insn)) 16486 { 16487 case TYPE_IMOV: 16488 return "mov{q}\t{%1, %0|%0, %1}"; 16489 16490 case TYPE_ALU: 16491 if (GET_CODE (operands[2]) == CONST_INT 16492 && (INTVAL (operands[2]) == 128 16493 || (INTVAL (operands[2]) < 0 16494 && INTVAL (operands[2]) != -128))) 16495 { 16496 operands[2] = GEN_INT (-INTVAL (operands[2])); 16497 return "sub{q}\t{%2, %0|%0, %2}"; 16498 } 16499 return "add{q}\t{%2, %0|%0, %2}"; 16500 16501 case TYPE_LEA: 16502 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); 16503 return "lea{q}\t{%a2, %0|%0, %a2}"; 16504 16505 default: 16506 abort (); 16507 } 16508} 16509 [(set (attr "type") 16510 (cond [(eq_attr "alternative" "0") 16511 (const_string "alu") 16512 (match_operand:DI 2 "const0_operand" "") 16513 (const_string "imov") 16514 ] 16515 (const_string "lea"))) 16516 (set_attr "mode" "DI")]) 16517 16518 16519;; Placeholder for the conditional moves. This one is split either to SSE 16520;; based moves emulation or to usual cmove sequence. Little bit unfortunate 16521;; fact is that compares supported by the cmp??ss instructions are exactly 16522;; swapped of those supported by cmove sequence. 16523;; The EQ/NE comparisons also needs bit care, since they are not directly 16524;; supported by i387 comparisons and we do need to emit two conditional moves 16525;; in tandem. 16526 16527(define_insn "sse_movsfcc" 16528 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf") 16529 (if_then_else:SF (match_operator 1 "sse_comparison_operator" 16530 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f") 16531 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")]) 16532 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx") 16533 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx"))) 16534 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X")) 16535 (clobber (reg:CC 17))] 16536 "TARGET_SSE 16537 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM) 16538 && (!TARGET_IEEE_FP 16539 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))" 16540 "#") 16541 16542(define_insn "sse_movsfcc_eq" 16543 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf") 16544 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f") 16545 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f")) 16546 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx") 16547 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx"))) 16548 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X")) 16549 (clobber (reg:CC 17))] 16550 "TARGET_SSE 16551 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 16552 "#") 16553 16554(define_insn "sse_movdfcc" 16555 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf") 16556 (if_then_else:DF (match_operator 1 "sse_comparison_operator" 16557 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f") 16558 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")]) 16559 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY") 16560 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY"))) 16561 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X")) 16562 (clobber (reg:CC 17))] 16563 "TARGET_SSE2 16564 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM) 16565 && (!TARGET_IEEE_FP 16566 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))" 16567 "#") 16568 16569(define_insn "sse_movdfcc_eq" 16570 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf") 16571 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f") 16572 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f")) 16573 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY") 16574 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY"))) 16575 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X")) 16576 (clobber (reg:CC 17))] 16577 "TARGET_SSE 16578 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" 16579 "#") 16580 16581;; For non-sse moves just expand the usual cmove sequence. 16582(define_split 16583 [(set (match_operand 0 "register_operand" "") 16584 (if_then_else (match_operator 1 "comparison_operator" 16585 [(match_operand 4 "nonimmediate_operand" "") 16586 (match_operand 5 "register_operand" "")]) 16587 (match_operand 2 "nonimmediate_operand" "") 16588 (match_operand 3 "nonimmediate_operand" ""))) 16589 (clobber (match_operand 6 "" "")) 16590 (clobber (reg:CC 17))] 16591 "!SSE_REG_P (operands[0]) && reload_completed 16592 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))" 16593 [(const_int 0)] 16594{ 16595 ix86_compare_op0 = operands[5]; 16596 ix86_compare_op1 = operands[4]; 16597 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])), 16598 VOIDmode, operands[5], operands[4]); 16599 ix86_expand_fp_movcc (operands); 16600 DONE; 16601}) 16602 16603;; Split SSE based conditional move into seqence: 16604;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison 16605;; and op2, op0 - zero op2 if comparison was false 16606;; nand op0, op3 - load op3 to op0 if comparison was false 16607;; or op2, op0 - get the nonzero one into the result. 16608(define_split 16609 [(set (match_operand 0 "register_operand" "") 16610 (if_then_else (match_operator 1 "sse_comparison_operator" 16611 [(match_operand 4 "register_operand" "") 16612 (match_operand 5 "nonimmediate_operand" "")]) 16613 (match_operand 2 "register_operand" "") 16614 (match_operand 3 "register_operand" ""))) 16615 (clobber (match_operand 6 "" "")) 16616 (clobber (reg:CC 17))] 16617 "SSE_REG_P (operands[0]) && reload_completed" 16618 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)])) 16619 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0) 16620 (subreg:TI (match_dup 4) 0))) 16621 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0)) 16622 (subreg:TI (match_dup 3) 0))) 16623 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0) 16624 (subreg:TI (match_dup 7) 0)))] 16625{ 16626 /* If op2 == op3, op3 will be clobbered before it is used. 16627 This should be optimized out though. */ 16628 if (operands_match_p (operands[2], operands[3])) 16629 abort (); 16630 PUT_MODE (operands[1], GET_MODE (operands[0])); 16631 if (operands_match_p (operands[0], operands[4])) 16632 operands[6] = operands[4], operands[7] = operands[2]; 16633 else 16634 operands[6] = operands[2], operands[7] = operands[4]; 16635}) 16636 16637;; Special case of conditional move we can handle effectivly. 16638;; Do not brother with the integer/floating point case, since these are 16639;; bot considerably slower, unlike in the generic case. 16640(define_insn "*sse_movsfcc_const0_1" 16641 [(set (match_operand:SF 0 "register_operand" "=&x") 16642 (if_then_else:SF (match_operator 1 "sse_comparison_operator" 16643 [(match_operand:SF 4 "register_operand" "0") 16644 (match_operand:SF 5 "nonimmediate_operand" "xm")]) 16645 (match_operand:SF 2 "register_operand" "x") 16646 (match_operand:SF 3 "const0_operand" "X")))] 16647 "TARGET_SSE" 16648 "#") 16649 16650(define_insn "*sse_movsfcc_const0_2" 16651 [(set (match_operand:SF 0 "register_operand" "=&x") 16652 (if_then_else:SF (match_operator 1 "sse_comparison_operator" 16653 [(match_operand:SF 4 "register_operand" "0") 16654 (match_operand:SF 5 "nonimmediate_operand" "xm")]) 16655 (match_operand:SF 2 "const0_operand" "X") 16656 (match_operand:SF 3 "register_operand" "x")))] 16657 "TARGET_SSE" 16658 "#") 16659 16660(define_insn "*sse_movsfcc_const0_3" 16661 [(set (match_operand:SF 0 "register_operand" "=&x") 16662 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 16663 [(match_operand:SF 4 "nonimmediate_operand" "xm") 16664 (match_operand:SF 5 "register_operand" "0")]) 16665 (match_operand:SF 2 "register_operand" "x") 16666 (match_operand:SF 3 "const0_operand" "X")))] 16667 "TARGET_SSE" 16668 "#") 16669 16670(define_insn "*sse_movsfcc_const0_4" 16671 [(set (match_operand:SF 0 "register_operand" "=&x") 16672 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 16673 [(match_operand:SF 4 "nonimmediate_operand" "xm") 16674 (match_operand:SF 5 "register_operand" "0")]) 16675 (match_operand:SF 2 "const0_operand" "X") 16676 (match_operand:SF 3 "register_operand" "x")))] 16677 "TARGET_SSE" 16678 "#") 16679 16680(define_insn "*sse_movdfcc_const0_1" 16681 [(set (match_operand:DF 0 "register_operand" "=&Y") 16682 (if_then_else:DF (match_operator 1 "sse_comparison_operator" 16683 [(match_operand:DF 4 "register_operand" "0") 16684 (match_operand:DF 5 "nonimmediate_operand" "Ym")]) 16685 (match_operand:DF 2 "register_operand" "Y") 16686 (match_operand:DF 3 "const0_operand" "X")))] 16687 "TARGET_SSE2" 16688 "#") 16689 16690(define_insn "*sse_movdfcc_const0_2" 16691 [(set (match_operand:DF 0 "register_operand" "=&Y") 16692 (if_then_else:DF (match_operator 1 "sse_comparison_operator" 16693 [(match_operand:DF 4 "register_operand" "0") 16694 (match_operand:DF 5 "nonimmediate_operand" "Ym")]) 16695 (match_operand:DF 2 "const0_operand" "X") 16696 (match_operand:DF 3 "register_operand" "Y")))] 16697 "TARGET_SSE2" 16698 "#") 16699 16700(define_insn "*sse_movdfcc_const0_3" 16701 [(set (match_operand:DF 0 "register_operand" "=&Y") 16702 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 16703 [(match_operand:DF 4 "nonimmediate_operand" "Ym") 16704 (match_operand:DF 5 "register_operand" "0")]) 16705 (match_operand:DF 2 "register_operand" "Y") 16706 (match_operand:DF 3 "const0_operand" "X")))] 16707 "TARGET_SSE2" 16708 "#") 16709 16710(define_insn "*sse_movdfcc_const0_4" 16711 [(set (match_operand:DF 0 "register_operand" "=&Y") 16712 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 16713 [(match_operand:DF 4 "nonimmediate_operand" "Ym") 16714 (match_operand:DF 5 "register_operand" "0")]) 16715 (match_operand:DF 2 "const0_operand" "X") 16716 (match_operand:DF 3 "register_operand" "Y")))] 16717 "TARGET_SSE2" 16718 "#") 16719 16720(define_split 16721 [(set (match_operand 0 "register_operand" "") 16722 (if_then_else (match_operator 1 "comparison_operator" 16723 [(match_operand 4 "nonimmediate_operand" "") 16724 (match_operand 5 "nonimmediate_operand" "")]) 16725 (match_operand 2 "nonmemory_operand" "") 16726 (match_operand 3 "nonmemory_operand" "")))] 16727 "SSE_REG_P (operands[0]) && reload_completed 16728 && (const0_operand (operands[2], GET_MODE (operands[0])) 16729 || const0_operand (operands[3], GET_MODE (operands[0])))" 16730 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)])) 16731 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6) 16732 (subreg:TI (match_dup 7) 0)))] 16733{ 16734 PUT_MODE (operands[1], GET_MODE (operands[0])); 16735 if (!sse_comparison_operator (operands[1], VOIDmode) 16736 || !rtx_equal_p (operands[0], operands[4])) 16737 { 16738 rtx tmp = operands[5]; 16739 operands[5] = operands[4]; 16740 operands[4] = tmp; 16741 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1]))); 16742 } 16743 if (!rtx_equal_p (operands[0], operands[4])) 16744 abort (); 16745 if (const0_operand (operands[2], GET_MODE (operands[0]))) 16746 { 16747 operands[7] = operands[3]; 16748 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0], 16749 0)); 16750 } 16751 else 16752 { 16753 operands[7] = operands[2]; 16754 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0); 16755 } 16756}) 16757 16758(define_expand "allocate_stack_worker" 16759 [(match_operand:SI 0 "register_operand" "")] 16760 "TARGET_STACK_PROBE" 16761{ 16762 if (TARGET_64BIT) 16763 emit_insn (gen_allocate_stack_worker_rex64 (operands[0])); 16764 else 16765 emit_insn (gen_allocate_stack_worker_1 (operands[0])); 16766 DONE; 16767}) 16768 16769(define_insn "allocate_stack_worker_1" 16770 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE) 16771 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0))) 16772 (clobber (match_dup 0)) 16773 (clobber (reg:CC 17))] 16774 "!TARGET_64BIT && TARGET_STACK_PROBE" 16775 "call\t__alloca" 16776 [(set_attr "type" "multi") 16777 (set_attr "length" "5")]) 16778 16779(define_insn "allocate_stack_worker_rex64" 16780 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE) 16781 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0))) 16782 (clobber (match_dup 0)) 16783 (clobber (reg:CC 17))] 16784 "TARGET_64BIT && TARGET_STACK_PROBE" 16785 "call\t__alloca" 16786 [(set_attr "type" "multi") 16787 (set_attr "length" "5")]) 16788 16789(define_expand "allocate_stack" 16790 [(parallel [(set (match_operand:SI 0 "register_operand" "=r") 16791 (minus:SI (reg:SI 7) 16792 (match_operand:SI 1 "general_operand" ""))) 16793 (clobber (reg:CC 17))]) 16794 (parallel [(set (reg:SI 7) 16795 (minus:SI (reg:SI 7) (match_dup 1))) 16796 (clobber (reg:CC 17))])] 16797 "TARGET_STACK_PROBE" 16798{ 16799#ifdef CHECK_STACK_LIMIT 16800 if (GET_CODE (operands[1]) == CONST_INT 16801 && INTVAL (operands[1]) < CHECK_STACK_LIMIT) 16802 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, 16803 operands[1])); 16804 else 16805#endif 16806 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode, 16807 operands[1]))); 16808 16809 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 16810 DONE; 16811}) 16812 16813(define_expand "builtin_setjmp_receiver" 16814 [(label_ref (match_operand 0 "" ""))] 16815 "!TARGET_64BIT && flag_pic" 16816{ 16817 emit_insn (gen_set_got (pic_offset_table_rtx)); 16818 DONE; 16819}) 16820 16821;; Avoid redundant prefixes by splitting HImode arithmetic to SImode. 16822 16823(define_split 16824 [(set (match_operand 0 "register_operand" "") 16825 (match_operator 3 "promotable_binary_operator" 16826 [(match_operand 1 "register_operand" "") 16827 (match_operand 2 "aligned_operand" "")])) 16828 (clobber (reg:CC 17))] 16829 "! TARGET_PARTIAL_REG_STALL && reload_completed 16830 && ((GET_MODE (operands[0]) == HImode 16831 && ((!optimize_size && !TARGET_FAST_PREFIX) 16832 || GET_CODE (operands[2]) != CONST_INT 16833 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))) 16834 || (GET_MODE (operands[0]) == QImode 16835 && (TARGET_PROMOTE_QImode || optimize_size)))" 16836 [(parallel [(set (match_dup 0) 16837 (match_op_dup 3 [(match_dup 1) (match_dup 2)])) 16838 (clobber (reg:CC 17))])] 16839 "operands[0] = gen_lowpart (SImode, operands[0]); 16840 operands[1] = gen_lowpart (SImode, operands[1]); 16841 if (GET_CODE (operands[3]) != ASHIFT) 16842 operands[2] = gen_lowpart (SImode, operands[2]); 16843 PUT_MODE (operands[3], SImode);") 16844 16845; Promote the QImode tests, as i386 has encoding of the AND 16846; instruction with 32-bit sign-extended immediate and thus the 16847; instruction size is unchanged, except in the %eax case for 16848; which it is increased by one byte, hence the ! optimize_size. 16849(define_split 16850 [(set (reg 17) 16851 (compare (and (match_operand 1 "aligned_operand" "") 16852 (match_operand 2 "const_int_operand" "")) 16853 (const_int 0))) 16854 (set (match_operand 0 "register_operand" "") 16855 (and (match_dup 1) (match_dup 2)))] 16856 "! TARGET_PARTIAL_REG_STALL && reload_completed 16857 /* Ensure that the operand will remain sign-extended immediate. */ 16858 && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode) 16859 && ! optimize_size 16860 && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX) 16861 || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))" 16862 [(parallel [(set (reg:CCNO 17) 16863 (compare:CCNO (and:SI (match_dup 1) (match_dup 2)) 16864 (const_int 0))) 16865 (set (match_dup 0) 16866 (and:SI (match_dup 1) (match_dup 2)))])] 16867 "operands[2] 16868 = gen_int_mode (INTVAL (operands[2]) 16869 & GET_MODE_MASK (GET_MODE (operands[0])), 16870 SImode); 16871 operands[0] = gen_lowpart (SImode, operands[0]); 16872 operands[1] = gen_lowpart (SImode, operands[1]);") 16873 16874; Don't promote the QImode tests, as i386 doesn't have encoding of 16875; the TEST instruction with 32-bit sign-extended immediate and thus 16876; the instruction size would at least double, which is not what we 16877; want even with ! optimize_size. 16878(define_split 16879 [(set (reg 17) 16880 (compare (and (match_operand:HI 0 "aligned_operand" "") 16881 (match_operand:HI 1 "const_int_operand" "")) 16882 (const_int 0)))] 16883 "! TARGET_PARTIAL_REG_STALL && reload_completed 16884 /* Ensure that the operand will remain sign-extended immediate. */ 16885 && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode) 16886 && ! TARGET_FAST_PREFIX 16887 && ! optimize_size" 16888 [(set (reg:CCNO 17) 16889 (compare:CCNO (and:SI (match_dup 0) (match_dup 1)) 16890 (const_int 0)))] 16891 "operands[1] 16892 = gen_int_mode (INTVAL (operands[1]) 16893 & GET_MODE_MASK (GET_MODE (operands[0])), 16894 SImode); 16895 operands[0] = gen_lowpart (SImode, operands[0]);") 16896 16897(define_split 16898 [(set (match_operand 0 "register_operand" "") 16899 (neg (match_operand 1 "register_operand" ""))) 16900 (clobber (reg:CC 17))] 16901 "! TARGET_PARTIAL_REG_STALL && reload_completed 16902 && (GET_MODE (operands[0]) == HImode 16903 || (GET_MODE (operands[0]) == QImode 16904 && (TARGET_PROMOTE_QImode || optimize_size)))" 16905 [(parallel [(set (match_dup 0) 16906 (neg:SI (match_dup 1))) 16907 (clobber (reg:CC 17))])] 16908 "operands[0] = gen_lowpart (SImode, operands[0]); 16909 operands[1] = gen_lowpart (SImode, operands[1]);") 16910 16911(define_split 16912 [(set (match_operand 0 "register_operand" "") 16913 (not (match_operand 1 "register_operand" "")))] 16914 "! TARGET_PARTIAL_REG_STALL && reload_completed 16915 && (GET_MODE (operands[0]) == HImode 16916 || (GET_MODE (operands[0]) == QImode 16917 && (TARGET_PROMOTE_QImode || optimize_size)))" 16918 [(set (match_dup 0) 16919 (not:SI (match_dup 1)))] 16920 "operands[0] = gen_lowpart (SImode, operands[0]); 16921 operands[1] = gen_lowpart (SImode, operands[1]);") 16922 16923(define_split 16924 [(set (match_operand 0 "register_operand" "") 16925 (if_then_else (match_operator 1 "comparison_operator" 16926 [(reg 17) (const_int 0)]) 16927 (match_operand 2 "register_operand" "") 16928 (match_operand 3 "register_operand" "")))] 16929 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE 16930 && (GET_MODE (operands[0]) == HImode 16931 || (GET_MODE (operands[0]) == QImode 16932 && (TARGET_PROMOTE_QImode || optimize_size)))" 16933 [(set (match_dup 0) 16934 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))] 16935 "operands[0] = gen_lowpart (SImode, operands[0]); 16936 operands[2] = gen_lowpart (SImode, operands[2]); 16937 operands[3] = gen_lowpart (SImode, operands[3]);") 16938 16939 16940;; RTL Peephole optimizations, run before sched2. These primarily look to 16941;; transform a complex memory operation into two memory to register operations. 16942 16943;; Don't push memory operands 16944(define_peephole2 16945 [(set (match_operand:SI 0 "push_operand" "") 16946 (match_operand:SI 1 "memory_operand" "")) 16947 (match_scratch:SI 2 "r")] 16948 "! optimize_size && ! TARGET_PUSH_MEMORY" 16949 [(set (match_dup 2) (match_dup 1)) 16950 (set (match_dup 0) (match_dup 2))] 16951 "") 16952 16953(define_peephole2 16954 [(set (match_operand:DI 0 "push_operand" "") 16955 (match_operand:DI 1 "memory_operand" "")) 16956 (match_scratch:DI 2 "r")] 16957 "! optimize_size && ! TARGET_PUSH_MEMORY" 16958 [(set (match_dup 2) (match_dup 1)) 16959 (set (match_dup 0) (match_dup 2))] 16960 "") 16961 16962;; We need to handle SFmode only, because DFmode and XFmode is split to 16963;; SImode pushes. 16964(define_peephole2 16965 [(set (match_operand:SF 0 "push_operand" "") 16966 (match_operand:SF 1 "memory_operand" "")) 16967 (match_scratch:SF 2 "r")] 16968 "! optimize_size && ! TARGET_PUSH_MEMORY" 16969 [(set (match_dup 2) (match_dup 1)) 16970 (set (match_dup 0) (match_dup 2))] 16971 "") 16972 16973(define_peephole2 16974 [(set (match_operand:HI 0 "push_operand" "") 16975 (match_operand:HI 1 "memory_operand" "")) 16976 (match_scratch:HI 2 "r")] 16977 "! optimize_size && ! TARGET_PUSH_MEMORY" 16978 [(set (match_dup 2) (match_dup 1)) 16979 (set (match_dup 0) (match_dup 2))] 16980 "") 16981 16982(define_peephole2 16983 [(set (match_operand:QI 0 "push_operand" "") 16984 (match_operand:QI 1 "memory_operand" "")) 16985 (match_scratch:QI 2 "q")] 16986 "! optimize_size && ! TARGET_PUSH_MEMORY" 16987 [(set (match_dup 2) (match_dup 1)) 16988 (set (match_dup 0) (match_dup 2))] 16989 "") 16990 16991;; Don't move an immediate directly to memory when the instruction 16992;; gets too big. 16993(define_peephole2 16994 [(match_scratch:SI 1 "r") 16995 (set (match_operand:SI 0 "memory_operand" "") 16996 (const_int 0))] 16997 "! optimize_size 16998 && ! TARGET_USE_MOV0 16999 && TARGET_SPLIT_LONG_MOVES 17000 && get_attr_length (insn) >= ix86_cost->large_insn 17001 && peep2_regno_dead_p (0, FLAGS_REG)" 17002 [(parallel [(set (match_dup 1) (const_int 0)) 17003 (clobber (reg:CC 17))]) 17004 (set (match_dup 0) (match_dup 1))] 17005 "") 17006 17007(define_peephole2 17008 [(match_scratch:HI 1 "r") 17009 (set (match_operand:HI 0 "memory_operand" "") 17010 (const_int 0))] 17011 "! optimize_size 17012 && ! TARGET_USE_MOV0 17013 && TARGET_SPLIT_LONG_MOVES 17014 && get_attr_length (insn) >= ix86_cost->large_insn 17015 && peep2_regno_dead_p (0, FLAGS_REG)" 17016 [(parallel [(set (match_dup 2) (const_int 0)) 17017 (clobber (reg:CC 17))]) 17018 (set (match_dup 0) (match_dup 1))] 17019 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));") 17020 17021(define_peephole2 17022 [(match_scratch:QI 1 "q") 17023 (set (match_operand:QI 0 "memory_operand" "") 17024 (const_int 0))] 17025 "! optimize_size 17026 && ! TARGET_USE_MOV0 17027 && TARGET_SPLIT_LONG_MOVES 17028 && get_attr_length (insn) >= ix86_cost->large_insn 17029 && peep2_regno_dead_p (0, FLAGS_REG)" 17030 [(parallel [(set (match_dup 2) (const_int 0)) 17031 (clobber (reg:CC 17))]) 17032 (set (match_dup 0) (match_dup 1))] 17033 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));") 17034 17035(define_peephole2 17036 [(match_scratch:SI 2 "r") 17037 (set (match_operand:SI 0 "memory_operand" "") 17038 (match_operand:SI 1 "immediate_operand" ""))] 17039 "! optimize_size 17040 && get_attr_length (insn) >= ix86_cost->large_insn 17041 && TARGET_SPLIT_LONG_MOVES" 17042 [(set (match_dup 2) (match_dup 1)) 17043 (set (match_dup 0) (match_dup 2))] 17044 "") 17045 17046(define_peephole2 17047 [(match_scratch:HI 2 "r") 17048 (set (match_operand:HI 0 "memory_operand" "") 17049 (match_operand:HI 1 "immediate_operand" ""))] 17050 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn 17051 && TARGET_SPLIT_LONG_MOVES" 17052 [(set (match_dup 2) (match_dup 1)) 17053 (set (match_dup 0) (match_dup 2))] 17054 "") 17055 17056(define_peephole2 17057 [(match_scratch:QI 2 "q") 17058 (set (match_operand:QI 0 "memory_operand" "") 17059 (match_operand:QI 1 "immediate_operand" ""))] 17060 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn 17061 && TARGET_SPLIT_LONG_MOVES" 17062 [(set (match_dup 2) (match_dup 1)) 17063 (set (match_dup 0) (match_dup 2))] 17064 "") 17065 17066;; Don't compare memory with zero, load and use a test instead. 17067(define_peephole2 17068 [(set (reg 17) 17069 (compare (match_operand:SI 0 "memory_operand" "") 17070 (const_int 0))) 17071 (match_scratch:SI 3 "r")] 17072 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size" 17073 [(set (match_dup 3) (match_dup 0)) 17074 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))] 17075 "") 17076 17077;; NOT is not pairable on Pentium, while XOR is, but one byte longer. 17078;; Don't split NOTs with a displacement operand, because resulting XOR 17079;; will not be pariable anyway. 17080;; 17081;; On AMD K6, NOT is vector decoded with memory operand that can not be 17082;; represented using a modRM byte. The XOR replacement is long decoded, 17083;; so this split helps here as well. 17084;; 17085;; Note: Can't do this as a regular split because we can't get proper 17086;; lifetime information then. 17087 17088(define_peephole2 17089 [(set (match_operand:SI 0 "nonimmediate_operand" "") 17090 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))] 17091 "!optimize_size 17092 && peep2_regno_dead_p (0, FLAGS_REG) 17093 && ((TARGET_PENTIUM 17094 && (GET_CODE (operands[0]) != MEM 17095 || !memory_displacement_operand (operands[0], SImode))) 17096 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))" 17097 [(parallel [(set (match_dup 0) 17098 (xor:SI (match_dup 1) (const_int -1))) 17099 (clobber (reg:CC 17))])] 17100 "") 17101 17102(define_peephole2 17103 [(set (match_operand:HI 0 "nonimmediate_operand" "") 17104 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))] 17105 "!optimize_size 17106 && peep2_regno_dead_p (0, FLAGS_REG) 17107 && ((TARGET_PENTIUM 17108 && (GET_CODE (operands[0]) != MEM 17109 || !memory_displacement_operand (operands[0], HImode))) 17110 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))" 17111 [(parallel [(set (match_dup 0) 17112 (xor:HI (match_dup 1) (const_int -1))) 17113 (clobber (reg:CC 17))])] 17114 "") 17115 17116(define_peephole2 17117 [(set (match_operand:QI 0 "nonimmediate_operand" "") 17118 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))] 17119 "!optimize_size 17120 && peep2_regno_dead_p (0, FLAGS_REG) 17121 && ((TARGET_PENTIUM 17122 && (GET_CODE (operands[0]) != MEM 17123 || !memory_displacement_operand (operands[0], QImode))) 17124 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))" 17125 [(parallel [(set (match_dup 0) 17126 (xor:QI (match_dup 1) (const_int -1))) 17127 (clobber (reg:CC 17))])] 17128 "") 17129 17130;; Non pairable "test imm, reg" instructions can be translated to 17131;; "and imm, reg" if reg dies. The "and" form is also shorter (one 17132;; byte opcode instead of two, have a short form for byte operands), 17133;; so do it for other CPUs as well. Given that the value was dead, 17134;; this should not create any new dependencies. Pass on the sub-word 17135;; versions if we're concerned about partial register stalls. 17136 17137(define_peephole2 17138 [(set (reg 17) 17139 (compare (and:SI (match_operand:SI 0 "register_operand" "") 17140 (match_operand:SI 1 "immediate_operand" "")) 17141 (const_int 0)))] 17142 "ix86_match_ccmode (insn, CCNOmode) 17143 && (true_regnum (operands[0]) != 0 17144 || (GET_CODE (operands[1]) == CONST_INT 17145 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))) 17146 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" 17147 [(parallel 17148 [(set (reg:CCNO 17) 17149 (compare:CCNO (and:SI (match_dup 0) 17150 (match_dup 1)) 17151 (const_int 0))) 17152 (set (match_dup 0) 17153 (and:SI (match_dup 0) (match_dup 1)))])] 17154 "") 17155 17156;; We don't need to handle HImode case, because it will be promoted to SImode 17157;; on ! TARGET_PARTIAL_REG_STALL 17158 17159(define_peephole2 17160 [(set (reg 17) 17161 (compare (and:QI (match_operand:QI 0 "register_operand" "") 17162 (match_operand:QI 1 "immediate_operand" "")) 17163 (const_int 0)))] 17164 "! TARGET_PARTIAL_REG_STALL 17165 && ix86_match_ccmode (insn, CCNOmode) 17166 && true_regnum (operands[0]) != 0 17167 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" 17168 [(parallel 17169 [(set (reg:CCNO 17) 17170 (compare:CCNO (and:QI (match_dup 0) 17171 (match_dup 1)) 17172 (const_int 0))) 17173 (set (match_dup 0) 17174 (and:QI (match_dup 0) (match_dup 1)))])] 17175 "") 17176 17177(define_peephole2 17178 [(set (reg 17) 17179 (compare 17180 (and:SI 17181 (zero_extract:SI 17182 (match_operand 0 "ext_register_operand" "") 17183 (const_int 8) 17184 (const_int 8)) 17185 (match_operand 1 "const_int_operand" "")) 17186 (const_int 0)))] 17187 "! TARGET_PARTIAL_REG_STALL 17188 && ix86_match_ccmode (insn, CCNOmode) 17189 && true_regnum (operands[0]) != 0 17190 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" 17191 [(parallel [(set (reg:CCNO 17) 17192 (compare:CCNO 17193 (and:SI 17194 (zero_extract:SI 17195 (match_dup 0) 17196 (const_int 8) 17197 (const_int 8)) 17198 (match_dup 1)) 17199 (const_int 0))) 17200 (set (zero_extract:SI (match_dup 0) 17201 (const_int 8) 17202 (const_int 8)) 17203 (and:SI 17204 (zero_extract:SI 17205 (match_dup 0) 17206 (const_int 8) 17207 (const_int 8)) 17208 (match_dup 1)))])] 17209 "") 17210 17211;; Don't do logical operations with memory inputs. 17212(define_peephole2 17213 [(match_scratch:SI 2 "r") 17214 (parallel [(set (match_operand:SI 0 "register_operand" "") 17215 (match_operator:SI 3 "arith_or_logical_operator" 17216 [(match_dup 0) 17217 (match_operand:SI 1 "memory_operand" "")])) 17218 (clobber (reg:CC 17))])] 17219 "! optimize_size && ! TARGET_READ_MODIFY" 17220 [(set (match_dup 2) (match_dup 1)) 17221 (parallel [(set (match_dup 0) 17222 (match_op_dup 3 [(match_dup 0) (match_dup 2)])) 17223 (clobber (reg:CC 17))])] 17224 "") 17225 17226(define_peephole2 17227 [(match_scratch:SI 2 "r") 17228 (parallel [(set (match_operand:SI 0 "register_operand" "") 17229 (match_operator:SI 3 "arith_or_logical_operator" 17230 [(match_operand:SI 1 "memory_operand" "") 17231 (match_dup 0)])) 17232 (clobber (reg:CC 17))])] 17233 "! optimize_size && ! TARGET_READ_MODIFY" 17234 [(set (match_dup 2) (match_dup 1)) 17235 (parallel [(set (match_dup 0) 17236 (match_op_dup 3 [(match_dup 2) (match_dup 0)])) 17237 (clobber (reg:CC 17))])] 17238 "") 17239 17240; Don't do logical operations with memory outputs 17241; 17242; These two don't make sense for PPro/PII -- we're expanding a 4-uop 17243; instruction into two 1-uop insns plus a 2-uop insn. That last has 17244; the same decoder scheduling characteristics as the original. 17245 17246(define_peephole2 17247 [(match_scratch:SI 2 "r") 17248 (parallel [(set (match_operand:SI 0 "memory_operand" "") 17249 (match_operator:SI 3 "arith_or_logical_operator" 17250 [(match_dup 0) 17251 (match_operand:SI 1 "nonmemory_operand" "")])) 17252 (clobber (reg:CC 17))])] 17253 "! optimize_size && ! TARGET_READ_MODIFY_WRITE" 17254 [(set (match_dup 2) (match_dup 0)) 17255 (parallel [(set (match_dup 2) 17256 (match_op_dup 3 [(match_dup 2) (match_dup 1)])) 17257 (clobber (reg:CC 17))]) 17258 (set (match_dup 0) (match_dup 2))] 17259 "") 17260 17261(define_peephole2 17262 [(match_scratch:SI 2 "r") 17263 (parallel [(set (match_operand:SI 0 "memory_operand" "") 17264 (match_operator:SI 3 "arith_or_logical_operator" 17265 [(match_operand:SI 1 "nonmemory_operand" "") 17266 (match_dup 0)])) 17267 (clobber (reg:CC 17))])] 17268 "! optimize_size && ! TARGET_READ_MODIFY_WRITE" 17269 [(set (match_dup 2) (match_dup 0)) 17270 (parallel [(set (match_dup 2) 17271 (match_op_dup 3 [(match_dup 1) (match_dup 2)])) 17272 (clobber (reg:CC 17))]) 17273 (set (match_dup 0) (match_dup 2))] 17274 "") 17275 17276;; Attempt to always use XOR for zeroing registers. 17277(define_peephole2 17278 [(set (match_operand 0 "register_operand" "") 17279 (const_int 0))] 17280 "(GET_MODE (operands[0]) == QImode 17281 || GET_MODE (operands[0]) == HImode 17282 || GET_MODE (operands[0]) == SImode 17283 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT)) 17284 && (! TARGET_USE_MOV0 || optimize_size) 17285 && peep2_regno_dead_p (0, FLAGS_REG)" 17286 [(parallel [(set (match_dup 0) (const_int 0)) 17287 (clobber (reg:CC 17))])] 17288 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode, 17289 true_regnum (operands[0]));") 17290 17291(define_peephole2 17292 [(set (strict_low_part (match_operand 0 "register_operand" "")) 17293 (const_int 0))] 17294 "(GET_MODE (operands[0]) == QImode 17295 || GET_MODE (operands[0]) == HImode) 17296 && (! TARGET_USE_MOV0 || optimize_size) 17297 && peep2_regno_dead_p (0, FLAGS_REG)" 17298 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0)) 17299 (clobber (reg:CC 17))])]) 17300 17301;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg. 17302(define_peephole2 17303 [(set (match_operand 0 "register_operand" "") 17304 (const_int -1))] 17305 "(GET_MODE (operands[0]) == HImode 17306 || GET_MODE (operands[0]) == SImode 17307 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT)) 17308 && (optimize_size || TARGET_PENTIUM) 17309 && peep2_regno_dead_p (0, FLAGS_REG)" 17310 [(parallel [(set (match_dup 0) (const_int -1)) 17311 (clobber (reg:CC 17))])] 17312 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode, 17313 true_regnum (operands[0]));") 17314 17315;; Attempt to convert simple leas to adds. These can be created by 17316;; move expanders. 17317(define_peephole2 17318 [(set (match_operand:SI 0 "register_operand" "") 17319 (plus:SI (match_dup 0) 17320 (match_operand:SI 1 "nonmemory_operand" "")))] 17321 "peep2_regno_dead_p (0, FLAGS_REG)" 17322 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 17323 (clobber (reg:CC 17))])] 17324 "") 17325 17326(define_peephole2 17327 [(set (match_operand:SI 0 "register_operand" "") 17328 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "") 17329 (match_operand:DI 2 "nonmemory_operand" "")) 0))] 17330 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])" 17331 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) 17332 (clobber (reg:CC 17))])] 17333 "operands[2] = gen_lowpart (SImode, operands[2]);") 17334 17335(define_peephole2 17336 [(set (match_operand:DI 0 "register_operand" "") 17337 (plus:DI (match_dup 0) 17338 (match_operand:DI 1 "x86_64_general_operand" "")))] 17339 "peep2_regno_dead_p (0, FLAGS_REG)" 17340 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) 17341 (clobber (reg:CC 17))])] 17342 "") 17343 17344(define_peephole2 17345 [(set (match_operand:SI 0 "register_operand" "") 17346 (mult:SI (match_dup 0) 17347 (match_operand:SI 1 "const_int_operand" "")))] 17348 "exact_log2 (INTVAL (operands[1])) >= 0 17349 && peep2_regno_dead_p (0, FLAGS_REG)" 17350 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2))) 17351 (clobber (reg:CC 17))])] 17352 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));") 17353 17354(define_peephole2 17355 [(set (match_operand:DI 0 "register_operand" "") 17356 (mult:DI (match_dup 0) 17357 (match_operand:DI 1 "const_int_operand" "")))] 17358 "exact_log2 (INTVAL (operands[1])) >= 0 17359 && peep2_regno_dead_p (0, FLAGS_REG)" 17360 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2))) 17361 (clobber (reg:CC 17))])] 17362 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));") 17363 17364(define_peephole2 17365 [(set (match_operand:SI 0 "register_operand" "") 17366 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "") 17367 (match_operand:DI 2 "const_int_operand" "")) 0))] 17368 "exact_log2 (INTVAL (operands[2])) >= 0 17369 && REGNO (operands[0]) == REGNO (operands[1]) 17370 && peep2_regno_dead_p (0, FLAGS_REG)" 17371 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2))) 17372 (clobber (reg:CC 17))])] 17373 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));") 17374 17375;; The ESP adjustments can be done by the push and pop instructions. Resulting 17376;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On 17377;; many CPUs it is also faster, since special hardware to avoid esp 17378;; dependencies is present. 17379 17380;; While some of these conversions may be done using splitters, we use peepholes 17381;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL. 17382 17383;; Convert prologue esp subtractions to push. 17384;; We need register to push. In order to keep verify_flow_info happy we have 17385;; two choices 17386;; - use scratch and clobber it in order to avoid dependencies 17387;; - use already live register 17388;; We can't use the second way right now, since there is no reliable way how to 17389;; verify that given register is live. First choice will also most likely in 17390;; fewer dependencies. On the place of esp adjustments it is very likely that 17391;; call clobbered registers are dead. We may want to use base pointer as an 17392;; alternative when no register is available later. 17393 17394(define_peephole2 17395 [(match_scratch:SI 0 "r") 17396 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) 17397 (clobber (reg:CC 17)) 17398 (clobber (mem:BLK (scratch)))])] 17399 "optimize_size || !TARGET_SUB_ESP_4" 17400 [(clobber (match_dup 0)) 17401 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) 17402 (clobber (mem:BLK (scratch)))])]) 17403 17404(define_peephole2 17405 [(match_scratch:SI 0 "r") 17406 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) 17407 (clobber (reg:CC 17)) 17408 (clobber (mem:BLK (scratch)))])] 17409 "optimize_size || !TARGET_SUB_ESP_8" 17410 [(clobber (match_dup 0)) 17411 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) 17412 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) 17413 (clobber (mem:BLK (scratch)))])]) 17414 17415;; Convert esp subtractions to push. 17416(define_peephole2 17417 [(match_scratch:SI 0 "r") 17418 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) 17419 (clobber (reg:CC 17))])] 17420 "optimize_size || !TARGET_SUB_ESP_4" 17421 [(clobber (match_dup 0)) 17422 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))]) 17423 17424(define_peephole2 17425 [(match_scratch:SI 0 "r") 17426 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) 17427 (clobber (reg:CC 17))])] 17428 "optimize_size || !TARGET_SUB_ESP_8" 17429 [(clobber (match_dup 0)) 17430 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) 17431 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))]) 17432 17433;; Convert epilogue deallocator to pop. 17434(define_peephole2 17435 [(match_scratch:SI 0 "r") 17436 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) 17437 (clobber (reg:CC 17)) 17438 (clobber (mem:BLK (scratch)))])] 17439 "optimize_size || !TARGET_ADD_ESP_4" 17440 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) 17441 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) 17442 (clobber (mem:BLK (scratch)))])] 17443 "") 17444 17445;; Two pops case is tricky, since pop causes dependency on destination register. 17446;; We use two registers if available. 17447(define_peephole2 17448 [(match_scratch:SI 0 "r") 17449 (match_scratch:SI 1 "r") 17450 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) 17451 (clobber (reg:CC 17)) 17452 (clobber (mem:BLK (scratch)))])] 17453 "optimize_size || !TARGET_ADD_ESP_8" 17454 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) 17455 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) 17456 (clobber (mem:BLK (scratch)))]) 17457 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) 17458 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] 17459 "") 17460 17461(define_peephole2 17462 [(match_scratch:SI 0 "r") 17463 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) 17464 (clobber (reg:CC 17)) 17465 (clobber (mem:BLK (scratch)))])] 17466 "optimize_size" 17467 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) 17468 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) 17469 (clobber (mem:BLK (scratch)))]) 17470 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) 17471 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] 17472 "") 17473 17474;; Convert esp additions to pop. 17475(define_peephole2 17476 [(match_scratch:SI 0 "r") 17477 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) 17478 (clobber (reg:CC 17))])] 17479 "" 17480 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) 17481 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] 17482 "") 17483 17484;; Two pops case is tricky, since pop causes dependency on destination register. 17485;; We use two registers if available. 17486(define_peephole2 17487 [(match_scratch:SI 0 "r") 17488 (match_scratch:SI 1 "r") 17489 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) 17490 (clobber (reg:CC 17))])] 17491 "" 17492 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) 17493 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))]) 17494 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) 17495 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] 17496 "") 17497 17498(define_peephole2 17499 [(match_scratch:SI 0 "r") 17500 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) 17501 (clobber (reg:CC 17))])] 17502 "optimize_size" 17503 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) 17504 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))]) 17505 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) 17506 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] 17507 "") 17508 17509;; Convert compares with 1 to shorter inc/dec operations when CF is not 17510;; required and register dies. 17511(define_peephole2 17512 [(set (reg 17) 17513 (compare (match_operand:SI 0 "register_operand" "") 17514 (match_operand:SI 1 "incdec_operand" "")))] 17515 "ix86_match_ccmode (insn, CCGCmode) 17516 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" 17517 [(parallel [(set (reg:CCGC 17) 17518 (compare:CCGC (match_dup 0) 17519 (match_dup 1))) 17520 (clobber (match_dup 0))])] 17521 "") 17522 17523(define_peephole2 17524 [(set (reg 17) 17525 (compare (match_operand:HI 0 "register_operand" "") 17526 (match_operand:HI 1 "incdec_operand" "")))] 17527 "ix86_match_ccmode (insn, CCGCmode) 17528 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" 17529 [(parallel [(set (reg:CCGC 17) 17530 (compare:CCGC (match_dup 0) 17531 (match_dup 1))) 17532 (clobber (match_dup 0))])] 17533 "") 17534 17535(define_peephole2 17536 [(set (reg 17) 17537 (compare (match_operand:QI 0 "register_operand" "") 17538 (match_operand:QI 1 "incdec_operand" "")))] 17539 "ix86_match_ccmode (insn, CCGCmode) 17540 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" 17541 [(parallel [(set (reg:CCGC 17) 17542 (compare:CCGC (match_dup 0) 17543 (match_dup 1))) 17544 (clobber (match_dup 0))])] 17545 "") 17546 17547;; Convert compares with 128 to shorter add -128 17548(define_peephole2 17549 [(set (reg 17) 17550 (compare (match_operand:SI 0 "register_operand" "") 17551 (const_int 128)))] 17552 "ix86_match_ccmode (insn, CCGCmode) 17553 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" 17554 [(parallel [(set (reg:CCGC 17) 17555 (compare:CCGC (match_dup 0) 17556 (const_int 128))) 17557 (clobber (match_dup 0))])] 17558 "") 17559 17560(define_peephole2 17561 [(set (reg 17) 17562 (compare (match_operand:HI 0 "register_operand" "") 17563 (const_int 128)))] 17564 "ix86_match_ccmode (insn, CCGCmode) 17565 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" 17566 [(parallel [(set (reg:CCGC 17) 17567 (compare:CCGC (match_dup 0) 17568 (const_int 128))) 17569 (clobber (match_dup 0))])] 17570 "") 17571 17572(define_peephole2 17573 [(match_scratch:DI 0 "r") 17574 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) 17575 (clobber (reg:CC 17)) 17576 (clobber (mem:BLK (scratch)))])] 17577 "optimize_size || !TARGET_SUB_ESP_4" 17578 [(clobber (match_dup 0)) 17579 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) 17580 (clobber (mem:BLK (scratch)))])]) 17581 17582(define_peephole2 17583 [(match_scratch:DI 0 "r") 17584 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) 17585 (clobber (reg:CC 17)) 17586 (clobber (mem:BLK (scratch)))])] 17587 "optimize_size || !TARGET_SUB_ESP_8" 17588 [(clobber (match_dup 0)) 17589 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) 17590 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) 17591 (clobber (mem:BLK (scratch)))])]) 17592 17593;; Convert esp subtractions to push. 17594(define_peephole2 17595 [(match_scratch:DI 0 "r") 17596 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) 17597 (clobber (reg:CC 17))])] 17598 "optimize_size || !TARGET_SUB_ESP_4" 17599 [(clobber (match_dup 0)) 17600 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))]) 17601 17602(define_peephole2 17603 [(match_scratch:DI 0 "r") 17604 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) 17605 (clobber (reg:CC 17))])] 17606 "optimize_size || !TARGET_SUB_ESP_8" 17607 [(clobber (match_dup 0)) 17608 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) 17609 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))]) 17610 17611;; Convert epilogue deallocator to pop. 17612(define_peephole2 17613 [(match_scratch:DI 0 "r") 17614 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) 17615 (clobber (reg:CC 17)) 17616 (clobber (mem:BLK (scratch)))])] 17617 "optimize_size || !TARGET_ADD_ESP_4" 17618 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) 17619 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) 17620 (clobber (mem:BLK (scratch)))])] 17621 "") 17622 17623;; Two pops case is tricky, since pop causes dependency on destination register. 17624;; We use two registers if available. 17625(define_peephole2 17626 [(match_scratch:DI 0 "r") 17627 (match_scratch:DI 1 "r") 17628 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) 17629 (clobber (reg:CC 17)) 17630 (clobber (mem:BLK (scratch)))])] 17631 "optimize_size || !TARGET_ADD_ESP_8" 17632 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) 17633 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) 17634 (clobber (mem:BLK (scratch)))]) 17635 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7))) 17636 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] 17637 "") 17638 17639(define_peephole2 17640 [(match_scratch:DI 0 "r") 17641 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) 17642 (clobber (reg:CC 17)) 17643 (clobber (mem:BLK (scratch)))])] 17644 "optimize_size" 17645 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) 17646 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) 17647 (clobber (mem:BLK (scratch)))]) 17648 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) 17649 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] 17650 "") 17651 17652;; Convert esp additions to pop. 17653(define_peephole2 17654 [(match_scratch:DI 0 "r") 17655 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) 17656 (clobber (reg:CC 17))])] 17657 "" 17658 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) 17659 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] 17660 "") 17661 17662;; Two pops case is tricky, since pop causes dependency on destination register. 17663;; We use two registers if available. 17664(define_peephole2 17665 [(match_scratch:DI 0 "r") 17666 (match_scratch:DI 1 "r") 17667 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) 17668 (clobber (reg:CC 17))])] 17669 "" 17670 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) 17671 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))]) 17672 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7))) 17673 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] 17674 "") 17675 17676(define_peephole2 17677 [(match_scratch:DI 0 "r") 17678 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) 17679 (clobber (reg:CC 17))])] 17680 "optimize_size" 17681 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) 17682 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))]) 17683 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) 17684 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] 17685 "") 17686 17687;; Call-value patterns last so that the wildcard operand does not 17688;; disrupt insn-recog's switch tables. 17689 17690(define_insn "*call_value_pop_0" 17691 [(set (match_operand 0 "" "") 17692 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" "")) 17693 (match_operand:SI 2 "" ""))) 17694 (set (reg:SI 7) (plus:SI (reg:SI 7) 17695 (match_operand:SI 3 "immediate_operand" "")))] 17696 "!TARGET_64BIT" 17697{ 17698 if (SIBLING_CALL_P (insn)) 17699 return "jmp\t%P1"; 17700 else 17701 return "call\t%P1"; 17702} 17703 [(set_attr "type" "callv")]) 17704 17705(define_insn "*call_value_pop_1" 17706 [(set (match_operand 0 "" "") 17707 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm")) 17708 (match_operand:SI 2 "" ""))) 17709 (set (reg:SI 7) (plus:SI (reg:SI 7) 17710 (match_operand:SI 3 "immediate_operand" "i")))] 17711 "!TARGET_64BIT" 17712{ 17713 if (constant_call_address_operand (operands[1], QImode)) 17714 { 17715 if (SIBLING_CALL_P (insn)) 17716 return "jmp\t%P1"; 17717 else 17718 return "call\t%P1"; 17719 } 17720 if (SIBLING_CALL_P (insn)) 17721 return "jmp\t%A1"; 17722 else 17723 return "call\t%A1"; 17724} 17725 [(set_attr "type" "callv")]) 17726 17727(define_insn "*call_value_0" 17728 [(set (match_operand 0 "" "") 17729 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" "")) 17730 (match_operand:SI 2 "" "")))] 17731 "!TARGET_64BIT" 17732{ 17733 if (SIBLING_CALL_P (insn)) 17734 return "jmp\t%P1"; 17735 else 17736 return "call\t%P1"; 17737} 17738 [(set_attr "type" "callv")]) 17739 17740(define_insn "*call_value_0_rex64" 17741 [(set (match_operand 0 "" "") 17742 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" "")) 17743 (match_operand:DI 2 "const_int_operand" "")))] 17744 "TARGET_64BIT" 17745{ 17746 if (SIBLING_CALL_P (insn)) 17747 return "jmp\t%P1"; 17748 else 17749 return "call\t%P1"; 17750} 17751 [(set_attr "type" "callv")]) 17752 17753(define_insn "*call_value_1" 17754 [(set (match_operand 0 "" "") 17755 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm")) 17756 (match_operand:SI 2 "" "")))] 17757 "!TARGET_64BIT" 17758{ 17759 if (constant_call_address_operand (operands[1], QImode)) 17760 { 17761 if (SIBLING_CALL_P (insn)) 17762 return "jmp\t%P1"; 17763 else 17764 return "call\t%P1"; 17765 } 17766 if (SIBLING_CALL_P (insn)) 17767 return "jmp\t%*%1"; 17768 else 17769 return "call\t%*%1"; 17770} 17771 [(set_attr "type" "callv")]) 17772 17773(define_insn "*call_value_1_rex64" 17774 [(set (match_operand 0 "" "") 17775 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm")) 17776 (match_operand:DI 2 "" "")))] 17777 "TARGET_64BIT" 17778{ 17779 if (constant_call_address_operand (operands[1], QImode)) 17780 { 17781 if (SIBLING_CALL_P (insn)) 17782 return "jmp\t%P1"; 17783 else 17784 return "call\t%P1"; 17785 } 17786 if (SIBLING_CALL_P (insn)) 17787 return "jmp\t%A1"; 17788 else 17789 return "call\t%A1"; 17790} 17791 [(set_attr "type" "callv")]) 17792 17793(define_insn "trap" 17794 [(trap_if (const_int 1) (const_int 5))] 17795 "" 17796 "int\t$5") 17797 17798;;; ix86 doesn't have conditional trap instructions, but we fake them 17799;;; for the sake of bounds checking. By emitting bounds checks as 17800;;; conditional traps rather than as conditional jumps around 17801;;; unconditional traps we avoid introducing spurious basic-block 17802;;; boundaries and facilitate elimination of redundant checks. In 17803;;; honor of the too-inflexible-for-BPs `bound' instruction, we use 17804;;; interrupt 5. 17805;;; 17806;;; FIXME: Static branch prediction rules for ix86 are such that 17807;;; forward conditional branches predict as untaken. As implemented 17808;;; below, pseudo conditional traps violate that rule. We should use 17809;;; .pushsection/.popsection to place all of the `int 5's in a special 17810;;; section loaded at the end of the text segment and branch forward 17811;;; there on bounds-failure, and then jump back immediately (in case 17812;;; the system chooses to ignore bounds violations, or to report 17813;;; violations and continue execution). 17814 17815(define_expand "conditional_trap" 17816 [(trap_if (match_operator 0 "comparison_operator" 17817 [(match_dup 2) (const_int 0)]) 17818 (match_operand 1 "const_int_operand" ""))] 17819 "" 17820{ 17821 emit_insn (gen_rtx_TRAP_IF (VOIDmode, 17822 ix86_expand_compare (GET_CODE (operands[0]), 17823 NULL, NULL), 17824 operands[1])); 17825 DONE; 17826}) 17827 17828(define_insn "*conditional_trap_1" 17829 [(trap_if (match_operator 0 "comparison_operator" 17830 [(reg 17) (const_int 0)]) 17831 (match_operand 1 "const_int_operand" ""))] 17832 "" 17833{ 17834 operands[2] = gen_label_rtx (); 17835 output_asm_insn ("j%c0\t%l2\; int\t%1", operands); 17836 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 17837 CODE_LABEL_NUMBER (operands[2])); 17838 RET; 17839}) 17840 17841 ;; Pentium III SIMD instructions. 17842 17843;; Moves for SSE/MMX regs. 17844 17845(define_insn "movv4sf_internal" 17846 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m") 17847 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))] 17848 "TARGET_SSE" 17849 ;; @@@ let's try to use movaps here. 17850 "@ 17851 xorps\t%0, %0 17852 movaps\t{%1, %0|%0, %1} 17853 movaps\t{%1, %0|%0, %1}" 17854 [(set_attr "type" "ssemov") 17855 (set_attr "mode" "V4SF")]) 17856 17857(define_insn "movv4si_internal" 17858 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m") 17859 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))] 17860 "TARGET_SSE" 17861 ;; @@@ let's try to use movaps here. 17862 "@ 17863 xorps\t%0, %0 17864 movaps\t{%1, %0|%0, %1} 17865 movaps\t{%1, %0|%0, %1}" 17866 [(set_attr "type" "ssemov") 17867 (set_attr "mode" "V4SF")]) 17868 17869(define_insn "movv2di_internal" 17870 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m") 17871 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))] 17872 "TARGET_SSE" 17873 ;; @@@ let's try to use movaps here. 17874 "@ 17875 pxor\t%0, %0 17876 movdqa\t{%1, %0|%0, %1} 17877 movdqa\t{%1, %0|%0, %1}" 17878 [(set_attr "type" "ssemov") 17879 (set_attr "mode" "V4SF")]) 17880 17881(define_insn "movv8qi_internal" 17882 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m") 17883 (match_operand:V8QI 1 "vector_move_operand" "C,ym,y"))] 17884 "TARGET_MMX 17885 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 17886 "@ 17887 pxor\t%0, %0 17888 movq\t{%1, %0|%0, %1} 17889 movq\t{%1, %0|%0, %1}" 17890 [(set_attr "type" "mmxmov") 17891 (set_attr "mode" "DI")]) 17892 17893(define_insn "movv4hi_internal" 17894 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m") 17895 (match_operand:V4HI 1 "vector_move_operand" "C,ym,y"))] 17896 "TARGET_MMX 17897 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 17898 "@ 17899 pxor\t%0, %0 17900 movq\t{%1, %0|%0, %1} 17901 movq\t{%1, %0|%0, %1}" 17902 [(set_attr "type" "mmxmov") 17903 (set_attr "mode" "DI")]) 17904 17905(define_insn "movv2si_internal" 17906 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m") 17907 (match_operand:V2SI 1 "vector_move_operand" "C,ym,y"))] 17908 "TARGET_MMX 17909 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 17910 "@ 17911 pxor\t%0, %0 17912 movq\t{%1, %0|%0, %1} 17913 movq\t{%1, %0|%0, %1}" 17914 [(set_attr "type" "mmxcvt") 17915 (set_attr "mode" "DI")]) 17916 17917(define_insn "movv2sf_internal" 17918 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m") 17919 (match_operand:V2SF 1 "vector_move_operand" "C,ym,y"))] 17920 "TARGET_3DNOW 17921 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 17922 "@ 17923 pxor\t%0, %0 17924 movq\t{%1, %0|%0, %1} 17925 movq\t{%1, %0|%0, %1}" 17926 [(set_attr "type" "mmxcvt") 17927 (set_attr "mode" "DI")]) 17928 17929(define_expand "movti" 17930 [(set (match_operand:TI 0 "nonimmediate_operand" "") 17931 (match_operand:TI 1 "nonimmediate_operand" ""))] 17932 "TARGET_SSE || TARGET_64BIT" 17933{ 17934 if (TARGET_64BIT) 17935 ix86_expand_move (TImode, operands); 17936 else 17937 ix86_expand_vector_move (TImode, operands); 17938 DONE; 17939}) 17940 17941(define_insn "movv2df_internal" 17942 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m") 17943 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))] 17944 "TARGET_SSE2 17945 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 17946 "@ 17947 xorpd\t%0, %0 17948 movapd\t{%1, %0|%0, %1} 17949 movapd\t{%1, %0|%0, %1}" 17950 [(set_attr "type" "ssemov") 17951 (set_attr "mode" "V2DF")]) 17952 17953(define_insn "movv8hi_internal" 17954 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m") 17955 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))] 17956 "TARGET_SSE2 17957 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 17958 "@ 17959 xorps\t%0, %0 17960 movaps\t{%1, %0|%0, %1} 17961 movaps\t{%1, %0|%0, %1}" 17962 [(set_attr "type" "ssemov") 17963 (set_attr "mode" "V4SF")]) 17964 17965(define_insn "movv16qi_internal" 17966 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m") 17967 (match_operand:V16QI 1 "vector_move_operand" "C,xm,x"))] 17968 "TARGET_SSE2 17969 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 17970 "@ 17971 xorps\t%0, %0 17972 movaps\t{%1, %0|%0, %1} 17973 movaps\t{%1, %0|%0, %1}" 17974 [(set_attr "type" "ssemov") 17975 (set_attr "mode" "V4SF")]) 17976 17977(define_expand "movv2df" 17978 [(set (match_operand:V2DF 0 "nonimmediate_operand" "") 17979 (match_operand:V2DF 1 "nonimmediate_operand" ""))] 17980 "TARGET_SSE2" 17981{ 17982 ix86_expand_vector_move (V2DFmode, operands); 17983 DONE; 17984}) 17985 17986(define_expand "movv8hi" 17987 [(set (match_operand:V8HI 0 "nonimmediate_operand" "") 17988 (match_operand:V8HI 1 "nonimmediate_operand" ""))] 17989 "TARGET_SSE2" 17990{ 17991 ix86_expand_vector_move (V8HImode, operands); 17992 DONE; 17993}) 17994 17995(define_expand "movv16qi" 17996 [(set (match_operand:V16QI 0 "nonimmediate_operand" "") 17997 (match_operand:V16QI 1 "nonimmediate_operand" ""))] 17998 "TARGET_SSE2" 17999{ 18000 ix86_expand_vector_move (V16QImode, operands); 18001 DONE; 18002}) 18003 18004(define_expand "movv4sf" 18005 [(set (match_operand:V4SF 0 "nonimmediate_operand" "") 18006 (match_operand:V4SF 1 "nonimmediate_operand" ""))] 18007 "TARGET_SSE" 18008{ 18009 ix86_expand_vector_move (V4SFmode, operands); 18010 DONE; 18011}) 18012 18013(define_expand "movv4si" 18014 [(set (match_operand:V4SI 0 "nonimmediate_operand" "") 18015 (match_operand:V4SI 1 "nonimmediate_operand" ""))] 18016 "TARGET_SSE" 18017{ 18018 ix86_expand_vector_move (V4SImode, operands); 18019 DONE; 18020}) 18021 18022(define_expand "movv2di" 18023 [(set (match_operand:V2DI 0 "nonimmediate_operand" "") 18024 (match_operand:V2DI 1 "nonimmediate_operand" ""))] 18025 "TARGET_SSE" 18026{ 18027 ix86_expand_vector_move (V2DImode, operands); 18028 DONE; 18029}) 18030 18031(define_expand "movv2si" 18032 [(set (match_operand:V2SI 0 "nonimmediate_operand" "") 18033 (match_operand:V2SI 1 "nonimmediate_operand" ""))] 18034 "TARGET_MMX" 18035{ 18036 ix86_expand_vector_move (V2SImode, operands); 18037 DONE; 18038}) 18039 18040(define_expand "movv4hi" 18041 [(set (match_operand:V4HI 0 "nonimmediate_operand" "") 18042 (match_operand:V4HI 1 "nonimmediate_operand" ""))] 18043 "TARGET_MMX" 18044{ 18045 ix86_expand_vector_move (V4HImode, operands); 18046 DONE; 18047}) 18048 18049(define_expand "movv8qi" 18050 [(set (match_operand:V8QI 0 "nonimmediate_operand" "") 18051 (match_operand:V8QI 1 "nonimmediate_operand" ""))] 18052 "TARGET_MMX" 18053{ 18054 ix86_expand_vector_move (V8QImode, operands); 18055 DONE; 18056}) 18057 18058(define_expand "movv2sf" 18059 [(set (match_operand:V2SF 0 "nonimmediate_operand" "") 18060 (match_operand:V2SF 1 "nonimmediate_operand" ""))] 18061 "TARGET_3DNOW" 18062{ 18063 ix86_expand_vector_move (V2SFmode, operands); 18064 DONE; 18065}) 18066 18067(define_insn "*pushv2df" 18068 [(set (match_operand:V2DF 0 "push_operand" "=<") 18069 (match_operand:V2DF 1 "register_operand" "x"))] 18070 "TARGET_SSE" 18071 "#") 18072 18073(define_insn "*pushv2di" 18074 [(set (match_operand:V2DI 0 "push_operand" "=<") 18075 (match_operand:V2DI 1 "register_operand" "x"))] 18076 "TARGET_SSE2" 18077 "#") 18078 18079(define_insn "*pushv8hi" 18080 [(set (match_operand:V8HI 0 "push_operand" "=<") 18081 (match_operand:V8HI 1 "register_operand" "x"))] 18082 "TARGET_SSE2" 18083 "#") 18084 18085(define_insn "*pushv16qi" 18086 [(set (match_operand:V16QI 0 "push_operand" "=<") 18087 (match_operand:V16QI 1 "register_operand" "x"))] 18088 "TARGET_SSE2" 18089 "#") 18090 18091(define_insn "*pushv4sf" 18092 [(set (match_operand:V4SF 0 "push_operand" "=<") 18093 (match_operand:V4SF 1 "register_operand" "x"))] 18094 "TARGET_SSE" 18095 "#") 18096 18097(define_insn "*pushv4si" 18098 [(set (match_operand:V4SI 0 "push_operand" "=<") 18099 (match_operand:V4SI 1 "register_operand" "x"))] 18100 "TARGET_SSE2" 18101 "#") 18102 18103(define_insn "*pushv2si" 18104 [(set (match_operand:V2SI 0 "push_operand" "=<") 18105 (match_operand:V2SI 1 "register_operand" "y"))] 18106 "TARGET_MMX" 18107 "#") 18108 18109(define_insn "*pushv4hi" 18110 [(set (match_operand:V4HI 0 "push_operand" "=<") 18111 (match_operand:V4HI 1 "register_operand" "y"))] 18112 "TARGET_MMX" 18113 "#") 18114 18115(define_insn "*pushv8qi" 18116 [(set (match_operand:V8QI 0 "push_operand" "=<") 18117 (match_operand:V8QI 1 "register_operand" "y"))] 18118 "TARGET_MMX" 18119 "#") 18120 18121(define_insn "*pushv2sf" 18122 [(set (match_operand:V2SF 0 "push_operand" "=<") 18123 (match_operand:V2SF 1 "register_operand" "y"))] 18124 "TARGET_3DNOW" 18125 "#") 18126 18127(define_split 18128 [(set (match_operand 0 "push_operand" "") 18129 (match_operand 1 "register_operand" ""))] 18130 "!TARGET_64BIT && reload_completed 18131 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))" 18132 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3))) 18133 (set (match_dup 2) (match_dup 1))] 18134 "operands[2] = change_address (operands[0], GET_MODE (operands[0]), 18135 stack_pointer_rtx); 18136 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));") 18137 18138(define_split 18139 [(set (match_operand 0 "push_operand" "") 18140 (match_operand 1 "register_operand" ""))] 18141 "TARGET_64BIT && reload_completed 18142 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))" 18143 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3))) 18144 (set (match_dup 2) (match_dup 1))] 18145 "operands[2] = change_address (operands[0], GET_MODE (operands[0]), 18146 stack_pointer_rtx); 18147 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));") 18148 18149 18150(define_insn_and_split "*pushti" 18151 [(set (match_operand:TI 0 "push_operand" "=<") 18152 (match_operand:TI 1 "nonmemory_operand" "x"))] 18153 "TARGET_SSE" 18154 "#" 18155 "" 18156 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) 18157 (set (mem:TI (reg:SI 7)) (match_dup 1))] 18158 "" 18159 [(set_attr "type" "multi")]) 18160 18161(define_insn_and_split "*pushv2df" 18162 [(set (match_operand:V2DF 0 "push_operand" "=<") 18163 (match_operand:V2DF 1 "nonmemory_operand" "x"))] 18164 "TARGET_SSE2" 18165 "#" 18166 "" 18167 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) 18168 (set (mem:V2DF (reg:SI 7)) (match_dup 1))] 18169 "" 18170 [(set_attr "type" "multi")]) 18171 18172(define_insn_and_split "*pushv2di" 18173 [(set (match_operand:V2DI 0 "push_operand" "=<") 18174 (match_operand:V2DI 1 "nonmemory_operand" "x"))] 18175 "TARGET_SSE2" 18176 "#" 18177 "" 18178 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) 18179 (set (mem:V2DI (reg:SI 7)) (match_dup 1))] 18180 "" 18181 [(set_attr "type" "multi")]) 18182 18183(define_insn_and_split "*pushv8hi" 18184 [(set (match_operand:V8HI 0 "push_operand" "=<") 18185 (match_operand:V8HI 1 "nonmemory_operand" "x"))] 18186 "TARGET_SSE2" 18187 "#" 18188 "" 18189 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) 18190 (set (mem:V8HI (reg:SI 7)) (match_dup 1))] 18191 "" 18192 [(set_attr "type" "multi")]) 18193 18194(define_insn_and_split "*pushv16qi" 18195 [(set (match_operand:V16QI 0 "push_operand" "=<") 18196 (match_operand:V16QI 1 "nonmemory_operand" "x"))] 18197 "TARGET_SSE2" 18198 "#" 18199 "" 18200 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) 18201 (set (mem:V16QI (reg:SI 7)) (match_dup 1))] 18202 "" 18203 [(set_attr "type" "multi")]) 18204 18205(define_insn_and_split "*pushv4sf" 18206 [(set (match_operand:V4SF 0 "push_operand" "=<") 18207 (match_operand:V4SF 1 "nonmemory_operand" "x"))] 18208 "TARGET_SSE" 18209 "#" 18210 "" 18211 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) 18212 (set (mem:V4SF (reg:SI 7)) (match_dup 1))] 18213 "" 18214 [(set_attr "type" "multi")]) 18215 18216(define_insn_and_split "*pushv4si" 18217 [(set (match_operand:V4SI 0 "push_operand" "=<") 18218 (match_operand:V4SI 1 "nonmemory_operand" "x"))] 18219 "TARGET_SSE" 18220 "#" 18221 "" 18222 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) 18223 (set (mem:V4SI (reg:SI 7)) (match_dup 1))] 18224 "" 18225 [(set_attr "type" "multi")]) 18226 18227(define_insn_and_split "*pushv2si" 18228 [(set (match_operand:V2SI 0 "push_operand" "=<") 18229 (match_operand:V2SI 1 "nonmemory_operand" "y"))] 18230 "TARGET_MMX" 18231 "#" 18232 "" 18233 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) 18234 (set (mem:V2SI (reg:SI 7)) (match_dup 1))] 18235 "" 18236 [(set_attr "type" "mmx")]) 18237 18238(define_insn_and_split "*pushv4hi" 18239 [(set (match_operand:V4HI 0 "push_operand" "=<") 18240 (match_operand:V4HI 1 "nonmemory_operand" "y"))] 18241 "TARGET_MMX" 18242 "#" 18243 "" 18244 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) 18245 (set (mem:V4HI (reg:SI 7)) (match_dup 1))] 18246 "" 18247 [(set_attr "type" "mmx")]) 18248 18249(define_insn_and_split "*pushv8qi" 18250 [(set (match_operand:V8QI 0 "push_operand" "=<") 18251 (match_operand:V8QI 1 "nonmemory_operand" "y"))] 18252 "TARGET_MMX" 18253 "#" 18254 "" 18255 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) 18256 (set (mem:V8QI (reg:SI 7)) (match_dup 1))] 18257 "" 18258 [(set_attr "type" "mmx")]) 18259 18260(define_insn_and_split "*pushv2sf" 18261 [(set (match_operand:V2SF 0 "push_operand" "=<") 18262 (match_operand:V2SF 1 "nonmemory_operand" "y"))] 18263 "TARGET_3DNOW" 18264 "#" 18265 "" 18266 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) 18267 (set (mem:V2SF (reg:SI 7)) (match_dup 1))] 18268 "" 18269 [(set_attr "type" "mmx")]) 18270 18271(define_insn "movti_internal" 18272 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m") 18273 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))] 18274 "TARGET_SSE && !TARGET_64BIT 18275 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 18276 "@ 18277 xorps\t%0, %0 18278 movaps\t{%1, %0|%0, %1} 18279 movaps\t{%1, %0|%0, %1}" 18280 [(set_attr "type" "ssemov,ssemov,ssemov") 18281 (set_attr "mode" "V4SF")]) 18282 18283(define_insn "*movti_rex64" 18284 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,mx,x") 18285 (match_operand:TI 1 "general_operand" "riFo,riF,C,x,m"))] 18286 "TARGET_64BIT 18287 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 18288 "@ 18289 # 18290 # 18291 xorps\t%0, %0 18292 movaps\\t{%1, %0|%0, %1} 18293 movaps\\t{%1, %0|%0, %1}" 18294 [(set_attr "type" "*,*,ssemov,ssemov,ssemov") 18295 (set_attr "mode" "V4SF")]) 18296 18297(define_split 18298 [(set (match_operand:TI 0 "nonimmediate_operand" "") 18299 (match_operand:TI 1 "general_operand" ""))] 18300 "reload_completed && !SSE_REG_P (operands[0]) 18301 && !SSE_REG_P (operands[1])" 18302 [(const_int 0)] 18303 "ix86_split_long_move (operands); DONE;") 18304 18305;; These two patterns are useful for specifying exactly whether to use 18306;; movaps or movups 18307(define_expand "sse_movaps" 18308 [(set (match_operand:V4SF 0 "nonimmediate_operand" "") 18309 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")] 18310 UNSPEC_MOVA))] 18311 "TARGET_SSE" 18312{ 18313 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 18314 { 18315 rtx tmp = gen_reg_rtx (V4SFmode); 18316 emit_insn (gen_sse_movaps (tmp, operands[1])); 18317 emit_move_insn (operands[0], tmp); 18318 DONE; 18319 } 18320}) 18321 18322(define_insn "*sse_movaps_1" 18323 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") 18324 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")] 18325 UNSPEC_MOVA))] 18326 "TARGET_SSE 18327 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 18328 "movaps\t{%1, %0|%0, %1}" 18329 [(set_attr "type" "ssemov,ssemov") 18330 (set_attr "mode" "V4SF")]) 18331 18332(define_expand "sse_movups" 18333 [(set (match_operand:V4SF 0 "nonimmediate_operand" "") 18334 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")] 18335 UNSPEC_MOVU))] 18336 "TARGET_SSE" 18337{ 18338 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 18339 { 18340 rtx tmp = gen_reg_rtx (V4SFmode); 18341 emit_insn (gen_sse_movups (tmp, operands[1])); 18342 emit_move_insn (operands[0], tmp); 18343 DONE; 18344 } 18345}) 18346 18347(define_insn "*sse_movups_1" 18348 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") 18349 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")] 18350 UNSPEC_MOVU))] 18351 "TARGET_SSE 18352 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 18353 "movups\t{%1, %0|%0, %1}" 18354 [(set_attr "type" "ssecvt,ssecvt") 18355 (set_attr "mode" "V4SF")]) 18356 18357;; SSE Strange Moves. 18358 18359(define_insn "sse_movmskps" 18360 [(set (match_operand:SI 0 "register_operand" "=r") 18361 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 18362 UNSPEC_MOVMSK))] 18363 "TARGET_SSE" 18364 "movmskps\t{%1, %0|%0, %1}" 18365 [(set_attr "type" "ssecvt") 18366 (set_attr "mode" "V4SF")]) 18367 18368(define_insn "mmx_pmovmskb" 18369 [(set (match_operand:SI 0 "register_operand" "=r") 18370 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 18371 UNSPEC_MOVMSK))] 18372 "TARGET_SSE || TARGET_3DNOW_A" 18373 "pmovmskb\t{%1, %0|%0, %1}" 18374 [(set_attr "type" "ssecvt") 18375 (set_attr "mode" "V4SF")]) 18376 18377 18378(define_insn "mmx_maskmovq" 18379 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D")) 18380 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") 18381 (match_operand:V8QI 2 "register_operand" "y")] 18382 UNSPEC_MASKMOV))] 18383 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT" 18384 ;; @@@ check ordering of operands in intel/nonintel syntax 18385 "maskmovq\t{%2, %1|%1, %2}" 18386 [(set_attr "type" "mmxcvt") 18387 (set_attr "mode" "DI")]) 18388 18389(define_insn "mmx_maskmovq_rex" 18390 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D")) 18391 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") 18392 (match_operand:V8QI 2 "register_operand" "y")] 18393 UNSPEC_MASKMOV))] 18394 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT" 18395 ;; @@@ check ordering of operands in intel/nonintel syntax 18396 "maskmovq\t{%2, %1|%1, %2}" 18397 [(set_attr "type" "mmxcvt") 18398 (set_attr "mode" "DI")]) 18399 18400(define_insn "sse_movntv4sf" 18401 [(set (match_operand:V4SF 0 "memory_operand" "=m") 18402 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 18403 UNSPEC_MOVNT))] 18404 "TARGET_SSE" 18405 "movntps\t{%1, %0|%0, %1}" 18406 [(set_attr "type" "ssemov") 18407 (set_attr "mode" "V4SF")]) 18408 18409(define_insn "sse_movntdi" 18410 [(set (match_operand:DI 0 "memory_operand" "=m") 18411 (unspec:DI [(match_operand:DI 1 "register_operand" "y")] 18412 UNSPEC_MOVNT))] 18413 "TARGET_SSE || TARGET_3DNOW_A" 18414 "movntq\t{%1, %0|%0, %1}" 18415 [(set_attr "type" "mmxmov") 18416 (set_attr "mode" "DI")]) 18417 18418(define_insn "sse_movhlps" 18419 [(set (match_operand:V4SF 0 "register_operand" "=x") 18420 (vec_merge:V4SF 18421 (match_operand:V4SF 1 "register_operand" "0") 18422 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x") 18423 (parallel [(const_int 2) 18424 (const_int 3) 18425 (const_int 0) 18426 (const_int 1)])) 18427 (const_int 3)))] 18428 "TARGET_SSE" 18429 "movhlps\t{%2, %0|%0, %2}" 18430 [(set_attr "type" "ssecvt") 18431 (set_attr "mode" "V4SF")]) 18432 18433(define_insn "sse_movlhps" 18434 [(set (match_operand:V4SF 0 "register_operand" "=x") 18435 (vec_merge:V4SF 18436 (match_operand:V4SF 1 "register_operand" "0") 18437 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x") 18438 (parallel [(const_int 2) 18439 (const_int 3) 18440 (const_int 0) 18441 (const_int 1)])) 18442 (const_int 12)))] 18443 "TARGET_SSE" 18444 "movlhps\t{%2, %0|%0, %2}" 18445 [(set_attr "type" "ssecvt") 18446 (set_attr "mode" "V4SF")]) 18447 18448(define_insn "sse_movhps" 18449 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") 18450 (vec_merge:V4SF 18451 (match_operand:V4SF 1 "nonimmediate_operand" "0,0") 18452 (match_operand:V4SF 2 "nonimmediate_operand" "m,x") 18453 (const_int 12)))] 18454 "TARGET_SSE 18455 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)" 18456 "movhps\t{%2, %0|%0, %2}" 18457 [(set_attr "type" "ssecvt") 18458 (set_attr "mode" "V4SF")]) 18459 18460(define_insn "sse_movlps" 18461 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") 18462 (vec_merge:V4SF 18463 (match_operand:V4SF 1 "nonimmediate_operand" "0,0") 18464 (match_operand:V4SF 2 "nonimmediate_operand" "m,x") 18465 (const_int 3)))] 18466 "TARGET_SSE 18467 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)" 18468 "movlps\t{%2, %0|%0, %2}" 18469 [(set_attr "type" "ssecvt") 18470 (set_attr "mode" "V4SF")]) 18471 18472(define_expand "sse_loadss" 18473 [(match_operand:V4SF 0 "register_operand" "") 18474 (match_operand:SF 1 "memory_operand" "")] 18475 "TARGET_SSE" 18476{ 18477 emit_insn (gen_sse_loadss_1 (operands[0], operands[1], 18478 CONST0_RTX (V4SFmode))); 18479 DONE; 18480}) 18481 18482(define_insn "sse_loadss_1" 18483 [(set (match_operand:V4SF 0 "register_operand" "=x") 18484 (vec_merge:V4SF 18485 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m")) 18486 (match_operand:V4SF 2 "const0_operand" "X") 18487 (const_int 1)))] 18488 "TARGET_SSE" 18489 "movss\t{%1, %0|%0, %1}" 18490 [(set_attr "type" "ssemov") 18491 (set_attr "mode" "SF")]) 18492 18493(define_insn "sse_movss" 18494 [(set (match_operand:V4SF 0 "register_operand" "=x") 18495 (vec_merge:V4SF 18496 (match_operand:V4SF 1 "register_operand" "0") 18497 (match_operand:V4SF 2 "register_operand" "x") 18498 (const_int 1)))] 18499 "TARGET_SSE" 18500 "movss\t{%2, %0|%0, %2}" 18501 [(set_attr "type" "ssemov") 18502 (set_attr "mode" "SF")]) 18503 18504(define_insn "sse_storess" 18505 [(set (match_operand:SF 0 "memory_operand" "=m") 18506 (vec_select:SF 18507 (match_operand:V4SF 1 "register_operand" "x") 18508 (parallel [(const_int 0)])))] 18509 "TARGET_SSE" 18510 "movss\t{%1, %0|%0, %1}" 18511 [(set_attr "type" "ssemov") 18512 (set_attr "mode" "SF")]) 18513 18514(define_insn "sse_shufps" 18515 [(set (match_operand:V4SF 0 "register_operand" "=x") 18516 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") 18517 (match_operand:V4SF 2 "nonimmediate_operand" "xm") 18518 (match_operand:SI 3 "immediate_operand" "i")] 18519 UNSPEC_SHUFFLE))] 18520 "TARGET_SSE" 18521 ;; @@@ check operand order for intel/nonintel syntax 18522 "shufps\t{%3, %2, %0|%0, %2, %3}" 18523 [(set_attr "type" "ssecvt") 18524 (set_attr "mode" "V4SF")]) 18525 18526 18527;; SSE arithmetic 18528 18529(define_insn "addv4sf3" 18530 [(set (match_operand:V4SF 0 "register_operand" "=x") 18531 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0") 18532 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] 18533 "TARGET_SSE" 18534 "addps\t{%2, %0|%0, %2}" 18535 [(set_attr "type" "sseadd") 18536 (set_attr "mode" "V4SF")]) 18537 18538(define_insn "vmaddv4sf3" 18539 [(set (match_operand:V4SF 0 "register_operand" "=x") 18540 (vec_merge:V4SF 18541 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0") 18542 (match_operand:V4SF 2 "nonimmediate_operand" "xm")) 18543 (match_dup 1) 18544 (const_int 1)))] 18545 "TARGET_SSE" 18546 "addss\t{%2, %0|%0, %2}" 18547 [(set_attr "type" "sseadd") 18548 (set_attr "mode" "SF")]) 18549 18550(define_insn "subv4sf3" 18551 [(set (match_operand:V4SF 0 "register_operand" "=x") 18552 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0") 18553 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] 18554 "TARGET_SSE" 18555 "subps\t{%2, %0|%0, %2}" 18556 [(set_attr "type" "sseadd") 18557 (set_attr "mode" "V4SF")]) 18558 18559(define_insn "vmsubv4sf3" 18560 [(set (match_operand:V4SF 0 "register_operand" "=x") 18561 (vec_merge:V4SF 18562 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0") 18563 (match_operand:V4SF 2 "nonimmediate_operand" "xm")) 18564 (match_dup 1) 18565 (const_int 1)))] 18566 "TARGET_SSE" 18567 "subss\t{%2, %0|%0, %2}" 18568 [(set_attr "type" "sseadd") 18569 (set_attr "mode" "SF")]) 18570 18571(define_insn "mulv4sf3" 18572 [(set (match_operand:V4SF 0 "register_operand" "=x") 18573 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0") 18574 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] 18575 "TARGET_SSE" 18576 "mulps\t{%2, %0|%0, %2}" 18577 [(set_attr "type" "ssemul") 18578 (set_attr "mode" "V4SF")]) 18579 18580(define_insn "vmmulv4sf3" 18581 [(set (match_operand:V4SF 0 "register_operand" "=x") 18582 (vec_merge:V4SF 18583 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0") 18584 (match_operand:V4SF 2 "nonimmediate_operand" "xm")) 18585 (match_dup 1) 18586 (const_int 1)))] 18587 "TARGET_SSE" 18588 "mulss\t{%2, %0|%0, %2}" 18589 [(set_attr "type" "ssemul") 18590 (set_attr "mode" "SF")]) 18591 18592(define_insn "divv4sf3" 18593 [(set (match_operand:V4SF 0 "register_operand" "=x") 18594 (div:V4SF (match_operand:V4SF 1 "register_operand" "0") 18595 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] 18596 "TARGET_SSE" 18597 "divps\t{%2, %0|%0, %2}" 18598 [(set_attr "type" "ssediv") 18599 (set_attr "mode" "V4SF")]) 18600 18601(define_insn "vmdivv4sf3" 18602 [(set (match_operand:V4SF 0 "register_operand" "=x") 18603 (vec_merge:V4SF 18604 (div:V4SF (match_operand:V4SF 1 "register_operand" "0") 18605 (match_operand:V4SF 2 "nonimmediate_operand" "xm")) 18606 (match_dup 1) 18607 (const_int 1)))] 18608 "TARGET_SSE" 18609 "divss\t{%2, %0|%0, %2}" 18610 [(set_attr "type" "ssediv") 18611 (set_attr "mode" "SF")]) 18612 18613 18614;; SSE square root/reciprocal 18615 18616(define_insn "rcpv4sf2" 18617 [(set (match_operand:V4SF 0 "register_operand" "=x") 18618 (unspec:V4SF 18619 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))] 18620 "TARGET_SSE" 18621 "rcpps\t{%1, %0|%0, %1}" 18622 [(set_attr "type" "sse") 18623 (set_attr "mode" "V4SF")]) 18624 18625(define_insn "vmrcpv4sf2" 18626 [(set (match_operand:V4SF 0 "register_operand" "=x") 18627 (vec_merge:V4SF 18628 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 18629 UNSPEC_RCP) 18630 (match_operand:V4SF 2 "register_operand" "0") 18631 (const_int 1)))] 18632 "TARGET_SSE" 18633 "rcpss\t{%1, %0|%0, %1}" 18634 [(set_attr "type" "sse") 18635 (set_attr "mode" "SF")]) 18636 18637(define_insn "rsqrtv4sf2" 18638 [(set (match_operand:V4SF 0 "register_operand" "=x") 18639 (unspec:V4SF 18640 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))] 18641 "TARGET_SSE" 18642 "rsqrtps\t{%1, %0|%0, %1}" 18643 [(set_attr "type" "sse") 18644 (set_attr "mode" "V4SF")]) 18645 18646(define_insn "vmrsqrtv4sf2" 18647 [(set (match_operand:V4SF 0 "register_operand" "=x") 18648 (vec_merge:V4SF 18649 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 18650 UNSPEC_RSQRT) 18651 (match_operand:V4SF 2 "register_operand" "0") 18652 (const_int 1)))] 18653 "TARGET_SSE" 18654 "rsqrtss\t{%1, %0|%0, %1}" 18655 [(set_attr "type" "sse") 18656 (set_attr "mode" "SF")]) 18657 18658(define_insn "sqrtv4sf2" 18659 [(set (match_operand:V4SF 0 "register_operand" "=x") 18660 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))] 18661 "TARGET_SSE" 18662 "sqrtps\t{%1, %0|%0, %1}" 18663 [(set_attr "type" "sse") 18664 (set_attr "mode" "V4SF")]) 18665 18666(define_insn "vmsqrtv4sf2" 18667 [(set (match_operand:V4SF 0 "register_operand" "=x") 18668 (vec_merge:V4SF 18669 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")) 18670 (match_operand:V4SF 2 "register_operand" "0") 18671 (const_int 1)))] 18672 "TARGET_SSE" 18673 "sqrtss\t{%1, %0|%0, %1}" 18674 [(set_attr "type" "sse") 18675 (set_attr "mode" "SF")]) 18676 18677;; SSE logical operations. 18678 18679;; SSE defines logical operations on floating point values. This brings 18680;; interesting challenge to RTL representation where logicals are only valid 18681;; on integral types. We deal with this by representing the floating point 18682;; logical as logical on arguments casted to TImode as this is what hardware 18683;; really does. Unfortunately hardware requires the type information to be 18684;; present and thus we must avoid subregs from being simplified and elliminated 18685;; in later compilation phases. 18686;; 18687;; We have following variants from each instruction: 18688;; sse_andsf3 - the operation taking V4SF vector operands 18689;; and doing TImode cast on them 18690;; *sse_andsf3_memory - the operation taking one memory operand casted to 18691;; TImode, since backend insist on elliminating casts 18692;; on memory operands 18693;; sse_andti3_sf_1 - the operation taking SF scalar operands. 18694;; We can not accept memory operand here as instruction reads 18695;; whole scalar. This is generated only post reload by GCC 18696;; scalar float operations that expands to logicals (fabs) 18697;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode 18698;; memory operand. Eventually combine can be able 18699;; to synthetize these using splitter. 18700;; sse2_anddf3, *sse2_anddf3_memory 18701;; 18702;; 18703;; These are not called andti3 etc. because we really really don't want 18704;; the compiler to widen DImode ands to TImode ands and then try to move 18705;; into DImode subregs of SSE registers, and them together, and move out 18706;; of DImode subregs again! 18707;; SSE1 single precision floating point logical operation 18708(define_expand "sse_andv4sf3" 18709 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0) 18710 (and:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0) 18711 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))] 18712 "TARGET_SSE" 18713 "") 18714 18715(define_insn "*sse_andv4sf3" 18716 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0) 18717 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18718 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18719 "TARGET_SSE 18720 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18721 "andps\t{%2, %0|%0, %2}" 18722 [(set_attr "type" "sselog") 18723 (set_attr "mode" "V4SF")]) 18724 18725(define_insn "*sse_andsf3" 18726 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) 18727 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18728 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18729 "TARGET_SSE 18730 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18731 "andps\t{%2, %0|%0, %2}" 18732 [(set_attr "type" "sselog") 18733 (set_attr "mode" "V4SF")]) 18734 18735(define_expand "sse_nandv4sf3" 18736 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0) 18737 (and:TI (not:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)) 18738 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))] 18739 "TARGET_SSE" 18740 "") 18741 18742(define_insn "*sse_nandv4sf3" 18743 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0) 18744 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) 18745 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18746 "TARGET_SSE" 18747 "andnps\t{%2, %0|%0, %2}" 18748 [(set_attr "type" "sselog") 18749 (set_attr "mode" "V4SF")]) 18750 18751(define_insn "*sse_nandsf3" 18752 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) 18753 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) 18754 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18755 "TARGET_SSE" 18756 "andnps\t{%2, %0|%0, %2}" 18757 [(set_attr "type" "sselog") 18758 (set_attr "mode" "V4SF")]) 18759 18760(define_expand "sse_iorv4sf3" 18761 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0) 18762 (ior:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0) 18763 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))] 18764 "TARGET_SSE" 18765 "") 18766 18767(define_insn "*sse_iorv4sf3" 18768 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0) 18769 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18770 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18771 "TARGET_SSE 18772 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18773 "orps\t{%2, %0|%0, %2}" 18774 [(set_attr "type" "sselog") 18775 (set_attr "mode" "V4SF")]) 18776 18777(define_insn "*sse_iorsf3" 18778 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) 18779 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18780 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18781 "TARGET_SSE 18782 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18783 "orps\t{%2, %0|%0, %2}" 18784 [(set_attr "type" "sselog") 18785 (set_attr "mode" "V4SF")]) 18786 18787(define_expand "sse_xorv4sf3" 18788 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0) 18789 (xor:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0) 18790 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))] 18791 "TARGET_SSE 18792 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18793 "") 18794 18795(define_insn "*sse_xorv4sf3" 18796 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0) 18797 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18798 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18799 "TARGET_SSE 18800 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18801 "xorps\t{%2, %0|%0, %2}" 18802 [(set_attr "type" "sselog") 18803 (set_attr "mode" "V4SF")]) 18804 18805(define_insn "*sse_xorsf3" 18806 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) 18807 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18808 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18809 "TARGET_SSE 18810 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18811 "xorps\t{%2, %0|%0, %2}" 18812 [(set_attr "type" "sselog") 18813 (set_attr "mode" "V4SF")]) 18814 18815;; SSE2 double precision floating point logical operation 18816 18817(define_expand "sse2_andv2df3" 18818 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0) 18819 (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0) 18820 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))] 18821 "TARGET_SSE2" 18822 "") 18823 18824(define_insn "*sse2_andv2df3" 18825 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0) 18826 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18827 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18828 "TARGET_SSE2 18829 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18830 "andpd\t{%2, %0|%0, %2}" 18831 [(set_attr "type" "sselog") 18832 (set_attr "mode" "V2DF")]) 18833 18834(define_insn "*sse2_andv2df3" 18835 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0) 18836 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18837 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18838 "TARGET_SSE2 18839 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18840 "andpd\t{%2, %0|%0, %2}" 18841 [(set_attr "type" "sselog") 18842 (set_attr "mode" "V2DF")]) 18843 18844(define_expand "sse2_nandv2df3" 18845 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0) 18846 (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)) 18847 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))] 18848 "TARGET_SSE2" 18849 "") 18850 18851(define_insn "*sse2_nandv2df3" 18852 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0) 18853 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) 18854 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18855 "TARGET_SSE2" 18856 "andnpd\t{%2, %0|%0, %2}" 18857 [(set_attr "type" "sselog") 18858 (set_attr "mode" "V2DF")]) 18859 18860(define_insn "*sse_nandti3_df" 18861 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) 18862 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) 18863 (match_operand:TI 2 "nonimmediate_operand" "Ym")))] 18864 "TARGET_SSE2" 18865 "andnpd\t{%2, %0|%0, %2}" 18866 [(set_attr "type" "sselog") 18867 (set_attr "mode" "V2DF")]) 18868 18869(define_expand "sse2_iorv2df3" 18870 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0) 18871 (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0) 18872 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))] 18873 "TARGET_SSE2" 18874 "") 18875 18876(define_insn "*sse2_iorv2df3" 18877 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0) 18878 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18879 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18880 "TARGET_SSE2 18881 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18882 "orpd\t{%2, %0|%0, %2}" 18883 [(set_attr "type" "sselog") 18884 (set_attr "mode" "V2DF")]) 18885 18886(define_insn "*sse2_iordf3" 18887 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0) 18888 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18889 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18890 "TARGET_SSE2 18891 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18892 "orpd\t{%2, %0|%0, %2}" 18893 [(set_attr "type" "sselog") 18894 (set_attr "mode" "V2DF")]) 18895 18896(define_expand "sse2_xorv2df3" 18897 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0) 18898 (xor:TI (subreg:TI (match_operand:V2DF 1 "nonimmediate_operand" "") 0) 18899 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))] 18900 "TARGET_SSE2" 18901 "") 18902 18903(define_insn "*sse2_xorv2df3" 18904 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0) 18905 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18906 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18907 "TARGET_SSE2 18908 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18909 "xorpd\t{%2, %0|%0, %2}" 18910 [(set_attr "type" "sselog") 18911 (set_attr "mode" "V2DF")]) 18912 18913(define_insn "*sse2_xordf3" 18914 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0) 18915 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18916 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18917 "TARGET_SSE2 18918 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18919 "xorpd\t{%2, %0|%0, %2}" 18920 [(set_attr "type" "sselog") 18921 (set_attr "mode" "V2DF")]) 18922 18923;; SSE2 integral logicals. These patterns must always come after floating 18924;; point ones since we don't want compiler to use integer opcodes on floating 18925;; point SSE values to avoid matching of subregs in the match_operand. 18926(define_insn "*sse2_andti3" 18927 [(set (match_operand:TI 0 "register_operand" "=x") 18928 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18929 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18930 "TARGET_SSE2 18931 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18932 "pand\t{%2, %0|%0, %2}" 18933 [(set_attr "type" "sselog") 18934 (set_attr "mode" "TI")]) 18935 18936(define_insn "sse2_andv2di3" 18937 [(set (match_operand:V2DI 0 "register_operand" "=x") 18938 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0") 18939 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))] 18940 "TARGET_SSE2 18941 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18942 "pand\t{%2, %0|%0, %2}" 18943 [(set_attr "type" "sselog") 18944 (set_attr "mode" "TI")]) 18945 18946(define_insn "*sse2_nandti3" 18947 [(set (match_operand:TI 0 "register_operand" "=x") 18948 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) 18949 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18950 "TARGET_SSE2" 18951 "pandn\t{%2, %0|%0, %2}" 18952 [(set_attr "type" "sselog") 18953 (set_attr "mode" "TI")]) 18954 18955(define_insn "sse2_nandv2di3" 18956 [(set (match_operand:V2DI 0 "register_operand" "=x") 18957 (and:V2DI (not:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "0")) 18958 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))] 18959 "TARGET_SSE2 18960 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18961 "pandn\t{%2, %0|%0, %2}" 18962 [(set_attr "type" "sselog") 18963 (set_attr "mode" "TI")]) 18964 18965(define_insn "*sse2_iorti3" 18966 [(set (match_operand:TI 0 "register_operand" "=x") 18967 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18968 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18969 "TARGET_SSE2 18970 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18971 "por\t{%2, %0|%0, %2}" 18972 [(set_attr "type" "sselog") 18973 (set_attr "mode" "TI")]) 18974 18975(define_insn "sse2_iorv2di3" 18976 [(set (match_operand:V2DI 0 "register_operand" "=x") 18977 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0") 18978 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))] 18979 "TARGET_SSE2 18980 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18981 "por\t{%2, %0|%0, %2}" 18982 [(set_attr "type" "sselog") 18983 (set_attr "mode" "TI")]) 18984 18985(define_insn "*sse2_xorti3" 18986 [(set (match_operand:TI 0 "register_operand" "=x") 18987 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 18988 (match_operand:TI 2 "nonimmediate_operand" "xm")))] 18989 "TARGET_SSE2 18990 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 18991 "pxor\t{%2, %0|%0, %2}" 18992 [(set_attr "type" "sselog") 18993 (set_attr "mode" "TI")]) 18994 18995(define_insn "sse2_xorv2di3" 18996 [(set (match_operand:V2DI 0 "register_operand" "=x") 18997 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0") 18998 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))] 18999 "TARGET_SSE2 19000 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" 19001 "pxor\t{%2, %0|%0, %2}" 19002 [(set_attr "type" "sselog") 19003 (set_attr "mode" "TI")]) 19004 19005;; Use xor, but don't show input operands so they aren't live before 19006;; this insn. 19007(define_insn "sse_clrv4sf" 19008 [(set (match_operand:V4SF 0 "register_operand" "=x") 19009 (unspec:V4SF [(const_int 0)] UNSPEC_NOP))] 19010 "TARGET_SSE" 19011 "xorps\t{%0, %0|%0, %0}" 19012 [(set_attr "type" "sselog") 19013 (set_attr "memory" "none") 19014 (set_attr "mode" "V4SF")]) 19015 19016;; Use xor, but don't show input operands so they aren't live before 19017;; this insn. 19018(define_insn "sse_clrv2df" 19019 [(set (match_operand:V2DF 0 "register_operand" "=x") 19020 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))] 19021 "TARGET_SSE2" 19022 "xorpd\t{%0, %0|%0, %0}" 19023 [(set_attr "type" "sselog") 19024 (set_attr "memory" "none") 19025 (set_attr "mode" "V4SF")]) 19026 19027;; SSE mask-generating compares 19028 19029(define_insn "maskcmpv4sf3" 19030 [(set (match_operand:V4SI 0 "register_operand" "=x") 19031 (match_operator:V4SI 3 "sse_comparison_operator" 19032 [(match_operand:V4SF 1 "register_operand" "0") 19033 (match_operand:V4SF 2 "register_operand" "x")]))] 19034 "TARGET_SSE" 19035 "cmp%D3ps\t{%2, %0|%0, %2}" 19036 [(set_attr "type" "ssecmp") 19037 (set_attr "mode" "V4SF")]) 19038 19039(define_insn "maskncmpv4sf3" 19040 [(set (match_operand:V4SI 0 "register_operand" "=x") 19041 (not:V4SI 19042 (match_operator:V4SI 3 "sse_comparison_operator" 19043 [(match_operand:V4SF 1 "register_operand" "0") 19044 (match_operand:V4SF 2 "register_operand" "x")])))] 19045 "TARGET_SSE" 19046{ 19047 if (GET_CODE (operands[3]) == UNORDERED) 19048 return "cmpordps\t{%2, %0|%0, %2}"; 19049 else 19050 return "cmpn%D3ps\t{%2, %0|%0, %2}"; 19051} 19052 [(set_attr "type" "ssecmp") 19053 (set_attr "mode" "V4SF")]) 19054 19055(define_insn "vmmaskcmpv4sf3" 19056 [(set (match_operand:V4SI 0 "register_operand" "=x") 19057 (vec_merge:V4SI 19058 (match_operator:V4SI 3 "sse_comparison_operator" 19059 [(match_operand:V4SF 1 "register_operand" "0") 19060 (match_operand:V4SF 2 "register_operand" "x")]) 19061 (subreg:V4SI (match_dup 1) 0) 19062 (const_int 1)))] 19063 "TARGET_SSE" 19064 "cmp%D3ss\t{%2, %0|%0, %2}" 19065 [(set_attr "type" "ssecmp") 19066 (set_attr "mode" "SF")]) 19067 19068(define_insn "vmmaskncmpv4sf3" 19069 [(set (match_operand:V4SI 0 "register_operand" "=x") 19070 (vec_merge:V4SI 19071 (not:V4SI 19072 (match_operator:V4SI 3 "sse_comparison_operator" 19073 [(match_operand:V4SF 1 "register_operand" "0") 19074 (match_operand:V4SF 2 "register_operand" "x")])) 19075 (subreg:V4SI (match_dup 1) 0) 19076 (const_int 1)))] 19077 "TARGET_SSE" 19078{ 19079 if (GET_CODE (operands[3]) == UNORDERED) 19080 return "cmpordss\t{%2, %0|%0, %2}"; 19081 else 19082 return "cmpn%D3ss\t{%2, %0|%0, %2}"; 19083} 19084 [(set_attr "type" "ssecmp") 19085 (set_attr "mode" "SF")]) 19086 19087(define_insn "sse_comi" 19088 [(set (reg:CCFP 17) 19089 (compare:CCFP (vec_select:SF 19090 (match_operand:V4SF 0 "register_operand" "x") 19091 (parallel [(const_int 0)])) 19092 (vec_select:SF 19093 (match_operand:V4SF 1 "register_operand" "x") 19094 (parallel [(const_int 0)]))))] 19095 "TARGET_SSE" 19096 "comiss\t{%1, %0|%0, %1}" 19097 [(set_attr "type" "ssecmp") 19098 (set_attr "mode" "SF")]) 19099 19100(define_insn "sse_ucomi" 19101 [(set (reg:CCFPU 17) 19102 (compare:CCFPU (vec_select:SF 19103 (match_operand:V4SF 0 "register_operand" "x") 19104 (parallel [(const_int 0)])) 19105 (vec_select:SF 19106 (match_operand:V4SF 1 "register_operand" "x") 19107 (parallel [(const_int 0)]))))] 19108 "TARGET_SSE" 19109 "ucomiss\t{%1, %0|%0, %1}" 19110 [(set_attr "type" "ssecmp") 19111 (set_attr "mode" "SF")]) 19112 19113 19114;; SSE unpack 19115 19116(define_insn "sse_unpckhps" 19117 [(set (match_operand:V4SF 0 "register_operand" "=x") 19118 (vec_merge:V4SF 19119 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0") 19120 (parallel [(const_int 2) 19121 (const_int 0) 19122 (const_int 3) 19123 (const_int 1)])) 19124 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x") 19125 (parallel [(const_int 0) 19126 (const_int 2) 19127 (const_int 1) 19128 (const_int 3)])) 19129 (const_int 5)))] 19130 "TARGET_SSE" 19131 "unpckhps\t{%2, %0|%0, %2}" 19132 [(set_attr "type" "ssecvt") 19133 (set_attr "mode" "V4SF")]) 19134 19135(define_insn "sse_unpcklps" 19136 [(set (match_operand:V4SF 0 "register_operand" "=x") 19137 (vec_merge:V4SF 19138 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0") 19139 (parallel [(const_int 0) 19140 (const_int 2) 19141 (const_int 1) 19142 (const_int 3)])) 19143 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x") 19144 (parallel [(const_int 2) 19145 (const_int 0) 19146 (const_int 3) 19147 (const_int 1)])) 19148 (const_int 5)))] 19149 "TARGET_SSE" 19150 "unpcklps\t{%2, %0|%0, %2}" 19151 [(set_attr "type" "ssecvt") 19152 (set_attr "mode" "V4SF")]) 19153 19154 19155;; SSE min/max 19156 19157(define_insn "smaxv4sf3" 19158 [(set (match_operand:V4SF 0 "register_operand" "=x") 19159 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0") 19160 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] 19161 "TARGET_SSE" 19162 "maxps\t{%2, %0|%0, %2}" 19163 [(set_attr "type" "sse") 19164 (set_attr "mode" "V4SF")]) 19165 19166(define_insn "vmsmaxv4sf3" 19167 [(set (match_operand:V4SF 0 "register_operand" "=x") 19168 (vec_merge:V4SF 19169 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0") 19170 (match_operand:V4SF 2 "nonimmediate_operand" "xm")) 19171 (match_dup 1) 19172 (const_int 1)))] 19173 "TARGET_SSE" 19174 "maxss\t{%2, %0|%0, %2}" 19175 [(set_attr "type" "sse") 19176 (set_attr "mode" "SF")]) 19177 19178(define_insn "sminv4sf3" 19179 [(set (match_operand:V4SF 0 "register_operand" "=x") 19180 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0") 19181 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] 19182 "TARGET_SSE" 19183 "minps\t{%2, %0|%0, %2}" 19184 [(set_attr "type" "sse") 19185 (set_attr "mode" "V4SF")]) 19186 19187(define_insn "vmsminv4sf3" 19188 [(set (match_operand:V4SF 0 "register_operand" "=x") 19189 (vec_merge:V4SF 19190 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0") 19191 (match_operand:V4SF 2 "nonimmediate_operand" "xm")) 19192 (match_dup 1) 19193 (const_int 1)))] 19194 "TARGET_SSE" 19195 "minss\t{%2, %0|%0, %2}" 19196 [(set_attr "type" "sse") 19197 (set_attr "mode" "SF")]) 19198 19199;; SSE <-> integer/MMX conversions 19200 19201(define_insn "cvtpi2ps" 19202 [(set (match_operand:V4SF 0 "register_operand" "=x") 19203 (vec_merge:V4SF 19204 (match_operand:V4SF 1 "register_operand" "0") 19205 (vec_duplicate:V4SF 19206 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym"))) 19207 (const_int 12)))] 19208 "TARGET_SSE" 19209 "cvtpi2ps\t{%2, %0|%0, %2}" 19210 [(set_attr "type" "ssecvt") 19211 (set_attr "mode" "V4SF")]) 19212 19213(define_insn "cvtps2pi" 19214 [(set (match_operand:V2SI 0 "register_operand" "=y") 19215 (vec_select:V2SI 19216 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")) 19217 (parallel [(const_int 0) (const_int 1)])))] 19218 "TARGET_SSE" 19219 "cvtps2pi\t{%1, %0|%0, %1}" 19220 [(set_attr "type" "ssecvt") 19221 (set_attr "mode" "V4SF")]) 19222 19223(define_insn "cvttps2pi" 19224 [(set (match_operand:V2SI 0 "register_operand" "=y") 19225 (vec_select:V2SI 19226 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 19227 UNSPEC_FIX) 19228 (parallel [(const_int 0) (const_int 1)])))] 19229 "TARGET_SSE" 19230 "cvttps2pi\t{%1, %0|%0, %1}" 19231 [(set_attr "type" "ssecvt") 19232 (set_attr "mode" "SF")]) 19233 19234(define_insn "cvtsi2ss" 19235 [(set (match_operand:V4SF 0 "register_operand" "=x") 19236 (vec_merge:V4SF 19237 (match_operand:V4SF 1 "register_operand" "0") 19238 (vec_duplicate:V4SF 19239 (float:SF (match_operand:SI 2 "nonimmediate_operand" "rm"))) 19240 (const_int 14)))] 19241 "TARGET_SSE" 19242 "cvtsi2ss\t{%2, %0|%0, %2}" 19243 [(set_attr "type" "ssecvt") 19244 (set_attr "mode" "SF")]) 19245 19246(define_insn "cvtsi2ssq" 19247 [(set (match_operand:V4SF 0 "register_operand" "=x,x") 19248 (vec_merge:V4SF 19249 (match_operand:V4SF 1 "register_operand" "0,0") 19250 (vec_duplicate:V4SF 19251 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm"))) 19252 (const_int 14)))] 19253 "TARGET_SSE && TARGET_64BIT" 19254 "cvtsi2ssq\t{%2, %0|%0, %2}" 19255 [(set_attr "type" "ssecvt") 19256 (set_attr "athlon_decode" "vector,vector") 19257 (set_attr "mode" "SF")]) 19258 19259(define_insn "cvtss2si" 19260 [(set (match_operand:SI 0 "register_operand" "=r") 19261 (vec_select:SI 19262 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")) 19263 (parallel [(const_int 0)])))] 19264 "TARGET_SSE" 19265 "cvtss2si\t{%1, %0|%0, %1}" 19266 [(set_attr "type" "ssecvt") 19267 (set_attr "mode" "SF")]) 19268 19269(define_insn "cvtss2siq" 19270 [(set (match_operand:DI 0 "register_operand" "=r,r") 19271 (vec_select:DI 19272 (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m")) 19273 (parallel [(const_int 0)])))] 19274 "TARGET_SSE" 19275 "cvtss2siq\t{%1, %0|%0, %1}" 19276 [(set_attr "type" "ssecvt") 19277 (set_attr "athlon_decode" "vector,vector") 19278 (set_attr "mode" "SF")]) 19279 19280(define_insn "cvttss2si" 19281 [(set (match_operand:SI 0 "register_operand" "=r") 19282 (vec_select:SI 19283 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 19284 UNSPEC_FIX) 19285 (parallel [(const_int 0)])))] 19286 "TARGET_SSE" 19287 "cvttss2si\t{%1, %0|%0, %1}" 19288 [(set_attr "type" "ssecvt") 19289 (set_attr "mode" "SF")]) 19290 19291(define_insn "cvttss2siq" 19292 [(set (match_operand:DI 0 "register_operand" "=r,r") 19293 (vec_select:DI 19294 (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")] 19295 UNSPEC_FIX) 19296 (parallel [(const_int 0)])))] 19297 "TARGET_SSE && TARGET_64BIT" 19298 "cvttss2siq\t{%1, %0|%0, %1}" 19299 [(set_attr "type" "ssecvt") 19300 (set_attr "mode" "SF") 19301 (set_attr "athlon_decode" "vector,vector")]) 19302 19303 19304;; MMX insns 19305 19306;; MMX arithmetic 19307 19308(define_insn "addv8qi3" 19309 [(set (match_operand:V8QI 0 "register_operand" "=y") 19310 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0") 19311 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] 19312 "TARGET_MMX" 19313 "paddb\t{%2, %0|%0, %2}" 19314 [(set_attr "type" "mmxadd") 19315 (set_attr "mode" "DI")]) 19316 19317(define_insn "addv4hi3" 19318 [(set (match_operand:V4HI 0 "register_operand" "=y") 19319 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0") 19320 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] 19321 "TARGET_MMX" 19322 "paddw\t{%2, %0|%0, %2}" 19323 [(set_attr "type" "mmxadd") 19324 (set_attr "mode" "DI")]) 19325 19326(define_insn "addv2si3" 19327 [(set (match_operand:V2SI 0 "register_operand" "=y") 19328 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0") 19329 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))] 19330 "TARGET_MMX" 19331 "paddd\t{%2, %0|%0, %2}" 19332 [(set_attr "type" "mmxadd") 19333 (set_attr "mode" "DI")]) 19334 19335(define_insn "mmx_adddi3" 19336 [(set (match_operand:DI 0 "register_operand" "=y") 19337 (unspec:DI 19338 [(plus:DI (match_operand:DI 1 "register_operand" "%0") 19339 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 19340 UNSPEC_NOP))] 19341 "TARGET_MMX" 19342 "paddq\t{%2, %0|%0, %2}" 19343 [(set_attr "type" "mmxadd") 19344 (set_attr "mode" "DI")]) 19345 19346(define_insn "ssaddv8qi3" 19347 [(set (match_operand:V8QI 0 "register_operand" "=y") 19348 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0") 19349 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] 19350 "TARGET_MMX" 19351 "paddsb\t{%2, %0|%0, %2}" 19352 [(set_attr "type" "mmxadd") 19353 (set_attr "mode" "DI")]) 19354 19355(define_insn "ssaddv4hi3" 19356 [(set (match_operand:V4HI 0 "register_operand" "=y") 19357 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0") 19358 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] 19359 "TARGET_MMX" 19360 "paddsw\t{%2, %0|%0, %2}" 19361 [(set_attr "type" "mmxadd") 19362 (set_attr "mode" "DI")]) 19363 19364(define_insn "usaddv8qi3" 19365 [(set (match_operand:V8QI 0 "register_operand" "=y") 19366 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0") 19367 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] 19368 "TARGET_MMX" 19369 "paddusb\t{%2, %0|%0, %2}" 19370 [(set_attr "type" "mmxadd") 19371 (set_attr "mode" "DI")]) 19372 19373(define_insn "usaddv4hi3" 19374 [(set (match_operand:V4HI 0 "register_operand" "=y") 19375 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0") 19376 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] 19377 "TARGET_MMX" 19378 "paddusw\t{%2, %0|%0, %2}" 19379 [(set_attr "type" "mmxadd") 19380 (set_attr "mode" "DI")]) 19381 19382(define_insn "subv8qi3" 19383 [(set (match_operand:V8QI 0 "register_operand" "=y") 19384 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0") 19385 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] 19386 "TARGET_MMX" 19387 "psubb\t{%2, %0|%0, %2}" 19388 [(set_attr "type" "mmxadd") 19389 (set_attr "mode" "DI")]) 19390 19391(define_insn "subv4hi3" 19392 [(set (match_operand:V4HI 0 "register_operand" "=y") 19393 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0") 19394 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] 19395 "TARGET_MMX" 19396 "psubw\t{%2, %0|%0, %2}" 19397 [(set_attr "type" "mmxadd") 19398 (set_attr "mode" "DI")]) 19399 19400(define_insn "subv2si3" 19401 [(set (match_operand:V2SI 0 "register_operand" "=y") 19402 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0") 19403 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))] 19404 "TARGET_MMX" 19405 "psubd\t{%2, %0|%0, %2}" 19406 [(set_attr "type" "mmxadd") 19407 (set_attr "mode" "DI")]) 19408 19409(define_insn "mmx_subdi3" 19410 [(set (match_operand:DI 0 "register_operand" "=y") 19411 (unspec:DI 19412 [(minus:DI (match_operand:DI 1 "register_operand" "0") 19413 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 19414 UNSPEC_NOP))] 19415 "TARGET_MMX" 19416 "psubq\t{%2, %0|%0, %2}" 19417 [(set_attr "type" "mmxadd") 19418 (set_attr "mode" "DI")]) 19419 19420(define_insn "sssubv8qi3" 19421 [(set (match_operand:V8QI 0 "register_operand" "=y") 19422 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0") 19423 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] 19424 "TARGET_MMX" 19425 "psubsb\t{%2, %0|%0, %2}" 19426 [(set_attr "type" "mmxadd") 19427 (set_attr "mode" "DI")]) 19428 19429(define_insn "sssubv4hi3" 19430 [(set (match_operand:V4HI 0 "register_operand" "=y") 19431 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0") 19432 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] 19433 "TARGET_MMX" 19434 "psubsw\t{%2, %0|%0, %2}" 19435 [(set_attr "type" "mmxadd") 19436 (set_attr "mode" "DI")]) 19437 19438(define_insn "ussubv8qi3" 19439 [(set (match_operand:V8QI 0 "register_operand" "=y") 19440 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0") 19441 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] 19442 "TARGET_MMX" 19443 "psubusb\t{%2, %0|%0, %2}" 19444 [(set_attr "type" "mmxadd") 19445 (set_attr "mode" "DI")]) 19446 19447(define_insn "ussubv4hi3" 19448 [(set (match_operand:V4HI 0 "register_operand" "=y") 19449 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0") 19450 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] 19451 "TARGET_MMX" 19452 "psubusw\t{%2, %0|%0, %2}" 19453 [(set_attr "type" "mmxadd") 19454 (set_attr "mode" "DI")]) 19455 19456(define_insn "mulv4hi3" 19457 [(set (match_operand:V4HI 0 "register_operand" "=y") 19458 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0") 19459 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] 19460 "TARGET_MMX" 19461 "pmullw\t{%2, %0|%0, %2}" 19462 [(set_attr "type" "mmxmul") 19463 (set_attr "mode" "DI")]) 19464 19465(define_insn "smulv4hi3_highpart" 19466 [(set (match_operand:V4HI 0 "register_operand" "=y") 19467 (truncate:V4HI 19468 (lshiftrt:V4SI 19469 (mult:V4SI (sign_extend:V4SI 19470 (match_operand:V4HI 1 "register_operand" "0")) 19471 (sign_extend:V4SI 19472 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) 19473 (const_int 16))))] 19474 "TARGET_MMX" 19475 "pmulhw\t{%2, %0|%0, %2}" 19476 [(set_attr "type" "mmxmul") 19477 (set_attr "mode" "DI")]) 19478 19479(define_insn "umulv4hi3_highpart" 19480 [(set (match_operand:V4HI 0 "register_operand" "=y") 19481 (truncate:V4HI 19482 (lshiftrt:V4SI 19483 (mult:V4SI (zero_extend:V4SI 19484 (match_operand:V4HI 1 "register_operand" "0")) 19485 (zero_extend:V4SI 19486 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) 19487 (const_int 16))))] 19488 "TARGET_SSE || TARGET_3DNOW_A" 19489 "pmulhuw\t{%2, %0|%0, %2}" 19490 [(set_attr "type" "mmxmul") 19491 (set_attr "mode" "DI")]) 19492 19493(define_insn "mmx_pmaddwd" 19494 [(set (match_operand:V2SI 0 "register_operand" "=y") 19495 (plus:V2SI 19496 (mult:V2SI 19497 (sign_extend:V2SI 19498 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0") 19499 (parallel [(const_int 0) (const_int 2)]))) 19500 (sign_extend:V2SI 19501 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym") 19502 (parallel [(const_int 0) (const_int 2)])))) 19503 (mult:V2SI 19504 (sign_extend:V2SI (vec_select:V2HI (match_dup 1) 19505 (parallel [(const_int 1) 19506 (const_int 3)]))) 19507 (sign_extend:V2SI (vec_select:V2HI (match_dup 2) 19508 (parallel [(const_int 1) 19509 (const_int 3)]))))))] 19510 "TARGET_MMX" 19511 "pmaddwd\t{%2, %0|%0, %2}" 19512 [(set_attr "type" "mmxmul") 19513 (set_attr "mode" "DI")]) 19514 19515 19516;; MMX logical operations 19517;; Note we don't want to declare these as regular iordi3 insns to prevent 19518;; normal code that also wants to use the FPU from getting broken. 19519;; The UNSPECs are there to prevent the combiner from getting overly clever. 19520(define_insn "mmx_iordi3" 19521 [(set (match_operand:DI 0 "register_operand" "=y") 19522 (unspec:DI 19523 [(ior:DI (match_operand:DI 1 "register_operand" "%0") 19524 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 19525 UNSPEC_NOP))] 19526 "TARGET_MMX" 19527 "por\t{%2, %0|%0, %2}" 19528 [(set_attr "type" "mmxadd") 19529 (set_attr "mode" "DI")]) 19530 19531(define_insn "mmx_xordi3" 19532 [(set (match_operand:DI 0 "register_operand" "=y") 19533 (unspec:DI 19534 [(xor:DI (match_operand:DI 1 "register_operand" "%0") 19535 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 19536 UNSPEC_NOP))] 19537 "TARGET_MMX" 19538 "pxor\t{%2, %0|%0, %2}" 19539 [(set_attr "type" "mmxadd") 19540 (set_attr "mode" "DI") 19541 (set_attr "memory" "none")]) 19542 19543;; Same as pxor, but don't show input operands so that we don't think 19544;; they are live. 19545(define_insn "mmx_clrdi" 19546 [(set (match_operand:DI 0 "register_operand" "=y") 19547 (unspec:DI [(const_int 0)] UNSPEC_NOP))] 19548 "TARGET_MMX" 19549 "pxor\t{%0, %0|%0, %0}" 19550 [(set_attr "type" "mmxadd") 19551 (set_attr "mode" "DI") 19552 (set_attr "memory" "none")]) 19553 19554(define_insn "mmx_anddi3" 19555 [(set (match_operand:DI 0 "register_operand" "=y") 19556 (unspec:DI 19557 [(and:DI (match_operand:DI 1 "register_operand" "%0") 19558 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 19559 UNSPEC_NOP))] 19560 "TARGET_MMX" 19561 "pand\t{%2, %0|%0, %2}" 19562 [(set_attr "type" "mmxadd") 19563 (set_attr "mode" "DI")]) 19564 19565(define_insn "mmx_nanddi3" 19566 [(set (match_operand:DI 0 "register_operand" "=y") 19567 (unspec:DI 19568 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0")) 19569 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 19570 UNSPEC_NOP))] 19571 "TARGET_MMX" 19572 "pandn\t{%2, %0|%0, %2}" 19573 [(set_attr "type" "mmxadd") 19574 (set_attr "mode" "DI")]) 19575 19576 19577;; MMX unsigned averages/sum of absolute differences 19578 19579(define_insn "mmx_uavgv8qi3" 19580 [(set (match_operand:V8QI 0 "register_operand" "=y") 19581 (ashiftrt:V8QI 19582 (plus:V8QI (plus:V8QI 19583 (match_operand:V8QI 1 "register_operand" "0") 19584 (match_operand:V8QI 2 "nonimmediate_operand" "ym")) 19585 (const_vector:V8QI [(const_int 1) 19586 (const_int 1) 19587 (const_int 1) 19588 (const_int 1) 19589 (const_int 1) 19590 (const_int 1) 19591 (const_int 1) 19592 (const_int 1)])) 19593 (const_int 1)))] 19594 "TARGET_SSE || TARGET_3DNOW_A" 19595 "pavgb\t{%2, %0|%0, %2}" 19596 [(set_attr "type" "mmxshft") 19597 (set_attr "mode" "DI")]) 19598 19599(define_insn "mmx_uavgv4hi3" 19600 [(set (match_operand:V4HI 0 "register_operand" "=y") 19601 (ashiftrt:V4HI 19602 (plus:V4HI (plus:V4HI 19603 (match_operand:V4HI 1 "register_operand" "0") 19604 (match_operand:V4HI 2 "nonimmediate_operand" "ym")) 19605 (const_vector:V4HI [(const_int 1) 19606 (const_int 1) 19607 (const_int 1) 19608 (const_int 1)])) 19609 (const_int 1)))] 19610 "TARGET_SSE || TARGET_3DNOW_A" 19611 "pavgw\t{%2, %0|%0, %2}" 19612 [(set_attr "type" "mmxshft") 19613 (set_attr "mode" "DI")]) 19614 19615(define_insn "mmx_psadbw" 19616 [(set (match_operand:DI 0 "register_operand" "=y") 19617 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0") 19618 (match_operand:V8QI 2 "nonimmediate_operand" "ym")] 19619 UNSPEC_PSADBW))] 19620 "TARGET_SSE || TARGET_3DNOW_A" 19621 "psadbw\t{%2, %0|%0, %2}" 19622 [(set_attr "type" "mmxshft") 19623 (set_attr "mode" "DI")]) 19624 19625 19626;; MMX insert/extract/shuffle 19627 19628(define_insn "mmx_pinsrw" 19629 [(set (match_operand:V4HI 0 "register_operand" "=y") 19630 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0") 19631 (vec_duplicate:V4HI 19632 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm"))) 19633 (match_operand:SI 3 "immediate_operand" "i")))] 19634 "TARGET_SSE || TARGET_3DNOW_A" 19635 "pinsrw\t{%3, %2, %0|%0, %2, %3}" 19636 [(set_attr "type" "mmxcvt") 19637 (set_attr "mode" "DI")]) 19638 19639(define_insn "mmx_pextrw" 19640 [(set (match_operand:SI 0 "register_operand" "=r") 19641 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") 19642 (parallel 19643 [(match_operand:SI 2 "immediate_operand" "i")]))))] 19644 "TARGET_SSE || TARGET_3DNOW_A" 19645 "pextrw\t{%2, %1, %0|%0, %1, %2}" 19646 [(set_attr "type" "mmxcvt") 19647 (set_attr "mode" "DI")]) 19648 19649(define_insn "mmx_pshufw" 19650 [(set (match_operand:V4HI 0 "register_operand" "=y") 19651 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0") 19652 (match_operand:SI 2 "immediate_operand" "i")] 19653 UNSPEC_SHUFFLE))] 19654 "TARGET_SSE || TARGET_3DNOW_A" 19655 "pshufw\t{%2, %1, %0|%0, %1, %2}" 19656 [(set_attr "type" "mmxcvt") 19657 (set_attr "mode" "DI")]) 19658 19659 19660;; MMX mask-generating comparisons 19661 19662(define_insn "eqv8qi3" 19663 [(set (match_operand:V8QI 0 "register_operand" "=y") 19664 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0") 19665 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] 19666 "TARGET_MMX" 19667 "pcmpeqb\t{%2, %0|%0, %2}" 19668 [(set_attr "type" "mmxcmp") 19669 (set_attr "mode" "DI")]) 19670 19671(define_insn "eqv4hi3" 19672 [(set (match_operand:V4HI 0 "register_operand" "=y") 19673 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0") 19674 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] 19675 "TARGET_MMX" 19676 "pcmpeqw\t{%2, %0|%0, %2}" 19677 [(set_attr "type" "mmxcmp") 19678 (set_attr "mode" "DI")]) 19679 19680(define_insn "eqv2si3" 19681 [(set (match_operand:V2SI 0 "register_operand" "=y") 19682 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0") 19683 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))] 19684 "TARGET_MMX" 19685 "pcmpeqd\t{%2, %0|%0, %2}" 19686 [(set_attr "type" "mmxcmp") 19687 (set_attr "mode" "DI")]) 19688 19689(define_insn "gtv8qi3" 19690 [(set (match_operand:V8QI 0 "register_operand" "=y") 19691 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0") 19692 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] 19693 "TARGET_MMX" 19694 "pcmpgtb\t{%2, %0|%0, %2}" 19695 [(set_attr "type" "mmxcmp") 19696 (set_attr "mode" "DI")]) 19697 19698(define_insn "gtv4hi3" 19699 [(set (match_operand:V4HI 0 "register_operand" "=y") 19700 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0") 19701 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] 19702 "TARGET_MMX" 19703 "pcmpgtw\t{%2, %0|%0, %2}" 19704 [(set_attr "type" "mmxcmp") 19705 (set_attr "mode" "DI")]) 19706 19707(define_insn "gtv2si3" 19708 [(set (match_operand:V2SI 0 "register_operand" "=y") 19709 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0") 19710 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))] 19711 "TARGET_MMX" 19712 "pcmpgtd\t{%2, %0|%0, %2}" 19713 [(set_attr "type" "mmxcmp") 19714 (set_attr "mode" "DI")]) 19715 19716 19717;; MMX max/min insns 19718 19719(define_insn "umaxv8qi3" 19720 [(set (match_operand:V8QI 0 "register_operand" "=y") 19721 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0") 19722 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] 19723 "TARGET_SSE || TARGET_3DNOW_A" 19724 "pmaxub\t{%2, %0|%0, %2}" 19725 [(set_attr "type" "mmxadd") 19726 (set_attr "mode" "DI")]) 19727 19728(define_insn "smaxv4hi3" 19729 [(set (match_operand:V4HI 0 "register_operand" "=y") 19730 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0") 19731 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] 19732 "TARGET_SSE || TARGET_3DNOW_A" 19733 "pmaxsw\t{%2, %0|%0, %2}" 19734 [(set_attr "type" "mmxadd") 19735 (set_attr "mode" "DI")]) 19736 19737(define_insn "uminv8qi3" 19738 [(set (match_operand:V8QI 0 "register_operand" "=y") 19739 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0") 19740 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] 19741 "TARGET_SSE || TARGET_3DNOW_A" 19742 "pminub\t{%2, %0|%0, %2}" 19743 [(set_attr "type" "mmxadd") 19744 (set_attr "mode" "DI")]) 19745 19746(define_insn "sminv4hi3" 19747 [(set (match_operand:V4HI 0 "register_operand" "=y") 19748 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0") 19749 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] 19750 "TARGET_SSE || TARGET_3DNOW_A" 19751 "pminsw\t{%2, %0|%0, %2}" 19752 [(set_attr "type" "mmxadd") 19753 (set_attr "mode" "DI")]) 19754 19755 19756;; MMX shifts 19757 19758(define_insn "ashrv4hi3" 19759 [(set (match_operand:V4HI 0 "register_operand" "=y") 19760 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0") 19761 (match_operand:DI 2 "nonmemory_operand" "yi")))] 19762 "TARGET_MMX" 19763 "psraw\t{%2, %0|%0, %2}" 19764 [(set_attr "type" "mmxshft") 19765 (set_attr "mode" "DI")]) 19766 19767(define_insn "ashrv2si3" 19768 [(set (match_operand:V2SI 0 "register_operand" "=y") 19769 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0") 19770 (match_operand:DI 2 "nonmemory_operand" "yi")))] 19771 "TARGET_MMX" 19772 "psrad\t{%2, %0|%0, %2}" 19773 [(set_attr "type" "mmxshft") 19774 (set_attr "mode" "DI")]) 19775 19776(define_insn "lshrv4hi3" 19777 [(set (match_operand:V4HI 0 "register_operand" "=y") 19778 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0") 19779 (match_operand:DI 2 "nonmemory_operand" "yi")))] 19780 "TARGET_MMX" 19781 "psrlw\t{%2, %0|%0, %2}" 19782 [(set_attr "type" "mmxshft") 19783 (set_attr "mode" "DI")]) 19784 19785(define_insn "lshrv2si3" 19786 [(set (match_operand:V2SI 0 "register_operand" "=y") 19787 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0") 19788 (match_operand:DI 2 "nonmemory_operand" "yi")))] 19789 "TARGET_MMX" 19790 "psrld\t{%2, %0|%0, %2}" 19791 [(set_attr "type" "mmxshft") 19792 (set_attr "mode" "DI")]) 19793 19794;; See logical MMX insns. 19795(define_insn "mmx_lshrdi3" 19796 [(set (match_operand:DI 0 "register_operand" "=y") 19797 (unspec:DI 19798 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0") 19799 (match_operand:DI 2 "nonmemory_operand" "yi"))] 19800 UNSPEC_NOP))] 19801 "TARGET_MMX" 19802 "psrlq\t{%2, %0|%0, %2}" 19803 [(set_attr "type" "mmxshft") 19804 (set_attr "mode" "DI")]) 19805 19806(define_insn "ashlv4hi3" 19807 [(set (match_operand:V4HI 0 "register_operand" "=y") 19808 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0") 19809 (match_operand:DI 2 "nonmemory_operand" "yi")))] 19810 "TARGET_MMX" 19811 "psllw\t{%2, %0|%0, %2}" 19812 [(set_attr "type" "mmxshft") 19813 (set_attr "mode" "DI")]) 19814 19815(define_insn "ashlv2si3" 19816 [(set (match_operand:V2SI 0 "register_operand" "=y") 19817 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0") 19818 (match_operand:DI 2 "nonmemory_operand" "yi")))] 19819 "TARGET_MMX" 19820 "pslld\t{%2, %0|%0, %2}" 19821 [(set_attr "type" "mmxshft") 19822 (set_attr "mode" "DI")]) 19823 19824;; See logical MMX insns. 19825(define_insn "mmx_ashldi3" 19826 [(set (match_operand:DI 0 "register_operand" "=y") 19827 (unspec:DI 19828 [(ashift:DI (match_operand:DI 1 "register_operand" "0") 19829 (match_operand:DI 2 "nonmemory_operand" "yi"))] 19830 UNSPEC_NOP))] 19831 "TARGET_MMX" 19832 "psllq\t{%2, %0|%0, %2}" 19833 [(set_attr "type" "mmxshft") 19834 (set_attr "mode" "DI")]) 19835 19836 19837;; MMX pack/unpack insns. 19838 19839(define_insn "mmx_packsswb" 19840 [(set (match_operand:V8QI 0 "register_operand" "=y") 19841 (vec_concat:V8QI 19842 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0")) 19843 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] 19844 "TARGET_MMX" 19845 "packsswb\t{%2, %0|%0, %2}" 19846 [(set_attr "type" "mmxshft") 19847 (set_attr "mode" "DI")]) 19848 19849(define_insn "mmx_packssdw" 19850 [(set (match_operand:V4HI 0 "register_operand" "=y") 19851 (vec_concat:V4HI 19852 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0")) 19853 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] 19854 "TARGET_MMX" 19855 "packssdw\t{%2, %0|%0, %2}" 19856 [(set_attr "type" "mmxshft") 19857 (set_attr "mode" "DI")]) 19858 19859(define_insn "mmx_packuswb" 19860 [(set (match_operand:V8QI 0 "register_operand" "=y") 19861 (vec_concat:V8QI 19862 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0")) 19863 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] 19864 "TARGET_MMX" 19865 "packuswb\t{%2, %0|%0, %2}" 19866 [(set_attr "type" "mmxshft") 19867 (set_attr "mode" "DI")]) 19868 19869(define_insn "mmx_punpckhbw" 19870 [(set (match_operand:V8QI 0 "register_operand" "=y") 19871 (vec_merge:V8QI 19872 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0") 19873 (parallel [(const_int 4) 19874 (const_int 0) 19875 (const_int 5) 19876 (const_int 1) 19877 (const_int 6) 19878 (const_int 2) 19879 (const_int 7) 19880 (const_int 3)])) 19881 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") 19882 (parallel [(const_int 0) 19883 (const_int 4) 19884 (const_int 1) 19885 (const_int 5) 19886 (const_int 2) 19887 (const_int 6) 19888 (const_int 3) 19889 (const_int 7)])) 19890 (const_int 85)))] 19891 "TARGET_MMX" 19892 "punpckhbw\t{%2, %0|%0, %2}" 19893 [(set_attr "type" "mmxcvt") 19894 (set_attr "mode" "DI")]) 19895 19896(define_insn "mmx_punpckhwd" 19897 [(set (match_operand:V4HI 0 "register_operand" "=y") 19898 (vec_merge:V4HI 19899 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0") 19900 (parallel [(const_int 0) 19901 (const_int 2) 19902 (const_int 1) 19903 (const_int 3)])) 19904 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") 19905 (parallel [(const_int 2) 19906 (const_int 0) 19907 (const_int 3) 19908 (const_int 1)])) 19909 (const_int 5)))] 19910 "TARGET_MMX" 19911 "punpckhwd\t{%2, %0|%0, %2}" 19912 [(set_attr "type" "mmxcvt") 19913 (set_attr "mode" "DI")]) 19914 19915(define_insn "mmx_punpckhdq" 19916 [(set (match_operand:V2SI 0 "register_operand" "=y") 19917 (vec_merge:V2SI 19918 (match_operand:V2SI 1 "register_operand" "0") 19919 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") 19920 (parallel [(const_int 1) 19921 (const_int 0)])) 19922 (const_int 1)))] 19923 "TARGET_MMX" 19924 "punpckhdq\t{%2, %0|%0, %2}" 19925 [(set_attr "type" "mmxcvt") 19926 (set_attr "mode" "DI")]) 19927 19928(define_insn "mmx_punpcklbw" 19929 [(set (match_operand:V8QI 0 "register_operand" "=y") 19930 (vec_merge:V8QI 19931 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0") 19932 (parallel [(const_int 0) 19933 (const_int 4) 19934 (const_int 1) 19935 (const_int 5) 19936 (const_int 2) 19937 (const_int 6) 19938 (const_int 3) 19939 (const_int 7)])) 19940 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") 19941 (parallel [(const_int 4) 19942 (const_int 0) 19943 (const_int 5) 19944 (const_int 1) 19945 (const_int 6) 19946 (const_int 2) 19947 (const_int 7) 19948 (const_int 3)])) 19949 (const_int 85)))] 19950 "TARGET_MMX" 19951 "punpcklbw\t{%2, %0|%0, %2}" 19952 [(set_attr "type" "mmxcvt") 19953 (set_attr "mode" "DI")]) 19954 19955(define_insn "mmx_punpcklwd" 19956 [(set (match_operand:V4HI 0 "register_operand" "=y") 19957 (vec_merge:V4HI 19958 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0") 19959 (parallel [(const_int 2) 19960 (const_int 0) 19961 (const_int 3) 19962 (const_int 1)])) 19963 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") 19964 (parallel [(const_int 0) 19965 (const_int 2) 19966 (const_int 1) 19967 (const_int 3)])) 19968 (const_int 5)))] 19969 "TARGET_MMX" 19970 "punpcklwd\t{%2, %0|%0, %2}" 19971 [(set_attr "type" "mmxcvt") 19972 (set_attr "mode" "DI")]) 19973 19974(define_insn "mmx_punpckldq" 19975 [(set (match_operand:V2SI 0 "register_operand" "=y") 19976 (vec_merge:V2SI 19977 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0") 19978 (parallel [(const_int 1) 19979 (const_int 0)])) 19980 (match_operand:V2SI 2 "register_operand" "y") 19981 (const_int 1)))] 19982 "TARGET_MMX" 19983 "punpckldq\t{%2, %0|%0, %2}" 19984 [(set_attr "type" "mmxcvt") 19985 (set_attr "mode" "DI")]) 19986 19987 19988;; Miscellaneous stuff 19989 19990(define_insn "emms" 19991 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS) 19992 (clobber (reg:XF 8)) 19993 (clobber (reg:XF 9)) 19994 (clobber (reg:XF 10)) 19995 (clobber (reg:XF 11)) 19996 (clobber (reg:XF 12)) 19997 (clobber (reg:XF 13)) 19998 (clobber (reg:XF 14)) 19999 (clobber (reg:XF 15)) 20000 (clobber (reg:DI 29)) 20001 (clobber (reg:DI 30)) 20002 (clobber (reg:DI 31)) 20003 (clobber (reg:DI 32)) 20004 (clobber (reg:DI 33)) 20005 (clobber (reg:DI 34)) 20006 (clobber (reg:DI 35)) 20007 (clobber (reg:DI 36))] 20008 "TARGET_MMX" 20009 "emms" 20010 [(set_attr "type" "mmx") 20011 (set_attr "memory" "unknown")]) 20012 20013(define_insn "ldmxcsr" 20014 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 20015 UNSPECV_LDMXCSR)] 20016 "TARGET_SSE" 20017 "ldmxcsr\t%0" 20018 [(set_attr "type" "sse") 20019 (set_attr "memory" "load")]) 20020 20021(define_insn "stmxcsr" 20022 [(set (match_operand:SI 0 "memory_operand" "=m") 20023 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))] 20024 "TARGET_SSE" 20025 "stmxcsr\t%0" 20026 [(set_attr "type" "sse") 20027 (set_attr "memory" "store")]) 20028 20029(define_expand "sfence" 20030 [(set (match_dup 0) 20031 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))] 20032 "TARGET_SSE || TARGET_3DNOW_A" 20033{ 20034 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 20035 MEM_VOLATILE_P (operands[0]) = 1; 20036}) 20037 20038(define_insn "*sfence_insn" 20039 [(set (match_operand:BLK 0 "" "") 20040 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))] 20041 "TARGET_SSE || TARGET_3DNOW_A" 20042 "sfence" 20043 [(set_attr "type" "sse") 20044 (set_attr "memory" "unknown")]) 20045 20046(define_expand "sse_prologue_save" 20047 [(parallel [(set (match_operand:BLK 0 "" "") 20048 (unspec:BLK [(reg:DI 21) 20049 (reg:DI 22) 20050 (reg:DI 23) 20051 (reg:DI 24) 20052 (reg:DI 25) 20053 (reg:DI 26) 20054 (reg:DI 27) 20055 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE)) 20056 (use (match_operand:DI 1 "register_operand" "")) 20057 (use (match_operand:DI 2 "immediate_operand" "")) 20058 (use (label_ref:DI (match_operand 3 "" "")))])] 20059 "TARGET_64BIT" 20060 "") 20061 20062(define_insn "*sse_prologue_save_insn" 20063 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R") 20064 (match_operand:DI 4 "const_int_operand" "n"))) 20065 (unspec:BLK [(reg:DI 21) 20066 (reg:DI 22) 20067 (reg:DI 23) 20068 (reg:DI 24) 20069 (reg:DI 25) 20070 (reg:DI 26) 20071 (reg:DI 27) 20072 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE)) 20073 (use (match_operand:DI 1 "register_operand" "r")) 20074 (use (match_operand:DI 2 "const_int_operand" "i")) 20075 (use (label_ref:DI (match_operand 3 "" "X")))] 20076 "TARGET_64BIT 20077 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128 20078 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128" 20079 "* 20080{ 20081 int i; 20082 operands[0] = gen_rtx_MEM (Pmode, 20083 gen_rtx_PLUS (Pmode, operands[0], operands[4])); 20084 output_asm_insn (\"jmp\\t%A1\", operands); 20085 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--) 20086 { 20087 operands[4] = adjust_address (operands[0], DImode, i*16); 20088 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i)); 20089 PUT_MODE (operands[4], TImode); 20090 if (GET_CODE (XEXP (operands[0], 0)) != PLUS) 20091 output_asm_insn (\"rex\", operands); 20092 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands); 20093 } 20094 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", 20095 CODE_LABEL_NUMBER (operands[3])); 20096 RET; 20097} 20098 " 20099 [(set_attr "type" "other") 20100 (set_attr "length_immediate" "0") 20101 (set_attr "length_address" "0") 20102 (set_attr "length" "135") 20103 (set_attr "memory" "store") 20104 (set_attr "modrm" "0") 20105 (set_attr "mode" "DI")]) 20106 20107;; 3Dnow! instructions 20108 20109(define_insn "addv2sf3" 20110 [(set (match_operand:V2SF 0 "register_operand" "=y") 20111 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0") 20112 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] 20113 "TARGET_3DNOW" 20114 "pfadd\\t{%2, %0|%0, %2}" 20115 [(set_attr "type" "mmxadd") 20116 (set_attr "mode" "V2SF")]) 20117 20118(define_insn "subv2sf3" 20119 [(set (match_operand:V2SF 0 "register_operand" "=y") 20120 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0") 20121 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] 20122 "TARGET_3DNOW" 20123 "pfsub\\t{%2, %0|%0, %2}" 20124 [(set_attr "type" "mmxadd") 20125 (set_attr "mode" "V2SF")]) 20126 20127(define_insn "subrv2sf3" 20128 [(set (match_operand:V2SF 0 "register_operand" "=y") 20129 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym") 20130 (match_operand:V2SF 1 "register_operand" "0")))] 20131 "TARGET_3DNOW" 20132 "pfsubr\\t{%2, %0|%0, %2}" 20133 [(set_attr "type" "mmxadd") 20134 (set_attr "mode" "V2SF")]) 20135 20136(define_insn "gtv2sf3" 20137 [(set (match_operand:V2SI 0 "register_operand" "=y") 20138 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0") 20139 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] 20140 "TARGET_3DNOW" 20141 "pfcmpgt\\t{%2, %0|%0, %2}" 20142 [(set_attr "type" "mmxcmp") 20143 (set_attr "mode" "V2SF")]) 20144 20145(define_insn "gev2sf3" 20146 [(set (match_operand:V2SI 0 "register_operand" "=y") 20147 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0") 20148 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] 20149 "TARGET_3DNOW" 20150 "pfcmpge\\t{%2, %0|%0, %2}" 20151 [(set_attr "type" "mmxcmp") 20152 (set_attr "mode" "V2SF")]) 20153 20154(define_insn "eqv2sf3" 20155 [(set (match_operand:V2SI 0 "register_operand" "=y") 20156 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0") 20157 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] 20158 "TARGET_3DNOW" 20159 "pfcmpeq\\t{%2, %0|%0, %2}" 20160 [(set_attr "type" "mmxcmp") 20161 (set_attr "mode" "V2SF")]) 20162 20163(define_insn "pfmaxv2sf3" 20164 [(set (match_operand:V2SF 0 "register_operand" "=y") 20165 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0") 20166 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] 20167 "TARGET_3DNOW" 20168 "pfmax\\t{%2, %0|%0, %2}" 20169 [(set_attr "type" "mmxadd") 20170 (set_attr "mode" "V2SF")]) 20171 20172(define_insn "pfminv2sf3" 20173 [(set (match_operand:V2SF 0 "register_operand" "=y") 20174 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0") 20175 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] 20176 "TARGET_3DNOW" 20177 "pfmin\\t{%2, %0|%0, %2}" 20178 [(set_attr "type" "mmxadd") 20179 (set_attr "mode" "V2SF")]) 20180 20181(define_insn "mulv2sf3" 20182 [(set (match_operand:V2SF 0 "register_operand" "=y") 20183 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0") 20184 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] 20185 "TARGET_3DNOW" 20186 "pfmul\\t{%2, %0|%0, %2}" 20187 [(set_attr "type" "mmxmul") 20188 (set_attr "mode" "V2SF")]) 20189 20190(define_insn "femms" 20191 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS) 20192 (clobber (reg:XF 8)) 20193 (clobber (reg:XF 9)) 20194 (clobber (reg:XF 10)) 20195 (clobber (reg:XF 11)) 20196 (clobber (reg:XF 12)) 20197 (clobber (reg:XF 13)) 20198 (clobber (reg:XF 14)) 20199 (clobber (reg:XF 15)) 20200 (clobber (reg:DI 29)) 20201 (clobber (reg:DI 30)) 20202 (clobber (reg:DI 31)) 20203 (clobber (reg:DI 32)) 20204 (clobber (reg:DI 33)) 20205 (clobber (reg:DI 34)) 20206 (clobber (reg:DI 35)) 20207 (clobber (reg:DI 36))] 20208 "TARGET_3DNOW" 20209 "femms" 20210 [(set_attr "type" "mmx") 20211 (set_attr "memory" "none")]) 20212 20213(define_insn "pf2id" 20214 [(set (match_operand:V2SI 0 "register_operand" "=y") 20215 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))] 20216 "TARGET_3DNOW" 20217 "pf2id\\t{%1, %0|%0, %1}" 20218 [(set_attr "type" "mmxcvt") 20219 (set_attr "mode" "V2SF")]) 20220 20221(define_insn "pf2iw" 20222 [(set (match_operand:V2SI 0 "register_operand" "=y") 20223 (sign_extend:V2SI 20224 (ss_truncate:V2HI 20225 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))] 20226 "TARGET_3DNOW_A" 20227 "pf2iw\\t{%1, %0|%0, %1}" 20228 [(set_attr "type" "mmxcvt") 20229 (set_attr "mode" "V2SF")]) 20230 20231(define_insn "pfacc" 20232 [(set (match_operand:V2SF 0 "register_operand" "=y") 20233 (vec_concat:V2SF 20234 (plus:SF 20235 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0") 20236 (parallel [(const_int 0)])) 20237 (vec_select:SF (match_dup 1) 20238 (parallel [(const_int 1)]))) 20239 (plus:SF 20240 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y") 20241 (parallel [(const_int 0)])) 20242 (vec_select:SF (match_dup 2) 20243 (parallel [(const_int 1)])))))] 20244 "TARGET_3DNOW" 20245 "pfacc\\t{%2, %0|%0, %2}" 20246 [(set_attr "type" "mmxadd") 20247 (set_attr "mode" "V2SF")]) 20248 20249(define_insn "pfnacc" 20250 [(set (match_operand:V2SF 0 "register_operand" "=y") 20251 (vec_concat:V2SF 20252 (minus:SF 20253 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0") 20254 (parallel [(const_int 0)])) 20255 (vec_select:SF (match_dup 1) 20256 (parallel [(const_int 1)]))) 20257 (minus:SF 20258 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y") 20259 (parallel [(const_int 0)])) 20260 (vec_select:SF (match_dup 2) 20261 (parallel [(const_int 1)])))))] 20262 "TARGET_3DNOW_A" 20263 "pfnacc\\t{%2, %0|%0, %2}" 20264 [(set_attr "type" "mmxadd") 20265 (set_attr "mode" "V2SF")]) 20266 20267(define_insn "pfpnacc" 20268 [(set (match_operand:V2SF 0 "register_operand" "=y") 20269 (vec_concat:V2SF 20270 (minus:SF 20271 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0") 20272 (parallel [(const_int 0)])) 20273 (vec_select:SF (match_dup 1) 20274 (parallel [(const_int 1)]))) 20275 (plus:SF 20276 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y") 20277 (parallel [(const_int 0)])) 20278 (vec_select:SF (match_dup 2) 20279 (parallel [(const_int 1)])))))] 20280 "TARGET_3DNOW_A" 20281 "pfpnacc\\t{%2, %0|%0, %2}" 20282 [(set_attr "type" "mmxadd") 20283 (set_attr "mode" "V2SF")]) 20284 20285(define_insn "pi2fw" 20286 [(set (match_operand:V2SF 0 "register_operand" "=y") 20287 (float:V2SF 20288 (vec_concat:V2SI 20289 (sign_extend:SI 20290 (truncate:HI 20291 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym") 20292 (parallel [(const_int 0)])))) 20293 (sign_extend:SI 20294 (truncate:HI 20295 (vec_select:SI (match_dup 1) 20296 (parallel [(const_int 1)])))))))] 20297 "TARGET_3DNOW_A" 20298 "pi2fw\\t{%1, %0|%0, %1}" 20299 [(set_attr "type" "mmxcvt") 20300 (set_attr "mode" "V2SF")]) 20301 20302(define_insn "floatv2si2" 20303 [(set (match_operand:V2SF 0 "register_operand" "=y") 20304 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))] 20305 "TARGET_3DNOW" 20306 "pi2fd\\t{%1, %0|%0, %1}" 20307 [(set_attr "type" "mmxcvt") 20308 (set_attr "mode" "V2SF")]) 20309 20310;; This insn is identical to pavgb in operation, but the opcode is 20311;; different. To avoid accidentally matching pavgb, use an unspec. 20312 20313(define_insn "pavgusb" 20314 [(set (match_operand:V8QI 0 "register_operand" "=y") 20315 (unspec:V8QI 20316 [(match_operand:V8QI 1 "register_operand" "0") 20317 (match_operand:V8QI 2 "nonimmediate_operand" "ym")] 20318 UNSPEC_PAVGUSB))] 20319 "TARGET_3DNOW" 20320 "pavgusb\\t{%2, %0|%0, %2}" 20321 [(set_attr "type" "mmxshft") 20322 (set_attr "mode" "TI")]) 20323 20324;; 3DNow reciprical and sqrt 20325 20326(define_insn "pfrcpv2sf2" 20327 [(set (match_operand:V2SF 0 "register_operand" "=y") 20328 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 20329 UNSPEC_PFRCP))] 20330 "TARGET_3DNOW" 20331 "pfrcp\\t{%1, %0|%0, %1}" 20332 [(set_attr "type" "mmx") 20333 (set_attr "mode" "TI")]) 20334 20335(define_insn "pfrcpit1v2sf3" 20336 [(set (match_operand:V2SF 0 "register_operand" "=y") 20337 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") 20338 (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 20339 UNSPEC_PFRCPIT1))] 20340 "TARGET_3DNOW" 20341 "pfrcpit1\\t{%2, %0|%0, %2}" 20342 [(set_attr "type" "mmx") 20343 (set_attr "mode" "TI")]) 20344 20345(define_insn "pfrcpit2v2sf3" 20346 [(set (match_operand:V2SF 0 "register_operand" "=y") 20347 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") 20348 (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 20349 UNSPEC_PFRCPIT2))] 20350 "TARGET_3DNOW" 20351 "pfrcpit2\\t{%2, %0|%0, %2}" 20352 [(set_attr "type" "mmx") 20353 (set_attr "mode" "TI")]) 20354 20355(define_insn "pfrsqrtv2sf2" 20356 [(set (match_operand:V2SF 0 "register_operand" "=y") 20357 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 20358 UNSPEC_PFRSQRT))] 20359 "TARGET_3DNOW" 20360 "pfrsqrt\\t{%1, %0|%0, %1}" 20361 [(set_attr "type" "mmx") 20362 (set_attr "mode" "TI")]) 20363 20364(define_insn "pfrsqit1v2sf3" 20365 [(set (match_operand:V2SF 0 "register_operand" "=y") 20366 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") 20367 (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 20368 UNSPEC_PFRSQIT1))] 20369 "TARGET_3DNOW" 20370 "pfrsqit1\\t{%2, %0|%0, %2}" 20371 [(set_attr "type" "mmx") 20372 (set_attr "mode" "TI")]) 20373 20374(define_insn "pmulhrwv4hi3" 20375 [(set (match_operand:V4HI 0 "register_operand" "=y") 20376 (truncate:V4HI 20377 (lshiftrt:V4SI 20378 (plus:V4SI 20379 (mult:V4SI 20380 (sign_extend:V4SI 20381 (match_operand:V4HI 1 "register_operand" "0")) 20382 (sign_extend:V4SI 20383 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) 20384 (const_vector:V4SI [(const_int 32768) 20385 (const_int 32768) 20386 (const_int 32768) 20387 (const_int 32768)])) 20388 (const_int 16))))] 20389 "TARGET_3DNOW" 20390 "pmulhrw\\t{%2, %0|%0, %2}" 20391 [(set_attr "type" "mmxmul") 20392 (set_attr "mode" "TI")]) 20393 20394(define_insn "pswapdv2si2" 20395 [(set (match_operand:V2SI 0 "register_operand" "=y") 20396 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym") 20397 (parallel [(const_int 1) (const_int 0)])))] 20398 "TARGET_3DNOW_A" 20399 "pswapd\\t{%1, %0|%0, %1}" 20400 [(set_attr "type" "mmxcvt") 20401 (set_attr "mode" "TI")]) 20402 20403(define_insn "pswapdv2sf2" 20404 [(set (match_operand:V2SF 0 "register_operand" "=y") 20405 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym") 20406 (parallel [(const_int 1) (const_int 0)])))] 20407 "TARGET_3DNOW_A" 20408 "pswapd\\t{%1, %0|%0, %1}" 20409 [(set_attr "type" "mmxcvt") 20410 (set_attr "mode" "TI")]) 20411 20412(define_expand "prefetch" 20413 [(prefetch (match_operand 0 "address_operand" "") 20414 (match_operand:SI 1 "const_int_operand" "") 20415 (match_operand:SI 2 "const_int_operand" ""))] 20416 "TARGET_PREFETCH_SSE || TARGET_3DNOW" 20417{ 20418 int rw = INTVAL (operands[1]); 20419 int locality = INTVAL (operands[2]); 20420 20421 if (rw != 0 && rw != 1) 20422 abort (); 20423 if (locality < 0 || locality > 3) 20424 abort (); 20425 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode) 20426 abort (); 20427 20428 /* Use 3dNOW prefetch in case we are asking for write prefetch not 20429 suported by SSE counterpart or the SSE prefetch is not available 20430 (K6 machines). Otherwise use SSE prefetch as it allows specifying 20431 of locality. */ 20432 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw)) 20433 operands[2] = GEN_INT (3); 20434 else 20435 operands[1] = const0_rtx; 20436}) 20437 20438(define_insn "*prefetch_sse" 20439 [(prefetch (match_operand:SI 0 "address_operand" "p") 20440 (const_int 0) 20441 (match_operand:SI 1 "const_int_operand" ""))] 20442 "TARGET_PREFETCH_SSE && !TARGET_64BIT" 20443{ 20444 static const char * const patterns[4] = { 20445 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0" 20446 }; 20447 20448 int locality = INTVAL (operands[1]); 20449 if (locality < 0 || locality > 3) 20450 abort (); 20451 20452 return patterns[locality]; 20453} 20454 [(set_attr "type" "sse") 20455 (set_attr "memory" "none")]) 20456 20457(define_insn "*prefetch_sse_rex" 20458 [(prefetch (match_operand:DI 0 "address_operand" "p") 20459 (const_int 0) 20460 (match_operand:SI 1 "const_int_operand" ""))] 20461 "TARGET_PREFETCH_SSE && TARGET_64BIT" 20462{ 20463 static const char * const patterns[4] = { 20464 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0" 20465 }; 20466 20467 int locality = INTVAL (operands[1]); 20468 if (locality < 0 || locality > 3) 20469 abort (); 20470 20471 return patterns[locality]; 20472} 20473 [(set_attr "type" "sse") 20474 (set_attr "memory" "none")]) 20475 20476(define_insn "*prefetch_3dnow" 20477 [(prefetch (match_operand:SI 0 "address_operand" "p") 20478 (match_operand:SI 1 "const_int_operand" "n") 20479 (const_int 3))] 20480 "TARGET_3DNOW && !TARGET_64BIT" 20481{ 20482 if (INTVAL (operands[1]) == 0) 20483 return "prefetch\t%a0"; 20484 else 20485 return "prefetchw\t%a0"; 20486} 20487 [(set_attr "type" "mmx") 20488 (set_attr "memory" "none")]) 20489 20490(define_insn "*prefetch_3dnow_rex" 20491 [(prefetch (match_operand:DI 0 "address_operand" "p") 20492 (match_operand:SI 1 "const_int_operand" "n") 20493 (const_int 3))] 20494 "TARGET_3DNOW && TARGET_64BIT" 20495{ 20496 if (INTVAL (operands[1]) == 0) 20497 return "prefetch\t%a0"; 20498 else 20499 return "prefetchw\t%a0"; 20500} 20501 [(set_attr "type" "mmx") 20502 (set_attr "memory" "none")]) 20503 20504;; SSE2 support 20505 20506(define_insn "addv2df3" 20507 [(set (match_operand:V2DF 0 "register_operand" "=x") 20508 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0") 20509 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] 20510 "TARGET_SSE2" 20511 "addpd\t{%2, %0|%0, %2}" 20512 [(set_attr "type" "sseadd") 20513 (set_attr "mode" "V2DF")]) 20514 20515(define_insn "vmaddv2df3" 20516 [(set (match_operand:V2DF 0 "register_operand" "=x") 20517 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0") 20518 (match_operand:V2DF 2 "nonimmediate_operand" "xm")) 20519 (match_dup 1) 20520 (const_int 1)))] 20521 "TARGET_SSE2" 20522 "addsd\t{%2, %0|%0, %2}" 20523 [(set_attr "type" "sseadd") 20524 (set_attr "mode" "DF")]) 20525 20526(define_insn "subv2df3" 20527 [(set (match_operand:V2DF 0 "register_operand" "=x") 20528 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0") 20529 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] 20530 "TARGET_SSE2" 20531 "subpd\t{%2, %0|%0, %2}" 20532 [(set_attr "type" "sseadd") 20533 (set_attr "mode" "V2DF")]) 20534 20535(define_insn "vmsubv2df3" 20536 [(set (match_operand:V2DF 0 "register_operand" "=x") 20537 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0") 20538 (match_operand:V2DF 2 "nonimmediate_operand" "xm")) 20539 (match_dup 1) 20540 (const_int 1)))] 20541 "TARGET_SSE2" 20542 "subsd\t{%2, %0|%0, %2}" 20543 [(set_attr "type" "sseadd") 20544 (set_attr "mode" "DF")]) 20545 20546(define_insn "mulv2df3" 20547 [(set (match_operand:V2DF 0 "register_operand" "=x") 20548 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0") 20549 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] 20550 "TARGET_SSE2" 20551 "mulpd\t{%2, %0|%0, %2}" 20552 [(set_attr "type" "ssemul") 20553 (set_attr "mode" "V2DF")]) 20554 20555(define_insn "vmmulv2df3" 20556 [(set (match_operand:V2DF 0 "register_operand" "=x") 20557 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0") 20558 (match_operand:V2DF 2 "nonimmediate_operand" "xm")) 20559 (match_dup 1) 20560 (const_int 1)))] 20561 "TARGET_SSE2" 20562 "mulsd\t{%2, %0|%0, %2}" 20563 [(set_attr "type" "ssemul") 20564 (set_attr "mode" "DF")]) 20565 20566(define_insn "divv2df3" 20567 [(set (match_operand:V2DF 0 "register_operand" "=x") 20568 (div:V2DF (match_operand:V2DF 1 "register_operand" "0") 20569 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] 20570 "TARGET_SSE2" 20571 "divpd\t{%2, %0|%0, %2}" 20572 [(set_attr "type" "ssediv") 20573 (set_attr "mode" "V2DF")]) 20574 20575(define_insn "vmdivv2df3" 20576 [(set (match_operand:V2DF 0 "register_operand" "=x") 20577 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0") 20578 (match_operand:V2DF 2 "nonimmediate_operand" "xm")) 20579 (match_dup 1) 20580 (const_int 1)))] 20581 "TARGET_SSE2" 20582 "divsd\t{%2, %0|%0, %2}" 20583 [(set_attr "type" "ssediv") 20584 (set_attr "mode" "DF")]) 20585 20586;; SSE min/max 20587 20588(define_insn "smaxv2df3" 20589 [(set (match_operand:V2DF 0 "register_operand" "=x") 20590 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0") 20591 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] 20592 "TARGET_SSE2" 20593 "maxpd\t{%2, %0|%0, %2}" 20594 [(set_attr "type" "sseadd") 20595 (set_attr "mode" "V2DF")]) 20596 20597(define_insn "vmsmaxv2df3" 20598 [(set (match_operand:V2DF 0 "register_operand" "=x") 20599 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0") 20600 (match_operand:V2DF 2 "nonimmediate_operand" "xm")) 20601 (match_dup 1) 20602 (const_int 1)))] 20603 "TARGET_SSE2" 20604 "maxsd\t{%2, %0|%0, %2}" 20605 [(set_attr "type" "sseadd") 20606 (set_attr "mode" "DF")]) 20607 20608(define_insn "sminv2df3" 20609 [(set (match_operand:V2DF 0 "register_operand" "=x") 20610 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0") 20611 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] 20612 "TARGET_SSE2" 20613 "minpd\t{%2, %0|%0, %2}" 20614 [(set_attr "type" "sseadd") 20615 (set_attr "mode" "V2DF")]) 20616 20617(define_insn "vmsminv2df3" 20618 [(set (match_operand:V2DF 0 "register_operand" "=x") 20619 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0") 20620 (match_operand:V2DF 2 "nonimmediate_operand" "xm")) 20621 (match_dup 1) 20622 (const_int 1)))] 20623 "TARGET_SSE2" 20624 "minsd\t{%2, %0|%0, %2}" 20625 [(set_attr "type" "sseadd") 20626 (set_attr "mode" "DF")]) 20627;; SSE2 square root. There doesn't appear to be an extension for the 20628;; reciprocal/rsqrt instructions if the Intel manual is to be believed. 20629 20630(define_insn "sqrtv2df2" 20631 [(set (match_operand:V2DF 0 "register_operand" "=x") 20632 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))] 20633 "TARGET_SSE2" 20634 "sqrtpd\t{%1, %0|%0, %1}" 20635 [(set_attr "type" "sse") 20636 (set_attr "mode" "V2DF")]) 20637 20638(define_insn "vmsqrtv2df2" 20639 [(set (match_operand:V2DF 0 "register_operand" "=x") 20640 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")) 20641 (match_operand:V2DF 2 "register_operand" "0") 20642 (const_int 1)))] 20643 "TARGET_SSE2" 20644 "sqrtsd\t{%1, %0|%0, %1}" 20645 [(set_attr "type" "sse") 20646 (set_attr "mode" "SF")]) 20647 20648;; SSE mask-generating compares 20649 20650(define_insn "maskcmpv2df3" 20651 [(set (match_operand:V2DI 0 "register_operand" "=x") 20652 (match_operator:V2DI 3 "sse_comparison_operator" 20653 [(match_operand:V2DF 1 "register_operand" "0") 20654 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))] 20655 "TARGET_SSE2" 20656 "cmp%D3pd\t{%2, %0|%0, %2}" 20657 [(set_attr "type" "ssecmp") 20658 (set_attr "mode" "V2DF")]) 20659 20660(define_insn "maskncmpv2df3" 20661 [(set (match_operand:V2DI 0 "register_operand" "=x") 20662 (not:V2DI 20663 (match_operator:V2DI 3 "sse_comparison_operator" 20664 [(match_operand:V2DF 1 "register_operand" "0") 20665 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))] 20666 "TARGET_SSE2" 20667{ 20668 if (GET_CODE (operands[3]) == UNORDERED) 20669 return "cmpordps\t{%2, %0|%0, %2}"; 20670 else 20671 return "cmpn%D3pd\t{%2, %0|%0, %2}"; 20672} 20673 [(set_attr "type" "ssecmp") 20674 (set_attr "mode" "V2DF")]) 20675 20676(define_insn "vmmaskcmpv2df3" 20677 [(set (match_operand:V2DI 0 "register_operand" "=x") 20678 (vec_merge:V2DI 20679 (match_operator:V2DI 3 "sse_comparison_operator" 20680 [(match_operand:V2DF 1 "register_operand" "0") 20681 (match_operand:V2DF 2 "nonimmediate_operand" "x")]) 20682 (subreg:V2DI (match_dup 1) 0) 20683 (const_int 1)))] 20684 "TARGET_SSE2" 20685 "cmp%D3sd\t{%2, %0|%0, %2}" 20686 [(set_attr "type" "ssecmp") 20687 (set_attr "mode" "DF")]) 20688 20689(define_insn "vmmaskncmpv2df3" 20690 [(set (match_operand:V2DI 0 "register_operand" "=x") 20691 (vec_merge:V2DI 20692 (not:V2DI 20693 (match_operator:V2DI 3 "sse_comparison_operator" 20694 [(match_operand:V2DF 1 "register_operand" "0") 20695 (match_operand:V2DF 2 "nonimmediate_operand" "x")])) 20696 (subreg:V2DI (match_dup 1) 0) 20697 (const_int 1)))] 20698 "TARGET_SSE2" 20699{ 20700 if (GET_CODE (operands[3]) == UNORDERED) 20701 return "cmpordsd\t{%2, %0|%0, %2}"; 20702 else 20703 return "cmpn%D3sd\t{%2, %0|%0, %2}"; 20704} 20705 [(set_attr "type" "ssecmp") 20706 (set_attr "mode" "DF")]) 20707 20708(define_insn "sse2_comi" 20709 [(set (reg:CCFP 17) 20710 (compare:CCFP (vec_select:DF 20711 (match_operand:V2DF 0 "register_operand" "x") 20712 (parallel [(const_int 0)])) 20713 (vec_select:DF 20714 (match_operand:V2DF 1 "register_operand" "x") 20715 (parallel [(const_int 0)]))))] 20716 "TARGET_SSE2" 20717 "comisd\t{%1, %0|%0, %1}" 20718 [(set_attr "type" "ssecmp") 20719 (set_attr "mode" "DF")]) 20720 20721(define_insn "sse2_ucomi" 20722 [(set (reg:CCFPU 17) 20723 (compare:CCFPU (vec_select:DF 20724 (match_operand:V2DF 0 "register_operand" "x") 20725 (parallel [(const_int 0)])) 20726 (vec_select:DF 20727 (match_operand:V2DF 1 "register_operand" "x") 20728 (parallel [(const_int 0)]))))] 20729 "TARGET_SSE2" 20730 "ucomisd\t{%1, %0|%0, %1}" 20731 [(set_attr "type" "ssecmp") 20732 (set_attr "mode" "DF")]) 20733 20734;; SSE Strange Moves. 20735 20736(define_insn "sse2_movmskpd" 20737 [(set (match_operand:SI 0 "register_operand" "=r") 20738 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")] 20739 UNSPEC_MOVMSK))] 20740 "TARGET_SSE2" 20741 "movmskpd\t{%1, %0|%0, %1}" 20742 [(set_attr "type" "ssecvt") 20743 (set_attr "mode" "V2DF")]) 20744 20745(define_insn "sse2_pmovmskb" 20746 [(set (match_operand:SI 0 "register_operand" "=r") 20747 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")] 20748 UNSPEC_MOVMSK))] 20749 "TARGET_SSE2" 20750 "pmovmskb\t{%1, %0|%0, %1}" 20751 [(set_attr "type" "ssecvt") 20752 (set_attr "mode" "V2DF")]) 20753 20754(define_insn "sse2_maskmovdqu" 20755 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D")) 20756 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x") 20757 (match_operand:V16QI 2 "register_operand" "x")] 20758 UNSPEC_MASKMOV))] 20759 "TARGET_SSE2" 20760 ;; @@@ check ordering of operands in intel/nonintel syntax 20761 "maskmovdqu\t{%2, %1|%1, %2}" 20762 [(set_attr "type" "ssecvt") 20763 (set_attr "mode" "TI")]) 20764 20765(define_insn "sse2_maskmovdqu_rex64" 20766 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D")) 20767 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x") 20768 (match_operand:V16QI 2 "register_operand" "x")] 20769 UNSPEC_MASKMOV))] 20770 "TARGET_SSE2" 20771 ;; @@@ check ordering of operands in intel/nonintel syntax 20772 "maskmovdqu\t{%2, %1|%1, %2}" 20773 [(set_attr "type" "ssecvt") 20774 (set_attr "mode" "TI")]) 20775 20776(define_insn "sse2_movntv2df" 20777 [(set (match_operand:V2DF 0 "memory_operand" "=m") 20778 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")] 20779 UNSPEC_MOVNT))] 20780 "TARGET_SSE2" 20781 "movntpd\t{%1, %0|%0, %1}" 20782 [(set_attr "type" "ssecvt") 20783 (set_attr "mode" "V2DF")]) 20784 20785(define_insn "sse2_movntv2di" 20786 [(set (match_operand:V2DI 0 "memory_operand" "=m") 20787 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")] 20788 UNSPEC_MOVNT))] 20789 "TARGET_SSE2" 20790 "movntdq\t{%1, %0|%0, %1}" 20791 [(set_attr "type" "ssecvt") 20792 (set_attr "mode" "TI")]) 20793 20794(define_insn "sse2_movntsi" 20795 [(set (match_operand:SI 0 "memory_operand" "=m") 20796 (unspec:SI [(match_operand:SI 1 "register_operand" "r")] 20797 UNSPEC_MOVNT))] 20798 "TARGET_SSE2" 20799 "movnti\t{%1, %0|%0, %1}" 20800 [(set_attr "type" "ssecvt") 20801 (set_attr "mode" "V2DF")]) 20802 20803;; SSE <-> integer/MMX conversions 20804 20805;; Conversions between SI and SF 20806 20807(define_insn "cvtdq2ps" 20808 [(set (match_operand:V4SF 0 "register_operand" "=x") 20809 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))] 20810 "TARGET_SSE2" 20811 "cvtdq2ps\t{%1, %0|%0, %1}" 20812 [(set_attr "type" "ssecvt") 20813 (set_attr "mode" "V2DF")]) 20814 20815(define_insn "cvtps2dq" 20816 [(set (match_operand:V4SI 0 "register_operand" "=x") 20817 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))] 20818 "TARGET_SSE2" 20819 "cvtps2dq\t{%1, %0|%0, %1}" 20820 [(set_attr "type" "ssecvt") 20821 (set_attr "mode" "TI")]) 20822 20823(define_insn "cvttps2dq" 20824 [(set (match_operand:V4SI 0 "register_operand" "=x") 20825 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 20826 UNSPEC_FIX))] 20827 "TARGET_SSE2" 20828 "cvttps2dq\t{%1, %0|%0, %1}" 20829 [(set_attr "type" "ssecvt") 20830 (set_attr "mode" "TI")]) 20831 20832;; Conversions between SI and DF 20833 20834(define_insn "cvtdq2pd" 20835 [(set (match_operand:V2DF 0 "register_operand" "=x") 20836 (float:V2DF (vec_select:V2SI 20837 (match_operand:V4SI 1 "nonimmediate_operand" "xm") 20838 (parallel 20839 [(const_int 0) 20840 (const_int 1)]))))] 20841 "TARGET_SSE2" 20842 "cvtdq2pd\t{%1, %0|%0, %1}" 20843 [(set_attr "type" "ssecvt") 20844 (set_attr "mode" "V2DF")]) 20845 20846(define_insn "cvtpd2dq" 20847 [(set (match_operand:V4SI 0 "register_operand" "=x") 20848 (vec_concat:V4SI 20849 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 20850 (const_vector:V2SI [(const_int 0) (const_int 0)])))] 20851 "TARGET_SSE2" 20852 "cvtpd2dq\t{%1, %0|%0, %1}" 20853 [(set_attr "type" "ssecvt") 20854 (set_attr "mode" "TI")]) 20855 20856(define_insn "cvttpd2dq" 20857 [(set (match_operand:V4SI 0 "register_operand" "=x") 20858 (vec_concat:V4SI 20859 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")] 20860 UNSPEC_FIX) 20861 (const_vector:V2SI [(const_int 0) (const_int 0)])))] 20862 "TARGET_SSE2" 20863 "cvttpd2dq\t{%1, %0|%0, %1}" 20864 [(set_attr "type" "ssecvt") 20865 (set_attr "mode" "TI")]) 20866 20867(define_insn "cvtpd2pi" 20868 [(set (match_operand:V2SI 0 "register_operand" "=y") 20869 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))] 20870 "TARGET_SSE2" 20871 "cvtpd2pi\t{%1, %0|%0, %1}" 20872 [(set_attr "type" "ssecvt") 20873 (set_attr "mode" "TI")]) 20874 20875(define_insn "cvttpd2pi" 20876 [(set (match_operand:V2SI 0 "register_operand" "=y") 20877 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")] 20878 UNSPEC_FIX))] 20879 "TARGET_SSE2" 20880 "cvttpd2pi\t{%1, %0|%0, %1}" 20881 [(set_attr "type" "ssecvt") 20882 (set_attr "mode" "TI")]) 20883 20884(define_insn "cvtpi2pd" 20885 [(set (match_operand:V2DF 0 "register_operand" "=x") 20886 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))] 20887 "TARGET_SSE2" 20888 "cvtpi2pd\t{%1, %0|%0, %1}" 20889 [(set_attr "type" "ssecvt") 20890 (set_attr "mode" "TI")]) 20891 20892;; Conversions between SI and DF 20893 20894(define_insn "cvtsd2si" 20895 [(set (match_operand:SI 0 "register_operand" "=r") 20896 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "xm") 20897 (parallel [(const_int 0)]))))] 20898 "TARGET_SSE2" 20899 "cvtsd2si\t{%1, %0|%0, %1}" 20900 [(set_attr "type" "ssecvt") 20901 (set_attr "mode" "SI")]) 20902 20903(define_insn "cvtsd2siq" 20904 [(set (match_operand:DI 0 "register_operand" "=r") 20905 (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "xm") 20906 (parallel [(const_int 0)]))))] 20907 "TARGET_SSE2 && TARGET_64BIT" 20908 "cvtsd2siq\t{%1, %0|%0, %1}" 20909 [(set_attr "type" "ssecvt") 20910 (set_attr "mode" "SI")]) 20911 20912(define_insn "cvttsd2si" 20913 [(set (match_operand:SI 0 "register_operand" "=r") 20914 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "xm") 20915 (parallel [(const_int 0)]))] UNSPEC_FIX))] 20916 "TARGET_SSE2" 20917 "cvttsd2si\t{%1, %0|%0, %1}" 20918 [(set_attr "type" "ssecvt") 20919 (set_attr "mode" "SI")]) 20920 20921(define_insn "cvttsd2siq" 20922 [(set (match_operand:DI 0 "register_operand" "=r,r") 20923 (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm") 20924 (parallel [(const_int 0)]))] UNSPEC_FIX))] 20925 "TARGET_SSE2 && TARGET_64BIT" 20926 "cvttsd2siq\t{%1, %0|%0, %1}" 20927 [(set_attr "type" "ssecvt") 20928 (set_attr "mode" "DI") 20929 (set_attr "athlon_decode" "vector,vector")]) 20930 20931(define_insn "cvtsi2sd" 20932 [(set (match_operand:V2DF 0 "register_operand" "=x") 20933 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0") 20934 (vec_duplicate:V2DF 20935 (float:DF 20936 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 20937 (const_int 2)))] 20938 "TARGET_SSE2" 20939 "cvtsi2sd\t{%2, %0|%0, %2}" 20940 [(set_attr "type" "ssecvt") 20941 (set_attr "mode" "DF")]) 20942 20943(define_insn "cvtsi2sdq" 20944 [(set (match_operand:V2DF 0 "register_operand" "=x,x") 20945 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0") 20946 (vec_duplicate:V2DF 20947 (float:DF 20948 (match_operand:DI 2 "nonimmediate_operand" "r,rm"))) 20949 (const_int 2)))] 20950 "TARGET_SSE2 && TARGET_64BIT" 20951 "cvtsi2sdq\t{%2, %0|%0, %2}" 20952 [(set_attr "type" "ssecvt") 20953 (set_attr "mode" "DF") 20954 (set_attr "athlon_decode" "vector,direct")]) 20955 20956;; Conversions between SF and DF 20957 20958(define_insn "cvtsd2ss" 20959 [(set (match_operand:V4SF 0 "register_operand" "=x") 20960 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0") 20961 (vec_duplicate:V4SF 20962 (float_truncate:V2SF 20963 (match_operand:V2DF 2 "register_operand" "xm"))) 20964 (const_int 14)))] 20965 "TARGET_SSE2" 20966 "cvtsd2ss\t{%2, %0|%0, %2}" 20967 [(set_attr "type" "ssecvt") 20968 (set_attr "mode" "SF")]) 20969 20970(define_insn "cvtss2sd" 20971 [(set (match_operand:V2DF 0 "register_operand" "=x") 20972 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0") 20973 (float_extend:V2DF 20974 (vec_select:V2SF 20975 (match_operand:V4SF 2 "register_operand" "xm") 20976 (parallel [(const_int 0) 20977 (const_int 1)]))) 20978 (const_int 2)))] 20979 "TARGET_SSE2" 20980 "cvtss2sd\t{%2, %0|%0, %2}" 20981 [(set_attr "type" "ssecvt") 20982 (set_attr "mode" "DF")]) 20983 20984(define_insn "cvtpd2ps" 20985 [(set (match_operand:V4SF 0 "register_operand" "=x") 20986 (subreg:V4SF 20987 (vec_concat:V4SI 20988 (subreg:V2SI (float_truncate:V2SF 20989 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0) 20990 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))] 20991 "TARGET_SSE2" 20992 "cvtpd2ps\t{%1, %0|%0, %1}" 20993 [(set_attr "type" "ssecvt") 20994 (set_attr "mode" "V4SF")]) 20995 20996(define_insn "cvtps2pd" 20997 [(set (match_operand:V2DF 0 "register_operand" "=x") 20998 (float_extend:V2DF 20999 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm") 21000 (parallel [(const_int 0) 21001 (const_int 1)]))))] 21002 "TARGET_SSE2" 21003 "cvtps2pd\t{%1, %0|%0, %1}" 21004 [(set_attr "type" "ssecvt") 21005 (set_attr "mode" "V2DF")]) 21006 21007;; SSE2 variants of MMX insns 21008 21009;; MMX arithmetic 21010 21011(define_insn "addv16qi3" 21012 [(set (match_operand:V16QI 0 "register_operand" "=x") 21013 (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0") 21014 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] 21015 "TARGET_SSE2" 21016 "paddb\t{%2, %0|%0, %2}" 21017 [(set_attr "type" "sseiadd") 21018 (set_attr "mode" "TI")]) 21019 21020(define_insn "addv8hi3" 21021 [(set (match_operand:V8HI 0 "register_operand" "=x") 21022 (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0") 21023 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] 21024 "TARGET_SSE2" 21025 "paddw\t{%2, %0|%0, %2}" 21026 [(set_attr "type" "sseiadd") 21027 (set_attr "mode" "TI")]) 21028 21029(define_insn "addv4si3" 21030 [(set (match_operand:V4SI 0 "register_operand" "=x") 21031 (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0") 21032 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))] 21033 "TARGET_SSE2" 21034 "paddd\t{%2, %0|%0, %2}" 21035 [(set_attr "type" "sseiadd") 21036 (set_attr "mode" "TI")]) 21037 21038(define_insn "addv2di3" 21039 [(set (match_operand:V2DI 0 "register_operand" "=x") 21040 (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0") 21041 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))] 21042 "TARGET_SSE2" 21043 "paddq\t{%2, %0|%0, %2}" 21044 [(set_attr "type" "sseiadd") 21045 (set_attr "mode" "TI")]) 21046 21047(define_insn "ssaddv16qi3" 21048 [(set (match_operand:V16QI 0 "register_operand" "=x") 21049 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0") 21050 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] 21051 "TARGET_SSE2" 21052 "paddsb\t{%2, %0|%0, %2}" 21053 [(set_attr "type" "sseiadd") 21054 (set_attr "mode" "TI")]) 21055 21056(define_insn "ssaddv8hi3" 21057 [(set (match_operand:V8HI 0 "register_operand" "=x") 21058 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0") 21059 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] 21060 "TARGET_SSE2" 21061 "paddsw\t{%2, %0|%0, %2}" 21062 [(set_attr "type" "sseiadd") 21063 (set_attr "mode" "TI")]) 21064 21065(define_insn "usaddv16qi3" 21066 [(set (match_operand:V16QI 0 "register_operand" "=x") 21067 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0") 21068 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] 21069 "TARGET_SSE2" 21070 "paddusb\t{%2, %0|%0, %2}" 21071 [(set_attr "type" "sseiadd") 21072 (set_attr "mode" "TI")]) 21073 21074(define_insn "usaddv8hi3" 21075 [(set (match_operand:V8HI 0 "register_operand" "=x") 21076 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0") 21077 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] 21078 "TARGET_SSE2" 21079 "paddusw\t{%2, %0|%0, %2}" 21080 [(set_attr "type" "sseiadd") 21081 (set_attr "mode" "TI")]) 21082 21083(define_insn "subv16qi3" 21084 [(set (match_operand:V16QI 0 "register_operand" "=x") 21085 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0") 21086 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] 21087 "TARGET_SSE2" 21088 "psubb\t{%2, %0|%0, %2}" 21089 [(set_attr "type" "sseiadd") 21090 (set_attr "mode" "TI")]) 21091 21092(define_insn "subv8hi3" 21093 [(set (match_operand:V8HI 0 "register_operand" "=x") 21094 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0") 21095 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] 21096 "TARGET_SSE2" 21097 "psubw\t{%2, %0|%0, %2}" 21098 [(set_attr "type" "sseiadd") 21099 (set_attr "mode" "TI")]) 21100 21101(define_insn "subv4si3" 21102 [(set (match_operand:V4SI 0 "register_operand" "=x") 21103 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0") 21104 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))] 21105 "TARGET_SSE2" 21106 "psubd\t{%2, %0|%0, %2}" 21107 [(set_attr "type" "sseiadd") 21108 (set_attr "mode" "TI")]) 21109 21110(define_insn "subv2di3" 21111 [(set (match_operand:V2DI 0 "register_operand" "=x") 21112 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0") 21113 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))] 21114 "TARGET_SSE2" 21115 "psubq\t{%2, %0|%0, %2}" 21116 [(set_attr "type" "sseiadd") 21117 (set_attr "mode" "TI")]) 21118 21119(define_insn "sssubv16qi3" 21120 [(set (match_operand:V16QI 0 "register_operand" "=x") 21121 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0") 21122 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] 21123 "TARGET_SSE2" 21124 "psubsb\t{%2, %0|%0, %2}" 21125 [(set_attr "type" "sseiadd") 21126 (set_attr "mode" "TI")]) 21127 21128(define_insn "sssubv8hi3" 21129 [(set (match_operand:V8HI 0 "register_operand" "=x") 21130 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0") 21131 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] 21132 "TARGET_SSE2" 21133 "psubsw\t{%2, %0|%0, %2}" 21134 [(set_attr "type" "sseiadd") 21135 (set_attr "mode" "TI")]) 21136 21137(define_insn "ussubv16qi3" 21138 [(set (match_operand:V16QI 0 "register_operand" "=x") 21139 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0") 21140 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] 21141 "TARGET_SSE2" 21142 "psubusb\t{%2, %0|%0, %2}" 21143 [(set_attr "type" "sseiadd") 21144 (set_attr "mode" "TI")]) 21145 21146(define_insn "ussubv8hi3" 21147 [(set (match_operand:V8HI 0 "register_operand" "=x") 21148 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0") 21149 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] 21150 "TARGET_SSE2" 21151 "psubusw\t{%2, %0|%0, %2}" 21152 [(set_attr "type" "sseiadd") 21153 (set_attr "mode" "TI")]) 21154 21155(define_insn "mulv8hi3" 21156 [(set (match_operand:V8HI 0 "register_operand" "=x") 21157 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0") 21158 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] 21159 "TARGET_SSE2" 21160 "pmullw\t{%2, %0|%0, %2}" 21161 [(set_attr "type" "sseimul") 21162 (set_attr "mode" "TI")]) 21163 21164(define_insn "smulv8hi3_highpart" 21165 [(set (match_operand:V8HI 0 "register_operand" "=x") 21166 (truncate:V8HI 21167 (lshiftrt:V8SI 21168 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0")) 21169 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm"))) 21170 (const_int 16))))] 21171 "TARGET_SSE2" 21172 "pmulhw\t{%2, %0|%0, %2}" 21173 [(set_attr "type" "sseimul") 21174 (set_attr "mode" "TI")]) 21175 21176(define_insn "umulv8hi3_highpart" 21177 [(set (match_operand:V8HI 0 "register_operand" "=x") 21178 (truncate:V8HI 21179 (lshiftrt:V8SI 21180 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0")) 21181 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm"))) 21182 (const_int 16))))] 21183 "TARGET_SSE2" 21184 "pmulhuw\t{%2, %0|%0, %2}" 21185 [(set_attr "type" "sseimul") 21186 (set_attr "mode" "TI")]) 21187 21188(define_insn "sse2_umulsidi3" 21189 [(set (match_operand:DI 0 "register_operand" "=y") 21190 (mult:DI (zero_extend:DI (vec_select:SI 21191 (match_operand:V2SI 1 "register_operand" "0") 21192 (parallel [(const_int 0)]))) 21193 (zero_extend:DI (vec_select:SI 21194 (match_operand:V2SI 2 "nonimmediate_operand" "ym") 21195 (parallel [(const_int 0)])))))] 21196 "TARGET_SSE2" 21197 "pmuludq\t{%2, %0|%0, %2}" 21198 [(set_attr "type" "sseimul") 21199 (set_attr "mode" "TI")]) 21200 21201(define_insn "sse2_umulv2siv2di3" 21202 [(set (match_operand:V2DI 0 "register_operand" "=x") 21203 (mult:V2DI (zero_extend:V2DI 21204 (vec_select:V2SI 21205 (match_operand:V4SI 1 "register_operand" "0") 21206 (parallel [(const_int 0) (const_int 2)]))) 21207 (zero_extend:V2DI 21208 (vec_select:V2SI 21209 (match_operand:V4SI 2 "nonimmediate_operand" "xm") 21210 (parallel [(const_int 0) (const_int 2)])))))] 21211 "TARGET_SSE2" 21212 "pmuludq\t{%2, %0|%0, %2}" 21213 [(set_attr "type" "sseimul") 21214 (set_attr "mode" "TI")]) 21215 21216(define_insn "sse2_pmaddwd" 21217 [(set (match_operand:V4SI 0 "register_operand" "=x") 21218 (plus:V4SI 21219 (mult:V4SI 21220 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0") 21221 (parallel [(const_int 0) 21222 (const_int 2) 21223 (const_int 4) 21224 (const_int 6)]))) 21225 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm") 21226 (parallel [(const_int 0) 21227 (const_int 2) 21228 (const_int 4) 21229 (const_int 6)])))) 21230 (mult:V4SI 21231 (sign_extend:V4SI (vec_select:V4HI (match_dup 1) 21232 (parallel [(const_int 1) 21233 (const_int 3) 21234 (const_int 5) 21235 (const_int 7)]))) 21236 (sign_extend:V4SI (vec_select:V4HI (match_dup 2) 21237 (parallel [(const_int 1) 21238 (const_int 3) 21239 (const_int 5) 21240 (const_int 7)]))))))] 21241 "TARGET_SSE2" 21242 "pmaddwd\t{%2, %0|%0, %2}" 21243 [(set_attr "type" "sseiadd") 21244 (set_attr "mode" "TI")]) 21245 21246;; Same as pxor, but don't show input operands so that we don't think 21247;; they are live. 21248(define_insn "sse2_clrti" 21249 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))] 21250 "TARGET_SSE2" 21251 "pxor\t{%0, %0|%0, %0}" 21252 [(set_attr "type" "sseiadd") 21253 (set_attr "memory" "none") 21254 (set_attr "mode" "TI")]) 21255 21256;; MMX unsigned averages/sum of absolute differences 21257 21258(define_insn "sse2_uavgv16qi3" 21259 [(set (match_operand:V16QI 0 "register_operand" "=x") 21260 (ashiftrt:V16QI 21261 (plus:V16QI (plus:V16QI 21262 (match_operand:V16QI 1 "register_operand" "0") 21263 (match_operand:V16QI 2 "nonimmediate_operand" "xm")) 21264 (const_vector:V16QI [(const_int 1) (const_int 1) 21265 (const_int 1) (const_int 1) 21266 (const_int 1) (const_int 1) 21267 (const_int 1) (const_int 1) 21268 (const_int 1) (const_int 1) 21269 (const_int 1) (const_int 1) 21270 (const_int 1) (const_int 1) 21271 (const_int 1) (const_int 1)])) 21272 (const_int 1)))] 21273 "TARGET_SSE2" 21274 "pavgb\t{%2, %0|%0, %2}" 21275 [(set_attr "type" "sseiadd") 21276 (set_attr "mode" "TI")]) 21277 21278(define_insn "sse2_uavgv8hi3" 21279 [(set (match_operand:V8HI 0 "register_operand" "=x") 21280 (ashiftrt:V8HI 21281 (plus:V8HI (plus:V8HI 21282 (match_operand:V8HI 1 "register_operand" "0") 21283 (match_operand:V8HI 2 "nonimmediate_operand" "xm")) 21284 (const_vector:V8HI [(const_int 1) (const_int 1) 21285 (const_int 1) (const_int 1) 21286 (const_int 1) (const_int 1) 21287 (const_int 1) (const_int 1)])) 21288 (const_int 1)))] 21289 "TARGET_SSE2" 21290 "pavgw\t{%2, %0|%0, %2}" 21291 [(set_attr "type" "sseiadd") 21292 (set_attr "mode" "TI")]) 21293 21294;; @@@ this isn't the right representation. 21295(define_insn "sse2_psadbw" 21296 [(set (match_operand:V2DI 0 "register_operand" "=x") 21297 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0") 21298 (match_operand:V16QI 2 "nonimmediate_operand" "xm")] 21299 UNSPEC_PSADBW))] 21300 "TARGET_SSE2" 21301 "psadbw\t{%2, %0|%0, %2}" 21302 [(set_attr "type" "sseiadd") 21303 (set_attr "mode" "TI")]) 21304 21305 21306;; MMX insert/extract/shuffle 21307 21308(define_insn "sse2_pinsrw" 21309 [(set (match_operand:V8HI 0 "register_operand" "=x") 21310 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0") 21311 (vec_duplicate:V8HI 21312 (truncate:HI 21313 (match_operand:SI 2 "nonimmediate_operand" "rm"))) 21314 (match_operand:SI 3 "immediate_operand" "i")))] 21315 "TARGET_SSE2" 21316 "pinsrw\t{%3, %2, %0|%0, %2, %3}" 21317 [(set_attr "type" "ssecvt") 21318 (set_attr "mode" "TI")]) 21319 21320(define_insn "sse2_pextrw" 21321 [(set (match_operand:SI 0 "register_operand" "=r") 21322 (zero_extend:SI 21323 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x") 21324 (parallel 21325 [(match_operand:SI 2 "immediate_operand" "i")]))))] 21326 "TARGET_SSE2" 21327 "pextrw\t{%2, %1, %0|%0, %1, %2}" 21328 [(set_attr "type" "ssecvt") 21329 (set_attr "mode" "TI")]) 21330 21331(define_insn "sse2_pshufd" 21332 [(set (match_operand:V4SI 0 "register_operand" "=x") 21333 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") 21334 (match_operand:SI 2 "immediate_operand" "i")] 21335 UNSPEC_SHUFFLE))] 21336 "TARGET_SSE2" 21337 "pshufd\t{%2, %1, %0|%0, %1, %2}" 21338 [(set_attr "type" "ssecvt") 21339 (set_attr "mode" "TI")]) 21340 21341(define_insn "sse2_pshuflw" 21342 [(set (match_operand:V8HI 0 "register_operand" "=x") 21343 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0") 21344 (match_operand:SI 2 "immediate_operand" "i")] 21345 UNSPEC_PSHUFLW))] 21346 "TARGET_SSE2" 21347 "pshuflw\t{%2, %1, %0|%0, %1, %2}" 21348 [(set_attr "type" "ssecvt") 21349 (set_attr "mode" "TI")]) 21350 21351(define_insn "sse2_pshufhw" 21352 [(set (match_operand:V8HI 0 "register_operand" "=x") 21353 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0") 21354 (match_operand:SI 2 "immediate_operand" "i")] 21355 UNSPEC_PSHUFHW))] 21356 "TARGET_SSE2" 21357 "pshufhw\t{%2, %1, %0|%0, %1, %2}" 21358 [(set_attr "type" "ssecvt") 21359 (set_attr "mode" "TI")]) 21360 21361;; MMX mask-generating comparisons 21362 21363(define_insn "eqv16qi3" 21364 [(set (match_operand:V16QI 0 "register_operand" "=x") 21365 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0") 21366 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] 21367 "TARGET_SSE2" 21368 "pcmpeqb\t{%2, %0|%0, %2}" 21369 [(set_attr "type" "ssecmp") 21370 (set_attr "mode" "TI")]) 21371 21372(define_insn "eqv8hi3" 21373 [(set (match_operand:V8HI 0 "register_operand" "=x") 21374 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0") 21375 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] 21376 "TARGET_SSE2" 21377 "pcmpeqw\t{%2, %0|%0, %2}" 21378 [(set_attr "type" "ssecmp") 21379 (set_attr "mode" "TI")]) 21380 21381(define_insn "eqv4si3" 21382 [(set (match_operand:V4SI 0 "register_operand" "=x") 21383 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0") 21384 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))] 21385 "TARGET_SSE2" 21386 "pcmpeqd\t{%2, %0|%0, %2}" 21387 [(set_attr "type" "ssecmp") 21388 (set_attr "mode" "TI")]) 21389 21390(define_insn "gtv16qi3" 21391 [(set (match_operand:V16QI 0 "register_operand" "=x") 21392 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0") 21393 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] 21394 "TARGET_SSE2" 21395 "pcmpgtb\t{%2, %0|%0, %2}" 21396 [(set_attr "type" "ssecmp") 21397 (set_attr "mode" "TI")]) 21398 21399(define_insn "gtv8hi3" 21400 [(set (match_operand:V8HI 0 "register_operand" "=x") 21401 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0") 21402 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] 21403 "TARGET_SSE2" 21404 "pcmpgtw\t{%2, %0|%0, %2}" 21405 [(set_attr "type" "ssecmp") 21406 (set_attr "mode" "TI")]) 21407 21408(define_insn "gtv4si3" 21409 [(set (match_operand:V4SI 0 "register_operand" "=x") 21410 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0") 21411 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))] 21412 "TARGET_SSE2" 21413 "pcmpgtd\t{%2, %0|%0, %2}" 21414 [(set_attr "type" "ssecmp") 21415 (set_attr "mode" "TI")]) 21416 21417 21418;; MMX max/min insns 21419 21420(define_insn "umaxv16qi3" 21421 [(set (match_operand:V16QI 0 "register_operand" "=x") 21422 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0") 21423 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] 21424 "TARGET_SSE2" 21425 "pmaxub\t{%2, %0|%0, %2}" 21426 [(set_attr "type" "sseiadd") 21427 (set_attr "mode" "TI")]) 21428 21429(define_insn "smaxv8hi3" 21430 [(set (match_operand:V8HI 0 "register_operand" "=x") 21431 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0") 21432 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] 21433 "TARGET_SSE2" 21434 "pmaxsw\t{%2, %0|%0, %2}" 21435 [(set_attr "type" "sseiadd") 21436 (set_attr "mode" "TI")]) 21437 21438(define_insn "uminv16qi3" 21439 [(set (match_operand:V16QI 0 "register_operand" "=x") 21440 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0") 21441 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] 21442 "TARGET_SSE2" 21443 "pminub\t{%2, %0|%0, %2}" 21444 [(set_attr "type" "sseiadd") 21445 (set_attr "mode" "TI")]) 21446 21447(define_insn "sminv8hi3" 21448 [(set (match_operand:V8HI 0 "register_operand" "=x") 21449 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0") 21450 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] 21451 "TARGET_SSE2" 21452 "pminsw\t{%2, %0|%0, %2}" 21453 [(set_attr "type" "sseiadd") 21454 (set_attr "mode" "TI")]) 21455 21456 21457;; MMX shifts 21458 21459(define_insn "ashrv8hi3" 21460 [(set (match_operand:V8HI 0 "register_operand" "=x") 21461 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0") 21462 (match_operand:TI 2 "nonmemory_operand" "xi")))] 21463 "TARGET_SSE2" 21464 "psraw\t{%2, %0|%0, %2}" 21465 [(set_attr "type" "sseishft") 21466 (set_attr "mode" "TI")]) 21467 21468(define_insn "ashrv4si3" 21469 [(set (match_operand:V4SI 0 "register_operand" "=x") 21470 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0") 21471 (match_operand:TI 2 "nonmemory_operand" "xi")))] 21472 "TARGET_SSE2" 21473 "psrad\t{%2, %0|%0, %2}" 21474 [(set_attr "type" "sseishft") 21475 (set_attr "mode" "TI")]) 21476 21477(define_insn "lshrv8hi3" 21478 [(set (match_operand:V8HI 0 "register_operand" "=x") 21479 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0") 21480 (match_operand:TI 2 "nonmemory_operand" "xi")))] 21481 "TARGET_SSE2" 21482 "psrlw\t{%2, %0|%0, %2}" 21483 [(set_attr "type" "sseishft") 21484 (set_attr "mode" "TI")]) 21485 21486(define_insn "lshrv4si3" 21487 [(set (match_operand:V4SI 0 "register_operand" "=x") 21488 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0") 21489 (match_operand:TI 2 "nonmemory_operand" "xi")))] 21490 "TARGET_SSE2" 21491 "psrld\t{%2, %0|%0, %2}" 21492 [(set_attr "type" "sseishft") 21493 (set_attr "mode" "TI")]) 21494 21495(define_insn "lshrv2di3" 21496 [(set (match_operand:V2DI 0 "register_operand" "=x") 21497 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0") 21498 (match_operand:TI 2 "nonmemory_operand" "xi")))] 21499 "TARGET_SSE2" 21500 "psrlq\t{%2, %0|%0, %2}" 21501 [(set_attr "type" "sseishft") 21502 (set_attr "mode" "TI")]) 21503 21504(define_insn "ashlv8hi3" 21505 [(set (match_operand:V8HI 0 "register_operand" "=x") 21506 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0") 21507 (match_operand:TI 2 "nonmemory_operand" "xi")))] 21508 "TARGET_SSE2" 21509 "psllw\t{%2, %0|%0, %2}" 21510 [(set_attr "type" "sseishft") 21511 (set_attr "mode" "TI")]) 21512 21513(define_insn "ashlv4si3" 21514 [(set (match_operand:V4SI 0 "register_operand" "=x") 21515 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0") 21516 (match_operand:TI 2 "nonmemory_operand" "xi")))] 21517 "TARGET_SSE2" 21518 "pslld\t{%2, %0|%0, %2}" 21519 [(set_attr "type" "sseishft") 21520 (set_attr "mode" "TI")]) 21521 21522(define_insn "ashlv2di3" 21523 [(set (match_operand:V2DI 0 "register_operand" "=x") 21524 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0") 21525 (match_operand:TI 2 "nonmemory_operand" "xi")))] 21526 "TARGET_SSE2" 21527 "psllq\t{%2, %0|%0, %2}" 21528 [(set_attr "type" "sseishft") 21529 (set_attr "mode" "TI")]) 21530 21531(define_insn "ashrv8hi3_ti" 21532 [(set (match_operand:V8HI 0 "register_operand" "=x") 21533 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0") 21534 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] 21535 "TARGET_SSE2" 21536 "psraw\t{%2, %0|%0, %2}" 21537 [(set_attr "type" "sseishft") 21538 (set_attr "mode" "TI")]) 21539 21540(define_insn "ashrv4si3_ti" 21541 [(set (match_operand:V4SI 0 "register_operand" "=x") 21542 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0") 21543 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] 21544 "TARGET_SSE2" 21545 "psrad\t{%2, %0|%0, %2}" 21546 [(set_attr "type" "sseishft") 21547 (set_attr "mode" "TI")]) 21548 21549(define_insn "lshrv8hi3_ti" 21550 [(set (match_operand:V8HI 0 "register_operand" "=x") 21551 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0") 21552 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] 21553 "TARGET_SSE2" 21554 "psrlw\t{%2, %0|%0, %2}" 21555 [(set_attr "type" "sseishft") 21556 (set_attr "mode" "TI")]) 21557 21558(define_insn "lshrv4si3_ti" 21559 [(set (match_operand:V4SI 0 "register_operand" "=x") 21560 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0") 21561 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] 21562 "TARGET_SSE2" 21563 "psrld\t{%2, %0|%0, %2}" 21564 [(set_attr "type" "sseishft") 21565 (set_attr "mode" "TI")]) 21566 21567(define_insn "lshrv2di3_ti" 21568 [(set (match_operand:V2DI 0 "register_operand" "=x") 21569 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0") 21570 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] 21571 "TARGET_SSE2" 21572 "psrlq\t{%2, %0|%0, %2}" 21573 [(set_attr "type" "sseishft") 21574 (set_attr "mode" "TI")]) 21575 21576(define_insn "ashlv8hi3_ti" 21577 [(set (match_operand:V8HI 0 "register_operand" "=x") 21578 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0") 21579 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] 21580 "TARGET_SSE2" 21581 "psllw\t{%2, %0|%0, %2}" 21582 [(set_attr "type" "sseishft") 21583 (set_attr "mode" "TI")]) 21584 21585(define_insn "ashlv4si3_ti" 21586 [(set (match_operand:V4SI 0 "register_operand" "=x") 21587 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0") 21588 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] 21589 "TARGET_SSE2" 21590 "pslld\t{%2, %0|%0, %2}" 21591 [(set_attr "type" "sseishft") 21592 (set_attr "mode" "TI")]) 21593 21594(define_insn "ashlv2di3_ti" 21595 [(set (match_operand:V2DI 0 "register_operand" "=x") 21596 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0") 21597 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] 21598 "TARGET_SSE2" 21599 "psllq\t{%2, %0|%0, %2}" 21600 [(set_attr "type" "sseishft") 21601 (set_attr "mode" "TI")]) 21602 21603;; See logical MMX insns for the reason for the unspec. Strictly speaking 21604;; we wouldn't need here it since we never generate TImode arithmetic. 21605 21606;; There has to be some kind of prize for the weirdest new instruction... 21607(define_insn "sse2_ashlti3" 21608 [(set (match_operand:TI 0 "register_operand" "=x") 21609 (unspec:TI 21610 [(ashift:TI (match_operand:TI 1 "register_operand" "0") 21611 (mult:SI (match_operand:SI 2 "immediate_operand" "i") 21612 (const_int 8)))] UNSPEC_NOP))] 21613 "TARGET_SSE2" 21614 "pslldq\t{%2, %0|%0, %2}" 21615 [(set_attr "type" "sseishft") 21616 (set_attr "mode" "TI")]) 21617 21618(define_insn "sse2_lshrti3" 21619 [(set (match_operand:TI 0 "register_operand" "=x") 21620 (unspec:TI 21621 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0") 21622 (mult:SI (match_operand:SI 2 "immediate_operand" "i") 21623 (const_int 8)))] UNSPEC_NOP))] 21624 "TARGET_SSE2" 21625 "psrldq\t{%2, %0|%0, %2}" 21626 [(set_attr "type" "sseishft") 21627 (set_attr "mode" "TI")]) 21628 21629;; SSE unpack 21630 21631(define_insn "sse2_unpckhpd" 21632 [(set (match_operand:V2DF 0 "register_operand" "=x") 21633 (vec_concat:V2DF 21634 (vec_select:V2DF (match_operand:V2DF 1 "register_operand" "0") 21635 (parallel [(const_int 1)])) 21636 (vec_select:V2DF (match_operand:V2DF 2 "register_operand" "x") 21637 (parallel [(const_int 0)]))))] 21638 "TARGET_SSE2" 21639 "unpckhpd\t{%2, %0|%0, %2}" 21640 [(set_attr "type" "ssecvt") 21641 (set_attr "mode" "TI")]) 21642 21643(define_insn "sse2_unpcklpd" 21644 [(set (match_operand:V2DF 0 "register_operand" "=x") 21645 (vec_concat:V2DF 21646 (vec_select:V2DF (match_operand:V2DF 1 "register_operand" "0") 21647 (parallel [(const_int 0)])) 21648 (vec_select:V2DF (match_operand:V2DF 2 "register_operand" "x") 21649 (parallel [(const_int 1)]))))] 21650 "TARGET_SSE2" 21651 "unpcklpd\t{%2, %0|%0, %2}" 21652 [(set_attr "type" "ssecvt") 21653 (set_attr "mode" "TI")]) 21654 21655;; MMX pack/unpack insns. 21656 21657(define_insn "sse2_packsswb" 21658 [(set (match_operand:V16QI 0 "register_operand" "=x") 21659 (vec_concat:V16QI 21660 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0")) 21661 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))] 21662 "TARGET_SSE2" 21663 "packsswb\t{%2, %0|%0, %2}" 21664 [(set_attr "type" "ssecvt") 21665 (set_attr "mode" "TI")]) 21666 21667(define_insn "sse2_packssdw" 21668 [(set (match_operand:V8HI 0 "register_operand" "=x") 21669 (vec_concat:V8HI 21670 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0")) 21671 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))] 21672 "TARGET_SSE2" 21673 "packssdw\t{%2, %0|%0, %2}" 21674 [(set_attr "type" "ssecvt") 21675 (set_attr "mode" "TI")]) 21676 21677(define_insn "sse2_packuswb" 21678 [(set (match_operand:V16QI 0 "register_operand" "=x") 21679 (vec_concat:V16QI 21680 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0")) 21681 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))] 21682 "TARGET_SSE2" 21683 "packuswb\t{%2, %0|%0, %2}" 21684 [(set_attr "type" "ssecvt") 21685 (set_attr "mode" "TI")]) 21686 21687(define_insn "sse2_punpckhbw" 21688 [(set (match_operand:V16QI 0 "register_operand" "=x") 21689 (vec_merge:V16QI 21690 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0") 21691 (parallel [(const_int 8) (const_int 0) 21692 (const_int 9) (const_int 1) 21693 (const_int 10) (const_int 2) 21694 (const_int 11) (const_int 3) 21695 (const_int 12) (const_int 4) 21696 (const_int 13) (const_int 5) 21697 (const_int 14) (const_int 6) 21698 (const_int 15) (const_int 7)])) 21699 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x") 21700 (parallel [(const_int 0) (const_int 8) 21701 (const_int 1) (const_int 9) 21702 (const_int 2) (const_int 10) 21703 (const_int 3) (const_int 11) 21704 (const_int 4) (const_int 12) 21705 (const_int 5) (const_int 13) 21706 (const_int 6) (const_int 14) 21707 (const_int 7) (const_int 15)])) 21708 (const_int 21845)))] 21709 "TARGET_SSE2" 21710 "punpckhbw\t{%2, %0|%0, %2}" 21711 [(set_attr "type" "ssecvt") 21712 (set_attr "mode" "TI")]) 21713 21714(define_insn "sse2_punpckhwd" 21715 [(set (match_operand:V8HI 0 "register_operand" "=x") 21716 (vec_merge:V8HI 21717 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0") 21718 (parallel [(const_int 4) (const_int 0) 21719 (const_int 5) (const_int 1) 21720 (const_int 6) (const_int 2) 21721 (const_int 7) (const_int 3)])) 21722 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x") 21723 (parallel [(const_int 0) (const_int 4) 21724 (const_int 1) (const_int 5) 21725 (const_int 2) (const_int 6) 21726 (const_int 3) (const_int 7)])) 21727 (const_int 85)))] 21728 "TARGET_SSE2" 21729 "punpckhwd\t{%2, %0|%0, %2}" 21730 [(set_attr "type" "ssecvt") 21731 (set_attr "mode" "TI")]) 21732 21733(define_insn "sse2_punpckhdq" 21734 [(set (match_operand:V4SI 0 "register_operand" "=x") 21735 (vec_merge:V4SI 21736 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0") 21737 (parallel [(const_int 2) (const_int 0) 21738 (const_int 3) (const_int 1)])) 21739 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x") 21740 (parallel [(const_int 0) (const_int 2) 21741 (const_int 1) (const_int 3)])) 21742 (const_int 5)))] 21743 "TARGET_SSE2" 21744 "punpckhdq\t{%2, %0|%0, %2}" 21745 [(set_attr "type" "ssecvt") 21746 (set_attr "mode" "TI")]) 21747 21748(define_insn "sse2_punpcklbw" 21749 [(set (match_operand:V16QI 0 "register_operand" "=x") 21750 (vec_merge:V16QI 21751 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0") 21752 (parallel [(const_int 0) (const_int 8) 21753 (const_int 1) (const_int 9) 21754 (const_int 2) (const_int 10) 21755 (const_int 3) (const_int 11) 21756 (const_int 4) (const_int 12) 21757 (const_int 5) (const_int 13) 21758 (const_int 6) (const_int 14) 21759 (const_int 7) (const_int 15)])) 21760 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x") 21761 (parallel [(const_int 8) (const_int 0) 21762 (const_int 9) (const_int 1) 21763 (const_int 10) (const_int 2) 21764 (const_int 11) (const_int 3) 21765 (const_int 12) (const_int 4) 21766 (const_int 13) (const_int 5) 21767 (const_int 14) (const_int 6) 21768 (const_int 15) (const_int 7)])) 21769 (const_int 21845)))] 21770 "TARGET_SSE2" 21771 "punpcklbw\t{%2, %0|%0, %2}" 21772 [(set_attr "type" "ssecvt") 21773 (set_attr "mode" "TI")]) 21774 21775(define_insn "sse2_punpcklwd" 21776 [(set (match_operand:V8HI 0 "register_operand" "=x") 21777 (vec_merge:V8HI 21778 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0") 21779 (parallel [(const_int 0) (const_int 4) 21780 (const_int 1) (const_int 5) 21781 (const_int 2) (const_int 6) 21782 (const_int 3) (const_int 7)])) 21783 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x") 21784 (parallel [(const_int 4) (const_int 0) 21785 (const_int 5) (const_int 1) 21786 (const_int 6) (const_int 2) 21787 (const_int 7) (const_int 3)])) 21788 (const_int 85)))] 21789 "TARGET_SSE2" 21790 "punpcklwd\t{%2, %0|%0, %2}" 21791 [(set_attr "type" "ssecvt") 21792 (set_attr "mode" "TI")]) 21793 21794(define_insn "sse2_punpckldq" 21795 [(set (match_operand:V4SI 0 "register_operand" "=x") 21796 (vec_merge:V4SI 21797 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0") 21798 (parallel [(const_int 0) (const_int 2) 21799 (const_int 1) (const_int 3)])) 21800 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x") 21801 (parallel [(const_int 2) (const_int 0) 21802 (const_int 3) (const_int 1)])) 21803 (const_int 5)))] 21804 "TARGET_SSE2" 21805 "punpckldq\t{%2, %0|%0, %2}" 21806 [(set_attr "type" "ssecvt") 21807 (set_attr "mode" "TI")]) 21808 21809(define_insn "sse2_punpcklqdq" 21810 [(set (match_operand:V2DI 0 "register_operand" "=x") 21811 (vec_merge:V2DI 21812 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x") 21813 (parallel [(const_int 1) 21814 (const_int 0)])) 21815 (match_operand:V2DI 1 "register_operand" "0") 21816 (const_int 1)))] 21817 "TARGET_SSE2" 21818 "punpcklqdq\t{%2, %0|%0, %2}" 21819 [(set_attr "type" "ssecvt") 21820 (set_attr "mode" "TI")]) 21821 21822(define_insn "sse2_punpckhqdq" 21823 [(set (match_operand:V2DI 0 "register_operand" "=x") 21824 (vec_merge:V2DI 21825 (match_operand:V2DI 1 "register_operand" "0") 21826 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x") 21827 (parallel [(const_int 1) 21828 (const_int 0)])) 21829 (const_int 1)))] 21830 "TARGET_SSE2" 21831 "punpckhqdq\t{%2, %0|%0, %2}" 21832 [(set_attr "type" "ssecvt") 21833 (set_attr "mode" "TI")]) 21834 21835;; SSE2 moves 21836 21837(define_insn "sse2_movapd" 21838 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m") 21839 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")] 21840 UNSPEC_MOVA))] 21841 "TARGET_SSE2 21842 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 21843 "movapd\t{%1, %0|%0, %1}" 21844 [(set_attr "type" "ssemov") 21845 (set_attr "mode" "V2DF")]) 21846 21847(define_insn "sse2_movupd" 21848 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m") 21849 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")] 21850 UNSPEC_MOVU))] 21851 "TARGET_SSE2 21852 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 21853 "movupd\t{%1, %0|%0, %1}" 21854 [(set_attr "type" "ssecvt") 21855 (set_attr "mode" "V2DF")]) 21856 21857(define_insn "sse2_movdqa" 21858 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m") 21859 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")] 21860 UNSPEC_MOVA))] 21861 "TARGET_SSE2 21862 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 21863 "movdqa\t{%1, %0|%0, %1}" 21864 [(set_attr "type" "ssemov") 21865 (set_attr "mode" "TI")]) 21866 21867(define_insn "sse2_movdqu" 21868 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m") 21869 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")] 21870 UNSPEC_MOVU))] 21871 "TARGET_SSE2 21872 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" 21873 "movdqu\t{%1, %0|%0, %1}" 21874 [(set_attr "type" "ssecvt") 21875 (set_attr "mode" "TI")]) 21876 21877(define_insn "sse2_movdq2q" 21878 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y") 21879 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x") 21880 (parallel [(const_int 0)])))] 21881 "TARGET_SSE2 && !TARGET_64BIT" 21882 "@ 21883 movq\t{%1, %0|%0, %1} 21884 movdq2q\t{%1, %0|%0, %1}" 21885 [(set_attr "type" "ssecvt") 21886 (set_attr "mode" "TI")]) 21887 21888(define_insn "sse2_movdq2q_rex64" 21889 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r") 21890 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x") 21891 (parallel [(const_int 0)])))] 21892 "TARGET_SSE2 && TARGET_64BIT" 21893 "@ 21894 movq\t{%1, %0|%0, %1} 21895 movdq2q\t{%1, %0|%0, %1} 21896 movd\t{%1, %0|%0, %1}" 21897 [(set_attr "type" "ssecvt") 21898 (set_attr "mode" "TI")]) 21899 21900(define_insn "sse2_movq2dq" 21901 [(set (match_operand:V2DI 0 "register_operand" "=x,?x") 21902 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y") 21903 (const_int 0)))] 21904 "TARGET_SSE2 && !TARGET_64BIT" 21905 "@ 21906 movq\t{%1, %0|%0, %1} 21907 movq2dq\t{%1, %0|%0, %1}" 21908 [(set_attr "type" "ssecvt,ssemov") 21909 (set_attr "mode" "TI")]) 21910 21911(define_insn "sse2_movq2dq_rex64" 21912 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x") 21913 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r") 21914 (const_int 0)))] 21915 "TARGET_SSE2 && TARGET_64BIT" 21916 "@ 21917 movq\t{%1, %0|%0, %1} 21918 movq2dq\t{%1, %0|%0, %1} 21919 movd\t{%1, %0|%0, %1}" 21920 [(set_attr "type" "ssecvt,ssemov,ssecvt") 21921 (set_attr "mode" "TI")]) 21922 21923(define_insn "sse2_movq" 21924 [(set (match_operand:V2DI 0 "register_operand" "=x") 21925 (vec_concat:V2DI (vec_select:DI 21926 (match_operand:V2DI 1 "nonimmediate_operand" "xm") 21927 (parallel [(const_int 0)])) 21928 (const_int 0)))] 21929 "TARGET_SSE2" 21930 "movq\t{%1, %0|%0, %1}" 21931 [(set_attr "type" "ssemov") 21932 (set_attr "mode" "TI")]) 21933 21934(define_insn "sse2_loadd" 21935 [(set (match_operand:V4SI 0 "register_operand" "=x") 21936 (vec_merge:V4SI 21937 (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr")) 21938 (const_vector:V4SI [(const_int 0) 21939 (const_int 0) 21940 (const_int 0) 21941 (const_int 0)]) 21942 (const_int 1)))] 21943 "TARGET_SSE2" 21944 "movd\t{%1, %0|%0, %1}" 21945 [(set_attr "type" "ssemov") 21946 (set_attr "mode" "TI")]) 21947 21948(define_insn "sse2_stored" 21949 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 21950 (vec_select:SI 21951 (match_operand:V4SI 1 "register_operand" "x") 21952 (parallel [(const_int 0)])))] 21953 "TARGET_SSE2" 21954 "movd\t{%1, %0|%0, %1}" 21955 [(set_attr "type" "ssemov") 21956 (set_attr "mode" "TI")]) 21957 21958(define_insn "sse2_movhpd" 21959 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m") 21960 (vec_merge:V2DF 21961 (match_operand:V2DF 1 "nonimmediate_operand" "0,0") 21962 (match_operand:V2DF 2 "nonimmediate_operand" "m,x") 21963 (const_int 2)))] 21964 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)" 21965 "movhpd\t{%2, %0|%0, %2}" 21966 [(set_attr "type" "ssecvt") 21967 (set_attr "mode" "V2DF")]) 21968 21969(define_insn "sse2_movlpd" 21970 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m") 21971 (vec_merge:V2DF 21972 (match_operand:V2DF 1 "nonimmediate_operand" "0,0") 21973 (match_operand:V2DF 2 "nonimmediate_operand" "m,x") 21974 (const_int 1)))] 21975 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)" 21976 "movlpd\t{%2, %0|%0, %2}" 21977 [(set_attr "type" "ssecvt") 21978 (set_attr "mode" "V2DF")]) 21979 21980(define_expand "sse2_loadsd" 21981 [(match_operand:V2DF 0 "register_operand" "") 21982 (match_operand:DF 1 "memory_operand" "")] 21983 "TARGET_SSE2" 21984{ 21985 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1], 21986 CONST0_RTX (V2DFmode))); 21987 DONE; 21988}) 21989 21990(define_insn "sse2_loadsd_1" 21991 [(set (match_operand:V2DF 0 "register_operand" "=x") 21992 (vec_merge:V2DF 21993 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")) 21994 (match_operand:V2DF 2 "const0_operand" "X") 21995 (const_int 1)))] 21996 "TARGET_SSE2" 21997 "movsd\t{%1, %0|%0, %1}" 21998 [(set_attr "type" "ssecvt") 21999 (set_attr "mode" "DF")]) 22000 22001(define_insn "sse2_movsd" 22002 [(set (match_operand:V2DF 0 "register_operand" "=x") 22003 (vec_merge:V2DF 22004 (match_operand:V2DF 1 "register_operand" "0") 22005 (match_operand:V2DF 2 "register_operand" "x") 22006 (const_int 1)))] 22007 "TARGET_SSE2" 22008 "movsd\t{%2, %0|%0, %2}" 22009 [(set_attr "type" "ssecvt") 22010 (set_attr "mode" "DF")]) 22011 22012(define_insn "sse2_storesd" 22013 [(set (match_operand:DF 0 "memory_operand" "=m") 22014 (vec_select:DF 22015 (match_operand:V2DF 1 "register_operand" "x") 22016 (parallel [(const_int 0)])))] 22017 "TARGET_SSE2" 22018 "movsd\t{%1, %0|%0, %1}" 22019 [(set_attr "type" "ssecvt") 22020 (set_attr "mode" "DF")]) 22021 22022(define_insn "sse2_shufpd" 22023 [(set (match_operand:V2DF 0 "register_operand" "=x") 22024 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") 22025 (match_operand:V2DF 2 "nonimmediate_operand" "xm") 22026 (match_operand:SI 3 "immediate_operand" "i")] 22027 UNSPEC_SHUFFLE))] 22028 "TARGET_SSE2" 22029 ;; @@@ check operand order for intel/nonintel syntax 22030 "shufpd\t{%3, %2, %0|%0, %2, %3}" 22031 [(set_attr "type" "ssecvt") 22032 (set_attr "mode" "V2DF")]) 22033 22034(define_insn "sse2_clflush" 22035 [(unspec_volatile [(match_operand 0 "address_operand" "p")] 22036 UNSPECV_CLFLUSH)] 22037 "TARGET_SSE2" 22038 "clflush %0" 22039 [(set_attr "type" "sse") 22040 (set_attr "memory" "unknown")]) 22041 22042(define_expand "sse2_mfence" 22043 [(set (match_dup 0) 22044 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))] 22045 "TARGET_SSE2" 22046{ 22047 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 22048 MEM_VOLATILE_P (operands[0]) = 1; 22049}) 22050 22051(define_insn "*mfence_insn" 22052 [(set (match_operand:BLK 0 "" "") 22053 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))] 22054 "TARGET_SSE2" 22055 "mfence" 22056 [(set_attr "type" "sse") 22057 (set_attr "memory" "unknown")]) 22058 22059(define_expand "sse2_lfence" 22060 [(set (match_dup 0) 22061 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))] 22062 "TARGET_SSE2" 22063{ 22064 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 22065 MEM_VOLATILE_P (operands[0]) = 1; 22066}) 22067 22068(define_insn "*lfence_insn" 22069 [(set (match_operand:BLK 0 "" "") 22070 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))] 22071 "TARGET_SSE2" 22072 "lfence" 22073 [(set_attr "type" "sse") 22074 (set_attr "memory" "unknown")]) 22075