alpha-opc.c revision 33965
11539Srgrimes/* alpha-opc.c -- Alpha AXP opcode list 21539Srgrimes Copyright 1996 Free Software Foundation, Inc. 31539Srgrimes Contributed by Richard Henderson <rth@tamu.edu>, 41539Srgrimes patterned after the PPC opcode handling written by Ian Lance Taylor. 51539Srgrimes 61539Srgrimes This file is part of GDB, GAS, and the GNU binutils. 71539Srgrimes 81539Srgrimes GDB, GAS, and the GNU binutils are free software; you can redistribute 91539Srgrimes them and/or modify them under the terms of the GNU General Public 101539Srgrimes License as published by the Free Software Foundation; either version 111539Srgrimes 2, or (at your option) any later version. 121539Srgrimes 13203964Simp GDB, GAS, and the GNU binutils are distributed in the hope that they 141539Srgrimes will be useful, but WITHOUT ANY WARRANTY; without even the implied 151539Srgrimes warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 161539Srgrimes the GNU General Public License for more details. 171539Srgrimes 181539Srgrimes You should have received a copy of the GNU General Public License 191539Srgrimes along with this file; see the file COPYING. If not, write to the 201539Srgrimes Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 211539Srgrimes 02111-1307, USA. */ 221539Srgrimes 231539Srgrimes#include <stdio.h> 241539Srgrimes#include "ansidecl.h" 251539Srgrimes#include "opcode/alpha.h" 261539Srgrimes#include "bfd.h" 271539Srgrimes 281539Srgrimes/* This file holds the Alpha AXP opcode table. The opcode table includes 291539Srgrimes almost all of the extended instruction mnemonics. This permits the 30203964Simp disassembler to use them, and simplifies the assembler logic, at the 31203964Simp cost of increasing the table size. The table is strictly constant 321539Srgrimes data, so the compiler should be able to put it in the .text section. 331539Srgrimes 342162Spaul This file also holds the operand table. All knowledge about inserting 352162Spaul operands into instructions and vice-versa is kept in this file. 362162Spaul 371539Srgrimes The information for the base instruction set was compiled from the 381539Srgrimes _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE, 391539Srgrimes version 2. 401539Srgrimes 411539Srgrimes The information for the post-ev5 architecture extensions BWX, CIX and 421539Srgrimes MAX came from version 3 of this same document, which is also available 431539Srgrimes on-line at http://ftp.digital.com/pub/Digital/info/semiconductor 441539Srgrimes /literature/alphahb2.pdf 451539Srgrimes 461539Srgrimes The information for the EV4 PALcode instructions was compiled from 471539Srgrimes _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware 481539Srgrimes Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary 491539Srgrimes revision dated June 1994. 501539Srgrimes 511539Srgrimes The information for the EV5 PALcode instructions was compiled from 521539Srgrimes _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital 531539Srgrimes Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */ 541539Srgrimes 551539Srgrimes/* Local insertion and extraction functions */ 561539Srgrimes 571539Srgrimesstatic unsigned insert_rba PARAMS((unsigned, int, const char **)); 581539Srgrimesstatic unsigned insert_rca PARAMS((unsigned, int, const char **)); 591539Srgrimesstatic unsigned insert_za PARAMS((unsigned, int, const char **)); 601539Srgrimesstatic unsigned insert_zb PARAMS((unsigned, int, const char **)); 611539Srgrimesstatic unsigned insert_zc PARAMS((unsigned, int, const char **)); 621539Srgrimesstatic unsigned insert_bdisp PARAMS((unsigned, int, const char **)); 631539Srgrimesstatic unsigned insert_jhint PARAMS((unsigned, int, const char **)); 641539Srgrimes 651539Srgrimesstatic int extract_rba PARAMS((unsigned, int *)); 661539Srgrimesstatic int extract_rca PARAMS((unsigned, int *)); 671539Srgrimesstatic int extract_za PARAMS((unsigned, int *)); 681539Srgrimesstatic int extract_zb PARAMS((unsigned, int *)); 692162Spaulstatic int extract_zc PARAMS((unsigned, int *)); 702162Spaulstatic int extract_bdisp PARAMS((unsigned, int *)); 71static int extract_jhint PARAMS((unsigned, int *)); 72 73 74/* The operands table */ 75 76const struct alpha_operand alpha_operands[] = 77{ 78 /* The fields are bits, shift, insert, extract, flags */ 79 /* The zero index is used to indicate end-of-list */ 80#define UNUSED 0 81 { 0, 0, 0, 0, 0 }, 82 83 /* The plain integer register fields */ 84#define RA (UNUSED + 1) 85 { 5, 21, 0, AXP_OPERAND_IR, 0, 0 }, 86#define RB (RA + 1) 87 { 5, 16, 0, AXP_OPERAND_IR, 0, 0 }, 88#define RC (RB + 1) 89 { 5, 0, 0, AXP_OPERAND_IR, 0, 0 }, 90 91 /* The plain fp register fields */ 92#define FA (RC + 1) 93 { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 }, 94#define FB (FA + 1) 95 { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 }, 96#define FC (FB + 1) 97 { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 }, 98 99 /* The integer registers when they are ZERO */ 100#define ZA (FC + 1) 101 { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za }, 102#define ZB (ZA + 1) 103 { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb }, 104#define ZC (ZB + 1) 105 { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc }, 106 107 /* The RB field when it needs parentheses */ 108#define PRB (ZC + 1) 109 { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 }, 110 111 /* The RB field when it needs parentheses _and_ a preceding comma */ 112#define CPRB (PRB + 1) 113 { 5, 16, 0, 114 AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 }, 115 116 /* The RB field when it must be the same as the RA field */ 117#define RBA (CPRB + 1) 118 { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba }, 119 120 /* The RC field when it must be the same as the RB field */ 121#define RCA (RBA + 1) 122 { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca }, 123 124 /* The RC field when it can *default* to RA */ 125#define DRC1 (RCA + 1) 126 { 5, 0, 0, 127 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, 128 129 /* The RC field when it can *default* to RB */ 130#define DRC2 (DRC1 + 1) 131 { 5, 0, 0, 132 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, 133 134 /* The FC field when it can *default* to RA */ 135#define DFC1 (DRC2 + 1) 136 { 5, 0, 0, 137 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, 138 139 /* The FC field when it can *default* to RB */ 140#define DFC2 (DFC1 + 1) 141 { 5, 0, 0, 142 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, 143 144 /* The unsigned 8-bit literal of Operate format insns */ 145#define LIT (DFC2 + 1) 146 { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 }, 147 148 /* The signed 16-bit displacement of Memory format insns. From here 149 we can't tell what relocation should be used, so don't use a default. */ 150#define MDISP (LIT + 1) 151 { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 }, 152 153 /* The signed "23-bit" aligned displacement of Branch format insns */ 154#define BDISP (MDISP + 1) 155 { 21, 0, BFD_RELOC_23_PCREL_S2, 156 AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp }, 157 158 /* The 26-bit PALcode function */ 159#define PALFN (BDISP + 1) 160 { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 }, 161 162 /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */ 163#define JMPHINT (PALFN + 1) 164 { 14, 0, BFD_RELOC_ALPHA_HINT, 165 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, 166 insert_jhint, extract_jhint }, 167 168 /* The optional hint to RET/JSR_COROUTINE */ 169#define RETHINT (JMPHINT + 1) 170 { 14, 0, -RETHINT, 171 AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 }, 172 173 /* The 12-bit displacement for the ev4 hw_{ld,st} (pal1b/pal1f) insns */ 174#define EV4HWDISP (RETHINT + 1) 175 { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, 176 177 /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */ 178#define EV4HWINDEX (EV4HWDISP + 1) 179 { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 180 181 /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns 182 that occur in DEC PALcode. */ 183#define EV4EXTHWINDEX (EV4HWINDEX + 1) 184 { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 185 186 /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */ 187#define EV5HWDISP (EV4EXTHWINDEX + 1) 188 { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, 189 190 /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */ 191#define EV5HWINDEX (EV5HWDISP + 1) 192 { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 193}; 194 195const int alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); 196 197/* The RB field when it is the same as the RA field in the same insn. 198 This operand is marked fake. The insertion function just copies 199 the RA field into the RB field, and the extraction function just 200 checks that the fields are the same. */ 201 202/*ARGSUSED*/ 203static unsigned 204insert_rba(insn, value, errmsg) 205 unsigned insn; 206 int value; 207 const char **errmsg; 208{ 209 return insn | (((insn >> 21) & 0x1f) << 16); 210} 211 212static int 213extract_rba(insn, invalid) 214 unsigned insn; 215 int *invalid; 216{ 217 if (invalid != (int *) NULL 218 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 219 *invalid = 1; 220 return 0; 221} 222 223 224/* The same for the RC field */ 225 226/*ARGSUSED*/ 227static unsigned 228insert_rca(insn, value, errmsg) 229 unsigned insn; 230 int value; 231 const char **errmsg; 232{ 233 return insn | ((insn >> 21) & 0x1f); 234} 235 236static int 237extract_rca(insn, invalid) 238 unsigned insn; 239 int *invalid; 240{ 241 if (invalid != (int *) NULL 242 && ((insn >> 21) & 0x1f) != (insn & 0x1f)) 243 *invalid = 1; 244 return 0; 245} 246 247 248/* Fake arguments in which the registers must be set to ZERO */ 249 250/*ARGSUSED*/ 251static unsigned 252insert_za(insn, value, errmsg) 253 unsigned insn; 254 int value; 255 const char **errmsg; 256{ 257 return insn | (31 << 21); 258} 259 260static int 261extract_za(insn, invalid) 262 unsigned insn; 263 int *invalid; 264{ 265 if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) 266 *invalid = 1; 267 return 0; 268} 269 270/*ARGSUSED*/ 271static unsigned 272insert_zb(insn, value, errmsg) 273 unsigned insn; 274 int value; 275 const char **errmsg; 276{ 277 return insn | (31 << 16); 278} 279 280static int 281extract_zb(insn, invalid) 282 unsigned insn; 283 int *invalid; 284{ 285 if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) 286 *invalid = 1; 287 return 0; 288} 289 290/*ARGSUSED*/ 291static unsigned 292insert_zc(insn, value, errmsg) 293 unsigned insn; 294 int value; 295 const char **errmsg; 296{ 297 return insn | 31; 298} 299 300static int 301extract_zc(insn, invalid) 302 unsigned insn; 303 int *invalid; 304{ 305 if (invalid != (int *) NULL && (insn & 0x1f) != 31) 306 *invalid = 1; 307 return 0; 308} 309 310 311/* The displacement field of a Branch format insn. */ 312 313static unsigned 314insert_bdisp(insn, value, errmsg) 315 unsigned insn; 316 int value; 317 const char **errmsg; 318{ 319 if (errmsg != (const char **)NULL && (value & 3)) 320 *errmsg = "branch operand unaligned"; 321 return insn | ((value / 4) & 0x1FFFFF); 322} 323 324/*ARGSUSED*/ 325static int 326extract_bdisp(insn, invalid) 327 unsigned insn; 328 int *invalid; 329{ 330 return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); 331} 332 333 334/* The hint field of a JMP/JSR insn. */ 335 336static unsigned 337insert_jhint(insn, value, errmsg) 338 unsigned insn; 339 int value; 340 const char **errmsg; 341{ 342 if (errmsg != (const char **)NULL && (value & 3)) 343 *errmsg = "jump hint unaligned"; 344 return insn | ((value / 4) & 0xFFFF); 345} 346 347/*ARGSUSED*/ 348static int 349extract_jhint(insn, invalid) 350 unsigned insn; 351 int *invalid; 352{ 353 return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); 354} 355 356 357/* Macros used to form opcodes */ 358 359/* The main opcode */ 360#define OP(x) (((x) & 0x3F) << 26) 361#define OP_MASK 0xFC000000 362 363/* Branch format instructions */ 364#define BRA_(oo) OP(oo) 365#define BRA_MASK OP_MASK 366#define BRA(oo) BRA_(oo), BRA_MASK 367 368/* Floating point format instructions */ 369#define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) 370#define FP_MASK (OP_MASK | 0xFFE0) 371#define FP(oo,fff) FP_(oo,fff), FP_MASK 372 373/* Memory format instructions */ 374#define MEM_(oo) OP(oo) 375#define MEM_MASK OP_MASK 376#define MEM(oo) MEM_(oo), MEM_MASK 377 378/* Memory/Func Code format instructions */ 379#define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) 380#define MFC_MASK (OP_MASK | 0xFFFF) 381#define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK 382 383/* Memory/Branch format instructions */ 384#define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) 385#define MBR_MASK (OP_MASK | 0xC000) 386#define MBR(oo,h) MBR_(oo,h), MBR_MASK 387 388/* Operate format instructions. The OPRL variant specifies a 389 literal second argument. */ 390#define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) 391#define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) 392#define OPR_MASK (OP_MASK | 0x1FE0) 393#define OPR(oo,ff) OPR_(oo,ff), OPR_MASK 394#define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK 395 396/* Generic PALcode format instructions */ 397#define PCD_(oo) OP(oo) 398#define PCD_MASK OP_MASK 399#define PCD(oo) PCD_(oo), PCD_MASK 400 401/* Specific PALcode instructions */ 402#define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) 403#define SPCD_MASK 0xFFFFFFFF 404#define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK 405 406/* Hardware memory (hw_{ld,st}) instructions */ 407#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) 408#define EV4HWMEM_MASK (OP_MASK | 0xF000) 409#define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK 410 411#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10)) 412#define EV5HWMEM_MASK (OP_MASK | 0xF800) 413#define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK 414 415/* Abbreviations for instruction subsets. */ 416#define BASE AXP_OPCODE_BASE 417#define EV4 AXP_OPCODE_EV4 418#define EV5 AXP_OPCODE_EV5 419#define BWX AXP_OPCODE_BWX 420#define CIX AXP_OPCODE_CIX 421#define MAX AXP_OPCODE_MAX 422 423/* Common combinations of arguments */ 424#define ARG_NONE { 0 } 425#define ARG_BRA { RA, BDISP } 426#define ARG_FBRA { FA, BDISP } 427#define ARG_FP { FA, FB, DFC1 } 428#define ARG_FPZ1 { ZA, FB, DFC1 } 429#define ARG_MEM { RA, MDISP, PRB } 430#define ARG_FMEM { FA, MDISP, PRB } 431#define ARG_OPR { RA, RB, DRC1 } 432#define ARG_OPRL { RA, LIT, DRC1 } 433#define ARG_OPRZ1 { ZA, RB, DRC1 } 434#define ARG_OPRLZ1 { ZA, LIT, RC } 435#define ARG_PCD { PALFN } 436#define ARG_EV4HWMEM { RA, EV4HWDISP, PRB } 437#define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX } 438#define ARG_EV5HWMEM { RA, EV5HWDISP, PRB } 439 440 441/* The opcode table. 442 443 The format of the opcode table is: 444 445 NAME OPCODE MASK { OPERANDS } 446 447 NAME is the name of the instruction. 448 449 OPCODE is the instruction opcode. 450 451 MASK is the opcode mask; this is used to tell the disassembler 452 which bits in the actual opcode must match OPCODE. 453 454 OPERANDS is the list of operands. 455 456 The preceding macros merge the text of the OPCODE and MASK fields. 457 458 The disassembler reads the table in order and prints the first 459 instruction which matches, so this table is sorted to put more 460 specific instructions before more general instructions. 461 462 Otherwise, it is sorted by major opcode and minor function code. 463 464 There are three classes of not-really-instructions in this table: 465 466 ALIAS is another name for another instruction. Some of 467 these come from the Architecture Handbook, some 468 come from the original gas opcode tables. In all 469 cases, the functionality of the opcode is unchanged. 470 471 PSEUDO a stylized code form endorsed by Chapter A.4 of the 472 Architecture Handbook. 473 474 EXTRA a stylized code form found in the original gas tables. 475 476 And two annotations: 477 478 EV56 BUT opcodes that are officially introduced as of the ev56, 479 but with defined results on previous implementations. 480 481 EV56 UNA opcodes that were introduced as of the ev56 with 482 presumably undefined results on previous implementations 483 that were not assigned to a particular extension. 484*/ 485 486const struct alpha_opcode alpha_opcodes[] = { 487 { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, 488 { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, 489 { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, 490 { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, 491 { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, 492 { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, 493 { "call_pal", PCD(0x00), BASE, ARG_PCD }, 494 { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ 495 496 { "lda", MEM(0x08), BASE, ARG_MEM }, 497 { "ldah", MEM(0x09), BASE, ARG_MEM }, 498 { "ldbu", MEM(0x0A), BWX, ARG_MEM }, 499 { "unop", MEM(0x0B), BASE, { ZA } }, /* pseudo */ 500 { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, 501 { "ldwu", MEM(0x0C), BWX, ARG_MEM }, 502 { "stw", MEM(0x0D), BWX, ARG_MEM }, 503 { "stb", MEM(0x0E), BWX, ARG_MEM }, 504 { "stq_u", MEM(0x0F), BASE, ARG_MEM }, 505 506 { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */ 507 { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */ 508 { "addl", OPR(0x10,0x00), BASE, ARG_OPR }, 509 { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL }, 510 { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR }, 511 { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL }, 512 { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */ 513 { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */ 514 { "subl", OPR(0x10,0x09), BASE, ARG_OPR }, 515 { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL }, 516 { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR }, 517 { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL }, 518 { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR }, 519 { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL }, 520 { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR }, 521 { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL }, 522 { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR }, 523 { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL }, 524 { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR }, 525 { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL }, 526 { "addq", OPR(0x10,0x20), BASE, ARG_OPR }, 527 { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL }, 528 { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR }, 529 { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL }, 530 { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */ 531 { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */ 532 { "subq", OPR(0x10,0x29), BASE, ARG_OPR }, 533 { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL }, 534 { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR }, 535 { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL }, 536 { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR }, 537 { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL }, 538 { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR }, 539 { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL }, 540 { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR }, 541 { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL }, 542 { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR }, 543 { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL }, 544 { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR }, 545 { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL }, 546 { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */ 547 { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */ 548 { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR }, 549 { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL }, 550 { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR }, 551 { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL }, 552 { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR }, 553 { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL }, 554 { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */ 555 { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */ 556 { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR }, 557 { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL }, 558 { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR }, 559 { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL }, 560 561 { "and", OPR(0x11,0x00), BASE, ARG_OPR }, 562 { "and", OPRL(0x11,0x00), BASE, ARG_OPRL }, 563 { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */ 564 { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */ 565 { "bic", OPR(0x11,0x08), BASE, ARG_OPR }, 566 { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL }, 567 { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR }, 568 { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL }, 569 { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR }, 570 { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL }, 571 { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */ 572 { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ 573 { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ 574 { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */ 575 { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */ 576 { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */ 577 { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */ 578 { "bis", OPR(0x11,0x20), BASE, ARG_OPR }, 579 { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL }, 580 { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR }, 581 { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL }, 582 { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR }, 583 { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL }, 584 { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */ 585 { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */ 586 { "ornot", OPR(0x11,0x28), BASE, ARG_OPR }, 587 { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL }, 588 { "xor", OPR(0x11,0x40), BASE, ARG_OPR }, 589 { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL }, 590 { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR }, 591 { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL }, 592 { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR }, 593 { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL }, 594 { "eqv", OPR(0x11,0x48), BASE, ARG_OPR }, 595 { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL }, 596 { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */ 597 { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */ 598 { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */ 599 { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */ 600 { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR }, 601 { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL }, 602 { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, 603 { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, 604 { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), 605 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ 606 607 { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, 608 { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, 609 { "extbl", OPR(0x12,0x06), BASE, ARG_OPR }, 610 { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL }, 611 { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR }, 612 { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL }, 613 { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR }, 614 { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL }, 615 { "extwl", OPR(0x12,0x16), BASE, ARG_OPR }, 616 { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL }, 617 { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR }, 618 { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL }, 619 { "mskll", OPR(0x12,0x22), BASE, ARG_OPR }, 620 { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL }, 621 { "extll", OPR(0x12,0x26), BASE, ARG_OPR }, 622 { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL }, 623 { "insll", OPR(0x12,0x2B), BASE, ARG_OPR }, 624 { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL }, 625 { "zap", OPR(0x12,0x30), BASE, ARG_OPR }, 626 { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL }, 627 { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR }, 628 { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL }, 629 { "mskql", OPR(0x12,0x32), BASE, ARG_OPR }, 630 { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL }, 631 { "srl", OPR(0x12,0x34), BASE, ARG_OPR }, 632 { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL }, 633 { "extql", OPR(0x12,0x36), BASE, ARG_OPR }, 634 { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL }, 635 { "sll", OPR(0x12,0x39), BASE, ARG_OPR }, 636 { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL }, 637 { "insql", OPR(0x12,0x3B), BASE, ARG_OPR }, 638 { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL }, 639 { "sra", OPR(0x12,0x3C), BASE, ARG_OPR }, 640 { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL }, 641 { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR }, 642 { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL }, 643 { "inswh", OPR(0x12,0x57), BASE, ARG_OPR }, 644 { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL }, 645 { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR }, 646 { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL }, 647 { "msklh", OPR(0x12,0x62), BASE, ARG_OPR }, 648 { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL }, 649 { "inslh", OPR(0x12,0x67), BASE, ARG_OPR }, 650 { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL }, 651 { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR }, 652 { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL }, 653 { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR }, 654 { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL }, 655 { "insqh", OPR(0x12,0x77), BASE, ARG_OPR }, 656 { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL }, 657 { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR }, 658 { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL }, 659 660 { "mull", OPR(0x13,0x00), BASE, ARG_OPR }, 661 { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL }, 662 { "mulq", OPR(0x13,0x20), BASE, ARG_OPR }, 663 { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL }, 664 { "umulh", OPR(0x13,0x30), BASE, ARG_OPR }, 665 { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL }, 666 { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR }, 667 { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL }, 668 { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR }, 669 { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL }, 670 671 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } }, 672 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } }, 673 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } }, 674 { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 }, 675 { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 }, 676 { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 }, 677 { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 }, 678 679 { "addf/c", FP(0x15,0x000), BASE, ARG_FP }, 680 { "subf/c", FP(0x15,0x001), BASE, ARG_FP }, 681 { "mulf/c", FP(0x15,0x002), BASE, ARG_FP }, 682 { "divf/c", FP(0x15,0x003), BASE, ARG_FP }, 683 { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 }, 684 { "addg/c", FP(0x15,0x020), BASE, ARG_FP }, 685 { "subg/c", FP(0x15,0x021), BASE, ARG_FP }, 686 { "mulg/c", FP(0x15,0x022), BASE, ARG_FP }, 687 { "divg/c", FP(0x15,0x023), BASE, ARG_FP }, 688 { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 }, 689 { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 }, 690 { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 }, 691 { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 }, 692 { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 }, 693 { "addf", FP(0x15,0x080), BASE, ARG_FP }, 694 { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */ 695 { "subf", FP(0x15,0x081), BASE, ARG_FP }, 696 { "mulf", FP(0x15,0x082), BASE, ARG_FP }, 697 { "divf", FP(0x15,0x083), BASE, ARG_FP }, 698 { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 }, 699 { "addg", FP(0x15,0x0A0), BASE, ARG_FP }, 700 { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ 701 { "subg", FP(0x15,0x0A1), BASE, ARG_FP }, 702 { "mulg", FP(0x15,0x0A2), BASE, ARG_FP }, 703 { "divg", FP(0x15,0x0A3), BASE, ARG_FP }, 704 { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP }, 705 { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP }, 706 { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP }, 707 { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 }, 708 { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 }, 709 { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 }, 710 { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 }, 711 { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 }, 712 { "addf/uc", FP(0x15,0x100), BASE, ARG_FP }, 713 { "subf/uc", FP(0x15,0x101), BASE, ARG_FP }, 714 { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP }, 715 { "divf/uc", FP(0x15,0x103), BASE, ARG_FP }, 716 { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 }, 717 { "addg/uc", FP(0x15,0x120), BASE, ARG_FP }, 718 { "subg/uc", FP(0x15,0x121), BASE, ARG_FP }, 719 { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP }, 720 { "divg/uc", FP(0x15,0x123), BASE, ARG_FP }, 721 { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 }, 722 { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 }, 723 { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 }, 724 { "addf/u", FP(0x15,0x180), BASE, ARG_FP }, 725 { "subf/u", FP(0x15,0x181), BASE, ARG_FP }, 726 { "mulf/u", FP(0x15,0x182), BASE, ARG_FP }, 727 { "divf/u", FP(0x15,0x183), BASE, ARG_FP }, 728 { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 }, 729 { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP }, 730 { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP }, 731 { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP }, 732 { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP }, 733 { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 }, 734 { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 }, 735 { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 }, 736 { "addf/sc", FP(0x15,0x400), BASE, ARG_FP }, 737 { "subf/sc", FP(0x15,0x401), BASE, ARG_FP }, 738 { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP }, 739 { "divf/sc", FP(0x15,0x403), BASE, ARG_FP }, 740 { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 }, 741 { "addg/sc", FP(0x15,0x420), BASE, ARG_FP }, 742 { "subg/sc", FP(0x15,0x421), BASE, ARG_FP }, 743 { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP }, 744 { "divg/sc", FP(0x15,0x423), BASE, ARG_FP }, 745 { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 }, 746 { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 }, 747 { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 }, 748 { "addf/s", FP(0x15,0x480), BASE, ARG_FP }, 749 { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */ 750 { "subf/s", FP(0x15,0x481), BASE, ARG_FP }, 751 { "mulf/s", FP(0x15,0x482), BASE, ARG_FP }, 752 { "divf/s", FP(0x15,0x483), BASE, ARG_FP }, 753 { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 }, 754 { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP }, 755 { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */ 756 { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP }, 757 { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP }, 758 { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP }, 759 { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP }, 760 { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP }, 761 { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP }, 762 { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 }, 763 { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 }, 764 { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 }, 765 { "addf/suc", FP(0x15,0x500), BASE, ARG_FP }, 766 { "subf/suc", FP(0x15,0x501), BASE, ARG_FP }, 767 { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP }, 768 { "divf/suc", FP(0x15,0x503), BASE, ARG_FP }, 769 { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 }, 770 { "addg/suc", FP(0x15,0x520), BASE, ARG_FP }, 771 { "subg/suc", FP(0x15,0x521), BASE, ARG_FP }, 772 { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP }, 773 { "divg/suc", FP(0x15,0x523), BASE, ARG_FP }, 774 { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 }, 775 { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 }, 776 { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 }, 777 { "addf/su", FP(0x15,0x580), BASE, ARG_FP }, 778 { "subf/su", FP(0x15,0x581), BASE, ARG_FP }, 779 { "mulf/su", FP(0x15,0x582), BASE, ARG_FP }, 780 { "divf/su", FP(0x15,0x583), BASE, ARG_FP }, 781 { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 }, 782 { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP }, 783 { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP }, 784 { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP }, 785 { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP }, 786 { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 }, 787 { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 }, 788 { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 }, 789 790 { "adds/c", FP(0x16,0x000), BASE, ARG_FP }, 791 { "subs/c", FP(0x16,0x001), BASE, ARG_FP }, 792 { "muls/c", FP(0x16,0x002), BASE, ARG_FP }, 793 { "divs/c", FP(0x16,0x003), BASE, ARG_FP }, 794 { "addt/c", FP(0x16,0x020), BASE, ARG_FP }, 795 { "subt/c", FP(0x16,0x021), BASE, ARG_FP }, 796 { "mult/c", FP(0x16,0x022), BASE, ARG_FP }, 797 { "divt/c", FP(0x16,0x023), BASE, ARG_FP }, 798 { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 }, 799 { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 }, 800 { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 }, 801 { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 }, 802 { "adds/m", FP(0x16,0x040), BASE, ARG_FP }, 803 { "subs/m", FP(0x16,0x041), BASE, ARG_FP }, 804 { "muls/m", FP(0x16,0x042), BASE, ARG_FP }, 805 { "divs/m", FP(0x16,0x043), BASE, ARG_FP }, 806 { "addt/m", FP(0x16,0x060), BASE, ARG_FP }, 807 { "subt/m", FP(0x16,0x061), BASE, ARG_FP }, 808 { "mult/m", FP(0x16,0x062), BASE, ARG_FP }, 809 { "divt/m", FP(0x16,0x063), BASE, ARG_FP }, 810 { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 }, 811 { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 }, 812 { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 }, 813 { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 }, 814 { "adds", FP(0x16,0x080), BASE, ARG_FP }, 815 { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */ 816 { "subs", FP(0x16,0x081), BASE, ARG_FP }, 817 { "muls", FP(0x16,0x082), BASE, ARG_FP }, 818 { "divs", FP(0x16,0x083), BASE, ARG_FP }, 819 { "addt", FP(0x16,0x0A0), BASE, ARG_FP }, 820 { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ 821 { "subt", FP(0x16,0x0A1), BASE, ARG_FP }, 822 { "mult", FP(0x16,0x0A2), BASE, ARG_FP }, 823 { "divt", FP(0x16,0x0A3), BASE, ARG_FP }, 824 { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP }, 825 { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP }, 826 { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP }, 827 { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP }, 828 { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 }, 829 { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 }, 830 { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 }, 831 { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 }, 832 { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP }, 833 { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP }, 834 { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP }, 835 { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP }, 836 { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP }, 837 { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP }, 838 { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP }, 839 { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP }, 840 { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 }, 841 { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 }, 842 { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 }, 843 { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 }, 844 { "adds/uc", FP(0x16,0x100), BASE, ARG_FP }, 845 { "subs/uc", FP(0x16,0x101), BASE, ARG_FP }, 846 { "muls/uc", FP(0x16,0x102), BASE, ARG_FP }, 847 { "divs/uc", FP(0x16,0x103), BASE, ARG_FP }, 848 { "addt/uc", FP(0x16,0x120), BASE, ARG_FP }, 849 { "subt/uc", FP(0x16,0x121), BASE, ARG_FP }, 850 { "mult/uc", FP(0x16,0x122), BASE, ARG_FP }, 851 { "divt/uc", FP(0x16,0x123), BASE, ARG_FP }, 852 { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 }, 853 { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 }, 854 { "adds/um", FP(0x16,0x140), BASE, ARG_FP }, 855 { "subs/um", FP(0x16,0x141), BASE, ARG_FP }, 856 { "muls/um", FP(0x16,0x142), BASE, ARG_FP }, 857 { "divs/um", FP(0x16,0x143), BASE, ARG_FP }, 858 { "addt/um", FP(0x16,0x160), BASE, ARG_FP }, 859 { "subt/um", FP(0x16,0x161), BASE, ARG_FP }, 860 { "mult/um", FP(0x16,0x162), BASE, ARG_FP }, 861 { "divt/um", FP(0x16,0x163), BASE, ARG_FP }, 862 { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 }, 863 { "cvttq/um", FP(0x16,0x16F), BASE, ARG_FPZ1 }, 864 { "cvtqs/um", FP(0x16,0x17C), BASE, ARG_FPZ1 }, 865 { "adds/u", FP(0x16,0x180), BASE, ARG_FP }, 866 { "subs/u", FP(0x16,0x181), BASE, ARG_FP }, 867 { "muls/u", FP(0x16,0x182), BASE, ARG_FP }, 868 { "divs/u", FP(0x16,0x183), BASE, ARG_FP }, 869 { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP }, 870 { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP }, 871 { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP }, 872 { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP }, 873 { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 }, 874 { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 }, 875 { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP }, 876 { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP }, 877 { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP }, 878 { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP }, 879 { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP }, 880 { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP }, 881 { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP }, 882 { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP }, 883 { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 }, 884 { "cvttq/ud", FP(0x16,0x1EF), BASE, ARG_FPZ1 }, 885 { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 }, 886 { "adds/suc", FP(0x16,0x500), BASE, ARG_FP }, 887 { "subs/suc", FP(0x16,0x501), BASE, ARG_FP }, 888 { "muls/suc", FP(0x16,0x502), BASE, ARG_FP }, 889 { "divs/suc", FP(0x16,0x503), BASE, ARG_FP }, 890 { "addt/suc", FP(0x16,0x520), BASE, ARG_FP }, 891 { "subt/suc", FP(0x16,0x521), BASE, ARG_FP }, 892 { "mult/suc", FP(0x16,0x522), BASE, ARG_FP }, 893 { "divt/suc", FP(0x16,0x523), BASE, ARG_FP }, 894 { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 }, 895 { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 }, 896 { "adds/sum", FP(0x16,0x540), BASE, ARG_FP }, 897 { "subs/sum", FP(0x16,0x541), BASE, ARG_FP }, 898 { "muls/sum", FP(0x16,0x542), BASE, ARG_FP }, 899 { "divs/sum", FP(0x16,0x543), BASE, ARG_FP }, 900 { "addt/sum", FP(0x16,0x560), BASE, ARG_FP }, 901 { "subt/sum", FP(0x16,0x561), BASE, ARG_FP }, 902 { "mult/sum", FP(0x16,0x562), BASE, ARG_FP }, 903 { "divt/sum", FP(0x16,0x563), BASE, ARG_FP }, 904 { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 }, 905 { "cvttq/sum", FP(0x16,0x56F), BASE, ARG_FPZ1 }, 906 { "cvtqs/sum", FP(0x16,0x57C), BASE, ARG_FPZ1 }, 907 { "adds/su", FP(0x16,0x580), BASE, ARG_FP }, 908 { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */ 909 { "subs/su", FP(0x16,0x581), BASE, ARG_FP }, 910 { "muls/su", FP(0x16,0x582), BASE, ARG_FP }, 911 { "divs/su", FP(0x16,0x583), BASE, ARG_FP }, 912 { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP }, 913 { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */ 914 { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP }, 915 { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP }, 916 { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP }, 917 { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP }, 918 { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP }, 919 { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP }, 920 { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP }, 921 { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 }, 922 { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 }, 923 { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP }, 924 { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP }, 925 { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP }, 926 { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP }, 927 { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP }, 928 { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP }, 929 { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP }, 930 { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP }, 931 { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 }, 932 { "cvttq/sud", FP(0x16,0x5EF), BASE, ARG_FPZ1 }, 933 { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 }, 934 { "adds/suic", FP(0x16,0x700), BASE, ARG_FP }, 935 { "subs/suic", FP(0x16,0x701), BASE, ARG_FP }, 936 { "muls/suic", FP(0x16,0x702), BASE, ARG_FP }, 937 { "divs/suic", FP(0x16,0x703), BASE, ARG_FP }, 938 { "addt/suic", FP(0x16,0x720), BASE, ARG_FP }, 939 { "subt/suic", FP(0x16,0x721), BASE, ARG_FP }, 940 { "mult/suic", FP(0x16,0x722), BASE, ARG_FP }, 941 { "divt/suic", FP(0x16,0x723), BASE, ARG_FP }, 942 { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 }, 943 { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 }, 944 { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 }, 945 { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 }, 946 { "adds/suim", FP(0x16,0x740), BASE, ARG_FP }, 947 { "subs/suim", FP(0x16,0x741), BASE, ARG_FP }, 948 { "muls/suim", FP(0x16,0x742), BASE, ARG_FP }, 949 { "divs/suim", FP(0x16,0x743), BASE, ARG_FP }, 950 { "addt/suim", FP(0x16,0x760), BASE, ARG_FP }, 951 { "subt/suim", FP(0x16,0x761), BASE, ARG_FP }, 952 { "mult/suim", FP(0x16,0x762), BASE, ARG_FP }, 953 { "divt/suim", FP(0x16,0x763), BASE, ARG_FP }, 954 { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 }, 955 { "cvttq/suim", FP(0x16,0x76F), BASE, ARG_FPZ1 }, 956 { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 }, 957 { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 }, 958 { "adds/sui", FP(0x16,0x780), BASE, ARG_FP }, 959 { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */ 960 { "subs/sui", FP(0x16,0x781), BASE, ARG_FP }, 961 { "muls/sui", FP(0x16,0x782), BASE, ARG_FP }, 962 { "divs/sui", FP(0x16,0x783), BASE, ARG_FP }, 963 { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP }, 964 { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */ 965 { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP }, 966 { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP }, 967 { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP }, 968 { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 }, 969 { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 }, 970 { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 }, 971 { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 }, 972 { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP }, 973 { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP }, 974 { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP }, 975 { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP }, 976 { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP }, 977 { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP }, 978 { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP }, 979 { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP }, 980 { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 }, 981 { "cvttq/suid", FP(0x16,0x7EF), BASE, ARG_FPZ1 }, 982 { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 }, 983 { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 }, 984 985 { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 }, 986 { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */ 987 { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */ 988 { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */ 989 { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */ 990 { "cpys", FP(0x17,0x020), BASE, ARG_FP }, 991 { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */ 992 { "cpysn", FP(0x17,0x021), BASE, ARG_FP }, 993 { "cpyse", FP(0x17,0x022), BASE, ARG_FP }, 994 { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } }, 995 { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } }, 996 { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP }, 997 { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP }, 998 { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP }, 999 { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP }, 1000 { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP }, 1001 { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP }, 1002 { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 }, 1003 { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 }, 1004 { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 }, 1005 1006 { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE }, 1007 { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */ 1008 { "excb", MFC(0x18,0x0400), BASE, ARG_NONE }, 1009 { "mb", MFC(0x18,0x4000), BASE, ARG_NONE }, 1010 { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE }, 1011 { "fetch", MFC(0x18,0x8000), BASE, { PRB } }, 1012 { "fetch_m", MFC(0x18,0xA000), BASE, { PRB } }, 1013 { "rpcc", MFC(0x18,0xC000), BASE, { RA } }, 1014 { "rc", MFC(0x18,0xE000), BASE, { RA } }, 1015 { "ecb", MFC(0x18,0xE800), BASE, { PRB } }, /* ev56 una */ 1016 { "rs", MFC(0x18,0xF000), BASE, { RA } }, 1017 { "wh64", MFC(0x18,0xF800), BASE, { PRB } }, /* ev56 una */ 1018 1019 { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, 1020 { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, 1021 { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR }, 1022 { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR }, 1023 { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR }, 1024 { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR }, 1025 { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR }, 1026 { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR }, 1027 { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR }, 1028 { "pal19", PCD(0x19), BASE, ARG_PCD }, 1029 1030 { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } }, 1031 { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } }, 1032 { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } }, 1033 { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */ 1034 { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, 1035 1036 { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, 1037 { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, 1038 { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, 1039 { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, 1040 { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 1041 { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, 1042 { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, 1043 { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 1044 { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, 1045 { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 1046 { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, 1047 { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 1048 { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 1049 { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, 1050 { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, 1051 { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, 1052 { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, 1053 { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 1054 { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, 1055 { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, 1056 { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 1057 { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, 1058 { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 1059 { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, 1060 { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 1061 { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 1062 { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, 1063 { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, 1064 { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 1065 { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, 1066 { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 1067 { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, 1068 { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 1069 { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, 1070 { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, 1071 { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 1072 { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, 1073 { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 1074 { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, 1075 { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 1076 { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 1077 { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 1078 { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 1079 { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 1080 { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 1081 { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 1082 { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 1083 { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 1084 { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 1085 { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 1086 { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 1087 { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 1088 { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 1089 { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 1090 { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 1091 { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 1092 { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, 1093 { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, 1094 { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, 1095 { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, 1096 { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 1097 { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, 1098 { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, 1099 { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 1100 { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, 1101 { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 1102 { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, 1103 { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 1104 { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 1105 { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, 1106 { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, 1107 { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, 1108 { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, 1109 { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 1110 { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, 1111 { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, 1112 { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 1113 { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, 1114 { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 1115 { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, 1116 { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 1117 { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 1118 { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, 1119 { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, 1120 { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 1121 { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, 1122 { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 1123 { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, 1124 { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 1125 { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, 1126 { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, 1127 { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 1128 { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, 1129 { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 1130 { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, 1131 { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 1132 { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 1133 { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 1134 { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 1135 { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 1136 { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 1137 { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 1138 { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 1139 { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 1140 { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 1141 { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 1142 { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 1143 { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 1144 { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 1145 { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 1146 { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 1147 { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 1148 { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, 1149 { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, 1150 { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, 1151 { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, 1152 { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 1153 { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, 1154 { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, 1155 { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 1156 { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, 1157 { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 1158 { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, 1159 { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, 1160 { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, 1161 { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 1162 { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, 1163 { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 1164 { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, 1165 { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 1166 { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, 1167 { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 1168 { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, 1169 { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 1170 { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 1171 { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, 1172 { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, 1173 { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, 1174 { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, 1175 { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 1176 { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, 1177 { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, 1178 { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 1179 { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, 1180 { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 1181 { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, 1182 { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, 1183 { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, 1184 { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 1185 { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, 1186 { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 1187 { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, 1188 { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 1189 { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, 1190 { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 1191 { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, 1192 { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 1193 { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 1194 { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, 1195 { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, 1196 { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 1197 { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, 1198 { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 1199 { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, 1200 { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, 1201 { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, 1202 { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 1203 { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, 1204 { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 1205 { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, 1206 { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 1207 { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, 1208 { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 1209 { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, 1210 { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 1211 { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, 1212 { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, 1213 { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 1214 { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, 1215 { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 1216 { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, 1217 { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, 1218 { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, 1219 { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 1220 { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, 1221 { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 1222 { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, 1223 { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 1224 { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, 1225 { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 1226 { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, 1227 { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 1228 { "pal1b", PCD(0x1B), BASE, ARG_PCD }, 1229 1230 { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 }, 1231 { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 }, 1232 { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 }, 1233 { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR }, 1234 { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 }, 1235 { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 }, 1236 { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 }, 1237 { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 }, 1238 { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 }, 1239 { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 }, 1240 { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR }, 1241 { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL }, 1242 { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR }, 1243 { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL }, 1244 { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR }, 1245 { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL }, 1246 { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR }, 1247 { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL }, 1248 { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR }, 1249 { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL }, 1250 { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR }, 1251 { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL }, 1252 { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR }, 1253 { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL }, 1254 { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR }, 1255 { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL }, 1256 { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } }, 1257 { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } }, 1258 1259 { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, 1260 { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, 1261 { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR }, 1262 { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR }, 1263 { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR }, 1264 { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR }, 1265 { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR }, 1266 { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR }, 1267 { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR }, 1268 { "pal1d", PCD(0x1D), BASE, ARG_PCD }, 1269 1270 { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE }, 1271 { "hw_rei_stBASE", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE }, 1272 { "pal1e", PCD(0x1E), BASE, ARG_PCD }, 1273 1274 { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, 1275 { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, 1276 { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, 1277 { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, 1278 { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 1279 { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, 1280 { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, 1281 { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 1282 { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 1283 { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, 1284 { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, 1285 { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, 1286 { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, 1287 { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 1288 { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, 1289 { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 1290 { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 1291 { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, 1292 { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, 1293 { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 1294 { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, 1295 { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, 1296 { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 1297 { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 1298 { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 1299 { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 1300 { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 1301 { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 1302 { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 1303 { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 1304 { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 1305 { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, 1306 { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, 1307 { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, 1308 { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, 1309 { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 1310 { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, 1311 { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, 1312 { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 1313 { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 1314 { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, 1315 { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, 1316 { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, 1317 { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, 1318 { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 1319 { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, 1320 { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, 1321 { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, 1322 { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 1323 { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 1324 { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, 1325 { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, 1326 { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 1327 { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM }, 1328 { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, 1329 { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 1330 { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 1331 { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 1332 { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 1333 { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 1334 { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 1335 { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 1336 { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 1337 { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 1338 { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, 1339 { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, 1340 { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, 1341 { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, 1342 { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 1343 { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, 1344 { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, 1345 { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 1346 { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, 1347 { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 1348 { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, 1349 { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, 1350 { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, 1351 { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 1352 { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 1353 { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, 1354 { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, 1355 { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, 1356 { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, 1357 { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 1358 { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, 1359 { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, 1360 { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 1361 { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, 1362 { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 1363 { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, 1364 { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, 1365 { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, 1366 { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 1367 { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 1368 { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, 1369 { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, 1370 { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 1371 { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, 1372 { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 1373 { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, 1374 { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, 1375 { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, 1376 { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 1377 { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, 1378 { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, 1379 { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 1380 { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, 1381 { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 1382 { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, 1383 { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, 1384 { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 1385 { "pal1f", PCD(0x1F), BASE, ARG_PCD }, 1386 1387 { "ldf", MEM(0x20), BASE, ARG_FMEM }, 1388 { "ldg", MEM(0x21), BASE, ARG_FMEM }, 1389 { "lds", MEM(0x22), BASE, ARG_FMEM }, 1390 { "ldt", MEM(0x23), BASE, ARG_FMEM }, 1391 { "stf", MEM(0x24), BASE, ARG_FMEM }, 1392 { "stg", MEM(0x25), BASE, ARG_FMEM }, 1393 { "sts", MEM(0x26), BASE, ARG_FMEM }, 1394 { "stt", MEM(0x27), BASE, ARG_FMEM }, 1395 1396 { "ldl", MEM(0x28), BASE, ARG_MEM }, 1397 { "ldq", MEM(0x29), BASE, ARG_MEM }, 1398 { "ldl_l", MEM(0x2A), BASE, ARG_MEM }, 1399 { "ldq_l", MEM(0x2B), BASE, ARG_MEM }, 1400 { "stl", MEM(0x2C), BASE, ARG_MEM }, 1401 { "stq", MEM(0x2D), BASE, ARG_MEM }, 1402 { "stl_c", MEM(0x2E), BASE, ARG_MEM }, 1403 { "stq_c", MEM(0x2F), BASE, ARG_MEM }, 1404 1405 { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */ 1406 { "br", BRA(0x30), BASE, ARG_BRA }, 1407 { "fbeq", BRA(0x31), BASE, ARG_FBRA }, 1408 { "fblt", BRA(0x32), BASE, ARG_FBRA }, 1409 { "fble", BRA(0x33), BASE, ARG_FBRA }, 1410 { "bsr", BRA(0x34), BASE, ARG_BRA }, 1411 { "fbne", BRA(0x35), BASE, ARG_FBRA }, 1412 { "fbge", BRA(0x36), BASE, ARG_FBRA }, 1413 { "fbgt", BRA(0x37), BASE, ARG_FBRA }, 1414 { "blbc", BRA(0x38), BASE, ARG_BRA }, 1415 { "beq", BRA(0x39), BASE, ARG_BRA }, 1416 { "blt", BRA(0x3A), BASE, ARG_BRA }, 1417 { "ble", BRA(0x3B), BASE, ARG_BRA }, 1418 { "blbs", BRA(0x3C), BASE, ARG_BRA }, 1419 { "bne", BRA(0x3D), BASE, ARG_BRA }, 1420 { "bge", BRA(0x3E), BASE, ARG_BRA }, 1421 { "bgt", BRA(0x3F), BASE, ARG_BRA }, 1422}; 1423 1424const int alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes); 1425