ppc.h revision 89857
1/* ppc.h -- Header file for PowerPC opcode table 2 Copyright 1994, 1995, 1999, 2000, 2001 Free Software Foundation, Inc. 3 Written by Ian Lance Taylor, Cygnus Support 4 5This file is part of GDB, GAS, and the GNU binutils. 6 7GDB, GAS, and the GNU binutils are free software; you can redistribute 8them and/or modify them under the terms of the GNU General Public 9License as published by the Free Software Foundation; either version 101, or (at your option) any later version. 11 12GDB, GAS, and the GNU binutils are distributed in the hope that they 13will be useful, but WITHOUT ANY WARRANTY; without even the implied 14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15the GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with this file; see the file COPYING. If not, write to the Free 19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 20 21#ifndef PPC_H 22#define PPC_H 23 24/* The opcode table is an array of struct powerpc_opcode. */ 25 26struct powerpc_opcode 27{ 28 /* The opcode name. */ 29 const char *name; 30 31 /* The opcode itself. Those bits which will be filled in with 32 operands are zeroes. */ 33 unsigned long opcode; 34 35 /* The opcode mask. This is used by the disassembler. This is a 36 mask containing ones indicating those bits which must match the 37 opcode field, and zeroes indicating those bits which need not 38 match (and are presumably filled in by operands). */ 39 unsigned long mask; 40 41 /* One bit flags for the opcode. These are used to indicate which 42 specific processors support the instructions. The defined values 43 are listed below. */ 44 unsigned long flags; 45 46 /* An array of operand codes. Each code is an index into the 47 operand table. They appear in the order which the operands must 48 appear in assembly code, and are terminated by a zero. */ 49 unsigned char operands[8]; 50}; 51 52/* The table itself is sorted by major opcode number, and is otherwise 53 in the order in which the disassembler should consider 54 instructions. */ 55extern const struct powerpc_opcode powerpc_opcodes[]; 56extern const int powerpc_num_opcodes; 57 58/* Values defined for the flags field of a struct powerpc_opcode. */ 59 60/* Opcode is defined for the PowerPC architecture. */ 61#define PPC_OPCODE_PPC (01) 62 63/* Opcode is defined for the POWER (RS/6000) architecture. */ 64#define PPC_OPCODE_POWER (02) 65 66/* Opcode is defined for the POWER2 (Rios 2) architecture. */ 67#define PPC_OPCODE_POWER2 (04) 68 69/* Opcode is only defined on 32 bit architectures. */ 70#define PPC_OPCODE_32 (010) 71 72/* Opcode is only defined on 64 bit architectures. */ 73#define PPC_OPCODE_64 (020) 74 75/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 76 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 77 but it also supports many additional POWER instructions. */ 78#define PPC_OPCODE_601 (040) 79 80/* Opcode is supported in both the Power and PowerPC architectures 81 (ie, compiler's -mcpu=common or assembler's -mcom). */ 82#define PPC_OPCODE_COMMON (0100) 83 84/* Opcode is supported for any Power or PowerPC platform (this is 85 for the assembler's -many option, and it eliminates duplicates). */ 86#define PPC_OPCODE_ANY (0200) 87 88/* Opcode is supported as part of the 64-bit bridge. */ 89#define PPC_OPCODE_64_BRIDGE (0400) 90 91/* Opcode is supported by Altivec Vector Unit */ 92#define PPC_OPCODE_ALTIVEC (01000) 93 94/* Opcode is supported by PowerPC 403 processor. */ 95#define PPC_OPCODE_403 (02000) 96 97/* Opcode is supported by PowerPC BookE processor. */ 98#define PPC_OPCODE_BOOKE (04000) 99 100/* Opcode is only supported by 64-bit PowerPC BookE processor. */ 101#define PPC_OPCODE_BOOKE64 (010000) 102 103/* A macro to extract the major opcode from an instruction. */ 104#define PPC_OP(i) (((i) >> 26) & 0x3f) 105 106/* The operands table is an array of struct powerpc_operand. */ 107 108struct powerpc_operand 109{ 110 /* The number of bits in the operand. */ 111 int bits; 112 113 /* How far the operand is left shifted in the instruction. */ 114 int shift; 115 116 /* Insertion function. This is used by the assembler. To insert an 117 operand value into an instruction, check this field. 118 119 If it is NULL, execute 120 i |= (op & ((1 << o->bits) - 1)) << o->shift; 121 (i is the instruction which we are filling in, o is a pointer to 122 this structure, and op is the opcode value; this assumes twos 123 complement arithmetic). 124 125 If this field is not NULL, then simply call it with the 126 instruction and the operand value. It will return the new value 127 of the instruction. If the ERRMSG argument is not NULL, then if 128 the operand value is illegal, *ERRMSG will be set to a warning 129 string (the operand will be inserted in any case). If the 130 operand value is legal, *ERRMSG will be unchanged (most operands 131 can accept any value). */ 132 unsigned long (*insert) PARAMS ((unsigned long instruction, long op, 133 int dialect, 134 const char **errmsg)); 135 136 /* Extraction function. This is used by the disassembler. To 137 extract this operand type from an instruction, check this field. 138 139 If it is NULL, compute 140 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 141 if ((o->flags & PPC_OPERAND_SIGNED) != 0 142 && (op & (1 << (o->bits - 1))) != 0) 143 op -= 1 << o->bits; 144 (i is the instruction, o is a pointer to this structure, and op 145 is the result; this assumes twos complement arithmetic). 146 147 If this field is not NULL, then simply call it with the 148 instruction value. It will return the value of the operand. If 149 the INVALID argument is not NULL, *INVALID will be set to 150 non-zero if this operand type can not actually be extracted from 151 this operand (i.e., the instruction does not match). If the 152 operand is valid, *INVALID will not be changed. */ 153 long (*extract) PARAMS ((unsigned long instruction, int dialect, 154 int *invalid)); 155 156 /* One bit syntax flags. */ 157 unsigned long flags; 158}; 159 160/* Elements in the table are retrieved by indexing with values from 161 the operands field of the powerpc_opcodes table. */ 162 163extern const struct powerpc_operand powerpc_operands[]; 164 165/* Values defined for the flags field of a struct powerpc_operand. */ 166 167/* This operand takes signed values. */ 168#define PPC_OPERAND_SIGNED (01) 169 170/* This operand takes signed values, but also accepts a full positive 171 range of values when running in 32 bit mode. That is, if bits is 172 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 173 this flag is ignored. */ 174#define PPC_OPERAND_SIGNOPT (02) 175 176/* This operand does not actually exist in the assembler input. This 177 is used to support extended mnemonics such as mr, for which two 178 operands fields are identical. The assembler should call the 179 insert function with any op value. The disassembler should call 180 the extract function, ignore the return value, and check the value 181 placed in the valid argument. */ 182#define PPC_OPERAND_FAKE (04) 183 184/* The next operand should be wrapped in parentheses rather than 185 separated from this one by a comma. This is used for the load and 186 store instructions which want their operands to look like 187 reg,displacement(reg) 188 */ 189#define PPC_OPERAND_PARENS (010) 190 191/* This operand may use the symbolic names for the CR fields, which 192 are 193 lt 0 gt 1 eq 2 so 3 un 3 194 cr0 0 cr1 1 cr2 2 cr3 3 195 cr4 4 cr5 5 cr6 6 cr7 7 196 These may be combined arithmetically, as in cr2*4+gt. These are 197 only supported on the PowerPC, not the POWER. */ 198#define PPC_OPERAND_CR (020) 199 200/* This operand names a register. The disassembler uses this to print 201 register names with a leading 'r'. */ 202#define PPC_OPERAND_GPR (040) 203 204/* This operand names a floating point register. The disassembler 205 prints these with a leading 'f'. */ 206#define PPC_OPERAND_FPR (0100) 207 208/* This operand is a relative branch displacement. The disassembler 209 prints these symbolically if possible. */ 210#define PPC_OPERAND_RELATIVE (0200) 211 212/* This operand is an absolute branch address. The disassembler 213 prints these symbolically if possible. */ 214#define PPC_OPERAND_ABSOLUTE (0400) 215 216/* This operand is optional, and is zero if omitted. This is used for 217 the optional BF and L fields in the comparison instructions. The 218 assembler must count the number of operands remaining on the line, 219 and the number of operands remaining for the opcode, and decide 220 whether this operand is present or not. The disassembler should 221 print this operand out only if it is not zero. */ 222#define PPC_OPERAND_OPTIONAL (01000) 223 224/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 225 is omitted, then for the next operand use this operand value plus 226 1, ignoring the next operand field for the opcode. This wretched 227 hack is needed because the Power rotate instructions can take 228 either 4 or 5 operands. The disassembler should print this operand 229 out regardless of the PPC_OPERAND_OPTIONAL field. */ 230#define PPC_OPERAND_NEXT (02000) 231 232/* This operand should be regarded as a negative number for the 233 purposes of overflow checking (i.e., the normal most negative 234 number is disallowed and one more than the normal most positive 235 number is allowed). This flag will only be set for a signed 236 operand. */ 237#define PPC_OPERAND_NEGATIVE (04000) 238 239/* This operand names a vector unit register. The disassembler 240 prints these with a leading 'v'. */ 241#define PPC_OPERAND_VR (010000) 242 243/* This operand is for the DS field in a DS form instruction. */ 244#define PPC_OPERAND_DS (020000) 245 246/* The POWER and PowerPC assemblers use a few macros. We keep them 247 with the operands table for simplicity. The macro table is an 248 array of struct powerpc_macro. */ 249 250struct powerpc_macro 251{ 252 /* The macro name. */ 253 const char *name; 254 255 /* The number of operands the macro takes. */ 256 unsigned int operands; 257 258 /* One bit flags for the opcode. These are used to indicate which 259 specific processors support the instructions. The values are the 260 same as those for the struct powerpc_opcode flags field. */ 261 unsigned long flags; 262 263 /* A format string to turn the macro into a normal instruction. 264 Each %N in the string is replaced with operand number N (zero 265 based). */ 266 const char *format; 267}; 268 269extern const struct powerpc_macro powerpc_macros[]; 270extern const int powerpc_num_macros; 271 272#endif /* PPC_H */ 273