c-mips.texi revision 179404
1@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, 2@c 2002, 2003, 2004 3@c Free Software Foundation, Inc. 4@c This is part of the GAS manual. 5@c For copying conditions, see the file as.texinfo. 6@ifset GENERIC 7@page 8@node MIPS-Dependent 9@chapter MIPS Dependent Features 10@end ifset 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter MIPS Dependent Features 14@end ifclear 15 16@cindex MIPS processor 17@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several 18different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, 19and MIPS64. For information about the @sc{mips} instruction set, see 20@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). 21For an overview of @sc{mips} assembly conventions, see ``Appendix D: 22Assembly Language Programming'' in the same work. 23 24@menu 25* MIPS Opts:: Assembler options 26* MIPS Object:: ECOFF object code 27* MIPS Stabs:: Directives for debugging information 28* MIPS ISA:: Directives to override the ISA level 29* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 30* MIPS insn:: Directive to mark data as an instruction 31* MIPS option stack:: Directives to save and restore options 32* MIPS ASE instruction generation overrides:: Directives to control 33 generation of MIPS ASE instructions 34@end menu 35 36@node MIPS Opts 37@section Assembler options 38 39The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these 40special options: 41 42@table @code 43@cindex @code{-G} option (MIPS) 44@item -G @var{num} 45This option sets the largest size of an object that can be referenced 46implicitly with the @code{gp} register. It is only accepted for targets 47that use @sc{ecoff} format. The default value is 8. 48 49@cindex @code{-EB} option (MIPS) 50@cindex @code{-EL} option (MIPS) 51@cindex MIPS big-endian output 52@cindex MIPS little-endian output 53@cindex big-endian output, MIPS 54@cindex little-endian output, MIPS 55@item -EB 56@itemx -EL 57Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or 58little-endian output at run time (unlike the other @sc{gnu} development 59tools, which must be configured for one or the other). Use @samp{-EB} 60to select big-endian output, and @samp{-EL} for little-endian. 61 62@cindex MIPS architecture options 63@item -mips1 64@itemx -mips2 65@itemx -mips3 66@itemx -mips4 67@itemx -mips5 68@itemx -mips32 69@itemx -mips32r2 70@itemx -mips64 71@itemx -mips64r2 72Generate code for a particular MIPS Instruction Set Architecture level. 73@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, 74@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the 75@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and 76@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, 77@samp{-mips64}, and @samp{-mips64r2} 78correspond to generic 79@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, 80and @sc{MIPS64 Release 2} 81ISA processors, respectively. You can also switch 82instruction sets during the assembly; see @ref{MIPS ISA, Directives to 83override the ISA level}. 84 85@item -mgp32 86@itemx -mfp32 87Some macros have different expansions for 32-bit and 64-bit registers. 88The register sizes are normally inferred from the ISA and ABI, but these 89flags force a certain group of registers to be treated as 32 bits wide at 90all times. @samp{-mgp32} controls the size of general-purpose registers 91and @samp{-mfp32} controls the size of floating-point registers. 92 93On some MIPS variants there is a 32-bit mode flag; when this flag is 94set, 64-bit instructions generate a trap. Also, some 32-bit OSes only 95save the 32-bit registers on a context switch, so it is essential never 96to use the 64-bit registers. 97 98@item -mgp64 99Assume that 64-bit general purpose registers are available. This is 100provided in the interests of symmetry with -gp32. 101 102@item -mips16 103@itemx -no-mips16 104Generate code for the MIPS 16 processor. This is equivalent to putting 105@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16} 106turns off this option. 107 108@item -mips3d 109@itemx -no-mips3d 110Generate code for the MIPS-3D Application Specific Extension. 111This tells the assembler to accept MIPS-3D instructions. 112@samp{-no-mips3d} turns off this option. 113 114@item -mdmx 115@itemx -no-mdmx 116Generate code for the MDMX Application Specific Extension. 117This tells the assembler to accept MDMX instructions. 118@samp{-no-mdmx} turns off this option. 119 120@item -mfix7000 121@itemx -mno-fix7000 122Cause nops to be inserted if the read of the destination register 123of an mfhi or mflo instruction occurs in the following two instructions. 124 125@item -mfix-vr4120 126@itemx -no-mfix-vr4120 127Insert nops to work around certain VR4120 errata. This option is 128intended to be used on GCC-generated code: it is not designed to catch 129all problems in hand-written assembler code. 130 131@item -m4010 132@itemx -no-m4010 133Generate code for the LSI @sc{r4010} chip. This tells the assembler to 134accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, 135etc.), and to not schedule @samp{nop} instructions around accesses to 136the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this 137option. 138 139@item -m4650 140@itemx -no-m4650 141Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept 142the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} 143instructions around accesses to the @samp{HI} and @samp{LO} registers. 144@samp{-no-m4650} turns off this option. 145 146@itemx -m3900 147@itemx -no-m3900 148@itemx -m4100 149@itemx -no-m4100 150For each option @samp{-m@var{nnnn}}, generate code for the MIPS 151@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions 152specific to that chip, and to schedule for that chip's hazards. 153 154@item -march=@var{cpu} 155Generate code for a particular MIPS cpu. It is exactly equivalent to 156@samp{-m@var{cpu}}, except that there are more value of @var{cpu} 157understood. Valid @var{cpu} value are: 158 159@quotation 1602000, 1613000, 1623900, 1634000, 1644010, 1654100, 1664111, 167vr4120, 168vr4130, 169vr4181, 1704300, 1714400, 1724600, 1734650, 1745000, 175rm5200, 176rm5230, 177rm5231, 178rm5261, 179rm5721, 180vr5400, 181vr5500, 1826000, 183rm7000, 1848000, 185rm9000, 18610000, 18712000, 188mips32-4k, 189sb1 190@end quotation 191 192@item -mtune=@var{cpu} 193Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are 194identical to @samp{-march=@var{cpu}}. 195 196@item -mabi=@var{abi} 197Record which ABI the source code uses. The recognized arguments 198are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. 199 200@cindex @code{-nocpp} ignored (MIPS) 201@item -nocpp 202This option is ignored. It is accepted for command-line compatibility with 203other assemblers, which use it to turn off C style preprocessing. With 204@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the 205@sc{gnu} assembler itself never runs the C preprocessor. 206 207@item --construct-floats 208@itemx --no-construct-floats 209@cindex --construct-floats 210@cindex --no-construct-floats 211The @code{--no-construct-floats} option disables the construction of 212double width floating point constants by loading the two halves of the 213value into the two single width floating point registers that make up 214the double width register. This feature is useful if the processor 215support the FR bit in its status register, and this bit is known (by 216the programmer) to be set. This bit prevents the aliasing of the double 217width register by the single width registers. 218 219By default @code{--construct-floats} is selected, allowing construction 220of these floating point constants. 221 222@item --trap 223@itemx --no-break 224@c FIXME! (1) reflect these options (next item too) in option summaries; 225@c (2) stop teasing, say _which_ instructions expanded _how_. 226@code{@value{AS}} automatically macro expands certain division and 227multiplication instructions to check for overflow and division by zero. This 228option causes @code{@value{AS}} to generate code to take a trap exception 229rather than a break exception when an error is detected. The trap instructions 230are only supported at Instruction Set Architecture level 2 and higher. 231 232@item --break 233@itemx --no-trap 234Generate code to take a break exception rather than a trap exception when an 235error is detected. This is the default. 236 237@item -mpdr 238@itemx -mno-pdr 239Control generation of @code{.pdr} sections. Off by default on IRIX, on 240elsewhere. 241@end table 242 243@node MIPS Object 244@section MIPS ECOFF object code 245 246@cindex ECOFF sections 247@cindex MIPS ECOFF sections 248Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections 249besides the usual @code{.text}, @code{.data} and @code{.bss}. The 250additional sections are @code{.rdata}, used for read-only data, 251@code{.sdata}, used for small data, and @code{.sbss}, used for small 252common objects. 253 254@cindex small objects, MIPS ECOFF 255@cindex @code{gp} register, MIPS 256When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) 257register to form the address of a ``small object''. Any object in the 258@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. 259For external objects, or for objects in the @code{.bss} section, you can use 260the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via 261@code{$gp}; the default value is 8, meaning that a reference to any object 262eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to 263@code{@value{AS}} prevents it from using the @code{$gp} register on the basis 264of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} 265or @code{sbss} in any case). The size of an object in the @code{.bss} section 266is set by the @code{.comm} or @code{.lcomm} directive that defines it. The 267size of an external object may be set with the @code{.extern} directive. For 268example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes 269in length, whie leaving @code{sym} otherwise undefined. 270 271Using small @sc{ecoff} objects requires linker support, and assumes that the 272@code{$gp} register is correctly initialized (normally done automatically by 273the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the 274@code{$gp} register. 275 276@node MIPS Stabs 277@section Directives for debugging information 278 279@cindex MIPS debugging directives 280@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for 281generating debugging information which are not support by traditional @sc{mips} 282assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, 283@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, 284@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information 285generated by the three @code{.stab} directives can only be read by @sc{gdb}, 286not by traditional @sc{mips} debuggers (this enhancement is required to fully 287support C++ debugging). These directives are primarily used by compilers, not 288assembly language programmers! 289 290@node MIPS ISA 291@section Directives to override the ISA level 292 293@cindex MIPS ISA override 294@kindex @code{.set mips@var{n}} 295@sc{gnu} @code{@value{AS}} supports an additional directive to change 296the @sc{mips} Instruction Set Architecture level on the fly: @code{.set 297mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 298or 64r2. 299The values other than 0 make the assembler accept instructions 300for the corresponding @sc{isa} level, from that point on in the 301assembly. @code{.set mips@var{n}} affects not only which instructions 302are permitted, but also how certain macros are expanded. @code{.set 303mips0} restores the @sc{isa} level to its original level: either the 304level you selected with command line options, or the default for your 305configuration. You can use this feature to permit specific @sc{r4000} 306instructions while assembling in 32 bit mode. Use this directive with 307care! 308 309The directive @samp{.set mips16} puts the assembler into MIPS 16 mode, 310in which it will assemble instructions for the MIPS 16 processor. Use 311@samp{.set nomips16} to return to normal 32 bit mode. 312 313Traditional @sc{mips} assemblers do not support this directive. 314 315@node MIPS autoextend 316@section Directives for extending MIPS 16 bit instructions 317 318@kindex @code{.set autoextend} 319@kindex @code{.set noautoextend} 320By default, MIPS 16 instructions are automatically extended to 32 bits 321when necessary. The directive @samp{.set noautoextend} will turn this 322off. When @samp{.set noautoextend} is in effect, any 32 bit instruction 323must be explicitly extended with the @samp{.e} modifier (e.g., 324@samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used 325to once again automatically extend instructions when necessary. 326 327This directive is only meaningful when in MIPS 16 mode. Traditional 328@sc{mips} assemblers do not support this directive. 329 330@node MIPS insn 331@section Directive to mark data as an instruction 332 333@kindex @code{.insn} 334The @code{.insn} directive tells @code{@value{AS}} that the following 335data is actually instructions. This makes a difference in MIPS 16 mode: 336when loading the address of a label which precedes instructions, 337@code{@value{AS}} automatically adds 1 to the value, so that jumping to 338the loaded address will do the right thing. 339 340@node MIPS option stack 341@section Directives to save and restore options 342 343@cindex MIPS option stack 344@kindex @code{.set push} 345@kindex @code{.set pop} 346The directives @code{.set push} and @code{.set pop} may be used to save 347and restore the current settings for all the options which are 348controlled by @code{.set}. The @code{.set push} directive saves the 349current settings on a stack. The @code{.set pop} directive pops the 350stack and restores the settings. 351 352These directives can be useful inside an macro which must change an 353option such as the ISA level or instruction reordering but does not want 354to change the state of the code which invoked the macro. 355 356Traditional @sc{mips} assemblers do not support these directives. 357 358@node MIPS ASE instruction generation overrides 359@section Directives to control generation of MIPS ASE instructions 360 361@cindex MIPS MIPS-3D instruction generation override 362@kindex @code{.set mips3d} 363@kindex @code{.set nomips3d} 364The directive @code{.set mips3d} makes the assembler accept instructions 365from the MIPS-3D Application Specific Extension from that point on 366in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D 367instructions from being accepted. 368 369@cindex MIPS MDMX instruction generation override 370@kindex @code{.set mdmx} 371@kindex @code{.set nomdmx} 372The directive @code{.set mdmx} makes the assembler accept instructions 373from the MDMX Application Specific Extension from that point on 374in the assembly. The @code{.set nomdmx} directive prevents MDMX 375instructions from being accepted. 376 377Traditional @sc{mips} assemblers do not support these directives. 378