tc-arm.c revision 275584 
1/* tc-arm.c -- Assemble for the ARM
2   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3   2004, 2005, 2006
4   Free Software Foundation, Inc.
5   Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6	Modified by David Taylor (dtaylor@armltd.co.uk)
7	Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8	Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9	Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
10
11   This file is part of GAS, the GNU Assembler.
12
13   GAS is free software; you can redistribute it and/or modify
14   it under the terms of the GNU General Public License as published by
15   the Free Software Foundation; either version 2, or (at your option)
16   any later version.
17
18   GAS is distributed in the hope that it will be useful,
19   but WITHOUT ANY WARRANTY; without even the implied warranty of
20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
21   GNU General Public License for more details.
22
23   You should have received a copy of the GNU General Public License
24   along with GAS; see the file COPYING.  If not, write to the Free
25   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26   02110-1301, USA.  */
27
28#include <limits.h>
29#include <stdarg.h>
30#define	 NO_RELOC 0
31#include "as.h"
32#include "safe-ctype.h"
33#include "subsegs.h"
34#include "obstack.h"
35
36#include "opcode/arm.h"
37
38#ifdef OBJ_ELF
39#include "elf/arm.h"
40#include "dw2gencfi.h"
41#endif
42
43#include "dwarf2dbg.h"
44
45#define WARN_DEPRECATED 1
46
47#ifdef OBJ_ELF
48/* Must be at least the size of the largest unwind opcode (currently two).  */
49#define ARM_OPCODE_CHUNK_SIZE 8
50
51/* This structure holds the unwinding state.  */
52
53static struct
54{
55  symbolS *	  proc_start;
56  symbolS *	  table_entry;
57  symbolS *	  personality_routine;
58  int		  personality_index;
59  /* The segment containing the function.  */
60  segT		  saved_seg;
61  subsegT	  saved_subseg;
62  /* Opcodes generated from this function.  */
63  unsigned char * opcodes;
64  int		  opcode_count;
65  int		  opcode_alloc;
66  /* The number of bytes pushed to the stack.  */
67  offsetT	  frame_size;
68  /* We don't add stack adjustment opcodes immediately so that we can merge
69     multiple adjustments.  We can also omit the final adjustment
70     when using a frame pointer.  */
71  offsetT	  pending_offset;
72  /* These two fields are set by both unwind_movsp and unwind_setfp.  They
73     hold the reg+offset to use when restoring sp from a frame pointer.	 */
74  offsetT	  fp_offset;
75  int		  fp_reg;
76  /* Nonzero if an unwind_setfp directive has been seen.  */
77  unsigned	  fp_used:1;
78  /* Nonzero if the last opcode restores sp from fp_reg.  */
79  unsigned	  sp_restored:1;
80} unwind;
81
82/* Bit N indicates that an R_ARM_NONE relocation has been output for
83   __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84   emitted only once per section, to save unnecessary bloat.  */
85static unsigned int marked_pr_dependency = 0;
86
87#endif /* OBJ_ELF */
88
89/* Results from operand parsing worker functions.  */
90
91typedef enum
92{
93  PARSE_OPERAND_SUCCESS,
94  PARSE_OPERAND_FAIL,
95  PARSE_OPERAND_FAIL_NO_BACKTRACK
96} parse_operand_result;
97
98enum arm_float_abi
99{
100  ARM_FLOAT_ABI_HARD,
101  ARM_FLOAT_ABI_SOFTFP,
102  ARM_FLOAT_ABI_SOFT
103};
104
105/* Types of processor to assemble for.	*/
106#ifndef CPU_DEFAULT
107#if defined __XSCALE__
108#define CPU_DEFAULT	ARM_ARCH_XSCALE
109#else
110#if defined __thumb__
111#define CPU_DEFAULT	ARM_ARCH_V5T
112#endif
113#endif
114#endif
115
116#ifndef FPU_DEFAULT
117# ifdef TE_LINUX
118#  define FPU_DEFAULT FPU_ARCH_FPA
119# elif defined (TE_NetBSD)
120#  ifdef OBJ_ELF
121#   define FPU_DEFAULT FPU_ARCH_VFP	/* Soft-float, but VFP order.  */
122#  else
123    /* Legacy a.out format.  */
124#   define FPU_DEFAULT FPU_ARCH_FPA	/* Soft-float, but FPA order.  */
125#  endif
126# elif defined (TE_VXWORKS)
127#  define FPU_DEFAULT FPU_ARCH_VFP	/* Soft-float, VFP order.  */
128# else
129   /* For backwards compatibility, default to FPA.  */
130#  define FPU_DEFAULT FPU_ARCH_FPA
131# endif
132#endif /* ifndef FPU_DEFAULT */
133
134#define streq(a, b)	      (strcmp (a, b) == 0)
135
136static arm_feature_set cpu_variant;
137static arm_feature_set arm_arch_used;
138static arm_feature_set thumb_arch_used;
139
140/* Flags stored in private area of BFD structure.  */
141static int uses_apcs_26	     = FALSE;
142static int atpcs	     = FALSE;
143static int support_interwork = FALSE;
144static int uses_apcs_float   = FALSE;
145static int pic_code	     = FALSE;
146
147/* Variables that we set while parsing command-line options.  Once all
148   options have been read we re-process these values to set the real
149   assembly flags.  */
150static const arm_feature_set *legacy_cpu = NULL;
151static const arm_feature_set *legacy_fpu = NULL;
152
153static const arm_feature_set *mcpu_cpu_opt = NULL;
154static const arm_feature_set *mcpu_fpu_opt = NULL;
155static const arm_feature_set *march_cpu_opt = NULL;
156static const arm_feature_set *march_fpu_opt = NULL;
157static const arm_feature_set *mfpu_opt = NULL;
158static const arm_feature_set *object_arch = NULL;
159
160/* Constants for known architecture features.  */
161static const arm_feature_set fpu_default = FPU_DEFAULT;
162static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
163static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
164static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
165static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
166static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
167static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
168static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
169static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
170
171#ifdef CPU_DEFAULT
172static const arm_feature_set cpu_default = CPU_DEFAULT;
173#endif
174
175static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
176static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
177static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
178static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
179static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
180static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
181static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
182static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
183static const arm_feature_set arm_ext_v4t_5 =
184  ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
185static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
186static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
187static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
188static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
189static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
190static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
191static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
192static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
193static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
194static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
195static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
196static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
197static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
198static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
199
200static const arm_feature_set arm_arch_any = ARM_ANY;
201static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
202static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
203static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
204
205static const arm_feature_set arm_cext_iwmmxt2 =
206  ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
207static const arm_feature_set arm_cext_iwmmxt =
208  ARM_FEATURE (0, ARM_CEXT_IWMMXT);
209static const arm_feature_set arm_cext_xscale =
210  ARM_FEATURE (0, ARM_CEXT_XSCALE);
211static const arm_feature_set arm_cext_maverick =
212  ARM_FEATURE (0, ARM_CEXT_MAVERICK);
213static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
214static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
215static const arm_feature_set fpu_vfp_ext_v1xd =
216  ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
217static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
218static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
219static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
220static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
221static const arm_feature_set fpu_vfp_v3_or_neon_ext =
222  ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
223
224static int mfloat_abi_opt = -1;
225/* Record user cpu selection for object attributes.  */
226static arm_feature_set selected_cpu = ARM_ARCH_NONE;
227/* Must be long enough to hold any of the names in arm_cpus.  */
228static char selected_cpu_name[16];
229#ifdef OBJ_ELF
230# ifdef EABI_DEFAULT
231static int meabi_flags = EABI_DEFAULT;
232# else
233static int meabi_flags = EF_ARM_EABI_UNKNOWN;
234# endif
235
236bfd_boolean
237arm_is_eabi(void)
238{
239  return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
240}
241#endif
242
243#ifdef OBJ_ELF
244/* Pre-defined "_GLOBAL_OFFSET_TABLE_"	*/
245symbolS * GOT_symbol;
246#endif
247
248/* 0: assemble for ARM,
249   1: assemble for Thumb,
250   2: assemble for Thumb even though target CPU does not support thumb
251      instructions.  */
252static int thumb_mode = 0;
253
254/* If unified_syntax is true, we are processing the new unified
255   ARM/Thumb syntax.  Important differences from the old ARM mode:
256
257     - Immediate operands do not require a # prefix.
258     - Conditional affixes always appear at the end of the
259       instruction.  (For backward compatibility, those instructions
260       that formerly had them in the middle, continue to accept them
261       there.)
262     - The IT instruction may appear, and if it does is validated
263       against subsequent conditional affixes.  It does not generate
264       machine code.
265
266   Important differences from the old Thumb mode:
267
268     - Immediate operands do not require a # prefix.
269     - Most of the V6T2 instructions are only available in unified mode.
270     - The .N and .W suffixes are recognized and honored (it is an error
271       if they cannot be honored).
272     - All instructions set the flags if and only if they have an 's' affix.
273     - Conditional affixes may be used.  They are validated against
274       preceding IT instructions.  Unlike ARM mode, you cannot use a
275       conditional affix except in the scope of an IT instruction.  */
276
277static bfd_boolean unified_syntax = FALSE;
278
279enum neon_el_type
280{
281  NT_invtype,
282  NT_untyped,
283  NT_integer,
284  NT_float,
285  NT_poly,
286  NT_signed,
287  NT_unsigned
288};
289
290struct neon_type_el
291{
292  enum neon_el_type type;
293  unsigned size;
294};
295
296#define NEON_MAX_TYPE_ELS 4
297
298struct neon_type
299{
300  struct neon_type_el el[NEON_MAX_TYPE_ELS];
301  unsigned elems;
302};
303
304struct arm_it
305{
306  const char *	error;
307  unsigned long instruction;
308  int		size;
309  int		size_req;
310  int		cond;
311  /* "uncond_value" is set to the value in place of the conditional field in
312     unconditional versions of the instruction, or -1 if nothing is
313     appropriate.  */
314  int		uncond_value;
315  struct neon_type vectype;
316  /* Set to the opcode if the instruction needs relaxation.
317     Zero if the instruction is not relaxed.  */
318  unsigned long	relax;
319  struct
320  {
321    bfd_reloc_code_real_type type;
322    expressionS		     exp;
323    int			     pc_rel;
324  } reloc;
325
326  struct
327  {
328    unsigned reg;
329    signed int imm;
330    struct neon_type_el vectype;
331    unsigned present	: 1;  /* Operand present.  */
332    unsigned isreg	: 1;  /* Operand was a register.  */
333    unsigned immisreg	: 1;  /* .imm field is a second register.  */
334    unsigned isscalar   : 1;  /* Operand is a (Neon) scalar.  */
335    unsigned immisalign : 1;  /* Immediate is an alignment specifier.  */
336    unsigned immisfloat : 1;  /* Immediate was parsed as a float.  */
337    /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
338       instructions. This allows us to disambiguate ARM <-> vector insns.  */
339    unsigned regisimm   : 1;  /* 64-bit immediate, reg forms high 32 bits.  */
340    unsigned isvec      : 1;  /* Is a single, double or quad VFP/Neon reg.  */
341    unsigned isquad     : 1;  /* Operand is Neon quad-precision register.  */
342    unsigned issingle   : 1;  /* Operand is VFP single-precision register.  */
343    unsigned hasreloc	: 1;  /* Operand has relocation suffix.  */
344    unsigned writeback	: 1;  /* Operand has trailing !  */
345    unsigned preind	: 1;  /* Preindexed address.  */
346    unsigned postind	: 1;  /* Postindexed address.  */
347    unsigned negative	: 1;  /* Index register was negated.  */
348    unsigned shifted	: 1;  /* Shift applied to operation.  */
349    unsigned shift_kind : 3;  /* Shift operation (enum shift_kind).  */
350  } operands[6];
351};
352
353static struct arm_it inst;
354
355#define NUM_FLOAT_VALS 8
356
357const char * fp_const[] =
358{
359  "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
360};
361
362/* Number of littlenums required to hold an extended precision number.	*/
363#define MAX_LITTLENUMS 6
364
365LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
366
367#define FAIL	(-1)
368#define SUCCESS (0)
369
370#define SUFF_S 1
371#define SUFF_D 2
372#define SUFF_E 3
373#define SUFF_P 4
374
375#define CP_T_X	 0x00008000
376#define CP_T_Y	 0x00400000
377
378#define CONDS_BIT	 0x00100000
379#define LOAD_BIT	 0x00100000
380
381#define DOUBLE_LOAD_FLAG 0x00000001
382
383struct asm_cond
384{
385  const char *	template;
386  unsigned long value;
387};
388
389#define COND_ALWAYS 0xE
390
391struct asm_psr
392{
393  const char *template;
394  unsigned long field;
395};
396
397struct asm_barrier_opt
398{
399  const char *template;
400  unsigned long value;
401};
402
403/* The bit that distinguishes CPSR and SPSR.  */
404#define SPSR_BIT   (1 << 22)
405
406/* The individual PSR flag bits.  */
407#define PSR_c	(1 << 16)
408#define PSR_x	(1 << 17)
409#define PSR_s	(1 << 18)
410#define PSR_f	(1 << 19)
411
412struct reloc_entry
413{
414  char *name;
415  bfd_reloc_code_real_type reloc;
416};
417
418enum vfp_reg_pos
419{
420  VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
421  VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
422};
423
424enum vfp_ldstm_type
425{
426  VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
427};
428
429/* Bits for DEFINED field in neon_typed_alias.  */
430#define NTA_HASTYPE  1
431#define NTA_HASINDEX 2
432
433struct neon_typed_alias
434{
435  unsigned char defined;
436  unsigned char index;
437  struct neon_type_el eltype;
438};
439
440/* ARM register categories.  This includes coprocessor numbers and various
441   architecture extensions' registers.	*/
442enum arm_reg_type
443{
444  REG_TYPE_RN,
445  REG_TYPE_CP,
446  REG_TYPE_CN,
447  REG_TYPE_FN,
448  REG_TYPE_VFS,
449  REG_TYPE_VFD,
450  REG_TYPE_NQ,
451  REG_TYPE_VFSD,
452  REG_TYPE_NDQ,
453  REG_TYPE_NSDQ,
454  REG_TYPE_VFC,
455  REG_TYPE_MVF,
456  REG_TYPE_MVD,
457  REG_TYPE_MVFX,
458  REG_TYPE_MVDX,
459  REG_TYPE_MVAX,
460  REG_TYPE_DSPSC,
461  REG_TYPE_MMXWR,
462  REG_TYPE_MMXWC,
463  REG_TYPE_MMXWCG,
464  REG_TYPE_XSCALE,
465};
466
467/* Structure for a hash table entry for a register.
468   If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
469   information which states whether a vector type or index is specified (for a
470   register alias created with .dn or .qn). Otherwise NEON should be NULL.  */
471struct reg_entry
472{
473  const char        *name;
474  unsigned char      number;
475  unsigned char      type;
476  unsigned char      builtin;
477  struct neon_typed_alias *neon;
478};
479
480/* Diagnostics used when we don't get a register of the expected type.	*/
481const char *const reg_expected_msgs[] =
482{
483  N_("ARM register expected"),
484  N_("bad or missing co-processor number"),
485  N_("co-processor register expected"),
486  N_("FPA register expected"),
487  N_("VFP single precision register expected"),
488  N_("VFP/Neon double precision register expected"),
489  N_("Neon quad precision register expected"),
490  N_("VFP single or double precision register expected"),
491  N_("Neon double or quad precision register expected"),
492  N_("VFP single, double or Neon quad precision register expected"),
493  N_("VFP system register expected"),
494  N_("Maverick MVF register expected"),
495  N_("Maverick MVD register expected"),
496  N_("Maverick MVFX register expected"),
497  N_("Maverick MVDX register expected"),
498  N_("Maverick MVAX register expected"),
499  N_("Maverick DSPSC register expected"),
500  N_("iWMMXt data register expected"),
501  N_("iWMMXt control register expected"),
502  N_("iWMMXt scalar register expected"),
503  N_("XScale accumulator register expected"),
504};
505
506/* Some well known registers that we refer to directly elsewhere.  */
507#define REG_SP	13
508#define REG_LR	14
509#define REG_PC	15
510
511/* ARM instructions take 4bytes in the object file, Thumb instructions
512   take 2:  */
513#define INSN_SIZE	4
514
515struct asm_opcode
516{
517  /* Basic string to match.  */
518  const char *template;
519
520  /* Parameters to instruction.	 */
521  unsigned char operands[8];
522
523  /* Conditional tag - see opcode_lookup.  */
524  unsigned int tag : 4;
525
526  /* Basic instruction code.  */
527  unsigned int avalue : 28;
528
529  /* Thumb-format instruction code.  */
530  unsigned int tvalue;
531
532  /* Which architecture variant provides this instruction.  */
533  const arm_feature_set *avariant;
534  const arm_feature_set *tvariant;
535
536  /* Function to call to encode instruction in ARM format.  */
537  void (* aencode) (void);
538
539  /* Function to call to encode instruction in Thumb format.  */
540  void (* tencode) (void);
541};
542
543/* Defines for various bits that we will want to toggle.  */
544#define INST_IMMEDIATE	0x02000000
545#define OFFSET_REG	0x02000000
546#define HWOFFSET_IMM	0x00400000
547#define SHIFT_BY_REG	0x00000010
548#define PRE_INDEX	0x01000000
549#define INDEX_UP	0x00800000
550#define WRITE_BACK	0x00200000
551#define LDM_TYPE_2_OR_3	0x00400000
552#define CPSI_MMOD	0x00020000
553
554#define LITERAL_MASK	0xf000f000
555#define OPCODE_MASK	0xfe1fffff
556#define V4_STR_BIT	0x00000020
557
558#define T2_SUBS_PC_LR	0xf3de8f00
559
560#define DATA_OP_SHIFT	21
561
562#define T2_OPCODE_MASK	0xfe1fffff
563#define T2_DATA_OP_SHIFT 21
564
565/* Codes to distinguish the arithmetic instructions.  */
566#define OPCODE_AND	0
567#define OPCODE_EOR	1
568#define OPCODE_SUB	2
569#define OPCODE_RSB	3
570#define OPCODE_ADD	4
571#define OPCODE_ADC	5
572#define OPCODE_SBC	6
573#define OPCODE_RSC	7
574#define OPCODE_TST	8
575#define OPCODE_TEQ	9
576#define OPCODE_CMP	10
577#define OPCODE_CMN	11
578#define OPCODE_ORR	12
579#define OPCODE_MOV	13
580#define OPCODE_BIC	14
581#define OPCODE_MVN	15
582
583#define T2_OPCODE_AND	0
584#define T2_OPCODE_BIC	1
585#define T2_OPCODE_ORR	2
586#define T2_OPCODE_ORN	3
587#define T2_OPCODE_EOR	4
588#define T2_OPCODE_ADD	8
589#define T2_OPCODE_ADC	10
590#define T2_OPCODE_SBC	11
591#define T2_OPCODE_SUB	13
592#define T2_OPCODE_RSB	14
593
594#define T_OPCODE_MUL 0x4340
595#define T_OPCODE_TST 0x4200
596#define T_OPCODE_CMN 0x42c0
597#define T_OPCODE_NEG 0x4240
598#define T_OPCODE_MVN 0x43c0
599
600#define T_OPCODE_ADD_R3	0x1800
601#define T_OPCODE_SUB_R3 0x1a00
602#define T_OPCODE_ADD_HI 0x4400
603#define T_OPCODE_ADD_ST 0xb000
604#define T_OPCODE_SUB_ST 0xb080
605#define T_OPCODE_ADD_SP 0xa800
606#define T_OPCODE_ADD_PC 0xa000
607#define T_OPCODE_ADD_I8 0x3000
608#define T_OPCODE_SUB_I8 0x3800
609#define T_OPCODE_ADD_I3 0x1c00
610#define T_OPCODE_SUB_I3 0x1e00
611
612#define T_OPCODE_ASR_R	0x4100
613#define T_OPCODE_LSL_R	0x4080
614#define T_OPCODE_LSR_R	0x40c0
615#define T_OPCODE_ROR_R	0x41c0
616#define T_OPCODE_ASR_I	0x1000
617#define T_OPCODE_LSL_I	0x0000
618#define T_OPCODE_LSR_I	0x0800
619
620#define T_OPCODE_MOV_I8	0x2000
621#define T_OPCODE_CMP_I8 0x2800
622#define T_OPCODE_CMP_LR 0x4280
623#define T_OPCODE_MOV_HR 0x4600
624#define T_OPCODE_CMP_HR 0x4500
625
626#define T_OPCODE_LDR_PC 0x4800
627#define T_OPCODE_LDR_SP 0x9800
628#define T_OPCODE_STR_SP 0x9000
629#define T_OPCODE_LDR_IW 0x6800
630#define T_OPCODE_STR_IW 0x6000
631#define T_OPCODE_LDR_IH 0x8800
632#define T_OPCODE_STR_IH 0x8000
633#define T_OPCODE_LDR_IB 0x7800
634#define T_OPCODE_STR_IB 0x7000
635#define T_OPCODE_LDR_RW 0x5800
636#define T_OPCODE_STR_RW 0x5000
637#define T_OPCODE_LDR_RH 0x5a00
638#define T_OPCODE_STR_RH 0x5200
639#define T_OPCODE_LDR_RB 0x5c00
640#define T_OPCODE_STR_RB 0x5400
641
642#define T_OPCODE_PUSH	0xb400
643#define T_OPCODE_POP	0xbc00
644
645#define T_OPCODE_BRANCH 0xe000
646
647#define THUMB_SIZE	2	/* Size of thumb instruction.  */
648#define THUMB_PP_PC_LR 0x0100
649#define THUMB_LOAD_BIT 0x0800
650#define THUMB2_LOAD_BIT 0x00100000
651
652#define BAD_ARGS	_("bad arguments to instruction")
653#define BAD_PC		_("r15 not allowed here")
654#define BAD_SP		_("r13 not allowed here")
655#define BAD_COND	_("instruction cannot be conditional")
656#define BAD_OVERLAP	_("registers may not be the same")
657#define BAD_HIREG	_("lo register required")
658#define BAD_THUMB32	_("instruction not supported in Thumb16 mode")
659#define BAD_ADDR_MODE   _("instruction does not accept this addressing mode");
660#define BAD_BRANCH	_("branch must be last instruction in IT block")
661#define BAD_NOT_IT	_("instruction not allowed in IT block")
662#define BAD_FPU		_("selected FPU does not support instruction")
663#define BAD_VMRS	_("APSR_nzcv may only be used with fpscr")
664
665static struct hash_control *arm_ops_hsh;
666static struct hash_control *arm_cond_hsh;
667static struct hash_control *arm_shift_hsh;
668static struct hash_control *arm_psr_hsh;
669static struct hash_control *arm_v7m_psr_hsh;
670static struct hash_control *arm_reg_hsh;
671static struct hash_control *arm_reloc_hsh;
672static struct hash_control *arm_barrier_opt_hsh;
673
674/* Stuff needed to resolve the label ambiguity
675   As:
676     ...
677     label:   <insn>
678   may differ from:
679     ...
680     label:
681	      <insn>
682*/
683
684symbolS *  last_label_seen;
685static int label_is_thumb_function_name = FALSE;
686
687/* Literal pool structure.  Held on a per-section
688   and per-sub-section basis.  */
689
690#define MAX_LITERAL_POOL_SIZE 1024
691typedef struct literal_pool
692{
693  expressionS	 literals [MAX_LITERAL_POOL_SIZE];
694  unsigned int	 next_free_entry;
695  unsigned int	 id;
696  symbolS *	 symbol;
697  segT		 section;
698  subsegT	 sub_section;
699  struct literal_pool * next;
700} literal_pool;
701
702/* Pointer to a linked list of literal pools.  */
703literal_pool * list_of_pools = NULL;
704
705/* State variables for IT block handling.  */
706static bfd_boolean current_it_mask = 0;
707static int current_cc;
708
709
710/* Pure syntax.	 */
711
712/* This array holds the chars that always start a comment.  If the
713   pre-processor is disabled, these aren't very useful.	 */
714const char comment_chars[] = "@";
715
716/* This array holds the chars that only start a comment at the beginning of
717   a line.  If the line seems to have the form '# 123 filename'
718   .line and .file directives will appear in the pre-processed output.	*/
719/* Note that input_file.c hand checks for '#' at the beginning of the
720   first line of the input file.  This is because the compiler outputs
721   #NO_APP at the beginning of its output.  */
722/* Also note that comments like this one will always work.  */
723const char line_comment_chars[] = "#";
724
725const char line_separator_chars[] = ";";
726
727/* Chars that can be used to separate mant
728   from exp in floating point numbers.	*/
729const char EXP_CHARS[] = "eE";
730
731/* Chars that mean this number is a floating point constant.  */
732/* As in 0f12.456  */
733/* or	 0d1.2345e12  */
734
735const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
736
737/* Prefix characters that indicate the start of an immediate
738   value.  */
739#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
740
741/* Separator character handling.  */
742
743#define skip_whitespace(str)  do { if (*(str) == ' ') ++(str); } while (0)
744
745static inline int
746skip_past_char (char ** str, char c)
747{
748  if (**str == c)
749    {
750      (*str)++;
751      return SUCCESS;
752    }
753  else
754    return FAIL;
755}
756#define skip_past_comma(str) skip_past_char (str, ',')
757
758/* Arithmetic expressions (possibly involving symbols).	 */
759
760/* Return TRUE if anything in the expression is a bignum.  */
761
762static int
763walk_no_bignums (symbolS * sp)
764{
765  if (symbol_get_value_expression (sp)->X_op == O_big)
766    return 1;
767
768  if (symbol_get_value_expression (sp)->X_add_symbol)
769    {
770      return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
771	      || (symbol_get_value_expression (sp)->X_op_symbol
772		  && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
773    }
774
775  return 0;
776}
777
778static int in_my_get_expression = 0;
779
780/* Third argument to my_get_expression.	 */
781#define GE_NO_PREFIX 0
782#define GE_IMM_PREFIX 1
783#define GE_OPT_PREFIX 2
784/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
785   immediates, as can be used in Neon VMVN and VMOV immediate instructions.  */
786#define GE_OPT_PREFIX_BIG 3
787
788static int
789my_get_expression (expressionS * ep, char ** str, int prefix_mode)
790{
791  char * save_in;
792  segT	 seg;
793
794  /* In unified syntax, all prefixes are optional.  */
795  if (unified_syntax)
796    prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
797                  : GE_OPT_PREFIX;
798
799  switch (prefix_mode)
800    {
801    case GE_NO_PREFIX: break;
802    case GE_IMM_PREFIX:
803      if (!is_immediate_prefix (**str))
804	{
805	  inst.error = _("immediate expression requires a # prefix");
806	  return FAIL;
807	}
808      (*str)++;
809      break;
810    case GE_OPT_PREFIX:
811    case GE_OPT_PREFIX_BIG:
812      if (is_immediate_prefix (**str))
813	(*str)++;
814      break;
815    default: abort ();
816    }
817
818  memset (ep, 0, sizeof (expressionS));
819
820  save_in = input_line_pointer;
821  input_line_pointer = *str;
822  in_my_get_expression = 1;
823  seg = expression (ep);
824  in_my_get_expression = 0;
825
826  if (ep->X_op == O_illegal)
827    {
828      /* We found a bad expression in md_operand().  */
829      *str = input_line_pointer;
830      input_line_pointer = save_in;
831      if (inst.error == NULL)
832	inst.error = _("bad expression");
833      return 1;
834    }
835
836#ifdef OBJ_AOUT
837  if (seg != absolute_section
838      && seg != text_section
839      && seg != data_section
840      && seg != bss_section
841      && seg != undefined_section)
842    {
843      inst.error = _("bad segment");
844      *str = input_line_pointer;
845      input_line_pointer = save_in;
846      return 1;
847    }
848#endif
849
850  /* Get rid of any bignums now, so that we don't generate an error for which
851     we can't establish a line number later on.	 Big numbers are never valid
852     in instructions, which is where this routine is always called.  */
853  if (prefix_mode != GE_OPT_PREFIX_BIG
854      && (ep->X_op == O_big
855          || (ep->X_add_symbol
856	      && (walk_no_bignums (ep->X_add_symbol)
857	          || (ep->X_op_symbol
858		      && walk_no_bignums (ep->X_op_symbol))))))
859    {
860      inst.error = _("invalid constant");
861      *str = input_line_pointer;
862      input_line_pointer = save_in;
863      return 1;
864    }
865
866  *str = input_line_pointer;
867  input_line_pointer = save_in;
868  return 0;
869}
870
871/* Turn a string in input_line_pointer into a floating point constant
872   of type TYPE, and store the appropriate bytes in *LITP.  The number
873   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
874   returned, or NULL on OK.
875
876   Note that fp constants aren't represent in the normal way on the ARM.
877   In big endian mode, things are as expected.	However, in little endian
878   mode fp constants are big-endian word-wise, and little-endian byte-wise
879   within the words.  For example, (double) 1.1 in big endian mode is
880   the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
881   the byte sequence 99 99 f1 3f 9a 99 99 99.
882
883   ??? The format of 12 byte floats is uncertain according to gcc's arm.h.  */
884
885char *
886md_atof (int type, char * litP, int * sizeP)
887{
888  int prec;
889  LITTLENUM_TYPE words[MAX_LITTLENUMS];
890  char *t;
891  int i;
892
893  switch (type)
894    {
895    case 'f':
896    case 'F':
897    case 's':
898    case 'S':
899      prec = 2;
900      break;
901
902    case 'd':
903    case 'D':
904    case 'r':
905    case 'R':
906      prec = 4;
907      break;
908
909    case 'x':
910    case 'X':
911      prec = 6;
912      break;
913
914    case 'p':
915    case 'P':
916      prec = 6;
917      break;
918
919    default:
920      *sizeP = 0;
921      return _("bad call to MD_ATOF()");
922    }
923
924  t = atof_ieee (input_line_pointer, type, words);
925  if (t)
926    input_line_pointer = t;
927  *sizeP = prec * 2;
928
929  if (target_big_endian)
930    {
931      for (i = 0; i < prec; i++)
932	{
933	  md_number_to_chars (litP, (valueT) words[i], 2);
934	  litP += 2;
935	}
936    }
937  else
938    {
939      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
940	for (i = prec - 1; i >= 0; i--)
941	  {
942	    md_number_to_chars (litP, (valueT) words[i], 2);
943	    litP += 2;
944	  }
945      else
946	/* For a 4 byte float the order of elements in `words' is 1 0.
947	   For an 8 byte float the order is 1 0 3 2.  */
948	for (i = 0; i < prec; i += 2)
949	  {
950	    md_number_to_chars (litP, (valueT) words[i + 1], 2);
951	    md_number_to_chars (litP + 2, (valueT) words[i], 2);
952	    litP += 4;
953	  }
954    }
955
956  return 0;
957}
958
959/* We handle all bad expressions here, so that we can report the faulty
960   instruction in the error message.  */
961void
962md_operand (expressionS * expr)
963{
964  if (in_my_get_expression)
965    expr->X_op = O_illegal;
966}
967
968/* Immediate values.  */
969
970/* Generic immediate-value read function for use in directives.
971   Accepts anything that 'expression' can fold to a constant.
972   *val receives the number.  */
973#ifdef OBJ_ELF
974static int
975immediate_for_directive (int *val)
976{
977  expressionS exp;
978  exp.X_op = O_illegal;
979
980  if (is_immediate_prefix (*input_line_pointer))
981    {
982      input_line_pointer++;
983      expression (&exp);
984    }
985
986  if (exp.X_op != O_constant)
987    {
988      as_bad (_("expected #constant"));
989      ignore_rest_of_line ();
990      return FAIL;
991    }
992  *val = exp.X_add_number;
993  return SUCCESS;
994}
995#endif
996
997/* Register parsing.  */
998
999/* Generic register parser.  CCP points to what should be the
1000   beginning of a register name.  If it is indeed a valid register
1001   name, advance CCP over it and return the reg_entry structure;
1002   otherwise return NULL.  Does not issue diagnostics.	*/
1003
1004static struct reg_entry *
1005arm_reg_parse_multi (char **ccp)
1006{
1007  char *start = *ccp;
1008  char *p;
1009  struct reg_entry *reg;
1010
1011#ifdef REGISTER_PREFIX
1012  if (*start != REGISTER_PREFIX)
1013    return NULL;
1014  start++;
1015#endif
1016#ifdef OPTIONAL_REGISTER_PREFIX
1017  if (*start == OPTIONAL_REGISTER_PREFIX)
1018    start++;
1019#endif
1020
1021  p = start;
1022  if (!ISALPHA (*p) || !is_name_beginner (*p))
1023    return NULL;
1024
1025  do
1026    p++;
1027  while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1028
1029  reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1030
1031  if (!reg)
1032    return NULL;
1033
1034  *ccp = p;
1035  return reg;
1036}
1037
1038static int
1039arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1040                    enum arm_reg_type type)
1041{
1042  /* Alternative syntaxes are accepted for a few register classes.  */
1043  switch (type)
1044    {
1045    case REG_TYPE_MVF:
1046    case REG_TYPE_MVD:
1047    case REG_TYPE_MVFX:
1048    case REG_TYPE_MVDX:
1049      /* Generic coprocessor register names are allowed for these.  */
1050      if (reg && reg->type == REG_TYPE_CN)
1051	return reg->number;
1052      break;
1053
1054    case REG_TYPE_CP:
1055      /* For backward compatibility, a bare number is valid here.  */
1056      {
1057	unsigned long processor = strtoul (start, ccp, 10);
1058	if (*ccp != start && processor <= 15)
1059	  return processor;
1060      }
1061
1062    case REG_TYPE_MMXWC:
1063      /* WC includes WCG.  ??? I'm not sure this is true for all
1064	 instructions that take WC registers.  */
1065      if (reg && reg->type == REG_TYPE_MMXWCG)
1066	return reg->number;
1067      break;
1068
1069    default:
1070      break;
1071    }
1072
1073  return FAIL;
1074}
1075
1076/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1077   return value is the register number or FAIL.  */
1078
1079static int
1080arm_reg_parse (char **ccp, enum arm_reg_type type)
1081{
1082  char *start = *ccp;
1083  struct reg_entry *reg = arm_reg_parse_multi (ccp);
1084  int ret;
1085
1086  /* Do not allow a scalar (reg+index) to parse as a register.  */
1087  if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1088    return FAIL;
1089
1090  if (reg && reg->type == type)
1091    return reg->number;
1092
1093  if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1094    return ret;
1095
1096  *ccp = start;
1097  return FAIL;
1098}
1099
1100/* Parse a Neon type specifier. *STR should point at the leading '.'
1101   character. Does no verification at this stage that the type fits the opcode
1102   properly. E.g.,
1103
1104     .i32.i32.s16
1105     .s32.f32
1106     .u16
1107
1108   Can all be legally parsed by this function.
1109
1110   Fills in neon_type struct pointer with parsed information, and updates STR
1111   to point after the parsed type specifier. Returns SUCCESS if this was a legal
1112   type, FAIL if not.  */
1113
1114static int
1115parse_neon_type (struct neon_type *type, char **str)
1116{
1117  char *ptr = *str;
1118
1119  if (type)
1120    type->elems = 0;
1121
1122  while (type->elems < NEON_MAX_TYPE_ELS)
1123    {
1124      enum neon_el_type thistype = NT_untyped;
1125      unsigned thissize = -1u;
1126
1127      if (*ptr != '.')
1128	break;
1129
1130      ptr++;
1131
1132      /* Just a size without an explicit type.  */
1133      if (ISDIGIT (*ptr))
1134	goto parsesize;
1135
1136      switch (TOLOWER (*ptr))
1137	{
1138	case 'i': thistype = NT_integer; break;
1139	case 'f': thistype = NT_float; break;
1140	case 'p': thistype = NT_poly; break;
1141	case 's': thistype = NT_signed; break;
1142	case 'u': thistype = NT_unsigned; break;
1143        case 'd':
1144          thistype = NT_float;
1145          thissize = 64;
1146          ptr++;
1147          goto done;
1148	default:
1149	  as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1150	  return FAIL;
1151	}
1152
1153      ptr++;
1154
1155      /* .f is an abbreviation for .f32.  */
1156      if (thistype == NT_float && !ISDIGIT (*ptr))
1157	thissize = 32;
1158      else
1159	{
1160	parsesize:
1161	  thissize = strtoul (ptr, &ptr, 10);
1162
1163	  if (thissize != 8 && thissize != 16 && thissize != 32
1164              && thissize != 64)
1165            {
1166              as_bad (_("bad size %d in type specifier"), thissize);
1167	      return FAIL;
1168	    }
1169	}
1170
1171      done:
1172      if (type)
1173        {
1174          type->el[type->elems].type = thistype;
1175	  type->el[type->elems].size = thissize;
1176	  type->elems++;
1177	}
1178    }
1179
1180  /* Empty/missing type is not a successful parse.  */
1181  if (type->elems == 0)
1182    return FAIL;
1183
1184  *str = ptr;
1185
1186  return SUCCESS;
1187}
1188
1189/* Errors may be set multiple times during parsing or bit encoding
1190   (particularly in the Neon bits), but usually the earliest error which is set
1191   will be the most meaningful. Avoid overwriting it with later (cascading)
1192   errors by calling this function.  */
1193
1194static void
1195first_error (const char *err)
1196{
1197  if (!inst.error)
1198    inst.error = err;
1199}
1200
1201/* Parse a single type, e.g. ".s32", leading period included.  */
1202static int
1203parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1204{
1205  char *str = *ccp;
1206  struct neon_type optype;
1207
1208  if (*str == '.')
1209    {
1210      if (parse_neon_type (&optype, &str) == SUCCESS)
1211        {
1212          if (optype.elems == 1)
1213            *vectype = optype.el[0];
1214          else
1215            {
1216              first_error (_("only one type should be specified for operand"));
1217              return FAIL;
1218            }
1219        }
1220      else
1221        {
1222          first_error (_("vector type expected"));
1223          return FAIL;
1224        }
1225    }
1226  else
1227    return FAIL;
1228
1229  *ccp = str;
1230
1231  return SUCCESS;
1232}
1233
1234/* Special meanings for indices (which have a range of 0-7), which will fit into
1235   a 4-bit integer.  */
1236
1237#define NEON_ALL_LANES		15
1238#define NEON_INTERLEAVE_LANES	14
1239
1240/* Parse either a register or a scalar, with an optional type. Return the
1241   register number, and optionally fill in the actual type of the register
1242   when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1243   type/index information in *TYPEINFO.  */
1244
1245static int
1246parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1247                           enum arm_reg_type *rtype,
1248                           struct neon_typed_alias *typeinfo)
1249{
1250  char *str = *ccp;
1251  struct reg_entry *reg = arm_reg_parse_multi (&str);
1252  struct neon_typed_alias atype;
1253  struct neon_type_el parsetype;
1254
1255  atype.defined = 0;
1256  atype.index = -1;
1257  atype.eltype.type = NT_invtype;
1258  atype.eltype.size = -1;
1259
1260  /* Try alternate syntax for some types of register. Note these are mutually
1261     exclusive with the Neon syntax extensions.  */
1262  if (reg == NULL)
1263    {
1264      int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1265      if (altreg != FAIL)
1266        *ccp = str;
1267      if (typeinfo)
1268        *typeinfo = atype;
1269      return altreg;
1270    }
1271
1272  /* Undo polymorphism when a set of register types may be accepted.  */
1273  if ((type == REG_TYPE_NDQ
1274       && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1275      || (type == REG_TYPE_VFSD
1276          && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1277      || (type == REG_TYPE_NSDQ
1278          && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1279              || reg->type == REG_TYPE_NQ))
1280      || (type == REG_TYPE_MMXWC
1281	  && (reg->type == REG_TYPE_MMXWCG)))
1282    type = reg->type;
1283
1284  if (type != reg->type)
1285    return FAIL;
1286
1287  if (reg->neon)
1288    atype = *reg->neon;
1289
1290  if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1291    {
1292      if ((atype.defined & NTA_HASTYPE) != 0)
1293        {
1294          first_error (_("can't redefine type for operand"));
1295          return FAIL;
1296        }
1297      atype.defined |= NTA_HASTYPE;
1298      atype.eltype = parsetype;
1299    }
1300
1301  if (skip_past_char (&str, '[') == SUCCESS)
1302    {
1303      if (type != REG_TYPE_VFD)
1304        {
1305          first_error (_("only D registers may be indexed"));
1306          return FAIL;
1307        }
1308
1309      if ((atype.defined & NTA_HASINDEX) != 0)
1310        {
1311          first_error (_("can't change index for operand"));
1312          return FAIL;
1313        }
1314
1315      atype.defined |= NTA_HASINDEX;
1316
1317      if (skip_past_char (&str, ']') == SUCCESS)
1318        atype.index = NEON_ALL_LANES;
1319      else
1320        {
1321          expressionS exp;
1322
1323          my_get_expression (&exp, &str, GE_NO_PREFIX);
1324
1325          if (exp.X_op != O_constant)
1326            {
1327              first_error (_("constant expression required"));
1328              return FAIL;
1329            }
1330
1331          if (skip_past_char (&str, ']') == FAIL)
1332            return FAIL;
1333
1334          atype.index = exp.X_add_number;
1335        }
1336    }
1337
1338  if (typeinfo)
1339    *typeinfo = atype;
1340
1341  if (rtype)
1342    *rtype = type;
1343
1344  *ccp = str;
1345
1346  return reg->number;
1347}
1348
1349/* Like arm_reg_parse, but allow allow the following extra features:
1350    - If RTYPE is non-zero, return the (possibly restricted) type of the
1351      register (e.g. Neon double or quad reg when either has been requested).
1352    - If this is a Neon vector type with additional type information, fill
1353      in the struct pointed to by VECTYPE (if non-NULL).
1354   This function will fault on encountering a scalar.
1355*/
1356
1357static int
1358arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1359                     enum arm_reg_type *rtype, struct neon_type_el *vectype)
1360{
1361  struct neon_typed_alias atype;
1362  char *str = *ccp;
1363  int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1364
1365  if (reg == FAIL)
1366    return FAIL;
1367
1368  /* Do not allow a scalar (reg+index) to parse as a register.  */
1369  if ((atype.defined & NTA_HASINDEX) != 0)
1370    {
1371      first_error (_("register operand expected, but got scalar"));
1372      return FAIL;
1373    }
1374
1375  if (vectype)
1376    *vectype = atype.eltype;
1377
1378  *ccp = str;
1379
1380  return reg;
1381}
1382
1383#define NEON_SCALAR_REG(X)	((X) >> 4)
1384#define NEON_SCALAR_INDEX(X)	((X) & 15)
1385
1386/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1387   have enough information to be able to do a good job bounds-checking. So, we
1388   just do easy checks here, and do further checks later.  */
1389
1390static int
1391parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1392{
1393  int reg;
1394  char *str = *ccp;
1395  struct neon_typed_alias atype;
1396
1397  reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1398
1399  if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1400    return FAIL;
1401
1402  if (atype.index == NEON_ALL_LANES)
1403    {
1404      first_error (_("scalar must have an index"));
1405      return FAIL;
1406    }
1407  else if (atype.index >= 64 / elsize)
1408    {
1409      first_error (_("scalar index out of range"));
1410      return FAIL;
1411    }
1412
1413  if (type)
1414    *type = atype.eltype;
1415
1416  *ccp = str;
1417
1418  return reg * 16 + atype.index;
1419}
1420
1421/* Parse an ARM register list.  Returns the bitmask, or FAIL.  */
1422static long
1423parse_reg_list (char ** strp)
1424{
1425  char * str = * strp;
1426  long	 range = 0;
1427  int	 another_range;
1428
1429  /* We come back here if we get ranges concatenated by '+' or '|'.  */
1430  do
1431    {
1432      another_range = 0;
1433
1434      if (*str == '{')
1435	{
1436	  int in_range = 0;
1437	  int cur_reg = -1;
1438
1439	  str++;
1440	  do
1441	    {
1442	      int reg;
1443
1444	      if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1445		{
1446		  first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1447		  return FAIL;
1448		}
1449
1450	      if (in_range)
1451		{
1452		  int i;
1453
1454		  if (reg <= cur_reg)
1455		    {
1456		      first_error (_("bad range in register list"));
1457		      return FAIL;
1458		    }
1459
1460		  for (i = cur_reg + 1; i < reg; i++)
1461		    {
1462		      if (range & (1 << i))
1463			as_tsktsk
1464			  (_("Warning: duplicated register (r%d) in register list"),
1465			   i);
1466		      else
1467			range |= 1 << i;
1468		    }
1469		  in_range = 0;
1470		}
1471
1472	      if (range & (1 << reg))
1473		as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1474			   reg);
1475	      else if (reg <= cur_reg)
1476		as_tsktsk (_("Warning: register range not in ascending order"));
1477
1478	      range |= 1 << reg;
1479	      cur_reg = reg;
1480	    }
1481	  while (skip_past_comma (&str) != FAIL
1482		 || (in_range = 1, *str++ == '-'));
1483	  str--;
1484
1485	  if (*str++ != '}')
1486	    {
1487	      first_error (_("missing `}'"));
1488	      return FAIL;
1489	    }
1490	}
1491      else
1492	{
1493	  expressionS expr;
1494
1495	  if (my_get_expression (&expr, &str, GE_NO_PREFIX))
1496	    return FAIL;
1497
1498	  if (expr.X_op == O_constant)
1499	    {
1500	      if (expr.X_add_number
1501		  != (expr.X_add_number & 0x0000ffff))
1502		{
1503		  inst.error = _("invalid register mask");
1504		  return FAIL;
1505		}
1506
1507	      if ((range & expr.X_add_number) != 0)
1508		{
1509		  int regno = range & expr.X_add_number;
1510
1511		  regno &= -regno;
1512		  regno = (1 << regno) - 1;
1513		  as_tsktsk
1514		    (_("Warning: duplicated register (r%d) in register list"),
1515		     regno);
1516		}
1517
1518	      range |= expr.X_add_number;
1519	    }
1520	  else
1521	    {
1522	      if (inst.reloc.type != 0)
1523		{
1524		  inst.error = _("expression too complex");
1525		  return FAIL;
1526		}
1527
1528	      memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1529	      inst.reloc.type = BFD_RELOC_ARM_MULTI;
1530	      inst.reloc.pc_rel = 0;
1531	    }
1532	}
1533
1534      if (*str == '|' || *str == '+')
1535	{
1536	  str++;
1537	  another_range = 1;
1538	}
1539    }
1540  while (another_range);
1541
1542  *strp = str;
1543  return range;
1544}
1545
1546/* Types of registers in a list.  */
1547
1548enum reg_list_els
1549{
1550  REGLIST_VFP_S,
1551  REGLIST_VFP_D,
1552  REGLIST_NEON_D
1553};
1554
1555/* Parse a VFP register list.  If the string is invalid return FAIL.
1556   Otherwise return the number of registers, and set PBASE to the first
1557   register.  Parses registers of type ETYPE.
1558   If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1559     - Q registers can be used to specify pairs of D registers
1560     - { } can be omitted from around a singleton register list
1561         FIXME: This is not implemented, as it would require backtracking in
1562         some cases, e.g.:
1563           vtbl.8 d3,d4,d5
1564         This could be done (the meaning isn't really ambiguous), but doesn't
1565         fit in well with the current parsing framework.
1566     - 32 D registers may be used (also true for VFPv3).
1567   FIXME: Types are ignored in these register lists, which is probably a
1568   bug.  */
1569
1570static int
1571parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1572{
1573  char *str = *ccp;
1574  int base_reg;
1575  int new_base;
1576  enum arm_reg_type regtype = 0;
1577  int max_regs = 0;
1578  int count = 0;
1579  int warned = 0;
1580  unsigned long mask = 0;
1581  int i;
1582
1583  if (*str != '{')
1584    {
1585      inst.error = _("expecting {");
1586      return FAIL;
1587    }
1588
1589  str++;
1590
1591  switch (etype)
1592    {
1593    case REGLIST_VFP_S:
1594      regtype = REG_TYPE_VFS;
1595      max_regs = 32;
1596      break;
1597
1598    case REGLIST_VFP_D:
1599      regtype = REG_TYPE_VFD;
1600      break;
1601
1602    case REGLIST_NEON_D:
1603      regtype = REG_TYPE_NDQ;
1604      break;
1605    }
1606
1607  if (etype != REGLIST_VFP_S)
1608    {
1609      /* VFPv3 allows 32 D registers.  */
1610      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
1611        {
1612          max_regs = 32;
1613          if (thumb_mode)
1614            ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1615                                    fpu_vfp_ext_v3);
1616          else
1617            ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1618                                    fpu_vfp_ext_v3);
1619        }
1620      else
1621        max_regs = 16;
1622    }
1623
1624  base_reg = max_regs;
1625
1626  do
1627    {
1628      int setmask = 1, addregs = 1;
1629
1630      new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
1631
1632      if (new_base == FAIL)
1633	{
1634	  first_error (_(reg_expected_msgs[regtype]));
1635	  return FAIL;
1636	}
1637
1638      if (new_base >= max_regs)
1639        {
1640          first_error (_("register out of range in list"));
1641          return FAIL;
1642        }
1643
1644      /* Note: a value of 2 * n is returned for the register Q<n>.  */
1645      if (regtype == REG_TYPE_NQ)
1646        {
1647          setmask = 3;
1648          addregs = 2;
1649        }
1650
1651      if (new_base < base_reg)
1652	base_reg = new_base;
1653
1654      if (mask & (setmask << new_base))
1655	{
1656	  first_error (_("invalid register list"));
1657	  return FAIL;
1658	}
1659
1660      if ((mask >> new_base) != 0 && ! warned)
1661	{
1662	  as_tsktsk (_("register list not in ascending order"));
1663	  warned = 1;
1664	}
1665
1666      mask |= setmask << new_base;
1667      count += addregs;
1668
1669      if (*str == '-') /* We have the start of a range expression */
1670	{
1671	  int high_range;
1672
1673	  str++;
1674
1675	  if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1676              == FAIL)
1677	    {
1678	      inst.error = gettext (reg_expected_msgs[regtype]);
1679	      return FAIL;
1680	    }
1681
1682          if (high_range >= max_regs)
1683            {
1684              first_error (_("register out of range in list"));
1685              return FAIL;
1686            }
1687
1688          if (regtype == REG_TYPE_NQ)
1689            high_range = high_range + 1;
1690
1691	  if (high_range <= new_base)
1692	    {
1693	      inst.error = _("register range not in ascending order");
1694	      return FAIL;
1695	    }
1696
1697	  for (new_base += addregs; new_base <= high_range; new_base += addregs)
1698	    {
1699	      if (mask & (setmask << new_base))
1700		{
1701		  inst.error = _("invalid register list");
1702		  return FAIL;
1703		}
1704
1705	      mask |= setmask << new_base;
1706	      count += addregs;
1707	    }
1708	}
1709    }
1710  while (skip_past_comma (&str) != FAIL);
1711
1712  str++;
1713
1714  /* Sanity check -- should have raised a parse error above.  */
1715  if (count == 0 || count > max_regs)
1716    abort ();
1717
1718  *pbase = base_reg;
1719
1720  /* Final test -- the registers must be consecutive.  */
1721  mask >>= base_reg;
1722  for (i = 0; i < count; i++)
1723    {
1724      if ((mask & (1u << i)) == 0)
1725	{
1726	  inst.error = _("non-contiguous register range");
1727	  return FAIL;
1728	}
1729    }
1730
1731  *ccp = str;
1732
1733  return count;
1734}
1735
1736/* True if two alias types are the same.  */
1737
1738static int
1739neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1740{
1741  if (!a && !b)
1742    return 1;
1743
1744  if (!a || !b)
1745    return 0;
1746
1747  if (a->defined != b->defined)
1748    return 0;
1749
1750  if ((a->defined & NTA_HASTYPE) != 0
1751      && (a->eltype.type != b->eltype.type
1752          || a->eltype.size != b->eltype.size))
1753    return 0;
1754
1755  if ((a->defined & NTA_HASINDEX) != 0
1756      && (a->index != b->index))
1757    return 0;
1758
1759  return 1;
1760}
1761
1762/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1763   The base register is put in *PBASE.
1764   The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1765   the return value.
1766   The register stride (minus one) is put in bit 4 of the return value.
1767   Bits [6:5] encode the list length (minus one).
1768   The type of the list elements is put in *ELTYPE, if non-NULL.  */
1769
1770#define NEON_LANE(X)		((X) & 0xf)
1771#define NEON_REG_STRIDE(X)	((((X) >> 4) & 1) + 1)
1772#define NEON_REGLIST_LENGTH(X)	((((X) >> 5) & 3) + 1)
1773
1774static int
1775parse_neon_el_struct_list (char **str, unsigned *pbase,
1776                           struct neon_type_el *eltype)
1777{
1778  char *ptr = *str;
1779  int base_reg = -1;
1780  int reg_incr = -1;
1781  int count = 0;
1782  int lane = -1;
1783  int leading_brace = 0;
1784  enum arm_reg_type rtype = REG_TYPE_NDQ;
1785  int addregs = 1;
1786  const char *const incr_error = "register stride must be 1 or 2";
1787  const char *const type_error = "mismatched element/structure types in list";
1788  struct neon_typed_alias firsttype;
1789
1790  if (skip_past_char (&ptr, '{') == SUCCESS)
1791    leading_brace = 1;
1792
1793  do
1794    {
1795      struct neon_typed_alias atype;
1796      int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1797
1798      if (getreg == FAIL)
1799        {
1800          first_error (_(reg_expected_msgs[rtype]));
1801          return FAIL;
1802        }
1803
1804      if (base_reg == -1)
1805        {
1806          base_reg = getreg;
1807          if (rtype == REG_TYPE_NQ)
1808            {
1809              reg_incr = 1;
1810              addregs = 2;
1811            }
1812          firsttype = atype;
1813        }
1814      else if (reg_incr == -1)
1815        {
1816          reg_incr = getreg - base_reg;
1817          if (reg_incr < 1 || reg_incr > 2)
1818            {
1819              first_error (_(incr_error));
1820              return FAIL;
1821            }
1822        }
1823      else if (getreg != base_reg + reg_incr * count)
1824        {
1825          first_error (_(incr_error));
1826          return FAIL;
1827        }
1828
1829      if (!neon_alias_types_same (&atype, &firsttype))
1830        {
1831          first_error (_(type_error));
1832          return FAIL;
1833        }
1834
1835      /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1836         modes.  */
1837      if (ptr[0] == '-')
1838        {
1839          struct neon_typed_alias htype;
1840          int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1841          if (lane == -1)
1842            lane = NEON_INTERLEAVE_LANES;
1843          else if (lane != NEON_INTERLEAVE_LANES)
1844            {
1845              first_error (_(type_error));
1846              return FAIL;
1847            }
1848          if (reg_incr == -1)
1849            reg_incr = 1;
1850          else if (reg_incr != 1)
1851            {
1852              first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1853              return FAIL;
1854            }
1855          ptr++;
1856          hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1857          if (hireg == FAIL)
1858            {
1859              first_error (_(reg_expected_msgs[rtype]));
1860              return FAIL;
1861            }
1862          if (!neon_alias_types_same (&htype, &firsttype))
1863            {
1864              first_error (_(type_error));
1865              return FAIL;
1866            }
1867          count += hireg + dregs - getreg;
1868          continue;
1869        }
1870
1871      /* If we're using Q registers, we can't use [] or [n] syntax.  */
1872      if (rtype == REG_TYPE_NQ)
1873        {
1874          count += 2;
1875          continue;
1876        }
1877
1878      if ((atype.defined & NTA_HASINDEX) != 0)
1879        {
1880          if (lane == -1)
1881            lane = atype.index;
1882          else if (lane != atype.index)
1883            {
1884              first_error (_(type_error));
1885              return FAIL;
1886            }
1887        }
1888      else if (lane == -1)
1889        lane = NEON_INTERLEAVE_LANES;
1890      else if (lane != NEON_INTERLEAVE_LANES)
1891        {
1892          first_error (_(type_error));
1893          return FAIL;
1894        }
1895      count++;
1896    }
1897  while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
1898
1899  /* No lane set by [x]. We must be interleaving structures.  */
1900  if (lane == -1)
1901    lane = NEON_INTERLEAVE_LANES;
1902
1903  /* Sanity check.  */
1904  if (lane == -1 || base_reg == -1 || count < 1 || count > 4
1905      || (count > 1 && reg_incr == -1))
1906    {
1907      first_error (_("error parsing element/structure list"));
1908      return FAIL;
1909    }
1910
1911  if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
1912    {
1913      first_error (_("expected }"));
1914      return FAIL;
1915    }
1916
1917  if (reg_incr == -1)
1918    reg_incr = 1;
1919
1920  if (eltype)
1921    *eltype = firsttype.eltype;
1922
1923  *pbase = base_reg;
1924  *str = ptr;
1925
1926  return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
1927}
1928
1929/* Parse an explicit relocation suffix on an expression.  This is
1930   either nothing, or a word in parentheses.  Note that if !OBJ_ELF,
1931   arm_reloc_hsh contains no entries, so this function can only
1932   succeed if there is no () after the word.  Returns -1 on error,
1933   BFD_RELOC_UNUSED if there wasn't any suffix.	 */
1934static int
1935parse_reloc (char **str)
1936{
1937  struct reloc_entry *r;
1938  char *p, *q;
1939
1940  if (**str != '(')
1941    return BFD_RELOC_UNUSED;
1942
1943  p = *str + 1;
1944  q = p;
1945
1946  while (*q && *q != ')' && *q != ',')
1947    q++;
1948  if (*q != ')')
1949    return -1;
1950
1951  if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1952    return -1;
1953
1954  *str = q + 1;
1955  return r->reloc;
1956}
1957
1958/* Directives: register aliases.  */
1959
1960static struct reg_entry *
1961insert_reg_alias (char *str, int number, int type)
1962{
1963  struct reg_entry *new;
1964  const char *name;
1965
1966  if ((new = hash_find (arm_reg_hsh, str)) != 0)
1967    {
1968      if (new->builtin)
1969	as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1970
1971      /* Only warn about a redefinition if it's not defined as the
1972	 same register.	 */
1973      else if (new->number != number || new->type != type)
1974	as_warn (_("ignoring redefinition of register alias '%s'"), str);
1975
1976      return 0;
1977    }
1978
1979  name = xstrdup (str);
1980  new = xmalloc (sizeof (struct reg_entry));
1981
1982  new->name = name;
1983  new->number = number;
1984  new->type = type;
1985  new->builtin = FALSE;
1986  new->neon = NULL;
1987
1988  if (hash_insert (arm_reg_hsh, name, (PTR) new))
1989    abort ();
1990
1991  return new;
1992}
1993
1994static void
1995insert_neon_reg_alias (char *str, int number, int type,
1996                       struct neon_typed_alias *atype)
1997{
1998  struct reg_entry *reg = insert_reg_alias (str, number, type);
1999
2000  if (!reg)
2001    {
2002      first_error (_("attempt to redefine typed alias"));
2003      return;
2004    }
2005
2006  if (atype)
2007    {
2008      reg->neon = xmalloc (sizeof (struct neon_typed_alias));
2009      *reg->neon = *atype;
2010    }
2011}
2012
2013/* Look for the .req directive.	 This is of the form:
2014
2015	new_register_name .req existing_register_name
2016
2017   If we find one, or if it looks sufficiently like one that we want to
2018   handle any error here, return non-zero.  Otherwise return zero.  */
2019
2020static int
2021create_register_alias (char * newname, char *p)
2022{
2023  struct reg_entry *old;
2024  char *oldname, *nbuf;
2025  size_t nlen;
2026
2027  /* The input scrubber ensures that whitespace after the mnemonic is
2028     collapsed to single spaces.  */
2029  oldname = p;
2030  if (strncmp (oldname, " .req ", 6) != 0)
2031    return 0;
2032
2033  oldname += 6;
2034  if (*oldname == '\0')
2035    return 0;
2036
2037  old = hash_find (arm_reg_hsh, oldname);
2038  if (!old)
2039    {
2040      as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2041      return 1;
2042    }
2043
2044  /* If TC_CASE_SENSITIVE is defined, then newname already points to
2045     the desired alias name, and p points to its end.  If not, then
2046     the desired alias name is in the global original_case_string.  */
2047#ifdef TC_CASE_SENSITIVE
2048  nlen = p - newname;
2049#else
2050  newname = original_case_string;
2051  nlen = strlen (newname);
2052#endif
2053
2054  nbuf = alloca (nlen + 1);
2055  memcpy (nbuf, newname, nlen);
2056  nbuf[nlen] = '\0';
2057
2058  /* Create aliases under the new name as stated; an all-lowercase
2059     version of the new name; and an all-uppercase version of the new
2060     name.  */
2061  insert_reg_alias (nbuf, old->number, old->type);
2062
2063  for (p = nbuf; *p; p++)
2064    *p = TOUPPER (*p);
2065
2066  if (strncmp (nbuf, newname, nlen))
2067    insert_reg_alias (nbuf, old->number, old->type);
2068
2069  for (p = nbuf; *p; p++)
2070    *p = TOLOWER (*p);
2071
2072  if (strncmp (nbuf, newname, nlen))
2073    insert_reg_alias (nbuf, old->number, old->type);
2074
2075  return 1;
2076}
2077
2078/* Create a Neon typed/indexed register alias using directives, e.g.:
2079     X .dn d5.s32[1]
2080     Y .qn 6.s16
2081     Z .dn d7
2082     T .dn Z[0]
2083   These typed registers can be used instead of the types specified after the
2084   Neon mnemonic, so long as all operands given have types. Types can also be
2085   specified directly, e.g.:
2086     vadd d0.s32, d1.s32, d2.s32
2087*/
2088
2089static int
2090create_neon_reg_alias (char *newname, char *p)
2091{
2092  enum arm_reg_type basetype;
2093  struct reg_entry *basereg;
2094  struct reg_entry mybasereg;
2095  struct neon_type ntype;
2096  struct neon_typed_alias typeinfo;
2097  char *namebuf, *nameend;
2098  int namelen;
2099
2100  typeinfo.defined = 0;
2101  typeinfo.eltype.type = NT_invtype;
2102  typeinfo.eltype.size = -1;
2103  typeinfo.index = -1;
2104
2105  nameend = p;
2106
2107  if (strncmp (p, " .dn ", 5) == 0)
2108    basetype = REG_TYPE_VFD;
2109  else if (strncmp (p, " .qn ", 5) == 0)
2110    basetype = REG_TYPE_NQ;
2111  else
2112    return 0;
2113
2114  p += 5;
2115
2116  if (*p == '\0')
2117    return 0;
2118
2119  basereg = arm_reg_parse_multi (&p);
2120
2121  if (basereg && basereg->type != basetype)
2122    {
2123      as_bad (_("bad type for register"));
2124      return 0;
2125    }
2126
2127  if (basereg == NULL)
2128    {
2129      expressionS exp;
2130      /* Try parsing as an integer.  */
2131      my_get_expression (&exp, &p, GE_NO_PREFIX);
2132      if (exp.X_op != O_constant)
2133        {
2134          as_bad (_("expression must be constant"));
2135          return 0;
2136        }
2137      basereg = &mybasereg;
2138      basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2139                                                  : exp.X_add_number;
2140      basereg->neon = 0;
2141    }
2142
2143  if (basereg->neon)
2144    typeinfo = *basereg->neon;
2145
2146  if (parse_neon_type (&ntype, &p) == SUCCESS)
2147    {
2148      /* We got a type.  */
2149      if (typeinfo.defined & NTA_HASTYPE)
2150        {
2151          as_bad (_("can't redefine the type of a register alias"));
2152          return 0;
2153        }
2154
2155      typeinfo.defined |= NTA_HASTYPE;
2156      if (ntype.elems != 1)
2157        {
2158          as_bad (_("you must specify a single type only"));
2159          return 0;
2160        }
2161      typeinfo.eltype = ntype.el[0];
2162    }
2163
2164  if (skip_past_char (&p, '[') == SUCCESS)
2165    {
2166      expressionS exp;
2167      /* We got a scalar index.  */
2168
2169      if (typeinfo.defined & NTA_HASINDEX)
2170        {
2171          as_bad (_("can't redefine the index of a scalar alias"));
2172          return 0;
2173        }
2174
2175      my_get_expression (&exp, &p, GE_NO_PREFIX);
2176
2177      if (exp.X_op != O_constant)
2178        {
2179          as_bad (_("scalar index must be constant"));
2180          return 0;
2181        }
2182
2183      typeinfo.defined |= NTA_HASINDEX;
2184      typeinfo.index = exp.X_add_number;
2185
2186      if (skip_past_char (&p, ']') == FAIL)
2187        {
2188          as_bad (_("expecting ]"));
2189          return 0;
2190        }
2191    }
2192
2193  namelen = nameend - newname;
2194  namebuf = alloca (namelen + 1);
2195  strncpy (namebuf, newname, namelen);
2196  namebuf[namelen] = '\0';
2197
2198  insert_neon_reg_alias (namebuf, basereg->number, basetype,
2199                         typeinfo.defined != 0 ? &typeinfo : NULL);
2200
2201  /* Insert name in all uppercase.  */
2202  for (p = namebuf; *p; p++)
2203    *p = TOUPPER (*p);
2204
2205  if (strncmp (namebuf, newname, namelen))
2206    insert_neon_reg_alias (namebuf, basereg->number, basetype,
2207                           typeinfo.defined != 0 ? &typeinfo : NULL);
2208
2209  /* Insert name in all lowercase.  */
2210  for (p = namebuf; *p; p++)
2211    *p = TOLOWER (*p);
2212
2213  if (strncmp (namebuf, newname, namelen))
2214    insert_neon_reg_alias (namebuf, basereg->number, basetype,
2215                           typeinfo.defined != 0 ? &typeinfo : NULL);
2216
2217  return 1;
2218}
2219
2220/* Should never be called, as .req goes between the alias and the
2221   register name, not at the beginning of the line.  */
2222static void
2223s_req (int a ATTRIBUTE_UNUSED)
2224{
2225  as_bad (_("invalid syntax for .req directive"));
2226}
2227
2228static void
2229s_dn (int a ATTRIBUTE_UNUSED)
2230{
2231  as_bad (_("invalid syntax for .dn directive"));
2232}
2233
2234static void
2235s_qn (int a ATTRIBUTE_UNUSED)
2236{
2237  as_bad (_("invalid syntax for .qn directive"));
2238}
2239
2240/* The .unreq directive deletes an alias which was previously defined
2241   by .req.  For example:
2242
2243       my_alias .req r11
2244       .unreq my_alias	  */
2245
2246static void
2247s_unreq (int a ATTRIBUTE_UNUSED)
2248{
2249  char * name;
2250  char saved_char;
2251
2252  name = input_line_pointer;
2253
2254  while (*input_line_pointer != 0
2255	 && *input_line_pointer != ' '
2256	 && *input_line_pointer != '\n')
2257    ++input_line_pointer;
2258
2259  saved_char = *input_line_pointer;
2260  *input_line_pointer = 0;
2261
2262  if (!*name)
2263    as_bad (_("invalid syntax for .unreq directive"));
2264  else
2265    {
2266      struct reg_entry *reg = hash_find (arm_reg_hsh, name);
2267
2268      if (!reg)
2269	as_bad (_("unknown register alias '%s'"), name);
2270      else if (reg->builtin)
2271	as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2272		 name);
2273      else
2274	{
2275	  hash_delete (arm_reg_hsh, name);
2276	  free ((char *) reg->name);
2277          if (reg->neon)
2278            free (reg->neon);
2279	  free (reg);
2280	}
2281    }
2282
2283  *input_line_pointer = saved_char;
2284  demand_empty_rest_of_line ();
2285}
2286
2287/* Directives: Instruction set selection.  */
2288
2289#ifdef OBJ_ELF
2290/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2291   (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2292   Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2293   and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped.  */
2294
2295static enum mstate mapstate = MAP_UNDEFINED;
2296
2297void
2298mapping_state (enum mstate state)
2299{
2300  symbolS * symbolP;
2301  const char * symname;
2302  int type;
2303
2304  if (mapstate == state)
2305    /* The mapping symbol has already been emitted.
2306       There is nothing else to do.  */
2307    return;
2308
2309  mapstate = state;
2310
2311  switch (state)
2312    {
2313    case MAP_DATA:
2314      symname = "$d";
2315      type = BSF_NO_FLAGS;
2316      break;
2317    case MAP_ARM:
2318      symname = "$a";
2319      type = BSF_NO_FLAGS;
2320      break;
2321    case MAP_THUMB:
2322      symname = "$t";
2323      type = BSF_NO_FLAGS;
2324      break;
2325    case MAP_UNDEFINED:
2326      return;
2327    default:
2328      abort ();
2329    }
2330
2331  seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2332
2333  symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
2334  symbol_table_insert (symbolP);
2335  symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2336
2337  switch (state)
2338    {
2339    case MAP_ARM:
2340      THUMB_SET_FUNC (symbolP, 0);
2341      ARM_SET_THUMB (symbolP, 0);
2342      ARM_SET_INTERWORK (symbolP, support_interwork);
2343      break;
2344
2345    case MAP_THUMB:
2346      THUMB_SET_FUNC (symbolP, 1);
2347      ARM_SET_THUMB (symbolP, 1);
2348      ARM_SET_INTERWORK (symbolP, support_interwork);
2349      break;
2350
2351    case MAP_DATA:
2352    default:
2353      return;
2354    }
2355}
2356#else
2357#define mapping_state(x) /* nothing */
2358#endif
2359
2360/* Find the real, Thumb encoded start of a Thumb function.  */
2361
2362static symbolS *
2363find_real_start (symbolS * symbolP)
2364{
2365  char *       real_start;
2366  const char * name = S_GET_NAME (symbolP);
2367  symbolS *    new_target;
2368
2369  /* This definition must agree with the one in gcc/config/arm/thumb.c.	 */
2370#define STUB_NAME ".real_start_of"
2371
2372  if (name == NULL)
2373    abort ();
2374
2375  /* The compiler may generate BL instructions to local labels because
2376     it needs to perform a branch to a far away location. These labels
2377     do not have a corresponding ".real_start_of" label.  We check
2378     both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2379     the ".real_start_of" convention for nonlocal branches.  */
2380  if (S_IS_LOCAL (symbolP) || name[0] == '.')
2381    return symbolP;
2382
2383  real_start = ACONCAT ((STUB_NAME, name, NULL));
2384  new_target = symbol_find (real_start);
2385
2386  if (new_target == NULL)
2387    {
2388      as_warn ("Failed to find real start of function: %s\n", name);
2389      new_target = symbolP;
2390    }
2391
2392  return new_target;
2393}
2394
2395static void
2396opcode_select (int width)
2397{
2398  switch (width)
2399    {
2400    case 16:
2401      if (! thumb_mode)
2402	{
2403	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2404	    as_bad (_("selected processor does not support THUMB opcodes"));
2405
2406	  thumb_mode = 1;
2407	  /* No need to force the alignment, since we will have been
2408	     coming from ARM mode, which is word-aligned.  */
2409	  record_alignment (now_seg, 1);
2410	}
2411      mapping_state (MAP_THUMB);
2412      break;
2413
2414    case 32:
2415      if (thumb_mode)
2416	{
2417	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2418	    as_bad (_("selected processor does not support ARM opcodes"));
2419
2420	  thumb_mode = 0;
2421
2422	  if (!need_pass_2)
2423	    frag_align (2, 0, 0);
2424
2425	  record_alignment (now_seg, 1);
2426	}
2427      mapping_state (MAP_ARM);
2428      break;
2429
2430    default:
2431      as_bad (_("invalid instruction size selected (%d)"), width);
2432    }
2433}
2434
2435static void
2436s_arm (int ignore ATTRIBUTE_UNUSED)
2437{
2438  opcode_select (32);
2439  demand_empty_rest_of_line ();
2440}
2441
2442static void
2443s_thumb (int ignore ATTRIBUTE_UNUSED)
2444{
2445  opcode_select (16);
2446  demand_empty_rest_of_line ();
2447}
2448
2449static void
2450s_code (int unused ATTRIBUTE_UNUSED)
2451{
2452  int temp;
2453
2454  temp = get_absolute_expression ();
2455  switch (temp)
2456    {
2457    case 16:
2458    case 32:
2459      opcode_select (temp);
2460      break;
2461
2462    default:
2463      as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2464    }
2465}
2466
2467static void
2468s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2469{
2470  /* If we are not already in thumb mode go into it, EVEN if
2471     the target processor does not support thumb instructions.
2472     This is used by gcc/config/arm/lib1funcs.asm for example
2473     to compile interworking support functions even if the
2474     target processor should not support interworking.	*/
2475  if (! thumb_mode)
2476    {
2477      thumb_mode = 2;
2478      record_alignment (now_seg, 1);
2479    }
2480
2481  demand_empty_rest_of_line ();
2482}
2483
2484static void
2485s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2486{
2487  s_thumb (0);
2488
2489  /* The following label is the name/address of the start of a Thumb function.
2490     We need to know this for the interworking support.	 */
2491  label_is_thumb_function_name = TRUE;
2492}
2493
2494/* Perform a .set directive, but also mark the alias as
2495   being a thumb function.  */
2496
2497static void
2498s_thumb_set (int equiv)
2499{
2500  /* XXX the following is a duplicate of the code for s_set() in read.c
2501     We cannot just call that code as we need to get at the symbol that
2502     is created.  */
2503  char *    name;
2504  char	    delim;
2505  char *    end_name;
2506  symbolS * symbolP;
2507
2508  /* Especial apologies for the random logic:
2509     This just grew, and could be parsed much more simply!
2510     Dean - in haste.  */
2511  name	    = input_line_pointer;
2512  delim	    = get_symbol_end ();
2513  end_name  = input_line_pointer;
2514  *end_name = delim;
2515
2516  if (*input_line_pointer != ',')
2517    {
2518      *end_name = 0;
2519      as_bad (_("expected comma after name \"%s\""), name);
2520      *end_name = delim;
2521      ignore_rest_of_line ();
2522      return;
2523    }
2524
2525  input_line_pointer++;
2526  *end_name = 0;
2527
2528  if (name[0] == '.' && name[1] == '\0')
2529    {
2530      /* XXX - this should not happen to .thumb_set.  */
2531      abort ();
2532    }
2533
2534  if ((symbolP = symbol_find (name)) == NULL
2535      && (symbolP = md_undefined_symbol (name)) == NULL)
2536    {
2537#ifndef NO_LISTING
2538      /* When doing symbol listings, play games with dummy fragments living
2539	 outside the normal fragment chain to record the file and line info
2540	 for this symbol.  */
2541      if (listing & LISTING_SYMBOLS)
2542	{
2543	  extern struct list_info_struct * listing_tail;
2544	  fragS * dummy_frag = xmalloc (sizeof (fragS));
2545
2546	  memset (dummy_frag, 0, sizeof (fragS));
2547	  dummy_frag->fr_type = rs_fill;
2548	  dummy_frag->line = listing_tail;
2549	  symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2550	  dummy_frag->fr_symbol = symbolP;
2551	}
2552      else
2553#endif
2554	symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2555
2556#ifdef OBJ_COFF
2557      /* "set" symbols are local unless otherwise specified.  */
2558      SF_SET_LOCAL (symbolP);
2559#endif /* OBJ_COFF  */
2560    }				/* Make a new symbol.  */
2561
2562  symbol_table_insert (symbolP);
2563
2564  * end_name = delim;
2565
2566  if (equiv
2567      && S_IS_DEFINED (symbolP)
2568      && S_GET_SEGMENT (symbolP) != reg_section)
2569    as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2570
2571  pseudo_set (symbolP);
2572
2573  demand_empty_rest_of_line ();
2574
2575  /* XXX Now we come to the Thumb specific bit of code.	 */
2576
2577  THUMB_SET_FUNC (symbolP, 1);
2578  ARM_SET_THUMB (symbolP, 1);
2579#if defined OBJ_ELF || defined OBJ_COFF
2580  ARM_SET_INTERWORK (symbolP, support_interwork);
2581#endif
2582}
2583
2584/* Directives: Mode selection.  */
2585
2586/* .syntax [unified|divided] - choose the new unified syntax
2587   (same for Arm and Thumb encoding, modulo slight differences in what
2588   can be represented) or the old divergent syntax for each mode.  */
2589static void
2590s_syntax (int unused ATTRIBUTE_UNUSED)
2591{
2592  char *name, delim;
2593
2594  name = input_line_pointer;
2595  delim = get_symbol_end ();
2596
2597  if (!strcasecmp (name, "unified"))
2598    unified_syntax = TRUE;
2599  else if (!strcasecmp (name, "divided"))
2600    unified_syntax = FALSE;
2601  else
2602    {
2603      as_bad (_("unrecognized syntax mode \"%s\""), name);
2604      return;
2605    }
2606  *input_line_pointer = delim;
2607  demand_empty_rest_of_line ();
2608}
2609
2610/* Directives: sectioning and alignment.  */
2611
2612/* Same as s_align_ptwo but align 0 => align 2.	 */
2613
2614static void
2615s_align (int unused ATTRIBUTE_UNUSED)
2616{
2617  int temp;
2618  bfd_boolean fill_p;
2619  long temp_fill;
2620  long max_alignment = 15;
2621
2622  temp = get_absolute_expression ();
2623  if (temp > max_alignment)
2624    as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2625  else if (temp < 0)
2626    {
2627      as_bad (_("alignment negative. 0 assumed."));
2628      temp = 0;
2629    }
2630
2631  if (*input_line_pointer == ',')
2632    {
2633      input_line_pointer++;
2634      temp_fill = get_absolute_expression ();
2635      fill_p = TRUE;
2636    }
2637  else
2638    {
2639      fill_p = FALSE;
2640      temp_fill = 0;
2641    }
2642
2643  if (!temp)
2644    temp = 2;
2645
2646  /* Only make a frag if we HAVE to.  */
2647  if (temp && !need_pass_2)
2648    {
2649      if (!fill_p && subseg_text_p (now_seg))
2650	frag_align_code (temp, 0);
2651      else
2652	frag_align (temp, (int) temp_fill, 0);
2653    }
2654  demand_empty_rest_of_line ();
2655
2656  record_alignment (now_seg, temp);
2657}
2658
2659static void
2660s_bss (int ignore ATTRIBUTE_UNUSED)
2661{
2662  /* We don't support putting frags in the BSS segment, we fake it by
2663     marking in_bss, then looking at s_skip for clues.	*/
2664  subseg_set (bss_section, 0);
2665  demand_empty_rest_of_line ();
2666  mapping_state (MAP_DATA);
2667}
2668
2669static void
2670s_even (int ignore ATTRIBUTE_UNUSED)
2671{
2672  /* Never make frag if expect extra pass.  */
2673  if (!need_pass_2)
2674    frag_align (1, 0, 0);
2675
2676  record_alignment (now_seg, 1);
2677
2678  demand_empty_rest_of_line ();
2679}
2680
2681/* Directives: Literal pools.  */
2682
2683static literal_pool *
2684find_literal_pool (void)
2685{
2686  literal_pool * pool;
2687
2688  for (pool = list_of_pools; pool != NULL; pool = pool->next)
2689    {
2690      if (pool->section == now_seg
2691	  && pool->sub_section == now_subseg)
2692	break;
2693    }
2694
2695  return pool;
2696}
2697
2698static literal_pool *
2699find_or_make_literal_pool (void)
2700{
2701  /* Next literal pool ID number.  */
2702  static unsigned int latest_pool_num = 1;
2703  literal_pool *      pool;
2704
2705  pool = find_literal_pool ();
2706
2707  if (pool == NULL)
2708    {
2709      /* Create a new pool.  */
2710      pool = xmalloc (sizeof (* pool));
2711      if (! pool)
2712	return NULL;
2713
2714      pool->next_free_entry = 0;
2715      pool->section	    = now_seg;
2716      pool->sub_section	    = now_subseg;
2717      pool->next	    = list_of_pools;
2718      pool->symbol	    = NULL;
2719
2720      /* Add it to the list.  */
2721      list_of_pools = pool;
2722    }
2723
2724  /* New pools, and emptied pools, will have a NULL symbol.  */
2725  if (pool->symbol == NULL)
2726    {
2727      pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
2728				    (valueT) 0, &zero_address_frag);
2729      pool->id = latest_pool_num ++;
2730    }
2731
2732  /* Done.  */
2733  return pool;
2734}
2735
2736/* Add the literal in the global 'inst'
2737   structure to the relevent literal pool.  */
2738
2739static int
2740add_to_lit_pool (void)
2741{
2742  literal_pool * pool;
2743  unsigned int entry;
2744
2745  pool = find_or_make_literal_pool ();
2746
2747  /* Check if this literal value is already in the pool.  */
2748  for (entry = 0; entry < pool->next_free_entry; entry ++)
2749    {
2750      if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
2751	  && (inst.reloc.exp.X_op == O_constant)
2752	  && (pool->literals[entry].X_add_number
2753	      == inst.reloc.exp.X_add_number)
2754	  && (pool->literals[entry].X_unsigned
2755	      == inst.reloc.exp.X_unsigned))
2756	break;
2757
2758      if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
2759	  && (inst.reloc.exp.X_op == O_symbol)
2760	  && (pool->literals[entry].X_add_number
2761	      == inst.reloc.exp.X_add_number)
2762	  && (pool->literals[entry].X_add_symbol
2763	      == inst.reloc.exp.X_add_symbol)
2764	  && (pool->literals[entry].X_op_symbol
2765	      == inst.reloc.exp.X_op_symbol))
2766	break;
2767    }
2768
2769  /* Do we need to create a new entry?	*/
2770  if (entry == pool->next_free_entry)
2771    {
2772      if (entry >= MAX_LITERAL_POOL_SIZE)
2773	{
2774	  inst.error = _("literal pool overflow");
2775	  return FAIL;
2776	}
2777
2778      pool->literals[entry] = inst.reloc.exp;
2779      pool->next_free_entry += 1;
2780    }
2781
2782  inst.reloc.exp.X_op	      = O_symbol;
2783  inst.reloc.exp.X_add_number = ((int) entry) * 4;
2784  inst.reloc.exp.X_add_symbol = pool->symbol;
2785
2786  return SUCCESS;
2787}
2788
2789/* Can't use symbol_new here, so have to create a symbol and then at
2790   a later date assign it a value. Thats what these functions do.  */
2791
2792static void
2793symbol_locate (symbolS *    symbolP,
2794	       const char * name,	/* It is copied, the caller can modify.	 */
2795	       segT	    segment,	/* Segment identifier (SEG_<something>).  */
2796	       valueT	    valu,	/* Symbol value.  */
2797	       fragS *	    frag)	/* Associated fragment.	 */
2798{
2799  unsigned int name_length;
2800  char * preserved_copy_of_name;
2801
2802  name_length = strlen (name) + 1;   /* +1 for \0.  */
2803  obstack_grow (&notes, name, name_length);
2804  preserved_copy_of_name = obstack_finish (&notes);
2805
2806#ifdef tc_canonicalize_symbol_name
2807  preserved_copy_of_name =
2808    tc_canonicalize_symbol_name (preserved_copy_of_name);
2809#endif
2810
2811  S_SET_NAME (symbolP, preserved_copy_of_name);
2812
2813  S_SET_SEGMENT (symbolP, segment);
2814  S_SET_VALUE (symbolP, valu);
2815  symbol_clear_list_pointers (symbolP);
2816
2817  symbol_set_frag (symbolP, frag);
2818
2819  /* Link to end of symbol chain.  */
2820  {
2821    extern int symbol_table_frozen;
2822
2823    if (symbol_table_frozen)
2824      abort ();
2825  }
2826
2827  symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
2828
2829  obj_symbol_new_hook (symbolP);
2830
2831#ifdef tc_symbol_new_hook
2832  tc_symbol_new_hook (symbolP);
2833#endif
2834
2835#ifdef DEBUG_SYMS
2836  verify_symbol_chain (symbol_rootP, symbol_lastP);
2837#endif /* DEBUG_SYMS  */
2838}
2839
2840
2841static void
2842s_ltorg (int ignored ATTRIBUTE_UNUSED)
2843{
2844  unsigned int entry;
2845  literal_pool * pool;
2846  char sym_name[20];
2847
2848  pool = find_literal_pool ();
2849  if (pool == NULL
2850      || pool->symbol == NULL
2851      || pool->next_free_entry == 0)
2852    return;
2853
2854  mapping_state (MAP_DATA);
2855
2856  /* Align pool as you have word accesses.
2857     Only make a frag if we have to.  */
2858  if (!need_pass_2)
2859    frag_align (2, 0, 0);
2860
2861  record_alignment (now_seg, 2);
2862
2863  sprintf (sym_name, "$$lit_\002%x", pool->id);
2864
2865  symbol_locate (pool->symbol, sym_name, now_seg,
2866		 (valueT) frag_now_fix (), frag_now);
2867  symbol_table_insert (pool->symbol);
2868
2869  ARM_SET_THUMB (pool->symbol, thumb_mode);
2870
2871#if defined OBJ_COFF || defined OBJ_ELF
2872  ARM_SET_INTERWORK (pool->symbol, support_interwork);
2873#endif
2874
2875  for (entry = 0; entry < pool->next_free_entry; entry ++)
2876    /* First output the expression in the instruction to the pool.  */
2877    emit_expr (&(pool->literals[entry]), 4); /* .word  */
2878
2879  /* Mark the pool as empty.  */
2880  pool->next_free_entry = 0;
2881  pool->symbol = NULL;
2882}
2883
2884#ifdef OBJ_ELF
2885/* Forward declarations for functions below, in the MD interface
2886   section.  */
2887static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
2888static valueT create_unwind_entry (int);
2889static void start_unwind_section (const segT, int);
2890static void add_unwind_opcode (valueT, int);
2891static void flush_pending_unwind (void);
2892
2893/* Directives: Data.  */
2894
2895static void
2896s_arm_elf_cons (int nbytes)
2897{
2898  expressionS exp;
2899
2900#ifdef md_flush_pending_output
2901  md_flush_pending_output ();
2902#endif
2903
2904  if (is_it_end_of_statement ())
2905    {
2906      demand_empty_rest_of_line ();
2907      return;
2908    }
2909
2910#ifdef md_cons_align
2911  md_cons_align (nbytes);
2912#endif
2913
2914  mapping_state (MAP_DATA);
2915  do
2916    {
2917      int reloc;
2918      char *base = input_line_pointer;
2919
2920      expression (& exp);
2921
2922      if (exp.X_op != O_symbol)
2923	emit_expr (&exp, (unsigned int) nbytes);
2924      else
2925	{
2926	  char *before_reloc = input_line_pointer;
2927	  reloc = parse_reloc (&input_line_pointer);
2928	  if (reloc == -1)
2929	    {
2930	      as_bad (_("unrecognized relocation suffix"));
2931	      ignore_rest_of_line ();
2932	      return;
2933	    }
2934	  else if (reloc == BFD_RELOC_UNUSED)
2935	    emit_expr (&exp, (unsigned int) nbytes);
2936	  else
2937	    {
2938	      reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
2939	      int size = bfd_get_reloc_size (howto);
2940
2941	      if (reloc == BFD_RELOC_ARM_PLT32)
2942		{
2943		  as_bad (_("(plt) is only valid on branch targets"));
2944		  reloc = BFD_RELOC_UNUSED;
2945		  size = 0;
2946		}
2947
2948	      if (size > nbytes)
2949		as_bad (_("%s relocations do not fit in %d bytes"),
2950			howto->name, nbytes);
2951	      else
2952		{
2953		  /* We've parsed an expression stopping at O_symbol.
2954		     But there may be more expression left now that we
2955		     have parsed the relocation marker.  Parse it again.
2956		     XXX Surely there is a cleaner way to do this.  */
2957		  char *p = input_line_pointer;
2958		  int offset;
2959		  char *save_buf = alloca (input_line_pointer - base);
2960		  memcpy (save_buf, base, input_line_pointer - base);
2961		  memmove (base + (input_line_pointer - before_reloc),
2962			   base, before_reloc - base);
2963
2964		  input_line_pointer = base + (input_line_pointer-before_reloc);
2965		  expression (&exp);
2966		  memcpy (base, save_buf, p - base);
2967
2968		  offset = nbytes - size;
2969		  p = frag_more ((int) nbytes);
2970		  fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2971			       size, &exp, 0, reloc);
2972		}
2973	    }
2974	}
2975    }
2976  while (*input_line_pointer++ == ',');
2977
2978  /* Put terminator back into stream.  */
2979  input_line_pointer --;
2980  demand_empty_rest_of_line ();
2981}
2982
2983
2984/* Parse a .rel31 directive.  */
2985
2986static void
2987s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2988{
2989  expressionS exp;
2990  char *p;
2991  valueT highbit;
2992
2993  highbit = 0;
2994  if (*input_line_pointer == '1')
2995    highbit = 0x80000000;
2996  else if (*input_line_pointer != '0')
2997    as_bad (_("expected 0 or 1"));
2998
2999  input_line_pointer++;
3000  if (*input_line_pointer != ',')
3001    as_bad (_("missing comma"));
3002  input_line_pointer++;
3003
3004#ifdef md_flush_pending_output
3005  md_flush_pending_output ();
3006#endif
3007
3008#ifdef md_cons_align
3009  md_cons_align (4);
3010#endif
3011
3012  mapping_state (MAP_DATA);
3013
3014  expression (&exp);
3015
3016  p = frag_more (4);
3017  md_number_to_chars (p, highbit, 4);
3018  fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3019	       BFD_RELOC_ARM_PREL31);
3020
3021  demand_empty_rest_of_line ();
3022}
3023
3024/* Directives: AEABI stack-unwind tables.  */
3025
3026/* Parse an unwind_fnstart directive.  Simply records the current location.  */
3027
3028static void
3029s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3030{
3031  demand_empty_rest_of_line ();
3032  /* Mark the start of the function.  */
3033  unwind.proc_start = expr_build_dot ();
3034
3035  /* Reset the rest of the unwind info.	 */
3036  unwind.opcode_count = 0;
3037  unwind.table_entry = NULL;
3038  unwind.personality_routine = NULL;
3039  unwind.personality_index = -1;
3040  unwind.frame_size = 0;
3041  unwind.fp_offset = 0;
3042  unwind.fp_reg = 13;
3043  unwind.fp_used = 0;
3044  unwind.sp_restored = 0;
3045}
3046
3047
3048/* Parse a handlerdata directive.  Creates the exception handling table entry
3049   for the function.  */
3050
3051static void
3052s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3053{
3054  demand_empty_rest_of_line ();
3055  if (unwind.table_entry)
3056    as_bad (_("dupicate .handlerdata directive"));
3057
3058  create_unwind_entry (1);
3059}
3060
3061/* Parse an unwind_fnend directive.  Generates the index table entry.  */
3062
3063static void
3064s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3065{
3066  long where;
3067  char *ptr;
3068  valueT val;
3069
3070  demand_empty_rest_of_line ();
3071
3072  /* Add eh table entry.  */
3073  if (unwind.table_entry == NULL)
3074    val = create_unwind_entry (0);
3075  else
3076    val = 0;
3077
3078  /* Add index table entry.  This is two words.	 */
3079  start_unwind_section (unwind.saved_seg, 1);
3080  frag_align (2, 0, 0);
3081  record_alignment (now_seg, 2);
3082
3083  ptr = frag_more (8);
3084  memset(ptr, 0, 8);
3085  where = frag_now_fix () - 8;
3086
3087  /* Self relative offset of the function start.  */
3088  fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3089	   BFD_RELOC_ARM_PREL31);
3090
3091  /* Indicate dependency on EHABI-defined personality routines to the
3092     linker, if it hasn't been done already.  */
3093  if (unwind.personality_index >= 0 && unwind.personality_index < 3
3094      && !(marked_pr_dependency & (1 << unwind.personality_index)))
3095    {
3096      static const char *const name[] = {
3097	"__aeabi_unwind_cpp_pr0",
3098	"__aeabi_unwind_cpp_pr1",
3099	"__aeabi_unwind_cpp_pr2"
3100      };
3101      symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3102      fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3103      marked_pr_dependency |= 1 << unwind.personality_index;
3104      seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3105	= marked_pr_dependency;
3106    }
3107
3108  if (val)
3109    /* Inline exception table entry.  */
3110    md_number_to_chars (ptr + 4, val, 4);
3111  else
3112    /* Self relative offset of the table entry.	 */
3113    fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3114	     BFD_RELOC_ARM_PREL31);
3115
3116  /* Restore the original section.  */
3117  subseg_set (unwind.saved_seg, unwind.saved_subseg);
3118}
3119
3120
3121/* Parse an unwind_cantunwind directive.  */
3122
3123static void
3124s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3125{
3126  demand_empty_rest_of_line ();
3127  if (unwind.personality_routine || unwind.personality_index != -1)
3128    as_bad (_("personality routine specified for cantunwind frame"));
3129
3130  unwind.personality_index = -2;
3131}
3132
3133
3134/* Parse a personalityindex directive.	*/
3135
3136static void
3137s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3138{
3139  expressionS exp;
3140
3141  if (unwind.personality_routine || unwind.personality_index != -1)
3142    as_bad (_("duplicate .personalityindex directive"));
3143
3144  expression (&exp);
3145
3146  if (exp.X_op != O_constant
3147      || exp.X_add_number < 0 || exp.X_add_number > 15)
3148    {
3149      as_bad (_("bad personality routine number"));
3150      ignore_rest_of_line ();
3151      return;
3152    }
3153
3154  unwind.personality_index = exp.X_add_number;
3155
3156  demand_empty_rest_of_line ();
3157}
3158
3159
3160/* Parse a personality directive.  */
3161
3162static void
3163s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3164{
3165  char *name, *p, c;
3166
3167  if (unwind.personality_routine || unwind.personality_index != -1)
3168    as_bad (_("duplicate .personality directive"));
3169
3170  name = input_line_pointer;
3171  c = get_symbol_end ();
3172  p = input_line_pointer;
3173  unwind.personality_routine = symbol_find_or_make (name);
3174  *p = c;
3175  demand_empty_rest_of_line ();
3176}
3177
3178
3179/* Parse a directive saving core registers.  */
3180
3181static void
3182s_arm_unwind_save_core (void)
3183{
3184  valueT op;
3185  long range;
3186  int n;
3187
3188  range = parse_reg_list (&input_line_pointer);
3189  if (range == FAIL)
3190    {
3191      as_bad (_("expected register list"));
3192      ignore_rest_of_line ();
3193      return;
3194    }
3195
3196  demand_empty_rest_of_line ();
3197
3198  /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3199     into .unwind_save {..., sp...}.  We aren't bothered about the value of
3200     ip because it is clobbered by calls.  */
3201  if (unwind.sp_restored && unwind.fp_reg == 12
3202      && (range & 0x3000) == 0x1000)
3203    {
3204      unwind.opcode_count--;
3205      unwind.sp_restored = 0;
3206      range = (range | 0x2000) & ~0x1000;
3207      unwind.pending_offset = 0;
3208    }
3209
3210  /* Pop r4-r15.  */
3211  if (range & 0xfff0)
3212    {
3213      /* See if we can use the short opcodes.  These pop a block of up to 8
3214	 registers starting with r4, plus maybe r14.  */
3215      for (n = 0; n < 8; n++)
3216	{
3217	  /* Break at the first non-saved register.	 */
3218	  if ((range & (1 << (n + 4))) == 0)
3219	    break;
3220	}
3221      /* See if there are any other bits set.  */
3222      if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3223	{
3224	  /* Use the long form.  */
3225	  op = 0x8000 | ((range >> 4) & 0xfff);
3226	  add_unwind_opcode (op, 2);
3227	}
3228      else
3229	{
3230	  /* Use the short form.  */
3231	  if (range & 0x4000)
3232	    op = 0xa8; /* Pop r14.	*/
3233	  else
3234	    op = 0xa0; /* Do not pop r14.  */
3235	  op |= (n - 1);
3236	  add_unwind_opcode (op, 1);
3237	}
3238    }
3239
3240  /* Pop r0-r3.	 */
3241  if (range & 0xf)
3242    {
3243      op = 0xb100 | (range & 0xf);
3244      add_unwind_opcode (op, 2);
3245    }
3246
3247  /* Record the number of bytes pushed.	 */
3248  for (n = 0; n < 16; n++)
3249    {
3250      if (range & (1 << n))
3251	unwind.frame_size += 4;
3252    }
3253}
3254
3255
3256/* Parse a directive saving FPA registers.  */
3257
3258static void
3259s_arm_unwind_save_fpa (int reg)
3260{
3261  expressionS exp;
3262  int num_regs;
3263  valueT op;
3264
3265  /* Get Number of registers to transfer.  */
3266  if (skip_past_comma (&input_line_pointer) != FAIL)
3267    expression (&exp);
3268  else
3269    exp.X_op = O_illegal;
3270
3271  if (exp.X_op != O_constant)
3272    {
3273      as_bad (_("expected , <constant>"));
3274      ignore_rest_of_line ();
3275      return;
3276    }
3277
3278  num_regs = exp.X_add_number;
3279
3280  if (num_regs < 1 || num_regs > 4)
3281    {
3282      as_bad (_("number of registers must be in the range [1:4]"));
3283      ignore_rest_of_line ();
3284      return;
3285    }
3286
3287  demand_empty_rest_of_line ();
3288
3289  if (reg == 4)
3290    {
3291      /* Short form.  */
3292      op = 0xb4 | (num_regs - 1);
3293      add_unwind_opcode (op, 1);
3294    }
3295  else
3296    {
3297      /* Long form.  */
3298      op = 0xc800 | (reg << 4) | (num_regs - 1);
3299      add_unwind_opcode (op, 2);
3300    }
3301  unwind.frame_size += num_regs * 12;
3302}
3303
3304
3305/* Parse a directive saving VFP registers for ARMv6 and above.  */
3306
3307static void
3308s_arm_unwind_save_vfp_armv6 (void)
3309{
3310  int count;
3311  unsigned int start;
3312  valueT op;
3313  int num_vfpv3_regs = 0;
3314  int num_regs_below_16;
3315
3316  count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3317  if (count == FAIL)
3318    {
3319      as_bad (_("expected register list"));
3320      ignore_rest_of_line ();
3321      return;
3322    }
3323
3324  demand_empty_rest_of_line ();
3325
3326  /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3327     than FSTMX/FLDMX-style ones).  */
3328
3329  /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31.  */
3330  if (start >= 16)
3331    num_vfpv3_regs = count;
3332  else if (start + count > 16)
3333    num_vfpv3_regs = start + count - 16;
3334
3335  if (num_vfpv3_regs > 0)
3336    {
3337      int start_offset = start > 16 ? start - 16 : 0;
3338      op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3339      add_unwind_opcode (op, 2);
3340    }
3341
3342  /* Generate opcode for registers numbered in the range 0 .. 15.  */
3343  num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3344  assert (num_regs_below_16 + num_vfpv3_regs == count);
3345  if (num_regs_below_16 > 0)
3346    {
3347      op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3348      add_unwind_opcode (op, 2);
3349    }
3350
3351  unwind.frame_size += count * 8;
3352}
3353
3354
3355/* Parse a directive saving VFP registers for pre-ARMv6.  */
3356
3357static void
3358s_arm_unwind_save_vfp (void)
3359{
3360  int count;
3361  unsigned int reg;
3362  valueT op;
3363
3364  count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D);
3365  if (count == FAIL)
3366    {
3367      as_bad (_("expected register list"));
3368      ignore_rest_of_line ();
3369      return;
3370    }
3371
3372  demand_empty_rest_of_line ();
3373
3374  if (reg == 8)
3375    {
3376      /* Short form.  */
3377      op = 0xb8 | (count - 1);
3378      add_unwind_opcode (op, 1);
3379    }
3380  else
3381    {
3382      /* Long form.  */
3383      op = 0xb300 | (reg << 4) | (count - 1);
3384      add_unwind_opcode (op, 2);
3385    }
3386  unwind.frame_size += count * 8 + 4;
3387}
3388
3389
3390/* Parse a directive saving iWMMXt data registers.  */
3391
3392static void
3393s_arm_unwind_save_mmxwr (void)
3394{
3395  int reg;
3396  int hi_reg;
3397  int i;
3398  unsigned mask = 0;
3399  valueT op;
3400
3401  if (*input_line_pointer == '{')
3402    input_line_pointer++;
3403
3404  do
3405    {
3406      reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3407
3408      if (reg == FAIL)
3409	{
3410	  as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
3411	  goto error;
3412	}
3413
3414      if (mask >> reg)
3415	as_tsktsk (_("register list not in ascending order"));
3416      mask |= 1 << reg;
3417
3418      if (*input_line_pointer == '-')
3419	{
3420	  input_line_pointer++;
3421	  hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3422	  if (hi_reg == FAIL)
3423	    {
3424	      as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
3425	      goto error;
3426	    }
3427	  else if (reg >= hi_reg)
3428	    {
3429	      as_bad (_("bad register range"));
3430	      goto error;
3431	    }
3432	  for (; reg < hi_reg; reg++)
3433	    mask |= 1 << reg;
3434	}
3435    }
3436  while (skip_past_comma (&input_line_pointer) != FAIL);
3437
3438  if (*input_line_pointer == '}')
3439    input_line_pointer++;
3440
3441  demand_empty_rest_of_line ();
3442
3443  /* Generate any deferred opcodes because we're going to be looking at
3444     the list.	*/
3445  flush_pending_unwind ();
3446
3447  for (i = 0; i < 16; i++)
3448    {
3449      if (mask & (1 << i))
3450	unwind.frame_size += 8;
3451    }
3452
3453  /* Attempt to combine with a previous opcode.	 We do this because gcc
3454     likes to output separate unwind directives for a single block of
3455     registers.	 */
3456  if (unwind.opcode_count > 0)
3457    {
3458      i = unwind.opcodes[unwind.opcode_count - 1];
3459      if ((i & 0xf8) == 0xc0)
3460	{
3461	  i &= 7;
3462	  /* Only merge if the blocks are contiguous.  */
3463	  if (i < 6)
3464	    {
3465	      if ((mask & 0xfe00) == (1 << 9))
3466		{
3467		  mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3468		  unwind.opcode_count--;
3469		}
3470	    }
3471	  else if (i == 6 && unwind.opcode_count >= 2)
3472	    {
3473	      i = unwind.opcodes[unwind.opcode_count - 2];
3474	      reg = i >> 4;
3475	      i &= 0xf;
3476
3477	      op = 0xffff << (reg - 1);
3478	      if (reg > 0
3479		  && ((mask & op) == (1u << (reg - 1))))
3480		{
3481		  op = (1 << (reg + i + 1)) - 1;
3482		  op &= ~((1 << reg) - 1);
3483		  mask |= op;
3484		  unwind.opcode_count -= 2;
3485		}
3486	    }
3487	}
3488    }
3489
3490  hi_reg = 15;
3491  /* We want to generate opcodes in the order the registers have been
3492     saved, ie. descending order.  */
3493  for (reg = 15; reg >= -1; reg--)
3494    {
3495      /* Save registers in blocks.  */
3496      if (reg < 0
3497	  || !(mask & (1 << reg)))
3498	{
3499	  /* We found an unsaved reg.  Generate opcodes to save the
3500	     preceeding block.	*/
3501	  if (reg != hi_reg)
3502	    {
3503	      if (reg == 9)
3504		{
3505		  /* Short form.  */
3506		  op = 0xc0 | (hi_reg - 10);
3507		  add_unwind_opcode (op, 1);
3508		}
3509	      else
3510		{
3511		  /* Long form.	 */
3512		  op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3513		  add_unwind_opcode (op, 2);
3514		}
3515	    }
3516	  hi_reg = reg - 1;
3517	}
3518    }
3519
3520  return;
3521error:
3522  ignore_rest_of_line ();
3523}
3524
3525static void
3526s_arm_unwind_save_mmxwcg (void)
3527{
3528  int reg;
3529  int hi_reg;
3530  unsigned mask = 0;
3531  valueT op;
3532
3533  if (*input_line_pointer == '{')
3534    input_line_pointer++;
3535
3536  do
3537    {
3538      reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3539
3540      if (reg == FAIL)
3541	{
3542	  as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
3543	  goto error;
3544	}
3545
3546      reg -= 8;
3547      if (mask >> reg)
3548	as_tsktsk (_("register list not in ascending order"));
3549      mask |= 1 << reg;
3550
3551      if (*input_line_pointer == '-')
3552	{
3553	  input_line_pointer++;
3554	  hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3555	  if (hi_reg == FAIL)
3556	    {
3557	      as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
3558	      goto error;
3559	    }
3560	  else if (reg >= hi_reg)
3561	    {
3562	      as_bad (_("bad register range"));
3563	      goto error;
3564	    }
3565	  for (; reg < hi_reg; reg++)
3566	    mask |= 1 << reg;
3567	}
3568    }
3569  while (skip_past_comma (&input_line_pointer) != FAIL);
3570
3571  if (*input_line_pointer == '}')
3572    input_line_pointer++;
3573
3574  demand_empty_rest_of_line ();
3575
3576  /* Generate any deferred opcodes because we're going to be looking at
3577     the list.	*/
3578  flush_pending_unwind ();
3579
3580  for (reg = 0; reg < 16; reg++)
3581    {
3582      if (mask & (1 << reg))
3583	unwind.frame_size += 4;
3584    }
3585  op = 0xc700 | mask;
3586  add_unwind_opcode (op, 2);
3587  return;
3588error:
3589  ignore_rest_of_line ();
3590}
3591
3592
3593/* Parse an unwind_save directive.
3594   If the argument is non-zero, this is a .vsave directive.  */
3595
3596static void
3597s_arm_unwind_save (int arch_v6)
3598{
3599  char *peek;
3600  struct reg_entry *reg;
3601  bfd_boolean had_brace = FALSE;
3602
3603  /* Figure out what sort of save we have.  */
3604  peek = input_line_pointer;
3605
3606  if (*peek == '{')
3607    {
3608      had_brace = TRUE;
3609      peek++;
3610    }
3611
3612  reg = arm_reg_parse_multi (&peek);
3613
3614  if (!reg)
3615    {
3616      as_bad (_("register expected"));
3617      ignore_rest_of_line ();
3618      return;
3619    }
3620
3621  switch (reg->type)
3622    {
3623    case REG_TYPE_FN:
3624      if (had_brace)
3625	{
3626	  as_bad (_("FPA .unwind_save does not take a register list"));
3627	  ignore_rest_of_line ();
3628	  return;
3629	}
3630      s_arm_unwind_save_fpa (reg->number);
3631      return;
3632
3633    case REG_TYPE_RN:	  s_arm_unwind_save_core ();   return;
3634    case REG_TYPE_VFD:
3635      if (arch_v6)
3636        s_arm_unwind_save_vfp_armv6 ();
3637      else
3638        s_arm_unwind_save_vfp ();
3639      return;
3640    case REG_TYPE_MMXWR:  s_arm_unwind_save_mmxwr ();  return;
3641    case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
3642
3643    default:
3644      as_bad (_(".unwind_save does not support this kind of register"));
3645      ignore_rest_of_line ();
3646    }
3647}
3648
3649
3650/* Parse an unwind_movsp directive.  */
3651
3652static void
3653s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
3654{
3655  int reg;
3656  valueT op;
3657  int offset;
3658
3659  reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3660  if (reg == FAIL)
3661    {
3662      as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
3663      ignore_rest_of_line ();
3664      return;
3665    }
3666
3667  /* Optional constant.	 */
3668  if (skip_past_comma (&input_line_pointer) != FAIL)
3669    {
3670      if (immediate_for_directive (&offset) == FAIL)
3671	return;
3672    }
3673  else
3674    offset = 0;
3675
3676  demand_empty_rest_of_line ();
3677
3678  if (reg == REG_SP || reg == REG_PC)
3679    {
3680      as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3681      return;
3682    }
3683
3684  if (unwind.fp_reg != REG_SP)
3685    as_bad (_("unexpected .unwind_movsp directive"));
3686
3687  /* Generate opcode to restore the value.  */
3688  op = 0x90 | reg;
3689  add_unwind_opcode (op, 1);
3690
3691  /* Record the information for later.	*/
3692  unwind.fp_reg = reg;
3693  unwind.fp_offset = unwind.frame_size - offset;
3694  unwind.sp_restored = 1;
3695}
3696
3697/* Parse an unwind_pad directive.  */
3698
3699static void
3700s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
3701{
3702  int offset;
3703
3704  if (immediate_for_directive (&offset) == FAIL)
3705    return;
3706
3707  if (offset & 3)
3708    {
3709      as_bad (_("stack increment must be multiple of 4"));
3710      ignore_rest_of_line ();
3711      return;
3712    }
3713
3714  /* Don't generate any opcodes, just record the details for later.  */
3715  unwind.frame_size += offset;
3716  unwind.pending_offset += offset;
3717
3718  demand_empty_rest_of_line ();
3719}
3720
3721/* Parse an unwind_setfp directive.  */
3722
3723static void
3724s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
3725{
3726  int sp_reg;
3727  int fp_reg;
3728  int offset;
3729
3730  fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3731  if (skip_past_comma (&input_line_pointer) == FAIL)
3732    sp_reg = FAIL;
3733  else
3734    sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3735
3736  if (fp_reg == FAIL || sp_reg == FAIL)
3737    {
3738      as_bad (_("expected <reg>, <reg>"));
3739      ignore_rest_of_line ();
3740      return;
3741    }
3742
3743  /* Optional constant.	 */
3744  if (skip_past_comma (&input_line_pointer) != FAIL)
3745    {
3746      if (immediate_for_directive (&offset) == FAIL)
3747	return;
3748    }
3749  else
3750    offset = 0;
3751
3752  demand_empty_rest_of_line ();
3753
3754  if (sp_reg != 13 && sp_reg != unwind.fp_reg)
3755    {
3756      as_bad (_("register must be either sp or set by a previous"
3757		"unwind_movsp directive"));
3758      return;
3759    }
3760
3761  /* Don't generate any opcodes, just record the information for later.	 */
3762  unwind.fp_reg = fp_reg;
3763  unwind.fp_used = 1;
3764  if (sp_reg == 13)
3765    unwind.fp_offset = unwind.frame_size - offset;
3766  else
3767    unwind.fp_offset -= offset;
3768}
3769
3770/* Parse an unwind_raw directive.  */
3771
3772static void
3773s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
3774{
3775  expressionS exp;
3776  /* This is an arbitrary limit.	 */
3777  unsigned char op[16];
3778  int count;
3779
3780  expression (&exp);
3781  if (exp.X_op == O_constant
3782      && skip_past_comma (&input_line_pointer) != FAIL)
3783    {
3784      unwind.frame_size += exp.X_add_number;
3785      expression (&exp);
3786    }
3787  else
3788    exp.X_op = O_illegal;
3789
3790  if (exp.X_op != O_constant)
3791    {
3792      as_bad (_("expected <offset>, <opcode>"));
3793      ignore_rest_of_line ();
3794      return;
3795    }
3796
3797  count = 0;
3798
3799  /* Parse the opcode.	*/
3800  for (;;)
3801    {
3802      if (count >= 16)
3803	{
3804	  as_bad (_("unwind opcode too long"));
3805	  ignore_rest_of_line ();
3806	}
3807      if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
3808	{
3809	  as_bad (_("invalid unwind opcode"));
3810	  ignore_rest_of_line ();
3811	  return;
3812	}
3813      op[count++] = exp.X_add_number;
3814
3815      /* Parse the next byte.  */
3816      if (skip_past_comma (&input_line_pointer) == FAIL)
3817	break;
3818
3819      expression (&exp);
3820    }
3821
3822  /* Add the opcode bytes in reverse order.  */
3823  while (count--)
3824    add_unwind_opcode (op[count], 1);
3825
3826  demand_empty_rest_of_line ();
3827}
3828
3829
3830/* Parse a .eabi_attribute directive.  */
3831
3832static void
3833s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
3834{
3835  s_vendor_attribute (OBJ_ATTR_PROC);
3836}
3837#endif /* OBJ_ELF */
3838
3839static void s_arm_arch (int);
3840static void s_arm_arch_extension (int);
3841static void s_arm_object_arch (int);
3842static void s_arm_cpu (int);
3843static void s_arm_fpu (int);
3844
3845#ifdef TE_PE
3846
3847static void
3848pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
3849{
3850  expressionS exp;
3851
3852  do
3853    {
3854      expression (&exp);
3855      if (exp.X_op == O_symbol)
3856	exp.X_op = O_secrel;
3857
3858      emit_expr (&exp, 4);
3859    }
3860  while (*input_line_pointer++ == ',');
3861
3862  input_line_pointer--;
3863  demand_empty_rest_of_line ();
3864}
3865#endif /* TE_PE */
3866
3867/* This table describes all the machine specific pseudo-ops the assembler
3868   has to support.  The fields are:
3869     pseudo-op name without dot
3870     function to call to execute this pseudo-op
3871     Integer arg to pass to the function.  */
3872
3873const pseudo_typeS md_pseudo_table[] =
3874{
3875  /* Never called because '.req' does not start a line.	 */
3876  { "req",	   s_req,	  0 },
3877  /* Following two are likewise never called.  */
3878  { "dn",	   s_dn,          0 },
3879  { "qn",          s_qn,          0 },
3880  { "unreq",	   s_unreq,	  0 },
3881  { "bss",	   s_bss,	  0 },
3882  { "align",	   s_align,	  0 },
3883  { "arm",	   s_arm,	  0 },
3884  { "thumb",	   s_thumb,	  0 },
3885  { "code",	   s_code,	  0 },
3886  { "force_thumb", s_force_thumb, 0 },
3887  { "thumb_func",  s_thumb_func,  0 },
3888  { "thumb_set",   s_thumb_set,	  0 },
3889  { "even",	   s_even,	  0 },
3890  { "ltorg",	   s_ltorg,	  0 },
3891  { "pool",	   s_ltorg,	  0 },
3892  { "syntax",	   s_syntax,	  0 },
3893  { "cpu",	   s_arm_cpu,	  0 },
3894  { "arch",	   s_arm_arch,	  0 },
3895  { "arch_extension",	   s_arm_arch_extension,	  0 },
3896  { "object_arch", s_arm_object_arch,	0 },
3897  { "fpu",	   s_arm_fpu,	  0 },
3898#ifdef OBJ_ELF
3899  { "word",	   s_arm_elf_cons, 4 },
3900  { "long",	   s_arm_elf_cons, 4 },
3901  { "rel31",	   s_arm_rel31,	  0 },
3902  { "fnstart",		s_arm_unwind_fnstart,	0 },
3903  { "fnend",		s_arm_unwind_fnend,	0 },
3904  { "cantunwind",	s_arm_unwind_cantunwind, 0 },
3905  { "personality",	s_arm_unwind_personality, 0 },
3906  { "personalityindex",	s_arm_unwind_personalityindex, 0 },
3907  { "handlerdata",	s_arm_unwind_handlerdata, 0 },
3908  { "save",		s_arm_unwind_save,	0 },
3909  { "vsave",		s_arm_unwind_save,	1 },
3910  { "movsp",		s_arm_unwind_movsp,	0 },
3911  { "pad",		s_arm_unwind_pad,	0 },
3912  { "setfp",		s_arm_unwind_setfp,	0 },
3913  { "unwind_raw",	s_arm_unwind_raw,	0 },
3914  { "eabi_attribute",	s_arm_eabi_attribute,	0 },
3915#else
3916  { "word",	   cons, 4},
3917
3918  /* These are used for dwarf.  */
3919  {"2byte", cons, 2},
3920  {"4byte", cons, 4},
3921  {"8byte", cons, 8},
3922  /* These are used for dwarf2.  */
3923  { "file", (void (*) (int)) dwarf2_directive_file, 0 },
3924  { "loc",  dwarf2_directive_loc,  0 },
3925  { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
3926#endif
3927  { "extend",	   float_cons, 'x' },
3928  { "ldouble",	   float_cons, 'x' },
3929  { "packed",	   float_cons, 'p' },
3930#ifdef TE_PE
3931  {"secrel32", pe_directive_secrel, 0},
3932#endif
3933  { 0, 0, 0 }
3934};
3935
3936/* Parser functions used exclusively in instruction operands.  */
3937
3938/* Generic immediate-value read function for use in insn parsing.
3939   STR points to the beginning of the immediate (the leading #);
3940   VAL receives the value; if the value is outside [MIN, MAX]
3941   issue an error.  PREFIX_OPT is true if the immediate prefix is
3942   optional.  */
3943
3944static int
3945parse_immediate (char **str, int *val, int min, int max,
3946		 bfd_boolean prefix_opt)
3947{
3948  expressionS exp;
3949  my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
3950  if (exp.X_op != O_constant)
3951    {
3952      inst.error = _("constant expression required");
3953      return FAIL;
3954    }
3955
3956  if (exp.X_add_number < min || exp.X_add_number > max)
3957    {
3958      inst.error = _("immediate value out of range");
3959      return FAIL;
3960    }
3961
3962  *val = exp.X_add_number;
3963  return SUCCESS;
3964}
3965
3966/* Less-generic immediate-value read function with the possibility of loading a
3967   big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
3968   instructions. Puts the result directly in inst.operands[i].  */
3969
3970static int
3971parse_big_immediate (char **str, int i)
3972{
3973  expressionS exp;
3974  char *ptr = *str;
3975
3976  my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
3977
3978  if (exp.X_op == O_constant)
3979    {
3980      inst.operands[i].imm = exp.X_add_number & 0xffffffff;
3981      /* If we're on a 64-bit host, then a 64-bit number can be returned using
3982	 O_constant.  We have to be careful not to break compilation for
3983	 32-bit X_add_number, though.  */
3984      if ((exp.X_add_number & ~0xffffffffl) != 0)
3985	{
3986          /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4.  */
3987	  inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
3988	  inst.operands[i].regisimm = 1;
3989	}
3990    }
3991  else if (exp.X_op == O_big
3992           && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32
3993           && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64)
3994    {
3995      unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
3996      /* Bignums have their least significant bits in
3997         generic_bignum[0]. Make sure we put 32 bits in imm and
3998         32 bits in reg,  in a (hopefully) portable way.  */
3999      assert (parts != 0);
4000      inst.operands[i].imm = 0;
4001      for (j = 0; j < parts; j++, idx++)
4002        inst.operands[i].imm |= generic_bignum[idx]
4003                                << (LITTLENUM_NUMBER_OF_BITS * j);
4004      inst.operands[i].reg = 0;
4005      for (j = 0; j < parts; j++, idx++)
4006        inst.operands[i].reg |= generic_bignum[idx]
4007                                << (LITTLENUM_NUMBER_OF_BITS * j);
4008      inst.operands[i].regisimm = 1;
4009    }
4010  else
4011    return FAIL;
4012
4013  *str = ptr;
4014
4015  return SUCCESS;
4016}
4017
4018/* Returns the pseudo-register number of an FPA immediate constant,
4019   or FAIL if there isn't a valid constant here.  */
4020
4021static int
4022parse_fpa_immediate (char ** str)
4023{
4024  LITTLENUM_TYPE words[MAX_LITTLENUMS];
4025  char *	 save_in;
4026  expressionS	 exp;
4027  int		 i;
4028  int		 j;
4029
4030  /* First try and match exact strings, this is to guarantee
4031     that some formats will work even for cross assembly.  */
4032
4033  for (i = 0; fp_const[i]; i++)
4034    {
4035      if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4036	{
4037	  char *start = *str;
4038
4039	  *str += strlen (fp_const[i]);
4040	  if (is_end_of_line[(unsigned char) **str])
4041	    return i + 8;
4042	  *str = start;
4043	}
4044    }
4045
4046  /* Just because we didn't get a match doesn't mean that the constant
4047     isn't valid, just that it is in a format that we don't
4048     automatically recognize.  Try parsing it with the standard
4049     expression routines.  */
4050
4051  memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4052
4053  /* Look for a raw floating point number.  */
4054  if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4055      && is_end_of_line[(unsigned char) *save_in])
4056    {
4057      for (i = 0; i < NUM_FLOAT_VALS; i++)
4058	{
4059	  for (j = 0; j < MAX_LITTLENUMS; j++)
4060	    {
4061	      if (words[j] != fp_values[i][j])
4062		break;
4063	    }
4064
4065	  if (j == MAX_LITTLENUMS)
4066	    {
4067	      *str = save_in;
4068	      return i + 8;
4069	    }
4070	}
4071    }
4072
4073  /* Try and parse a more complex expression, this will probably fail
4074     unless the code uses a floating point prefix (eg "0f").  */
4075  save_in = input_line_pointer;
4076  input_line_pointer = *str;
4077  if (expression (&exp) == absolute_section
4078      && exp.X_op == O_big
4079      && exp.X_add_number < 0)
4080    {
4081      /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4082	 Ditto for 15.	*/
4083      if (gen_to_words (words, 5, (long) 15) == 0)
4084	{
4085	  for (i = 0; i < NUM_FLOAT_VALS; i++)
4086	    {
4087	      for (j = 0; j < MAX_LITTLENUMS; j++)
4088		{
4089		  if (words[j] != fp_values[i][j])
4090		    break;
4091		}
4092
4093	      if (j == MAX_LITTLENUMS)
4094		{
4095		  *str = input_line_pointer;
4096		  input_line_pointer = save_in;
4097		  return i + 8;
4098		}
4099	    }
4100	}
4101    }
4102
4103  *str = input_line_pointer;
4104  input_line_pointer = save_in;
4105  inst.error = _("invalid FPA immediate expression");
4106  return FAIL;
4107}
4108
4109/* Returns 1 if a number has "quarter-precision" float format
4110   0baBbbbbbc defgh000 00000000 00000000.  */
4111
4112static int
4113is_quarter_float (unsigned imm)
4114{
4115  int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4116  return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4117}
4118
4119/* Parse an 8-bit "quarter-precision" floating point number of the form:
4120   0baBbbbbbc defgh000 00000000 00000000.
4121   The zero and minus-zero cases need special handling, since they can't be
4122   encoded in the "quarter-precision" float format, but can nonetheless be
4123   loaded as integer constants.  */
4124
4125static unsigned
4126parse_qfloat_immediate (char **ccp, int *immed)
4127{
4128  char *str = *ccp;
4129  char *fpnum;
4130  LITTLENUM_TYPE words[MAX_LITTLENUMS];
4131  int found_fpchar = 0;
4132
4133  skip_past_char (&str, '#');
4134
4135  /* We must not accidentally parse an integer as a floating-point number. Make
4136     sure that the value we parse is not an integer by checking for special
4137     characters '.' or 'e'.
4138     FIXME: This is a horrible hack, but doing better is tricky because type
4139     information isn't in a very usable state at parse time.  */
4140  fpnum = str;
4141  skip_whitespace (fpnum);
4142
4143  if (strncmp (fpnum, "0x", 2) == 0)
4144    return FAIL;
4145  else
4146    {
4147      for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4148        if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4149          {
4150            found_fpchar = 1;
4151            break;
4152          }
4153
4154      if (!found_fpchar)
4155        return FAIL;
4156    }
4157
4158  if ((str = atof_ieee (str, 's', words)) != NULL)
4159    {
4160      unsigned fpword = 0;
4161      int i;
4162
4163      /* Our FP word must be 32 bits (single-precision FP).  */
4164      for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4165        {
4166          fpword <<= LITTLENUM_NUMBER_OF_BITS;
4167          fpword |= words[i];
4168        }
4169
4170      if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4171        *immed = fpword;
4172      else
4173        return FAIL;
4174
4175      *ccp = str;
4176
4177      return SUCCESS;
4178    }
4179
4180  return FAIL;
4181}
4182
4183/* Shift operands.  */
4184enum shift_kind
4185{
4186  SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4187};
4188
4189struct asm_shift_name
4190{
4191  const char	  *name;
4192  enum shift_kind  kind;
4193};
4194
4195/* Third argument to parse_shift.  */
4196enum parse_shift_mode
4197{
4198  NO_SHIFT_RESTRICT,		/* Any kind of shift is accepted.  */
4199  SHIFT_IMMEDIATE,		/* Shift operand must be an immediate.	*/
4200  SHIFT_LSL_OR_ASR_IMMEDIATE,	/* Shift must be LSL or ASR immediate.	*/
4201  SHIFT_ASR_IMMEDIATE,		/* Shift must be ASR immediate.	 */
4202  SHIFT_LSL_IMMEDIATE,		/* Shift must be LSL immediate.	 */
4203};
4204
4205/* Parse a <shift> specifier on an ARM data processing instruction.
4206   This has three forms:
4207
4208     (LSL|LSR|ASL|ASR|ROR) Rs
4209     (LSL|LSR|ASL|ASR|ROR) #imm
4210     RRX
4211
4212   Note that ASL is assimilated to LSL in the instruction encoding, and
4213   RRX to ROR #0 (which cannot be written as such).  */
4214
4215static int
4216parse_shift (char **str, int i, enum parse_shift_mode mode)
4217{
4218  const struct asm_shift_name *shift_name;
4219  enum shift_kind shift;
4220  char *s = *str;
4221  char *p = s;
4222  int reg;
4223
4224  for (p = *str; ISALPHA (*p); p++)
4225    ;
4226
4227  if (p == *str)
4228    {
4229      inst.error = _("shift expression expected");
4230      return FAIL;
4231    }
4232
4233  shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
4234
4235  if (shift_name == NULL)
4236    {
4237      inst.error = _("shift expression expected");
4238      return FAIL;
4239    }
4240
4241  shift = shift_name->kind;
4242
4243  switch (mode)
4244    {
4245    case NO_SHIFT_RESTRICT:
4246    case SHIFT_IMMEDIATE:   break;
4247
4248    case SHIFT_LSL_OR_ASR_IMMEDIATE:
4249      if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4250	{
4251	  inst.error = _("'LSL' or 'ASR' required");
4252	  return FAIL;
4253	}
4254      break;
4255
4256    case SHIFT_LSL_IMMEDIATE:
4257      if (shift != SHIFT_LSL)
4258	{
4259	  inst.error = _("'LSL' required");
4260	  return FAIL;
4261	}
4262      break;
4263
4264    case SHIFT_ASR_IMMEDIATE:
4265      if (shift != SHIFT_ASR)
4266	{
4267	  inst.error = _("'ASR' required");
4268	  return FAIL;
4269	}
4270      break;
4271
4272    default: abort ();
4273    }
4274
4275  if (shift != SHIFT_RRX)
4276    {
4277      /* Whitespace can appear here if the next thing is a bare digit.	*/
4278      skip_whitespace (p);
4279
4280      if (mode == NO_SHIFT_RESTRICT
4281	  && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4282	{
4283	  inst.operands[i].imm = reg;
4284	  inst.operands[i].immisreg = 1;
4285	}
4286      else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4287	return FAIL;
4288    }
4289  inst.operands[i].shift_kind = shift;
4290  inst.operands[i].shifted = 1;
4291  *str = p;
4292  return SUCCESS;
4293}
4294
4295/* Parse a <shifter_operand> for an ARM data processing instruction:
4296
4297      #<immediate>
4298      #<immediate>, <rotate>
4299      <Rm>
4300      <Rm>, <shift>
4301
4302   where <shift> is defined by parse_shift above, and <rotate> is a
4303   multiple of 2 between 0 and 30.  Validation of immediate operands
4304   is deferred to md_apply_fix.  */
4305
4306static int
4307parse_shifter_operand (char **str, int i)
4308{
4309  int value;
4310  expressionS expr;
4311
4312  if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4313    {
4314      inst.operands[i].reg = value;
4315      inst.operands[i].isreg = 1;
4316
4317      /* parse_shift will override this if appropriate */
4318      inst.reloc.exp.X_op = O_constant;
4319      inst.reloc.exp.X_add_number = 0;
4320
4321      if (skip_past_comma (str) == FAIL)
4322	return SUCCESS;
4323
4324      /* Shift operation on register.  */
4325      return parse_shift (str, i, NO_SHIFT_RESTRICT);
4326    }
4327
4328  if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4329    return FAIL;
4330
4331  if (skip_past_comma (str) == SUCCESS)
4332    {
4333      /* #x, y -- ie explicit rotation by Y.  */
4334      if (my_get_expression (&expr, str, GE_NO_PREFIX))
4335	return FAIL;
4336
4337      if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4338	{
4339	  inst.error = _("constant expression expected");
4340	  return FAIL;
4341	}
4342
4343      value = expr.X_add_number;
4344      if (value < 0 || value > 30 || value % 2 != 0)
4345	{
4346	  inst.error = _("invalid rotation");
4347	  return FAIL;
4348	}
4349      if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4350	{
4351	  inst.error = _("invalid constant");
4352	  return FAIL;
4353	}
4354
4355      /* Convert to decoded value.  md_apply_fix will put it back.  */
4356      inst.reloc.exp.X_add_number
4357	= (((inst.reloc.exp.X_add_number << (32 - value))
4358	    | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
4359    }
4360
4361  inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4362  inst.reloc.pc_rel = 0;
4363  return SUCCESS;
4364}
4365
4366/* Group relocation information.  Each entry in the table contains the
4367   textual name of the relocation as may appear in assembler source
4368   and must end with a colon.
4369   Along with this textual name are the relocation codes to be used if
4370   the corresponding instruction is an ALU instruction (ADD or SUB only),
4371   an LDR, an LDRS, or an LDC.  */
4372
4373struct group_reloc_table_entry
4374{
4375  const char *name;
4376  int alu_code;
4377  int ldr_code;
4378  int ldrs_code;
4379  int ldc_code;
4380};
4381
4382typedef enum
4383{
4384  /* Varieties of non-ALU group relocation.  */
4385
4386  GROUP_LDR,
4387  GROUP_LDRS,
4388  GROUP_LDC
4389} group_reloc_type;
4390
4391static struct group_reloc_table_entry group_reloc_table[] =
4392  { /* Program counter relative: */
4393    { "pc_g0_nc",
4394      BFD_RELOC_ARM_ALU_PC_G0_NC,	/* ALU */
4395      0,				/* LDR */
4396      0,				/* LDRS */
4397      0 },				/* LDC */
4398    { "pc_g0",
4399      BFD_RELOC_ARM_ALU_PC_G0,		/* ALU */
4400      BFD_RELOC_ARM_LDR_PC_G0,		/* LDR */
4401      BFD_RELOC_ARM_LDRS_PC_G0,		/* LDRS */
4402      BFD_RELOC_ARM_LDC_PC_G0 },	/* LDC */
4403    { "pc_g1_nc",
4404      BFD_RELOC_ARM_ALU_PC_G1_NC,	/* ALU */
4405      0,				/* LDR */
4406      0,				/* LDRS */
4407      0 },				/* LDC */
4408    { "pc_g1",
4409      BFD_RELOC_ARM_ALU_PC_G1,		/* ALU */
4410      BFD_RELOC_ARM_LDR_PC_G1, 		/* LDR */
4411      BFD_RELOC_ARM_LDRS_PC_G1,		/* LDRS */
4412      BFD_RELOC_ARM_LDC_PC_G1 },	/* LDC */
4413    { "pc_g2",
4414      BFD_RELOC_ARM_ALU_PC_G2,		/* ALU */
4415      BFD_RELOC_ARM_LDR_PC_G2,		/* LDR */
4416      BFD_RELOC_ARM_LDRS_PC_G2,		/* LDRS */
4417      BFD_RELOC_ARM_LDC_PC_G2 },	/* LDC */
4418    /* Section base relative */
4419    { "sb_g0_nc",
4420      BFD_RELOC_ARM_ALU_SB_G0_NC,	/* ALU */
4421      0,				/* LDR */
4422      0,				/* LDRS */
4423      0 },				/* LDC */
4424    { "sb_g0",
4425      BFD_RELOC_ARM_ALU_SB_G0,		/* ALU */
4426      BFD_RELOC_ARM_LDR_SB_G0,		/* LDR */
4427      BFD_RELOC_ARM_LDRS_SB_G0,		/* LDRS */
4428      BFD_RELOC_ARM_LDC_SB_G0 },	/* LDC */
4429    { "sb_g1_nc",
4430      BFD_RELOC_ARM_ALU_SB_G1_NC,	/* ALU */
4431      0,				/* LDR */
4432      0,				/* LDRS */
4433      0 },				/* LDC */
4434    { "sb_g1",
4435      BFD_RELOC_ARM_ALU_SB_G1,		/* ALU */
4436      BFD_RELOC_ARM_LDR_SB_G1, 		/* LDR */
4437      BFD_RELOC_ARM_LDRS_SB_G1,		/* LDRS */
4438      BFD_RELOC_ARM_LDC_SB_G1 },	/* LDC */
4439    { "sb_g2",
4440      BFD_RELOC_ARM_ALU_SB_G2,		/* ALU */
4441      BFD_RELOC_ARM_LDR_SB_G2,		/* LDR */
4442      BFD_RELOC_ARM_LDRS_SB_G2,		/* LDRS */
4443      BFD_RELOC_ARM_LDC_SB_G2 }	};	/* LDC */
4444
4445/* Given the address of a pointer pointing to the textual name of a group
4446   relocation as may appear in assembler source, attempt to find its details
4447   in group_reloc_table.  The pointer will be updated to the character after
4448   the trailing colon.  On failure, FAIL will be returned; SUCCESS
4449   otherwise.  On success, *entry will be updated to point at the relevant
4450   group_reloc_table entry. */
4451
4452static int
4453find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4454{
4455  unsigned int i;
4456  for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4457    {
4458      int length = strlen (group_reloc_table[i].name);
4459
4460      if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 &&
4461          (*str)[length] == ':')
4462        {
4463          *out = &group_reloc_table[i];
4464          *str += (length + 1);
4465          return SUCCESS;
4466        }
4467    }
4468
4469  return FAIL;
4470}
4471
4472/* Parse a <shifter_operand> for an ARM data processing instruction
4473   (as for parse_shifter_operand) where group relocations are allowed:
4474
4475      #<immediate>
4476      #<immediate>, <rotate>
4477      #:<group_reloc>:<expression>
4478      <Rm>
4479      <Rm>, <shift>
4480
4481   where <group_reloc> is one of the strings defined in group_reloc_table.
4482   The hashes are optional.
4483
4484   Everything else is as for parse_shifter_operand.  */
4485
4486static parse_operand_result
4487parse_shifter_operand_group_reloc (char **str, int i)
4488{
4489  /* Determine if we have the sequence of characters #: or just :
4490     coming next.  If we do, then we check for a group relocation.
4491     If we don't, punt the whole lot to parse_shifter_operand.  */
4492
4493  if (((*str)[0] == '#' && (*str)[1] == ':')
4494      || (*str)[0] == ':')
4495    {
4496      struct group_reloc_table_entry *entry;
4497
4498      if ((*str)[0] == '#')
4499        (*str) += 2;
4500      else
4501        (*str)++;
4502
4503      /* Try to parse a group relocation.  Anything else is an error.  */
4504      if (find_group_reloc_table_entry (str, &entry) == FAIL)
4505        {
4506          inst.error = _("unknown group relocation");
4507          return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4508        }
4509
4510      /* We now have the group relocation table entry corresponding to
4511         the name in the assembler source.  Next, we parse the expression.  */
4512      if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
4513        return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4514
4515      /* Record the relocation type (always the ALU variant here).  */
4516      inst.reloc.type = entry->alu_code;
4517      assert (inst.reloc.type != 0);
4518
4519      return PARSE_OPERAND_SUCCESS;
4520    }
4521  else
4522    return parse_shifter_operand (str, i) == SUCCESS
4523           ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4524
4525  /* Never reached.  */
4526}
4527
4528/* Parse all forms of an ARM address expression.  Information is written
4529   to inst.operands[i] and/or inst.reloc.
4530
4531   Preindexed addressing (.preind=1):
4532
4533   [Rn, #offset]       .reg=Rn .reloc.exp=offset
4534   [Rn, +/-Rm]	       .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4535   [Rn, +/-Rm, shift]  .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4536		       .shift_kind=shift .reloc.exp=shift_imm
4537
4538   These three may have a trailing ! which causes .writeback to be set also.
4539
4540   Postindexed addressing (.postind=1, .writeback=1):
4541
4542   [Rn], #offset       .reg=Rn .reloc.exp=offset
4543   [Rn], +/-Rm	       .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4544   [Rn], +/-Rm, shift  .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4545		       .shift_kind=shift .reloc.exp=shift_imm
4546
4547   Unindexed addressing (.preind=0, .postind=0):
4548
4549   [Rn], {option}      .reg=Rn .imm=option .immisreg=0
4550
4551   Other:
4552
4553   [Rn]{!}	       shorthand for [Rn,#0]{!}
4554   =immediate	       .isreg=0 .reloc.exp=immediate
4555   label	       .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4556
4557  It is the caller's responsibility to check for addressing modes not
4558  supported by the instruction, and to set inst.reloc.type.  */
4559
4560static parse_operand_result
4561parse_address_main (char **str, int i, int group_relocations,
4562                    group_reloc_type group_type)
4563{
4564  char *p = *str;
4565  int reg;
4566
4567  if (skip_past_char (&p, '[') == FAIL)
4568    {
4569      if (skip_past_char (&p, '=') == FAIL)
4570	{
4571	  /* bare address - translate to PC-relative offset */
4572	  inst.reloc.pc_rel = 1;
4573	  inst.operands[i].reg = REG_PC;
4574	  inst.operands[i].isreg = 1;
4575	  inst.operands[i].preind = 1;
4576	}
4577      /* else a load-constant pseudo op, no special treatment needed here */
4578
4579      if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4580	return PARSE_OPERAND_FAIL;
4581
4582      *str = p;
4583      return PARSE_OPERAND_SUCCESS;
4584    }
4585
4586  if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
4587    {
4588      inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4589      return PARSE_OPERAND_FAIL;
4590    }
4591  inst.operands[i].reg = reg;
4592  inst.operands[i].isreg = 1;
4593
4594  if (skip_past_comma (&p) == SUCCESS)
4595    {
4596      inst.operands[i].preind = 1;
4597
4598      if (*p == '+') p++;
4599      else if (*p == '-') p++, inst.operands[i].negative = 1;
4600
4601      if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4602	{
4603	  inst.operands[i].imm = reg;
4604	  inst.operands[i].immisreg = 1;
4605
4606	  if (skip_past_comma (&p) == SUCCESS)
4607	    if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4608	      return PARSE_OPERAND_FAIL;
4609	}
4610      else if (skip_past_char (&p, ':') == SUCCESS)
4611        {
4612          /* FIXME: '@' should be used here, but it's filtered out by generic
4613             code before we get to see it here. This may be subject to
4614             change.  */
4615          expressionS exp;
4616          my_get_expression (&exp, &p, GE_NO_PREFIX);
4617          if (exp.X_op != O_constant)
4618            {
4619              inst.error = _("alignment must be constant");
4620              return PARSE_OPERAND_FAIL;
4621            }
4622          inst.operands[i].imm = exp.X_add_number << 8;
4623          inst.operands[i].immisalign = 1;
4624          /* Alignments are not pre-indexes.  */
4625          inst.operands[i].preind = 0;
4626        }
4627      else
4628	{
4629	  if (inst.operands[i].negative)
4630	    {
4631	      inst.operands[i].negative = 0;
4632	      p--;
4633	    }
4634
4635	  if (group_relocations &&
4636              ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4637
4638	    {
4639	      struct group_reloc_table_entry *entry;
4640
4641              /* Skip over the #: or : sequence.  */
4642              if (*p == '#')
4643                p += 2;
4644              else
4645                p++;
4646
4647	      /* Try to parse a group relocation.  Anything else is an
4648                 error.  */
4649	      if (find_group_reloc_table_entry (&p, &entry) == FAIL)
4650		{
4651		  inst.error = _("unknown group relocation");
4652		  return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4653		}
4654
4655	      /* We now have the group relocation table entry corresponding to
4656		 the name in the assembler source.  Next, we parse the
4657                 expression.  */
4658	      if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4659		return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4660
4661	      /* Record the relocation type.  */
4662              switch (group_type)
4663                {
4664                  case GROUP_LDR:
4665	            inst.reloc.type = entry->ldr_code;
4666                    break;
4667
4668                  case GROUP_LDRS:
4669	            inst.reloc.type = entry->ldrs_code;
4670                    break;
4671
4672                  case GROUP_LDC:
4673	            inst.reloc.type = entry->ldc_code;
4674                    break;
4675
4676                  default:
4677                    assert (0);
4678                }
4679
4680              if (inst.reloc.type == 0)
4681		{
4682		  inst.error = _("this group relocation is not allowed on this instruction");
4683		  return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4684		}
4685            }
4686          else
4687	    if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4688	      return PARSE_OPERAND_FAIL;
4689	}
4690    }
4691  else if (skip_past_char (&p, ':') == SUCCESS)
4692    {
4693      /* FIXME: '@' should be used here, but it's filtered out by generic
4694         code before we get to see it here. This may be subject to
4695         change.  */
4696      expressionS exp;
4697      my_get_expression (&exp, &p, GE_NO_PREFIX);
4698      if (exp.X_op != O_constant)
4699        {
4700          inst.error = _("alignment must be constant");
4701          return PARSE_OPERAND_FAIL;
4702        }
4703      inst.operands[i].imm = exp.X_add_number << 8;
4704      inst.operands[i].immisalign = 1;
4705      /* Alignments are not pre-indexes.  */
4706      inst.operands[i].preind = 0;
4707    }
4708
4709  if (skip_past_char (&p, ']') == FAIL)
4710    {
4711      inst.error = _("']' expected");
4712      return PARSE_OPERAND_FAIL;
4713    }
4714
4715  if (skip_past_char (&p, '!') == SUCCESS)
4716    inst.operands[i].writeback = 1;
4717
4718  else if (skip_past_comma (&p) == SUCCESS)
4719    {
4720      if (skip_past_char (&p, '{') == SUCCESS)
4721	{
4722	  /* [Rn], {expr} - unindexed, with option */
4723	  if (parse_immediate (&p, &inst.operands[i].imm,
4724			       0, 255, TRUE) == FAIL)
4725	    return PARSE_OPERAND_FAIL;
4726
4727	  if (skip_past_char (&p, '}') == FAIL)
4728	    {
4729	      inst.error = _("'}' expected at end of 'option' field");
4730	      return PARSE_OPERAND_FAIL;
4731	    }
4732	  if (inst.operands[i].preind)
4733	    {
4734	      inst.error = _("cannot combine index with option");
4735	      return PARSE_OPERAND_FAIL;
4736	    }
4737	  *str = p;
4738	  return PARSE_OPERAND_SUCCESS;
4739	}
4740      else
4741	{
4742	  inst.operands[i].postind = 1;
4743	  inst.operands[i].writeback = 1;
4744
4745	  if (inst.operands[i].preind)
4746	    {
4747	      inst.error = _("cannot combine pre- and post-indexing");
4748	      return PARSE_OPERAND_FAIL;
4749	    }
4750
4751	  if (*p == '+') p++;
4752	  else if (*p == '-') p++, inst.operands[i].negative = 1;
4753
4754	  if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4755	    {
4756              /* We might be using the immediate for alignment already. If we
4757                 are, OR the register number into the low-order bits.  */
4758              if (inst.operands[i].immisalign)
4759	        inst.operands[i].imm |= reg;
4760              else
4761                inst.operands[i].imm = reg;
4762	      inst.operands[i].immisreg = 1;
4763
4764	      if (skip_past_comma (&p) == SUCCESS)
4765		if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4766		  return PARSE_OPERAND_FAIL;
4767	    }
4768	  else
4769	    {
4770	      if (inst.operands[i].negative)
4771		{
4772		  inst.operands[i].negative = 0;
4773		  p--;
4774		}
4775	      if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4776		return PARSE_OPERAND_FAIL;
4777	    }
4778	}
4779    }
4780
4781  /* If at this point neither .preind nor .postind is set, we have a
4782     bare [Rn]{!}, which is shorthand for [Rn,#0]{!}.  */
4783  if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
4784    {
4785      inst.operands[i].preind = 1;
4786      inst.reloc.exp.X_op = O_constant;
4787      inst.reloc.exp.X_add_number = 0;
4788    }
4789  *str = p;
4790  return PARSE_OPERAND_SUCCESS;
4791}
4792
4793static int
4794parse_address (char **str, int i)
4795{
4796  return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS
4797         ? SUCCESS : FAIL;
4798}
4799
4800static parse_operand_result
4801parse_address_group_reloc (char **str, int i, group_reloc_type type)
4802{
4803  return parse_address_main (str, i, 1, type);
4804}
4805
4806/* Parse an operand for a MOVW or MOVT instruction.  */
4807static int
4808parse_half (char **str)
4809{
4810  char * p;
4811
4812  p = *str;
4813  skip_past_char (&p, '#');
4814  if (strncasecmp (p, ":lower16:", 9) == 0)
4815    inst.reloc.type = BFD_RELOC_ARM_MOVW;
4816  else if (strncasecmp (p, ":upper16:", 9) == 0)
4817    inst.reloc.type = BFD_RELOC_ARM_MOVT;
4818
4819  if (inst.reloc.type != BFD_RELOC_UNUSED)
4820    {
4821      p += 9;
4822      skip_whitespace(p);
4823    }
4824
4825  if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4826    return FAIL;
4827
4828  if (inst.reloc.type == BFD_RELOC_UNUSED)
4829    {
4830      if (inst.reloc.exp.X_op != O_constant)
4831	{
4832	  inst.error = _("constant expression expected");
4833	  return FAIL;
4834	}
4835      if (inst.reloc.exp.X_add_number < 0
4836	  || inst.reloc.exp.X_add_number > 0xffff)
4837	{
4838	  inst.error = _("immediate value out of range");
4839	  return FAIL;
4840	}
4841    }
4842  *str = p;
4843  return SUCCESS;
4844}
4845
4846/* Miscellaneous. */
4847
4848/* Parse a PSR flag operand.  The value returned is FAIL on syntax error,
4849   or a bitmask suitable to be or-ed into the ARM msr instruction.  */
4850static int
4851parse_psr (char **str)
4852{
4853  char *p;
4854  unsigned long psr_field;
4855  const struct asm_psr *psr;
4856  char *start;
4857
4858  /* CPSR's and SPSR's can now be lowercase.  This is just a convenience
4859     feature for ease of use and backwards compatibility.  */
4860  p = *str;
4861  if (strncasecmp (p, "SPSR", 4) == 0)
4862    psr_field = SPSR_BIT;
4863  else if (strncasecmp (p, "CPSR", 4) == 0)
4864    psr_field = 0;
4865  else
4866    {
4867      start = p;
4868      do
4869	p++;
4870      while (ISALNUM (*p) || *p == '_');
4871
4872      psr = hash_find_n (arm_v7m_psr_hsh, start, p - start);
4873      if (!psr)
4874	return FAIL;
4875
4876      *str = p;
4877      return psr->field;
4878    }
4879
4880  p += 4;
4881  if (*p == '_')
4882    {
4883      /* A suffix follows.  */
4884      p++;
4885      start = p;
4886
4887      do
4888	p++;
4889      while (ISALNUM (*p) || *p == '_');
4890
4891      psr = hash_find_n (arm_psr_hsh, start, p - start);
4892      if (!psr)
4893	goto error;
4894
4895      psr_field |= psr->field;
4896    }
4897  else
4898    {
4899      if (ISALNUM (*p))
4900	goto error;    /* Garbage after "[CS]PSR".  */
4901
4902      psr_field |= (PSR_c | PSR_f);
4903    }
4904  *str = p;
4905  return psr_field;
4906
4907 error:
4908  inst.error = _("flag for {c}psr instruction expected");
4909  return FAIL;
4910}
4911
4912/* Parse the flags argument to CPSI[ED].  Returns FAIL on error, or a
4913   value suitable for splatting into the AIF field of the instruction.	*/
4914
4915static int
4916parse_cps_flags (char **str)
4917{
4918  int val = 0;
4919  int saw_a_flag = 0;
4920  char *s = *str;
4921
4922  for (;;)
4923    switch (*s++)
4924      {
4925      case '\0': case ',':
4926	goto done;
4927
4928      case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
4929      case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
4930      case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
4931
4932      default:
4933	inst.error = _("unrecognized CPS flag");
4934	return FAIL;
4935      }
4936
4937 done:
4938  if (saw_a_flag == 0)
4939    {
4940      inst.error = _("missing CPS flags");
4941      return FAIL;
4942    }
4943
4944  *str = s - 1;
4945  return val;
4946}
4947
4948/* Parse an endian specifier ("BE" or "LE", case insensitive);
4949   returns 0 for big-endian, 1 for little-endian, FAIL for an error.  */
4950
4951static int
4952parse_endian_specifier (char **str)
4953{
4954  int little_endian;
4955  char *s = *str;
4956
4957  if (strncasecmp (s, "BE", 2))
4958    little_endian = 0;
4959  else if (strncasecmp (s, "LE", 2))
4960    little_endian = 1;
4961  else
4962    {
4963      inst.error = _("valid endian specifiers are be or le");
4964      return FAIL;
4965    }
4966
4967  if (ISALNUM (s[2]) || s[2] == '_')
4968    {
4969      inst.error = _("valid endian specifiers are be or le");
4970      return FAIL;
4971    }
4972
4973  *str = s + 2;
4974  return little_endian;
4975}
4976
4977/* Parse a rotation specifier: ROR #0, #8, #16, #24.  *val receives a
4978   value suitable for poking into the rotate field of an sxt or sxta
4979   instruction, or FAIL on error.  */
4980
4981static int
4982parse_ror (char **str)
4983{
4984  int rot;
4985  char *s = *str;
4986
4987  if (strncasecmp (s, "ROR", 3) == 0)
4988    s += 3;
4989  else
4990    {
4991      inst.error = _("missing rotation field after comma");
4992      return FAIL;
4993    }
4994
4995  if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
4996    return FAIL;
4997
4998  switch (rot)
4999    {
5000    case  0: *str = s; return 0x0;
5001    case  8: *str = s; return 0x1;
5002    case 16: *str = s; return 0x2;
5003    case 24: *str = s; return 0x3;
5004
5005    default:
5006      inst.error = _("rotation can only be 0, 8, 16, or 24");
5007      return FAIL;
5008    }
5009}
5010
5011/* Parse a conditional code (from conds[] below).  The value returned is in the
5012   range 0 .. 14, or FAIL.  */
5013static int
5014parse_cond (char **str)
5015{
5016  char *p, *q;
5017  const struct asm_cond *c;
5018
5019  p = q = *str;
5020  while (ISALPHA (*q))
5021    q++;
5022
5023  c = hash_find_n (arm_cond_hsh, p, q - p);
5024  if (!c)
5025    {
5026      inst.error = _("condition required");
5027      return FAIL;
5028    }
5029
5030  *str = q;
5031  return c->value;
5032}
5033
5034/* Parse an option for a barrier instruction.  Returns the encoding for the
5035   option, or FAIL.  */
5036static int
5037parse_barrier (char **str)
5038{
5039  char *p, *q;
5040  const struct asm_barrier_opt *o;
5041
5042  p = q = *str;
5043  while (ISALPHA (*q))
5044    q++;
5045
5046  o = hash_find_n (arm_barrier_opt_hsh, p, q - p);
5047  if (!o)
5048    return FAIL;
5049
5050  *str = q;
5051  return o->value;
5052}
5053
5054/* Parse the operands of a table branch instruction.  Similar to a memory
5055   operand.  */
5056static int
5057parse_tb (char **str)
5058{
5059  char * p = *str;
5060  int reg;
5061
5062  if (skip_past_char (&p, '[') == FAIL)
5063    {
5064      inst.error = _("'[' expected");
5065      return FAIL;
5066    }
5067
5068  if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5069    {
5070      inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5071      return FAIL;
5072    }
5073  inst.operands[0].reg = reg;
5074
5075  if (skip_past_comma (&p) == FAIL)
5076    {
5077      inst.error = _("',' expected");
5078      return FAIL;
5079    }
5080
5081  if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5082    {
5083      inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5084      return FAIL;
5085    }
5086  inst.operands[0].imm = reg;
5087
5088  if (skip_past_comma (&p) == SUCCESS)
5089    {
5090      if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5091	return FAIL;
5092      if (inst.reloc.exp.X_add_number != 1)
5093	{
5094	  inst.error = _("invalid shift");
5095	  return FAIL;
5096	}
5097      inst.operands[0].shifted = 1;
5098    }
5099
5100  if (skip_past_char (&p, ']') == FAIL)
5101    {
5102      inst.error = _("']' expected");
5103      return FAIL;
5104    }
5105  *str = p;
5106  return SUCCESS;
5107}
5108
5109/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5110   information on the types the operands can take and how they are encoded.
5111   Up to four operands may be read; this function handles setting the
5112   ".present" field for each read operand itself.
5113   Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5114   else returns FAIL.  */
5115
5116static int
5117parse_neon_mov (char **str, int *which_operand)
5118{
5119  int i = *which_operand, val;
5120  enum arm_reg_type rtype;
5121  char *ptr = *str;
5122  struct neon_type_el optype;
5123
5124  if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5125    {
5126      /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>.  */
5127      inst.operands[i].reg = val;
5128      inst.operands[i].isscalar = 1;
5129      inst.operands[i].vectype = optype;
5130      inst.operands[i++].present = 1;
5131
5132      if (skip_past_comma (&ptr) == FAIL)
5133        goto wanted_comma;
5134
5135      if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5136        goto wanted_arm;
5137
5138      inst.operands[i].reg = val;
5139      inst.operands[i].isreg = 1;
5140      inst.operands[i].present = 1;
5141    }
5142  else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5143           != FAIL)
5144    {
5145      /* Cases 0, 1, 2, 3, 5 (D only).  */
5146      if (skip_past_comma (&ptr) == FAIL)
5147        goto wanted_comma;
5148
5149      inst.operands[i].reg = val;
5150      inst.operands[i].isreg = 1;
5151      inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5152      inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5153      inst.operands[i].isvec = 1;
5154      inst.operands[i].vectype = optype;
5155      inst.operands[i++].present = 1;
5156
5157      if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5158        {
5159          /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5160             Case 13: VMOV <Sd>, <Rm>  */
5161          inst.operands[i].reg = val;
5162          inst.operands[i].isreg = 1;
5163          inst.operands[i].present = 1;
5164
5165          if (rtype == REG_TYPE_NQ)
5166            {
5167              first_error (_("can't use Neon quad register here"));
5168              return FAIL;
5169            }
5170          else if (rtype != REG_TYPE_VFS)
5171            {
5172              i++;
5173              if (skip_past_comma (&ptr) == FAIL)
5174                goto wanted_comma;
5175              if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5176                goto wanted_arm;
5177              inst.operands[i].reg = val;
5178              inst.operands[i].isreg = 1;
5179              inst.operands[i].present = 1;
5180            }
5181        }
5182      else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5183          /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5184             Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5185             Case 10: VMOV.F32 <Sd>, #<imm>
5186             Case 11: VMOV.F64 <Dd>, #<imm>  */
5187        inst.operands[i].immisfloat = 1;
5188      else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5189                                           &optype)) != FAIL)
5190        {
5191          /* Case 0: VMOV<c><q> <Qd>, <Qm>
5192             Case 1: VMOV<c><q> <Dd>, <Dm>
5193             Case 8: VMOV.F32 <Sd>, <Sm>
5194             Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm>  */
5195
5196          inst.operands[i].reg = val;
5197          inst.operands[i].isreg = 1;
5198          inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5199          inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5200          inst.operands[i].isvec = 1;
5201          inst.operands[i].vectype = optype;
5202          inst.operands[i].present = 1;
5203
5204          if (skip_past_comma (&ptr) == SUCCESS)
5205            {
5206              /* Case 15.  */
5207              i++;
5208
5209              if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5210                goto wanted_arm;
5211
5212              inst.operands[i].reg = val;
5213              inst.operands[i].isreg = 1;
5214              inst.operands[i++].present = 1;
5215
5216              if (skip_past_comma (&ptr) == FAIL)
5217                goto wanted_comma;
5218
5219              if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5220                goto wanted_arm;
5221
5222              inst.operands[i].reg = val;
5223              inst.operands[i].isreg = 1;
5224              inst.operands[i++].present = 1;
5225            }
5226        }
5227      else if (parse_big_immediate (&ptr, i) == SUCCESS)
5228          /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5229             Case 3: VMOV<c><q>.<dt> <Dd>, #<imm>  */
5230        ;
5231      else
5232        {
5233          first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5234          return FAIL;
5235        }
5236    }
5237  else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5238    {
5239      /* Cases 6, 7.  */
5240      inst.operands[i].reg = val;
5241      inst.operands[i].isreg = 1;
5242      inst.operands[i++].present = 1;
5243
5244      if (skip_past_comma (&ptr) == FAIL)
5245        goto wanted_comma;
5246
5247      if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5248        {
5249          /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]>  */
5250          inst.operands[i].reg = val;
5251          inst.operands[i].isscalar = 1;
5252          inst.operands[i].present = 1;
5253          inst.operands[i].vectype = optype;
5254        }
5255      else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5256        {
5257          /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm>  */
5258          inst.operands[i].reg = val;
5259          inst.operands[i].isreg = 1;
5260          inst.operands[i++].present = 1;
5261
5262          if (skip_past_comma (&ptr) == FAIL)
5263            goto wanted_comma;
5264
5265          if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5266              == FAIL)
5267            {
5268              first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5269              return FAIL;
5270            }
5271
5272          inst.operands[i].reg = val;
5273          inst.operands[i].isreg = 1;
5274          inst.operands[i].isvec = 1;
5275          inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5276          inst.operands[i].vectype = optype;
5277          inst.operands[i].present = 1;
5278
5279          if (rtype == REG_TYPE_VFS)
5280            {
5281              /* Case 14.  */
5282              i++;
5283              if (skip_past_comma (&ptr) == FAIL)
5284                goto wanted_comma;
5285              if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
5286                                              &optype)) == FAIL)
5287                {
5288                  first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
5289                  return FAIL;
5290                }
5291              inst.operands[i].reg = val;
5292              inst.operands[i].isreg = 1;
5293              inst.operands[i].isvec = 1;
5294              inst.operands[i].issingle = 1;
5295              inst.operands[i].vectype = optype;
5296              inst.operands[i].present = 1;
5297            }
5298        }
5299      else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
5300               != FAIL)
5301        {
5302          /* Case 13.  */
5303          inst.operands[i].reg = val;
5304          inst.operands[i].isreg = 1;
5305          inst.operands[i].isvec = 1;
5306          inst.operands[i].issingle = 1;
5307          inst.operands[i].vectype = optype;
5308          inst.operands[i++].present = 1;
5309        }
5310    }
5311  else
5312    {
5313      first_error (_("parse error"));
5314      return FAIL;
5315    }
5316
5317  /* Successfully parsed the operands. Update args.  */
5318  *which_operand = i;
5319  *str = ptr;
5320  return SUCCESS;
5321
5322  wanted_comma:
5323  first_error (_("expected comma"));
5324  return FAIL;
5325
5326  wanted_arm:
5327  first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5328  return FAIL;
5329}
5330
5331/* Matcher codes for parse_operands.  */
5332enum operand_parse_code
5333{
5334  OP_stop,	/* end of line */
5335
5336  OP_RR,	/* ARM register */
5337  OP_RRnpc,	/* ARM register, not r15 */
5338  OP_RRnpcb,	/* ARM register, not r15, in square brackets */
5339  OP_RRw,	/* ARM register, not r15, optional trailing ! */
5340  OP_RCP,	/* Coprocessor number */
5341  OP_RCN,	/* Coprocessor register */
5342  OP_RF,	/* FPA register */
5343  OP_RVS,	/* VFP single precision register */
5344  OP_RVD,	/* VFP double precision register (0..15) */
5345  OP_RND,       /* Neon double precision register (0..31) */
5346  OP_RNQ,	/* Neon quad precision register */
5347  OP_RVSD,	/* VFP single or double precision register */
5348  OP_RNDQ,      /* Neon double or quad precision register */
5349  OP_RNSDQ,	/* Neon single, double or quad precision register */
5350  OP_RNSC,      /* Neon scalar D[X] */
5351  OP_RVC,	/* VFP control register */
5352  OP_RMF,	/* Maverick F register */
5353  OP_RMD,	/* Maverick D register */
5354  OP_RMFX,	/* Maverick FX register */
5355  OP_RMDX,	/* Maverick DX register */
5356  OP_RMAX,	/* Maverick AX register */
5357  OP_RMDS,	/* Maverick DSPSC register */
5358  OP_RIWR,	/* iWMMXt wR register */
5359  OP_RIWC,	/* iWMMXt wC register */
5360  OP_RIWG,	/* iWMMXt wCG register */
5361  OP_RXA,	/* XScale accumulator register */
5362
5363  OP_REGLST,	/* ARM register list */
5364  OP_VRSLST,	/* VFP single-precision register list */
5365  OP_VRDLST,	/* VFP double-precision register list */
5366  OP_VRSDLST,   /* VFP single or double-precision register list (& quad) */
5367  OP_NRDLST,    /* Neon double-precision register list (d0-d31, qN aliases) */
5368  OP_NSTRLST,   /* Neon element/structure list */
5369
5370  OP_NILO,      /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...)  */
5371  OP_RNDQ_I0,   /* Neon D or Q reg, or immediate zero.  */
5372  OP_RVSD_I0,	/* VFP S or D reg, or immediate zero.  */
5373  OP_RR_RNSC,   /* ARM reg or Neon scalar.  */
5374  OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar.  */
5375  OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar.  */
5376  OP_RND_RNSC,  /* Neon D reg, or Neon scalar.  */
5377  OP_VMOV,      /* Neon VMOV operands.  */
5378  OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN.  */
5379  OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift.  */
5380  OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2.  */
5381
5382  OP_I0,        /* immediate zero */
5383  OP_I7,	/* immediate value 0 .. 7 */
5384  OP_I15,	/*		   0 .. 15 */
5385  OP_I16,	/*		   1 .. 16 */
5386  OP_I16z,      /*                 0 .. 16 */
5387  OP_I31,	/*		   0 .. 31 */
5388  OP_I31w,	/*		   0 .. 31, optional trailing ! */
5389  OP_I32,	/*		   1 .. 32 */
5390  OP_I32z,	/*		   0 .. 32 */
5391  OP_I63,	/*		   0 .. 63 */
5392  OP_I63s,	/*		 -64 .. 63 */
5393  OP_I64,	/*		   1 .. 64 */
5394  OP_I64z,	/*		   0 .. 64 */
5395  OP_I255,	/*		   0 .. 255 */
5396
5397  OP_I4b,	/* immediate, prefix optional, 1 .. 4 */
5398  OP_I7b,	/*			       0 .. 7 */
5399  OP_I15b,	/*			       0 .. 15 */
5400  OP_I31b,	/*			       0 .. 31 */
5401
5402  OP_SH,	/* shifter operand */
5403  OP_SHG,	/* shifter operand with possible group relocation */
5404  OP_ADDR,	/* Memory address expression (any mode) */
5405  OP_ADDRGLDR,	/* Mem addr expr (any mode) with possible LDR group reloc */
5406  OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
5407  OP_ADDRGLDC,  /* Mem addr expr (any mode) with possible LDC group reloc */
5408  OP_EXP,	/* arbitrary expression */
5409  OP_EXPi,	/* same, with optional immediate prefix */
5410  OP_EXPr,	/* same, with optional relocation suffix */
5411  OP_HALF,	/* 0 .. 65535 or low/high reloc.  */
5412
5413  OP_CPSF,	/* CPS flags */
5414  OP_ENDI,	/* Endianness specifier */
5415  OP_PSR,	/* CPSR/SPSR mask for msr */
5416  OP_COND,	/* conditional code */
5417  OP_TB,	/* Table branch.  */
5418
5419  OP_RVC_PSR,	/* CPSR/SPSR mask for msr, or VFP control register.  */
5420  OP_APSR_RR,   /* ARM register or "APSR_nzcv".  */
5421
5422  OP_RRnpc_I0,	/* ARM register or literal 0 */
5423  OP_RR_EXr,	/* ARM register or expression with opt. reloc suff. */
5424  OP_RR_EXi,	/* ARM register or expression with imm prefix */
5425  OP_RF_IF,	/* FPA register or immediate */
5426  OP_RIWR_RIWC, /* iWMMXt R or C reg */
5427  OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
5428
5429  /* Optional operands.	 */
5430  OP_oI7b,	 /* immediate, prefix optional, 0 .. 7 */
5431  OP_oI31b,	 /*				0 .. 31 */
5432  OP_oI32b,      /*                             1 .. 32 */
5433  OP_oIffffb,	 /*				0 .. 65535 */
5434  OP_oI255c,	 /*	  curly-brace enclosed, 0 .. 255 */
5435
5436  OP_oRR,	 /* ARM register */
5437  OP_oRRnpc,	 /* ARM register, not the PC */
5438  OP_oRRw,	 /* ARM register, not r15, optional trailing ! */
5439  OP_oRND,       /* Optional Neon double precision register */
5440  OP_oRNQ,       /* Optional Neon quad precision register */
5441  OP_oRNDQ,      /* Optional Neon double or quad precision register */
5442  OP_oRNSDQ,	 /* Optional single, double or quad precision vector register */
5443  OP_oSHll,	 /* LSL immediate */
5444  OP_oSHar,	 /* ASR immediate */
5445  OP_oSHllar,	 /* LSL or ASR immediate */
5446  OP_oROR,	 /* ROR 0/8/16/24 */
5447  OP_oBARRIER,	 /* Option argument for a barrier instruction.  */
5448
5449  OP_FIRST_OPTIONAL = OP_oI7b
5450};
5451
5452/* Generic instruction operand parser.	This does no encoding and no
5453   semantic validation; it merely squirrels values away in the inst
5454   structure.  Returns SUCCESS or FAIL depending on whether the
5455   specified grammar matched.  */
5456static int
5457parse_operands (char *str, const unsigned char *pattern)
5458{
5459  unsigned const char *upat = pattern;
5460  char *backtrack_pos = 0;
5461  const char *backtrack_error = 0;
5462  int i, val, backtrack_index = 0;
5463  enum arm_reg_type rtype;
5464  parse_operand_result result;
5465
5466#define po_char_or_fail(chr) do {		\
5467  if (skip_past_char (&str, chr) == FAIL)	\
5468    goto bad_args;				\
5469} while (0)
5470
5471#define po_reg_or_fail(regtype) do {				\
5472  val = arm_typed_reg_parse (&str, regtype, &rtype,		\
5473  			     &inst.operands[i].vectype);	\
5474  if (val == FAIL)						\
5475    {								\
5476      first_error (_(reg_expected_msgs[regtype]));		\
5477      goto failure;						\
5478    }								\
5479  inst.operands[i].reg = val;					\
5480  inst.operands[i].isreg = 1;					\
5481  inst.operands[i].isquad = (rtype == REG_TYPE_NQ);		\
5482  inst.operands[i].issingle = (rtype == REG_TYPE_VFS);		\
5483  inst.operands[i].isvec = (rtype == REG_TYPE_VFS		\
5484                            || rtype == REG_TYPE_VFD		\
5485                            || rtype == REG_TYPE_NQ);		\
5486} while (0)
5487
5488#define po_reg_or_goto(regtype, label) do {			\
5489  val = arm_typed_reg_parse (&str, regtype, &rtype,		\
5490                             &inst.operands[i].vectype);	\
5491  if (val == FAIL)						\
5492    goto label;							\
5493								\
5494  inst.operands[i].reg = val;					\
5495  inst.operands[i].isreg = 1;					\
5496  inst.operands[i].isquad = (rtype == REG_TYPE_NQ);		\
5497  inst.operands[i].issingle = (rtype == REG_TYPE_VFS);		\
5498  inst.operands[i].isvec = (rtype == REG_TYPE_VFS		\
5499                            || rtype == REG_TYPE_VFD		\
5500                            || rtype == REG_TYPE_NQ);		\
5501} while (0)
5502
5503#define po_imm_or_fail(min, max, popt) do {			\
5504  if (parse_immediate (&str, &val, min, max, popt) == FAIL)	\
5505    goto failure;						\
5506  inst.operands[i].imm = val;					\
5507} while (0)
5508
5509#define po_scalar_or_goto(elsz, label) do {			\
5510  val = parse_scalar (&str, elsz, &inst.operands[i].vectype);	\
5511  if (val == FAIL)						\
5512    goto label;							\
5513  inst.operands[i].reg = val;					\
5514  inst.operands[i].isscalar = 1;				\
5515} while (0)
5516
5517#define po_misc_or_fail(expr) do {		\
5518  if (expr)					\
5519    goto failure;				\
5520} while (0)
5521
5522#define po_misc_or_fail_no_backtrack(expr) do {	\
5523  result = expr;				\
5524  if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5525    backtrack_pos = 0;				\
5526  if (result != PARSE_OPERAND_SUCCESS)		\
5527    goto failure;				\
5528} while (0)
5529
5530  skip_whitespace (str);
5531
5532  for (i = 0; upat[i] != OP_stop; i++)
5533    {
5534      if (upat[i] >= OP_FIRST_OPTIONAL)
5535	{
5536	  /* Remember where we are in case we need to backtrack.  */
5537	  assert (!backtrack_pos);
5538	  backtrack_pos = str;
5539	  backtrack_error = inst.error;
5540	  backtrack_index = i;
5541	}
5542
5543      if (i > 0 && (i > 1 || inst.operands[0].present))
5544	po_char_or_fail (',');
5545
5546      switch (upat[i])
5547	{
5548	  /* Registers */
5549	case OP_oRRnpc:
5550	case OP_RRnpc:
5551	case OP_oRR:
5552	case OP_RR:    po_reg_or_fail (REG_TYPE_RN);	  break;
5553	case OP_RCP:   po_reg_or_fail (REG_TYPE_CP);	  break;
5554	case OP_RCN:   po_reg_or_fail (REG_TYPE_CN);	  break;
5555	case OP_RF:    po_reg_or_fail (REG_TYPE_FN);	  break;
5556	case OP_RVS:   po_reg_or_fail (REG_TYPE_VFS);	  break;
5557	case OP_RVD:   po_reg_or_fail (REG_TYPE_VFD);	  break;
5558        case OP_oRND:
5559	case OP_RND:   po_reg_or_fail (REG_TYPE_VFD);	  break;
5560	case OP_RVC:
5561	  po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
5562	  break;
5563	  /* Also accept generic coprocessor regs for unknown registers.  */
5564	  coproc_reg:
5565	  po_reg_or_fail (REG_TYPE_CN);
5566	  break;
5567	case OP_RMF:   po_reg_or_fail (REG_TYPE_MVF);	  break;
5568	case OP_RMD:   po_reg_or_fail (REG_TYPE_MVD);	  break;
5569	case OP_RMFX:  po_reg_or_fail (REG_TYPE_MVFX);	  break;
5570	case OP_RMDX:  po_reg_or_fail (REG_TYPE_MVDX);	  break;
5571	case OP_RMAX:  po_reg_or_fail (REG_TYPE_MVAX);	  break;
5572	case OP_RMDS:  po_reg_or_fail (REG_TYPE_DSPSC);	  break;
5573	case OP_RIWR:  po_reg_or_fail (REG_TYPE_MMXWR);	  break;
5574	case OP_RIWC:  po_reg_or_fail (REG_TYPE_MMXWC);	  break;
5575	case OP_RIWG:  po_reg_or_fail (REG_TYPE_MMXWCG);  break;
5576	case OP_RXA:   po_reg_or_fail (REG_TYPE_XSCALE);  break;
5577        case OP_oRNQ:
5578	case OP_RNQ:   po_reg_or_fail (REG_TYPE_NQ);      break;
5579        case OP_oRNDQ:
5580	case OP_RNDQ:  po_reg_or_fail (REG_TYPE_NDQ);     break;
5581        case OP_RVSD:  po_reg_or_fail (REG_TYPE_VFSD);    break;
5582        case OP_oRNSDQ:
5583        case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ);    break;
5584
5585        /* Neon scalar. Using an element size of 8 means that some invalid
5586           scalars are accepted here, so deal with those in later code.  */
5587        case OP_RNSC:  po_scalar_or_goto (8, failure);    break;
5588
5589        /* WARNING: We can expand to two operands here. This has the potential
5590           to totally confuse the backtracking mechanism! It will be OK at
5591           least as long as we don't try to use optional args as well,
5592           though.  */
5593        case OP_NILO:
5594          {
5595            po_reg_or_goto (REG_TYPE_NDQ, try_imm);
5596	    inst.operands[i].present = 1;
5597            i++;
5598            skip_past_comma (&str);
5599            po_reg_or_goto (REG_TYPE_NDQ, one_reg_only);
5600            break;
5601            one_reg_only:
5602            /* Optional register operand was omitted. Unfortunately, it's in
5603               operands[i-1] and we need it to be in inst.operands[i]. Fix that
5604               here (this is a bit grotty).  */
5605            inst.operands[i] = inst.operands[i-1];
5606            inst.operands[i-1].present = 0;
5607            break;
5608            try_imm:
5609	    /* There's a possibility of getting a 64-bit immediate here, so
5610	       we need special handling.  */
5611	    if (parse_big_immediate (&str, i) == FAIL)
5612	      {
5613		inst.error = _("immediate value is out of range");
5614		goto failure;
5615	      }
5616          }
5617          break;
5618
5619        case OP_RNDQ_I0:
5620          {
5621            po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
5622            break;
5623            try_imm0:
5624            po_imm_or_fail (0, 0, TRUE);
5625          }
5626          break;
5627
5628        case OP_RVSD_I0:
5629          po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
5630          break;
5631
5632        case OP_RR_RNSC:
5633          {
5634            po_scalar_or_goto (8, try_rr);
5635            break;
5636            try_rr:
5637            po_reg_or_fail (REG_TYPE_RN);
5638          }
5639          break;
5640
5641        case OP_RNSDQ_RNSC:
5642          {
5643            po_scalar_or_goto (8, try_nsdq);
5644            break;
5645            try_nsdq:
5646            po_reg_or_fail (REG_TYPE_NSDQ);
5647          }
5648          break;
5649
5650        case OP_RNDQ_RNSC:
5651          {
5652            po_scalar_or_goto (8, try_ndq);
5653            break;
5654            try_ndq:
5655            po_reg_or_fail (REG_TYPE_NDQ);
5656          }
5657          break;
5658
5659        case OP_RND_RNSC:
5660          {
5661            po_scalar_or_goto (8, try_vfd);
5662            break;
5663            try_vfd:
5664            po_reg_or_fail (REG_TYPE_VFD);
5665          }
5666          break;
5667
5668        case OP_VMOV:
5669          /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5670             not careful then bad things might happen.  */
5671          po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
5672          break;
5673
5674        case OP_RNDQ_IMVNb:
5675          {
5676            po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm);
5677            break;
5678            try_mvnimm:
5679            /* There's a possibility of getting a 64-bit immediate here, so
5680               we need special handling.  */
5681            if (parse_big_immediate (&str, i) == FAIL)
5682              {
5683                inst.error = _("immediate value is out of range");
5684                goto failure;
5685              }
5686          }
5687          break;
5688
5689        case OP_RNDQ_I63b:
5690          {
5691            po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
5692            break;
5693            try_shimm:
5694            po_imm_or_fail (0, 63, TRUE);
5695          }
5696          break;
5697
5698	case OP_RRnpcb:
5699	  po_char_or_fail ('[');
5700	  po_reg_or_fail  (REG_TYPE_RN);
5701	  po_char_or_fail (']');
5702	  break;
5703
5704	case OP_RRw:
5705	case OP_oRRw:
5706	  po_reg_or_fail (REG_TYPE_RN);
5707	  if (skip_past_char (&str, '!') == SUCCESS)
5708	    inst.operands[i].writeback = 1;
5709	  break;
5710
5711	  /* Immediates */
5712	case OP_I7:	 po_imm_or_fail (  0,	   7, FALSE);	break;
5713	case OP_I15:	 po_imm_or_fail (  0,	  15, FALSE);	break;
5714	case OP_I16:	 po_imm_or_fail (  1,	  16, FALSE);	break;
5715        case OP_I16z:	 po_imm_or_fail (  0,     16, FALSE);   break;
5716	case OP_I31:	 po_imm_or_fail (  0,	  31, FALSE);	break;
5717	case OP_I32:	 po_imm_or_fail (  1,	  32, FALSE);	break;
5718        case OP_I32z:	 po_imm_or_fail (  0,     32, FALSE);   break;
5719	case OP_I63s:	 po_imm_or_fail (-64,	  63, FALSE);	break;
5720        case OP_I63:	 po_imm_or_fail (  0,     63, FALSE);   break;
5721        case OP_I64:	 po_imm_or_fail (  1,     64, FALSE);   break;
5722        case OP_I64z:	 po_imm_or_fail (  0,     64, FALSE);   break;
5723	case OP_I255:	 po_imm_or_fail (  0,	 255, FALSE);	break;
5724
5725	case OP_I4b:	 po_imm_or_fail (  1,	   4, TRUE);	break;
5726	case OP_oI7b:
5727	case OP_I7b:	 po_imm_or_fail (  0,	   7, TRUE);	break;
5728	case OP_I15b:	 po_imm_or_fail (  0,	  15, TRUE);	break;
5729	case OP_oI31b:
5730	case OP_I31b:	 po_imm_or_fail (  0,	  31, TRUE);	break;
5731        case OP_oI32b:   po_imm_or_fail (  1,     32, TRUE);    break;
5732	case OP_oIffffb: po_imm_or_fail (  0, 0xffff, TRUE);	break;
5733
5734	  /* Immediate variants */
5735	case OP_oI255c:
5736	  po_char_or_fail ('{');
5737	  po_imm_or_fail (0, 255, TRUE);
5738	  po_char_or_fail ('}');
5739	  break;
5740
5741	case OP_I31w:
5742	  /* The expression parser chokes on a trailing !, so we have
5743	     to find it first and zap it.  */
5744	  {
5745	    char *s = str;
5746	    while (*s && *s != ',')
5747	      s++;
5748	    if (s[-1] == '!')
5749	      {
5750		s[-1] = '\0';
5751		inst.operands[i].writeback = 1;
5752	      }
5753	    po_imm_or_fail (0, 31, TRUE);
5754	    if (str == s - 1)
5755	      str = s;
5756	  }
5757	  break;
5758
5759	  /* Expressions */
5760	case OP_EXPi:	EXPi:
5761	  po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5762					      GE_OPT_PREFIX));
5763	  break;
5764
5765	case OP_EXP:
5766	  po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5767					      GE_NO_PREFIX));
5768	  break;
5769
5770	case OP_EXPr:	EXPr:
5771	  po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5772					      GE_NO_PREFIX));
5773	  if (inst.reloc.exp.X_op == O_symbol)
5774	    {
5775	      val = parse_reloc (&str);
5776	      if (val == -1)
5777		{
5778		  inst.error = _("unrecognized relocation suffix");
5779		  goto failure;
5780		}
5781	      else if (val != BFD_RELOC_UNUSED)
5782		{
5783		  inst.operands[i].imm = val;
5784		  inst.operands[i].hasreloc = 1;
5785		}
5786	    }
5787	  break;
5788
5789	  /* Operand for MOVW or MOVT.  */
5790	case OP_HALF:
5791	  po_misc_or_fail (parse_half (&str));
5792	  break;
5793
5794	  /* Register or expression */
5795	case OP_RR_EXr:	  po_reg_or_goto (REG_TYPE_RN, EXPr); break;
5796	case OP_RR_EXi:	  po_reg_or_goto (REG_TYPE_RN, EXPi); break;
5797
5798	  /* Register or immediate */
5799	case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0);   break;
5800	I0:		  po_imm_or_fail (0, 0, FALSE);	      break;
5801
5802	case OP_RF_IF:    po_reg_or_goto (REG_TYPE_FN, IF);   break;
5803	IF:
5804	  if (!is_immediate_prefix (*str))
5805	    goto bad_args;
5806	  str++;
5807	  val = parse_fpa_immediate (&str);
5808	  if (val == FAIL)
5809	    goto failure;
5810	  /* FPA immediates are encoded as registers 8-15.
5811	     parse_fpa_immediate has already applied the offset.  */
5812	  inst.operands[i].reg = val;
5813	  inst.operands[i].isreg = 1;
5814	  break;
5815
5816	case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
5817	I32z:		  po_imm_or_fail (0, 32, FALSE);	  break;
5818
5819	  /* Two kinds of register */
5820	case OP_RIWR_RIWC:
5821	  {
5822	    struct reg_entry *rege = arm_reg_parse_multi (&str);
5823	    if (!rege
5824		|| (rege->type != REG_TYPE_MMXWR
5825		    && rege->type != REG_TYPE_MMXWC
5826		    && rege->type != REG_TYPE_MMXWCG))
5827	      {
5828		inst.error = _("iWMMXt data or control register expected");
5829		goto failure;
5830	      }
5831	    inst.operands[i].reg = rege->number;
5832	    inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
5833	  }
5834	  break;
5835
5836	case OP_RIWC_RIWG:
5837	  {
5838	    struct reg_entry *rege = arm_reg_parse_multi (&str);
5839	    if (!rege
5840		|| (rege->type != REG_TYPE_MMXWC
5841		    && rege->type != REG_TYPE_MMXWCG))
5842	      {
5843		inst.error = _("iWMMXt control register expected");
5844		goto failure;
5845	      }
5846	    inst.operands[i].reg = rege->number;
5847	    inst.operands[i].isreg = 1;
5848	  }
5849	  break;
5850
5851	  /* Misc */
5852	case OP_CPSF:	 val = parse_cps_flags (&str);		break;
5853	case OP_ENDI:	 val = parse_endian_specifier (&str);	break;
5854	case OP_oROR:	 val = parse_ror (&str);		break;
5855	case OP_PSR:	 val = parse_psr (&str);		break;
5856	case OP_COND:	 val = parse_cond (&str);		break;
5857	case OP_oBARRIER:val = parse_barrier (&str);		break;
5858
5859        case OP_RVC_PSR:
5860          po_reg_or_goto (REG_TYPE_VFC, try_psr);
5861          inst.operands[i].isvec = 1;  /* Mark VFP control reg as vector.  */
5862          break;
5863          try_psr:
5864          val = parse_psr (&str);
5865          break;
5866
5867        case OP_APSR_RR:
5868          po_reg_or_goto (REG_TYPE_RN, try_apsr);
5869          break;
5870          try_apsr:
5871          /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5872             instruction).  */
5873          if (strncasecmp (str, "APSR_", 5) == 0)
5874            {
5875              unsigned found = 0;
5876              str += 5;
5877              while (found < 15)
5878                switch (*str++)
5879                  {
5880                  case 'c': found = (found & 1) ? 16 : found | 1; break;
5881                  case 'n': found = (found & 2) ? 16 : found | 2; break;
5882                  case 'z': found = (found & 4) ? 16 : found | 4; break;
5883                  case 'v': found = (found & 8) ? 16 : found | 8; break;
5884                  default: found = 16;
5885                  }
5886              if (found != 15)
5887                goto failure;
5888              inst.operands[i].isvec = 1;
5889            }
5890          else
5891            goto failure;
5892          break;
5893
5894	case OP_TB:
5895	  po_misc_or_fail (parse_tb (&str));
5896	  break;
5897
5898	  /* Register lists */
5899	case OP_REGLST:
5900	  val = parse_reg_list (&str);
5901	  if (*str == '^')
5902	    {
5903	      inst.operands[1].writeback = 1;
5904	      str++;
5905	    }
5906	  break;
5907
5908	case OP_VRSLST:
5909	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
5910	  break;
5911
5912	case OP_VRDLST:
5913	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
5914	  break;
5915
5916        case OP_VRSDLST:
5917          /* Allow Q registers too.  */
5918          val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5919                                    REGLIST_NEON_D);
5920          if (val == FAIL)
5921            {
5922              inst.error = NULL;
5923              val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5924                                        REGLIST_VFP_S);
5925              inst.operands[i].issingle = 1;
5926            }
5927          break;
5928
5929        case OP_NRDLST:
5930          val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5931                                    REGLIST_NEON_D);
5932          break;
5933
5934	case OP_NSTRLST:
5935          val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
5936                                           &inst.operands[i].vectype);
5937          break;
5938
5939	  /* Addressing modes */
5940	case OP_ADDR:
5941	  po_misc_or_fail (parse_address (&str, i));
5942	  break;
5943
5944	case OP_ADDRGLDR:
5945	  po_misc_or_fail_no_backtrack (
5946            parse_address_group_reloc (&str, i, GROUP_LDR));
5947	  break;
5948
5949	case OP_ADDRGLDRS:
5950	  po_misc_or_fail_no_backtrack (
5951            parse_address_group_reloc (&str, i, GROUP_LDRS));
5952	  break;
5953
5954	case OP_ADDRGLDC:
5955	  po_misc_or_fail_no_backtrack (
5956            parse_address_group_reloc (&str, i, GROUP_LDC));
5957	  break;
5958
5959	case OP_SH:
5960	  po_misc_or_fail (parse_shifter_operand (&str, i));
5961	  break;
5962
5963	case OP_SHG:
5964	  po_misc_or_fail_no_backtrack (
5965            parse_shifter_operand_group_reloc (&str, i));
5966	  break;
5967
5968	case OP_oSHll:
5969	  po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
5970	  break;
5971
5972	case OP_oSHar:
5973	  po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
5974	  break;
5975
5976	case OP_oSHllar:
5977	  po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
5978	  break;
5979
5980	default:
5981	  as_fatal ("unhandled operand code %d", upat[i]);
5982	}
5983
5984      /* Various value-based sanity checks and shared operations.  We
5985	 do not signal immediate failures for the register constraints;
5986	 this allows a syntax error to take precedence.	 */
5987      switch (upat[i])
5988	{
5989	case OP_oRRnpc:
5990	case OP_RRnpc:
5991	case OP_RRnpcb:
5992	case OP_RRw:
5993	case OP_oRRw:
5994	case OP_RRnpc_I0:
5995	  if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
5996	    inst.error = BAD_PC;
5997	  break;
5998
5999	case OP_CPSF:
6000	case OP_ENDI:
6001	case OP_oROR:
6002	case OP_PSR:
6003        case OP_RVC_PSR:
6004	case OP_COND:
6005	case OP_oBARRIER:
6006	case OP_REGLST:
6007	case OP_VRSLST:
6008	case OP_VRDLST:
6009        case OP_VRSDLST:
6010        case OP_NRDLST:
6011        case OP_NSTRLST:
6012	  if (val == FAIL)
6013	    goto failure;
6014	  inst.operands[i].imm = val;
6015	  break;
6016
6017	default:
6018	  break;
6019	}
6020
6021      /* If we get here, this operand was successfully parsed.	*/
6022      inst.operands[i].present = 1;
6023      continue;
6024
6025    bad_args:
6026      inst.error = BAD_ARGS;
6027
6028    failure:
6029      if (!backtrack_pos)
6030	{
6031	  /* The parse routine should already have set inst.error, but set a
6032	     defaut here just in case.  */
6033	  if (!inst.error)
6034	    inst.error = _("syntax error");
6035	  return FAIL;
6036	}
6037
6038      /* Do not backtrack over a trailing optional argument that
6039	 absorbed some text.  We will only fail again, with the
6040	 'garbage following instruction' error message, which is
6041	 probably less helpful than the current one.  */
6042      if (backtrack_index == i && backtrack_pos != str
6043	  && upat[i+1] == OP_stop)
6044	{
6045	  if (!inst.error)
6046	    inst.error = _("syntax error");
6047	  return FAIL;
6048	}
6049
6050      /* Try again, skipping the optional argument at backtrack_pos.  */
6051      str = backtrack_pos;
6052      inst.error = backtrack_error;
6053      inst.operands[backtrack_index].present = 0;
6054      i = backtrack_index;
6055      backtrack_pos = 0;
6056    }
6057
6058  /* Check that we have parsed all the arguments.  */
6059  if (*str != '\0' && !inst.error)
6060    inst.error = _("garbage following instruction");
6061
6062  return inst.error ? FAIL : SUCCESS;
6063}
6064
6065#undef po_char_or_fail
6066#undef po_reg_or_fail
6067#undef po_reg_or_goto
6068#undef po_imm_or_fail
6069#undef po_scalar_or_fail
6070
6071/* Shorthand macro for instruction encoding functions issuing errors.  */
6072#define constraint(expr, err) do {		\
6073  if (expr)					\
6074    {						\
6075      inst.error = err;				\
6076      return;					\
6077    }						\
6078} while (0)
6079
6080/* Functions for operand encoding.  ARM, then Thumb.  */
6081
6082#define rotate_left(v, n) (v << (n % 32) | v >> ((32 - n) % 32))
6083
6084/* If VAL can be encoded in the immediate field of an ARM instruction,
6085   return the encoded form.  Otherwise, return FAIL.  */
6086
6087static unsigned int
6088encode_arm_immediate (unsigned int val)
6089{
6090  unsigned int a, i;
6091
6092  for (i = 0; i < 32; i += 2)
6093    if ((a = rotate_left (val, i)) <= 0xff)
6094      return a | (i << 7); /* 12-bit pack: [shift-cnt,const].  */
6095
6096  return FAIL;
6097}
6098
6099/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6100   return the encoded form.  Otherwise, return FAIL.  */
6101static unsigned int
6102encode_thumb32_immediate (unsigned int val)
6103{
6104  unsigned int a, i;
6105
6106  if (val <= 0xff)
6107    return val;
6108
6109  for (i = 1; i <= 24; i++)
6110    {
6111      a = val >> i;
6112      if ((val & ~(0xff << i)) == 0)
6113	return ((val >> i) & 0x7f) | ((32 - i) << 7);
6114    }
6115
6116  a = val & 0xff;
6117  if (val == ((a << 16) | a))
6118    return 0x100 | a;
6119  if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6120    return 0x300 | a;
6121
6122  a = val & 0xff00;
6123  if (val == ((a << 16) | a))
6124    return 0x200 | (a >> 8);
6125
6126  return FAIL;
6127}
6128/* Encode a VFP SP or DP register number into inst.instruction.  */
6129
6130static void
6131encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6132{
6133  if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6134      && reg > 15)
6135    {
6136      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
6137        {
6138          if (thumb_mode)
6139            ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6140                                    fpu_vfp_ext_v3);
6141          else
6142            ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6143                                    fpu_vfp_ext_v3);
6144        }
6145      else
6146        {
6147          first_error (_("D register out of range for selected VFP version"));
6148          return;
6149        }
6150    }
6151
6152  switch (pos)
6153    {
6154    case VFP_REG_Sd:
6155      inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6156      break;
6157
6158    case VFP_REG_Sn:
6159      inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6160      break;
6161
6162    case VFP_REG_Sm:
6163      inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6164      break;
6165
6166    case VFP_REG_Dd:
6167      inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6168      break;
6169
6170    case VFP_REG_Dn:
6171      inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6172      break;
6173
6174    case VFP_REG_Dm:
6175      inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6176      break;
6177
6178    default:
6179      abort ();
6180    }
6181}
6182
6183/* Encode a <shift> in an ARM-format instruction.  The immediate,
6184   if any, is handled by md_apply_fix.	 */
6185static void
6186encode_arm_shift (int i)
6187{
6188  if (inst.operands[i].shift_kind == SHIFT_RRX)
6189    inst.instruction |= SHIFT_ROR << 5;
6190  else
6191    {
6192      inst.instruction |= inst.operands[i].shift_kind << 5;
6193      if (inst.operands[i].immisreg)
6194	{
6195	  inst.instruction |= SHIFT_BY_REG;
6196	  inst.instruction |= inst.operands[i].imm << 8;
6197	}
6198      else
6199	inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6200    }
6201}
6202
6203static void
6204encode_arm_shifter_operand (int i)
6205{
6206  if (inst.operands[i].isreg)
6207    {
6208      inst.instruction |= inst.operands[i].reg;
6209      encode_arm_shift (i);
6210    }
6211  else
6212    inst.instruction |= INST_IMMEDIATE;
6213}
6214
6215/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3.  */
6216static void
6217encode_arm_addr_mode_common (int i, bfd_boolean is_t)
6218{
6219  assert (inst.operands[i].isreg);
6220  inst.instruction |= inst.operands[i].reg << 16;
6221
6222  if (inst.operands[i].preind)
6223    {
6224      if (is_t)
6225	{
6226	  inst.error = _("instruction does not accept preindexed addressing");
6227	  return;
6228	}
6229      inst.instruction |= PRE_INDEX;
6230      if (inst.operands[i].writeback)
6231	inst.instruction |= WRITE_BACK;
6232
6233    }
6234  else if (inst.operands[i].postind)
6235    {
6236      assert (inst.operands[i].writeback);
6237      if (is_t)
6238	inst.instruction |= WRITE_BACK;
6239    }
6240  else /* unindexed - only for coprocessor */
6241    {
6242      inst.error = _("instruction does not accept unindexed addressing");
6243      return;
6244    }
6245
6246  if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
6247      && (((inst.instruction & 0x000f0000) >> 16)
6248	  == ((inst.instruction & 0x0000f000) >> 12)))
6249    as_warn ((inst.instruction & LOAD_BIT)
6250	     ? _("destination register same as write-back base")
6251	     : _("source register same as write-back base"));
6252}
6253
6254/* inst.operands[i] was set up by parse_address.  Encode it into an
6255   ARM-format mode 2 load or store instruction.	 If is_t is true,
6256   reject forms that cannot be used with a T instruction (i.e. not
6257   post-indexed).  */
6258static void
6259encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
6260{
6261  encode_arm_addr_mode_common (i, is_t);
6262
6263  if (inst.operands[i].immisreg)
6264    {
6265      inst.instruction |= INST_IMMEDIATE;  /* yes, this is backwards */
6266      inst.instruction |= inst.operands[i].imm;
6267      if (!inst.operands[i].negative)
6268	inst.instruction |= INDEX_UP;
6269      if (inst.operands[i].shifted)
6270	{
6271	  if (inst.operands[i].shift_kind == SHIFT_RRX)
6272	    inst.instruction |= SHIFT_ROR << 5;
6273	  else
6274	    {
6275	      inst.instruction |= inst.operands[i].shift_kind << 5;
6276	      inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6277	    }
6278	}
6279    }
6280  else /* immediate offset in inst.reloc */
6281    {
6282      if (inst.reloc.type == BFD_RELOC_UNUSED)
6283	inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
6284    }
6285}
6286
6287/* inst.operands[i] was set up by parse_address.  Encode it into an
6288   ARM-format mode 3 load or store instruction.	 Reject forms that
6289   cannot be used with such instructions.  If is_t is true, reject
6290   forms that cannot be used with a T instruction (i.e. not
6291   post-indexed).  */
6292static void
6293encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
6294{
6295  if (inst.operands[i].immisreg && inst.operands[i].shifted)
6296    {
6297      inst.error = _("instruction does not accept scaled register index");
6298      return;
6299    }
6300
6301  encode_arm_addr_mode_common (i, is_t);
6302
6303  if (inst.operands[i].immisreg)
6304    {
6305      inst.instruction |= inst.operands[i].imm;
6306      if (!inst.operands[i].negative)
6307	inst.instruction |= INDEX_UP;
6308    }
6309  else /* immediate offset in inst.reloc */
6310    {
6311      inst.instruction |= HWOFFSET_IMM;
6312      if (inst.reloc.type == BFD_RELOC_UNUSED)
6313	inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
6314    }
6315}
6316
6317/* inst.operands[i] was set up by parse_address.  Encode it into an
6318   ARM-format instruction.  Reject all forms which cannot be encoded
6319   into a coprocessor load/store instruction.  If wb_ok is false,
6320   reject use of writeback; if unind_ok is false, reject use of
6321   unindexed addressing.  If reloc_override is not 0, use it instead
6322   of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6323   (in which case it is preserved).  */
6324
6325static int
6326encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
6327{
6328  inst.instruction |= inst.operands[i].reg << 16;
6329
6330  assert (!(inst.operands[i].preind && inst.operands[i].postind));
6331
6332  if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
6333    {
6334      assert (!inst.operands[i].writeback);
6335      if (!unind_ok)
6336	{
6337	  inst.error = _("instruction does not support unindexed addressing");
6338	  return FAIL;
6339	}
6340      inst.instruction |= inst.operands[i].imm;
6341      inst.instruction |= INDEX_UP;
6342      return SUCCESS;
6343    }
6344
6345  if (inst.operands[i].preind)
6346    inst.instruction |= PRE_INDEX;
6347
6348  if (inst.operands[i].writeback)
6349    {
6350      if (inst.operands[i].reg == REG_PC)
6351	{
6352	  inst.error = _("pc may not be used with write-back");
6353	  return FAIL;
6354	}
6355      if (!wb_ok)
6356	{
6357	  inst.error = _("instruction does not support writeback");
6358	  return FAIL;
6359	}
6360      inst.instruction |= WRITE_BACK;
6361    }
6362
6363  if (reloc_override)
6364    inst.reloc.type = reloc_override;
6365  else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
6366            || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
6367           && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
6368    {
6369      if (thumb_mode)
6370        inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
6371      else
6372        inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
6373    }
6374
6375  return SUCCESS;
6376}
6377
6378/* inst.reloc.exp describes an "=expr" load pseudo-operation.
6379   Determine whether it can be performed with a move instruction; if
6380   it can, convert inst.instruction to that move instruction and
6381   return 1; if it can't, convert inst.instruction to a literal-pool
6382   load and return 0.  If this is not a valid thing to do in the
6383   current context, set inst.error and return 1.
6384
6385   inst.operands[i] describes the destination register.	 */
6386
6387static int
6388move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
6389{
6390  unsigned long tbit;
6391
6392  if (thumb_p)
6393    tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
6394  else
6395    tbit = LOAD_BIT;
6396
6397  if ((inst.instruction & tbit) == 0)
6398    {
6399      inst.error = _("invalid pseudo operation");
6400      return 1;
6401    }
6402  if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
6403    {
6404      inst.error = _("constant expression expected");
6405      return 1;
6406    }
6407  if (inst.reloc.exp.X_op == O_constant)
6408    {
6409      if (thumb_p)
6410	{
6411	  if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
6412	    {
6413	      /* This can be done with a mov(1) instruction.  */
6414	      inst.instruction	= T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
6415	      inst.instruction |= inst.reloc.exp.X_add_number;
6416	      return 1;
6417	    }
6418	}
6419      else
6420	{
6421	  int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
6422	  if (value != FAIL)
6423	    {
6424	      /* This can be done with a mov instruction.  */
6425	      inst.instruction &= LITERAL_MASK;
6426	      inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
6427	      inst.instruction |= value & 0xfff;
6428	      return 1;
6429	    }
6430
6431	  value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
6432	  if (value != FAIL)
6433	    {
6434	      /* This can be done with a mvn instruction.  */
6435	      inst.instruction &= LITERAL_MASK;
6436	      inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
6437	      inst.instruction |= value & 0xfff;
6438	      return 1;
6439	    }
6440	}
6441    }
6442
6443  if (add_to_lit_pool () == FAIL)
6444    {
6445      inst.error = _("literal pool insertion failed");
6446      return 1;
6447    }
6448  inst.operands[1].reg = REG_PC;
6449  inst.operands[1].isreg = 1;
6450  inst.operands[1].preind = 1;
6451  inst.reloc.pc_rel = 1;
6452  inst.reloc.type = (thumb_p
6453		     ? BFD_RELOC_ARM_THUMB_OFFSET
6454		     : (mode_3
6455			? BFD_RELOC_ARM_HWLITERAL
6456			: BFD_RELOC_ARM_LITERAL));
6457  return 0;
6458}
6459
6460/* Functions for instruction encoding, sorted by subarchitecture.
6461   First some generics; their names are taken from the conventional
6462   bit positions for register arguments in ARM format instructions.  */
6463
6464static void
6465do_noargs (void)
6466{
6467}
6468
6469static void
6470do_rd (void)
6471{
6472  inst.instruction |= inst.operands[0].reg << 12;
6473}
6474
6475static void
6476do_rd_rm (void)
6477{
6478  inst.instruction |= inst.operands[0].reg << 12;
6479  inst.instruction |= inst.operands[1].reg;
6480}
6481
6482static void
6483do_rd_rn (void)
6484{
6485  inst.instruction |= inst.operands[0].reg << 12;
6486  inst.instruction |= inst.operands[1].reg << 16;
6487}
6488
6489static void
6490do_rn_rd (void)
6491{
6492  inst.instruction |= inst.operands[0].reg << 16;
6493  inst.instruction |= inst.operands[1].reg << 12;
6494}
6495
6496static void
6497do_rd_rm_rn (void)
6498{
6499  unsigned Rn = inst.operands[2].reg;
6500  /* Enforce restrictions on SWP instruction.  */
6501  if ((inst.instruction & 0x0fbfffff) == 0x01000090)
6502    constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
6503		_("Rn must not overlap other operands"));
6504  inst.instruction |= inst.operands[0].reg << 12;
6505  inst.instruction |= inst.operands[1].reg;
6506  inst.instruction |= Rn << 16;
6507}
6508
6509static void
6510do_rd_rn_rm (void)
6511{
6512  inst.instruction |= inst.operands[0].reg << 12;
6513  inst.instruction |= inst.operands[1].reg << 16;
6514  inst.instruction |= inst.operands[2].reg;
6515}
6516
6517static void
6518do_rm_rd_rn (void)
6519{
6520  inst.instruction |= inst.operands[0].reg;
6521  inst.instruction |= inst.operands[1].reg << 12;
6522  inst.instruction |= inst.operands[2].reg << 16;
6523}
6524
6525static void
6526do_imm0 (void)
6527{
6528  inst.instruction |= inst.operands[0].imm;
6529}
6530
6531static void
6532do_rd_cpaddr (void)
6533{
6534  inst.instruction |= inst.operands[0].reg << 12;
6535  encode_arm_cp_address (1, TRUE, TRUE, 0);
6536}
6537
6538/* ARM instructions, in alphabetical order by function name (except
6539   that wrapper functions appear immediately after the function they
6540   wrap).  */
6541
6542/* This is a pseudo-op of the form "adr rd, label" to be converted
6543   into a relative address of the form "add rd, pc, #label-.-8".  */
6544
6545static void
6546do_adr (void)
6547{
6548  inst.instruction |= (inst.operands[0].reg << 12);  /* Rd */
6549
6550  /* Frag hacking will turn this into a sub instruction if the offset turns
6551     out to be negative.  */
6552  inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
6553  inst.reloc.pc_rel = 1;
6554  inst.reloc.exp.X_add_number -= 8;
6555}
6556
6557/* This is a pseudo-op of the form "adrl rd, label" to be converted
6558   into a relative address of the form:
6559   add rd, pc, #low(label-.-8)"
6560   add rd, rd, #high(label-.-8)"  */
6561
6562static void
6563do_adrl (void)
6564{
6565  inst.instruction |= (inst.operands[0].reg << 12);  /* Rd */
6566
6567  /* Frag hacking will turn this into a sub instruction if the offset turns
6568     out to be negative.  */
6569  inst.reloc.type	       = BFD_RELOC_ARM_ADRL_IMMEDIATE;
6570  inst.reloc.pc_rel	       = 1;
6571  inst.size		       = INSN_SIZE * 2;
6572  inst.reloc.exp.X_add_number -= 8;
6573}
6574
6575static void
6576do_arit (void)
6577{
6578  if (!inst.operands[1].present)
6579    inst.operands[1].reg = inst.operands[0].reg;
6580  inst.instruction |= inst.operands[0].reg << 12;
6581  inst.instruction |= inst.operands[1].reg << 16;
6582  encode_arm_shifter_operand (2);
6583}
6584
6585static void
6586do_barrier (void)
6587{
6588  if (inst.operands[0].present)
6589    {
6590      constraint ((inst.instruction & 0xf0) != 0x40
6591		  && (inst.instruction & 0xf0) != 0x50
6592		  && inst.operands[0].imm != 0xf,
6593		  "bad barrier type");
6594      inst.instruction |= inst.operands[0].imm;
6595    }
6596  else
6597    inst.instruction |= 0xf;
6598}
6599
6600static void
6601do_bfc (void)
6602{
6603  unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6604  constraint (msb > 32, _("bit-field extends past end of register"));
6605  /* The instruction encoding stores the LSB and MSB,
6606     not the LSB and width.  */
6607  inst.instruction |= inst.operands[0].reg << 12;
6608  inst.instruction |= inst.operands[1].imm << 7;
6609  inst.instruction |= (msb - 1) << 16;
6610}
6611
6612static void
6613do_bfi (void)
6614{
6615  unsigned int msb;
6616
6617  /* #0 in second position is alternative syntax for bfc, which is
6618     the same instruction but with REG_PC in the Rm field.  */
6619  if (!inst.operands[1].isreg)
6620    inst.operands[1].reg = REG_PC;
6621
6622  msb = inst.operands[2].imm + inst.operands[3].imm;
6623  constraint (msb > 32, _("bit-field extends past end of register"));
6624  /* The instruction encoding stores the LSB and MSB,
6625     not the LSB and width.  */
6626  inst.instruction |= inst.operands[0].reg << 12;
6627  inst.instruction |= inst.operands[1].reg;
6628  inst.instruction |= inst.operands[2].imm << 7;
6629  inst.instruction |= (msb - 1) << 16;
6630}
6631
6632static void
6633do_bfx (void)
6634{
6635  constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6636	      _("bit-field extends past end of register"));
6637  inst.instruction |= inst.operands[0].reg << 12;
6638  inst.instruction |= inst.operands[1].reg;
6639  inst.instruction |= inst.operands[2].imm << 7;
6640  inst.instruction |= (inst.operands[3].imm - 1) << 16;
6641}
6642
6643/* ARM V5 breakpoint instruction (argument parse)
6644     BKPT <16 bit unsigned immediate>
6645     Instruction is not conditional.
6646	The bit pattern given in insns[] has the COND_ALWAYS condition,
6647	and it is an error if the caller tried to override that.  */
6648
6649static void
6650do_bkpt (void)
6651{
6652  /* Top 12 of 16 bits to bits 19:8.  */
6653  inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
6654
6655  /* Bottom 4 of 16 bits to bits 3:0.  */
6656  inst.instruction |= inst.operands[0].imm & 0xf;
6657}
6658
6659static void
6660encode_branch (int default_reloc)
6661{
6662  if (inst.operands[0].hasreloc)
6663    {
6664      constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
6665		  _("the only suffix valid here is '(plt)'"));
6666      inst.reloc.type	= BFD_RELOC_ARM_PLT32;
6667    }
6668  else
6669    {
6670      inst.reloc.type = default_reloc;
6671    }
6672  inst.reloc.pc_rel = 1;
6673}
6674
6675static void
6676do_branch (void)
6677{
6678#ifdef OBJ_ELF
6679  if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6680    encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
6681  else
6682#endif
6683    encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
6684}
6685
6686static void
6687do_bl (void)
6688{
6689#ifdef OBJ_ELF
6690  if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6691    {
6692      if (inst.cond == COND_ALWAYS)
6693	encode_branch (BFD_RELOC_ARM_PCREL_CALL);
6694      else
6695	encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
6696    }
6697  else
6698#endif
6699    encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
6700}
6701
6702/* ARM V5 branch-link-exchange instruction (argument parse)
6703     BLX <target_addr>		ie BLX(1)
6704     BLX{<condition>} <Rm>	ie BLX(2)
6705   Unfortunately, there are two different opcodes for this mnemonic.
6706   So, the insns[].value is not used, and the code here zaps values
6707	into inst.instruction.
6708   Also, the <target_addr> can be 25 bits, hence has its own reloc.  */
6709
6710static void
6711do_blx (void)
6712{
6713  if (inst.operands[0].isreg)
6714    {
6715      /* Arg is a register; the opcode provided by insns[] is correct.
6716	 It is not illegal to do "blx pc", just useless.  */
6717      if (inst.operands[0].reg == REG_PC)
6718	as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6719
6720      inst.instruction |= inst.operands[0].reg;
6721    }
6722  else
6723    {
6724      /* Arg is an address; this instruction cannot be executed
6725	 conditionally, and the opcode must be adjusted.  */
6726      constraint (inst.cond != COND_ALWAYS, BAD_COND);
6727      inst.instruction = 0xfa000000;
6728#ifdef OBJ_ELF
6729      if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6730	encode_branch (BFD_RELOC_ARM_PCREL_CALL);
6731      else
6732#endif
6733	encode_branch (BFD_RELOC_ARM_PCREL_BLX);
6734    }
6735}
6736
6737static void
6738do_bx (void)
6739{
6740  if (inst.operands[0].reg == REG_PC)
6741    as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6742
6743  inst.instruction |= inst.operands[0].reg;
6744}
6745
6746
6747/* ARM v5TEJ.  Jump to Jazelle code.  */
6748
6749static void
6750do_bxj (void)
6751{
6752  if (inst.operands[0].reg == REG_PC)
6753    as_tsktsk (_("use of r15 in bxj is not really useful"));
6754
6755  inst.instruction |= inst.operands[0].reg;
6756}
6757
6758/* Co-processor data operation:
6759      CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6760      CDP2	<coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}	 */
6761static void
6762do_cdp (void)
6763{
6764  inst.instruction |= inst.operands[0].reg << 8;
6765  inst.instruction |= inst.operands[1].imm << 20;
6766  inst.instruction |= inst.operands[2].reg << 12;
6767  inst.instruction |= inst.operands[3].reg << 16;
6768  inst.instruction |= inst.operands[4].reg;
6769  inst.instruction |= inst.operands[5].imm << 5;
6770}
6771
6772static void
6773do_cmp (void)
6774{
6775  inst.instruction |= inst.operands[0].reg << 16;
6776  encode_arm_shifter_operand (1);
6777}
6778
6779/* Transfer between coprocessor and ARM registers.
6780   MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6781   MRC2
6782   MCR{cond}
6783   MCR2
6784
6785   No special properties.  */
6786
6787static void
6788do_co_reg (void)
6789{
6790  inst.instruction |= inst.operands[0].reg << 8;
6791  inst.instruction |= inst.operands[1].imm << 21;
6792  /* If this is a vector we are using the APSR_nzcv syntax, encode as r15 */
6793  if (inst.operands[2].isvec != 0)
6794    inst.instruction |= 15 << 12;
6795  else
6796    inst.instruction |= inst.operands[2].reg << 12;
6797  inst.instruction |= inst.operands[3].reg << 16;
6798  inst.instruction |= inst.operands[4].reg;
6799  inst.instruction |= inst.operands[5].imm << 5;
6800}
6801
6802/* Transfer between coprocessor register and pair of ARM registers.
6803   MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6804   MCRR2
6805   MRRC{cond}
6806   MRRC2
6807
6808   Two XScale instructions are special cases of these:
6809
6810     MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6811     MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6812
6813   Result unpredicatable if Rd or Rn is R15.  */
6814
6815static void
6816do_co_reg2c (void)
6817{
6818  inst.instruction |= inst.operands[0].reg << 8;
6819  inst.instruction |= inst.operands[1].imm << 4;
6820  inst.instruction |= inst.operands[2].reg << 12;
6821  inst.instruction |= inst.operands[3].reg << 16;
6822  inst.instruction |= inst.operands[4].reg;
6823}
6824
6825static void
6826do_cpsi (void)
6827{
6828  inst.instruction |= inst.operands[0].imm << 6;
6829  if (inst.operands[1].present)
6830    {
6831      inst.instruction |= CPSI_MMOD;
6832      inst.instruction |= inst.operands[1].imm;
6833    }
6834}
6835
6836static void
6837do_dbg (void)
6838{
6839  inst.instruction |= inst.operands[0].imm;
6840}
6841
6842static void
6843do_it (void)
6844{
6845  /* There is no IT instruction in ARM mode.  We
6846     process it but do not generate code for it.  */
6847  inst.size = 0;
6848}
6849
6850static void
6851do_ldmstm (void)
6852{
6853  int base_reg = inst.operands[0].reg;
6854  int range = inst.operands[1].imm;
6855
6856  inst.instruction |= base_reg << 16;
6857  inst.instruction |= range;
6858
6859  if (inst.operands[1].writeback)
6860    inst.instruction |= LDM_TYPE_2_OR_3;
6861
6862  if (inst.operands[0].writeback)
6863    {
6864      inst.instruction |= WRITE_BACK;
6865      /* Check for unpredictable uses of writeback.  */
6866      if (inst.instruction & LOAD_BIT)
6867	{
6868	  /* Not allowed in LDM type 2.	 */
6869	  if ((inst.instruction & LDM_TYPE_2_OR_3)
6870	      && ((range & (1 << REG_PC)) == 0))
6871	    as_warn (_("writeback of base register is UNPREDICTABLE"));
6872	  /* Only allowed if base reg not in list for other types.  */
6873	  else if (range & (1 << base_reg))
6874	    as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6875	}
6876      else /* STM.  */
6877	{
6878	  /* Not allowed for type 2.  */
6879	  if (inst.instruction & LDM_TYPE_2_OR_3)
6880	    as_warn (_("writeback of base register is UNPREDICTABLE"));
6881	  /* Only allowed if base reg not in list, or first in list.  */
6882	  else if ((range & (1 << base_reg))
6883		   && (range & ((1 << base_reg) - 1)))
6884	    as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6885	}
6886    }
6887}
6888
6889/* ARMv5TE load-consecutive (argument parse)
6890   Mode is like LDRH.
6891
6892     LDRccD R, mode
6893     STRccD R, mode.  */
6894
6895static void
6896do_ldrd (void)
6897{
6898  constraint (inst.operands[0].reg % 2 != 0,
6899	      _("first destination register must be even"));
6900  constraint (inst.operands[1].present
6901	      && inst.operands[1].reg != inst.operands[0].reg + 1,
6902	      _("can only load two consecutive registers"));
6903  constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
6904  constraint (!inst.operands[2].isreg, _("'[' expected"));
6905
6906  if (!inst.operands[1].present)
6907    inst.operands[1].reg = inst.operands[0].reg + 1;
6908
6909  if (inst.instruction & LOAD_BIT)
6910    {
6911      /* encode_arm_addr_mode_3 will diagnose overlap between the base
6912	 register and the first register written; we have to diagnose
6913	 overlap between the base and the second register written here.	 */
6914
6915      if (inst.operands[2].reg == inst.operands[1].reg
6916	  && (inst.operands[2].writeback || inst.operands[2].postind))
6917	as_warn (_("base register written back, and overlaps "
6918		   "second destination register"));
6919
6920      /* For an index-register load, the index register must not overlap the
6921	 destination (even if not write-back).	*/
6922      else if (inst.operands[2].immisreg
6923	       && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
6924		   || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
6925	as_warn (_("index register overlaps destination register"));
6926    }
6927
6928  inst.instruction |= inst.operands[0].reg << 12;
6929  encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
6930}
6931
6932static void
6933do_ldrex (void)
6934{
6935  constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6936	      || inst.operands[1].postind || inst.operands[1].writeback
6937	      || inst.operands[1].immisreg || inst.operands[1].shifted
6938	      || inst.operands[1].negative
6939	      /* This can arise if the programmer has written
6940		   strex rN, rM, foo
6941		 or if they have mistakenly used a register name as the last
6942		 operand,  eg:
6943		   strex rN, rM, rX
6944		 It is very difficult to distinguish between these two cases
6945		 because "rX" might actually be a label. ie the register
6946		 name has been occluded by a symbol of the same name. So we
6947		 just generate a general 'bad addressing mode' type error
6948		 message and leave it up to the programmer to discover the
6949		 true cause and fix their mistake.  */
6950	      || (inst.operands[1].reg == REG_PC),
6951	      BAD_ADDR_MODE);
6952
6953  constraint (inst.reloc.exp.X_op != O_constant
6954	      || inst.reloc.exp.X_add_number != 0,
6955	      _("offset must be zero in ARM encoding"));
6956
6957  inst.instruction |= inst.operands[0].reg << 12;
6958  inst.instruction |= inst.operands[1].reg << 16;
6959  inst.reloc.type = BFD_RELOC_UNUSED;
6960}
6961
6962static void
6963do_ldrexd (void)
6964{
6965  constraint (inst.operands[0].reg % 2 != 0,
6966	      _("even register required"));
6967  constraint (inst.operands[1].present
6968	      && inst.operands[1].reg != inst.operands[0].reg + 1,
6969	      _("can only load two consecutive registers"));
6970  /* If op 1 were present and equal to PC, this function wouldn't
6971     have been called in the first place.  */
6972  constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
6973
6974  inst.instruction |= inst.operands[0].reg << 12;
6975  inst.instruction |= inst.operands[2].reg << 16;
6976}
6977
6978static void
6979do_ldst (void)
6980{
6981  inst.instruction |= inst.operands[0].reg << 12;
6982  if (!inst.operands[1].isreg)
6983    if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
6984      return;
6985  encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
6986}
6987
6988static void
6989do_ldstt (void)
6990{
6991  /* ldrt/strt always use post-indexed addressing.  Turn [Rn] into [Rn]! and
6992     reject [Rn,...].  */
6993  if (inst.operands[1].preind)
6994    {
6995      constraint (inst.reloc.exp.X_op != O_constant ||
6996		  inst.reloc.exp.X_add_number != 0,
6997		  _("this instruction requires a post-indexed address"));
6998
6999      inst.operands[1].preind = 0;
7000      inst.operands[1].postind = 1;
7001      inst.operands[1].writeback = 1;
7002    }
7003  inst.instruction |= inst.operands[0].reg << 12;
7004  encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
7005}
7006
7007/* Halfword and signed-byte load/store operations.  */
7008
7009static void
7010do_ldstv4 (void)
7011{
7012  inst.instruction |= inst.operands[0].reg << 12;
7013  if (!inst.operands[1].isreg)
7014    if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
7015      return;
7016  encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
7017}
7018
7019static void
7020do_ldsttv4 (void)
7021{
7022  /* ldrt/strt always use post-indexed addressing.  Turn [Rn] into [Rn]! and
7023     reject [Rn,...].  */
7024  if (inst.operands[1].preind)
7025    {
7026      constraint (inst.reloc.exp.X_op != O_constant ||
7027		  inst.reloc.exp.X_add_number != 0,
7028		  _("this instruction requires a post-indexed address"));
7029
7030      inst.operands[1].preind = 0;
7031      inst.operands[1].postind = 1;
7032      inst.operands[1].writeback = 1;
7033    }
7034  inst.instruction |= inst.operands[0].reg << 12;
7035  encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7036}
7037
7038/* Co-processor register load/store.
7039   Format: <LDC|STC>{cond}[L] CP#,CRd,<address>	 */
7040static void
7041do_lstc (void)
7042{
7043  inst.instruction |= inst.operands[0].reg << 8;
7044  inst.instruction |= inst.operands[1].reg << 12;
7045  encode_arm_cp_address (2, TRUE, TRUE, 0);
7046}
7047
7048static void
7049do_mlas (void)
7050{
7051  /* This restriction does not apply to mls (nor to mla in v6 or later).  */
7052  if (inst.operands[0].reg == inst.operands[1].reg
7053      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
7054      && !(inst.instruction & 0x00400000))
7055    as_tsktsk (_("Rd and Rm should be different in mla"));
7056
7057  inst.instruction |= inst.operands[0].reg << 16;
7058  inst.instruction |= inst.operands[1].reg;
7059  inst.instruction |= inst.operands[2].reg << 8;
7060  inst.instruction |= inst.operands[3].reg << 12;
7061}
7062
7063static void
7064do_mov (void)
7065{
7066  inst.instruction |= inst.operands[0].reg << 12;
7067  encode_arm_shifter_operand (1);
7068}
7069
7070/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>.	 */
7071static void
7072do_mov16 (void)
7073{
7074  bfd_vma imm;
7075  bfd_boolean top;
7076
7077  top = (inst.instruction & 0x00400000) != 0;
7078  constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
7079	      _(":lower16: not allowed this instruction"));
7080  constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
7081	      _(":upper16: not allowed instruction"));
7082  inst.instruction |= inst.operands[0].reg << 12;
7083  if (inst.reloc.type == BFD_RELOC_UNUSED)
7084    {
7085      imm = inst.reloc.exp.X_add_number;
7086      /* The value is in two pieces: 0:11, 16:19.  */
7087      inst.instruction |= (imm & 0x00000fff);
7088      inst.instruction |= (imm & 0x0000f000) << 4;
7089    }
7090}
7091
7092static void do_vfp_nsyn_opcode (const char *);
7093
7094static int
7095do_vfp_nsyn_mrs (void)
7096{
7097  if (inst.operands[0].isvec)
7098    {
7099      if (inst.operands[1].reg != 1)
7100        first_error (_("operand 1 must be FPSCR"));
7101      memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
7102      memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
7103      do_vfp_nsyn_opcode ("fmstat");
7104    }
7105  else if (inst.operands[1].isvec)
7106    do_vfp_nsyn_opcode ("fmrx");
7107  else
7108    return FAIL;
7109
7110  return SUCCESS;
7111}
7112
7113static int
7114do_vfp_nsyn_msr (void)
7115{
7116  if (inst.operands[0].isvec)
7117    do_vfp_nsyn_opcode ("fmxr");
7118  else
7119    return FAIL;
7120
7121  return SUCCESS;
7122}
7123
7124static void
7125do_vfp_vmrs (void)
7126{
7127  int rt;
7128
7129  /* The destination register can be r0-r14 or APSR_nzcv */
7130  if (inst.operands[0].reg > 14)
7131    {
7132      inst.error = BAD_PC;
7133      return;
7134    }
7135
7136  /* If the destination is r13 and not in ARM mode then unprefictable */
7137  if (thumb_mode && inst.operands[0].reg == REG_SP)
7138    {
7139      inst.error = BAD_SP;
7140      return;
7141    }
7142
7143  /* If the destination is APSR_nzcv */
7144  if (inst.operands[0].isvec && inst.operands[1].reg != 1)
7145    {
7146      inst.error = BAD_VMRS;
7147      return;
7148    }
7149
7150  if (inst.operands[0].isvec)
7151    rt = 15;
7152  else
7153    rt = inst.operands[0].reg;
7154
7155  /* Or in the registers to use */
7156  inst.instruction |= rt << 12;
7157  inst.instruction |= inst.operands[1].reg << 16;
7158}
7159
7160static void
7161do_vfp_vmsr (void)
7162{
7163  /* The destination register can be r0-r14 or APSR_nzcv */
7164  if (inst.operands[1].reg > 14)
7165    {
7166      inst.error = BAD_PC;
7167      return;
7168    }
7169
7170  /* If the destination is r13 and not in ARM mode then unprefictable */
7171  if (thumb_mode && inst.operands[0].reg == REG_SP)
7172    {
7173      inst.error = BAD_SP;
7174      return;
7175    }
7176
7177  /* Or in the registers to use */
7178  inst.instruction |= inst.operands[1].reg << 12;
7179  inst.instruction |= inst.operands[0].reg << 16;
7180}
7181
7182static void
7183do_mrs (void)
7184{
7185  if (do_vfp_nsyn_mrs () == SUCCESS)
7186    return;
7187
7188  /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all.  */
7189  constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
7190	      != (PSR_c|PSR_f),
7191	      _("'CPSR' or 'SPSR' expected"));
7192  inst.instruction |= inst.operands[0].reg << 12;
7193  inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
7194}
7195
7196/* Two possible forms:
7197      "{C|S}PSR_<field>, Rm",
7198      "{C|S}PSR_f, #expression".  */
7199
7200static void
7201do_msr (void)
7202{
7203  if (do_vfp_nsyn_msr () == SUCCESS)
7204    return;
7205
7206  inst.instruction |= inst.operands[0].imm;
7207  if (inst.operands[1].isreg)
7208    inst.instruction |= inst.operands[1].reg;
7209  else
7210    {
7211      inst.instruction |= INST_IMMEDIATE;
7212      inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7213      inst.reloc.pc_rel = 0;
7214    }
7215}
7216
7217static void
7218do_mul (void)
7219{
7220  if (!inst.operands[2].present)
7221    inst.operands[2].reg = inst.operands[0].reg;
7222  inst.instruction |= inst.operands[0].reg << 16;
7223  inst.instruction |= inst.operands[1].reg;
7224  inst.instruction |= inst.operands[2].reg << 8;
7225
7226  if (inst.operands[0].reg == inst.operands[1].reg
7227      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7228    as_tsktsk (_("Rd and Rm should be different in mul"));
7229}
7230
7231/* Long Multiply Parser
7232   UMULL RdLo, RdHi, Rm, Rs
7233   SMULL RdLo, RdHi, Rm, Rs
7234   UMLAL RdLo, RdHi, Rm, Rs
7235   SMLAL RdLo, RdHi, Rm, Rs.  */
7236
7237static void
7238do_mull (void)
7239{
7240  inst.instruction |= inst.operands[0].reg << 12;
7241  inst.instruction |= inst.operands[1].reg << 16;
7242  inst.instruction |= inst.operands[2].reg;
7243  inst.instruction |= inst.operands[3].reg << 8;
7244
7245  /* rdhi, rdlo and rm must all be different prior to ARMv6.  */
7246  if (inst.operands[0].reg == inst.operands[1].reg
7247      || ((inst.operands[0].reg == inst.operands[2].reg
7248      || inst.operands[1].reg == inst.operands[2].reg)
7249      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)))
7250    as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7251}
7252
7253static void
7254do_nop (void)
7255{
7256  if (inst.operands[0].present)
7257    {
7258      /* Architectural NOP hints are CPSR sets with no bits selected.  */
7259      inst.instruction &= 0xf0000000;
7260      inst.instruction |= 0x0320f000 + inst.operands[0].imm;
7261    }
7262}
7263
7264/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7265   PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7266   Condition defaults to COND_ALWAYS.
7267   Error if Rd, Rn or Rm are R15.  */
7268
7269static void
7270do_pkhbt (void)
7271{
7272  inst.instruction |= inst.operands[0].reg << 12;
7273  inst.instruction |= inst.operands[1].reg << 16;
7274  inst.instruction |= inst.operands[2].reg;
7275  if (inst.operands[3].present)
7276    encode_arm_shift (3);
7277}
7278
7279/* ARM V6 PKHTB (Argument Parse).  */
7280
7281static void
7282do_pkhtb (void)
7283{
7284  if (!inst.operands[3].present)
7285    {
7286      /* If the shift specifier is omitted, turn the instruction
7287	 into pkhbt rd, rm, rn. */
7288      inst.instruction &= 0xfff00010;
7289      inst.instruction |= inst.operands[0].reg << 12;
7290      inst.instruction |= inst.operands[1].reg;
7291      inst.instruction |= inst.operands[2].reg << 16;
7292    }
7293  else
7294    {
7295      inst.instruction |= inst.operands[0].reg << 12;
7296      inst.instruction |= inst.operands[1].reg << 16;
7297      inst.instruction |= inst.operands[2].reg;
7298      encode_arm_shift (3);
7299    }
7300}
7301
7302/* ARMv5TE: Preload-Cache
7303
7304    PLD <addr_mode>
7305
7306  Syntactically, like LDR with B=1, W=0, L=1.  */
7307
7308static void
7309do_pld (void)
7310{
7311  constraint (!inst.operands[0].isreg,
7312	      _("'[' expected after PLD mnemonic"));
7313  constraint (inst.operands[0].postind,
7314	      _("post-indexed expression used in preload instruction"));
7315  constraint (inst.operands[0].writeback,
7316	      _("writeback used in preload instruction"));
7317  constraint (!inst.operands[0].preind,
7318	      _("unindexed addressing used in preload instruction"));
7319  encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7320}
7321
7322/* ARMv7: PLI <addr_mode>  */
7323static void
7324do_pli (void)
7325{
7326  constraint (!inst.operands[0].isreg,
7327	      _("'[' expected after PLI mnemonic"));
7328  constraint (inst.operands[0].postind,
7329	      _("post-indexed expression used in preload instruction"));
7330  constraint (inst.operands[0].writeback,
7331	      _("writeback used in preload instruction"));
7332  constraint (!inst.operands[0].preind,
7333	      _("unindexed addressing used in preload instruction"));
7334  encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7335  inst.instruction &= ~PRE_INDEX;
7336}
7337
7338static void
7339do_push_pop (void)
7340{
7341  inst.operands[1] = inst.operands[0];
7342  memset (&inst.operands[0], 0, sizeof inst.operands[0]);
7343  inst.operands[0].isreg = 1;
7344  inst.operands[0].writeback = 1;
7345  inst.operands[0].reg = REG_SP;
7346  do_ldmstm ();
7347}
7348
7349/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7350   word at the specified address and the following word
7351   respectively.
7352   Unconditionally executed.
7353   Error if Rn is R15.	*/
7354
7355static void
7356do_rfe (void)
7357{
7358  inst.instruction |= inst.operands[0].reg << 16;
7359  if (inst.operands[0].writeback)
7360    inst.instruction |= WRITE_BACK;
7361}
7362
7363/* ARM V6 ssat (argument parse).  */
7364
7365static void
7366do_ssat (void)
7367{
7368  inst.instruction |= inst.operands[0].reg << 12;
7369  inst.instruction |= (inst.operands[1].imm - 1) << 16;
7370  inst.instruction |= inst.operands[2].reg;
7371
7372  if (inst.operands[3].present)
7373    encode_arm_shift (3);
7374}
7375
7376/* ARM V6 usat (argument parse).  */
7377
7378static void
7379do_usat (void)
7380{
7381  inst.instruction |= inst.operands[0].reg << 12;
7382  inst.instruction |= inst.operands[1].imm << 16;
7383  inst.instruction |= inst.operands[2].reg;
7384
7385  if (inst.operands[3].present)
7386    encode_arm_shift (3);
7387}
7388
7389/* ARM V6 ssat16 (argument parse).  */
7390
7391static void
7392do_ssat16 (void)
7393{
7394  inst.instruction |= inst.operands[0].reg << 12;
7395  inst.instruction |= ((inst.operands[1].imm - 1) << 16);
7396  inst.instruction |= inst.operands[2].reg;
7397}
7398
7399static void
7400do_usat16 (void)
7401{
7402  inst.instruction |= inst.operands[0].reg << 12;
7403  inst.instruction |= inst.operands[1].imm << 16;
7404  inst.instruction |= inst.operands[2].reg;
7405}
7406
7407/* ARM V6 SETEND (argument parse).  Sets the E bit in the CPSR while
7408   preserving the other bits.
7409
7410   setend <endian_specifier>, where <endian_specifier> is either
7411   BE or LE.  */
7412
7413static void
7414do_setend (void)
7415{
7416  if (inst.operands[0].imm)
7417    inst.instruction |= 0x200;
7418}
7419
7420static void
7421do_shift (void)
7422{
7423  unsigned int Rm = (inst.operands[1].present
7424		     ? inst.operands[1].reg
7425		     : inst.operands[0].reg);
7426
7427  inst.instruction |= inst.operands[0].reg << 12;
7428  inst.instruction |= Rm;
7429  if (inst.operands[2].isreg)  /* Rd, {Rm,} Rs */
7430    {
7431      inst.instruction |= inst.operands[2].reg << 8;
7432      inst.instruction |= SHIFT_BY_REG;
7433    }
7434  else
7435    inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7436}
7437
7438static void
7439do_smc (void)
7440{
7441  inst.reloc.type = BFD_RELOC_ARM_SMC;
7442  inst.reloc.pc_rel = 0;
7443}
7444
7445static void
7446do_swi (void)
7447{
7448  inst.reloc.type = BFD_RELOC_ARM_SWI;
7449  inst.reloc.pc_rel = 0;
7450}
7451
7452/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7453   SMLAxy{cond} Rd,Rm,Rs,Rn
7454   SMLAWy{cond} Rd,Rm,Rs,Rn
7455   Error if any register is R15.  */
7456
7457static void
7458do_smla (void)
7459{
7460  inst.instruction |= inst.operands[0].reg << 16;
7461  inst.instruction |= inst.operands[1].reg;
7462  inst.instruction |= inst.operands[2].reg << 8;
7463  inst.instruction |= inst.operands[3].reg << 12;
7464}
7465
7466/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7467   SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7468   Error if any register is R15.
7469   Warning if Rdlo == Rdhi.  */
7470
7471static void
7472do_smlal (void)
7473{
7474  inst.instruction |= inst.operands[0].reg << 12;
7475  inst.instruction |= inst.operands[1].reg << 16;
7476  inst.instruction |= inst.operands[2].reg;
7477  inst.instruction |= inst.operands[3].reg << 8;
7478
7479  if (inst.operands[0].reg == inst.operands[1].reg)
7480    as_tsktsk (_("rdhi and rdlo must be different"));
7481}
7482
7483/* ARM V5E (El Segundo) signed-multiply (argument parse)
7484   SMULxy{cond} Rd,Rm,Rs
7485   Error if any register is R15.  */
7486
7487static void
7488do_smul (void)
7489{
7490  inst.instruction |= inst.operands[0].reg << 16;
7491  inst.instruction |= inst.operands[1].reg;
7492  inst.instruction |= inst.operands[2].reg << 8;
7493}
7494
7495/* ARM V6 srs (argument parse).  The variable fields in the encoding are
7496   the same for both ARM and Thumb-2.  */
7497
7498static void
7499do_srs (void)
7500{
7501  int reg;
7502
7503  if (inst.operands[0].present)
7504    {
7505      reg = inst.operands[0].reg;
7506      constraint (reg != 13, _("SRS base register must be r13"));
7507    }
7508  else
7509    reg = 13;
7510
7511  inst.instruction |= reg << 16;
7512  inst.instruction |= inst.operands[1].imm;
7513  if (inst.operands[0].writeback || inst.operands[1].writeback)
7514    inst.instruction |= WRITE_BACK;
7515}
7516
7517/* ARM V6 strex (argument parse).  */
7518
7519static void
7520do_strex (void)
7521{
7522  constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7523	      || inst.operands[2].postind || inst.operands[2].writeback
7524	      || inst.operands[2].immisreg || inst.operands[2].shifted
7525	      || inst.operands[2].negative
7526	      /* See comment in do_ldrex().  */
7527	      || (inst.operands[2].reg == REG_PC),
7528	      BAD_ADDR_MODE);
7529
7530  constraint (inst.operands[0].reg == inst.operands[1].reg
7531	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
7532
7533  constraint (inst.reloc.exp.X_op != O_constant
7534	      || inst.reloc.exp.X_add_number != 0,
7535	      _("offset must be zero in ARM encoding"));
7536
7537  inst.instruction |= inst.operands[0].reg << 12;
7538  inst.instruction |= inst.operands[1].reg;
7539  inst.instruction |= inst.operands[2].reg << 16;
7540  inst.reloc.type = BFD_RELOC_UNUSED;
7541}
7542
7543static void
7544do_strexd (void)
7545{
7546  constraint (inst.operands[1].reg % 2 != 0,
7547	      _("even register required"));
7548  constraint (inst.operands[2].present
7549	      && inst.operands[2].reg != inst.operands[1].reg + 1,
7550	      _("can only store two consecutive registers"));
7551  /* If op 2 were present and equal to PC, this function wouldn't
7552     have been called in the first place.  */
7553  constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
7554
7555  constraint (inst.operands[0].reg == inst.operands[1].reg
7556	      || inst.operands[0].reg == inst.operands[1].reg + 1
7557	      || inst.operands[0].reg == inst.operands[3].reg,
7558	      BAD_OVERLAP);
7559
7560  inst.instruction |= inst.operands[0].reg << 12;
7561  inst.instruction |= inst.operands[1].reg;
7562  inst.instruction |= inst.operands[3].reg << 16;
7563}
7564
7565/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7566   extends it to 32-bits, and adds the result to a value in another
7567   register.  You can specify a rotation by 0, 8, 16, or 24 bits
7568   before extracting the 16-bit value.
7569   SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7570   Condition defaults to COND_ALWAYS.
7571   Error if any register uses R15.  */
7572
7573static void
7574do_sxtah (void)
7575{
7576  inst.instruction |= inst.operands[0].reg << 12;
7577  inst.instruction |= inst.operands[1].reg << 16;
7578  inst.instruction |= inst.operands[2].reg;
7579  inst.instruction |= inst.operands[3].imm << 10;
7580}
7581
7582/* ARM V6 SXTH.
7583
7584   SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7585   Condition defaults to COND_ALWAYS.
7586   Error if any register uses R15.  */
7587
7588static void
7589do_sxth (void)
7590{
7591  inst.instruction |= inst.operands[0].reg << 12;
7592  inst.instruction |= inst.operands[1].reg;
7593  inst.instruction |= inst.operands[2].imm << 10;
7594}
7595
7596/* VFP instructions.  In a logical order: SP variant first, monad
7597   before dyad, arithmetic then move then load/store.  */
7598
7599static void
7600do_vfp_sp_monadic (void)
7601{
7602  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7603  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
7604}
7605
7606static void
7607do_vfp_sp_dyadic (void)
7608{
7609  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7610  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7611  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
7612}
7613
7614static void
7615do_vfp_sp_compare_z (void)
7616{
7617  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7618}
7619
7620static void
7621do_vfp_dp_sp_cvt (void)
7622{
7623  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7624  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
7625}
7626
7627static void
7628do_vfp_sp_dp_cvt (void)
7629{
7630  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7631  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7632}
7633
7634static void
7635do_vfp_reg_from_sp (void)
7636{
7637  inst.instruction |= inst.operands[0].reg << 12;
7638  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7639}
7640
7641static void
7642do_vfp_reg2_from_sp2 (void)
7643{
7644  constraint (inst.operands[2].imm != 2,
7645	      _("only two consecutive VFP SP registers allowed here"));
7646  inst.instruction |= inst.operands[0].reg << 12;
7647  inst.instruction |= inst.operands[1].reg << 16;
7648  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
7649}
7650
7651static void
7652do_vfp_sp_from_reg (void)
7653{
7654  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
7655  inst.instruction |= inst.operands[1].reg << 12;
7656}
7657
7658static void
7659do_vfp_sp2_from_reg2 (void)
7660{
7661  constraint (inst.operands[0].imm != 2,
7662	      _("only two consecutive VFP SP registers allowed here"));
7663  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
7664  inst.instruction |= inst.operands[1].reg << 12;
7665  inst.instruction |= inst.operands[2].reg << 16;
7666}
7667
7668static void
7669do_vfp_sp_ldst (void)
7670{
7671  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7672  encode_arm_cp_address (1, FALSE, TRUE, 0);
7673}
7674
7675static void
7676do_vfp_dp_ldst (void)
7677{
7678  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7679  encode_arm_cp_address (1, FALSE, TRUE, 0);
7680}
7681
7682
7683static void
7684vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
7685{
7686  if (inst.operands[0].writeback)
7687    inst.instruction |= WRITE_BACK;
7688  else
7689    constraint (ldstm_type != VFP_LDSTMIA,
7690		_("this addressing mode requires base-register writeback"));
7691  inst.instruction |= inst.operands[0].reg << 16;
7692  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
7693  inst.instruction |= inst.operands[1].imm;
7694}
7695
7696static void
7697vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
7698{
7699  int count;
7700
7701  if (inst.operands[0].writeback)
7702    inst.instruction |= WRITE_BACK;
7703  else
7704    constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
7705		_("this addressing mode requires base-register writeback"));
7706
7707  inst.instruction |= inst.operands[0].reg << 16;
7708  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7709
7710  count = inst.operands[1].imm << 1;
7711  if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
7712    count += 1;
7713
7714  inst.instruction |= count;
7715}
7716
7717static void
7718do_vfp_sp_ldstmia (void)
7719{
7720  vfp_sp_ldstm (VFP_LDSTMIA);
7721}
7722
7723static void
7724do_vfp_sp_ldstmdb (void)
7725{
7726  vfp_sp_ldstm (VFP_LDSTMDB);
7727}
7728
7729static void
7730do_vfp_dp_ldstmia (void)
7731{
7732  vfp_dp_ldstm (VFP_LDSTMIA);
7733}
7734
7735static void
7736do_vfp_dp_ldstmdb (void)
7737{
7738  vfp_dp_ldstm (VFP_LDSTMDB);
7739}
7740
7741static void
7742do_vfp_xp_ldstmia (void)
7743{
7744  vfp_dp_ldstm (VFP_LDSTMIAX);
7745}
7746
7747static void
7748do_vfp_xp_ldstmdb (void)
7749{
7750  vfp_dp_ldstm (VFP_LDSTMDBX);
7751}
7752
7753static void
7754do_vfp_dp_rd_rm (void)
7755{
7756  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7757  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7758}
7759
7760static void
7761do_vfp_dp_rn_rd (void)
7762{
7763  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
7764  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7765}
7766
7767static void
7768do_vfp_dp_rd_rn (void)
7769{
7770  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7771  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7772}
7773
7774static void
7775do_vfp_dp_rd_rn_rm (void)
7776{
7777  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7778  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7779  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
7780}
7781
7782static void
7783do_vfp_dp_rd (void)
7784{
7785  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7786}
7787
7788static void
7789do_vfp_dp_rm_rd_rn (void)
7790{
7791  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
7792  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7793  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
7794}
7795
7796/* VFPv3 instructions.  */
7797static void
7798do_vfp_sp_const (void)
7799{
7800  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7801  inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7802  inst.instruction |= (inst.operands[1].imm & 0x0f);
7803}
7804
7805static void
7806do_vfp_dp_const (void)
7807{
7808  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7809  inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7810  inst.instruction |= (inst.operands[1].imm & 0x0f);
7811}
7812
7813static void
7814vfp_conv (int srcsize)
7815{
7816  unsigned immbits = srcsize - inst.operands[1].imm;
7817  inst.instruction |= (immbits & 1) << 5;
7818  inst.instruction |= (immbits >> 1);
7819}
7820
7821static void
7822do_vfp_sp_conv_16 (void)
7823{
7824  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7825  vfp_conv (16);
7826}
7827
7828static void
7829do_vfp_dp_conv_16 (void)
7830{
7831  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7832  vfp_conv (16);
7833}
7834
7835static void
7836do_vfp_sp_conv_32 (void)
7837{
7838  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7839  vfp_conv (32);
7840}
7841
7842static void
7843do_vfp_dp_conv_32 (void)
7844{
7845  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7846  vfp_conv (32);
7847}
7848
7849
7850/* FPA instructions.  Also in a logical order.	*/
7851
7852static void
7853do_fpa_cmp (void)
7854{
7855  inst.instruction |= inst.operands[0].reg << 16;
7856  inst.instruction |= inst.operands[1].reg;
7857}
7858
7859static void
7860do_fpa_ldmstm (void)
7861{
7862  inst.instruction |= inst.operands[0].reg << 12;
7863  switch (inst.operands[1].imm)
7864    {
7865    case 1: inst.instruction |= CP_T_X;		 break;
7866    case 2: inst.instruction |= CP_T_Y;		 break;
7867    case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
7868    case 4:					 break;
7869    default: abort ();
7870    }
7871
7872  if (inst.instruction & (PRE_INDEX | INDEX_UP))
7873    {
7874      /* The instruction specified "ea" or "fd", so we can only accept
7875	 [Rn]{!}.  The instruction does not really support stacking or
7876	 unstacking, so we have to emulate these by setting appropriate
7877	 bits and offsets.  */
7878      constraint (inst.reloc.exp.X_op != O_constant
7879		  || inst.reloc.exp.X_add_number != 0,
7880		  _("this instruction does not support indexing"));
7881
7882      if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
7883	inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
7884
7885      if (!(inst.instruction & INDEX_UP))
7886	inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
7887
7888      if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
7889	{
7890	  inst.operands[2].preind = 0;
7891	  inst.operands[2].postind = 1;
7892	}
7893    }
7894
7895  encode_arm_cp_address (2, TRUE, TRUE, 0);
7896}
7897
7898
7899/* iWMMXt instructions: strictly in alphabetical order.	 */
7900
7901static void
7902do_iwmmxt_tandorc (void)
7903{
7904  constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
7905}
7906
7907static void
7908do_iwmmxt_textrc (void)
7909{
7910  inst.instruction |= inst.operands[0].reg << 12;
7911  inst.instruction |= inst.operands[1].imm;
7912}
7913
7914static void
7915do_iwmmxt_textrm (void)
7916{
7917  inst.instruction |= inst.operands[0].reg << 12;
7918  inst.instruction |= inst.operands[1].reg << 16;
7919  inst.instruction |= inst.operands[2].imm;
7920}
7921
7922static void
7923do_iwmmxt_tinsr (void)
7924{
7925  inst.instruction |= inst.operands[0].reg << 16;
7926  inst.instruction |= inst.operands[1].reg << 12;
7927  inst.instruction |= inst.operands[2].imm;
7928}
7929
7930static void
7931do_iwmmxt_tmia (void)
7932{
7933  inst.instruction |= inst.operands[0].reg << 5;
7934  inst.instruction |= inst.operands[1].reg;
7935  inst.instruction |= inst.operands[2].reg << 12;
7936}
7937
7938static void
7939do_iwmmxt_waligni (void)
7940{
7941  inst.instruction |= inst.operands[0].reg << 12;
7942  inst.instruction |= inst.operands[1].reg << 16;
7943  inst.instruction |= inst.operands[2].reg;
7944  inst.instruction |= inst.operands[3].imm << 20;
7945}
7946
7947static void
7948do_iwmmxt_wmerge (void)
7949{
7950  inst.instruction |= inst.operands[0].reg << 12;
7951  inst.instruction |= inst.operands[1].reg << 16;
7952  inst.instruction |= inst.operands[2].reg;
7953  inst.instruction |= inst.operands[3].imm << 21;
7954}
7955
7956static void
7957do_iwmmxt_wmov (void)
7958{
7959  /* WMOV rD, rN is an alias for WOR rD, rN, rN.  */
7960  inst.instruction |= inst.operands[0].reg << 12;
7961  inst.instruction |= inst.operands[1].reg << 16;
7962  inst.instruction |= inst.operands[1].reg;
7963}
7964
7965static void
7966do_iwmmxt_wldstbh (void)
7967{
7968  int reloc;
7969  inst.instruction |= inst.operands[0].reg << 12;
7970  if (thumb_mode)
7971    reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
7972  else
7973    reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
7974  encode_arm_cp_address (1, TRUE, FALSE, reloc);
7975}
7976
7977static void
7978do_iwmmxt_wldstw (void)
7979{
7980  /* RIWR_RIWC clears .isreg for a control register.  */
7981  if (!inst.operands[0].isreg)
7982    {
7983      constraint (inst.cond != COND_ALWAYS, BAD_COND);
7984      inst.instruction |= 0xf0000000;
7985    }
7986
7987  inst.instruction |= inst.operands[0].reg << 12;
7988  encode_arm_cp_address (1, TRUE, TRUE, 0);
7989}
7990
7991static void
7992do_iwmmxt_wldstd (void)
7993{
7994  inst.instruction |= inst.operands[0].reg << 12;
7995  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
7996      && inst.operands[1].immisreg)
7997    {
7998      inst.instruction &= ~0x1a000ff;
7999      inst.instruction |= (0xf << 28);
8000      if (inst.operands[1].preind)
8001	inst.instruction |= PRE_INDEX;
8002      if (!inst.operands[1].negative)
8003	inst.instruction |= INDEX_UP;
8004      if (inst.operands[1].writeback)
8005	inst.instruction |= WRITE_BACK;
8006      inst.instruction |= inst.operands[1].reg << 16;
8007      inst.instruction |= inst.reloc.exp.X_add_number << 4;
8008      inst.instruction |= inst.operands[1].imm;
8009    }
8010  else
8011    encode_arm_cp_address (1, TRUE, FALSE, 0);
8012}
8013
8014static void
8015do_iwmmxt_wshufh (void)
8016{
8017  inst.instruction |= inst.operands[0].reg << 12;
8018  inst.instruction |= inst.operands[1].reg << 16;
8019  inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
8020  inst.instruction |= (inst.operands[2].imm & 0x0f);
8021}
8022
8023static void
8024do_iwmmxt_wzero (void)
8025{
8026  /* WZERO reg is an alias for WANDN reg, reg, reg.  */
8027  inst.instruction |= inst.operands[0].reg;
8028  inst.instruction |= inst.operands[0].reg << 12;
8029  inst.instruction |= inst.operands[0].reg << 16;
8030}
8031
8032static void
8033do_iwmmxt_wrwrwr_or_imm5 (void)
8034{
8035  if (inst.operands[2].isreg)
8036    do_rd_rn_rm ();
8037  else {
8038    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
8039		_("immediate operand requires iWMMXt2"));
8040    do_rd_rn ();
8041    if (inst.operands[2].imm == 0)
8042      {
8043	switch ((inst.instruction >> 20) & 0xf)
8044	  {
8045	  case 4:
8046	  case 5:
8047	  case 6:
8048	  case 7:
8049	    /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16.  */
8050	    inst.operands[2].imm = 16;
8051	    inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
8052	    break;
8053	  case 8:
8054	  case 9:
8055	  case 10:
8056	  case 11:
8057	    /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32.  */
8058	    inst.operands[2].imm = 32;
8059	    inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
8060	    break;
8061	  case 12:
8062	  case 13:
8063	  case 14:
8064	  case 15:
8065	    {
8066	      /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn.  */
8067	      unsigned long wrn;
8068	      wrn = (inst.instruction >> 16) & 0xf;
8069	      inst.instruction &= 0xff0fff0f;
8070	      inst.instruction |= wrn;
8071	      /* Bail out here; the instruction is now assembled.  */
8072	      return;
8073	    }
8074	  }
8075      }
8076    /* Map 32 -> 0, etc.  */
8077    inst.operands[2].imm &= 0x1f;
8078    inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
8079  }
8080}
8081
8082/* Cirrus Maverick instructions.  Simple 2-, 3-, and 4-register
8083   operations first, then control, shift, and load/store.  */
8084
8085/* Insns like "foo X,Y,Z".  */
8086
8087static void
8088do_mav_triple (void)
8089{
8090  inst.instruction |= inst.operands[0].reg << 16;
8091  inst.instruction |= inst.operands[1].reg;
8092  inst.instruction |= inst.operands[2].reg << 12;
8093}
8094
8095/* Insns like "foo W,X,Y,Z".
8096    where W=MVAX[0:3] and X,Y,Z=MVFX[0:15].  */
8097
8098static void
8099do_mav_quad (void)
8100{
8101  inst.instruction |= inst.operands[0].reg << 5;
8102  inst.instruction |= inst.operands[1].reg << 12;
8103  inst.instruction |= inst.operands[2].reg << 16;
8104  inst.instruction |= inst.operands[3].reg;
8105}
8106
8107/* cfmvsc32<cond> DSPSC,MVDX[15:0].  */
8108static void
8109do_mav_dspsc (void)
8110{
8111  inst.instruction |= inst.operands[1].reg << 12;
8112}
8113
8114/* Maverick shift immediate instructions.
8115   cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8116   cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0].  */
8117
8118static void
8119do_mav_shift (void)
8120{
8121  int imm = inst.operands[2].imm;
8122
8123  inst.instruction |= inst.operands[0].reg << 12;
8124  inst.instruction |= inst.operands[1].reg << 16;
8125
8126  /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8127     Bits 5-7 of the insn should have bits 4-6 of the immediate.
8128     Bit 4 should be 0.	 */
8129  imm = (imm & 0xf) | ((imm & 0x70) << 1);
8130
8131  inst.instruction |= imm;
8132}
8133
8134/* XScale instructions.	 Also sorted arithmetic before move.  */
8135
8136/* Xscale multiply-accumulate (argument parse)
8137     MIAcc   acc0,Rm,Rs
8138     MIAPHcc acc0,Rm,Rs
8139     MIAxycc acc0,Rm,Rs.  */
8140
8141static void
8142do_xsc_mia (void)
8143{
8144  inst.instruction |= inst.operands[1].reg;
8145  inst.instruction |= inst.operands[2].reg << 12;
8146}
8147
8148/* Xscale move-accumulator-register (argument parse)
8149
8150     MARcc   acc0,RdLo,RdHi.  */
8151
8152static void
8153do_xsc_mar (void)
8154{
8155  inst.instruction |= inst.operands[1].reg << 12;
8156  inst.instruction |= inst.operands[2].reg << 16;
8157}
8158
8159/* Xscale move-register-accumulator (argument parse)
8160
8161     MRAcc   RdLo,RdHi,acc0.  */
8162
8163static void
8164do_xsc_mra (void)
8165{
8166  constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
8167  inst.instruction |= inst.operands[0].reg << 12;
8168  inst.instruction |= inst.operands[1].reg << 16;
8169}
8170
8171/* Encoding functions relevant only to Thumb.  */
8172
8173/* inst.operands[i] is a shifted-register operand; encode
8174   it into inst.instruction in the format used by Thumb32.  */
8175
8176static void
8177encode_thumb32_shifted_operand (int i)
8178{
8179  unsigned int value = inst.reloc.exp.X_add_number;
8180  unsigned int shift = inst.operands[i].shift_kind;
8181
8182  constraint (inst.operands[i].immisreg,
8183	      _("shift by register not allowed in thumb mode"));
8184  inst.instruction |= inst.operands[i].reg;
8185  if (shift == SHIFT_RRX)
8186    inst.instruction |= SHIFT_ROR << 4;
8187  else
8188    {
8189      constraint (inst.reloc.exp.X_op != O_constant,
8190		  _("expression too complex"));
8191
8192      constraint (value > 32
8193		  || (value == 32 && (shift == SHIFT_LSL
8194				      || shift == SHIFT_ROR)),
8195		  _("shift expression is too large"));
8196
8197      if (value == 0)
8198	shift = SHIFT_LSL;
8199      else if (value == 32)
8200	value = 0;
8201
8202      inst.instruction |= shift << 4;
8203      inst.instruction |= (value & 0x1c) << 10;
8204      inst.instruction |= (value & 0x03) << 6;
8205    }
8206}
8207
8208
8209/* inst.operands[i] was set up by parse_address.  Encode it into a
8210   Thumb32 format load or store instruction.  Reject forms that cannot
8211   be used with such instructions.  If is_t is true, reject forms that
8212   cannot be used with a T instruction; if is_d is true, reject forms
8213   that cannot be used with a D instruction.  */
8214
8215static void
8216encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
8217{
8218  bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8219
8220  constraint (!inst.operands[i].isreg,
8221	      _("Instruction does not support =N addresses"));
8222
8223  inst.instruction |= inst.operands[i].reg << 16;
8224  if (inst.operands[i].immisreg)
8225    {
8226      constraint (is_pc, _("cannot use register index with PC-relative addressing"));
8227      constraint (is_t || is_d, _("cannot use register index with this instruction"));
8228      constraint (inst.operands[i].negative,
8229		  _("Thumb does not support negative register indexing"));
8230      constraint (inst.operands[i].postind,
8231		  _("Thumb does not support register post-indexing"));
8232      constraint (inst.operands[i].writeback,
8233		  _("Thumb does not support register indexing with writeback"));
8234      constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
8235		  _("Thumb supports only LSL in shifted register indexing"));
8236
8237      inst.instruction |= inst.operands[i].imm;
8238      if (inst.operands[i].shifted)
8239	{
8240	  constraint (inst.reloc.exp.X_op != O_constant,
8241		      _("expression too complex"));
8242	  constraint (inst.reloc.exp.X_add_number < 0
8243		      || inst.reloc.exp.X_add_number > 3,
8244		      _("shift out of range"));
8245	  inst.instruction |= inst.reloc.exp.X_add_number << 4;
8246	}
8247      inst.reloc.type = BFD_RELOC_UNUSED;
8248    }
8249  else if (inst.operands[i].preind)
8250    {
8251      constraint (is_pc && inst.operands[i].writeback,
8252		  _("cannot use writeback with PC-relative addressing"));
8253      constraint (is_t && inst.operands[i].writeback,
8254		  _("cannot use writeback with this instruction"));
8255
8256      if (is_d)
8257	{
8258	  inst.instruction |= 0x01000000;
8259	  if (inst.operands[i].writeback)
8260	    inst.instruction |= 0x00200000;
8261	}
8262      else
8263	{
8264	  inst.instruction |= 0x00000c00;
8265	  if (inst.operands[i].writeback)
8266	    inst.instruction |= 0x00000100;
8267	}
8268      inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
8269    }
8270  else if (inst.operands[i].postind)
8271    {
8272      assert (inst.operands[i].writeback);
8273      constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
8274      constraint (is_t, _("cannot use post-indexing with this instruction"));
8275
8276      if (is_d)
8277	inst.instruction |= 0x00200000;
8278      else
8279	inst.instruction |= 0x00000900;
8280      inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
8281    }
8282  else /* unindexed - only for coprocessor */
8283    inst.error = _("instruction does not accept unindexed addressing");
8284}
8285
8286/* Table of Thumb instructions which exist in both 16- and 32-bit
8287   encodings (the latter only in post-V6T2 cores).  The index is the
8288   value used in the insns table below.  When there is more than one
8289   possible 16-bit encoding for the instruction, this table always
8290   holds variant (1).
8291   Also contains several pseudo-instructions used during relaxation.  */
8292#define T16_32_TAB				\
8293  X(adc,   4140, eb400000),			\
8294  X(adcs,  4140, eb500000),			\
8295  X(add,   1c00, eb000000),			\
8296  X(adds,  1c00, eb100000),			\
8297  X(addi,  0000, f1000000),			\
8298  X(addis, 0000, f1100000),			\
8299  X(add_pc,000f, f20f0000),			\
8300  X(add_sp,000d, f10d0000),			\
8301  X(adr,   000f, f20f0000),			\
8302  X(and,   4000, ea000000),			\
8303  X(ands,  4000, ea100000),			\
8304  X(asr,   1000, fa40f000),			\
8305  X(asrs,  1000, fa50f000),			\
8306  X(b,     e000, f000b000),			\
8307  X(bcond, d000, f0008000),			\
8308  X(bic,   4380, ea200000),			\
8309  X(bics,  4380, ea300000),			\
8310  X(cmn,   42c0, eb100f00),			\
8311  X(cmp,   2800, ebb00f00),			\
8312  X(cpsie, b660, f3af8400),			\
8313  X(cpsid, b670, f3af8600),			\
8314  X(cpy,   4600, ea4f0000),			\
8315  X(dec_sp,80dd, f1ad0d00),			\
8316  X(eor,   4040, ea800000),			\
8317  X(eors,  4040, ea900000),			\
8318  X(inc_sp,00dd, f10d0d00),			\
8319  X(ldmia, c800, e8900000),			\
8320  X(ldr,   6800, f8500000),			\
8321  X(ldrb,  7800, f8100000),			\
8322  X(ldrh,  8800, f8300000),			\
8323  X(ldrsb, 5600, f9100000),			\
8324  X(ldrsh, 5e00, f9300000),			\
8325  X(ldr_pc,4800, f85f0000),			\
8326  X(ldr_pc2,4800, f85f0000),			\
8327  X(ldr_sp,9800, f85d0000),			\
8328  X(lsl,   0000, fa00f000),			\
8329  X(lsls,  0000, fa10f000),			\
8330  X(lsr,   0800, fa20f000),			\
8331  X(lsrs,  0800, fa30f000),			\
8332  X(mov,   2000, ea4f0000),			\
8333  X(movs,  2000, ea5f0000),			\
8334  X(mul,   4340, fb00f000),                     \
8335  X(muls,  4340, ffffffff), /* no 32b muls */	\
8336  X(mvn,   43c0, ea6f0000),			\
8337  X(mvns,  43c0, ea7f0000),			\
8338  X(neg,   4240, f1c00000), /* rsb #0 */	\
8339  X(negs,  4240, f1d00000), /* rsbs #0 */	\
8340  X(orr,   4300, ea400000),			\
8341  X(orrs,  4300, ea500000),			\
8342  X(pop,   bc00, e8bd0000), /* ldmia sp!,... */	\
8343  X(push,  b400, e92d0000), /* stmdb sp!,... */	\
8344  X(rev,   ba00, fa90f080),			\
8345  X(rev16, ba40, fa90f090),			\
8346  X(revsh, bac0, fa90f0b0),			\
8347  X(ror,   41c0, fa60f000),			\
8348  X(rors,  41c0, fa70f000),			\
8349  X(sbc,   4180, eb600000),			\
8350  X(sbcs,  4180, eb700000),			\
8351  X(stmia, c000, e8800000),			\
8352  X(str,   6000, f8400000),			\
8353  X(strb,  7000, f8000000),			\
8354  X(strh,  8000, f8200000),			\
8355  X(str_sp,9000, f84d0000),			\
8356  X(sub,   1e00, eba00000),			\
8357  X(subs,  1e00, ebb00000),			\
8358  X(subi,  8000, f1a00000),			\
8359  X(subis, 8000, f1b00000),			\
8360  X(sxtb,  b240, fa4ff080),			\
8361  X(sxth,  b200, fa0ff080),			\
8362  X(tst,   4200, ea100f00),			\
8363  X(uxtb,  b2c0, fa5ff080),			\
8364  X(uxth,  b280, fa1ff080),			\
8365  X(nop,   bf00, f3af8000),			\
8366  X(yield, bf10, f3af8001),			\
8367  X(wfe,   bf20, f3af8002),			\
8368  X(wfi,   bf30, f3af8003),			\
8369  X(sev,   bf40, f3af9004), /* typo, 8004? */
8370
8371/* To catch errors in encoding functions, the codes are all offset by
8372   0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8373   as 16-bit instructions.  */
8374#define X(a,b,c) T_MNEM_##a
8375enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
8376#undef X
8377
8378#define X(a,b,c) 0x##b
8379static const unsigned short thumb_op16[] = { T16_32_TAB };
8380#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8381#undef X
8382
8383#define X(a,b,c) 0x##c
8384static const unsigned int thumb_op32[] = { T16_32_TAB };
8385#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8386#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8387#undef X
8388#undef T16_32_TAB
8389
8390/* Thumb instruction encoders, in alphabetical order.  */
8391
8392/* ADDW or SUBW.  */
8393static void
8394do_t_add_sub_w (void)
8395{
8396  int Rd, Rn;
8397
8398  Rd = inst.operands[0].reg;
8399  Rn = inst.operands[1].reg;
8400
8401  constraint (Rd == 15, _("PC not allowed as destination"));
8402  inst.instruction |= (Rn << 16) | (Rd << 8);
8403  inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8404}
8405
8406/* Parse an add or subtract instruction.  We get here with inst.instruction
8407   equalling any of THUMB_OPCODE_add, adds, sub, or subs.  */
8408
8409static void
8410do_t_add_sub (void)
8411{
8412  int Rd, Rs, Rn;
8413
8414  Rd = inst.operands[0].reg;
8415  Rs = (inst.operands[1].present
8416	? inst.operands[1].reg    /* Rd, Rs, foo */
8417	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
8418
8419  if (unified_syntax)
8420    {
8421      bfd_boolean flags;
8422      bfd_boolean narrow;
8423      int opcode;
8424
8425      flags = (inst.instruction == T_MNEM_adds
8426	       || inst.instruction == T_MNEM_subs);
8427      if (flags)
8428	narrow = (current_it_mask == 0);
8429      else
8430	narrow = (current_it_mask != 0);
8431      if (!inst.operands[2].isreg)
8432	{
8433	  int add;
8434
8435	  add = (inst.instruction == T_MNEM_add
8436		 || inst.instruction == T_MNEM_adds);
8437	  opcode = 0;
8438	  if (inst.size_req != 4)
8439	    {
8440	      /* Attempt to use a narrow opcode, with relaxation if
8441	         appropriate.  */
8442	      if (Rd == REG_SP && Rs == REG_SP && !flags)
8443		opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
8444	      else if (Rd <= 7 && Rs == REG_SP && add && !flags)
8445		opcode = T_MNEM_add_sp;
8446	      else if (Rd <= 7 && Rs == REG_PC && add && !flags)
8447		opcode = T_MNEM_add_pc;
8448	      else if (Rd <= 7 && Rs <= 7 && narrow)
8449		{
8450		  if (flags)
8451		    opcode = add ? T_MNEM_addis : T_MNEM_subis;
8452		  else
8453		    opcode = add ? T_MNEM_addi : T_MNEM_subi;
8454		}
8455	      if (opcode)
8456		{
8457		  inst.instruction = THUMB_OP16(opcode);
8458		  inst.instruction |= (Rd << 4) | Rs;
8459		  inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8460		  if (inst.size_req != 2)
8461		    inst.relax = opcode;
8462		}
8463	      else
8464		constraint (inst.size_req == 2, BAD_HIREG);
8465	    }
8466	  if (inst.size_req == 4
8467	      || (inst.size_req != 2 && !opcode))
8468	    {
8469	      if (Rd == REG_PC)
8470		{
8471		  constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
8472			     _("only SUBS PC, LR, #const allowed"));
8473		  constraint (inst.reloc.exp.X_op != O_constant,
8474			      _("expression too complex"));
8475		  constraint (inst.reloc.exp.X_add_number < 0
8476			      || inst.reloc.exp.X_add_number > 0xff,
8477			     _("immediate value out of range"));
8478		  inst.instruction = T2_SUBS_PC_LR
8479				     | inst.reloc.exp.X_add_number;
8480		  inst.reloc.type = BFD_RELOC_UNUSED;
8481		  return;
8482		}
8483	      else if (Rs == REG_PC)
8484		{
8485		  /* Always use addw/subw.  */
8486		  inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
8487		  inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8488		}
8489	      else
8490		{
8491		  inst.instruction = THUMB_OP32 (inst.instruction);
8492		  inst.instruction = (inst.instruction & 0xe1ffffff)
8493				     | 0x10000000;
8494		  if (flags)
8495		    inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8496		  else
8497		    inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
8498		}
8499	      inst.instruction |= Rd << 8;
8500	      inst.instruction |= Rs << 16;
8501	    }
8502	}
8503      else
8504	{
8505	  Rn = inst.operands[2].reg;
8506	  /* See if we can do this with a 16-bit instruction.  */
8507	  if (!inst.operands[2].shifted && inst.size_req != 4)
8508	    {
8509	      if (Rd > 7 || Rs > 7 || Rn > 7)
8510		narrow = FALSE;
8511
8512	      if (narrow)
8513		{
8514		  inst.instruction = ((inst.instruction == T_MNEM_adds
8515				       || inst.instruction == T_MNEM_add)
8516				      ? T_OPCODE_ADD_R3
8517				      : T_OPCODE_SUB_R3);
8518		  inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8519		  return;
8520		}
8521
8522	      if (inst.instruction == T_MNEM_add)
8523		{
8524		  if (Rd == Rs)
8525		    {
8526		      inst.instruction = T_OPCODE_ADD_HI;
8527		      inst.instruction |= (Rd & 8) << 4;
8528		      inst.instruction |= (Rd & 7);
8529		      inst.instruction |= Rn << 3;
8530		      return;
8531		    }
8532		  /* ... because addition is commutative! */
8533		  else if (Rd == Rn)
8534		    {
8535		      inst.instruction = T_OPCODE_ADD_HI;
8536		      inst.instruction |= (Rd & 8) << 4;
8537		      inst.instruction |= (Rd & 7);
8538		      inst.instruction |= Rs << 3;
8539		      return;
8540		    }
8541		}
8542	    }
8543	  /* If we get here, it can't be done in 16 bits.  */
8544	  constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
8545		      _("shift must be constant"));
8546	  inst.instruction = THUMB_OP32 (inst.instruction);
8547	  inst.instruction |= Rd << 8;
8548	  inst.instruction |= Rs << 16;
8549	  encode_thumb32_shifted_operand (2);
8550	}
8551    }
8552  else
8553    {
8554      constraint (inst.instruction == T_MNEM_adds
8555		  || inst.instruction == T_MNEM_subs,
8556		  BAD_THUMB32);
8557
8558      if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
8559	{
8560	  constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
8561		      || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
8562		      BAD_HIREG);
8563
8564	  inst.instruction = (inst.instruction == T_MNEM_add
8565			      ? 0x0000 : 0x8000);
8566	  inst.instruction |= (Rd << 4) | Rs;
8567	  inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8568	  return;
8569	}
8570
8571      Rn = inst.operands[2].reg;
8572      constraint (inst.operands[2].shifted, _("unshifted register required"));
8573
8574      /* We now have Rd, Rs, and Rn set to registers.  */
8575      if (Rd > 7 || Rs > 7 || Rn > 7)
8576	{
8577	  /* Can't do this for SUB.	 */
8578	  constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
8579	  inst.instruction = T_OPCODE_ADD_HI;
8580	  inst.instruction |= (Rd & 8) << 4;
8581	  inst.instruction |= (Rd & 7);
8582	  if (Rs == Rd)
8583	    inst.instruction |= Rn << 3;
8584	  else if (Rn == Rd)
8585	    inst.instruction |= Rs << 3;
8586	  else
8587	    constraint (1, _("dest must overlap one source register"));
8588	}
8589      else
8590	{
8591	  inst.instruction = (inst.instruction == T_MNEM_add
8592			      ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
8593	  inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8594	}
8595    }
8596}
8597
8598static void
8599do_t_adr (void)
8600{
8601  if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
8602    {
8603      /* Defer to section relaxation.  */
8604      inst.relax = inst.instruction;
8605      inst.instruction = THUMB_OP16 (inst.instruction);
8606      inst.instruction |= inst.operands[0].reg << 4;
8607    }
8608  else if (unified_syntax && inst.size_req != 2)
8609    {
8610      /* Generate a 32-bit opcode.  */
8611      inst.instruction = THUMB_OP32 (inst.instruction);
8612      inst.instruction |= inst.operands[0].reg << 8;
8613      inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
8614      inst.reloc.pc_rel = 1;
8615    }
8616  else
8617    {
8618      /* Generate a 16-bit opcode.  */
8619      inst.instruction = THUMB_OP16 (inst.instruction);
8620      inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8621      inst.reloc.exp.X_add_number -= 4; /* PC relative adjust.  */
8622      inst.reloc.pc_rel = 1;
8623
8624      inst.instruction |= inst.operands[0].reg << 4;
8625    }
8626}
8627
8628/* Arithmetic instructions for which there is just one 16-bit
8629   instruction encoding, and it allows only two low registers.
8630   For maximal compatibility with ARM syntax, we allow three register
8631   operands even when Thumb-32 instructions are not available, as long
8632   as the first two are identical.  For instance, both "sbc r0,r1" and
8633   "sbc r0,r0,r1" are allowed.  */
8634static void
8635do_t_arit3 (void)
8636{
8637  int Rd, Rs, Rn;
8638
8639  Rd = inst.operands[0].reg;
8640  Rs = (inst.operands[1].present
8641	? inst.operands[1].reg    /* Rd, Rs, foo */
8642	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
8643  Rn = inst.operands[2].reg;
8644
8645  if (unified_syntax)
8646    {
8647      if (!inst.operands[2].isreg)
8648	{
8649	  /* For an immediate, we always generate a 32-bit opcode;
8650	     section relaxation will shrink it later if possible.  */
8651	  inst.instruction = THUMB_OP32 (inst.instruction);
8652	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
8653	  inst.instruction |= Rd << 8;
8654	  inst.instruction |= Rs << 16;
8655	  inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8656	}
8657      else
8658	{
8659	  bfd_boolean narrow;
8660
8661	  /* See if we can do this with a 16-bit instruction.  */
8662	  if (THUMB_SETS_FLAGS (inst.instruction))
8663	    narrow = current_it_mask == 0;
8664	  else
8665	    narrow = current_it_mask != 0;
8666
8667	  if (Rd > 7 || Rn > 7 || Rs > 7)
8668	    narrow = FALSE;
8669	  if (inst.operands[2].shifted)
8670	    narrow = FALSE;
8671	  if (inst.size_req == 4)
8672	    narrow = FALSE;
8673
8674	  if (narrow
8675	      && Rd == Rs)
8676	    {
8677	      inst.instruction = THUMB_OP16 (inst.instruction);
8678	      inst.instruction |= Rd;
8679	      inst.instruction |= Rn << 3;
8680	      return;
8681	    }
8682
8683	  /* If we get here, it can't be done in 16 bits.  */
8684	  constraint (inst.operands[2].shifted
8685		      && inst.operands[2].immisreg,
8686		      _("shift must be constant"));
8687	  inst.instruction = THUMB_OP32 (inst.instruction);
8688	  inst.instruction |= Rd << 8;
8689	  inst.instruction |= Rs << 16;
8690	  encode_thumb32_shifted_operand (2);
8691	}
8692    }
8693  else
8694    {
8695      /* On its face this is a lie - the instruction does set the
8696	 flags.  However, the only supported mnemonic in this mode
8697	 says it doesn't.  */
8698      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
8699
8700      constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
8701		  _("unshifted register required"));
8702      constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8703      constraint (Rd != Rs,
8704		  _("dest and source1 must be the same register"));
8705
8706      inst.instruction = THUMB_OP16 (inst.instruction);
8707      inst.instruction |= Rd;
8708      inst.instruction |= Rn << 3;
8709    }
8710}
8711
8712/* Similarly, but for instructions where the arithmetic operation is
8713   commutative, so we can allow either of them to be different from
8714   the destination operand in a 16-bit instruction.  For instance, all
8715   three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8716   accepted.  */
8717static void
8718do_t_arit3c (void)
8719{
8720  int Rd, Rs, Rn;
8721
8722  Rd = inst.operands[0].reg;
8723  Rs = (inst.operands[1].present
8724	? inst.operands[1].reg    /* Rd, Rs, foo */
8725	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
8726  Rn = inst.operands[2].reg;
8727
8728  if (unified_syntax)
8729    {
8730      if (!inst.operands[2].isreg)
8731	{
8732	  /* For an immediate, we always generate a 32-bit opcode;
8733	     section relaxation will shrink it later if possible.  */
8734	  inst.instruction = THUMB_OP32 (inst.instruction);
8735	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
8736	  inst.instruction |= Rd << 8;
8737	  inst.instruction |= Rs << 16;
8738	  inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8739	}
8740      else
8741	{
8742	  bfd_boolean narrow;
8743
8744	  /* See if we can do this with a 16-bit instruction.  */
8745	  if (THUMB_SETS_FLAGS (inst.instruction))
8746	    narrow = current_it_mask == 0;
8747	  else
8748	    narrow = current_it_mask != 0;
8749
8750	  if (Rd > 7 || Rn > 7 || Rs > 7)
8751	    narrow = FALSE;
8752	  if (inst.operands[2].shifted)
8753	    narrow = FALSE;
8754	  if (inst.size_req == 4)
8755	    narrow = FALSE;
8756
8757	  if (narrow)
8758	    {
8759	      if (Rd == Rs)
8760		{
8761		  inst.instruction = THUMB_OP16 (inst.instruction);
8762		  inst.instruction |= Rd;
8763		  inst.instruction |= Rn << 3;
8764		  return;
8765		}
8766	      if (Rd == Rn)
8767		{
8768		  inst.instruction = THUMB_OP16 (inst.instruction);
8769		  inst.instruction |= Rd;
8770		  inst.instruction |= Rs << 3;
8771		  return;
8772		}
8773	    }
8774
8775	  /* If we get here, it can't be done in 16 bits.  */
8776	  constraint (inst.operands[2].shifted
8777		      && inst.operands[2].immisreg,
8778		      _("shift must be constant"));
8779	  inst.instruction = THUMB_OP32 (inst.instruction);
8780	  inst.instruction |= Rd << 8;
8781	  inst.instruction |= Rs << 16;
8782	  encode_thumb32_shifted_operand (2);
8783	}
8784    }
8785  else
8786    {
8787      /* On its face this is a lie - the instruction does set the
8788	 flags.  However, the only supported mnemonic in this mode
8789	 says it doesn't.  */
8790      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
8791
8792      constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
8793		  _("unshifted register required"));
8794      constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8795
8796      inst.instruction = THUMB_OP16 (inst.instruction);
8797      inst.instruction |= Rd;
8798
8799      if (Rd == Rs)
8800	inst.instruction |= Rn << 3;
8801      else if (Rd == Rn)
8802	inst.instruction |= Rs << 3;
8803      else
8804	constraint (1, _("dest must overlap one source register"));
8805    }
8806}
8807
8808static void
8809do_t_barrier (void)
8810{
8811  if (inst.operands[0].present)
8812    {
8813      constraint ((inst.instruction & 0xf0) != 0x40
8814		  && inst.operands[0].imm != 0xf,
8815		  "bad barrier type");
8816      inst.instruction |= inst.operands[0].imm;
8817    }
8818  else
8819    inst.instruction |= 0xf;
8820}
8821
8822static void
8823do_t_bfc (void)
8824{
8825  unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8826  constraint (msb > 32, _("bit-field extends past end of register"));
8827  /* The instruction encoding stores the LSB and MSB,
8828     not the LSB and width.  */
8829  inst.instruction |= inst.operands[0].reg << 8;
8830  inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
8831  inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
8832  inst.instruction |= msb - 1;
8833}
8834
8835static void
8836do_t_bfi (void)
8837{
8838  unsigned int msb;
8839
8840  /* #0 in second position is alternative syntax for bfc, which is
8841     the same instruction but with REG_PC in the Rm field.  */
8842  if (!inst.operands[1].isreg)
8843    inst.operands[1].reg = REG_PC;
8844
8845  msb = inst.operands[2].imm + inst.operands[3].imm;
8846  constraint (msb > 32, _("bit-field extends past end of register"));
8847  /* The instruction encoding stores the LSB and MSB,
8848     not the LSB and width.  */
8849  inst.instruction |= inst.operands[0].reg << 8;
8850  inst.instruction |= inst.operands[1].reg << 16;
8851  inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8852  inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8853  inst.instruction |= msb - 1;
8854}
8855
8856static void
8857do_t_bfx (void)
8858{
8859  constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8860	      _("bit-field extends past end of register"));
8861  inst.instruction |= inst.operands[0].reg << 8;
8862  inst.instruction |= inst.operands[1].reg << 16;
8863  inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8864  inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8865  inst.instruction |= inst.operands[3].imm - 1;
8866}
8867
8868/* ARM V5 Thumb BLX (argument parse)
8869	BLX <target_addr>	which is BLX(1)
8870	BLX <Rm>		which is BLX(2)
8871   Unfortunately, there are two different opcodes for this mnemonic.
8872   So, the insns[].value is not used, and the code here zaps values
8873	into inst.instruction.
8874
8875   ??? How to take advantage of the additional two bits of displacement
8876   available in Thumb32 mode?  Need new relocation?  */
8877
8878static void
8879do_t_blx (void)
8880{
8881  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8882  if (inst.operands[0].isreg)
8883    /* We have a register, so this is BLX(2).  */
8884    inst.instruction |= inst.operands[0].reg << 3;
8885  else
8886    {
8887      /* No register.  This must be BLX(1).  */
8888      inst.instruction = 0xf000e800;
8889#ifdef OBJ_ELF
8890      if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8891	inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
8892      else
8893#endif
8894	inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
8895      inst.reloc.pc_rel = 1;
8896    }
8897}
8898
8899static void
8900do_t_branch (void)
8901{
8902  int opcode;
8903  int cond;
8904
8905  if (current_it_mask)
8906    {
8907      /* Conditional branches inside IT blocks are encoded as unconditional
8908         branches.  */
8909      cond = COND_ALWAYS;
8910      /* A branch must be the last instruction in an IT block.  */
8911      constraint (current_it_mask != 0x10, BAD_BRANCH);
8912    }
8913  else
8914    cond = inst.cond;
8915
8916  if (cond != COND_ALWAYS)
8917    opcode = T_MNEM_bcond;
8918  else
8919    opcode = inst.instruction;
8920
8921  if (unified_syntax && inst.size_req == 4)
8922    {
8923      inst.instruction = THUMB_OP32(opcode);
8924      if (cond == COND_ALWAYS)
8925	inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
8926      else
8927	{
8928	  assert (cond != 0xF);
8929	  inst.instruction |= cond << 22;
8930	  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
8931	}
8932    }
8933  else
8934    {
8935      inst.instruction = THUMB_OP16(opcode);
8936      if (cond == COND_ALWAYS)
8937	inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
8938      else
8939	{
8940	  inst.instruction |= cond << 8;
8941	  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
8942	}
8943      /* Allow section relaxation.  */
8944      if (unified_syntax && inst.size_req != 2)
8945	inst.relax = opcode;
8946    }
8947
8948  inst.reloc.pc_rel = 1;
8949}
8950
8951static void
8952do_t_bkpt (void)
8953{
8954  constraint (inst.cond != COND_ALWAYS,
8955	      _("instruction is always unconditional"));
8956  if (inst.operands[0].present)
8957    {
8958      constraint (inst.operands[0].imm > 255,
8959		  _("immediate value out of range"));
8960      inst.instruction |= inst.operands[0].imm;
8961    }
8962}
8963
8964static void
8965do_t_branch23 (void)
8966{
8967  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8968  inst.reloc.type   = BFD_RELOC_THUMB_PCREL_BRANCH23;
8969  inst.reloc.pc_rel = 1;
8970
8971  /* If the destination of the branch is a defined symbol which does not have
8972     the THUMB_FUNC attribute, then we must be calling a function which has
8973     the (interfacearm) attribute.  We look for the Thumb entry point to that
8974     function and change the branch to refer to that function instead.	*/
8975  if (	 inst.reloc.exp.X_op == O_symbol
8976      && inst.reloc.exp.X_add_symbol != NULL
8977      && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
8978      && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
8979    inst.reloc.exp.X_add_symbol =
8980      find_real_start (inst.reloc.exp.X_add_symbol);
8981}
8982
8983static void
8984do_t_bx (void)
8985{
8986  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8987  inst.instruction |= inst.operands[0].reg << 3;
8988  /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC.	 The reloc
8989     should cause the alignment to be checked once it is known.	 This is
8990     because BX PC only works if the instruction is word aligned.  */
8991}
8992
8993static void
8994do_t_bxj (void)
8995{
8996  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8997  if (inst.operands[0].reg == REG_PC)
8998    as_tsktsk (_("use of r15 in bxj is not really useful"));
8999
9000  inst.instruction |= inst.operands[0].reg << 16;
9001}
9002
9003static void
9004do_t_clz (void)
9005{
9006  inst.instruction |= inst.operands[0].reg << 8;
9007  inst.instruction |= inst.operands[1].reg << 16;
9008  inst.instruction |= inst.operands[1].reg;
9009}
9010
9011static void
9012do_t_cps (void)
9013{
9014  constraint (current_it_mask, BAD_NOT_IT);
9015  inst.instruction |= inst.operands[0].imm;
9016}
9017
9018static void
9019do_t_cpsi (void)
9020{
9021  constraint (current_it_mask, BAD_NOT_IT);
9022  if (unified_syntax
9023      && (inst.operands[1].present || inst.size_req == 4)
9024      && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
9025    {
9026      unsigned int imod = (inst.instruction & 0x0030) >> 4;
9027      inst.instruction = 0xf3af8000;
9028      inst.instruction |= imod << 9;
9029      inst.instruction |= inst.operands[0].imm << 5;
9030      if (inst.operands[1].present)
9031	inst.instruction |= 0x100 | inst.operands[1].imm;
9032    }
9033  else
9034    {
9035      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
9036		  && (inst.operands[0].imm & 4),
9037		  _("selected processor does not support 'A' form "
9038		    "of this instruction"));
9039      constraint (inst.operands[1].present || inst.size_req == 4,
9040		  _("Thumb does not support the 2-argument "
9041		    "form of this instruction"));
9042      inst.instruction |= inst.operands[0].imm;
9043    }
9044}
9045
9046/* THUMB CPY instruction (argument parse).  */
9047
9048static void
9049do_t_cpy (void)
9050{
9051  if (inst.size_req == 4)
9052    {
9053      inst.instruction = THUMB_OP32 (T_MNEM_mov);
9054      inst.instruction |= inst.operands[0].reg << 8;
9055      inst.instruction |= inst.operands[1].reg;
9056    }
9057  else
9058    {
9059      inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9060      inst.instruction |= (inst.operands[0].reg & 0x7);
9061      inst.instruction |= inst.operands[1].reg << 3;
9062    }
9063}
9064
9065static void
9066do_t_cbz (void)
9067{
9068  constraint (current_it_mask, BAD_NOT_IT);
9069  constraint (inst.operands[0].reg > 7, BAD_HIREG);
9070  inst.instruction |= inst.operands[0].reg;
9071  inst.reloc.pc_rel = 1;
9072  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
9073}
9074
9075static void
9076do_t_dbg (void)
9077{
9078  inst.instruction |= inst.operands[0].imm;
9079}
9080
9081static void
9082do_t_div (void)
9083{
9084  if (!inst.operands[1].present)
9085    inst.operands[1].reg = inst.operands[0].reg;
9086  inst.instruction |= inst.operands[0].reg << 8;
9087  inst.instruction |= inst.operands[1].reg << 16;
9088  inst.instruction |= inst.operands[2].reg;
9089}
9090
9091static void
9092do_t_hint (void)
9093{
9094  if (unified_syntax && inst.size_req == 4)
9095    inst.instruction = THUMB_OP32 (inst.instruction);
9096  else
9097    inst.instruction = THUMB_OP16 (inst.instruction);
9098}
9099
9100static void
9101do_t_it (void)
9102{
9103  unsigned int cond = inst.operands[0].imm;
9104
9105  constraint (current_it_mask, BAD_NOT_IT);
9106  current_it_mask = (inst.instruction & 0xf) | 0x10;
9107  current_cc = cond;
9108
9109  /* If the condition is a negative condition, invert the mask.  */
9110  if ((cond & 0x1) == 0x0)
9111    {
9112      unsigned int mask = inst.instruction & 0x000f;
9113
9114      if ((mask & 0x7) == 0)
9115	/* no conversion needed */;
9116      else if ((mask & 0x3) == 0)
9117	mask ^= 0x8;
9118      else if ((mask & 0x1) == 0)
9119	mask ^= 0xC;
9120      else
9121	mask ^= 0xE;
9122
9123      inst.instruction &= 0xfff0;
9124      inst.instruction |= mask;
9125    }
9126
9127  inst.instruction |= cond << 4;
9128}
9129
9130/* Helper function used for both push/pop and ldm/stm.  */
9131static void
9132encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
9133{
9134  bfd_boolean load;
9135
9136  load = (inst.instruction & (1 << 20)) != 0;
9137
9138  if (mask & (1 << 13))
9139    inst.error =  _("SP not allowed in register list");
9140  if (load)
9141    {
9142      if (mask & (1 << 14)
9143	  && mask & (1 << 15))
9144	inst.error = _("LR and PC should not both be in register list");
9145
9146      if ((mask & (1 << base)) != 0
9147	  && writeback)
9148	as_warn (_("base register should not be in register list "
9149		   "when written back"));
9150    }
9151  else
9152    {
9153      if (mask & (1 << 15))
9154	inst.error = _("PC not allowed in register list");
9155
9156      if (mask & (1 << base))
9157	as_warn (_("value stored for r%d is UNPREDICTABLE"), base);
9158    }
9159
9160  if ((mask & (mask - 1)) == 0)
9161    {
9162      /* Single register transfers implemented as str/ldr.  */
9163      if (writeback)
9164	{
9165	  if (inst.instruction & (1 << 23))
9166	    inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
9167	  else
9168	    inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
9169	}
9170      else
9171	{
9172	  if (inst.instruction & (1 << 23))
9173	    inst.instruction = 0x00800000; /* ia -> [base] */
9174	  else
9175	    inst.instruction = 0x00000c04; /* db -> [base, #-4] */
9176	}
9177
9178      inst.instruction |= 0xf8400000;
9179      if (load)
9180	inst.instruction |= 0x00100000;
9181
9182      mask = ffs(mask) - 1;
9183      mask <<= 12;
9184    }
9185  else if (writeback)
9186    inst.instruction |= WRITE_BACK;
9187
9188  inst.instruction |= mask;
9189  inst.instruction |= base << 16;
9190}
9191
9192static void
9193do_t_ldmstm (void)
9194{
9195  /* This really doesn't seem worth it.  */
9196  constraint (inst.reloc.type != BFD_RELOC_UNUSED,
9197	      _("expression too complex"));
9198  constraint (inst.operands[1].writeback,
9199	      _("Thumb load/store multiple does not support {reglist}^"));
9200
9201  if (unified_syntax)
9202    {
9203      bfd_boolean narrow;
9204      unsigned mask;
9205
9206      narrow = FALSE;
9207      /* See if we can use a 16-bit instruction.  */
9208      if (inst.instruction < 0xffff /* not ldmdb/stmdb */
9209	  && inst.size_req != 4
9210	  && !(inst.operands[1].imm & ~0xff))
9211	{
9212	  mask = 1 << inst.operands[0].reg;
9213
9214	  if (inst.operands[0].reg <= 7
9215	      && (inst.instruction == T_MNEM_stmia
9216		  ? inst.operands[0].writeback
9217		  : (inst.operands[0].writeback
9218		     == !(inst.operands[1].imm & mask))))
9219	    {
9220	      if (inst.instruction == T_MNEM_stmia
9221		  && (inst.operands[1].imm & mask)
9222		  && (inst.operands[1].imm & (mask - 1)))
9223		as_warn (_("value stored for r%d is UNPREDICTABLE"),
9224			 inst.operands[0].reg);
9225
9226	      inst.instruction = THUMB_OP16 (inst.instruction);
9227	      inst.instruction |= inst.operands[0].reg << 8;
9228	      inst.instruction |= inst.operands[1].imm;
9229	      narrow = TRUE;
9230	    }
9231	  else if (inst.operands[0] .reg == REG_SP
9232		   && inst.operands[0].writeback)
9233	    {
9234	      inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia
9235					     ? T_MNEM_push : T_MNEM_pop);
9236	      inst.instruction |= inst.operands[1].imm;
9237	      narrow = TRUE;
9238	    }
9239	}
9240
9241      if (!narrow)
9242	{
9243	  if (inst.instruction < 0xffff)
9244	    inst.instruction = THUMB_OP32 (inst.instruction);
9245
9246	  encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm,
9247			       inst.operands[0].writeback);
9248	}
9249    }
9250  else
9251    {
9252      constraint (inst.operands[0].reg > 7
9253		  || (inst.operands[1].imm & ~0xff), BAD_HIREG);
9254      constraint (inst.instruction != T_MNEM_ldmia
9255		  && inst.instruction != T_MNEM_stmia,
9256		  _("Thumb-2 instruction only valid in unified syntax"));
9257      if (inst.instruction == T_MNEM_stmia)
9258	{
9259	  if (!inst.operands[0].writeback)
9260	    as_warn (_("this instruction will write back the base register"));
9261	  if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
9262	      && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
9263	    as_warn (_("value stored for r%d is UNPREDICTABLE"),
9264		     inst.operands[0].reg);
9265	}
9266      else
9267	{
9268	  if (!inst.operands[0].writeback
9269	      && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
9270	    as_warn (_("this instruction will write back the base register"));
9271	  else if (inst.operands[0].writeback
9272		   && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
9273	    as_warn (_("this instruction will not write back the base register"));
9274	}
9275
9276      inst.instruction = THUMB_OP16 (inst.instruction);
9277      inst.instruction |= inst.operands[0].reg << 8;
9278      inst.instruction |= inst.operands[1].imm;
9279    }
9280}
9281
9282static void
9283do_t_ldrex (void)
9284{
9285  constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9286	      || inst.operands[1].postind || inst.operands[1].writeback
9287	      || inst.operands[1].immisreg || inst.operands[1].shifted
9288	      || inst.operands[1].negative,
9289	      BAD_ADDR_MODE);
9290
9291  inst.instruction |= inst.operands[0].reg << 12;
9292  inst.instruction |= inst.operands[1].reg << 16;
9293  inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
9294}
9295
9296static void
9297do_t_ldrexd (void)
9298{
9299  if (!inst.operands[1].present)
9300    {
9301      constraint (inst.operands[0].reg == REG_LR,
9302		  _("r14 not allowed as first register "
9303		    "when second register is omitted"));
9304      inst.operands[1].reg = inst.operands[0].reg + 1;
9305    }
9306  constraint (inst.operands[0].reg == inst.operands[1].reg,
9307	      BAD_OVERLAP);
9308
9309  inst.instruction |= inst.operands[0].reg << 12;
9310  inst.instruction |= inst.operands[1].reg << 8;
9311  inst.instruction |= inst.operands[2].reg << 16;
9312}
9313
9314static void
9315do_t_ldst (void)
9316{
9317  unsigned long opcode;
9318  int Rn;
9319
9320  opcode = inst.instruction;
9321  if (unified_syntax)
9322    {
9323      if (!inst.operands[1].isreg)
9324	{
9325	  if (opcode <= 0xffff)
9326	    inst.instruction = THUMB_OP32 (opcode);
9327	  if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9328	    return;
9329	}
9330      if (inst.operands[1].isreg
9331	  && !inst.operands[1].writeback
9332	  && !inst.operands[1].shifted && !inst.operands[1].postind
9333	  && !inst.operands[1].negative && inst.operands[0].reg <= 7
9334	  && opcode <= 0xffff
9335	  && inst.size_req != 4)
9336	{
9337	  /* Insn may have a 16-bit form.  */
9338	  Rn = inst.operands[1].reg;
9339	  if (inst.operands[1].immisreg)
9340	    {
9341	      inst.instruction = THUMB_OP16 (opcode);
9342	      /* [Rn, Ri] */
9343	      if (Rn <= 7 && inst.operands[1].imm <= 7)
9344		goto op16;
9345	    }
9346	  else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
9347		    && opcode != T_MNEM_ldrsb)
9348		   || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
9349		   || (Rn == REG_SP && opcode == T_MNEM_str))
9350	    {
9351	      /* [Rn, #const] */
9352	      if (Rn > 7)
9353		{
9354		  if (Rn == REG_PC)
9355		    {
9356		      if (inst.reloc.pc_rel)
9357			opcode = T_MNEM_ldr_pc2;
9358		      else
9359			opcode = T_MNEM_ldr_pc;
9360		    }
9361		  else
9362		    {
9363		      if (opcode == T_MNEM_ldr)
9364			opcode = T_MNEM_ldr_sp;
9365		      else
9366			opcode = T_MNEM_str_sp;
9367		    }
9368		  inst.instruction = inst.operands[0].reg << 8;
9369		}
9370	      else
9371		{
9372		  inst.instruction = inst.operands[0].reg;
9373		  inst.instruction |= inst.operands[1].reg << 3;
9374		}
9375	      inst.instruction |= THUMB_OP16 (opcode);
9376	      if (inst.size_req == 2)
9377		inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9378	      else
9379		inst.relax = opcode;
9380	      return;
9381	    }
9382	}
9383      /* Definitely a 32-bit variant.  */
9384      inst.instruction = THUMB_OP32 (opcode);
9385      inst.instruction |= inst.operands[0].reg << 12;
9386      encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
9387      return;
9388    }
9389
9390  constraint (inst.operands[0].reg > 7, BAD_HIREG);
9391
9392  if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
9393    {
9394      /* Only [Rn,Rm] is acceptable.  */
9395      constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
9396      constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
9397		  || inst.operands[1].postind || inst.operands[1].shifted
9398		  || inst.operands[1].negative,
9399		  _("Thumb does not support this addressing mode"));
9400      inst.instruction = THUMB_OP16 (inst.instruction);
9401      goto op16;
9402    }
9403
9404  inst.instruction = THUMB_OP16 (inst.instruction);
9405  if (!inst.operands[1].isreg)
9406    if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9407      return;
9408
9409  constraint (!inst.operands[1].preind
9410	      || inst.operands[1].shifted
9411	      || inst.operands[1].writeback,
9412	      _("Thumb does not support this addressing mode"));
9413  if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
9414    {
9415      constraint (inst.instruction & 0x0600,
9416		  _("byte or halfword not valid for base register"));
9417      constraint (inst.operands[1].reg == REG_PC
9418		  && !(inst.instruction & THUMB_LOAD_BIT),
9419		  _("r15 based store not allowed"));
9420      constraint (inst.operands[1].immisreg,
9421		  _("invalid base register for register offset"));
9422
9423      if (inst.operands[1].reg == REG_PC)
9424	inst.instruction = T_OPCODE_LDR_PC;
9425      else if (inst.instruction & THUMB_LOAD_BIT)
9426	inst.instruction = T_OPCODE_LDR_SP;
9427      else
9428	inst.instruction = T_OPCODE_STR_SP;
9429
9430      inst.instruction |= inst.operands[0].reg << 8;
9431      inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9432      return;
9433    }
9434
9435  constraint (inst.operands[1].reg > 7, BAD_HIREG);
9436  if (!inst.operands[1].immisreg)
9437    {
9438      /* Immediate offset.  */
9439      inst.instruction |= inst.operands[0].reg;
9440      inst.instruction |= inst.operands[1].reg << 3;
9441      inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9442      return;
9443    }
9444
9445  /* Register offset.  */
9446  constraint (inst.operands[1].imm > 7, BAD_HIREG);
9447  constraint (inst.operands[1].negative,
9448	      _("Thumb does not support this addressing mode"));
9449
9450 op16:
9451  switch (inst.instruction)
9452    {
9453    case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
9454    case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
9455    case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
9456    case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
9457    case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
9458    case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
9459    case 0x5600 /* ldrsb */:
9460    case 0x5e00 /* ldrsh */: break;
9461    default: abort ();
9462    }
9463
9464  inst.instruction |= inst.operands[0].reg;
9465  inst.instruction |= inst.operands[1].reg << 3;
9466  inst.instruction |= inst.operands[1].imm << 6;
9467}
9468
9469static void
9470do_t_ldstd (void)
9471{
9472  if (!inst.operands[1].present)
9473    {
9474      inst.operands[1].reg = inst.operands[0].reg + 1;
9475      constraint (inst.operands[0].reg == REG_LR,
9476		  _("r14 not allowed here"));
9477    }
9478  inst.instruction |= inst.operands[0].reg << 12;
9479  inst.instruction |= inst.operands[1].reg << 8;
9480  encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
9481
9482}
9483
9484static void
9485do_t_ldstt (void)
9486{
9487  inst.instruction |= inst.operands[0].reg << 12;
9488  encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
9489}
9490
9491static void
9492do_t_mla (void)
9493{
9494  inst.instruction |= inst.operands[0].reg << 8;
9495  inst.instruction |= inst.operands[1].reg << 16;
9496  inst.instruction |= inst.operands[2].reg;
9497  inst.instruction |= inst.operands[3].reg << 12;
9498}
9499
9500static void
9501do_t_mlal (void)
9502{
9503  inst.instruction |= inst.operands[0].reg << 12;
9504  inst.instruction |= inst.operands[1].reg << 8;
9505  inst.instruction |= inst.operands[2].reg << 16;
9506  inst.instruction |= inst.operands[3].reg;
9507}
9508
9509static void
9510do_t_mov_cmp (void)
9511{
9512  if (unified_syntax)
9513    {
9514      int r0off = (inst.instruction == T_MNEM_mov
9515		   || inst.instruction == T_MNEM_movs) ? 8 : 16;
9516      unsigned long opcode;
9517      bfd_boolean narrow;
9518      bfd_boolean low_regs;
9519
9520      low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
9521      opcode = inst.instruction;
9522      if (current_it_mask)
9523	narrow = opcode != T_MNEM_movs;
9524      else
9525	narrow = opcode != T_MNEM_movs || low_regs;
9526      if (inst.size_req == 4
9527	  || inst.operands[1].shifted)
9528	narrow = FALSE;
9529
9530      /* MOVS PC, LR is encoded as SUBS PC, LR, #0.  */
9531      if (opcode == T_MNEM_movs && inst.operands[1].isreg
9532	  && !inst.operands[1].shifted
9533	  && inst.operands[0].reg == REG_PC
9534	  && inst.operands[1].reg == REG_LR)
9535	{
9536	  inst.instruction = T2_SUBS_PC_LR;
9537	  return;
9538	}
9539
9540      if (!inst.operands[1].isreg)
9541	{
9542	  /* Immediate operand.  */
9543	  if (current_it_mask == 0 && opcode == T_MNEM_mov)
9544	    narrow = 0;
9545	  if (low_regs && narrow)
9546	    {
9547	      inst.instruction = THUMB_OP16 (opcode);
9548	      inst.instruction |= inst.operands[0].reg << 8;
9549	      if (inst.size_req == 2)
9550		inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
9551	      else
9552		inst.relax = opcode;
9553	    }
9554	  else
9555	    {
9556	      inst.instruction = THUMB_OP32 (inst.instruction);
9557	      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9558	      inst.instruction |= inst.operands[0].reg << r0off;
9559	      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9560	    }
9561	}
9562      else if (inst.operands[1].shifted && inst.operands[1].immisreg
9563	       && (inst.instruction == T_MNEM_mov
9564		   || inst.instruction == T_MNEM_movs))
9565	{
9566	  /* Register shifts are encoded as separate shift instructions.  */
9567	  bfd_boolean flags = (inst.instruction == T_MNEM_movs);
9568
9569	  if (current_it_mask)
9570	    narrow = !flags;
9571	  else
9572	    narrow = flags;
9573
9574	  if (inst.size_req == 4)
9575	    narrow = FALSE;
9576
9577	  if (!low_regs || inst.operands[1].imm > 7)
9578	    narrow = FALSE;
9579
9580	  if (inst.operands[0].reg != inst.operands[1].reg)
9581	    narrow = FALSE;
9582
9583	  switch (inst.operands[1].shift_kind)
9584	    {
9585	    case SHIFT_LSL:
9586	      opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
9587	      break;
9588	    case SHIFT_ASR:
9589	      opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
9590	      break;
9591	    case SHIFT_LSR:
9592	      opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
9593	      break;
9594	    case SHIFT_ROR:
9595	      opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
9596	      break;
9597	    default:
9598	      abort();
9599	    }
9600
9601	  inst.instruction = opcode;
9602	  if (narrow)
9603	    {
9604	      inst.instruction |= inst.operands[0].reg;
9605	      inst.instruction |= inst.operands[1].imm << 3;
9606	    }
9607	  else
9608	    {
9609	      if (flags)
9610		inst.instruction |= CONDS_BIT;
9611
9612	      inst.instruction |= inst.operands[0].reg << 8;
9613	      inst.instruction |= inst.operands[1].reg << 16;
9614	      inst.instruction |= inst.operands[1].imm;
9615	    }
9616	}
9617      else if (!narrow)
9618	{
9619	  /* Some mov with immediate shift have narrow variants.
9620	     Register shifts are handled above.  */
9621	  if (low_regs && inst.operands[1].shifted
9622	      && (inst.instruction == T_MNEM_mov
9623		  || inst.instruction == T_MNEM_movs))
9624	    {
9625	      if (current_it_mask)
9626		narrow = (inst.instruction == T_MNEM_mov);
9627	      else
9628		narrow = (inst.instruction == T_MNEM_movs);
9629	    }
9630
9631	  if (narrow)
9632	    {
9633	      switch (inst.operands[1].shift_kind)
9634		{
9635		case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
9636		case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
9637		case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
9638		default: narrow = FALSE; break;
9639		}
9640	    }
9641
9642	  if (narrow)
9643	    {
9644	      inst.instruction |= inst.operands[0].reg;
9645	      inst.instruction |= inst.operands[1].reg << 3;
9646	      inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
9647	    }
9648	  else
9649	    {
9650	      inst.instruction = THUMB_OP32 (inst.instruction);
9651	      inst.instruction |= inst.operands[0].reg << r0off;
9652	      encode_thumb32_shifted_operand (1);
9653	    }
9654	}
9655      else
9656	switch (inst.instruction)
9657	  {
9658	  case T_MNEM_mov:
9659	    inst.instruction = T_OPCODE_MOV_HR;
9660	    inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9661	    inst.instruction |= (inst.operands[0].reg & 0x7);
9662	    inst.instruction |= inst.operands[1].reg << 3;
9663	    break;
9664
9665	  case T_MNEM_movs:
9666	    /* We know we have low registers at this point.
9667	       Generate ADD Rd, Rs, #0.  */
9668	    inst.instruction = T_OPCODE_ADD_I3;
9669	    inst.instruction |= inst.operands[0].reg;
9670	    inst.instruction |= inst.operands[1].reg << 3;
9671	    break;
9672
9673	  case T_MNEM_cmp:
9674	    if (low_regs)
9675	      {
9676		inst.instruction = T_OPCODE_CMP_LR;
9677		inst.instruction |= inst.operands[0].reg;
9678		inst.instruction |= inst.operands[1].reg << 3;
9679	      }
9680	    else
9681	      {
9682		inst.instruction = T_OPCODE_CMP_HR;
9683		inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9684		inst.instruction |= (inst.operands[0].reg & 0x7);
9685		inst.instruction |= inst.operands[1].reg << 3;
9686	      }
9687	    break;
9688	  }
9689      return;
9690    }
9691
9692  inst.instruction = THUMB_OP16 (inst.instruction);
9693  if (inst.operands[1].isreg)
9694    {
9695      if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
9696	{
9697	  /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9698	     since a MOV instruction produces unpredictable results.  */
9699	  if (inst.instruction == T_OPCODE_MOV_I8)
9700	    inst.instruction = T_OPCODE_ADD_I3;
9701	  else
9702	    inst.instruction = T_OPCODE_CMP_LR;
9703
9704	  inst.instruction |= inst.operands[0].reg;
9705	  inst.instruction |= inst.operands[1].reg << 3;
9706	}
9707      else
9708	{
9709	  if (inst.instruction == T_OPCODE_MOV_I8)
9710	    inst.instruction = T_OPCODE_MOV_HR;
9711	  else
9712	    inst.instruction = T_OPCODE_CMP_HR;
9713	  do_t_cpy ();
9714	}
9715    }
9716  else
9717    {
9718      constraint (inst.operands[0].reg > 7,
9719		  _("only lo regs allowed with immediate"));
9720      inst.instruction |= inst.operands[0].reg << 8;
9721      inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
9722    }
9723}
9724
9725static void
9726do_t_mov16 (void)
9727{
9728  bfd_vma imm;
9729  bfd_boolean top;
9730
9731  top = (inst.instruction & 0x00800000) != 0;
9732  if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
9733    {
9734      constraint (top, _(":lower16: not allowed this instruction"));
9735      inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
9736    }
9737  else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
9738    {
9739      constraint (!top, _(":upper16: not allowed this instruction"));
9740      inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
9741    }
9742
9743  inst.instruction |= inst.operands[0].reg << 8;
9744  if (inst.reloc.type == BFD_RELOC_UNUSED)
9745    {
9746      imm = inst.reloc.exp.X_add_number;
9747      inst.instruction |= (imm & 0xf000) << 4;
9748      inst.instruction |= (imm & 0x0800) << 15;
9749      inst.instruction |= (imm & 0x0700) << 4;
9750      inst.instruction |= (imm & 0x00ff);
9751    }
9752}
9753
9754static void
9755do_t_mvn_tst (void)
9756{
9757  if (unified_syntax)
9758    {
9759      int r0off = (inst.instruction == T_MNEM_mvn
9760		   || inst.instruction == T_MNEM_mvns) ? 8 : 16;
9761      bfd_boolean narrow;
9762
9763      if (inst.size_req == 4
9764	  || inst.instruction > 0xffff
9765	  || inst.operands[1].shifted
9766	  || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9767	narrow = FALSE;
9768      else if (inst.instruction == T_MNEM_cmn)
9769	narrow = TRUE;
9770      else if (THUMB_SETS_FLAGS (inst.instruction))
9771	narrow = (current_it_mask == 0);
9772      else
9773	narrow = (current_it_mask != 0);
9774
9775      if (!inst.operands[1].isreg)
9776	{
9777	  /* For an immediate, we always generate a 32-bit opcode;
9778	     section relaxation will shrink it later if possible.  */
9779	  if (inst.instruction < 0xffff)
9780	    inst.instruction = THUMB_OP32 (inst.instruction);
9781	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9782	  inst.instruction |= inst.operands[0].reg << r0off;
9783	  inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9784	}
9785      else
9786	{
9787	  /* See if we can do this with a 16-bit instruction.  */
9788	  if (narrow)
9789	    {
9790	      inst.instruction = THUMB_OP16 (inst.instruction);
9791	      inst.instruction |= inst.operands[0].reg;
9792	      inst.instruction |= inst.operands[1].reg << 3;
9793	    }
9794	  else
9795	    {
9796	      constraint (inst.operands[1].shifted
9797			  && inst.operands[1].immisreg,
9798			  _("shift must be constant"));
9799	      if (inst.instruction < 0xffff)
9800		inst.instruction = THUMB_OP32 (inst.instruction);
9801	      inst.instruction |= inst.operands[0].reg << r0off;
9802	      encode_thumb32_shifted_operand (1);
9803	    }
9804	}
9805    }
9806  else
9807    {
9808      constraint (inst.instruction > 0xffff
9809		  || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
9810      constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
9811		  _("unshifted register required"));
9812      constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9813		  BAD_HIREG);
9814
9815      inst.instruction = THUMB_OP16 (inst.instruction);
9816      inst.instruction |= inst.operands[0].reg;
9817      inst.instruction |= inst.operands[1].reg << 3;
9818    }
9819}
9820
9821static void
9822do_t_mrs (void)
9823{
9824  int flags;
9825
9826  if (do_vfp_nsyn_mrs () == SUCCESS)
9827    return;
9828
9829  flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
9830  if (flags == 0)
9831    {
9832      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
9833		  _("selected processor does not support "
9834		    "requested special purpose register"));
9835    }
9836  else
9837    {
9838      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
9839		  _("selected processor does not support "
9840		    "requested special purpose register %x"));
9841      /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all.  */
9842      constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
9843		  _("'CPSR' or 'SPSR' expected"));
9844    }
9845
9846  inst.instruction |= inst.operands[0].reg << 8;
9847  inst.instruction |= (flags & SPSR_BIT) >> 2;
9848  inst.instruction |= inst.operands[1].imm & 0xff;
9849}
9850
9851static void
9852do_t_msr (void)
9853{
9854  int flags;
9855
9856  if (do_vfp_nsyn_msr () == SUCCESS)
9857    return;
9858
9859  constraint (!inst.operands[1].isreg,
9860	      _("Thumb encoding does not support an immediate here"));
9861  flags = inst.operands[0].imm;
9862  if (flags & ~0xff)
9863    {
9864      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
9865		  _("selected processor does not support "
9866		    "requested special purpose register"));
9867    }
9868  else
9869    {
9870      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
9871		  _("selected processor does not support "
9872		    "requested special purpose register"));
9873      flags |= PSR_f;
9874    }
9875  inst.instruction |= (flags & SPSR_BIT) >> 2;
9876  inst.instruction |= (flags & ~SPSR_BIT) >> 8;
9877  inst.instruction |= (flags & 0xff);
9878  inst.instruction |= inst.operands[1].reg << 16;
9879}
9880
9881static void
9882do_t_mul (void)
9883{
9884  if (!inst.operands[2].present)
9885    inst.operands[2].reg = inst.operands[0].reg;
9886
9887  /* There is no 32-bit MULS and no 16-bit MUL. */
9888  if (unified_syntax && inst.instruction == T_MNEM_mul)
9889    {
9890      inst.instruction = THUMB_OP32 (inst.instruction);
9891      inst.instruction |= inst.operands[0].reg << 8;
9892      inst.instruction |= inst.operands[1].reg << 16;
9893      inst.instruction |= inst.operands[2].reg << 0;
9894    }
9895  else
9896    {
9897      constraint (!unified_syntax
9898		  && inst.instruction == T_MNEM_muls, BAD_THUMB32);
9899      constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9900		  BAD_HIREG);
9901
9902      inst.instruction = THUMB_OP16 (inst.instruction);
9903      inst.instruction |= inst.operands[0].reg;
9904
9905      if (inst.operands[0].reg == inst.operands[1].reg)
9906	inst.instruction |= inst.operands[2].reg << 3;
9907      else if (inst.operands[0].reg == inst.operands[2].reg)
9908	inst.instruction |= inst.operands[1].reg << 3;
9909      else
9910	constraint (1, _("dest must overlap one source register"));
9911    }
9912}
9913
9914static void
9915do_t_mull (void)
9916{
9917  inst.instruction |= inst.operands[0].reg << 12;
9918  inst.instruction |= inst.operands[1].reg << 8;
9919  inst.instruction |= inst.operands[2].reg << 16;
9920  inst.instruction |= inst.operands[3].reg;
9921
9922  if (inst.operands[0].reg == inst.operands[1].reg)
9923    as_tsktsk (_("rdhi and rdlo must be different"));
9924}
9925
9926static void
9927do_t_nop (void)
9928{
9929  if (unified_syntax)
9930    {
9931      if (inst.size_req == 4 || inst.operands[0].imm > 15)
9932	{
9933	  inst.instruction = THUMB_OP32 (inst.instruction);
9934	  inst.instruction |= inst.operands[0].imm;
9935	}
9936      else
9937	{
9938	  inst.instruction = THUMB_OP16 (inst.instruction);
9939	  inst.instruction |= inst.operands[0].imm << 4;
9940	}
9941    }
9942  else
9943    {
9944      constraint (inst.operands[0].present,
9945		  _("Thumb does not support NOP with hints"));
9946      inst.instruction = 0x46c0;
9947    }
9948}
9949
9950static void
9951do_t_neg (void)
9952{
9953  if (unified_syntax)
9954    {
9955      bfd_boolean narrow;
9956
9957      if (THUMB_SETS_FLAGS (inst.instruction))
9958	narrow = (current_it_mask == 0);
9959      else
9960	narrow = (current_it_mask != 0);
9961      if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9962	narrow = FALSE;
9963      if (inst.size_req == 4)
9964	narrow = FALSE;
9965
9966      if (!narrow)
9967	{
9968	  inst.instruction = THUMB_OP32 (inst.instruction);
9969	  inst.instruction |= inst.operands[0].reg << 8;
9970	  inst.instruction |= inst.operands[1].reg << 16;
9971	}
9972      else
9973	{
9974	  inst.instruction = THUMB_OP16 (inst.instruction);
9975	  inst.instruction |= inst.operands[0].reg;
9976	  inst.instruction |= inst.operands[1].reg << 3;
9977	}
9978    }
9979  else
9980    {
9981      constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9982		  BAD_HIREG);
9983      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9984
9985      inst.instruction = THUMB_OP16 (inst.instruction);
9986      inst.instruction |= inst.operands[0].reg;
9987      inst.instruction |= inst.operands[1].reg << 3;
9988    }
9989}
9990
9991static void
9992do_t_pkhbt (void)
9993{
9994  inst.instruction |= inst.operands[0].reg << 8;
9995  inst.instruction |= inst.operands[1].reg << 16;
9996  inst.instruction |= inst.operands[2].reg;
9997  if (inst.operands[3].present)
9998    {
9999      unsigned int val = inst.reloc.exp.X_add_number;
10000      constraint (inst.reloc.exp.X_op != O_constant,
10001		  _("expression too complex"));
10002      inst.instruction |= (val & 0x1c) << 10;
10003      inst.instruction |= (val & 0x03) << 6;
10004    }
10005}
10006
10007static void
10008do_t_pkhtb (void)
10009{
10010  if (!inst.operands[3].present)
10011    inst.instruction &= ~0x00000020;
10012  do_t_pkhbt ();
10013}
10014
10015static void
10016do_t_pld (void)
10017{
10018  encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
10019}
10020
10021static void
10022do_t_push_pop (void)
10023{
10024  unsigned mask;
10025
10026  constraint (inst.operands[0].writeback,
10027	      _("push/pop do not support {reglist}^"));
10028  constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10029	      _("expression too complex"));
10030
10031  mask = inst.operands[0].imm;
10032  if ((mask & ~0xff) == 0)
10033    inst.instruction = THUMB_OP16 (inst.instruction) | mask;
10034  else if ((inst.instruction == T_MNEM_push
10035	    && (mask & ~0xff) == 1 << REG_LR)
10036	   || (inst.instruction == T_MNEM_pop
10037	       && (mask & ~0xff) == 1 << REG_PC))
10038    {
10039      inst.instruction = THUMB_OP16 (inst.instruction);
10040      inst.instruction |= THUMB_PP_PC_LR;
10041      inst.instruction |= mask & 0xff;
10042    }
10043  else if (unified_syntax)
10044    {
10045      inst.instruction = THUMB_OP32 (inst.instruction);
10046      encode_thumb2_ldmstm(13, mask, TRUE);
10047    }
10048  else
10049    {
10050      inst.error = _("invalid register list to push/pop instruction");
10051      return;
10052    }
10053}
10054
10055static void
10056do_t_rbit (void)
10057{
10058  inst.instruction |= inst.operands[0].reg << 8;
10059  inst.instruction |= inst.operands[1].reg << 16;
10060}
10061
10062static void
10063do_t_rd_rm (void)
10064{
10065  inst.instruction |= inst.operands[0].reg << 8;
10066  inst.instruction |= inst.operands[1].reg;
10067}
10068
10069static void
10070do_t_rev (void)
10071{
10072  if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
10073      && inst.size_req != 4)
10074    {
10075      inst.instruction = THUMB_OP16 (inst.instruction);
10076      inst.instruction |= inst.operands[0].reg;
10077      inst.instruction |= inst.operands[1].reg << 3;
10078    }
10079  else if (unified_syntax)
10080    {
10081      inst.instruction = THUMB_OP32 (inst.instruction);
10082      inst.instruction |= inst.operands[0].reg << 8;
10083      inst.instruction |= inst.operands[1].reg << 16;
10084      inst.instruction |= inst.operands[1].reg;
10085    }
10086  else
10087    inst.error = BAD_HIREG;
10088}
10089
10090static void
10091do_t_rsb (void)
10092{
10093  int Rd, Rs;
10094
10095  Rd = inst.operands[0].reg;
10096  Rs = (inst.operands[1].present
10097	? inst.operands[1].reg    /* Rd, Rs, foo */
10098	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
10099
10100  inst.instruction |= Rd << 8;
10101  inst.instruction |= Rs << 16;
10102  if (!inst.operands[2].isreg)
10103    {
10104      bfd_boolean narrow;
10105
10106      if ((inst.instruction & 0x00100000) != 0)
10107	narrow = (current_it_mask == 0);
10108      else
10109	narrow = (current_it_mask != 0);
10110
10111      if (Rd > 7 || Rs > 7)
10112	narrow = FALSE;
10113
10114      if (inst.size_req == 4 || !unified_syntax)
10115	narrow = FALSE;
10116
10117      if (inst.reloc.exp.X_op != O_constant
10118	  || inst.reloc.exp.X_add_number != 0)
10119	narrow = FALSE;
10120
10121      /* Turn rsb #0 into 16-bit neg.  We should probably do this via
10122         relaxation, but it doesn't seem worth the hassle.  */
10123      if (narrow)
10124	{
10125	  inst.reloc.type = BFD_RELOC_UNUSED;
10126	  inst.instruction = THUMB_OP16 (T_MNEM_negs);
10127	  inst.instruction |= Rs << 3;
10128	  inst.instruction |= Rd;
10129	}
10130      else
10131	{
10132	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10133	  inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10134	}
10135    }
10136  else
10137    encode_thumb32_shifted_operand (2);
10138}
10139
10140static void
10141do_t_setend (void)
10142{
10143  constraint (current_it_mask, BAD_NOT_IT);
10144  if (inst.operands[0].imm)
10145    inst.instruction |= 0x8;
10146}
10147
10148static void
10149do_t_shift (void)
10150{
10151  if (!inst.operands[1].present)
10152    inst.operands[1].reg = inst.operands[0].reg;
10153
10154  if (unified_syntax)
10155    {
10156      bfd_boolean narrow;
10157      int shift_kind;
10158
10159      switch (inst.instruction)
10160	{
10161	case T_MNEM_asr:
10162	case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
10163	case T_MNEM_lsl:
10164	case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
10165	case T_MNEM_lsr:
10166	case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
10167	case T_MNEM_ror:
10168	case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
10169	default: abort ();
10170	}
10171
10172      if (THUMB_SETS_FLAGS (inst.instruction))
10173	narrow = (current_it_mask == 0);
10174      else
10175	narrow = (current_it_mask != 0);
10176      if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
10177	narrow = FALSE;
10178      if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
10179	narrow = FALSE;
10180      if (inst.operands[2].isreg
10181	  && (inst.operands[1].reg != inst.operands[0].reg
10182	      || inst.operands[2].reg > 7))
10183	narrow = FALSE;
10184      if (inst.size_req == 4)
10185	narrow = FALSE;
10186
10187      if (!narrow)
10188	{
10189	  if (inst.operands[2].isreg)
10190	    {
10191	      inst.instruction = THUMB_OP32 (inst.instruction);
10192	      inst.instruction |= inst.operands[0].reg << 8;
10193	      inst.instruction |= inst.operands[1].reg << 16;
10194	      inst.instruction |= inst.operands[2].reg;
10195	    }
10196	  else
10197	    {
10198	      inst.operands[1].shifted = 1;
10199	      inst.operands[1].shift_kind = shift_kind;
10200	      inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
10201					     ? T_MNEM_movs : T_MNEM_mov);
10202	      inst.instruction |= inst.operands[0].reg << 8;
10203	      encode_thumb32_shifted_operand (1);
10204	      /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup.  */
10205	      inst.reloc.type = BFD_RELOC_UNUSED;
10206	    }
10207	}
10208      else
10209	{
10210	  if (inst.operands[2].isreg)
10211	    {
10212	      switch (shift_kind)
10213		{
10214		case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
10215		case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
10216		case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
10217		case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
10218		default: abort ();
10219		}
10220
10221	      inst.instruction |= inst.operands[0].reg;
10222	      inst.instruction |= inst.operands[2].reg << 3;
10223	    }
10224	  else
10225	    {
10226	      switch (shift_kind)
10227		{
10228		case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10229		case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10230		case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10231		default: abort ();
10232		}
10233	      inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10234	      inst.instruction |= inst.operands[0].reg;
10235	      inst.instruction |= inst.operands[1].reg << 3;
10236	    }
10237	}
10238    }
10239  else
10240    {
10241      constraint (inst.operands[0].reg > 7
10242		  || inst.operands[1].reg > 7, BAD_HIREG);
10243      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10244
10245      if (inst.operands[2].isreg)  /* Rd, {Rs,} Rn */
10246	{
10247	  constraint (inst.operands[2].reg > 7, BAD_HIREG);
10248	  constraint (inst.operands[0].reg != inst.operands[1].reg,
10249		      _("source1 and dest must be same register"));
10250
10251	  switch (inst.instruction)
10252	    {
10253	    case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
10254	    case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
10255	    case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
10256	    case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
10257	    default: abort ();
10258	    }
10259
10260	  inst.instruction |= inst.operands[0].reg;
10261	  inst.instruction |= inst.operands[2].reg << 3;
10262	}
10263      else
10264	{
10265	  switch (inst.instruction)
10266	    {
10267	    case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
10268	    case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
10269	    case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
10270	    case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
10271	    default: abort ();
10272	    }
10273	  inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10274	  inst.instruction |= inst.operands[0].reg;
10275	  inst.instruction |= inst.operands[1].reg << 3;
10276	}
10277    }
10278}
10279
10280static void
10281do_t_simd (void)
10282{
10283  inst.instruction |= inst.operands[0].reg << 8;
10284  inst.instruction |= inst.operands[1].reg << 16;
10285  inst.instruction |= inst.operands[2].reg;
10286}
10287
10288static void
10289do_t_smc (void)
10290{
10291  unsigned int value = inst.reloc.exp.X_add_number;
10292  constraint (inst.reloc.exp.X_op != O_constant,
10293	      _("expression too complex"));
10294  inst.reloc.type = BFD_RELOC_UNUSED;
10295  inst.instruction |= (value & 0xf000) >> 12;
10296  inst.instruction |= (value & 0x0ff0);
10297  inst.instruction |= (value & 0x000f) << 16;
10298}
10299
10300static void
10301do_t_ssat (void)
10302{
10303  inst.instruction |= inst.operands[0].reg << 8;
10304  inst.instruction |= inst.operands[1].imm - 1;
10305  inst.instruction |= inst.operands[2].reg << 16;
10306
10307  if (inst.operands[3].present)
10308    {
10309      constraint (inst.reloc.exp.X_op != O_constant,
10310		  _("expression too complex"));
10311
10312      if (inst.reloc.exp.X_add_number != 0)
10313	{
10314	  if (inst.operands[3].shift_kind == SHIFT_ASR)
10315	    inst.instruction |= 0x00200000;  /* sh bit */
10316	  inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
10317	  inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
10318	}
10319      inst.reloc.type = BFD_RELOC_UNUSED;
10320    }
10321}
10322
10323static void
10324do_t_ssat16 (void)
10325{
10326  inst.instruction |= inst.operands[0].reg << 8;
10327  inst.instruction |= inst.operands[1].imm - 1;
10328  inst.instruction |= inst.operands[2].reg << 16;
10329}
10330
10331static void
10332do_t_strex (void)
10333{
10334  constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10335	      || inst.operands[2].postind || inst.operands[2].writeback
10336	      || inst.operands[2].immisreg || inst.operands[2].shifted
10337	      || inst.operands[2].negative,
10338	      BAD_ADDR_MODE);
10339
10340  inst.instruction |= inst.operands[0].reg << 8;
10341  inst.instruction |= inst.operands[1].reg << 12;
10342  inst.instruction |= inst.operands[2].reg << 16;
10343  inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10344}
10345
10346static void
10347do_t_strexd (void)
10348{
10349  if (!inst.operands[2].present)
10350    inst.operands[2].reg = inst.operands[1].reg + 1;
10351
10352  constraint (inst.operands[0].reg == inst.operands[1].reg
10353	      || inst.operands[0].reg == inst.operands[2].reg
10354	      || inst.operands[0].reg == inst.operands[3].reg
10355	      || inst.operands[1].reg == inst.operands[2].reg,
10356	      BAD_OVERLAP);
10357
10358  inst.instruction |= inst.operands[0].reg;
10359  inst.instruction |= inst.operands[1].reg << 12;
10360  inst.instruction |= inst.operands[2].reg << 8;
10361  inst.instruction |= inst.operands[3].reg << 16;
10362}
10363
10364static void
10365do_t_sxtah (void)
10366{
10367  inst.instruction |= inst.operands[0].reg << 8;
10368  inst.instruction |= inst.operands[1].reg << 16;
10369  inst.instruction |= inst.operands[2].reg;
10370  inst.instruction |= inst.operands[3].imm << 4;
10371}
10372
10373static void
10374do_t_sxth (void)
10375{
10376  if (inst.instruction <= 0xffff && inst.size_req != 4
10377      && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
10378      && (!inst.operands[2].present || inst.operands[2].imm == 0))
10379    {
10380      inst.instruction = THUMB_OP16 (inst.instruction);
10381      inst.instruction |= inst.operands[0].reg;
10382      inst.instruction |= inst.operands[1].reg << 3;
10383    }
10384  else if (unified_syntax)
10385    {
10386      if (inst.instruction <= 0xffff)
10387	inst.instruction = THUMB_OP32 (inst.instruction);
10388      inst.instruction |= inst.operands[0].reg << 8;
10389      inst.instruction |= inst.operands[1].reg;
10390      inst.instruction |= inst.operands[2].imm << 4;
10391    }
10392  else
10393    {
10394      constraint (inst.operands[2].present && inst.operands[2].imm != 0,
10395		  _("Thumb encoding does not support rotation"));
10396      constraint (1, BAD_HIREG);
10397    }
10398}
10399
10400static void
10401do_t_swi (void)
10402{
10403  inst.reloc.type = BFD_RELOC_ARM_SWI;
10404}
10405
10406static void
10407do_t_tb (void)
10408{
10409  int half;
10410
10411  half = (inst.instruction & 0x10) != 0;
10412  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
10413  constraint (inst.operands[0].immisreg,
10414	      _("instruction requires register index"));
10415  constraint (inst.operands[0].imm == 15,
10416	      _("PC is not a valid index register"));
10417  constraint (!half && inst.operands[0].shifted,
10418	      _("instruction does not allow shifted index"));
10419  inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
10420}
10421
10422static void
10423do_t_usat (void)
10424{
10425  inst.instruction |= inst.operands[0].reg << 8;
10426  inst.instruction |= inst.operands[1].imm;
10427  inst.instruction |= inst.operands[2].reg << 16;
10428
10429  if (inst.operands[3].present)
10430    {
10431      constraint (inst.reloc.exp.X_op != O_constant,
10432		  _("expression too complex"));
10433      if (inst.reloc.exp.X_add_number != 0)
10434	{
10435	  if (inst.operands[3].shift_kind == SHIFT_ASR)
10436	    inst.instruction |= 0x00200000;  /* sh bit */
10437
10438	  inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
10439	  inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
10440	}
10441      inst.reloc.type = BFD_RELOC_UNUSED;
10442    }
10443}
10444
10445static void
10446do_t_usat16 (void)
10447{
10448  inst.instruction |= inst.operands[0].reg << 8;
10449  inst.instruction |= inst.operands[1].imm;
10450  inst.instruction |= inst.operands[2].reg << 16;
10451}
10452
10453/* Neon instruction encoder helpers.  */
10454
10455/* Encodings for the different types for various Neon opcodes.  */
10456
10457/* An "invalid" code for the following tables.  */
10458#define N_INV -1u
10459
10460struct neon_tab_entry
10461{
10462  unsigned integer;
10463  unsigned float_or_poly;
10464  unsigned scalar_or_imm;
10465};
10466
10467/* Map overloaded Neon opcodes to their respective encodings.  */
10468#define NEON_ENC_TAB					\
10469  X(vabd,	0x0000700, 0x1200d00, N_INV),		\
10470  X(vmax,	0x0000600, 0x0000f00, N_INV),		\
10471  X(vmin,	0x0000610, 0x0200f00, N_INV),		\
10472  X(vpadd,	0x0000b10, 0x1000d00, N_INV),		\
10473  X(vpmax,	0x0000a00, 0x1000f00, N_INV),		\
10474  X(vpmin,	0x0000a10, 0x1200f00, N_INV),		\
10475  X(vadd,	0x0000800, 0x0000d00, N_INV),		\
10476  X(vsub,	0x1000800, 0x0200d00, N_INV),		\
10477  X(vceq,	0x1000810, 0x0000e00, 0x1b10100),	\
10478  X(vcge,	0x0000310, 0x1000e00, 0x1b10080),	\
10479  X(vcgt,	0x0000300, 0x1200e00, 0x1b10000),	\
10480  /* Register variants of the following two instructions are encoded as
10481     vcge / vcgt with the operands reversed. */  	\
10482  X(vclt,	0x0000300, 0x1200e00, 0x1b10200),	\
10483  X(vcle,	0x0000310, 0x1000e00, 0x1b10180),	\
10484  X(vmla,	0x0000900, 0x0000d10, 0x0800040),	\
10485  X(vmls,	0x1000900, 0x0200d10, 0x0800440),	\
10486  X(vmul,	0x0000910, 0x1000d10, 0x0800840),	\
10487  X(vmull,	0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float.  */ \
10488  X(vmlal,	0x0800800, N_INV,     0x0800240),	\
10489  X(vmlsl,	0x0800a00, N_INV,     0x0800640),	\
10490  X(vqdmlal,	0x0800900, N_INV,     0x0800340),	\
10491  X(vqdmlsl,	0x0800b00, N_INV,     0x0800740),	\
10492  X(vqdmull,	0x0800d00, N_INV,     0x0800b40),	\
10493  X(vqdmulh,    0x0000b00, N_INV,     0x0800c40),	\
10494  X(vqrdmulh,   0x1000b00, N_INV,     0x0800d40),	\
10495  X(vshl,	0x0000400, N_INV,     0x0800510),	\
10496  X(vqshl,	0x0000410, N_INV,     0x0800710),	\
10497  X(vand,	0x0000110, N_INV,     0x0800030),	\
10498  X(vbic,	0x0100110, N_INV,     0x0800030),	\
10499  X(veor,	0x1000110, N_INV,     N_INV),		\
10500  X(vorn,	0x0300110, N_INV,     0x0800010),	\
10501  X(vorr,	0x0200110, N_INV,     0x0800010),	\
10502  X(vmvn,	0x1b00580, N_INV,     0x0800030),	\
10503  X(vshll,	0x1b20300, N_INV,     0x0800a10), /* max shift, immediate.  */ \
10504  X(vcvt,       0x1b30600, N_INV,     0x0800e10), /* integer, fixed-point.  */ \
10505  X(vdup,       0xe800b10, N_INV,     0x1b00c00), /* arm, scalar.  */ \
10506  X(vld1,       0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup.  */ \
10507  X(vst1,	0x0000000, 0x0800000, N_INV),		\
10508  X(vld2,	0x0200100, 0x0a00100, 0x0a00d00),	\
10509  X(vst2,	0x0000100, 0x0800100, N_INV),		\
10510  X(vld3,	0x0200200, 0x0a00200, 0x0a00e00),	\
10511  X(vst3,	0x0000200, 0x0800200, N_INV),		\
10512  X(vld4,	0x0200300, 0x0a00300, 0x0a00f00),	\
10513  X(vst4,	0x0000300, 0x0800300, N_INV),		\
10514  X(vmovn,	0x1b20200, N_INV,     N_INV),		\
10515  X(vtrn,	0x1b20080, N_INV,     N_INV),		\
10516  X(vqmovn,	0x1b20200, N_INV,     N_INV),		\
10517  X(vqmovun,	0x1b20240, N_INV,     N_INV),		\
10518  X(vnmul,      0xe200a40, 0xe200b40, N_INV),		\
10519  X(vnmla,      0xe000a40, 0xe000b40, N_INV),		\
10520  X(vnmls,      0xe100a40, 0xe100b40, N_INV),		\
10521  X(vcmp,	0xeb40a40, 0xeb40b40, N_INV),		\
10522  X(vcmpz,	0xeb50a40, 0xeb50b40, N_INV),		\
10523  X(vcmpe,	0xeb40ac0, 0xeb40bc0, N_INV),		\
10524  X(vcmpez,     0xeb50ac0, 0xeb50bc0, N_INV)
10525
10526enum neon_opc
10527{
10528#define X(OPC,I,F,S) N_MNEM_##OPC
10529NEON_ENC_TAB
10530#undef X
10531};
10532
10533static const struct neon_tab_entry neon_enc_tab[] =
10534{
10535#define X(OPC,I,F,S) { (I), (F), (S) }
10536NEON_ENC_TAB
10537#undef X
10538};
10539
10540#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10541#define NEON_ENC_ARMREG(X)  (neon_enc_tab[(X) & 0x0fffffff].integer)
10542#define NEON_ENC_POLY(X)    (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10543#define NEON_ENC_FLOAT(X)   (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10544#define NEON_ENC_SCALAR(X)  (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10545#define NEON_ENC_IMMED(X)   (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10546#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10547#define NEON_ENC_LANE(X)    (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10548#define NEON_ENC_DUP(X)     (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10549#define NEON_ENC_SINGLE(X) \
10550  ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10551#define NEON_ENC_DOUBLE(X) \
10552  ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10553
10554/* Define shapes for instruction operands. The following mnemonic characters
10555   are used in this table:
10556
10557     F - VFP S<n> register
10558     D - Neon D<n> register
10559     Q - Neon Q<n> register
10560     I - Immediate
10561     S - Scalar
10562     R - ARM register
10563     L - D<n> register list
10564
10565   This table is used to generate various data:
10566     - enumerations of the form NS_DDR to be used as arguments to
10567       neon_select_shape.
10568     - a table classifying shapes into single, double, quad, mixed.
10569     - a table used to drive neon_select_shape.
10570*/
10571
10572#define NEON_SHAPE_DEF			\
10573  X(3, (D, D, D), DOUBLE),		\
10574  X(3, (Q, Q, Q), QUAD),		\
10575  X(3, (D, D, I), DOUBLE),		\
10576  X(3, (Q, Q, I), QUAD),		\
10577  X(3, (D, D, S), DOUBLE),		\
10578  X(3, (Q, Q, S), QUAD),		\
10579  X(2, (D, D), DOUBLE),			\
10580  X(2, (Q, Q), QUAD),			\
10581  X(2, (D, S), DOUBLE),			\
10582  X(2, (Q, S), QUAD),			\
10583  X(2, (D, R), DOUBLE),			\
10584  X(2, (Q, R), QUAD),			\
10585  X(2, (D, I), DOUBLE),			\
10586  X(2, (Q, I), QUAD),			\
10587  X(3, (D, L, D), DOUBLE),		\
10588  X(2, (D, Q), MIXED),			\
10589  X(2, (Q, D), MIXED),			\
10590  X(3, (D, Q, I), MIXED),		\
10591  X(3, (Q, D, I), MIXED),		\
10592  X(3, (Q, D, D), MIXED),		\
10593  X(3, (D, Q, Q), MIXED),		\
10594  X(3, (Q, Q, D), MIXED),		\
10595  X(3, (Q, D, S), MIXED),		\
10596  X(3, (D, Q, S), MIXED),		\
10597  X(4, (D, D, D, I), DOUBLE),		\
10598  X(4, (Q, Q, Q, I), QUAD),		\
10599  X(2, (F, F), SINGLE),			\
10600  X(3, (F, F, F), SINGLE),		\
10601  X(2, (F, I), SINGLE),			\
10602  X(2, (F, D), MIXED),			\
10603  X(2, (D, F), MIXED),			\
10604  X(3, (F, F, I), MIXED),		\
10605  X(4, (R, R, F, F), SINGLE),		\
10606  X(4, (F, F, R, R), SINGLE),		\
10607  X(3, (D, R, R), DOUBLE),		\
10608  X(3, (R, R, D), DOUBLE),		\
10609  X(2, (S, R), SINGLE),			\
10610  X(2, (R, S), SINGLE),			\
10611  X(2, (F, R), SINGLE),			\
10612  X(2, (R, F), SINGLE)
10613
10614#define S2(A,B)		NS_##A##B
10615#define S3(A,B,C)	NS_##A##B##C
10616#define S4(A,B,C,D)	NS_##A##B##C##D
10617
10618#define X(N, L, C) S##N L
10619
10620enum neon_shape
10621{
10622  NEON_SHAPE_DEF,
10623  NS_NULL
10624};
10625
10626#undef X
10627#undef S2
10628#undef S3
10629#undef S4
10630
10631enum neon_shape_class
10632{
10633  SC_SINGLE,
10634  SC_DOUBLE,
10635  SC_QUAD,
10636  SC_MIXED
10637};
10638
10639#define X(N, L, C) SC_##C
10640
10641static enum neon_shape_class neon_shape_class[] =
10642{
10643  NEON_SHAPE_DEF
10644};
10645
10646#undef X
10647
10648enum neon_shape_el
10649{
10650  SE_F,
10651  SE_D,
10652  SE_Q,
10653  SE_I,
10654  SE_S,
10655  SE_R,
10656  SE_L
10657};
10658
10659/* Register widths of above.  */
10660static unsigned neon_shape_el_size[] =
10661{
10662  32,
10663  64,
10664  128,
10665  0,
10666  32,
10667  32,
10668  0
10669};
10670
10671struct neon_shape_info
10672{
10673  unsigned els;
10674  enum neon_shape_el el[NEON_MAX_TYPE_ELS];
10675};
10676
10677#define S2(A,B)		{ SE_##A, SE_##B }
10678#define S3(A,B,C)	{ SE_##A, SE_##B, SE_##C }
10679#define S4(A,B,C,D)	{ SE_##A, SE_##B, SE_##C, SE_##D }
10680
10681#define X(N, L, C) { N, S##N L }
10682
10683static struct neon_shape_info neon_shape_tab[] =
10684{
10685  NEON_SHAPE_DEF
10686};
10687
10688#undef X
10689#undef S2
10690#undef S3
10691#undef S4
10692
10693/* Bit masks used in type checking given instructions.
10694  'N_EQK' means the type must be the same as (or based on in some way) the key
10695   type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10696   set, various other bits can be set as well in order to modify the meaning of
10697   the type constraint.  */
10698
10699enum neon_type_mask
10700{
10701  N_S8   = 0x000001,
10702  N_S16  = 0x000002,
10703  N_S32  = 0x000004,
10704  N_S64  = 0x000008,
10705  N_U8   = 0x000010,
10706  N_U16  = 0x000020,
10707  N_U32  = 0x000040,
10708  N_U64  = 0x000080,
10709  N_I8   = 0x000100,
10710  N_I16  = 0x000200,
10711  N_I32  = 0x000400,
10712  N_I64  = 0x000800,
10713  N_8    = 0x001000,
10714  N_16   = 0x002000,
10715  N_32   = 0x004000,
10716  N_64   = 0x008000,
10717  N_P8   = 0x010000,
10718  N_P16  = 0x020000,
10719  N_F32  = 0x040000,
10720  N_F64  = 0x080000,
10721  N_KEY  = 0x100000, /* key element (main type specifier).  */
10722  N_EQK  = 0x200000, /* given operand has the same type & size as the key.  */
10723  N_VFP  = 0x400000, /* VFP mode: operand size must match register width.  */
10724  N_DBL  = 0x000001, /* if N_EQK, this operand is twice the size.  */
10725  N_HLF  = 0x000002, /* if N_EQK, this operand is half the size.  */
10726  N_SGN  = 0x000004, /* if N_EQK, this operand is forced to be signed.  */
10727  N_UNS  = 0x000008, /* if N_EQK, this operand is forced to be unsigned.  */
10728  N_INT  = 0x000010, /* if N_EQK, this operand is forced to be integer.  */
10729  N_FLT  = 0x000020, /* if N_EQK, this operand is forced to be float.  */
10730  N_SIZ  = 0x000040, /* if N_EQK, this operand is forced to be size-only.  */
10731  N_UTYP = 0,
10732  N_MAX_NONSPECIAL = N_F64
10733};
10734
10735#define N_ALLMODS  (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10736
10737#define N_SU_ALL   (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10738#define N_SU_32    (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10739#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10740#define N_SUF_32   (N_SU_32 | N_F32)
10741#define N_I_ALL    (N_I8 | N_I16 | N_I32 | N_I64)
10742#define N_IF_32    (N_I8 | N_I16 | N_I32 | N_F32)
10743
10744/* Pass this as the first type argument to neon_check_type to ignore types
10745   altogether.  */
10746#define N_IGNORE_TYPE (N_KEY | N_EQK)
10747
10748/* Select a "shape" for the current instruction (describing register types or
10749   sizes) from a list of alternatives. Return NS_NULL if the current instruction
10750   doesn't fit. For non-polymorphic shapes, checking is usually done as a
10751   function of operand parsing, so this function doesn't need to be called.
10752   Shapes should be listed in order of decreasing length.  */
10753
10754static enum neon_shape
10755neon_select_shape (enum neon_shape shape, ...)
10756{
10757  va_list ap;
10758  enum neon_shape first_shape = shape;
10759
10760  /* Fix missing optional operands. FIXME: we don't know at this point how
10761     many arguments we should have, so this makes the assumption that we have
10762     > 1. This is true of all current Neon opcodes, I think, but may not be
10763     true in the future.  */
10764  if (!inst.operands[1].present)
10765    inst.operands[1] = inst.operands[0];
10766
10767  va_start (ap, shape);
10768
10769  for (; shape != NS_NULL; shape = va_arg (ap, int))
10770    {
10771      unsigned j;
10772      int matches = 1;
10773
10774      for (j = 0; j < neon_shape_tab[shape].els; j++)
10775        {
10776          if (!inst.operands[j].present)
10777            {
10778              matches = 0;
10779              break;
10780            }
10781
10782          switch (neon_shape_tab[shape].el[j])
10783            {
10784            case SE_F:
10785              if (!(inst.operands[j].isreg
10786                    && inst.operands[j].isvec
10787                    && inst.operands[j].issingle
10788                    && !inst.operands[j].isquad))
10789                matches = 0;
10790              break;
10791
10792            case SE_D:
10793              if (!(inst.operands[j].isreg
10794                    && inst.operands[j].isvec
10795                    && !inst.operands[j].isquad
10796                    && !inst.operands[j].issingle))
10797                matches = 0;
10798              break;
10799
10800            case SE_R:
10801              if (!(inst.operands[j].isreg
10802                    && !inst.operands[j].isvec))
10803                matches = 0;
10804              break;
10805
10806            case SE_Q:
10807              if (!(inst.operands[j].isreg
10808                    && inst.operands[j].isvec
10809                    && inst.operands[j].isquad
10810                    && !inst.operands[j].issingle))
10811                matches = 0;
10812              break;
10813
10814            case SE_I:
10815              if (!(!inst.operands[j].isreg
10816                    && !inst.operands[j].isscalar))
10817                matches = 0;
10818              break;
10819
10820            case SE_S:
10821              if (!(!inst.operands[j].isreg
10822                    && inst.operands[j].isscalar))
10823                matches = 0;
10824              break;
10825
10826            case SE_L:
10827              break;
10828            }
10829        }
10830      if (matches)
10831        break;
10832    }
10833
10834  va_end (ap);
10835
10836  if (shape == NS_NULL && first_shape != NS_NULL)
10837    first_error (_("invalid instruction shape"));
10838
10839  return shape;
10840}
10841
10842/* True if SHAPE is predominantly a quadword operation (most of the time, this
10843   means the Q bit should be set).  */
10844
10845static int
10846neon_quad (enum neon_shape shape)
10847{
10848  return neon_shape_class[shape] == SC_QUAD;
10849}
10850
10851static void
10852neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
10853                       unsigned *g_size)
10854{
10855  /* Allow modification to be made to types which are constrained to be
10856     based on the key element, based on bits set alongside N_EQK.  */
10857  if ((typebits & N_EQK) != 0)
10858    {
10859      if ((typebits & N_HLF) != 0)
10860	*g_size /= 2;
10861      else if ((typebits & N_DBL) != 0)
10862	*g_size *= 2;
10863      if ((typebits & N_SGN) != 0)
10864	*g_type = NT_signed;
10865      else if ((typebits & N_UNS) != 0)
10866        *g_type = NT_unsigned;
10867      else if ((typebits & N_INT) != 0)
10868        *g_type = NT_integer;
10869      else if ((typebits & N_FLT) != 0)
10870        *g_type = NT_float;
10871      else if ((typebits & N_SIZ) != 0)
10872        *g_type = NT_untyped;
10873    }
10874}
10875
10876/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10877   operand type, i.e. the single type specified in a Neon instruction when it
10878   is the only one given.  */
10879
10880static struct neon_type_el
10881neon_type_promote (struct neon_type_el *key, unsigned thisarg)
10882{
10883  struct neon_type_el dest = *key;
10884
10885  assert ((thisarg & N_EQK) != 0);
10886
10887  neon_modify_type_size (thisarg, &dest.type, &dest.size);
10888
10889  return dest;
10890}
10891
10892/* Convert Neon type and size into compact bitmask representation.  */
10893
10894static enum neon_type_mask
10895type_chk_of_el_type (enum neon_el_type type, unsigned size)
10896{
10897  switch (type)
10898    {
10899    case NT_untyped:
10900      switch (size)
10901        {
10902        case 8:  return N_8;
10903        case 16: return N_16;
10904        case 32: return N_32;
10905        case 64: return N_64;
10906        default: ;
10907        }
10908      break;
10909
10910    case NT_integer:
10911      switch (size)
10912        {
10913        case 8:  return N_I8;
10914        case 16: return N_I16;
10915        case 32: return N_I32;
10916        case 64: return N_I64;
10917        default: ;
10918        }
10919      break;
10920
10921    case NT_float:
10922      switch (size)
10923        {
10924        case 32: return N_F32;
10925        case 64: return N_F64;
10926        default: ;
10927        }
10928      break;
10929
10930    case NT_poly:
10931      switch (size)
10932        {
10933        case 8:  return N_P8;
10934        case 16: return N_P16;
10935        default: ;
10936        }
10937      break;
10938
10939    case NT_signed:
10940      switch (size)
10941        {
10942        case 8:  return N_S8;
10943        case 16: return N_S16;
10944        case 32: return N_S32;
10945        case 64: return N_S64;
10946        default: ;
10947        }
10948      break;
10949
10950    case NT_unsigned:
10951      switch (size)
10952        {
10953        case 8:  return N_U8;
10954        case 16: return N_U16;
10955        case 32: return N_U32;
10956        case 64: return N_U64;
10957        default: ;
10958        }
10959      break;
10960
10961    default: ;
10962    }
10963
10964  return N_UTYP;
10965}
10966
10967/* Convert compact Neon bitmask type representation to a type and size. Only
10968   handles the case where a single bit is set in the mask.  */
10969
10970static int
10971el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
10972                     enum neon_type_mask mask)
10973{
10974  if ((mask & N_EQK) != 0)
10975    return FAIL;
10976
10977  if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
10978    *size = 8;
10979  else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
10980    *size = 16;
10981  else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
10982    *size = 32;
10983  else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
10984    *size = 64;
10985  else
10986    return FAIL;
10987
10988  if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
10989    *type = NT_signed;
10990  else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
10991    *type = NT_unsigned;
10992  else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
10993    *type = NT_integer;
10994  else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
10995    *type = NT_untyped;
10996  else if ((mask & (N_P8 | N_P16)) != 0)
10997    *type = NT_poly;
10998  else if ((mask & (N_F32 | N_F64)) != 0)
10999    *type = NT_float;
11000  else
11001    return FAIL;
11002
11003  return SUCCESS;
11004}
11005
11006/* Modify a bitmask of allowed types. This is only needed for type
11007   relaxation.  */
11008
11009static unsigned
11010modify_types_allowed (unsigned allowed, unsigned mods)
11011{
11012  unsigned size;
11013  enum neon_el_type type;
11014  unsigned destmask;
11015  int i;
11016
11017  destmask = 0;
11018
11019  for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
11020    {
11021      if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS)
11022        {
11023          neon_modify_type_size (mods, &type, &size);
11024          destmask |= type_chk_of_el_type (type, size);
11025        }
11026    }
11027
11028  return destmask;
11029}
11030
11031/* Check type and return type classification.
11032   The manual states (paraphrase): If one datatype is given, it indicates the
11033   type given in:
11034    - the second operand, if there is one
11035    - the operand, if there is no second operand
11036    - the result, if there are no operands.
11037   This isn't quite good enough though, so we use a concept of a "key" datatype
11038   which is set on a per-instruction basis, which is the one which matters when
11039   only one data type is written.
11040   Note: this function has side-effects (e.g. filling in missing operands). All
11041   Neon instructions should call it before performing bit encoding.  */
11042
11043static struct neon_type_el
11044neon_check_type (unsigned els, enum neon_shape ns, ...)
11045{
11046  va_list ap;
11047  unsigned i, pass, key_el = 0;
11048  unsigned types[NEON_MAX_TYPE_ELS];
11049  enum neon_el_type k_type = NT_invtype;
11050  unsigned k_size = -1u;
11051  struct neon_type_el badtype = {NT_invtype, -1};
11052  unsigned key_allowed = 0;
11053
11054  /* Optional registers in Neon instructions are always (not) in operand 1.
11055     Fill in the missing operand here, if it was omitted.  */
11056  if (els > 1 && !inst.operands[1].present)
11057    inst.operands[1] = inst.operands[0];
11058
11059  /* Suck up all the varargs.  */
11060  va_start (ap, ns);
11061  for (i = 0; i < els; i++)
11062    {
11063      unsigned thisarg = va_arg (ap, unsigned);
11064      if (thisarg == N_IGNORE_TYPE)
11065        {
11066          va_end (ap);
11067          return badtype;
11068        }
11069      types[i] = thisarg;
11070      if ((thisarg & N_KEY) != 0)
11071        key_el = i;
11072    }
11073  va_end (ap);
11074
11075  if (inst.vectype.elems > 0)
11076    for (i = 0; i < els; i++)
11077      if (inst.operands[i].vectype.type != NT_invtype)
11078        {
11079          first_error (_("types specified in both the mnemonic and operands"));
11080          return badtype;
11081        }
11082
11083  /* Duplicate inst.vectype elements here as necessary.
11084     FIXME: No idea if this is exactly the same as the ARM assembler,
11085     particularly when an insn takes one register and one non-register
11086     operand. */
11087  if (inst.vectype.elems == 1 && els > 1)
11088    {
11089      unsigned j;
11090      inst.vectype.elems = els;
11091      inst.vectype.el[key_el] = inst.vectype.el[0];
11092      for (j = 0; j < els; j++)
11093        if (j != key_el)
11094          inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
11095                                                  types[j]);
11096    }
11097  else if (inst.vectype.elems == 0 && els > 0)
11098    {
11099      unsigned j;
11100      /* No types were given after the mnemonic, so look for types specified
11101         after each operand. We allow some flexibility here; as long as the
11102         "key" operand has a type, we can infer the others.  */
11103      for (j = 0; j < els; j++)
11104        if (inst.operands[j].vectype.type != NT_invtype)
11105          inst.vectype.el[j] = inst.operands[j].vectype;
11106
11107      if (inst.operands[key_el].vectype.type != NT_invtype)
11108        {
11109          for (j = 0; j < els; j++)
11110            if (inst.operands[j].vectype.type == NT_invtype)
11111              inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
11112                                                      types[j]);
11113        }
11114      else
11115        {
11116          first_error (_("operand types can't be inferred"));
11117          return badtype;
11118        }
11119    }
11120  else if (inst.vectype.elems != els)
11121    {
11122      first_error (_("type specifier has the wrong number of parts"));
11123      return badtype;
11124    }
11125
11126  for (pass = 0; pass < 2; pass++)
11127    {
11128      for (i = 0; i < els; i++)
11129        {
11130          unsigned thisarg = types[i];
11131          unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
11132            ? modify_types_allowed (key_allowed, thisarg) : thisarg;
11133          enum neon_el_type g_type = inst.vectype.el[i].type;
11134          unsigned g_size = inst.vectype.el[i].size;
11135
11136          /* Decay more-specific signed & unsigned types to sign-insensitive
11137	     integer types if sign-specific variants are unavailable.  */
11138          if ((g_type == NT_signed || g_type == NT_unsigned)
11139	      && (types_allowed & N_SU_ALL) == 0)
11140	    g_type = NT_integer;
11141
11142          /* If only untyped args are allowed, decay any more specific types to
11143	     them. Some instructions only care about signs for some element
11144	     sizes, so handle that properly.  */
11145          if ((g_size == 8 && (types_allowed & N_8) != 0)
11146	      || (g_size == 16 && (types_allowed & N_16) != 0)
11147	      || (g_size == 32 && (types_allowed & N_32) != 0)
11148	      || (g_size == 64 && (types_allowed & N_64) != 0))
11149	    g_type = NT_untyped;
11150
11151          if (pass == 0)
11152            {
11153              if ((thisarg & N_KEY) != 0)
11154                {
11155                  k_type = g_type;
11156                  k_size = g_size;
11157                  key_allowed = thisarg & ~N_KEY;
11158                }
11159            }
11160          else
11161            {
11162              if ((thisarg & N_VFP) != 0)
11163                {
11164                  enum neon_shape_el regshape = neon_shape_tab[ns].el[i];
11165                  unsigned regwidth = neon_shape_el_size[regshape], match;
11166
11167                  /* In VFP mode, operands must match register widths. If we
11168                     have a key operand, use its width, else use the width of
11169                     the current operand.  */
11170                  if (k_size != -1u)
11171                    match = k_size;
11172                  else
11173                    match = g_size;
11174
11175                  if (regwidth != match)
11176                    {
11177                      first_error (_("operand size must match register width"));
11178                      return badtype;
11179                    }
11180                }
11181
11182              if ((thisarg & N_EQK) == 0)
11183                {
11184                  unsigned given_type = type_chk_of_el_type (g_type, g_size);
11185
11186                  if ((given_type & types_allowed) == 0)
11187                    {
11188	              first_error (_("bad type in Neon instruction"));
11189	              return badtype;
11190                    }
11191                }
11192              else
11193                {
11194                  enum neon_el_type mod_k_type = k_type;
11195                  unsigned mod_k_size = k_size;
11196                  neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
11197                  if (g_type != mod_k_type || g_size != mod_k_size)
11198                    {
11199                      first_error (_("inconsistent types in Neon instruction"));
11200                      return badtype;
11201                    }
11202                }
11203            }
11204        }
11205    }
11206
11207  return inst.vectype.el[key_el];
11208}
11209
11210/* Neon-style VFP instruction forwarding.  */
11211
11212/* Thumb VFP instructions have 0xE in the condition field.  */
11213
11214static void
11215do_vfp_cond_or_thumb (void)
11216{
11217  if (thumb_mode)
11218    inst.instruction |= 0xe0000000;
11219  else
11220    inst.instruction |= inst.cond << 28;
11221}
11222
11223/* Look up and encode a simple mnemonic, for use as a helper function for the
11224   Neon-style VFP syntax.  This avoids duplication of bits of the insns table,
11225   etc.  It is assumed that operand parsing has already been done, and that the
11226   operands are in the form expected by the given opcode (this isn't necessarily
11227   the same as the form in which they were parsed, hence some massaging must
11228   take place before this function is called).
11229   Checks current arch version against that in the looked-up opcode.  */
11230
11231static void
11232do_vfp_nsyn_opcode (const char *opname)
11233{
11234  const struct asm_opcode *opcode;
11235
11236  opcode = hash_find (arm_ops_hsh, opname);
11237
11238  if (!opcode)
11239    abort ();
11240
11241  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
11242                thumb_mode ? *opcode->tvariant : *opcode->avariant),
11243              _(BAD_FPU));
11244
11245  if (thumb_mode)
11246    {
11247      inst.instruction = opcode->tvalue;
11248      opcode->tencode ();
11249    }
11250  else
11251    {
11252      inst.instruction = (inst.cond << 28) | opcode->avalue;
11253      opcode->aencode ();
11254    }
11255}
11256
11257static void
11258do_vfp_nsyn_add_sub (enum neon_shape rs)
11259{
11260  int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
11261
11262  if (rs == NS_FFF)
11263    {
11264      if (is_add)
11265        do_vfp_nsyn_opcode ("fadds");
11266      else
11267        do_vfp_nsyn_opcode ("fsubs");
11268    }
11269  else
11270    {
11271      if (is_add)
11272        do_vfp_nsyn_opcode ("faddd");
11273      else
11274        do_vfp_nsyn_opcode ("fsubd");
11275    }
11276}
11277
11278/* Check operand types to see if this is a VFP instruction, and if so call
11279   PFN ().  */
11280
11281static int
11282try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
11283{
11284  enum neon_shape rs;
11285  struct neon_type_el et;
11286
11287  switch (args)
11288    {
11289    case 2:
11290      rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11291      et = neon_check_type (2, rs,
11292        N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11293      break;
11294
11295    case 3:
11296      rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11297      et = neon_check_type (3, rs,
11298        N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11299      break;
11300
11301    default:
11302      abort ();
11303    }
11304
11305  if (et.type != NT_invtype)
11306    {
11307      pfn (rs);
11308      return SUCCESS;
11309    }
11310  else
11311    inst.error = NULL;
11312
11313  return FAIL;
11314}
11315
11316static void
11317do_vfp_nsyn_mla_mls (enum neon_shape rs)
11318{
11319  int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
11320
11321  if (rs == NS_FFF)
11322    {
11323      if (is_mla)
11324        do_vfp_nsyn_opcode ("fmacs");
11325      else
11326        do_vfp_nsyn_opcode ("fmscs");
11327    }
11328  else
11329    {
11330      if (is_mla)
11331        do_vfp_nsyn_opcode ("fmacd");
11332      else
11333        do_vfp_nsyn_opcode ("fmscd");
11334    }
11335}
11336
11337static void
11338do_vfp_nsyn_mul (enum neon_shape rs)
11339{
11340  if (rs == NS_FFF)
11341    do_vfp_nsyn_opcode ("fmuls");
11342  else
11343    do_vfp_nsyn_opcode ("fmuld");
11344}
11345
11346static void
11347do_vfp_nsyn_abs_neg (enum neon_shape rs)
11348{
11349  int is_neg = (inst.instruction & 0x80) != 0;
11350  neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
11351
11352  if (rs == NS_FF)
11353    {
11354      if (is_neg)
11355        do_vfp_nsyn_opcode ("fnegs");
11356      else
11357        do_vfp_nsyn_opcode ("fabss");
11358    }
11359  else
11360    {
11361      if (is_neg)
11362        do_vfp_nsyn_opcode ("fnegd");
11363      else
11364        do_vfp_nsyn_opcode ("fabsd");
11365    }
11366}
11367
11368/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11369   insns belong to Neon, and are handled elsewhere.  */
11370
11371static void
11372do_vfp_nsyn_ldm_stm (int is_dbmode)
11373{
11374  int is_ldm = (inst.instruction & (1 << 20)) != 0;
11375  if (is_ldm)
11376    {
11377      if (is_dbmode)
11378        do_vfp_nsyn_opcode ("fldmdbs");
11379      else
11380        do_vfp_nsyn_opcode ("fldmias");
11381    }
11382  else
11383    {
11384      if (is_dbmode)
11385        do_vfp_nsyn_opcode ("fstmdbs");
11386      else
11387        do_vfp_nsyn_opcode ("fstmias");
11388    }
11389}
11390
11391static void
11392do_vfp_nsyn_sqrt (void)
11393{
11394  enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11395  neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11396
11397  if (rs == NS_FF)
11398    do_vfp_nsyn_opcode ("fsqrts");
11399  else
11400    do_vfp_nsyn_opcode ("fsqrtd");
11401}
11402
11403static void
11404do_vfp_nsyn_div (void)
11405{
11406  enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11407  neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
11408    N_F32 | N_F64 | N_KEY | N_VFP);
11409
11410  if (rs == NS_FFF)
11411    do_vfp_nsyn_opcode ("fdivs");
11412  else
11413    do_vfp_nsyn_opcode ("fdivd");
11414}
11415
11416static void
11417do_vfp_nsyn_nmul (void)
11418{
11419  enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11420  neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
11421    N_F32 | N_F64 | N_KEY | N_VFP);
11422
11423  if (rs == NS_FFF)
11424    {
11425      inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11426      do_vfp_sp_dyadic ();
11427    }
11428  else
11429    {
11430      inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11431      do_vfp_dp_rd_rn_rm ();
11432    }
11433  do_vfp_cond_or_thumb ();
11434}
11435
11436static void
11437do_vfp_nsyn_cmp (void)
11438{
11439  if (inst.operands[1].isreg)
11440    {
11441      enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11442      neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11443
11444      if (rs == NS_FF)
11445        {
11446          inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11447          do_vfp_sp_monadic ();
11448        }
11449      else
11450        {
11451          inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11452          do_vfp_dp_rd_rm ();
11453        }
11454    }
11455  else
11456    {
11457      enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
11458      neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
11459
11460      switch (inst.instruction & 0x0fffffff)
11461        {
11462        case N_MNEM_vcmp:
11463          inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
11464          break;
11465        case N_MNEM_vcmpe:
11466          inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
11467          break;
11468        default:
11469          abort ();
11470        }
11471
11472      if (rs == NS_FI)
11473        {
11474          inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11475          do_vfp_sp_compare_z ();
11476        }
11477      else
11478        {
11479          inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11480          do_vfp_dp_rd ();
11481        }
11482    }
11483  do_vfp_cond_or_thumb ();
11484}
11485
11486static void
11487nsyn_insert_sp (void)
11488{
11489  inst.operands[1] = inst.operands[0];
11490  memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
11491  inst.operands[0].reg = 13;
11492  inst.operands[0].isreg = 1;
11493  inst.operands[0].writeback = 1;
11494  inst.operands[0].present = 1;
11495}
11496
11497static void
11498do_vfp_nsyn_push (void)
11499{
11500  nsyn_insert_sp ();
11501  if (inst.operands[1].issingle)
11502    do_vfp_nsyn_opcode ("fstmdbs");
11503  else
11504    do_vfp_nsyn_opcode ("fstmdbd");
11505}
11506
11507static void
11508do_vfp_nsyn_pop (void)
11509{
11510  nsyn_insert_sp ();
11511  if (inst.operands[1].issingle)
11512    do_vfp_nsyn_opcode ("fldmias");
11513  else
11514    do_vfp_nsyn_opcode ("fldmiad");
11515}
11516
11517/* Fix up Neon data-processing instructions, ORing in the correct bits for
11518   ARM mode or Thumb mode and moving the encoded bit 24 to bit 28.  */
11519
11520static unsigned
11521neon_dp_fixup (unsigned i)
11522{
11523  if (thumb_mode)
11524    {
11525      /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode.  */
11526      if (i & (1 << 24))
11527        i |= 1 << 28;
11528
11529      i &= ~(1 << 24);
11530
11531      i |= 0xef000000;
11532    }
11533  else
11534    i |= 0xf2000000;
11535
11536  return i;
11537}
11538
11539/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11540   (0, 1, 2, 3).  */
11541
11542static unsigned
11543neon_logbits (unsigned x)
11544{
11545  return ffs (x) - 4;
11546}
11547
11548#define LOW4(R) ((R) & 0xf)
11549#define HI1(R) (((R) >> 4) & 1)
11550
11551/* Encode insns with bit pattern:
11552
11553  |28/24|23|22 |21 20|19 16|15 12|11    8|7|6|5|4|3  0|
11554  |  U  |x |D  |size | Rn  | Rd  |x x x x|N|Q|M|x| Rm |
11555
11556  SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11557  different meaning for some instruction.  */
11558
11559static void
11560neon_three_same (int isquad, int ubit, int size)
11561{
11562  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11563  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11564  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
11565  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
11566  inst.instruction |= LOW4 (inst.operands[2].reg);
11567  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
11568  inst.instruction |= (isquad != 0) << 6;
11569  inst.instruction |= (ubit != 0) << 24;
11570  if (size != -1)
11571    inst.instruction |= neon_logbits (size) << 20;
11572
11573  inst.instruction = neon_dp_fixup (inst.instruction);
11574}
11575
11576/* Encode instructions of the form:
11577
11578  |28/24|23|22|21 20|19 18|17 16|15 12|11      7|6|5|4|3  0|
11579  |  U  |x |D |x  x |size |x  x | Rd  |x x x x x|Q|M|x| Rm |
11580
11581  Don't write size if SIZE == -1.  */
11582
11583static void
11584neon_two_same (int qbit, int ubit, int size)
11585{
11586  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11587  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11588  inst.instruction |= LOW4 (inst.operands[1].reg);
11589  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11590  inst.instruction |= (qbit != 0) << 6;
11591  inst.instruction |= (ubit != 0) << 24;
11592
11593  if (size != -1)
11594    inst.instruction |= neon_logbits (size) << 18;
11595
11596  inst.instruction = neon_dp_fixup (inst.instruction);
11597}
11598
11599/* Neon instruction encoders, in approximate order of appearance.  */
11600
11601static void
11602do_neon_dyadic_i_su (void)
11603{
11604  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11605  struct neon_type_el et = neon_check_type (3, rs,
11606    N_EQK, N_EQK, N_SU_32 | N_KEY);
11607  neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11608}
11609
11610static void
11611do_neon_dyadic_i64_su (void)
11612{
11613  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11614  struct neon_type_el et = neon_check_type (3, rs,
11615    N_EQK, N_EQK, N_SU_ALL | N_KEY);
11616  neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11617}
11618
11619static void
11620neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
11621                unsigned immbits)
11622{
11623  unsigned size = et.size >> 3;
11624  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11625  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11626  inst.instruction |= LOW4 (inst.operands[1].reg);
11627  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11628  inst.instruction |= (isquad != 0) << 6;
11629  inst.instruction |= immbits << 16;
11630  inst.instruction |= (size >> 3) << 7;
11631  inst.instruction |= (size & 0x7) << 19;
11632  if (write_ubit)
11633    inst.instruction |= (uval != 0) << 24;
11634
11635  inst.instruction = neon_dp_fixup (inst.instruction);
11636}
11637
11638static void
11639do_neon_shl_imm (void)
11640{
11641  if (!inst.operands[2].isreg)
11642    {
11643      enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
11644      struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
11645      inst.instruction = NEON_ENC_IMMED (inst.instruction);
11646      neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
11647    }
11648  else
11649    {
11650      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11651      struct neon_type_el et = neon_check_type (3, rs,
11652        N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
11653      unsigned int tmp;
11654
11655      /* VSHL/VQSHL 3-register variants have syntax such as:
11656           vshl.xx Dd, Dm, Dn
11657         whereas other 3-register operations encoded by neon_three_same have
11658         syntax like:
11659           vadd.xx Dd, Dn, Dm
11660         (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11661         here.  */
11662      tmp = inst.operands[2].reg;
11663      inst.operands[2].reg = inst.operands[1].reg;
11664      inst.operands[1].reg = tmp;
11665      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11666      neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11667    }
11668}
11669
11670static void
11671do_neon_qshl_imm (void)
11672{
11673  if (!inst.operands[2].isreg)
11674    {
11675      enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
11676      struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
11677
11678      inst.instruction = NEON_ENC_IMMED (inst.instruction);
11679      neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
11680                      inst.operands[2].imm);
11681    }
11682  else
11683    {
11684      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11685      struct neon_type_el et = neon_check_type (3, rs,
11686        N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
11687      unsigned int tmp;
11688
11689      /* See note in do_neon_shl_imm.  */
11690      tmp = inst.operands[2].reg;
11691      inst.operands[2].reg = inst.operands[1].reg;
11692      inst.operands[1].reg = tmp;
11693      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11694      neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11695    }
11696}
11697
11698static void
11699do_neon_rshl (void)
11700{
11701  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11702  struct neon_type_el et = neon_check_type (3, rs,
11703    N_EQK, N_EQK, N_SU_ALL | N_KEY);
11704  unsigned int tmp;
11705
11706  tmp = inst.operands[2].reg;
11707  inst.operands[2].reg = inst.operands[1].reg;
11708  inst.operands[1].reg = tmp;
11709  neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11710}
11711
11712static int
11713neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
11714{
11715  /* Handle .I8 pseudo-instructions.  */
11716  if (size == 8)
11717    {
11718      /* Unfortunately, this will make everything apart from zero out-of-range.
11719         FIXME is this the intended semantics? There doesn't seem much point in
11720         accepting .I8 if so.  */
11721      immediate |= immediate << 8;
11722      size = 16;
11723    }
11724
11725  if (size >= 32)
11726    {
11727      if (immediate == (immediate & 0x000000ff))
11728	{
11729	  *immbits = immediate;
11730	  return 0x1;
11731	}
11732      else if (immediate == (immediate & 0x0000ff00))
11733	{
11734	  *immbits = immediate >> 8;
11735	  return 0x3;
11736	}
11737      else if (immediate == (immediate & 0x00ff0000))
11738	{
11739	  *immbits = immediate >> 16;
11740	  return 0x5;
11741	}
11742      else if (immediate == (immediate & 0xff000000))
11743	{
11744	  *immbits = immediate >> 24;
11745	  return 0x7;
11746	}
11747      if ((immediate & 0xffff) != (immediate >> 16))
11748	goto bad_immediate;
11749      immediate &= 0xffff;
11750    }
11751
11752  if (immediate == (immediate & 0x000000ff))
11753    {
11754      *immbits = immediate;
11755      return 0x9;
11756    }
11757  else if (immediate == (immediate & 0x0000ff00))
11758    {
11759      *immbits = immediate >> 8;
11760      return 0xb;
11761    }
11762
11763  bad_immediate:
11764  first_error (_("immediate value out of range"));
11765  return FAIL;
11766}
11767
11768/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11769   A, B, C, D.  */
11770
11771static int
11772neon_bits_same_in_bytes (unsigned imm)
11773{
11774  return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
11775         && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
11776         && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
11777         && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
11778}
11779
11780/* For immediate of above form, return 0bABCD.  */
11781
11782static unsigned
11783neon_squash_bits (unsigned imm)
11784{
11785  return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
11786         | ((imm & 0x01000000) >> 21);
11787}
11788
11789/* Compress quarter-float representation to 0b...000 abcdefgh.  */
11790
11791static unsigned
11792neon_qfloat_bits (unsigned imm)
11793{
11794  return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
11795}
11796
11797/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11798   the instruction. *OP is passed as the initial value of the op field, and
11799   may be set to a different value depending on the constant (i.e.
11800   "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11801   MVN).  If the immediate looks like a repeated parttern then also
11802   try smaller element sizes.  */
11803
11804static int
11805neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
11806			 unsigned *immbits, int *op, int size,
11807			 enum neon_el_type type)
11808{
11809  /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11810     float.  */
11811  if (type == NT_float && !float_p)
11812    return FAIL;
11813
11814  if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
11815    {
11816      if (size != 32 || *op == 1)
11817        return FAIL;
11818      *immbits = neon_qfloat_bits (immlo);
11819      return 0xf;
11820    }
11821
11822  if (size == 64)
11823    {
11824      if (neon_bits_same_in_bytes (immhi)
11825	  && neon_bits_same_in_bytes (immlo))
11826	{
11827	  if (*op == 1)
11828	    return FAIL;
11829	  *immbits = (neon_squash_bits (immhi) << 4)
11830		     | neon_squash_bits (immlo);
11831	  *op = 1;
11832	  return 0xe;
11833	}
11834
11835      if (immhi != immlo)
11836	return FAIL;
11837    }
11838
11839  if (size >= 32)
11840    {
11841      if (immlo == (immlo & 0x000000ff))
11842	{
11843	  *immbits = immlo;
11844	  return 0x0;
11845	}
11846      else if (immlo == (immlo & 0x0000ff00))
11847	{
11848	  *immbits = immlo >> 8;
11849	  return 0x2;
11850	}
11851      else if (immlo == (immlo & 0x00ff0000))
11852	{
11853	  *immbits = immlo >> 16;
11854	  return 0x4;
11855	}
11856      else if (immlo == (immlo & 0xff000000))
11857	{
11858	  *immbits = immlo >> 24;
11859	  return 0x6;
11860	}
11861      else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
11862	{
11863	  *immbits = (immlo >> 8) & 0xff;
11864	  return 0xc;
11865	}
11866      else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
11867	{
11868	  *immbits = (immlo >> 16) & 0xff;
11869	  return 0xd;
11870	}
11871
11872      if ((immlo & 0xffff) != (immlo >> 16))
11873	return FAIL;
11874      immlo &= 0xffff;
11875    }
11876
11877  if (size >= 16)
11878    {
11879      if (immlo == (immlo & 0x000000ff))
11880	{
11881	  *immbits = immlo;
11882	  return 0x8;
11883	}
11884      else if (immlo == (immlo & 0x0000ff00))
11885	{
11886	  *immbits = immlo >> 8;
11887	  return 0xa;
11888	}
11889
11890      if ((immlo & 0xff) != (immlo >> 8))
11891	return FAIL;
11892      immlo &= 0xff;
11893    }
11894
11895  if (immlo == (immlo & 0x000000ff))
11896    {
11897      /* Don't allow MVN with 8-bit immediate.  */
11898      if (*op == 1)
11899	return FAIL;
11900      *immbits = immlo;
11901      return 0xe;
11902    }
11903
11904  return FAIL;
11905}
11906
11907/* Write immediate bits [7:0] to the following locations:
11908
11909  |28/24|23     19|18 16|15                    4|3     0|
11910  |  a  |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11911
11912  This function is used by VMOV/VMVN/VORR/VBIC.  */
11913
11914static void
11915neon_write_immbits (unsigned immbits)
11916{
11917  inst.instruction |= immbits & 0xf;
11918  inst.instruction |= ((immbits >> 4) & 0x7) << 16;
11919  inst.instruction |= ((immbits >> 7) & 0x1) << 24;
11920}
11921
11922/* Invert low-order SIZE bits of XHI:XLO.  */
11923
11924static void
11925neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
11926{
11927  unsigned immlo = xlo ? *xlo : 0;
11928  unsigned immhi = xhi ? *xhi : 0;
11929
11930  switch (size)
11931    {
11932    case 8:
11933      immlo = (~immlo) & 0xff;
11934      break;
11935
11936    case 16:
11937      immlo = (~immlo) & 0xffff;
11938      break;
11939
11940    case 64:
11941      immhi = (~immhi) & 0xffffffff;
11942      /* fall through.  */
11943
11944    case 32:
11945      immlo = (~immlo) & 0xffffffff;
11946      break;
11947
11948    default:
11949      abort ();
11950    }
11951
11952  if (xlo)
11953    *xlo = immlo;
11954
11955  if (xhi)
11956    *xhi = immhi;
11957}
11958
11959static void
11960do_neon_logic (void)
11961{
11962  if (inst.operands[2].present && inst.operands[2].isreg)
11963    {
11964      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11965      neon_check_type (3, rs, N_IGNORE_TYPE);
11966      /* U bit and size field were set as part of the bitmask.  */
11967      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11968      neon_three_same (neon_quad (rs), 0, -1);
11969    }
11970  else
11971    {
11972      enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
11973      struct neon_type_el et = neon_check_type (2, rs,
11974        N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
11975      enum neon_opc opcode = inst.instruction & 0x0fffffff;
11976      unsigned immbits;
11977      int cmode;
11978
11979      if (et.type == NT_invtype)
11980        return;
11981
11982      inst.instruction = NEON_ENC_IMMED (inst.instruction);
11983
11984      immbits = inst.operands[1].imm;
11985      if (et.size == 64)
11986	{
11987	  /* .i64 is a pseudo-op, so the immediate must be a repeating
11988	     pattern.  */
11989	  if (immbits != (inst.operands[1].regisimm ?
11990			  inst.operands[1].reg : 0))
11991	    {
11992	      /* Set immbits to an invalid constant.  */
11993	      immbits = 0xdeadbeef;
11994	    }
11995	}
11996
11997      switch (opcode)
11998        {
11999        case N_MNEM_vbic:
12000          cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
12001          break;
12002
12003        case N_MNEM_vorr:
12004          cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
12005          break;
12006
12007        case N_MNEM_vand:
12008          /* Pseudo-instruction for VBIC.  */
12009          neon_invert_size (&immbits, 0, et.size);
12010          cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
12011          break;
12012
12013        case N_MNEM_vorn:
12014          /* Pseudo-instruction for VORR.  */
12015          neon_invert_size (&immbits, 0, et.size);
12016          cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
12017          break;
12018
12019        default:
12020          abort ();
12021        }
12022
12023      if (cmode == FAIL)
12024        return;
12025
12026      inst.instruction |= neon_quad (rs) << 6;
12027      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12028      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12029      inst.instruction |= cmode << 8;
12030      neon_write_immbits (immbits);
12031
12032      inst.instruction = neon_dp_fixup (inst.instruction);
12033    }
12034}
12035
12036static void
12037do_neon_bitfield (void)
12038{
12039  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12040  neon_check_type (3, rs, N_IGNORE_TYPE);
12041  neon_three_same (neon_quad (rs), 0, -1);
12042}
12043
12044static void
12045neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
12046                  unsigned destbits)
12047{
12048  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12049  struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
12050                                            types | N_KEY);
12051  if (et.type == NT_float)
12052    {
12053      inst.instruction = NEON_ENC_FLOAT (inst.instruction);
12054      neon_three_same (neon_quad (rs), 0, -1);
12055    }
12056  else
12057    {
12058      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12059      neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
12060    }
12061}
12062
12063static void
12064do_neon_dyadic_if_su (void)
12065{
12066  neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
12067}
12068
12069static void
12070do_neon_dyadic_if_su_d (void)
12071{
12072  /* This version only allow D registers, but that constraint is enforced during
12073     operand parsing so we don't need to do anything extra here.  */
12074  neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
12075}
12076
12077static void
12078do_neon_dyadic_if_i_d (void)
12079{
12080  /* The "untyped" case can't happen. Do this to stop the "U" bit being
12081     affected if we specify unsigned args.  */
12082  neon_dyadic_misc (NT_untyped, N_IF_32, 0);
12083}
12084
12085enum vfp_or_neon_is_neon_bits
12086{
12087  NEON_CHECK_CC = 1,
12088  NEON_CHECK_ARCH = 2
12089};
12090
12091/* Call this function if an instruction which may have belonged to the VFP or
12092   Neon instruction sets, but turned out to be a Neon instruction (due to the
12093   operand types involved, etc.). We have to check and/or fix-up a couple of
12094   things:
12095
12096     - Make sure the user hasn't attempted to make a Neon instruction
12097       conditional.
12098     - Alter the value in the condition code field if necessary.
12099     - Make sure that the arch supports Neon instructions.
12100
12101   Which of these operations take place depends on bits from enum
12102   vfp_or_neon_is_neon_bits.
12103
12104   WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12105   current instruction's condition is COND_ALWAYS, the condition field is
12106   changed to inst.uncond_value. This is necessary because instructions shared
12107   between VFP and Neon may be conditional for the VFP variants only, and the
12108   unconditional Neon version must have, e.g., 0xF in the condition field.  */
12109
12110static int
12111vfp_or_neon_is_neon (unsigned check)
12112{
12113  /* Conditions are always legal in Thumb mode (IT blocks).  */
12114  if (!thumb_mode && (check & NEON_CHECK_CC))
12115    {
12116      if (inst.cond != COND_ALWAYS)
12117        {
12118          first_error (_(BAD_COND));
12119          return FAIL;
12120        }
12121      if (inst.uncond_value != -1)
12122        inst.instruction |= inst.uncond_value << 28;
12123    }
12124
12125  if ((check & NEON_CHECK_ARCH)
12126      && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
12127    {
12128      first_error (_(BAD_FPU));
12129      return FAIL;
12130    }
12131
12132  return SUCCESS;
12133}
12134
12135static void
12136do_neon_addsub_if_i (void)
12137{
12138  if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
12139    return;
12140
12141  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12142    return;
12143
12144  /* The "untyped" case can't happen. Do this to stop the "U" bit being
12145     affected if we specify unsigned args.  */
12146  neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
12147}
12148
12149/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12150   result to be:
12151     V<op> A,B     (A is operand 0, B is operand 2)
12152   to mean:
12153     V<op> A,B,A
12154   not:
12155     V<op> A,B,B
12156   so handle that case specially.  */
12157
12158static void
12159neon_exchange_operands (void)
12160{
12161  void *scratch = alloca (sizeof (inst.operands[0]));
12162  if (inst.operands[1].present)
12163    {
12164      /* Swap operands[1] and operands[2].  */
12165      memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
12166      inst.operands[1] = inst.operands[2];
12167      memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
12168    }
12169  else
12170    {
12171      inst.operands[1] = inst.operands[2];
12172      inst.operands[2] = inst.operands[0];
12173    }
12174}
12175
12176static void
12177neon_compare (unsigned regtypes, unsigned immtypes, int invert)
12178{
12179  if (inst.operands[2].isreg)
12180    {
12181      if (invert)
12182        neon_exchange_operands ();
12183      neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
12184    }
12185  else
12186    {
12187      enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12188      struct neon_type_el et = neon_check_type (2, rs,
12189        N_EQK | N_SIZ, immtypes | N_KEY);
12190
12191      inst.instruction = NEON_ENC_IMMED (inst.instruction);
12192      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12193      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12194      inst.instruction |= LOW4 (inst.operands[1].reg);
12195      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12196      inst.instruction |= neon_quad (rs) << 6;
12197      inst.instruction |= (et.type == NT_float) << 10;
12198      inst.instruction |= neon_logbits (et.size) << 18;
12199
12200      inst.instruction = neon_dp_fixup (inst.instruction);
12201    }
12202}
12203
12204static void
12205do_neon_cmp (void)
12206{
12207  neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
12208}
12209
12210static void
12211do_neon_cmp_inv (void)
12212{
12213  neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
12214}
12215
12216static void
12217do_neon_ceq (void)
12218{
12219  neon_compare (N_IF_32, N_IF_32, FALSE);
12220}
12221
12222/* For multiply instructions, we have the possibility of 16-bit or 32-bit
12223   scalars, which are encoded in 5 bits, M : Rm.
12224   For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12225   M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12226   index in M.  */
12227
12228static unsigned
12229neon_scalar_for_mul (unsigned scalar, unsigned elsize)
12230{
12231  unsigned regno = NEON_SCALAR_REG (scalar);
12232  unsigned elno = NEON_SCALAR_INDEX (scalar);
12233
12234  switch (elsize)
12235    {
12236    case 16:
12237      if (regno > 7 || elno > 3)
12238        goto bad_scalar;
12239      return regno | (elno << 3);
12240
12241    case 32:
12242      if (regno > 15 || elno > 1)
12243        goto bad_scalar;
12244      return regno | (elno << 4);
12245
12246    default:
12247    bad_scalar:
12248      first_error (_("scalar out of range for multiply instruction"));
12249    }
12250
12251  return 0;
12252}
12253
12254/* Encode multiply / multiply-accumulate scalar instructions.  */
12255
12256static void
12257neon_mul_mac (struct neon_type_el et, int ubit)
12258{
12259  unsigned scalar;
12260
12261  /* Give a more helpful error message if we have an invalid type.  */
12262  if (et.type == NT_invtype)
12263    return;
12264
12265  scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
12266  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12267  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12268  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12269  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12270  inst.instruction |= LOW4 (scalar);
12271  inst.instruction |= HI1 (scalar) << 5;
12272  inst.instruction |= (et.type == NT_float) << 8;
12273  inst.instruction |= neon_logbits (et.size) << 20;
12274  inst.instruction |= (ubit != 0) << 24;
12275
12276  inst.instruction = neon_dp_fixup (inst.instruction);
12277}
12278
12279static void
12280do_neon_mac_maybe_scalar (void)
12281{
12282  if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
12283    return;
12284
12285  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12286    return;
12287
12288  if (inst.operands[2].isscalar)
12289    {
12290      enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
12291      struct neon_type_el et = neon_check_type (3, rs,
12292        N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
12293      inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12294      neon_mul_mac (et, neon_quad (rs));
12295    }
12296  else
12297    {
12298      /* The "untyped" case can't happen.  Do this to stop the "U" bit being
12299	 affected if we specify unsigned args.  */
12300      neon_dyadic_misc (NT_untyped, N_IF_32, 0);
12301    }
12302}
12303
12304static void
12305do_neon_tst (void)
12306{
12307  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12308  struct neon_type_el et = neon_check_type (3, rs,
12309    N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
12310  neon_three_same (neon_quad (rs), 0, et.size);
12311}
12312
12313/* VMUL with 3 registers allows the P8 type. The scalar version supports the
12314   same types as the MAC equivalents. The polynomial type for this instruction
12315   is encoded the same as the integer type.  */
12316
12317static void
12318do_neon_mul (void)
12319{
12320  if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
12321    return;
12322
12323  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12324    return;
12325
12326  if (inst.operands[2].isscalar)
12327    do_neon_mac_maybe_scalar ();
12328  else
12329    neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
12330}
12331
12332static void
12333do_neon_qdmulh (void)
12334{
12335  if (inst.operands[2].isscalar)
12336    {
12337      enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
12338      struct neon_type_el et = neon_check_type (3, rs,
12339        N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
12340      inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12341      neon_mul_mac (et, neon_quad (rs));
12342    }
12343  else
12344    {
12345      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12346      struct neon_type_el et = neon_check_type (3, rs,
12347        N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
12348      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12349      /* The U bit (rounding) comes from bit mask.  */
12350      neon_three_same (neon_quad (rs), 0, et.size);
12351    }
12352}
12353
12354static void
12355do_neon_fcmp_absolute (void)
12356{
12357  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12358  neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
12359  /* Size field comes from bit mask.  */
12360  neon_three_same (neon_quad (rs), 1, -1);
12361}
12362
12363static void
12364do_neon_fcmp_absolute_inv (void)
12365{
12366  neon_exchange_operands ();
12367  do_neon_fcmp_absolute ();
12368}
12369
12370static void
12371do_neon_step (void)
12372{
12373  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12374  neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
12375  neon_three_same (neon_quad (rs), 0, -1);
12376}
12377
12378static void
12379do_neon_abs_neg (void)
12380{
12381  enum neon_shape rs;
12382  struct neon_type_el et;
12383
12384  if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
12385    return;
12386
12387  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12388    return;
12389
12390  rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12391  et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
12392
12393  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12394  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12395  inst.instruction |= LOW4 (inst.operands[1].reg);
12396  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12397  inst.instruction |= neon_quad (rs) << 6;
12398  inst.instruction |= (et.type == NT_float) << 10;
12399  inst.instruction |= neon_logbits (et.size) << 18;
12400
12401  inst.instruction = neon_dp_fixup (inst.instruction);
12402}
12403
12404static void
12405do_neon_sli (void)
12406{
12407  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12408  struct neon_type_el et = neon_check_type (2, rs,
12409    N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12410  int imm = inst.operands[2].imm;
12411  constraint (imm < 0 || (unsigned)imm >= et.size,
12412              _("immediate out of range for insert"));
12413  neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
12414}
12415
12416static void
12417do_neon_sri (void)
12418{
12419  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12420  struct neon_type_el et = neon_check_type (2, rs,
12421    N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12422  int imm = inst.operands[2].imm;
12423  constraint (imm < 1 || (unsigned)imm > et.size,
12424              _("immediate out of range for insert"));
12425  neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
12426}
12427
12428static void
12429do_neon_qshlu_imm (void)
12430{
12431  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12432  struct neon_type_el et = neon_check_type (2, rs,
12433    N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
12434  int imm = inst.operands[2].imm;
12435  constraint (imm < 0 || (unsigned)imm >= et.size,
12436              _("immediate out of range for shift"));
12437  /* Only encodes the 'U present' variant of the instruction.
12438     In this case, signed types have OP (bit 8) set to 0.
12439     Unsigned types have OP set to 1.  */
12440  inst.instruction |= (et.type == NT_unsigned) << 8;
12441  /* The rest of the bits are the same as other immediate shifts.  */
12442  neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
12443}
12444
12445static void
12446do_neon_qmovn (void)
12447{
12448  struct neon_type_el et = neon_check_type (2, NS_DQ,
12449    N_EQK | N_HLF, N_SU_16_64 | N_KEY);
12450  /* Saturating move where operands can be signed or unsigned, and the
12451     destination has the same signedness.  */
12452  inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12453  if (et.type == NT_unsigned)
12454    inst.instruction |= 0xc0;
12455  else
12456    inst.instruction |= 0x80;
12457  neon_two_same (0, 1, et.size / 2);
12458}
12459
12460static void
12461do_neon_qmovun (void)
12462{
12463  struct neon_type_el et = neon_check_type (2, NS_DQ,
12464    N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
12465  /* Saturating move with unsigned results. Operands must be signed.  */
12466  inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12467  neon_two_same (0, 1, et.size / 2);
12468}
12469
12470static void
12471do_neon_rshift_sat_narrow (void)
12472{
12473  /* FIXME: Types for narrowing. If operands are signed, results can be signed
12474     or unsigned. If operands are unsigned, results must also be unsigned.  */
12475  struct neon_type_el et = neon_check_type (2, NS_DQI,
12476    N_EQK | N_HLF, N_SU_16_64 | N_KEY);
12477  int imm = inst.operands[2].imm;
12478  /* This gets the bounds check, size encoding and immediate bits calculation
12479     right.  */
12480  et.size /= 2;
12481
12482  /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12483     VQMOVN.I<size> <Dd>, <Qm>.  */
12484  if (imm == 0)
12485    {
12486      inst.operands[2].present = 0;
12487      inst.instruction = N_MNEM_vqmovn;
12488      do_neon_qmovn ();
12489      return;
12490    }
12491
12492  constraint (imm < 1 || (unsigned)imm > et.size,
12493              _("immediate out of range"));
12494  neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
12495}
12496
12497static void
12498do_neon_rshift_sat_narrow_u (void)
12499{
12500  /* FIXME: Types for narrowing. If operands are signed, results can be signed
12501     or unsigned. If operands are unsigned, results must also be unsigned.  */
12502  struct neon_type_el et = neon_check_type (2, NS_DQI,
12503    N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
12504  int imm = inst.operands[2].imm;
12505  /* This gets the bounds check, size encoding and immediate bits calculation
12506     right.  */
12507  et.size /= 2;
12508
12509  /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12510     VQMOVUN.I<size> <Dd>, <Qm>.  */
12511  if (imm == 0)
12512    {
12513      inst.operands[2].present = 0;
12514      inst.instruction = N_MNEM_vqmovun;
12515      do_neon_qmovun ();
12516      return;
12517    }
12518
12519  constraint (imm < 1 || (unsigned)imm > et.size,
12520              _("immediate out of range"));
12521  /* FIXME: The manual is kind of unclear about what value U should have in
12522     VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12523     must be 1.  */
12524  neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
12525}
12526
12527static void
12528do_neon_movn (void)
12529{
12530  struct neon_type_el et = neon_check_type (2, NS_DQ,
12531    N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
12532  inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12533  neon_two_same (0, 1, et.size / 2);
12534}
12535
12536static void
12537do_neon_rshift_narrow (void)
12538{
12539  struct neon_type_el et = neon_check_type (2, NS_DQI,
12540    N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
12541  int imm = inst.operands[2].imm;
12542  /* This gets the bounds check, size encoding and immediate bits calculation
12543     right.  */
12544  et.size /= 2;
12545
12546  /* If immediate is zero then we are a pseudo-instruction for
12547     VMOVN.I<size> <Dd>, <Qm>  */
12548  if (imm == 0)
12549    {
12550      inst.operands[2].present = 0;
12551      inst.instruction = N_MNEM_vmovn;
12552      do_neon_movn ();
12553      return;
12554    }
12555
12556  constraint (imm < 1 || (unsigned)imm > et.size,
12557              _("immediate out of range for narrowing operation"));
12558  neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
12559}
12560
12561static void
12562do_neon_shll (void)
12563{
12564  /* FIXME: Type checking when lengthening.  */
12565  struct neon_type_el et = neon_check_type (2, NS_QDI,
12566    N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
12567  unsigned imm = inst.operands[2].imm;
12568
12569  if (imm == et.size)
12570    {
12571      /* Maximum shift variant.  */
12572      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12573      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12574      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12575      inst.instruction |= LOW4 (inst.operands[1].reg);
12576      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12577      inst.instruction |= neon_logbits (et.size) << 18;
12578
12579      inst.instruction = neon_dp_fixup (inst.instruction);
12580    }
12581  else
12582    {
12583      /* A more-specific type check for non-max versions.  */
12584      et = neon_check_type (2, NS_QDI,
12585        N_EQK | N_DBL, N_SU_32 | N_KEY);
12586      inst.instruction = NEON_ENC_IMMED (inst.instruction);
12587      neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
12588    }
12589}
12590
12591/* Check the various types for the VCVT instruction, and return which version
12592   the current instruction is.  */
12593
12594static int
12595neon_cvt_flavour (enum neon_shape rs)
12596{
12597#define CVT_VAR(C,X,Y)							\
12598  et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y));	\
12599  if (et.type != NT_invtype)						\
12600    {									\
12601      inst.error = NULL;						\
12602      return (C);							\
12603    }
12604  struct neon_type_el et;
12605  unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
12606                        || rs == NS_FF) ? N_VFP : 0;
12607  /* The instruction versions which take an immediate take one register
12608     argument, which is extended to the width of the full register. Thus the
12609     "source" and "destination" registers must have the same width.  Hack that
12610     here by making the size equal to the key (wider, in this case) operand.  */
12611  unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
12612
12613  CVT_VAR (0, N_S32, N_F32);
12614  CVT_VAR (1, N_U32, N_F32);
12615  CVT_VAR (2, N_F32, N_S32);
12616  CVT_VAR (3, N_F32, N_U32);
12617
12618  whole_reg = N_VFP;
12619
12620  /* VFP instructions.  */
12621  CVT_VAR (4, N_F32, N_F64);
12622  CVT_VAR (5, N_F64, N_F32);
12623  CVT_VAR (6, N_S32, N_F64 | key);
12624  CVT_VAR (7, N_U32, N_F64 | key);
12625  CVT_VAR (8, N_F64 | key, N_S32);
12626  CVT_VAR (9, N_F64 | key, N_U32);
12627  /* VFP instructions with bitshift.  */
12628  CVT_VAR (10, N_F32 | key, N_S16);
12629  CVT_VAR (11, N_F32 | key, N_U16);
12630  CVT_VAR (12, N_F64 | key, N_S16);
12631  CVT_VAR (13, N_F64 | key, N_U16);
12632  CVT_VAR (14, N_S16, N_F32 | key);
12633  CVT_VAR (15, N_U16, N_F32 | key);
12634  CVT_VAR (16, N_S16, N_F64 | key);
12635  CVT_VAR (17, N_U16, N_F64 | key);
12636
12637  return -1;
12638#undef CVT_VAR
12639}
12640
12641/* Neon-syntax VFP conversions.  */
12642
12643static void
12644do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
12645{
12646  const char *opname = 0;
12647
12648  if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
12649    {
12650      /* Conversions with immediate bitshift.  */
12651      const char *enc[] =
12652        {
12653          "ftosls",
12654          "ftouls",
12655          "fsltos",
12656          "fultos",
12657          NULL,
12658          NULL,
12659          "ftosld",
12660          "ftould",
12661          "fsltod",
12662          "fultod",
12663          "fshtos",
12664          "fuhtos",
12665          "fshtod",
12666          "fuhtod",
12667          "ftoshs",
12668          "ftouhs",
12669          "ftoshd",
12670          "ftouhd"
12671        };
12672
12673      if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
12674        {
12675          opname = enc[flavour];
12676          constraint (inst.operands[0].reg != inst.operands[1].reg,
12677                      _("operands 0 and 1 must be the same register"));
12678          inst.operands[1] = inst.operands[2];
12679          memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
12680        }
12681    }
12682  else
12683    {
12684      /* Conversions without bitshift.  */
12685      const char *enc[] =
12686        {
12687          "ftosizs",
12688          "ftouizs",
12689          "fsitos",
12690          "fuitos",
12691          "fcvtsd",
12692          "fcvtds",
12693          "ftosizd",
12694          "ftouizd",
12695          "fsitod",
12696          "fuitod"
12697        };
12698
12699      if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
12700        opname = enc[flavour];
12701    }
12702
12703  if (opname)
12704    do_vfp_nsyn_opcode (opname);
12705}
12706
12707static void
12708do_vfp_nsyn_cvtz (void)
12709{
12710  enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
12711  int flavour = neon_cvt_flavour (rs);
12712  const char *enc[] =
12713    {
12714      "ftosizs",
12715      "ftouizs",
12716      NULL,
12717      NULL,
12718      NULL,
12719      NULL,
12720      "ftosizd",
12721      "ftouizd"
12722    };
12723
12724  if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
12725    do_vfp_nsyn_opcode (enc[flavour]);
12726}
12727
12728static void
12729do_neon_cvt (void)
12730{
12731  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
12732    NS_FD, NS_DF, NS_FF, NS_NULL);
12733  int flavour = neon_cvt_flavour (rs);
12734
12735  /* VFP rather than Neon conversions.  */
12736  if (flavour >= 4)
12737    {
12738      do_vfp_nsyn_cvt (rs, flavour);
12739      return;
12740    }
12741
12742  switch (rs)
12743    {
12744    case NS_DDI:
12745    case NS_QQI:
12746      {
12747        if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12748          return;
12749
12750        /* Fixed-point conversion with #0 immediate is encoded as an
12751           integer conversion.  */
12752        if (inst.operands[2].present && inst.operands[2].imm == 0)
12753          goto int_encode;
12754        unsigned immbits = 32 - inst.operands[2].imm;
12755        unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12756        inst.instruction = NEON_ENC_IMMED (inst.instruction);
12757        if (flavour != -1)
12758          inst.instruction |= enctab[flavour];
12759        inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12760        inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12761        inst.instruction |= LOW4 (inst.operands[1].reg);
12762        inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12763        inst.instruction |= neon_quad (rs) << 6;
12764        inst.instruction |= 1 << 21;
12765        inst.instruction |= immbits << 16;
12766
12767        inst.instruction = neon_dp_fixup (inst.instruction);
12768      }
12769      break;
12770
12771    case NS_DD:
12772    case NS_QQ:
12773    int_encode:
12774      {
12775        unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
12776
12777        inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12778
12779        if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12780          return;
12781
12782        if (flavour != -1)
12783          inst.instruction |= enctab[flavour];
12784
12785        inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12786        inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12787        inst.instruction |= LOW4 (inst.operands[1].reg);
12788        inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12789        inst.instruction |= neon_quad (rs) << 6;
12790        inst.instruction |= 2 << 18;
12791
12792        inst.instruction = neon_dp_fixup (inst.instruction);
12793      }
12794    break;
12795
12796    default:
12797      /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32).  */
12798      do_vfp_nsyn_cvt (rs, flavour);
12799    }
12800}
12801
12802static void
12803neon_move_immediate (void)
12804{
12805  enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
12806  struct neon_type_el et = neon_check_type (2, rs,
12807    N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
12808  unsigned immlo, immhi = 0, immbits;
12809  int op, cmode, float_p;
12810
12811  constraint (et.type == NT_invtype,
12812              _("operand size must be specified for immediate VMOV"));
12813
12814  /* We start out as an MVN instruction if OP = 1, MOV otherwise.  */
12815  op = (inst.instruction & (1 << 5)) != 0;
12816
12817  immlo = inst.operands[1].imm;
12818  if (inst.operands[1].regisimm)
12819    immhi = inst.operands[1].reg;
12820
12821  constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
12822              _("immediate has bits set outside the operand size"));
12823
12824  float_p = inst.operands[1].immisfloat;
12825
12826  if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
12827                                        et.size, et.type)) == FAIL)
12828    {
12829      /* Invert relevant bits only.  */
12830      neon_invert_size (&immlo, &immhi, et.size);
12831      /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12832         with one or the other; those cases are caught by
12833         neon_cmode_for_move_imm.  */
12834      op = !op;
12835      if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
12836					    &op, et.size, et.type)) == FAIL)
12837        {
12838          first_error (_("immediate out of range"));
12839          return;
12840        }
12841    }
12842
12843  inst.instruction &= ~(1 << 5);
12844  inst.instruction |= op << 5;
12845
12846  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12847  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12848  inst.instruction |= neon_quad (rs) << 6;
12849  inst.instruction |= cmode << 8;
12850
12851  neon_write_immbits (immbits);
12852}
12853
12854static void
12855do_neon_mvn (void)
12856{
12857  if (inst.operands[1].isreg)
12858    {
12859      enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12860
12861      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12862      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12863      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12864      inst.instruction |= LOW4 (inst.operands[1].reg);
12865      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12866      inst.instruction |= neon_quad (rs) << 6;
12867    }
12868  else
12869    {
12870      inst.instruction = NEON_ENC_IMMED (inst.instruction);
12871      neon_move_immediate ();
12872    }
12873
12874  inst.instruction = neon_dp_fixup (inst.instruction);
12875}
12876
12877/* Encode instructions of form:
12878
12879  |28/24|23|22|21 20|19 16|15 12|11    8|7|6|5|4|3  0|
12880  |  U  |x |D |size | Rn  | Rd  |x x x x|N|x|M|x| Rm |
12881
12882*/
12883
12884static void
12885neon_mixed_length (struct neon_type_el et, unsigned size)
12886{
12887  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12888  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12889  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12890  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12891  inst.instruction |= LOW4 (inst.operands[2].reg);
12892  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
12893  inst.instruction |= (et.type == NT_unsigned) << 24;
12894  inst.instruction |= neon_logbits (size) << 20;
12895
12896  inst.instruction = neon_dp_fixup (inst.instruction);
12897}
12898
12899static void
12900do_neon_dyadic_long (void)
12901{
12902  /* FIXME: Type checking for lengthening op.  */
12903  struct neon_type_el et = neon_check_type (3, NS_QDD,
12904    N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
12905  neon_mixed_length (et, et.size);
12906}
12907
12908static void
12909do_neon_abal (void)
12910{
12911  struct neon_type_el et = neon_check_type (3, NS_QDD,
12912    N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
12913  neon_mixed_length (et, et.size);
12914}
12915
12916static void
12917neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
12918{
12919  if (inst.operands[2].isscalar)
12920    {
12921      struct neon_type_el et = neon_check_type (3, NS_QDS,
12922        N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
12923      inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12924      neon_mul_mac (et, et.type == NT_unsigned);
12925    }
12926  else
12927    {
12928      struct neon_type_el et = neon_check_type (3, NS_QDD,
12929        N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
12930      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12931      neon_mixed_length (et, et.size);
12932    }
12933}
12934
12935static void
12936do_neon_mac_maybe_scalar_long (void)
12937{
12938  neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
12939}
12940
12941static void
12942do_neon_dyadic_wide (void)
12943{
12944  struct neon_type_el et = neon_check_type (3, NS_QQD,
12945    N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
12946  neon_mixed_length (et, et.size);
12947}
12948
12949static void
12950do_neon_dyadic_narrow (void)
12951{
12952  struct neon_type_el et = neon_check_type (3, NS_QDD,
12953    N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
12954  /* Operand sign is unimportant, and the U bit is part of the opcode,
12955     so force the operand type to integer.  */
12956  et.type = NT_integer;
12957  neon_mixed_length (et, et.size / 2);
12958}
12959
12960static void
12961do_neon_mul_sat_scalar_long (void)
12962{
12963  neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
12964}
12965
12966static void
12967do_neon_vmull (void)
12968{
12969  if (inst.operands[2].isscalar)
12970    do_neon_mac_maybe_scalar_long ();
12971  else
12972    {
12973      struct neon_type_el et = neon_check_type (3, NS_QDD,
12974        N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
12975      if (et.type == NT_poly)
12976        inst.instruction = NEON_ENC_POLY (inst.instruction);
12977      else
12978        inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12979      /* For polynomial encoding, size field must be 0b00 and the U bit must be
12980         zero. Should be OK as-is.  */
12981      neon_mixed_length (et, et.size);
12982    }
12983}
12984
12985static void
12986do_neon_ext (void)
12987{
12988  enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
12989  struct neon_type_el et = neon_check_type (3, rs,
12990    N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12991  unsigned imm = (inst.operands[3].imm * et.size) / 8;
12992  constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range"));
12993  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12994  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12995  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12996  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12997  inst.instruction |= LOW4 (inst.operands[2].reg);
12998  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
12999  inst.instruction |= neon_quad (rs) << 6;
13000  inst.instruction |= imm << 8;
13001
13002  inst.instruction = neon_dp_fixup (inst.instruction);
13003}
13004
13005static void
13006do_neon_rev (void)
13007{
13008  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13009  struct neon_type_el et = neon_check_type (2, rs,
13010    N_EQK, N_8 | N_16 | N_32 | N_KEY);
13011  unsigned op = (inst.instruction >> 7) & 3;
13012  /* N (width of reversed regions) is encoded as part of the bitmask. We
13013     extract it here to check the elements to be reversed are smaller.
13014     Otherwise we'd get a reserved instruction.  */
13015  unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
13016  assert (elsize != 0);
13017  constraint (et.size >= elsize,
13018              _("elements must be smaller than reversal region"));
13019  neon_two_same (neon_quad (rs), 1, et.size);
13020}
13021
13022static void
13023do_neon_dup (void)
13024{
13025  if (inst.operands[1].isscalar)
13026    {
13027      enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
13028      struct neon_type_el et = neon_check_type (2, rs,
13029        N_EQK, N_8 | N_16 | N_32 | N_KEY);
13030      unsigned sizebits = et.size >> 3;
13031      unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
13032      int logsize = neon_logbits (et.size);
13033      unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
13034
13035      if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
13036        return;
13037
13038      inst.instruction = NEON_ENC_SCALAR (inst.instruction);
13039      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13040      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13041      inst.instruction |= LOW4 (dm);
13042      inst.instruction |= HI1 (dm) << 5;
13043      inst.instruction |= neon_quad (rs) << 6;
13044      inst.instruction |= x << 17;
13045      inst.instruction |= sizebits << 16;
13046
13047      inst.instruction = neon_dp_fixup (inst.instruction);
13048    }
13049  else
13050    {
13051      enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
13052      struct neon_type_el et = neon_check_type (2, rs,
13053        N_8 | N_16 | N_32 | N_KEY, N_EQK);
13054      /* Duplicate ARM register to lanes of vector.  */
13055      inst.instruction = NEON_ENC_ARMREG (inst.instruction);
13056      switch (et.size)
13057        {
13058        case 8:  inst.instruction |= 0x400000; break;
13059        case 16: inst.instruction |= 0x000020; break;
13060        case 32: inst.instruction |= 0x000000; break;
13061        default: break;
13062        }
13063      inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
13064      inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
13065      inst.instruction |= HI1 (inst.operands[0].reg) << 7;
13066      inst.instruction |= neon_quad (rs) << 21;
13067      /* The encoding for this instruction is identical for the ARM and Thumb
13068         variants, except for the condition field.  */
13069      do_vfp_cond_or_thumb ();
13070    }
13071}
13072
13073/* VMOV has particularly many variations. It can be one of:
13074     0. VMOV<c><q> <Qd>, <Qm>
13075     1. VMOV<c><q> <Dd>, <Dm>
13076   (Register operations, which are VORR with Rm = Rn.)
13077     2. VMOV<c><q>.<dt> <Qd>, #<imm>
13078     3. VMOV<c><q>.<dt> <Dd>, #<imm>
13079   (Immediate loads.)
13080     4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13081   (ARM register to scalar.)
13082     5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13083   (Two ARM registers to vector.)
13084     6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13085   (Scalar to ARM register.)
13086     7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13087   (Vector to two ARM registers.)
13088     8. VMOV.F32 <Sd>, <Sm>
13089     9. VMOV.F64 <Dd>, <Dm>
13090   (VFP register moves.)
13091    10. VMOV.F32 <Sd>, #imm
13092    11. VMOV.F64 <Dd>, #imm
13093   (VFP float immediate load.)
13094    12. VMOV <Rd>, <Sm>
13095   (VFP single to ARM reg.)
13096    13. VMOV <Sd>, <Rm>
13097   (ARM reg to VFP single.)
13098    14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13099   (Two ARM regs to two VFP singles.)
13100    15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13101   (Two VFP singles to two ARM regs.)
13102
13103   These cases can be disambiguated using neon_select_shape, except cases 1/9
13104   and 3/11 which depend on the operand type too.
13105
13106   All the encoded bits are hardcoded by this function.
13107
13108   Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13109   Cases 5, 7 may be used with VFPv2 and above.
13110
13111   FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13112   can specify a type where it doesn't make sense to, and is ignored).
13113*/
13114
13115static void
13116do_neon_mov (void)
13117{
13118  enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
13119    NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
13120    NS_NULL);
13121  struct neon_type_el et;
13122  const char *ldconst = 0;
13123
13124  switch (rs)
13125    {
13126    case NS_DD:  /* case 1/9.  */
13127      et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
13128      /* It is not an error here if no type is given.  */
13129      inst.error = NULL;
13130      if (et.type == NT_float && et.size == 64)
13131        {
13132          do_vfp_nsyn_opcode ("fcpyd");
13133          break;
13134        }
13135      /* fall through.  */
13136
13137    case NS_QQ:  /* case 0/1.  */
13138      {
13139        if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13140          return;
13141        /* The architecture manual I have doesn't explicitly state which
13142           value the U bit should have for register->register moves, but
13143           the equivalent VORR instruction has U = 0, so do that.  */
13144        inst.instruction = 0x0200110;
13145        inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13146        inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13147        inst.instruction |= LOW4 (inst.operands[1].reg);
13148        inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13149        inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13150        inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13151        inst.instruction |= neon_quad (rs) << 6;
13152
13153        inst.instruction = neon_dp_fixup (inst.instruction);
13154      }
13155      break;
13156
13157    case NS_DI:  /* case 3/11.  */
13158      et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
13159      inst.error = NULL;
13160      if (et.type == NT_float && et.size == 64)
13161        {
13162          /* case 11 (fconstd).  */
13163          ldconst = "fconstd";
13164          goto encode_fconstd;
13165        }
13166      /* fall through.  */
13167
13168    case NS_QI:  /* case 2/3.  */
13169      if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13170        return;
13171      inst.instruction = 0x0800010;
13172      neon_move_immediate ();
13173      inst.instruction = neon_dp_fixup (inst.instruction);
13174      break;
13175
13176    case NS_SR:  /* case 4.  */
13177      {
13178        unsigned bcdebits = 0;
13179        struct neon_type_el et = neon_check_type (2, NS_NULL,
13180          N_8 | N_16 | N_32 | N_KEY, N_EQK);
13181        int logsize = neon_logbits (et.size);
13182        unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
13183        unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
13184
13185        constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
13186                    _(BAD_FPU));
13187        constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
13188                    && et.size != 32, _(BAD_FPU));
13189        constraint (et.type == NT_invtype, _("bad type for scalar"));
13190        constraint (x >= 64 / et.size, _("scalar index out of range"));
13191
13192        switch (et.size)
13193          {
13194          case 8:  bcdebits = 0x8; break;
13195          case 16: bcdebits = 0x1; break;
13196          case 32: bcdebits = 0x0; break;
13197          default: ;
13198          }
13199
13200        bcdebits |= x << logsize;
13201
13202        inst.instruction = 0xe000b10;
13203        do_vfp_cond_or_thumb ();
13204        inst.instruction |= LOW4 (dn) << 16;
13205        inst.instruction |= HI1 (dn) << 7;
13206        inst.instruction |= inst.operands[1].reg << 12;
13207        inst.instruction |= (bcdebits & 3) << 5;
13208        inst.instruction |= (bcdebits >> 2) << 21;
13209      }
13210      break;
13211
13212    case NS_DRR:  /* case 5 (fmdrr).  */
13213      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
13214                  _(BAD_FPU));
13215
13216      inst.instruction = 0xc400b10;
13217      do_vfp_cond_or_thumb ();
13218      inst.instruction |= LOW4 (inst.operands[0].reg);
13219      inst.instruction |= HI1 (inst.operands[0].reg) << 5;
13220      inst.instruction |= inst.operands[1].reg << 12;
13221      inst.instruction |= inst.operands[2].reg << 16;
13222      break;
13223
13224    case NS_RS:  /* case 6.  */
13225      {
13226        struct neon_type_el et = neon_check_type (2, NS_NULL,
13227          N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
13228        unsigned logsize = neon_logbits (et.size);
13229        unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
13230        unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
13231        unsigned abcdebits = 0;
13232
13233        constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
13234                    _(BAD_FPU));
13235        constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
13236                    && et.size != 32, _(BAD_FPU));
13237        constraint (et.type == NT_invtype, _("bad type for scalar"));
13238        constraint (x >= 64 / et.size, _("scalar index out of range"));
13239
13240        switch (et.size)
13241          {
13242          case 8:  abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
13243          case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
13244          case 32: abcdebits = 0x00; break;
13245          default: ;
13246          }
13247
13248        abcdebits |= x << logsize;
13249        inst.instruction = 0xe100b10;
13250        do_vfp_cond_or_thumb ();
13251        inst.instruction |= LOW4 (dn) << 16;
13252        inst.instruction |= HI1 (dn) << 7;
13253        inst.instruction |= inst.operands[0].reg << 12;
13254        inst.instruction |= (abcdebits & 3) << 5;
13255        inst.instruction |= (abcdebits >> 2) << 21;
13256      }
13257      break;
13258
13259    case NS_RRD:  /* case 7 (fmrrd).  */
13260      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
13261                  _(BAD_FPU));
13262
13263      inst.instruction = 0xc500b10;
13264      do_vfp_cond_or_thumb ();
13265      inst.instruction |= inst.operands[0].reg << 12;
13266      inst.instruction |= inst.operands[1].reg << 16;
13267      inst.instruction |= LOW4 (inst.operands[2].reg);
13268      inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13269      break;
13270
13271    case NS_FF:  /* case 8 (fcpys).  */
13272      do_vfp_nsyn_opcode ("fcpys");
13273      break;
13274
13275    case NS_FI:  /* case 10 (fconsts).  */
13276      ldconst = "fconsts";
13277      encode_fconstd:
13278      if (is_quarter_float (inst.operands[1].imm))
13279        {
13280          inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
13281          do_vfp_nsyn_opcode (ldconst);
13282        }
13283      else
13284        first_error (_("immediate out of range"));
13285      break;
13286
13287    case NS_RF:  /* case 12 (fmrs).  */
13288      do_vfp_nsyn_opcode ("fmrs");
13289      break;
13290
13291    case NS_FR:  /* case 13 (fmsr).  */
13292      do_vfp_nsyn_opcode ("fmsr");
13293      break;
13294
13295    /* The encoders for the fmrrs and fmsrr instructions expect three operands
13296       (one of which is a list), but we have parsed four.  Do some fiddling to
13297       make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13298       expect.  */
13299    case NS_RRFF:  /* case 14 (fmrrs).  */
13300      constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
13301                  _("VFP registers must be adjacent"));
13302      inst.operands[2].imm = 2;
13303      memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
13304      do_vfp_nsyn_opcode ("fmrrs");
13305      break;
13306
13307    case NS_FFRR:  /* case 15 (fmsrr).  */
13308      constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
13309                  _("VFP registers must be adjacent"));
13310      inst.operands[1] = inst.operands[2];
13311      inst.operands[2] = inst.operands[3];
13312      inst.operands[0].imm = 2;
13313      memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
13314      do_vfp_nsyn_opcode ("fmsrr");
13315      break;
13316
13317    default:
13318      abort ();
13319    }
13320}
13321
13322static void
13323do_neon_rshift_round_imm (void)
13324{
13325  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13326  struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13327  int imm = inst.operands[2].imm;
13328
13329  /* imm == 0 case is encoded as VMOV for V{R}SHR.  */
13330  if (imm == 0)
13331    {
13332      inst.operands[2].present = 0;
13333      do_neon_mov ();
13334      return;
13335    }
13336
13337  constraint (imm < 1 || (unsigned)imm > et.size,
13338              _("immediate out of range for shift"));
13339  neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13340                  et.size - imm);
13341}
13342
13343static void
13344do_neon_movl (void)
13345{
13346  struct neon_type_el et = neon_check_type (2, NS_QD,
13347    N_EQK | N_DBL, N_SU_32 | N_KEY);
13348  unsigned sizebits = et.size >> 3;
13349  inst.instruction |= sizebits << 19;
13350  neon_two_same (0, et.type == NT_unsigned, -1);
13351}
13352
13353static void
13354do_neon_trn (void)
13355{
13356  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13357  struct neon_type_el et = neon_check_type (2, rs,
13358    N_EQK, N_8 | N_16 | N_32 | N_KEY);
13359  inst.instruction = NEON_ENC_INTEGER (inst.instruction);
13360  neon_two_same (neon_quad (rs), 1, et.size);
13361}
13362
13363static void
13364do_neon_zip_uzp (void)
13365{
13366  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13367  struct neon_type_el et = neon_check_type (2, rs,
13368    N_EQK, N_8 | N_16 | N_32 | N_KEY);
13369  if (rs == NS_DD && et.size == 32)
13370    {
13371      /* Special case: encode as VTRN.32 <Dd>, <Dm>.  */
13372      inst.instruction = N_MNEM_vtrn;
13373      do_neon_trn ();
13374      return;
13375    }
13376  neon_two_same (neon_quad (rs), 1, et.size);
13377}
13378
13379static void
13380do_neon_sat_abs_neg (void)
13381{
13382  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13383  struct neon_type_el et = neon_check_type (2, rs,
13384    N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
13385  neon_two_same (neon_quad (rs), 1, et.size);
13386}
13387
13388static void
13389do_neon_pair_long (void)
13390{
13391  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13392  struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
13393  /* Unsigned is encoded in OP field (bit 7) for these instruction.  */
13394  inst.instruction |= (et.type == NT_unsigned) << 7;
13395  neon_two_same (neon_quad (rs), 1, et.size);
13396}
13397
13398static void
13399do_neon_recip_est (void)
13400{
13401  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13402  struct neon_type_el et = neon_check_type (2, rs,
13403    N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
13404  inst.instruction |= (et.type == NT_float) << 8;
13405  neon_two_same (neon_quad (rs), 1, et.size);
13406}
13407
13408static void
13409do_neon_cls (void)
13410{
13411  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13412  struct neon_type_el et = neon_check_type (2, rs,
13413    N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
13414  neon_two_same (neon_quad (rs), 1, et.size);
13415}
13416
13417static void
13418do_neon_clz (void)
13419{
13420  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13421  struct neon_type_el et = neon_check_type (2, rs,
13422    N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
13423  neon_two_same (neon_quad (rs), 1, et.size);
13424}
13425
13426static void
13427do_neon_cnt (void)
13428{
13429  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13430  struct neon_type_el et = neon_check_type (2, rs,
13431    N_EQK | N_INT, N_8 | N_KEY);
13432  neon_two_same (neon_quad (rs), 1, et.size);
13433}
13434
13435static void
13436do_neon_swp (void)
13437{
13438  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13439  neon_two_same (neon_quad (rs), 1, -1);
13440}
13441
13442static void
13443do_neon_tbl_tbx (void)
13444{
13445  unsigned listlenbits;
13446  neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
13447
13448  if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
13449    {
13450      first_error (_("bad list length for table lookup"));
13451      return;
13452    }
13453
13454  listlenbits = inst.operands[1].imm - 1;
13455  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13456  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13457  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13458  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13459  inst.instruction |= LOW4 (inst.operands[2].reg);
13460  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13461  inst.instruction |= listlenbits << 8;
13462
13463  inst.instruction = neon_dp_fixup (inst.instruction);
13464}
13465
13466static void
13467do_neon_ldm_stm (void)
13468{
13469  /* P, U and L bits are part of bitmask.  */
13470  int is_dbmode = (inst.instruction & (1 << 24)) != 0;
13471  unsigned offsetbits = inst.operands[1].imm * 2;
13472
13473  if (inst.operands[1].issingle)
13474    {
13475      do_vfp_nsyn_ldm_stm (is_dbmode);
13476      return;
13477    }
13478
13479  constraint (is_dbmode && !inst.operands[0].writeback,
13480              _("writeback (!) must be used for VLDMDB and VSTMDB"));
13481
13482  constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
13483              _("register list must contain at least 1 and at most 16 "
13484                "registers"));
13485
13486  inst.instruction |= inst.operands[0].reg << 16;
13487  inst.instruction |= inst.operands[0].writeback << 21;
13488  inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
13489  inst.instruction |= HI1 (inst.operands[1].reg) << 22;
13490
13491  inst.instruction |= offsetbits;
13492
13493  do_vfp_cond_or_thumb ();
13494}
13495
13496static void
13497do_neon_ldr_str (void)
13498{
13499  int is_ldr = (inst.instruction & (1 << 20)) != 0;
13500
13501  if (inst.operands[0].issingle)
13502    {
13503      if (is_ldr)
13504        do_vfp_nsyn_opcode ("flds");
13505      else
13506        do_vfp_nsyn_opcode ("fsts");
13507    }
13508  else
13509    {
13510      if (is_ldr)
13511        do_vfp_nsyn_opcode ("fldd");
13512      else
13513        do_vfp_nsyn_opcode ("fstd");
13514    }
13515}
13516
13517/* "interleave" version also handles non-interleaving register VLD1/VST1
13518   instructions.  */
13519
13520static void
13521do_neon_ld_st_interleave (void)
13522{
13523  struct neon_type_el et = neon_check_type (1, NS_NULL,
13524                                            N_8 | N_16 | N_32 | N_64);
13525  unsigned alignbits = 0;
13526  unsigned idx;
13527  /* The bits in this table go:
13528     0: register stride of one (0) or two (1)
13529     1,2: register list length, minus one (1, 2, 3, 4).
13530     3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13531     We use -1 for invalid entries.  */
13532  const int typetable[] =
13533    {
13534      0x7,  -1, 0xa,  -1, 0x6,  -1, 0x2,  -1, /* VLD1 / VST1.  */
13535       -1,  -1, 0x8, 0x9,  -1,  -1, 0x3,  -1, /* VLD2 / VST2.  */
13536       -1,  -1,  -1,  -1, 0x4, 0x5,  -1,  -1, /* VLD3 / VST3.  */
13537       -1,  -1,  -1,  -1,  -1,  -1, 0x0, 0x1  /* VLD4 / VST4.  */
13538    };
13539  int typebits;
13540
13541  if (et.type == NT_invtype)
13542    return;
13543
13544  if (inst.operands[1].immisalign)
13545    switch (inst.operands[1].imm >> 8)
13546      {
13547      case 64: alignbits = 1; break;
13548      case 128:
13549        if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13550          goto bad_alignment;
13551        alignbits = 2;
13552        break;
13553      case 256:
13554        if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13555          goto bad_alignment;
13556        alignbits = 3;
13557        break;
13558      default:
13559      bad_alignment:
13560        first_error (_("bad alignment"));
13561        return;
13562      }
13563
13564  inst.instruction |= alignbits << 4;
13565  inst.instruction |= neon_logbits (et.size) << 6;
13566
13567  /* Bits [4:6] of the immediate in a list specifier encode register stride
13568     (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13569     VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13570     up the right value for "type" in a table based on this value and the given
13571     list style, then stick it back.  */
13572  idx = ((inst.operands[0].imm >> 4) & 7)
13573        | (((inst.instruction >> 8) & 3) << 3);
13574
13575  typebits = typetable[idx];
13576
13577  constraint (typebits == -1, _("bad list type for instruction"));
13578
13579  inst.instruction &= ~0xf00;
13580  inst.instruction |= typebits << 8;
13581}
13582
13583/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13584   *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13585   otherwise. The variable arguments are a list of pairs of legal (size, align)
13586   values, terminated with -1.  */
13587
13588static int
13589neon_alignment_bit (int size, int align, int *do_align, ...)
13590{
13591  va_list ap;
13592  int result = FAIL, thissize, thisalign;
13593
13594  if (!inst.operands[1].immisalign)
13595    {
13596      *do_align = 0;
13597      return SUCCESS;
13598    }
13599
13600  va_start (ap, do_align);
13601
13602  do
13603    {
13604      thissize = va_arg (ap, int);
13605      if (thissize == -1)
13606        break;
13607      thisalign = va_arg (ap, int);
13608
13609      if (size == thissize && align == thisalign)
13610        result = SUCCESS;
13611    }
13612  while (result != SUCCESS);
13613
13614  va_end (ap);
13615
13616  if (result == SUCCESS)
13617    *do_align = 1;
13618  else
13619    first_error (_("unsupported alignment for instruction"));
13620
13621  return result;
13622}
13623
13624static void
13625do_neon_ld_st_lane (void)
13626{
13627  struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
13628  int align_good, do_align = 0;
13629  int logsize = neon_logbits (et.size);
13630  int align = inst.operands[1].imm >> 8;
13631  int n = (inst.instruction >> 8) & 3;
13632  int max_el = 64 / et.size;
13633
13634  if (et.type == NT_invtype)
13635    return;
13636
13637  constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
13638              _("bad list length"));
13639  constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
13640              _("scalar index out of range"));
13641  constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
13642              && et.size == 8,
13643              _("stride of 2 unavailable when element size is 8"));
13644
13645  switch (n)
13646    {
13647    case 0:  /* VLD1 / VST1.  */
13648      align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
13649                                       32, 32, -1);
13650      if (align_good == FAIL)
13651        return;
13652      if (do_align)
13653        {
13654          unsigned alignbits = 0;
13655          switch (et.size)
13656            {
13657            case 16: alignbits = 0x1; break;
13658            case 32: alignbits = 0x3; break;
13659            default: ;
13660            }
13661          inst.instruction |= alignbits << 4;
13662        }
13663      break;
13664
13665    case 1:  /* VLD2 / VST2.  */
13666      align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
13667                                       32, 64, -1);
13668      if (align_good == FAIL)
13669        return;
13670      if (do_align)
13671        inst.instruction |= 1 << 4;
13672      break;
13673
13674    case 2:  /* VLD3 / VST3.  */
13675      constraint (inst.operands[1].immisalign,
13676                  _("can't use alignment with this instruction"));
13677      break;
13678
13679    case 3:  /* VLD4 / VST4.  */
13680      align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
13681                                       16, 64, 32, 64, 32, 128, -1);
13682      if (align_good == FAIL)
13683        return;
13684      if (do_align)
13685        {
13686          unsigned alignbits = 0;
13687          switch (et.size)
13688            {
13689            case 8:  alignbits = 0x1; break;
13690            case 16: alignbits = 0x1; break;
13691            case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
13692            default: ;
13693            }
13694          inst.instruction |= alignbits << 4;
13695        }
13696      break;
13697
13698    default: ;
13699    }
13700
13701  /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32.  */
13702  if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13703    inst.instruction |= 1 << (4 + logsize);
13704
13705  inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
13706  inst.instruction |= logsize << 10;
13707}
13708
13709/* Encode single n-element structure to all lanes VLD<n> instructions.  */
13710
13711static void
13712do_neon_ld_dup (void)
13713{
13714  struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
13715  int align_good, do_align = 0;
13716
13717  if (et.type == NT_invtype)
13718    return;
13719
13720  switch ((inst.instruction >> 8) & 3)
13721    {
13722    case 0:  /* VLD1.  */
13723      assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
13724      align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13725                                       &do_align, 16, 16, 32, 32, -1);
13726      if (align_good == FAIL)
13727        return;
13728      switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
13729        {
13730        case 1: break;
13731        case 2: inst.instruction |= 1 << 5; break;
13732        default: first_error (_("bad list length")); return;
13733        }
13734      inst.instruction |= neon_logbits (et.size) << 6;
13735      break;
13736
13737    case 1:  /* VLD2.  */
13738      align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13739                                       &do_align, 8, 16, 16, 32, 32, 64, -1);
13740      if (align_good == FAIL)
13741        return;
13742      constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
13743                  _("bad list length"));
13744      if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13745        inst.instruction |= 1 << 5;
13746      inst.instruction |= neon_logbits (et.size) << 6;
13747      break;
13748
13749    case 2:  /* VLD3.  */
13750      constraint (inst.operands[1].immisalign,
13751                  _("can't use alignment with this instruction"));
13752      constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
13753                  _("bad list length"));
13754      if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13755        inst.instruction |= 1 << 5;
13756      inst.instruction |= neon_logbits (et.size) << 6;
13757      break;
13758
13759    case 3:  /* VLD4.  */
13760      {
13761        int align = inst.operands[1].imm >> 8;
13762        align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
13763                                         16, 64, 32, 64, 32, 128, -1);
13764        if (align_good == FAIL)
13765          return;
13766        constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
13767                    _("bad list length"));
13768        if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13769          inst.instruction |= 1 << 5;
13770        if (et.size == 32 && align == 128)
13771          inst.instruction |= 0x3 << 6;
13772        else
13773          inst.instruction |= neon_logbits (et.size) << 6;
13774      }
13775      break;
13776
13777    default: ;
13778    }
13779
13780  inst.instruction |= do_align << 4;
13781}
13782
13783/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13784   apart from bits [11:4].  */
13785
13786static void
13787do_neon_ldx_stx (void)
13788{
13789  switch (NEON_LANE (inst.operands[0].imm))
13790    {
13791    case NEON_INTERLEAVE_LANES:
13792      inst.instruction = NEON_ENC_INTERLV (inst.instruction);
13793      do_neon_ld_st_interleave ();
13794      break;
13795
13796    case NEON_ALL_LANES:
13797      inst.instruction = NEON_ENC_DUP (inst.instruction);
13798      do_neon_ld_dup ();
13799      break;
13800
13801    default:
13802      inst.instruction = NEON_ENC_LANE (inst.instruction);
13803      do_neon_ld_st_lane ();
13804    }
13805
13806  /* L bit comes from bit mask.  */
13807  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13808  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13809  inst.instruction |= inst.operands[1].reg << 16;
13810
13811  if (inst.operands[1].postind)
13812    {
13813      int postreg = inst.operands[1].imm & 0xf;
13814      constraint (!inst.operands[1].immisreg,
13815                  _("post-index must be a register"));
13816      constraint (postreg == 0xd || postreg == 0xf,
13817                  _("bad register for post-index"));
13818      inst.instruction |= postreg;
13819    }
13820  else if (inst.operands[1].writeback)
13821    {
13822      inst.instruction |= 0xd;
13823    }
13824  else
13825    inst.instruction |= 0xf;
13826
13827  if (thumb_mode)
13828    inst.instruction |= 0xf9000000;
13829  else
13830    inst.instruction |= 0xf4000000;
13831}
13832
13833
13834/* Overall per-instruction processing.	*/
13835
13836/* We need to be able to fix up arbitrary expressions in some statements.
13837   This is so that we can handle symbols that are an arbitrary distance from
13838   the pc.  The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13839   which returns part of an address in a form which will be valid for
13840   a data instruction.	We do this by pushing the expression into a symbol
13841   in the expr_section, and creating a fix for that.  */
13842
13843static void
13844fix_new_arm (fragS *	   frag,
13845	     int	   where,
13846	     short int	   size,
13847	     expressionS * exp,
13848	     int	   pc_rel,
13849	     int	   reloc)
13850{
13851  fixS *	   new_fix;
13852
13853  switch (exp->X_op)
13854    {
13855    case O_constant:
13856    case O_symbol:
13857    case O_add:
13858    case O_subtract:
13859      new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
13860      break;
13861
13862    default:
13863      new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
13864			 pc_rel, reloc);
13865      break;
13866    }
13867
13868  /* Mark whether the fix is to a THUMB instruction, or an ARM
13869     instruction.  */
13870  new_fix->tc_fix_data = thumb_mode;
13871}
13872
13873/* Create a frg for an instruction requiring relaxation.  */
13874static void
13875output_relax_insn (void)
13876{
13877  char * to;
13878  symbolS *sym;
13879  int offset;
13880
13881  /* The size of the instruction is unknown, so tie the debug info to the
13882     start of the instruction.  */
13883  dwarf2_emit_insn (0);
13884
13885  switch (inst.reloc.exp.X_op)
13886    {
13887    case O_symbol:
13888      sym = inst.reloc.exp.X_add_symbol;
13889      offset = inst.reloc.exp.X_add_number;
13890      break;
13891    case O_constant:
13892      sym = NULL;
13893      offset = inst.reloc.exp.X_add_number;
13894      break;
13895    default:
13896      sym = make_expr_symbol (&inst.reloc.exp);
13897      offset = 0;
13898      break;
13899  }
13900  to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
13901		 inst.relax, sym, offset, NULL/*offset, opcode*/);
13902  md_number_to_chars (to, inst.instruction, THUMB_SIZE);
13903}
13904
13905/* Write a 32-bit thumb instruction to buf.  */
13906static void
13907put_thumb32_insn (char * buf, unsigned long insn)
13908{
13909  md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
13910  md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
13911}
13912
13913static void
13914output_inst (const char * str)
13915{
13916  char * to = NULL;
13917
13918  if (inst.error)
13919    {
13920      as_bad ("%s -- `%s'", inst.error, str);
13921      return;
13922    }
13923  if (inst.relax) {
13924      output_relax_insn();
13925      return;
13926  }
13927  if (inst.size == 0)
13928    return;
13929
13930  to = frag_more (inst.size);
13931
13932  if (thumb_mode && (inst.size > THUMB_SIZE))
13933    {
13934      assert (inst.size == (2 * THUMB_SIZE));
13935      put_thumb32_insn (to, inst.instruction);
13936    }
13937  else if (inst.size > INSN_SIZE)
13938    {
13939      assert (inst.size == (2 * INSN_SIZE));
13940      md_number_to_chars (to, inst.instruction, INSN_SIZE);
13941      md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
13942    }
13943  else
13944    md_number_to_chars (to, inst.instruction, inst.size);
13945
13946  if (inst.reloc.type != BFD_RELOC_UNUSED)
13947    fix_new_arm (frag_now, to - frag_now->fr_literal,
13948		 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
13949		 inst.reloc.type);
13950
13951  dwarf2_emit_insn (inst.size);
13952}
13953
13954/* Tag values used in struct asm_opcode's tag field.  */
13955enum opcode_tag
13956{
13957  OT_unconditional,	/* Instruction cannot be conditionalized.
13958			   The ARM condition field is still 0xE.  */
13959  OT_unconditionalF,	/* Instruction cannot be conditionalized
13960			   and carries 0xF in its ARM condition field.  */
13961  OT_csuffix,		/* Instruction takes a conditional suffix.  */
13962  OT_csuffixF,		/* Some forms of the instruction take a conditional
13963                           suffix, others place 0xF where the condition field
13964                           would be.  */
13965  OT_cinfix3,		/* Instruction takes a conditional infix,
13966			   beginning at character index 3.  (In
13967			   unified mode, it becomes a suffix.)  */
13968  OT_cinfix3_deprecated, /* The same as OT_cinfix3.  This is used for
13969			    tsts, cmps, cmns, and teqs. */
13970  OT_cinfix3_legacy,	/* Legacy instruction takes a conditional infix at
13971			   character index 3, even in unified mode.  Used for
13972			   legacy instructions where suffix and infix forms
13973			   may be ambiguous.  */
13974  OT_csuf_or_in3,	/* Instruction takes either a conditional
13975			   suffix or an infix at character index 3.  */
13976  OT_odd_infix_unc,	/* This is the unconditional variant of an
13977			   instruction that takes a conditional infix
13978			   at an unusual position.  In unified mode,
13979			   this variant will accept a suffix.  */
13980  OT_odd_infix_0	/* Values greater than or equal to OT_odd_infix_0
13981			   are the conditional variants of instructions that
13982			   take conditional infixes in unusual positions.
13983			   The infix appears at character index
13984			   (tag - OT_odd_infix_0).  These are not accepted
13985			   in unified mode.  */
13986};
13987
13988/* Subroutine of md_assemble, responsible for looking up the primary
13989   opcode from the mnemonic the user wrote.  STR points to the
13990   beginning of the mnemonic.
13991
13992   This is not simply a hash table lookup, because of conditional
13993   variants.  Most instructions have conditional variants, which are
13994   expressed with a _conditional affix_ to the mnemonic.  If we were
13995   to encode each conditional variant as a literal string in the opcode
13996   table, it would have approximately 20,000 entries.
13997
13998   Most mnemonics take this affix as a suffix, and in unified syntax,
13999   'most' is upgraded to 'all'.  However, in the divided syntax, some
14000   instructions take the affix as an infix, notably the s-variants of
14001   the arithmetic instructions.  Of those instructions, all but six
14002   have the infix appear after the third character of the mnemonic.
14003
14004   Accordingly, the algorithm for looking up primary opcodes given
14005   an identifier is:
14006
14007   1. Look up the identifier in the opcode table.
14008      If we find a match, go to step U.
14009
14010   2. Look up the last two characters of the identifier in the
14011      conditions table.  If we find a match, look up the first N-2
14012      characters of the identifier in the opcode table.  If we
14013      find a match, go to step CE.
14014
14015   3. Look up the fourth and fifth characters of the identifier in
14016      the conditions table.  If we find a match, extract those
14017      characters from the identifier, and look up the remaining
14018      characters in the opcode table.  If we find a match, go
14019      to step CM.
14020
14021   4. Fail.
14022
14023   U. Examine the tag field of the opcode structure, in case this is
14024      one of the six instructions with its conditional infix in an
14025      unusual place.  If it is, the tag tells us where to find the
14026      infix; look it up in the conditions table and set inst.cond
14027      accordingly.  Otherwise, this is an unconditional instruction.
14028      Again set inst.cond accordingly.  Return the opcode structure.
14029
14030  CE. Examine the tag field to make sure this is an instruction that
14031      should receive a conditional suffix.  If it is not, fail.
14032      Otherwise, set inst.cond from the suffix we already looked up,
14033      and return the opcode structure.
14034
14035  CM. Examine the tag field to make sure this is an instruction that
14036      should receive a conditional infix after the third character.
14037      If it is not, fail.  Otherwise, undo the edits to the current
14038      line of input and proceed as for case CE.  */
14039
14040static const struct asm_opcode *
14041opcode_lookup (char **str)
14042{
14043  char *end, *base;
14044  char *affix;
14045  const struct asm_opcode *opcode;
14046  const struct asm_cond *cond;
14047  char save[2];
14048  bfd_boolean neon_supported;
14049
14050  neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1);
14051
14052  /* Scan up to the end of the mnemonic, which must end in white space,
14053     '.' (in unified mode, or for Neon instructions), or end of string.  */
14054  for (base = end = *str; *end != '\0'; end++)
14055    if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.'))
14056      break;
14057
14058  if (end == base)
14059    return 0;
14060
14061  /* Handle a possible width suffix and/or Neon type suffix.  */
14062  if (end[0] == '.')
14063    {
14064      int offset = 2;
14065
14066      /* The .w and .n suffixes are only valid if the unified syntax is in
14067         use.  */
14068      if (unified_syntax && end[1] == 'w')
14069	inst.size_req = 4;
14070      else if (unified_syntax && end[1] == 'n')
14071	inst.size_req = 2;
14072      else
14073        offset = 0;
14074
14075      inst.vectype.elems = 0;
14076
14077      *str = end + offset;
14078
14079      if (end[offset] == '.')
14080	{
14081	  /* See if we have a Neon type suffix (possible in either unified or
14082             non-unified ARM syntax mode).  */
14083          if (parse_neon_type (&inst.vectype, str) == FAIL)
14084	    return 0;
14085        }
14086      else if (end[offset] != '\0' && end[offset] != ' ')
14087        return 0;
14088    }
14089  else
14090    *str = end;
14091
14092  /* Look for unaffixed or special-case affixed mnemonic.  */
14093  opcode = hash_find_n (arm_ops_hsh, base, end - base);
14094  if (opcode)
14095    {
14096      /* step U */
14097      if (opcode->tag < OT_odd_infix_0)
14098	{
14099	  inst.cond = COND_ALWAYS;
14100	  return opcode;
14101	}
14102
14103      if (unified_syntax)
14104	as_warn (_("conditional infixes are deprecated in unified syntax"));
14105      affix = base + (opcode->tag - OT_odd_infix_0);
14106      cond = hash_find_n (arm_cond_hsh, affix, 2);
14107      assert (cond);
14108
14109      inst.cond = cond->value;
14110      return opcode;
14111    }
14112
14113  /* Cannot have a conditional suffix on a mnemonic of less than two
14114     characters.  */
14115  if (end - base < 3)
14116    return 0;
14117
14118  /* Look for suffixed mnemonic.  */
14119  affix = end - 2;
14120  cond = hash_find_n (arm_cond_hsh, affix, 2);
14121  opcode = hash_find_n (arm_ops_hsh, base, affix - base);
14122  if (opcode && cond)
14123    {
14124      /* step CE */
14125      switch (opcode->tag)
14126	{
14127	case OT_cinfix3_legacy:
14128	  /* Ignore conditional suffixes matched on infix only mnemonics.  */
14129	  break;
14130
14131	case OT_cinfix3:
14132	case OT_cinfix3_deprecated:
14133	case OT_odd_infix_unc:
14134	  if (!unified_syntax)
14135	    return 0;
14136	  /* else fall through */
14137
14138	case OT_csuffix:
14139        case OT_csuffixF:
14140	case OT_csuf_or_in3:
14141	  inst.cond = cond->value;
14142	  return opcode;
14143
14144	case OT_unconditional:
14145	case OT_unconditionalF:
14146	  if (thumb_mode)
14147	    {
14148	      inst.cond = cond->value;
14149	    }
14150	  else
14151	    {
14152	      /* delayed diagnostic */
14153	      inst.error = BAD_COND;
14154	      inst.cond = COND_ALWAYS;
14155	    }
14156	  return opcode;
14157
14158	default:
14159	  return 0;
14160	}
14161    }
14162
14163  /* Cannot have a usual-position infix on a mnemonic of less than
14164     six characters (five would be a suffix).  */
14165  if (end - base < 6)
14166    return 0;
14167
14168  /* Look for infixed mnemonic in the usual position.  */
14169  affix = base + 3;
14170  cond = hash_find_n (arm_cond_hsh, affix, 2);
14171  if (!cond)
14172    return 0;
14173
14174  memcpy (save, affix, 2);
14175  memmove (affix, affix + 2, (end - affix) - 2);
14176  opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
14177  memmove (affix + 2, affix, (end - affix) - 2);
14178  memcpy (affix, save, 2);
14179
14180  if (opcode
14181      && (opcode->tag == OT_cinfix3
14182	  || opcode->tag == OT_cinfix3_deprecated
14183	  || opcode->tag == OT_csuf_or_in3
14184	  || opcode->tag == OT_cinfix3_legacy))
14185    {
14186      /* step CM */
14187      if (unified_syntax
14188	  && (opcode->tag == OT_cinfix3
14189	      || opcode->tag == OT_cinfix3_deprecated))
14190	as_warn (_("conditional infixes are deprecated in unified syntax"));
14191
14192      inst.cond = cond->value;
14193      return opcode;
14194    }
14195
14196  return 0;
14197}
14198
14199void
14200md_assemble (char *str)
14201{
14202  char *p = str;
14203  const struct asm_opcode * opcode;
14204
14205  /* Align the previous label if needed.  */
14206  if (last_label_seen != NULL)
14207    {
14208      symbol_set_frag (last_label_seen, frag_now);
14209      S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
14210      S_SET_SEGMENT (last_label_seen, now_seg);
14211    }
14212
14213  memset (&inst, '\0', sizeof (inst));
14214  inst.reloc.type = BFD_RELOC_UNUSED;
14215
14216  opcode = opcode_lookup (&p);
14217  if (!opcode)
14218    {
14219      /* It wasn't an instruction, but it might be a register alias of
14220	 the form alias .req reg, or a Neon .dn/.qn directive.  */
14221      if (!create_register_alias (str, p)
14222          && !create_neon_reg_alias (str, p))
14223	as_bad (_("bad instruction `%s'"), str);
14224
14225      return;
14226    }
14227
14228  if (opcode->tag == OT_cinfix3_deprecated)
14229    as_warn (_("s suffix on comparison instruction is deprecated"));
14230
14231  /* The value which unconditional instructions should have in place of the
14232     condition field.  */
14233  inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
14234
14235  if (thumb_mode)
14236    {
14237      arm_feature_set variant;
14238
14239      variant = cpu_variant;
14240      /* Only allow coprocessor instructions on Thumb-2 capable devices.  */
14241      if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
14242	ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
14243      /* Check that this instruction is supported for this CPU.  */
14244      if (!opcode->tvariant
14245	  || (thumb_mode == 1
14246	      && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
14247	{
14248	  as_bad (_("selected processor does not support `%s'"), str);
14249	  return;
14250	}
14251      if (inst.cond != COND_ALWAYS && !unified_syntax
14252	  && opcode->tencode != do_t_branch)
14253	{
14254	  as_bad (_("Thumb does not support conditional execution"));
14255	  return;
14256	}
14257
14258      if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req)
14259	{
14260	  /* Implicit require narrow instructions on Thumb-1.  This avoids
14261	     relaxation accidentally introducing Thumb-2 instructions.  */
14262	  if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23)
14263	    inst.size_req = 2;
14264	}
14265
14266      /* Check conditional suffixes.  */
14267      if (current_it_mask)
14268	{
14269	  int cond;
14270	  cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
14271	  current_it_mask <<= 1;
14272	  current_it_mask &= 0x1f;
14273	  /* The BKPT instruction is unconditional even in an IT block.  */
14274	  if (!inst.error
14275	      && cond != inst.cond && opcode->tencode != do_t_bkpt)
14276	    {
14277	      as_bad (_("incorrect condition in IT block"));
14278	      return;
14279	    }
14280	}
14281      else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
14282	{
14283	  as_bad (_("thumb conditional instrunction not in IT block"));
14284	  return;
14285	}
14286
14287      mapping_state (MAP_THUMB);
14288      inst.instruction = opcode->tvalue;
14289
14290      if (!parse_operands (p, opcode->operands))
14291	opcode->tencode ();
14292
14293      /* Clear current_it_mask at the end of an IT block.  */
14294      if (current_it_mask == 0x10)
14295	current_it_mask = 0;
14296
14297      if (!(inst.error || inst.relax))
14298	{
14299	  assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
14300	  inst.size = (inst.instruction > 0xffff ? 4 : 2);
14301	  if (inst.size_req && inst.size_req != inst.size)
14302	    {
14303	      as_bad (_("cannot honor width suffix -- `%s'"), str);
14304	      return;
14305	    }
14306	}
14307
14308      /* Something has gone badly wrong if we try to relax a fixed size
14309         instruction.  */
14310      assert (inst.size_req == 0 || !inst.relax);
14311
14312      ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
14313			      *opcode->tvariant);
14314      /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14315	 set those bits when Thumb-2 32-bit instructions are seen.  ie.
14316	 anything other than bl/blx.
14317	 This is overly pessimistic for relaxable instructions.  */
14318      if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
14319	  || inst.relax)
14320	ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
14321				arm_ext_v6t2);
14322    }
14323  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
14324    {
14325      /* Check that this instruction is supported for this CPU.  */
14326      if (!opcode->avariant ||
14327	  !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
14328	{
14329	  as_bad (_("selected processor does not support `%s'"), str);
14330	  return;
14331	}
14332      if (inst.size_req)
14333	{
14334	  as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
14335	  return;
14336	}
14337
14338      mapping_state (MAP_ARM);
14339      inst.instruction = opcode->avalue;
14340      if (opcode->tag == OT_unconditionalF)
14341	inst.instruction |= 0xF << 28;
14342      else
14343	inst.instruction |= inst.cond << 28;
14344      inst.size = INSN_SIZE;
14345      if (!parse_operands (p, opcode->operands))
14346	opcode->aencode ();
14347      /* Arm mode bx is marked as both v4T and v5 because it's still required
14348         on a hypothetical non-thumb v5 core.  */
14349      if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t)
14350	  || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5))
14351	ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
14352      else
14353	ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
14354				*opcode->avariant);
14355    }
14356  else
14357    {
14358      as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14359		"-- `%s'"), str);
14360      return;
14361    }
14362  output_inst (str);
14363}
14364
14365/* Various frobbings of labels and their addresses.  */
14366
14367void
14368arm_start_line_hook (void)
14369{
14370  last_label_seen = NULL;
14371}
14372
14373void
14374arm_frob_label (symbolS * sym)
14375{
14376  last_label_seen = sym;
14377
14378  ARM_SET_THUMB (sym, thumb_mode);
14379
14380#if defined OBJ_COFF || defined OBJ_ELF
14381  ARM_SET_INTERWORK (sym, support_interwork);
14382#endif
14383
14384  /* Note - do not allow local symbols (.Lxxx) to be labeled
14385     as Thumb functions.  This is because these labels, whilst
14386     they exist inside Thumb code, are not the entry points for
14387     possible ARM->Thumb calls.	 Also, these labels can be used
14388     as part of a computed goto or switch statement.  eg gcc
14389     can generate code that looks like this:
14390
14391		ldr  r2, [pc, .Laaa]
14392		lsl  r3, r3, #2
14393		ldr  r2, [r3, r2]
14394		mov  pc, r2
14395
14396       .Lbbb:  .word .Lxxx
14397       .Lccc:  .word .Lyyy
14398       ..etc...
14399       .Laaa:	.word Lbbb
14400
14401     The first instruction loads the address of the jump table.
14402     The second instruction converts a table index into a byte offset.
14403     The third instruction gets the jump address out of the table.
14404     The fourth instruction performs the jump.
14405
14406     If the address stored at .Laaa is that of a symbol which has the
14407     Thumb_Func bit set, then the linker will arrange for this address
14408     to have the bottom bit set, which in turn would mean that the
14409     address computation performed by the third instruction would end
14410     up with the bottom bit set.  Since the ARM is capable of unaligned
14411     word loads, the instruction would then load the incorrect address
14412     out of the jump table, and chaos would ensue.  */
14413  if (label_is_thumb_function_name
14414      && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
14415      && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
14416    {
14417      /* When the address of a Thumb function is taken the bottom
14418	 bit of that address should be set.  This will allow
14419	 interworking between Arm and Thumb functions to work
14420	 correctly.  */
14421
14422      THUMB_SET_FUNC (sym, 1);
14423
14424      label_is_thumb_function_name = FALSE;
14425    }
14426
14427  dwarf2_emit_label (sym);
14428}
14429
14430int
14431arm_data_in_code (void)
14432{
14433  if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
14434    {
14435      *input_line_pointer = '/';
14436      input_line_pointer += 5;
14437      *input_line_pointer = 0;
14438      return 1;
14439    }
14440
14441  return 0;
14442}
14443
14444char *
14445arm_canonicalize_symbol_name (char * name)
14446{
14447  int len;
14448
14449  if (thumb_mode && (len = strlen (name)) > 5
14450      && streq (name + len - 5, "/data"))
14451    *(name + len - 5) = 0;
14452
14453  return name;
14454}
14455
14456/* Table of all register names defined by default.  The user can
14457   define additional names with .req.  Note that all register names
14458   should appear in both upper and lowercase variants.	Some registers
14459   also have mixed-case names.	*/
14460
14461#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14462#define REGNUM(p,n,t) REGDEF(p##n, n, t)
14463#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14464#define REGSET(p,t) \
14465  REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14466  REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14467  REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14468  REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14469#define REGSETH(p,t) \
14470  REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14471  REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14472  REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14473  REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14474#define REGSET2(p,t) \
14475  REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14476  REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14477  REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14478  REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14479
14480static const struct reg_entry reg_names[] =
14481{
14482  /* ARM integer registers.  */
14483  REGSET(r, RN), REGSET(R, RN),
14484
14485  /* ATPCS synonyms.  */
14486  REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
14487  REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
14488  REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
14489
14490  REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
14491  REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
14492  REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
14493
14494  /* Well-known aliases.  */
14495  REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
14496  REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
14497
14498  REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
14499  REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
14500
14501  /* Coprocessor numbers.  */
14502  REGSET(p, CP), REGSET(P, CP),
14503
14504  /* Coprocessor register numbers.  The "cr" variants are for backward
14505     compatibility.  */
14506  REGSET(c,  CN), REGSET(C, CN),
14507  REGSET(cr, CN), REGSET(CR, CN),
14508
14509  /* FPA registers.  */
14510  REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
14511  REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
14512
14513  REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
14514  REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
14515
14516  /* VFP SP registers.	*/
14517  REGSET(s,VFS),  REGSET(S,VFS),
14518  REGSETH(s,VFS), REGSETH(S,VFS),
14519
14520  /* VFP DP Registers.	*/
14521  REGSET(d,VFD),  REGSET(D,VFD),
14522  /* Extra Neon DP registers.  */
14523  REGSETH(d,VFD), REGSETH(D,VFD),
14524
14525  /* Neon QP registers.  */
14526  REGSET2(q,NQ),  REGSET2(Q,NQ),
14527
14528  /* VFP control registers.  */
14529  REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
14530  REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
14531  REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
14532  REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
14533  REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
14534  REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
14535
14536  /* Maverick DSP coprocessor registers.  */
14537  REGSET(mvf,MVF),  REGSET(mvd,MVD),  REGSET(mvfx,MVFX),  REGSET(mvdx,MVDX),
14538  REGSET(MVF,MVF),  REGSET(MVD,MVD),  REGSET(MVFX,MVFX),  REGSET(MVDX,MVDX),
14539
14540  REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
14541  REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
14542  REGDEF(dspsc,0,DSPSC),
14543
14544  REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
14545  REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
14546  REGDEF(DSPSC,0,DSPSC),
14547
14548  /* iWMMXt data registers - p0, c0-15.	 */
14549  REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
14550
14551  /* iWMMXt control registers - p1, c0-3.  */
14552  REGDEF(wcid,	0,MMXWC),  REGDEF(wCID,	 0,MMXWC),  REGDEF(WCID,  0,MMXWC),
14553  REGDEF(wcon,	1,MMXWC),  REGDEF(wCon,	 1,MMXWC),  REGDEF(WCON,  1,MMXWC),
14554  REGDEF(wcssf, 2,MMXWC),  REGDEF(wCSSF, 2,MMXWC),  REGDEF(WCSSF, 2,MMXWC),
14555  REGDEF(wcasf, 3,MMXWC),  REGDEF(wCASF, 3,MMXWC),  REGDEF(WCASF, 3,MMXWC),
14556
14557  /* iWMMXt scalar (constant/offset) registers - p1, c8-11.  */
14558  REGDEF(wcgr0, 8,MMXWCG),  REGDEF(wCGR0, 8,MMXWCG),  REGDEF(WCGR0, 8,MMXWCG),
14559  REGDEF(wcgr1, 9,MMXWCG),  REGDEF(wCGR1, 9,MMXWCG),  REGDEF(WCGR1, 9,MMXWCG),
14560  REGDEF(wcgr2,10,MMXWCG),  REGDEF(wCGR2,10,MMXWCG),  REGDEF(WCGR2,10,MMXWCG),
14561  REGDEF(wcgr3,11,MMXWCG),  REGDEF(wCGR3,11,MMXWCG),  REGDEF(WCGR3,11,MMXWCG),
14562
14563  /* XScale accumulator registers.  */
14564  REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
14565};
14566#undef REGDEF
14567#undef REGNUM
14568#undef REGSET
14569
14570/* Table of all PSR suffixes.  Bare "CPSR" and "SPSR" are handled
14571   within psr_required_here.  */
14572static const struct asm_psr psrs[] =
14573{
14574  /* Backward compatibility notation.  Note that "all" is no longer
14575     truly all possible PSR bits.  */
14576  {"all",  PSR_c | PSR_f},
14577  {"flg",  PSR_f},
14578  {"ctl",  PSR_c},
14579
14580  /* Individual flags.	*/
14581  {"f",	   PSR_f},
14582  {"c",	   PSR_c},
14583  {"x",	   PSR_x},
14584  {"s",	   PSR_s},
14585  /* Combinations of flags.  */
14586  {"fs",   PSR_f | PSR_s},
14587  {"fx",   PSR_f | PSR_x},
14588  {"fc",   PSR_f | PSR_c},
14589  {"sf",   PSR_s | PSR_f},
14590  {"sx",   PSR_s | PSR_x},
14591  {"sc",   PSR_s | PSR_c},
14592  {"xf",   PSR_x | PSR_f},
14593  {"xs",   PSR_x | PSR_s},
14594  {"xc",   PSR_x | PSR_c},
14595  {"cf",   PSR_c | PSR_f},
14596  {"cs",   PSR_c | PSR_s},
14597  {"cx",   PSR_c | PSR_x},
14598  {"fsx",  PSR_f | PSR_s | PSR_x},
14599  {"fsc",  PSR_f | PSR_s | PSR_c},
14600  {"fxs",  PSR_f | PSR_x | PSR_s},
14601  {"fxc",  PSR_f | PSR_x | PSR_c},
14602  {"fcs",  PSR_f | PSR_c | PSR_s},
14603  {"fcx",  PSR_f | PSR_c | PSR_x},
14604  {"sfx",  PSR_s | PSR_f | PSR_x},
14605  {"sfc",  PSR_s | PSR_f | PSR_c},
14606  {"sxf",  PSR_s | PSR_x | PSR_f},
14607  {"sxc",  PSR_s | PSR_x | PSR_c},
14608  {"scf",  PSR_s | PSR_c | PSR_f},
14609  {"scx",  PSR_s | PSR_c | PSR_x},
14610  {"xfs",  PSR_x | PSR_f | PSR_s},
14611  {"xfc",  PSR_x | PSR_f | PSR_c},
14612  {"xsf",  PSR_x | PSR_s | PSR_f},
14613  {"xsc",  PSR_x | PSR_s | PSR_c},
14614  {"xcf",  PSR_x | PSR_c | PSR_f},
14615  {"xcs",  PSR_x | PSR_c | PSR_s},
14616  {"cfs",  PSR_c | PSR_f | PSR_s},
14617  {"cfx",  PSR_c | PSR_f | PSR_x},
14618  {"csf",  PSR_c | PSR_s | PSR_f},
14619  {"csx",  PSR_c | PSR_s | PSR_x},
14620  {"cxf",  PSR_c | PSR_x | PSR_f},
14621  {"cxs",  PSR_c | PSR_x | PSR_s},
14622  {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
14623  {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
14624  {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
14625  {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
14626  {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
14627  {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
14628  {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
14629  {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
14630  {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
14631  {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
14632  {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
14633  {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
14634  {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
14635  {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
14636  {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
14637  {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
14638  {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
14639  {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
14640  {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
14641  {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
14642  {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
14643  {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
14644  {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
14645  {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
14646};
14647
14648/* Table of V7M psr names.  */
14649static const struct asm_psr v7m_psrs[] =
14650{
14651  {"apsr",	  0 }, {"APSR",		0 },
14652  {"iapsr",	  1 }, {"IAPSR",	1 },
14653  {"eapsr",	  2 }, {"EAPSR",	2 },
14654  {"psr",	  3 }, {"PSR",		3 },
14655  {"xpsr",	  3 }, {"XPSR",		3 }, {"xPSR",	  3 },
14656  {"ipsr",	  5 }, {"IPSR",		5 },
14657  {"epsr",	  6 }, {"EPSR",		6 },
14658  {"iepsr",	  7 }, {"IEPSR",	7 },
14659  {"msp",	  8 }, {"MSP",		8 },
14660  {"psp",	  9 }, {"PSP",		9 },
14661  {"primask",	  16}, {"PRIMASK",	16},
14662  {"basepri",	  17}, {"BASEPRI",	17},
14663  {"basepri_max", 18}, {"BASEPRI_MAX",	18},
14664  {"faultmask",	  19}, {"FAULTMASK",	19},
14665  {"control",	  20}, {"CONTROL",	20}
14666};
14667
14668/* Table of all shift-in-operand names.	 */
14669static const struct asm_shift_name shift_names [] =
14670{
14671  { "asl", SHIFT_LSL },	 { "ASL", SHIFT_LSL },
14672  { "lsl", SHIFT_LSL },	 { "LSL", SHIFT_LSL },
14673  { "lsr", SHIFT_LSR },	 { "LSR", SHIFT_LSR },
14674  { "asr", SHIFT_ASR },	 { "ASR", SHIFT_ASR },
14675  { "ror", SHIFT_ROR },	 { "ROR", SHIFT_ROR },
14676  { "rrx", SHIFT_RRX },	 { "RRX", SHIFT_RRX }
14677};
14678
14679/* Table of all explicit relocation names.  */
14680#ifdef OBJ_ELF
14681static struct reloc_entry reloc_names[] =
14682{
14683  { "got",     BFD_RELOC_ARM_GOT32   },	 { "GOT",     BFD_RELOC_ARM_GOT32   },
14684  { "gotoff",  BFD_RELOC_ARM_GOTOFF  },	 { "GOTOFF",  BFD_RELOC_ARM_GOTOFF  },
14685  { "plt",     BFD_RELOC_ARM_PLT32   },	 { "PLT",     BFD_RELOC_ARM_PLT32   },
14686  { "target1", BFD_RELOC_ARM_TARGET1 },	 { "TARGET1", BFD_RELOC_ARM_TARGET1 },
14687  { "target2", BFD_RELOC_ARM_TARGET2 },	 { "TARGET2", BFD_RELOC_ARM_TARGET2 },
14688  { "sbrel",   BFD_RELOC_ARM_SBREL32 },	 { "SBREL",   BFD_RELOC_ARM_SBREL32 },
14689  { "tlsgd",   BFD_RELOC_ARM_TLS_GD32},  { "TLSGD",   BFD_RELOC_ARM_TLS_GD32},
14690  { "tlsldm",  BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM",  BFD_RELOC_ARM_TLS_LDM32},
14691  { "tlsldo",  BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO",  BFD_RELOC_ARM_TLS_LDO32},
14692  { "gottpoff",BFD_RELOC_ARM_TLS_IE32},  { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
14693  { "tpoff",   BFD_RELOC_ARM_TLS_LE32},  { "TPOFF",   BFD_RELOC_ARM_TLS_LE32}
14694};
14695#endif
14696
14697/* Table of all conditional affixes.  0xF is not defined as a condition code.  */
14698static const struct asm_cond conds[] =
14699{
14700  {"eq", 0x0},
14701  {"ne", 0x1},
14702  {"cs", 0x2}, {"hs", 0x2},
14703  {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14704  {"mi", 0x4},
14705  {"pl", 0x5},
14706  {"vs", 0x6},
14707  {"vc", 0x7},
14708  {"hi", 0x8},
14709  {"ls", 0x9},
14710  {"ge", 0xa},
14711  {"lt", 0xb},
14712  {"gt", 0xc},
14713  {"le", 0xd},
14714  {"al", 0xe}
14715};
14716
14717static struct asm_barrier_opt barrier_opt_names[] =
14718{
14719  { "sy",    0xf },
14720  { "un",    0x7 },
14721  { "st",    0xe },
14722  { "unst",  0x6 },
14723  { "ish",   0xb },
14724  { "sh",    0xb },
14725  { "ishst", 0xa },
14726  { "shst",  0xa },
14727  { "nsh",   0x7 },
14728  { "nshst", 0x6 },
14729  { "osh",   0x3 },
14730  { "oshst", 0x2 }
14731};
14732
14733/* Table of ARM-format instructions.	*/
14734
14735/* Macros for gluing together operand strings.  N.B. In all cases
14736   other than OPS0, the trailing OP_stop comes from default
14737   zero-initialization of the unspecified elements of the array.  */
14738#define OPS0()		  { OP_stop, }
14739#define OPS1(a)		  { OP_##a, }
14740#define OPS2(a,b)	  { OP_##a,OP_##b, }
14741#define OPS3(a,b,c)	  { OP_##a,OP_##b,OP_##c, }
14742#define OPS4(a,b,c,d)	  { OP_##a,OP_##b,OP_##c,OP_##d, }
14743#define OPS5(a,b,c,d,e)	  { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14744#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14745
14746/* These macros abstract out the exact format of the mnemonic table and
14747   save some repeated characters.  */
14748
14749/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix.  */
14750#define TxCE(mnem, op, top, nops, ops, ae, te) \
14751  { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14752    THUMB_VARIANT, do_##ae, do_##te }
14753
14754/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14755   a T_MNEM_xyz enumerator.  */
14756#define TCE(mnem, aop, top, nops, ops, ae, te) \
14757       TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14758#define tCE(mnem, aop, top, nops, ops, ae, te) \
14759       TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14760
14761/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14762   infix after the third character.  */
14763#define TxC3(mnem, op, top, nops, ops, ae, te) \
14764  { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14765    THUMB_VARIANT, do_##ae, do_##te }
14766#define TxC3w(mnem, op, top, nops, ops, ae, te) \
14767  { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14768    THUMB_VARIANT, do_##ae, do_##te }
14769#define TC3(mnem, aop, top, nops, ops, ae, te) \
14770       TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14771#define TC3w(mnem, aop, top, nops, ops, ae, te) \
14772       TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14773#define tC3(mnem, aop, top, nops, ops, ae, te) \
14774       TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14775#define tC3w(mnem, aop, top, nops, ops, ae, te) \
14776       TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14777
14778/* Mnemonic with a conditional infix in an unusual place.  Each and every variant has to
14779   appear in the condition table.  */
14780#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te)	\
14781  { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14782    0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14783
14784#define TxCM(m1, m2, op, top, nops, ops, ae, te)	\
14785  TxCM_(m1,   , m2, op, top, nops, ops, ae, te),	\
14786  TxCM_(m1, eq, m2, op, top, nops, ops, ae, te),	\
14787  TxCM_(m1, ne, m2, op, top, nops, ops, ae, te),	\
14788  TxCM_(m1, cs, m2, op, top, nops, ops, ae, te),	\
14789  TxCM_(m1, hs, m2, op, top, nops, ops, ae, te),	\
14790  TxCM_(m1, cc, m2, op, top, nops, ops, ae, te),	\
14791  TxCM_(m1, ul, m2, op, top, nops, ops, ae, te),	\
14792  TxCM_(m1, lo, m2, op, top, nops, ops, ae, te),	\
14793  TxCM_(m1, mi, m2, op, top, nops, ops, ae, te),	\
14794  TxCM_(m1, pl, m2, op, top, nops, ops, ae, te),	\
14795  TxCM_(m1, vs, m2, op, top, nops, ops, ae, te),	\
14796  TxCM_(m1, vc, m2, op, top, nops, ops, ae, te),	\
14797  TxCM_(m1, hi, m2, op, top, nops, ops, ae, te),	\
14798  TxCM_(m1, ls, m2, op, top, nops, ops, ae, te),	\
14799  TxCM_(m1, ge, m2, op, top, nops, ops, ae, te),	\
14800  TxCM_(m1, lt, m2, op, top, nops, ops, ae, te),	\
14801  TxCM_(m1, gt, m2, op, top, nops, ops, ae, te),	\
14802  TxCM_(m1, le, m2, op, top, nops, ops, ae, te),	\
14803  TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14804
14805#define TCM(m1,m2, aop, top, nops, ops, ae, te)		\
14806       TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14807#define tCM(m1,m2, aop, top, nops, ops, ae, te)			\
14808       TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14809
14810/* Mnemonic that cannot be conditionalized.  The ARM condition-code
14811   field is still 0xE.  Many of the Thumb variants can be executed
14812   conditionally, so this is checked separately.  */
14813#define TUE(mnem, op, top, nops, ops, ae, te)				\
14814  { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14815    THUMB_VARIANT, do_##ae, do_##te }
14816
14817/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14818   condition code field.  */
14819#define TUF(mnem, op, top, nops, ops, ae, te)				\
14820  { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14821    THUMB_VARIANT, do_##ae, do_##te }
14822
14823/* ARM-only variants of all the above.  */
14824#define CE(mnem,  op, nops, ops, ae)	\
14825  { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14826
14827#define C3(mnem, op, nops, ops, ae)	\
14828  { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14829
14830/* Legacy mnemonics that always have conditional infix after the third
14831   character.  */
14832#define CL(mnem, op, nops, ops, ae)	\
14833  { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14834    0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14835
14836/* Coprocessor instructions.  Isomorphic between Arm and Thumb-2.  */
14837#define cCE(mnem,  op, nops, ops, ae)	\
14838  { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14839
14840/* Legacy coprocessor instructions where conditional infix and conditional
14841   suffix are ambiguous.  For consistency this includes all FPA instructions,
14842   not just the potentially ambiguous ones.  */
14843#define cCL(mnem, op, nops, ops, ae)	\
14844  { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14845    0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14846
14847/* Coprocessor, takes either a suffix or a position-3 infix
14848   (for an FPA corner case). */
14849#define C3E(mnem, op, nops, ops, ae) \
14850  { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14851    0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14852
14853#define xCM_(m1, m2, m3, op, nops, ops, ae)	\
14854  { #m1 #m2 #m3, OPS##nops ops, \
14855    sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14856    0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14857
14858#define CM(m1, m2, op, nops, ops, ae)	\
14859  xCM_(m1,   , m2, op, nops, ops, ae),	\
14860  xCM_(m1, eq, m2, op, nops, ops, ae),	\
14861  xCM_(m1, ne, m2, op, nops, ops, ae),	\
14862  xCM_(m1, cs, m2, op, nops, ops, ae),	\
14863  xCM_(m1, hs, m2, op, nops, ops, ae),	\
14864  xCM_(m1, cc, m2, op, nops, ops, ae),	\
14865  xCM_(m1, ul, m2, op, nops, ops, ae),	\
14866  xCM_(m1, lo, m2, op, nops, ops, ae),	\
14867  xCM_(m1, mi, m2, op, nops, ops, ae),	\
14868  xCM_(m1, pl, m2, op, nops, ops, ae),	\
14869  xCM_(m1, vs, m2, op, nops, ops, ae),	\
14870  xCM_(m1, vc, m2, op, nops, ops, ae),	\
14871  xCM_(m1, hi, m2, op, nops, ops, ae),	\
14872  xCM_(m1, ls, m2, op, nops, ops, ae),	\
14873  xCM_(m1, ge, m2, op, nops, ops, ae),	\
14874  xCM_(m1, lt, m2, op, nops, ops, ae),	\
14875  xCM_(m1, gt, m2, op, nops, ops, ae),	\
14876  xCM_(m1, le, m2, op, nops, ops, ae),	\
14877  xCM_(m1, al, m2, op, nops, ops, ae)
14878
14879#define UE(mnem, op, nops, ops, ae)	\
14880  { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14881
14882#define UF(mnem, op, nops, ops, ae)	\
14883  { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14884
14885/* Neon data-processing. ARM versions are unconditional with cond=0xf.
14886   The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14887   use the same encoding function for each.  */
14888#define NUF(mnem, op, nops, ops, enc)					\
14889  { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op,		\
14890    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14891
14892/* Neon data processing, version which indirects through neon_enc_tab for
14893   the various overloaded versions of opcodes.  */
14894#define nUF(mnem, op, nops, ops, enc)					\
14895  { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op,	\
14896    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14897
14898/* Neon insn with conditional suffix for the ARM version, non-overloaded
14899   version.  */
14900#define NCE_tag(mnem, op, nops, ops, enc, tag)				\
14901  { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT,		\
14902    THUMB_VARIANT, do_##enc, do_##enc }
14903
14904#define NCE(mnem, op, nops, ops, enc)					\
14905  NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14906
14907#define NCEF(mnem, op, nops, ops, enc)					\
14908  NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14909
14910/* Neon insn with conditional suffix for the ARM version, overloaded types.  */
14911#define nCE_tag(mnem, op, nops, ops, enc, tag)				\
14912  { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op,		\
14913    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14914
14915#define nCE(mnem, op, nops, ops, enc)					\
14916  nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14917
14918#define nCEF(mnem, op, nops, ops, enc)					\
14919  nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14920
14921#define do_0 0
14922
14923/* Thumb-only, unconditional.  */
14924#define UT(mnem,  op, nops, ops, te) TUE(mnem,  0, op, nops, ops, 0, te)
14925
14926static const struct asm_opcode insns[] =
14927{
14928#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions.  */
14929#define THUMB_VARIANT &arm_ext_v4t
14930 tCE(and,	0000000, and,      3, (RR, oRR, SH), arit, t_arit3c),
14931 tC3(ands,	0100000, ands,	   3, (RR, oRR, SH), arit, t_arit3c),
14932 tCE(eor,	0200000, eor,	   3, (RR, oRR, SH), arit, t_arit3c),
14933 tC3(eors,	0300000, eors,	   3, (RR, oRR, SH), arit, t_arit3c),
14934 tCE(sub,	0400000, sub,	   3, (RR, oRR, SH), arit, t_add_sub),
14935 tC3(subs,	0500000, subs,	   3, (RR, oRR, SH), arit, t_add_sub),
14936 tCE(add,	0800000, add,	   3, (RR, oRR, SHG), arit, t_add_sub),
14937 tC3(adds,	0900000, adds,	   3, (RR, oRR, SHG), arit, t_add_sub),
14938 tCE(adc,	0a00000, adc,	   3, (RR, oRR, SH), arit, t_arit3c),
14939 tC3(adcs,	0b00000, adcs,	   3, (RR, oRR, SH), arit, t_arit3c),
14940 tCE(sbc,	0c00000, sbc,	   3, (RR, oRR, SH), arit, t_arit3),
14941 tC3(sbcs,	0d00000, sbcs,	   3, (RR, oRR, SH), arit, t_arit3),
14942 tCE(orr,	1800000, orr,	   3, (RR, oRR, SH), arit, t_arit3c),
14943 tC3(orrs,	1900000, orrs,	   3, (RR, oRR, SH), arit, t_arit3c),
14944 tCE(bic,	1c00000, bic,	   3, (RR, oRR, SH), arit, t_arit3),
14945 tC3(bics,	1d00000, bics,	   3, (RR, oRR, SH), arit, t_arit3),
14946
14947 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14948    for setting PSR flag bits.  They are obsolete in V6 and do not
14949    have Thumb equivalents. */
14950 tCE(tst,	1100000, tst,	   2, (RR, SH),      cmp,  t_mvn_tst),
14951 tC3w(tsts,	1100000, tst,	   2, (RR, SH),      cmp,  t_mvn_tst),
14952  CL(tstp,	110f000,     	   2, (RR, SH),      cmp),
14953 tCE(cmp,	1500000, cmp,	   2, (RR, SH),      cmp,  t_mov_cmp),
14954 tC3w(cmps,	1500000, cmp,	   2, (RR, SH),      cmp,  t_mov_cmp),
14955  CL(cmpp,	150f000,     	   2, (RR, SH),      cmp),
14956 tCE(cmn,	1700000, cmn,	   2, (RR, SH),      cmp,  t_mvn_tst),
14957 tC3w(cmns,	1700000, cmn,	   2, (RR, SH),      cmp,  t_mvn_tst),
14958  CL(cmnp,	170f000,     	   2, (RR, SH),      cmp),
14959
14960 tCE(mov,	1a00000, mov,	   2, (RR, SH),      mov,  t_mov_cmp),
14961 tC3(movs,	1b00000, movs,	   2, (RR, SH),      mov,  t_mov_cmp),
14962 tCE(mvn,	1e00000, mvn,	   2, (RR, SH),      mov,  t_mvn_tst),
14963 tC3(mvns,	1f00000, mvns,	   2, (RR, SH),      mov,  t_mvn_tst),
14964
14965 tCE(ldr,	4100000, ldr,	   2, (RR, ADDRGLDR),ldst, t_ldst),
14966 tC3(ldrb,	4500000, ldrb,	   2, (RR, ADDRGLDR),ldst, t_ldst),
14967 tCE(str,	4000000, str,	   2, (RR, ADDRGLDR),ldst, t_ldst),
14968 tC3(strb,	4400000, strb,	   2, (RR, ADDRGLDR),ldst, t_ldst),
14969
14970 tCE(stm,	8800000, stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
14971 tC3(stmia,	8800000, stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
14972 tC3(stmea,	8800000, stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
14973 tCE(ldm,	8900000, ldmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
14974 tC3(ldmia,	8900000, ldmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
14975 tC3(ldmfd,	8900000, ldmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
14976
14977 TCE(swi,	f000000, df00,     1, (EXPi),        swi, t_swi),
14978 TCE(svc,	f000000, df00,     1, (EXPi),        swi, t_swi),
14979 tCE(b,		a000000, b,	   1, (EXPr),	     branch, t_branch),
14980 TCE(bl,	b000000, f000f800, 1, (EXPr),	     bl, t_branch23),
14981
14982  /* Pseudo ops.  */
14983 tCE(adr,	28f0000, adr,	   2, (RR, EXP),     adr,  t_adr),
14984  C3(adrl,	28f0000,           2, (RR, EXP),     adrl),
14985 tCE(nop,	1a00000, nop,	   1, (oI255c),	     nop,  t_nop),
14986
14987  /* Thumb-compatibility pseudo ops.  */
14988 tCE(lsl,	1a00000, lsl,	   3, (RR, oRR, SH), shift, t_shift),
14989 tC3(lsls,	1b00000, lsls,	   3, (RR, oRR, SH), shift, t_shift),
14990 tCE(lsr,	1a00020, lsr,	   3, (RR, oRR, SH), shift, t_shift),
14991 tC3(lsrs,	1b00020, lsrs,	   3, (RR, oRR, SH), shift, t_shift),
14992 tCE(asr,	1a00040, asr,	   3, (RR, oRR, SH), shift, t_shift),
14993 tC3(asrs,      1b00040, asrs,     3, (RR, oRR, SH), shift, t_shift),
14994 tCE(ror,	1a00060, ror,	   3, (RR, oRR, SH), shift, t_shift),
14995 tC3(rors,	1b00060, rors,	   3, (RR, oRR, SH), shift, t_shift),
14996 tCE(neg,	2600000, neg,	   2, (RR, RR),      rd_rn, t_neg),
14997 tC3(negs,	2700000, negs,	   2, (RR, RR),      rd_rn, t_neg),
14998 tCE(push,	92d0000, push,     1, (REGLST),	     push_pop, t_push_pop),
14999 tCE(pop,	8bd0000, pop,	   1, (REGLST),	     push_pop, t_push_pop),
15000
15001 /* These may simplify to neg.  */
15002 TCE(rsb,	0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
15003 TC3(rsbs,	0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
15004
15005 TCE(rrx,      1a00060, ea4f0030, 2, (RR, RR),      rd_rm, t_rd_rm),
15006 TCE(rrxs,     1b00060, ea5f0030, 2, (RR, RR),      rd_rm, t_rd_rm),
15007
15008#undef THUMB_VARIANT
15009#define THUMB_VARIANT &arm_ext_v6
15010 TCE(cpy,       1a00000, 4600,     2, (RR, RR),      rd_rm, t_cpy),
15011
15012 /* V1 instructions with no Thumb analogue prior to V6T2.  */
15013#undef THUMB_VARIANT
15014#define THUMB_VARIANT &arm_ext_v6t2
15015 TCE(teq,	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
15016 TC3w(teqs,	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
15017  CL(teqp,	130f000,           2, (RR, SH),      cmp),
15018
15019 TC3(ldrt,	4300000, f8500e00, 2, (RR, ADDR),    ldstt, t_ldstt),
15020 TC3(ldrbt,	4700000, f8100e00, 2, (RR, ADDR),    ldstt, t_ldstt),
15021 TC3(strt,	4200000, f8400e00, 2, (RR, ADDR),    ldstt, t_ldstt),
15022 TC3(strbt,	4600000, f8000e00, 2, (RR, ADDR),    ldstt, t_ldstt),
15023
15024 TC3(stmdb,	9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
15025 TC3(stmfd,     9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
15026
15027 TC3(ldmdb,	9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
15028 TC3(ldmea,	9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
15029
15030 /* V1 instructions with no Thumb analogue at all.  */
15031  CE(rsc,	0e00000,	   3, (RR, oRR, SH), arit),
15032  C3(rscs,	0f00000,	   3, (RR, oRR, SH), arit),
15033
15034  C3(stmib,	9800000,	   2, (RRw, REGLST), ldmstm),
15035  C3(stmfa,	9800000,	   2, (RRw, REGLST), ldmstm),
15036  C3(stmda,	8000000,	   2, (RRw, REGLST), ldmstm),
15037  C3(stmed,	8000000,	   2, (RRw, REGLST), ldmstm),
15038  C3(ldmib,	9900000,	   2, (RRw, REGLST), ldmstm),
15039  C3(ldmed,	9900000,	   2, (RRw, REGLST), ldmstm),
15040  C3(ldmda,	8100000,	   2, (RRw, REGLST), ldmstm),
15041  C3(ldmfa,	8100000,	   2, (RRw, REGLST), ldmstm),
15042
15043#undef ARM_VARIANT
15044#define ARM_VARIANT &arm_ext_v2	/* ARM 2 - multiplies.	*/
15045#undef THUMB_VARIANT
15046#define THUMB_VARIANT &arm_ext_v4t
15047 tCE(mul,	0000090, mul,	   3, (RRnpc, RRnpc, oRR), mul, t_mul),
15048 tC3(muls,	0100090, muls,	   3, (RRnpc, RRnpc, oRR), mul, t_mul),
15049
15050#undef THUMB_VARIANT
15051#define THUMB_VARIANT &arm_ext_v6t2
15052 TCE(mla,	0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
15053  C3(mlas,	0300090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
15054
15055  /* Generic coprocessor instructions.	*/
15056 TCE(cdp,	e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp,    cdp),
15057 TCE(ldc,	c100000, ec100000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
15058 TC3(ldcl,	c500000, ec500000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
15059 TCE(stc,	c000000, ec000000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
15060 TC3(stcl,	c400000, ec400000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
15061 TCE(mcr,	e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
15062 TCE(mrc,	e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b),   co_reg, co_reg),
15063
15064#undef ARM_VARIANT
15065#define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions.  */
15066  CE(swp,	1000090,           3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
15067  C3(swpb,	1400090,           3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
15068
15069#undef ARM_VARIANT
15070#define ARM_VARIANT &arm_ext_v3	/* ARM 6 Status register instructions.	*/
15071 TCE(mrs,	10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
15072 TCE(msr,	120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
15073
15074#undef ARM_VARIANT
15075#define ARM_VARIANT &arm_ext_v3m	 /* ARM 7M long multiplies.  */
15076 TCE(smull,	0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15077  CM(smull,s,	0d00090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15078 TCE(umull,	0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15079  CM(umull,s,	0900090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15080 TCE(smlal,	0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15081  CM(smlal,s,	0f00090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15082 TCE(umlal,	0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15083  CM(umlal,s,	0b00090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15084
15085#undef ARM_VARIANT
15086#define ARM_VARIANT &arm_ext_v4	/* ARM Architecture 4.	*/
15087#undef THUMB_VARIANT
15088#define THUMB_VARIANT &arm_ext_v4t
15089 tC3(ldrh,	01000b0, ldrh,     2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15090 tC3(strh,	00000b0, strh,     2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15091 tC3(ldrsh,	01000f0, ldrsh,    2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15092 tC3(ldrsb,	01000d0, ldrsb,    2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15093 tCM(ld,sh,	01000f0, ldrsh,    2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15094 tCM(ld,sb,	01000d0, ldrsb,    2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15095
15096#undef ARM_VARIANT
15097#define ARM_VARIANT &arm_ext_v4t_5
15098  /* ARM Architecture 4T.  */
15099  /* Note: bx (and blx) are required on V5, even if the processor does
15100     not support Thumb.	 */
15101 TCE(bx,	12fff10, 4700, 1, (RR),	bx, t_bx),
15102
15103#undef ARM_VARIANT
15104#define ARM_VARIANT &arm_ext_v5 /*  ARM Architecture 5T.	 */
15105#undef THUMB_VARIANT
15106#define THUMB_VARIANT &arm_ext_v5t
15107  /* Note: blx has 2 variants; the .value coded here is for
15108     BLX(2).  Only this variant has conditional execution.  */
15109 TCE(blx,	12fff30, 4780, 1, (RR_EXr),			    blx,  t_blx),
15110 TUE(bkpt,	1200070, be00, 1, (oIffffb),			    bkpt, t_bkpt),
15111
15112#undef THUMB_VARIANT
15113#define THUMB_VARIANT &arm_ext_v6t2
15114 TCE(clz,	16f0f10, fab0f080, 2, (RRnpc, RRnpc),		        rd_rm,  t_clz),
15115 TUF(ldc2,	c100000, fc100000, 3, (RCP, RCN, ADDRGLDC),	        lstc,	lstc),
15116 TUF(ldc2l,	c500000, fc500000, 3, (RCP, RCN, ADDRGLDC),		        lstc,	lstc),
15117 TUF(stc2,	c000000, fc000000, 3, (RCP, RCN, ADDRGLDC),	        lstc,	lstc),
15118 TUF(stc2l,	c400000, fc400000, 3, (RCP, RCN, ADDRGLDC),		        lstc,	lstc),
15119 TUF(cdp2,	e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp,    cdp),
15120 TUF(mcr2,	e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
15121 TUF(mrc2,	e100010, fe100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b),   co_reg, co_reg),
15122
15123#undef ARM_VARIANT
15124#define ARM_VARIANT &arm_ext_v5exp /*  ARM Architecture 5TExP.  */
15125 TCE(smlabb,	1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
15126 TCE(smlatb,	10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
15127 TCE(smlabt,	10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
15128 TCE(smlatt,	10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
15129
15130 TCE(smlawb,	1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
15131 TCE(smlawt,	12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
15132
15133 TCE(smlalbb,	1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smlal, t_mlal),
15134 TCE(smlaltb,	14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smlal, t_mlal),
15135 TCE(smlalbt,	14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smlal, t_mlal),
15136 TCE(smlaltt,	14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smlal, t_mlal),
15137
15138 TCE(smulbb,	1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
15139 TCE(smultb,	16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
15140 TCE(smulbt,	16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
15141 TCE(smultt,	16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
15142
15143 TCE(smulwb,	12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
15144 TCE(smulwt,	12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
15145
15146 TCE(qadd,	1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc),	    rd_rm_rn, rd_rm_rn),
15147 TCE(qdadd,	1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc),	    rd_rm_rn, rd_rm_rn),
15148 TCE(qsub,	1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc),	    rd_rm_rn, rd_rm_rn),
15149 TCE(qdsub,	1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc),	    rd_rm_rn, rd_rm_rn),
15150
15151#undef ARM_VARIANT
15152#define ARM_VARIANT &arm_ext_v5e /*  ARM Architecture 5TE.  */
15153 TUF(pld,	450f000, f810f000, 1, (ADDR),		     pld,  t_pld),
15154 TC3(ldrd,	00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
15155 TC3(strd,	00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
15156
15157 TCE(mcrr,	c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15158 TCE(mrrc,	c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15159
15160#undef ARM_VARIANT
15161#define ARM_VARIANT &arm_ext_v5j /*  ARM Architecture 5TEJ.  */
15162 TCE(bxj,	12fff20, f3c08f00, 1, (RR),			  bxj, t_bxj),
15163
15164#undef ARM_VARIANT
15165#define ARM_VARIANT &arm_ext_v6 /*  ARM V6.  */
15166#undef THUMB_VARIANT
15167#define THUMB_VARIANT &arm_ext_v6
15168 TUF(cpsie,     1080000, b660,     2, (CPSF, oI31b),              cpsi,   t_cpsi),
15169 TUF(cpsid,     10c0000, b670,     2, (CPSF, oI31b),              cpsi,   t_cpsi),
15170 tCE(rev,       6bf0f30, rev,      2, (RRnpc, RRnpc),             rd_rm,  t_rev),
15171 tCE(rev16,     6bf0fb0, rev16,    2, (RRnpc, RRnpc),             rd_rm,  t_rev),
15172 tCE(revsh,     6ff0fb0, revsh,    2, (RRnpc, RRnpc),             rd_rm,  t_rev),
15173 tCE(sxth,      6bf0070, sxth,     3, (RRnpc, RRnpc, oROR),       sxth,   t_sxth),
15174 tCE(uxth,      6ff0070, uxth,     3, (RRnpc, RRnpc, oROR),       sxth,   t_sxth),
15175 tCE(sxtb,      6af0070, sxtb,     3, (RRnpc, RRnpc, oROR),       sxth,   t_sxth),
15176 tCE(uxtb,      6ef0070, uxtb,     3, (RRnpc, RRnpc, oROR),       sxth,   t_sxth),
15177 TUF(setend,    1010000, b650,     1, (ENDI),                     setend, t_setend),
15178
15179#undef THUMB_VARIANT
15180#define THUMB_VARIANT &arm_ext_v6t2
15181 TCE(ldrex,	1900f9f, e8500f00, 2, (RRnpc, ADDR),		  ldrex, t_ldrex),
15182 TCE(strex,	1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR),	   strex,  t_strex),
15183 TUF(mcrr2,	c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15184 TUF(mrrc2,	c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15185
15186 TCE(ssat,	6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat,   t_ssat),
15187 TCE(usat,	6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat,   t_usat),
15188
15189/*  ARM V6 not included in V7M (eg. integer SIMD).  */
15190#undef THUMB_VARIANT
15191#define THUMB_VARIANT &arm_ext_v6_notm
15192 TUF(cps,	1020000, f3af8100, 1, (I31b),			  imm0, t_cps),
15193 TCE(pkhbt,	6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll),   pkhbt, t_pkhbt),
15194 TCE(pkhtb,	6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar),   pkhtb, t_pkhtb),
15195 TCE(qadd16,	6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15196 TCE(qadd8,	6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15197 TCE(qaddsubx,	6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15198 TCE(qsub16,	6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15199 TCE(qsub8,	6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15200 TCE(qsubaddx,	6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15201 TCE(sadd16,	6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15202 TCE(sadd8,	6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15203 TCE(saddsubx,	6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15204 TCE(shadd16,	6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15205 TCE(shadd8,	6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15206 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15207 TCE(shsub16,	6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15208 TCE(shsub8,	6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15209 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15210 TCE(ssub16,	6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15211 TCE(ssub8,	6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15212 TCE(ssubaddx,	6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15213 TCE(uadd16,	6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15214 TCE(uadd8,	6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15215 TCE(uaddsubx,	6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15216 TCE(uhadd16,	6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15217 TCE(uhadd8,	6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15218 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15219 TCE(uhsub16,	6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15220 TCE(uhsub8,	6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15221 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15222 TCE(uqadd16,	6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15223 TCE(uqadd8,	6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15224 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15225 TCE(uqsub16,	6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15226 TCE(uqsub8,	6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15227 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15228 TCE(usub16,	6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15229 TCE(usub8,	6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15230 TCE(usubaddx,	6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15231 TUF(rfeia,	8900a00, e990c000, 1, (RRw),			   rfe, rfe),
15232  UF(rfeib,	9900a00,           1, (RRw),			   rfe),
15233  UF(rfeda,	8100a00,           1, (RRw),			   rfe),
15234 TUF(rfedb,	9100a00, e810c000, 1, (RRw),			   rfe, rfe),
15235 TUF(rfefd,	8900a00, e990c000, 1, (RRw),			   rfe, rfe),
15236  UF(rfefa,	9900a00,           1, (RRw),			   rfe),
15237  UF(rfeea,	8100a00,           1, (RRw),			   rfe),
15238 TUF(rfeed,	9100a00, e810c000, 1, (RRw),			   rfe, rfe),
15239 TCE(sxtah,	6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15240 TCE(sxtab16,	6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15241 TCE(sxtab,	6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15242 TCE(sxtb16,	68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR),	   sxth,  t_sxth),
15243 TCE(uxtah,	6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15244 TCE(uxtab16,	6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15245 TCE(uxtab,	6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15246 TCE(uxtb16,	6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR),	   sxth,  t_sxth),
15247 TCE(sel,	6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
15248 TCE(smlad,	7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15249 TCE(smladx,	7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15250 TCE(smlald,	7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15251 TCE(smlaldx,	7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15252 TCE(smlsd,	7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15253 TCE(smlsdx,	7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15254 TCE(smlsld,	7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15255 TCE(smlsldx,	7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15256 TCE(smmla,	7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15257 TCE(smmlar,	7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15258 TCE(smmls,	75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15259 TCE(smmlsr,	75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15260 TCE(smmul,	750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
15261 TCE(smmulr,	750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
15262 TCE(smuad,	700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
15263 TCE(smuadx,	700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
15264 TCE(smusd,	700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
15265 TCE(smusdx,	700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
15266 TUF(srsia,	8c00500, e980c000, 2, (oRRw, I31w),		   srs,  srs),
15267  UF(srsib,	9c00500,           2, (oRRw, I31w),		   srs),
15268  UF(srsda,	8400500,	   2, (oRRw, I31w),		   srs),
15269 TUF(srsdb,	9400500, e800c000, 2, (oRRw, I31w),		   srs,  srs),
15270 TCE(ssat16,	6a00f30, f3200000, 3, (RRnpc, I16, RRnpc),	   ssat16, t_ssat16),
15271 TCE(umaal,	0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,  t_mlal),
15272 TCE(usad8,	780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc),	   smul,   t_simd),
15273 TCE(usada8,	7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla,   t_mla),
15274 TCE(usat16,	6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc),	   usat16, t_usat16),
15275
15276#undef ARM_VARIANT
15277#define ARM_VARIANT &arm_ext_v6k
15278#undef THUMB_VARIANT
15279#define THUMB_VARIANT &arm_ext_v6k
15280 tCE(yield,	320f001, yield,    0, (), noargs, t_hint),
15281 tCE(wfe,	320f002, wfe,      0, (), noargs, t_hint),
15282 tCE(wfi,	320f003, wfi,      0, (), noargs, t_hint),
15283 tCE(sev,	320f004, sev,      0, (), noargs, t_hint),
15284
15285#undef THUMB_VARIANT
15286#define THUMB_VARIANT &arm_ext_v6_notm
15287 TCE(ldrexd,	1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb),        ldrexd, t_ldrexd),
15288 TCE(strexd,	1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
15289
15290#undef THUMB_VARIANT
15291#define THUMB_VARIANT &arm_ext_v6t2
15292 TCE(ldrexb,	1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb),	              rd_rn,  rd_rn),
15293 TCE(ldrexh,	1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb),	              rd_rn,  rd_rn),
15294 TCE(strexb,	1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR),           strex,  rm_rd_rn),
15295 TCE(strexh,	1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR),           strex,  rm_rd_rn),
15296 TUF(clrex,	57ff01f, f3bf8f2f, 0, (),			      noargs, noargs),
15297
15298#undef ARM_VARIANT
15299#define ARM_VARIANT &arm_ext_v6z
15300 TCE(smc,	1600070, f7f08000, 1, (EXPi), smc, t_smc),
15301
15302#undef ARM_VARIANT
15303#define ARM_VARIANT &arm_ext_v6t2
15304 TCE(bfc,	7c0001f, f36f0000, 3, (RRnpc, I31, I32),	   bfc, t_bfc),
15305 TCE(bfi,	7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
15306 TCE(sbfx,	7a00050, f3400000, 4, (RR, RR, I31, I32),	   bfx, t_bfx),
15307 TCE(ubfx,	7e00050, f3c00000, 4, (RR, RR, I31, I32),	   bfx, t_bfx),
15308
15309 TCE(mls,	0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
15310 TCE(movw,	3000000, f2400000, 2, (RRnpc, HALF),		    mov16, t_mov16),
15311 TCE(movt,	3400000, f2c00000, 2, (RRnpc, HALF),		    mov16, t_mov16),
15312 TCE(rbit,	6ff0f30, fa90f0a0, 2, (RR, RR),			    rd_rm, t_rbit),
15313
15314 TC3(ldrht,	03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15315 TC3(ldrsht,	03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15316 TC3(ldrsbt,	03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15317 TC3(strht,	02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15318
15319  UT(cbnz,      b900,    2, (RR, EXP), t_cbz),
15320  UT(cbz,       b100,    2, (RR, EXP), t_cbz),
15321 /* ARM does not really have an IT instruction, so always allow it.  */
15322#undef ARM_VARIANT
15323#define ARM_VARIANT &arm_ext_v1
15324 TUE(it,        0, bf08, 1, (COND),    it, t_it),
15325 TUE(itt,       0, bf0c, 1, (COND),    it, t_it),
15326 TUE(ite,       0, bf04, 1, (COND),    it, t_it),
15327 TUE(ittt,      0, bf0e, 1, (COND),    it, t_it),
15328 TUE(itet,      0, bf06, 1, (COND),    it, t_it),
15329 TUE(itte,      0, bf0a, 1, (COND),    it, t_it),
15330 TUE(itee,      0, bf02, 1, (COND),    it, t_it),
15331 TUE(itttt,     0, bf0f, 1, (COND),    it, t_it),
15332 TUE(itett,     0, bf07, 1, (COND),    it, t_it),
15333 TUE(ittet,     0, bf0b, 1, (COND),    it, t_it),
15334 TUE(iteet,     0, bf03, 1, (COND),    it, t_it),
15335 TUE(ittte,     0, bf0d, 1, (COND),    it, t_it),
15336 TUE(itete,     0, bf05, 1, (COND),    it, t_it),
15337 TUE(ittee,     0, bf09, 1, (COND),    it, t_it),
15338 TUE(iteee,     0, bf01, 1, (COND),    it, t_it),
15339
15340 /* Thumb2 only instructions.  */
15341#undef ARM_VARIANT
15342#define ARM_VARIANT NULL
15343
15344 TCE(addw,	0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
15345 TCE(subw,	0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
15346 TCE(tbb,       0, e8d0f000, 1, (TB), 0, t_tb),
15347 TCE(tbh,       0, e8d0f010, 1, (TB), 0, t_tb),
15348
15349 /* Thumb-2 hardware division instructions (R and M profiles only).  */
15350#undef THUMB_VARIANT
15351#define THUMB_VARIANT &arm_ext_div
15352 TCE(sdiv,	0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
15353 TCE(udiv,	0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
15354
15355 /* ARM V7 instructions.  */
15356#undef ARM_VARIANT
15357#define ARM_VARIANT &arm_ext_v7
15358#undef THUMB_VARIANT
15359#define THUMB_VARIANT &arm_ext_v7
15360 TUF(pli,	450f000, f910f000, 1, (ADDR),	  pli,	    t_pld),
15361 TCE(dbg,	320f0f0, f3af80f0, 1, (I15),	  dbg,	    t_dbg),
15362 TUF(dmb,	57ff050, f3bf8f50, 1, (oBARRIER), barrier,  t_barrier),
15363 TUF(dsb,	57ff040, f3bf8f40, 1, (oBARRIER), barrier,  t_barrier),
15364 TUF(isb,	57ff060, f3bf8f60, 1, (oBARRIER), barrier,  t_barrier),
15365
15366#undef ARM_VARIANT
15367#define ARM_VARIANT &fpu_fpa_ext_v1  /* Core FPA instruction set (V1).  */
15368 cCE(wfs,	e200110, 1, (RR),	     rd),
15369 cCE(rfs,	e300110, 1, (RR),	     rd),
15370 cCE(wfc,	e400110, 1, (RR),	     rd),
15371 cCE(rfc,	e500110, 1, (RR),	     rd),
15372
15373 cCL(ldfs,	c100100, 2, (RF, ADDRGLDC),  rd_cpaddr),
15374 cCL(ldfd,	c108100, 2, (RF, ADDRGLDC),  rd_cpaddr),
15375 cCL(ldfe,	c500100, 2, (RF, ADDRGLDC),  rd_cpaddr),
15376 cCL(ldfp,	c508100, 2, (RF, ADDRGLDC),  rd_cpaddr),
15377
15378 cCL(stfs,	c000100, 2, (RF, ADDRGLDC),  rd_cpaddr),
15379 cCL(stfd,	c008100, 2, (RF, ADDRGLDC),  rd_cpaddr),
15380 cCL(stfe,	c400100, 2, (RF, ADDRGLDC),  rd_cpaddr),
15381 cCL(stfp,	c408100, 2, (RF, ADDRGLDC),  rd_cpaddr),
15382
15383 cCL(mvfs,	e008100, 2, (RF, RF_IF),     rd_rm),
15384 cCL(mvfsp,	e008120, 2, (RF, RF_IF),     rd_rm),
15385 cCL(mvfsm,	e008140, 2, (RF, RF_IF),     rd_rm),
15386 cCL(mvfsz,	e008160, 2, (RF, RF_IF),     rd_rm),
15387 cCL(mvfd,	e008180, 2, (RF, RF_IF),     rd_rm),
15388 cCL(mvfdp,	e0081a0, 2, (RF, RF_IF),     rd_rm),
15389 cCL(mvfdm,	e0081c0, 2, (RF, RF_IF),     rd_rm),
15390 cCL(mvfdz,	e0081e0, 2, (RF, RF_IF),     rd_rm),
15391 cCL(mvfe,	e088100, 2, (RF, RF_IF),     rd_rm),
15392 cCL(mvfep,	e088120, 2, (RF, RF_IF),     rd_rm),
15393 cCL(mvfem,	e088140, 2, (RF, RF_IF),     rd_rm),
15394 cCL(mvfez,	e088160, 2, (RF, RF_IF),     rd_rm),
15395
15396 cCL(mnfs,	e108100, 2, (RF, RF_IF),     rd_rm),
15397 cCL(mnfsp,	e108120, 2, (RF, RF_IF),     rd_rm),
15398 cCL(mnfsm,	e108140, 2, (RF, RF_IF),     rd_rm),
15399 cCL(mnfsz,	e108160, 2, (RF, RF_IF),     rd_rm),
15400 cCL(mnfd,	e108180, 2, (RF, RF_IF),     rd_rm),
15401 cCL(mnfdp,	e1081a0, 2, (RF, RF_IF),     rd_rm),
15402 cCL(mnfdm,	e1081c0, 2, (RF, RF_IF),     rd_rm),
15403 cCL(mnfdz,	e1081e0, 2, (RF, RF_IF),     rd_rm),
15404 cCL(mnfe,	e188100, 2, (RF, RF_IF),     rd_rm),
15405 cCL(mnfep,	e188120, 2, (RF, RF_IF),     rd_rm),
15406 cCL(mnfem,	e188140, 2, (RF, RF_IF),     rd_rm),
15407 cCL(mnfez,	e188160, 2, (RF, RF_IF),     rd_rm),
15408
15409 cCL(abss,	e208100, 2, (RF, RF_IF),     rd_rm),
15410 cCL(abssp,	e208120, 2, (RF, RF_IF),     rd_rm),
15411 cCL(abssm,	e208140, 2, (RF, RF_IF),     rd_rm),
15412 cCL(abssz,	e208160, 2, (RF, RF_IF),     rd_rm),
15413 cCL(absd,	e208180, 2, (RF, RF_IF),     rd_rm),
15414 cCL(absdp,	e2081a0, 2, (RF, RF_IF),     rd_rm),
15415 cCL(absdm,	e2081c0, 2, (RF, RF_IF),     rd_rm),
15416 cCL(absdz,	e2081e0, 2, (RF, RF_IF),     rd_rm),
15417 cCL(abse,	e288100, 2, (RF, RF_IF),     rd_rm),
15418 cCL(absep,	e288120, 2, (RF, RF_IF),     rd_rm),
15419 cCL(absem,	e288140, 2, (RF, RF_IF),     rd_rm),
15420 cCL(absez,	e288160, 2, (RF, RF_IF),     rd_rm),
15421
15422 cCL(rnds,	e308100, 2, (RF, RF_IF),     rd_rm),
15423 cCL(rndsp,	e308120, 2, (RF, RF_IF),     rd_rm),
15424 cCL(rndsm,	e308140, 2, (RF, RF_IF),     rd_rm),
15425 cCL(rndsz,	e308160, 2, (RF, RF_IF),     rd_rm),
15426 cCL(rndd,	e308180, 2, (RF, RF_IF),     rd_rm),
15427 cCL(rnddp,	e3081a0, 2, (RF, RF_IF),     rd_rm),
15428 cCL(rnddm,	e3081c0, 2, (RF, RF_IF),     rd_rm),
15429 cCL(rnddz,	e3081e0, 2, (RF, RF_IF),     rd_rm),
15430 cCL(rnde,	e388100, 2, (RF, RF_IF),     rd_rm),
15431 cCL(rndep,	e388120, 2, (RF, RF_IF),     rd_rm),
15432 cCL(rndem,	e388140, 2, (RF, RF_IF),     rd_rm),
15433 cCL(rndez,	e388160, 2, (RF, RF_IF),     rd_rm),
15434
15435 cCL(sqts,	e408100, 2, (RF, RF_IF),     rd_rm),
15436 cCL(sqtsp,	e408120, 2, (RF, RF_IF),     rd_rm),
15437 cCL(sqtsm,	e408140, 2, (RF, RF_IF),     rd_rm),
15438 cCL(sqtsz,	e408160, 2, (RF, RF_IF),     rd_rm),
15439 cCL(sqtd,	e408180, 2, (RF, RF_IF),     rd_rm),
15440 cCL(sqtdp,	e4081a0, 2, (RF, RF_IF),     rd_rm),
15441 cCL(sqtdm,	e4081c0, 2, (RF, RF_IF),     rd_rm),
15442 cCL(sqtdz,	e4081e0, 2, (RF, RF_IF),     rd_rm),
15443 cCL(sqte,	e488100, 2, (RF, RF_IF),     rd_rm),
15444 cCL(sqtep,	e488120, 2, (RF, RF_IF),     rd_rm),
15445 cCL(sqtem,	e488140, 2, (RF, RF_IF),     rd_rm),
15446 cCL(sqtez,	e488160, 2, (RF, RF_IF),     rd_rm),
15447
15448 cCL(logs,	e508100, 2, (RF, RF_IF),     rd_rm),
15449 cCL(logsp,	e508120, 2, (RF, RF_IF),     rd_rm),
15450 cCL(logsm,	e508140, 2, (RF, RF_IF),     rd_rm),
15451 cCL(logsz,	e508160, 2, (RF, RF_IF),     rd_rm),
15452 cCL(logd,	e508180, 2, (RF, RF_IF),     rd_rm),
15453 cCL(logdp,	e5081a0, 2, (RF, RF_IF),     rd_rm),
15454 cCL(logdm,	e5081c0, 2, (RF, RF_IF),     rd_rm),
15455 cCL(logdz,	e5081e0, 2, (RF, RF_IF),     rd_rm),
15456 cCL(loge,	e588100, 2, (RF, RF_IF),     rd_rm),
15457 cCL(logep,	e588120, 2, (RF, RF_IF),     rd_rm),
15458 cCL(logem,	e588140, 2, (RF, RF_IF),     rd_rm),
15459 cCL(logez,	e588160, 2, (RF, RF_IF),     rd_rm),
15460
15461 cCL(lgns,	e608100, 2, (RF, RF_IF),     rd_rm),
15462 cCL(lgnsp,	e608120, 2, (RF, RF_IF),     rd_rm),
15463 cCL(lgnsm,	e608140, 2, (RF, RF_IF),     rd_rm),
15464 cCL(lgnsz,	e608160, 2, (RF, RF_IF),     rd_rm),
15465 cCL(lgnd,	e608180, 2, (RF, RF_IF),     rd_rm),
15466 cCL(lgndp,	e6081a0, 2, (RF, RF_IF),     rd_rm),
15467 cCL(lgndm,	e6081c0, 2, (RF, RF_IF),     rd_rm),
15468 cCL(lgndz,	e6081e0, 2, (RF, RF_IF),     rd_rm),
15469 cCL(lgne,	e688100, 2, (RF, RF_IF),     rd_rm),
15470 cCL(lgnep,	e688120, 2, (RF, RF_IF),     rd_rm),
15471 cCL(lgnem,	e688140, 2, (RF, RF_IF),     rd_rm),
15472 cCL(lgnez,	e688160, 2, (RF, RF_IF),     rd_rm),
15473
15474 cCL(exps,	e708100, 2, (RF, RF_IF),     rd_rm),
15475 cCL(expsp,	e708120, 2, (RF, RF_IF),     rd_rm),
15476 cCL(expsm,	e708140, 2, (RF, RF_IF),     rd_rm),
15477 cCL(expsz,	e708160, 2, (RF, RF_IF),     rd_rm),
15478 cCL(expd,	e708180, 2, (RF, RF_IF),     rd_rm),
15479 cCL(expdp,	e7081a0, 2, (RF, RF_IF),     rd_rm),
15480 cCL(expdm,	e7081c0, 2, (RF, RF_IF),     rd_rm),
15481 cCL(expdz,	e7081e0, 2, (RF, RF_IF),     rd_rm),
15482 cCL(expe,	e788100, 2, (RF, RF_IF),     rd_rm),
15483 cCL(expep,	e788120, 2, (RF, RF_IF),     rd_rm),
15484 cCL(expem,	e788140, 2, (RF, RF_IF),     rd_rm),
15485 cCL(expdz,	e788160, 2, (RF, RF_IF),     rd_rm),
15486
15487 cCL(sins,	e808100, 2, (RF, RF_IF),     rd_rm),
15488 cCL(sinsp,	e808120, 2, (RF, RF_IF),     rd_rm),
15489 cCL(sinsm,	e808140, 2, (RF, RF_IF),     rd_rm),
15490 cCL(sinsz,	e808160, 2, (RF, RF_IF),     rd_rm),
15491 cCL(sind,	e808180, 2, (RF, RF_IF),     rd_rm),
15492 cCL(sindp,	e8081a0, 2, (RF, RF_IF),     rd_rm),
15493 cCL(sindm,	e8081c0, 2, (RF, RF_IF),     rd_rm),
15494 cCL(sindz,	e8081e0, 2, (RF, RF_IF),     rd_rm),
15495 cCL(sine,	e888100, 2, (RF, RF_IF),     rd_rm),
15496 cCL(sinep,	e888120, 2, (RF, RF_IF),     rd_rm),
15497 cCL(sinem,	e888140, 2, (RF, RF_IF),     rd_rm),
15498 cCL(sinez,	e888160, 2, (RF, RF_IF),     rd_rm),
15499
15500 cCL(coss,	e908100, 2, (RF, RF_IF),     rd_rm),
15501 cCL(cossp,	e908120, 2, (RF, RF_IF),     rd_rm),
15502 cCL(cossm,	e908140, 2, (RF, RF_IF),     rd_rm),
15503 cCL(cossz,	e908160, 2, (RF, RF_IF),     rd_rm),
15504 cCL(cosd,	e908180, 2, (RF, RF_IF),     rd_rm),
15505 cCL(cosdp,	e9081a0, 2, (RF, RF_IF),     rd_rm),
15506 cCL(cosdm,	e9081c0, 2, (RF, RF_IF),     rd_rm),
15507 cCL(cosdz,	e9081e0, 2, (RF, RF_IF),     rd_rm),
15508 cCL(cose,	e988100, 2, (RF, RF_IF),     rd_rm),
15509 cCL(cosep,	e988120, 2, (RF, RF_IF),     rd_rm),
15510 cCL(cosem,	e988140, 2, (RF, RF_IF),     rd_rm),
15511 cCL(cosez,	e988160, 2, (RF, RF_IF),     rd_rm),
15512
15513 cCL(tans,	ea08100, 2, (RF, RF_IF),     rd_rm),
15514 cCL(tansp,	ea08120, 2, (RF, RF_IF),     rd_rm),
15515 cCL(tansm,	ea08140, 2, (RF, RF_IF),     rd_rm),
15516 cCL(tansz,	ea08160, 2, (RF, RF_IF),     rd_rm),
15517 cCL(tand,	ea08180, 2, (RF, RF_IF),     rd_rm),
15518 cCL(tandp,	ea081a0, 2, (RF, RF_IF),     rd_rm),
15519 cCL(tandm,	ea081c0, 2, (RF, RF_IF),     rd_rm),
15520 cCL(tandz,	ea081e0, 2, (RF, RF_IF),     rd_rm),
15521 cCL(tane,	ea88100, 2, (RF, RF_IF),     rd_rm),
15522 cCL(tanep,	ea88120, 2, (RF, RF_IF),     rd_rm),
15523 cCL(tanem,	ea88140, 2, (RF, RF_IF),     rd_rm),
15524 cCL(tanez,	ea88160, 2, (RF, RF_IF),     rd_rm),
15525
15526 cCL(asns,	eb08100, 2, (RF, RF_IF),     rd_rm),
15527 cCL(asnsp,	eb08120, 2, (RF, RF_IF),     rd_rm),
15528 cCL(asnsm,	eb08140, 2, (RF, RF_IF),     rd_rm),
15529 cCL(asnsz,	eb08160, 2, (RF, RF_IF),     rd_rm),
15530 cCL(asnd,	eb08180, 2, (RF, RF_IF),     rd_rm),
15531 cCL(asndp,	eb081a0, 2, (RF, RF_IF),     rd_rm),
15532 cCL(asndm,	eb081c0, 2, (RF, RF_IF),     rd_rm),
15533 cCL(asndz,	eb081e0, 2, (RF, RF_IF),     rd_rm),
15534 cCL(asne,	eb88100, 2, (RF, RF_IF),     rd_rm),
15535 cCL(asnep,	eb88120, 2, (RF, RF_IF),     rd_rm),
15536 cCL(asnem,	eb88140, 2, (RF, RF_IF),     rd_rm),
15537 cCL(asnez,	eb88160, 2, (RF, RF_IF),     rd_rm),
15538
15539 cCL(acss,	ec08100, 2, (RF, RF_IF),     rd_rm),
15540 cCL(acssp,	ec08120, 2, (RF, RF_IF),     rd_rm),
15541 cCL(acssm,	ec08140, 2, (RF, RF_IF),     rd_rm),
15542 cCL(acssz,	ec08160, 2, (RF, RF_IF),     rd_rm),
15543 cCL(acsd,	ec08180, 2, (RF, RF_IF),     rd_rm),
15544 cCL(acsdp,	ec081a0, 2, (RF, RF_IF),     rd_rm),
15545 cCL(acsdm,	ec081c0, 2, (RF, RF_IF),     rd_rm),
15546 cCL(acsdz,	ec081e0, 2, (RF, RF_IF),     rd_rm),
15547 cCL(acse,	ec88100, 2, (RF, RF_IF),     rd_rm),
15548 cCL(acsep,	ec88120, 2, (RF, RF_IF),     rd_rm),
15549 cCL(acsem,	ec88140, 2, (RF, RF_IF),     rd_rm),
15550 cCL(acsez,	ec88160, 2, (RF, RF_IF),     rd_rm),
15551
15552 cCL(atns,	ed08100, 2, (RF, RF_IF),     rd_rm),
15553 cCL(atnsp,	ed08120, 2, (RF, RF_IF),     rd_rm),
15554 cCL(atnsm,	ed08140, 2, (RF, RF_IF),     rd_rm),
15555 cCL(atnsz,	ed08160, 2, (RF, RF_IF),     rd_rm),
15556 cCL(atnd,	ed08180, 2, (RF, RF_IF),     rd_rm),
15557 cCL(atndp,	ed081a0, 2, (RF, RF_IF),     rd_rm),
15558 cCL(atndm,	ed081c0, 2, (RF, RF_IF),     rd_rm),
15559 cCL(atndz,	ed081e0, 2, (RF, RF_IF),     rd_rm),
15560 cCL(atne,	ed88100, 2, (RF, RF_IF),     rd_rm),
15561 cCL(atnep,	ed88120, 2, (RF, RF_IF),     rd_rm),
15562 cCL(atnem,	ed88140, 2, (RF, RF_IF),     rd_rm),
15563 cCL(atnez,	ed88160, 2, (RF, RF_IF),     rd_rm),
15564
15565 cCL(urds,	ee08100, 2, (RF, RF_IF),     rd_rm),
15566 cCL(urdsp,	ee08120, 2, (RF, RF_IF),     rd_rm),
15567 cCL(urdsm,	ee08140, 2, (RF, RF_IF),     rd_rm),
15568 cCL(urdsz,	ee08160, 2, (RF, RF_IF),     rd_rm),
15569 cCL(urdd,	ee08180, 2, (RF, RF_IF),     rd_rm),
15570 cCL(urddp,	ee081a0, 2, (RF, RF_IF),     rd_rm),
15571 cCL(urddm,	ee081c0, 2, (RF, RF_IF),     rd_rm),
15572 cCL(urddz,	ee081e0, 2, (RF, RF_IF),     rd_rm),
15573 cCL(urde,	ee88100, 2, (RF, RF_IF),     rd_rm),
15574 cCL(urdep,	ee88120, 2, (RF, RF_IF),     rd_rm),
15575 cCL(urdem,	ee88140, 2, (RF, RF_IF),     rd_rm),
15576 cCL(urdez,	ee88160, 2, (RF, RF_IF),     rd_rm),
15577
15578 cCL(nrms,	ef08100, 2, (RF, RF_IF),     rd_rm),
15579 cCL(nrmsp,	ef08120, 2, (RF, RF_IF),     rd_rm),
15580 cCL(nrmsm,	ef08140, 2, (RF, RF_IF),     rd_rm),
15581 cCL(nrmsz,	ef08160, 2, (RF, RF_IF),     rd_rm),
15582 cCL(nrmd,	ef08180, 2, (RF, RF_IF),     rd_rm),
15583 cCL(nrmdp,	ef081a0, 2, (RF, RF_IF),     rd_rm),
15584 cCL(nrmdm,	ef081c0, 2, (RF, RF_IF),     rd_rm),
15585 cCL(nrmdz,	ef081e0, 2, (RF, RF_IF),     rd_rm),
15586 cCL(nrme,	ef88100, 2, (RF, RF_IF),     rd_rm),
15587 cCL(nrmep,	ef88120, 2, (RF, RF_IF),     rd_rm),
15588 cCL(nrmem,	ef88140, 2, (RF, RF_IF),     rd_rm),
15589 cCL(nrmez,	ef88160, 2, (RF, RF_IF),     rd_rm),
15590
15591 cCL(adfs,	e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
15592 cCL(adfsp,	e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
15593 cCL(adfsm,	e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
15594 cCL(adfsz,	e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
15595 cCL(adfd,	e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
15596 cCL(adfdp,	e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15597 cCL(adfdm,	e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15598 cCL(adfdz,	e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15599 cCL(adfe,	e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
15600 cCL(adfep,	e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
15601 cCL(adfem,	e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
15602 cCL(adfez,	e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
15603
15604 cCL(sufs,	e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
15605 cCL(sufsp,	e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
15606 cCL(sufsm,	e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
15607 cCL(sufsz,	e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
15608 cCL(sufd,	e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
15609 cCL(sufdp,	e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15610 cCL(sufdm,	e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15611 cCL(sufdz,	e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15612 cCL(sufe,	e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
15613 cCL(sufep,	e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
15614 cCL(sufem,	e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
15615 cCL(sufez,	e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
15616
15617 cCL(rsfs,	e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
15618 cCL(rsfsp,	e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
15619 cCL(rsfsm,	e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
15620 cCL(rsfsz,	e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
15621 cCL(rsfd,	e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
15622 cCL(rsfdp,	e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15623 cCL(rsfdm,	e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15624 cCL(rsfdz,	e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15625 cCL(rsfe,	e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
15626 cCL(rsfep,	e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
15627 cCL(rsfem,	e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
15628 cCL(rsfez,	e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
15629
15630 cCL(mufs,	e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
15631 cCL(mufsp,	e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
15632 cCL(mufsm,	e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
15633 cCL(mufsz,	e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
15634 cCL(mufd,	e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
15635 cCL(mufdp,	e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15636 cCL(mufdm,	e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15637 cCL(mufdz,	e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15638 cCL(mufe,	e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
15639 cCL(mufep,	e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
15640 cCL(mufem,	e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
15641 cCL(mufez,	e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
15642
15643 cCL(dvfs,	e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
15644 cCL(dvfsp,	e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
15645 cCL(dvfsm,	e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
15646 cCL(dvfsz,	e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
15647 cCL(dvfd,	e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
15648 cCL(dvfdp,	e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15649 cCL(dvfdm,	e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15650 cCL(dvfdz,	e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15651 cCL(dvfe,	e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
15652 cCL(dvfep,	e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
15653 cCL(dvfem,	e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
15654 cCL(dvfez,	e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
15655
15656 cCL(rdfs,	e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
15657 cCL(rdfsp,	e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
15658 cCL(rdfsm,	e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
15659 cCL(rdfsz,	e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
15660 cCL(rdfd,	e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
15661 cCL(rdfdp,	e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15662 cCL(rdfdm,	e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15663 cCL(rdfdz,	e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15664 cCL(rdfe,	e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
15665 cCL(rdfep,	e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
15666 cCL(rdfem,	e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
15667 cCL(rdfez,	e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
15668
15669 cCL(pows,	e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
15670 cCL(powsp,	e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
15671 cCL(powsm,	e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
15672 cCL(powsz,	e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
15673 cCL(powd,	e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
15674 cCL(powdp,	e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15675 cCL(powdm,	e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15676 cCL(powdz,	e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15677 cCL(powe,	e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
15678 cCL(powep,	e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
15679 cCL(powem,	e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
15680 cCL(powez,	e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
15681
15682 cCL(rpws,	e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
15683 cCL(rpwsp,	e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
15684 cCL(rpwsm,	e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
15685 cCL(rpwsz,	e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
15686 cCL(rpwd,	e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
15687 cCL(rpwdp,	e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15688 cCL(rpwdm,	e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15689 cCL(rpwdz,	e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15690 cCL(rpwe,	e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
15691 cCL(rpwep,	e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
15692 cCL(rpwem,	e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
15693 cCL(rpwez,	e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
15694
15695 cCL(rmfs,	e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
15696 cCL(rmfsp,	e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
15697 cCL(rmfsm,	e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
15698 cCL(rmfsz,	e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
15699 cCL(rmfd,	e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
15700 cCL(rmfdp,	e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15701 cCL(rmfdm,	e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15702 cCL(rmfdz,	e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15703 cCL(rmfe,	e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
15704 cCL(rmfep,	e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
15705 cCL(rmfem,	e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
15706 cCL(rmfez,	e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
15707
15708 cCL(fmls,	e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
15709 cCL(fmlsp,	e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
15710 cCL(fmlsm,	e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
15711 cCL(fmlsz,	e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
15712 cCL(fmld,	e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
15713 cCL(fmldp,	e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15714 cCL(fmldm,	e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15715 cCL(fmldz,	e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15716 cCL(fmle,	e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
15717 cCL(fmlep,	e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
15718 cCL(fmlem,	e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
15719 cCL(fmlez,	e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
15720
15721 cCL(fdvs,	ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15722 cCL(fdvsp,	ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15723 cCL(fdvsm,	ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15724 cCL(fdvsz,	ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15725 cCL(fdvd,	ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15726 cCL(fdvdp,	ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15727 cCL(fdvdm,	ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15728 cCL(fdvdz,	ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15729 cCL(fdve,	ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15730 cCL(fdvep,	ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15731 cCL(fdvem,	ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15732 cCL(fdvez,	ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15733
15734 cCL(frds,	eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15735 cCL(frdsp,	eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15736 cCL(frdsm,	eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15737 cCL(frdsz,	eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15738 cCL(frdd,	eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15739 cCL(frddp,	eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15740 cCL(frddm,	eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15741 cCL(frddz,	eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15742 cCL(frde,	eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15743 cCL(frdep,	eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15744 cCL(frdem,	eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15745 cCL(frdez,	eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15746
15747 cCL(pols,	ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15748 cCL(polsp,	ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15749 cCL(polsm,	ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15750 cCL(polsz,	ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15751 cCL(pold,	ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15752 cCL(poldp,	ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15753 cCL(poldm,	ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15754 cCL(poldz,	ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15755 cCL(pole,	ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15756 cCL(polep,	ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15757 cCL(polem,	ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15758 cCL(polez,	ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15759
15760 cCE(cmf,	e90f110, 2, (RF, RF_IF),     fpa_cmp),
15761 C3E(cmfe,	ed0f110, 2, (RF, RF_IF),     fpa_cmp),
15762 cCE(cnf,	eb0f110, 2, (RF, RF_IF),     fpa_cmp),
15763 C3E(cnfe,	ef0f110, 2, (RF, RF_IF),     fpa_cmp),
15764
15765 cCL(flts,	e000110, 2, (RF, RR),	     rn_rd),
15766 cCL(fltsp,	e000130, 2, (RF, RR),	     rn_rd),
15767 cCL(fltsm,	e000150, 2, (RF, RR),	     rn_rd),
15768 cCL(fltsz,	e000170, 2, (RF, RR),	     rn_rd),
15769 cCL(fltd,	e000190, 2, (RF, RR),	     rn_rd),
15770 cCL(fltdp,	e0001b0, 2, (RF, RR),	     rn_rd),
15771 cCL(fltdm,	e0001d0, 2, (RF, RR),	     rn_rd),
15772 cCL(fltdz,	e0001f0, 2, (RF, RR),	     rn_rd),
15773 cCL(flte,	e080110, 2, (RF, RR),	     rn_rd),
15774 cCL(fltep,	e080130, 2, (RF, RR),	     rn_rd),
15775 cCL(fltem,	e080150, 2, (RF, RR),	     rn_rd),
15776 cCL(fltez,	e080170, 2, (RF, RR),	     rn_rd),
15777
15778  /* The implementation of the FIX instruction is broken on some
15779     assemblers, in that it accepts a precision specifier as well as a
15780     rounding specifier, despite the fact that this is meaningless.
15781     To be more compatible, we accept it as well, though of course it
15782     does not set any bits.  */
15783 cCE(fix,	e100110, 2, (RR, RF),	     rd_rm),
15784 cCL(fixp,	e100130, 2, (RR, RF),	     rd_rm),
15785 cCL(fixm,	e100150, 2, (RR, RF),	     rd_rm),
15786 cCL(fixz,	e100170, 2, (RR, RF),	     rd_rm),
15787 cCL(fixsp,	e100130, 2, (RR, RF),	     rd_rm),
15788 cCL(fixsm,	e100150, 2, (RR, RF),	     rd_rm),
15789 cCL(fixsz,	e100170, 2, (RR, RF),	     rd_rm),
15790 cCL(fixdp,	e100130, 2, (RR, RF),	     rd_rm),
15791 cCL(fixdm,	e100150, 2, (RR, RF),	     rd_rm),
15792 cCL(fixdz,	e100170, 2, (RR, RF),	     rd_rm),
15793 cCL(fixep,	e100130, 2, (RR, RF),	     rd_rm),
15794 cCL(fixem,	e100150, 2, (RR, RF),	     rd_rm),
15795 cCL(fixez,	e100170, 2, (RR, RF),	     rd_rm),
15796
15797  /* Instructions that were new with the real FPA, call them V2.  */
15798#undef ARM_VARIANT
15799#define ARM_VARIANT &fpu_fpa_ext_v2
15800 cCE(lfm,	c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15801 cCL(lfmfd,	c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15802 cCL(lfmea,	d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15803 cCE(sfm,	c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15804 cCL(sfmfd,	d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15805 cCL(sfmea,	c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15806
15807#undef ARM_VARIANT
15808#define ARM_VARIANT &fpu_vfp_ext_v1xd  /* VFP V1xD (single precision).  */
15809  /* Moves and type conversions.  */
15810 cCE(fcpys,	eb00a40, 2, (RVS, RVS),	      vfp_sp_monadic),
15811 cCE(fmrs,	e100a10, 2, (RR, RVS),	      vfp_reg_from_sp),
15812 cCE(fmsr,	e000a10, 2, (RVS, RR),	      vfp_sp_from_reg),
15813 cCE(fmstat,	ef1fa10, 0, (),		      noargs),
15814 cCE(fsitos,	eb80ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
15815 cCE(fuitos,	eb80a40, 2, (RVS, RVS),	      vfp_sp_monadic),
15816 cCE(ftosis,	ebd0a40, 2, (RVS, RVS),	      vfp_sp_monadic),
15817 cCE(ftosizs,	ebd0ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
15818 cCE(ftouis,	ebc0a40, 2, (RVS, RVS),	      vfp_sp_monadic),
15819 cCE(ftouizs,	ebc0ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
15820 cCE(fmrx,	ef00a10, 2, (RR, RVC),	      rd_rn),
15821 cCE(fmxr,	ee00a10, 2, (RVC, RR),	      rn_rd),
15822 cCE(vmrs,	ef00a10, 2, (APSR_RR, RVC),   vfp_vmrs),
15823 cCE(vmsr,	ee00a10, 2, (RVC, RR),        vfp_vmsr),
15824
15825  /* Memory operations.	 */
15826 cCE(flds,	d100a00, 2, (RVS, ADDRGLDC),  vfp_sp_ldst),
15827 cCE(fsts,	d000a00, 2, (RVS, ADDRGLDC),  vfp_sp_ldst),
15828 cCE(fldmias,	c900a00, 2, (RRw, VRSLST),    vfp_sp_ldstmia),
15829 cCE(fldmfds,	c900a00, 2, (RRw, VRSLST),    vfp_sp_ldstmia),
15830 cCE(fldmdbs,	d300a00, 2, (RRw, VRSLST),    vfp_sp_ldstmdb),
15831 cCE(fldmeas,	d300a00, 2, (RRw, VRSLST),    vfp_sp_ldstmdb),
15832 cCE(fldmiax,	c900b00, 2, (RRw, VRDLST),    vfp_xp_ldstmia),
15833 cCE(fldmfdx,	c900b00, 2, (RRw, VRDLST),    vfp_xp_ldstmia),
15834 cCE(fldmdbx,	d300b00, 2, (RRw, VRDLST),    vfp_xp_ldstmdb),
15835 cCE(fldmeax,	d300b00, 2, (RRw, VRDLST),    vfp_xp_ldstmdb),
15836 cCE(fstmias,	c800a00, 2, (RRw, VRSLST),    vfp_sp_ldstmia),
15837 cCE(fstmeas,	c800a00, 2, (RRw, VRSLST),    vfp_sp_ldstmia),
15838 cCE(fstmdbs,	d200a00, 2, (RRw, VRSLST),    vfp_sp_ldstmdb),
15839 cCE(fstmfds,	d200a00, 2, (RRw, VRSLST),    vfp_sp_ldstmdb),
15840 cCE(fstmiax,	c800b00, 2, (RRw, VRDLST),    vfp_xp_ldstmia),
15841 cCE(fstmeax,	c800b00, 2, (RRw, VRDLST),    vfp_xp_ldstmia),
15842 cCE(fstmdbx,	d200b00, 2, (RRw, VRDLST),    vfp_xp_ldstmdb),
15843 cCE(fstmfdx,	d200b00, 2, (RRw, VRDLST),    vfp_xp_ldstmdb),
15844
15845  /* Monadic operations.  */
15846 cCE(fabss,	eb00ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
15847 cCE(fnegs,	eb10a40, 2, (RVS, RVS),	      vfp_sp_monadic),
15848 cCE(fsqrts,	eb10ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
15849
15850  /* Dyadic operations.	 */
15851 cCE(fadds,	e300a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
15852 cCE(fsubs,	e300a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
15853 cCE(fmuls,	e200a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
15854 cCE(fdivs,	e800a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
15855 cCE(fmacs,	e000a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
15856 cCE(fmscs,	e100a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
15857 cCE(fnmuls,	e200a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
15858 cCE(fnmacs,	e000a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
15859 cCE(fnmscs,	e100a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
15860
15861  /* Comparisons.  */
15862 cCE(fcmps,	eb40a40, 2, (RVS, RVS),	      vfp_sp_monadic),
15863 cCE(fcmpzs,	eb50a40, 1, (RVS),	      vfp_sp_compare_z),
15864 cCE(fcmpes,	eb40ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
15865 cCE(fcmpezs,	eb50ac0, 1, (RVS),	      vfp_sp_compare_z),
15866
15867#undef ARM_VARIANT
15868#define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision).  */
15869  /* Moves and type conversions.  */
15870 cCE(fcpyd,	eb00b40, 2, (RVD, RVD),	      vfp_dp_rd_rm),
15871 cCE(fcvtds,	eb70ac0, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
15872 cCE(fcvtsd,	eb70bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
15873 cCE(fmdhr,	e200b10, 2, (RVD, RR),	      vfp_dp_rn_rd),
15874 cCE(fmdlr,	e000b10, 2, (RVD, RR),	      vfp_dp_rn_rd),
15875 cCE(fmrdh,	e300b10, 2, (RR, RVD),	      vfp_dp_rd_rn),
15876 cCE(fmrdl,	e100b10, 2, (RR, RVD),	      vfp_dp_rd_rn),
15877 cCE(fsitod,	eb80bc0, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
15878 cCE(fuitod,	eb80b40, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
15879 cCE(ftosid,	ebd0b40, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
15880 cCE(ftosizd,	ebd0bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
15881 cCE(ftouid,	ebc0b40, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
15882 cCE(ftouizd,	ebc0bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
15883
15884  /* Memory operations.	 */
15885 cCE(fldd,	d100b00, 2, (RVD, ADDRGLDC),  vfp_dp_ldst),
15886 cCE(fstd,	d000b00, 2, (RVD, ADDRGLDC),  vfp_dp_ldst),
15887 cCE(fldmiad,	c900b00, 2, (RRw, VRDLST),    vfp_dp_ldstmia),
15888 cCE(fldmfdd,	c900b00, 2, (RRw, VRDLST),    vfp_dp_ldstmia),
15889 cCE(fldmdbd,	d300b00, 2, (RRw, VRDLST),    vfp_dp_ldstmdb),
15890 cCE(fldmead,	d300b00, 2, (RRw, VRDLST),    vfp_dp_ldstmdb),
15891 cCE(fstmiad,	c800b00, 2, (RRw, VRDLST),    vfp_dp_ldstmia),
15892 cCE(fstmead,	c800b00, 2, (RRw, VRDLST),    vfp_dp_ldstmia),
15893 cCE(fstmdbd,	d200b00, 2, (RRw, VRDLST),    vfp_dp_ldstmdb),
15894 cCE(fstmfdd,	d200b00, 2, (RRw, VRDLST),    vfp_dp_ldstmdb),
15895
15896  /* Monadic operations.  */
15897 cCE(fabsd,	eb00bc0, 2, (RVD, RVD),	      vfp_dp_rd_rm),
15898 cCE(fnegd,	eb10b40, 2, (RVD, RVD),	      vfp_dp_rd_rm),
15899 cCE(fsqrtd,	eb10bc0, 2, (RVD, RVD),	      vfp_dp_rd_rm),
15900
15901  /* Dyadic operations.	 */
15902 cCE(faddd,	e300b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
15903 cCE(fsubd,	e300b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
15904 cCE(fmuld,	e200b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
15905 cCE(fdivd,	e800b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
15906 cCE(fmacd,	e000b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
15907 cCE(fmscd,	e100b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
15908 cCE(fnmuld,	e200b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
15909 cCE(fnmacd,	e000b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
15910 cCE(fnmscd,	e100b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
15911
15912  /* Comparisons.  */
15913 cCE(fcmpd,	eb40b40, 2, (RVD, RVD),	      vfp_dp_rd_rm),
15914 cCE(fcmpzd,	eb50b40, 1, (RVD),	      vfp_dp_rd),
15915 cCE(fcmped,	eb40bc0, 2, (RVD, RVD),	      vfp_dp_rd_rm),
15916 cCE(fcmpezd,	eb50bc0, 1, (RVD),	      vfp_dp_rd),
15917
15918#undef ARM_VARIANT
15919#define ARM_VARIANT &fpu_vfp_ext_v2
15920 cCE(fmsrr,	c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
15921 cCE(fmrrs,	c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
15922 cCE(fmdrr,	c400b10, 3, (RVD, RR, RR),    vfp_dp_rm_rd_rn),
15923 cCE(fmrrd,	c500b10, 3, (RR, RR, RVD),    vfp_dp_rd_rn_rm),
15924
15925/* Instructions which may belong to either the Neon or VFP instruction sets.
15926   Individual encoder functions perform additional architecture checks.  */
15927#undef ARM_VARIANT
15928#define ARM_VARIANT &fpu_vfp_ext_v1xd
15929#undef THUMB_VARIANT
15930#define THUMB_VARIANT &fpu_vfp_ext_v1xd
15931  /* These mnemonics are unique to VFP.  */
15932 NCE(vsqrt,     0,       2, (RVSD, RVSD),       vfp_nsyn_sqrt),
15933 NCE(vdiv,      0,       3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
15934 nCE(vnmul,     vnmul,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15935 nCE(vnmla,     vnmla,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15936 nCE(vnmls,     vnmls,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15937 nCE(vcmp,      vcmp,    2, (RVSD, RVSD_I0),    vfp_nsyn_cmp),
15938 nCE(vcmpe,     vcmpe,   2, (RVSD, RVSD_I0),    vfp_nsyn_cmp),
15939 NCE(vpush,     0,       1, (VRSDLST),          vfp_nsyn_push),
15940 NCE(vpop,      0,       1, (VRSDLST),          vfp_nsyn_pop),
15941 NCE(vcvtz,     0,       2, (RVSD, RVSD),       vfp_nsyn_cvtz),
15942
15943  /* Mnemonics shared by Neon and VFP.  */
15944 nCEF(vmul,     vmul,    3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
15945 nCEF(vmla,     vmla,    3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
15946 nCEF(vmls,     vmls,    3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
15947
15948 nCEF(vadd,     vadd,    3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
15949 nCEF(vsub,     vsub,    3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
15950
15951 NCEF(vabs,     1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
15952 NCEF(vneg,     1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
15953
15954 NCE(vldm,      c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15955 NCE(vldmia,    c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15956 NCE(vldmdb,    d100b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15957 NCE(vstm,      c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15958 NCE(vstmia,    c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15959 NCE(vstmdb,    d000b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15960 NCE(vldr,      d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
15961 NCE(vstr,      d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
15962
15963 nCEF(vcvt,     vcvt,    3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
15964
15965  /* NOTE: All VMOV encoding is special-cased!  */
15966 NCE(vmov,      0,       1, (VMOV), neon_mov),
15967 NCE(vmovq,     0,       1, (VMOV), neon_mov),
15968
15969#undef THUMB_VARIANT
15970#define THUMB_VARIANT &fpu_neon_ext_v1
15971#undef ARM_VARIANT
15972#define ARM_VARIANT &fpu_neon_ext_v1
15973  /* Data processing with three registers of the same length.  */
15974  /* integer ops, valid types S8 S16 S32 U8 U16 U32.  */
15975 NUF(vaba,      0000710, 3, (RNDQ, RNDQ,  RNDQ), neon_dyadic_i_su),
15976 NUF(vabaq,     0000710, 3, (RNQ,  RNQ,   RNQ),  neon_dyadic_i_su),
15977 NUF(vhadd,     0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15978 NUF(vhaddq,    0000000, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i_su),
15979 NUF(vrhadd,    0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15980 NUF(vrhaddq,   0000100, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i_su),
15981 NUF(vhsub,     0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15982 NUF(vhsubq,    0000200, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i_su),
15983  /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64.  */
15984 NUF(vqadd,     0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
15985 NUF(vqaddq,    0000010, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i64_su),
15986 NUF(vqsub,     0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
15987 NUF(vqsubq,    0000210, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i64_su),
15988 NUF(vrshl,     0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
15989 NUF(vrshlq,    0000500, 3, (RNQ,  oRNQ,  RNQ),  neon_rshl),
15990 NUF(vqrshl,    0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
15991 NUF(vqrshlq,   0000510, 3, (RNQ,  oRNQ,  RNQ),  neon_rshl),
15992  /* If not immediate, fall back to neon_dyadic_i64_su.
15993     shl_imm should accept I8 I16 I32 I64,
15994     qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64.  */
15995 nUF(vshl,      vshl,    3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
15996 nUF(vshlq,     vshl,    3, (RNQ,  oRNQ,  RNDQ_I63b), neon_shl_imm),
15997 nUF(vqshl,     vqshl,   3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
15998 nUF(vqshlq,    vqshl,   3, (RNQ,  oRNQ,  RNDQ_I63b), neon_qshl_imm),
15999  /* Logic ops, types optional & ignored.  */
16000 nUF(vand,      vand,    2, (RNDQ, NILO),        neon_logic),
16001 nUF(vandq,     vand,    2, (RNQ,  NILO),        neon_logic),
16002 nUF(vbic,      vbic,    2, (RNDQ, NILO),        neon_logic),
16003 nUF(vbicq,     vbic,    2, (RNQ,  NILO),        neon_logic),
16004 nUF(vorr,      vorr,    2, (RNDQ, NILO),        neon_logic),
16005 nUF(vorrq,     vorr,    2, (RNQ,  NILO),        neon_logic),
16006 nUF(vorn,      vorn,    2, (RNDQ, NILO),        neon_logic),
16007 nUF(vornq,     vorn,    2, (RNQ,  NILO),        neon_logic),
16008 nUF(veor,      veor,    3, (RNDQ, oRNDQ, RNDQ), neon_logic),
16009 nUF(veorq,     veor,    3, (RNQ,  oRNQ,  RNQ),  neon_logic),
16010  /* Bitfield ops, untyped.  */
16011 NUF(vbsl,      1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
16012 NUF(vbslq,     1100110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
16013 NUF(vbit,      1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
16014 NUF(vbitq,     1200110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
16015 NUF(vbif,      1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
16016 NUF(vbifq,     1300110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
16017  /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32.  */
16018 nUF(vabd,      vabd,    3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
16019 nUF(vabdq,     vabd,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
16020 nUF(vmax,      vmax,    3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
16021 nUF(vmaxq,     vmax,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
16022 nUF(vmin,      vmin,    3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
16023 nUF(vminq,     vmin,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
16024  /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
16025     back to neon_dyadic_if_su.  */
16026 nUF(vcge,      vcge,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
16027 nUF(vcgeq,     vcge,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp),
16028 nUF(vcgt,      vcgt,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
16029 nUF(vcgtq,     vcgt,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp),
16030 nUF(vclt,      vclt,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
16031 nUF(vcltq,     vclt,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp_inv),
16032 nUF(vcle,      vcle,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
16033 nUF(vcleq,     vcle,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp_inv),
16034  /* Comparison. Type I8 I16 I32 F32.  */
16035 nUF(vceq,      vceq,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
16036 nUF(vceqq,     vceq,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_ceq),
16037  /* As above, D registers only.  */
16038 nUF(vpmax,     vpmax,   3, (RND, oRND, RND), neon_dyadic_if_su_d),
16039 nUF(vpmin,     vpmin,   3, (RND, oRND, RND), neon_dyadic_if_su_d),
16040  /* Int and float variants, signedness unimportant.  */
16041 nUF(vmlaq,     vmla,    3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_mac_maybe_scalar),
16042 nUF(vmlsq,     vmls,    3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_mac_maybe_scalar),
16043 nUF(vpadd,     vpadd,   3, (RND,  oRND,  RND),       neon_dyadic_if_i_d),
16044  /* Add/sub take types I8 I16 I32 I64 F32.  */
16045 nUF(vaddq,     vadd,    3, (RNQ,  oRNQ,  RNQ),  neon_addsub_if_i),
16046 nUF(vsubq,     vsub,    3, (RNQ,  oRNQ,  RNQ),  neon_addsub_if_i),
16047  /* vtst takes sizes 8, 16, 32.  */
16048 NUF(vtst,      0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
16049 NUF(vtstq,     0000810, 3, (RNQ,  oRNQ,  RNQ),  neon_tst),
16050  /* VMUL takes I8 I16 I32 F32 P8.  */
16051 nUF(vmulq,     vmul,     3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_mul),
16052  /* VQD{R}MULH takes S16 S32.  */
16053 nUF(vqdmulh,   vqdmulh,  3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
16054 nUF(vqdmulhq,  vqdmulh,  3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_qdmulh),
16055 nUF(vqrdmulh,  vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
16056 nUF(vqrdmulhq, vqrdmulh, 3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_qdmulh),
16057 NUF(vacge,     0000e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
16058 NUF(vacgeq,    0000e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute),
16059 NUF(vacgt,     0200e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
16060 NUF(vacgtq,    0200e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute),
16061 NUF(vaclt,     0200e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
16062 NUF(vacltq,    0200e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute_inv),
16063 NUF(vacle,     0000e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
16064 NUF(vacleq,    0000e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute_inv),
16065 NUF(vrecps,    0000f10,  3, (RNDQ, oRNDQ, RNDQ), neon_step),
16066 NUF(vrecpsq,   0000f10,  3, (RNQ,  oRNQ,  RNQ),  neon_step),
16067 NUF(vrsqrts,   0200f10,  3, (RNDQ, oRNDQ, RNDQ), neon_step),
16068 NUF(vrsqrtsq,  0200f10,  3, (RNQ,  oRNQ,  RNQ),  neon_step),
16069
16070  /* Two address, int/float. Types S8 S16 S32 F32.  */
16071 NUF(vabsq,     1b10300, 2, (RNQ,  RNQ),      neon_abs_neg),
16072 NUF(vnegq,     1b10380, 2, (RNQ,  RNQ),      neon_abs_neg),
16073
16074  /* Data processing with two registers and a shift amount.  */
16075  /* Right shifts, and variants with rounding.
16076     Types accepted S8 S16 S32 S64 U8 U16 U32 U64.  */
16077 NUF(vshr,      0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
16078 NUF(vshrq,     0800010, 3, (RNQ,  oRNQ,  I64z), neon_rshift_round_imm),
16079 NUF(vrshr,     0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
16080 NUF(vrshrq,    0800210, 3, (RNQ,  oRNQ,  I64z), neon_rshift_round_imm),
16081 NUF(vsra,      0800110, 3, (RNDQ, oRNDQ, I64),  neon_rshift_round_imm),
16082 NUF(vsraq,     0800110, 3, (RNQ,  oRNQ,  I64),  neon_rshift_round_imm),
16083 NUF(vrsra,     0800310, 3, (RNDQ, oRNDQ, I64),  neon_rshift_round_imm),
16084 NUF(vrsraq,    0800310, 3, (RNQ,  oRNQ,  I64),  neon_rshift_round_imm),
16085  /* Shift and insert. Sizes accepted 8 16 32 64.  */
16086 NUF(vsli,      1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
16087 NUF(vsliq,     1800510, 3, (RNQ,  oRNQ,  I63), neon_sli),
16088 NUF(vsri,      1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
16089 NUF(vsriq,     1800410, 3, (RNQ,  oRNQ,  I64), neon_sri),
16090  /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64.  */
16091 NUF(vqshlu,    1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
16092 NUF(vqshluq,   1800610, 3, (RNQ,  oRNQ,  I63), neon_qshlu_imm),
16093  /* Right shift immediate, saturating & narrowing, with rounding variants.
16094     Types accepted S16 S32 S64 U16 U32 U64.  */
16095 NUF(vqshrn,    0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
16096 NUF(vqrshrn,   0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
16097  /* As above, unsigned. Types accepted S16 S32 S64.  */
16098 NUF(vqshrun,   0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
16099 NUF(vqrshrun,  0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
16100  /* Right shift narrowing. Types accepted I16 I32 I64.  */
16101 NUF(vshrn,     0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
16102 NUF(vrshrn,    0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
16103  /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant.  */
16104 nUF(vshll,     vshll,   3, (RNQ, RND, I32),  neon_shll),
16105  /* CVT with optional immediate for fixed-point variant.  */
16106 nUF(vcvtq,     vcvt,    3, (RNQ, RNQ, oI32b), neon_cvt),
16107
16108 nUF(vmvn,      vmvn,    2, (RNDQ, RNDQ_IMVNb), neon_mvn),
16109 nUF(vmvnq,     vmvn,    2, (RNQ,  RNDQ_IMVNb), neon_mvn),
16110
16111  /* Data processing, three registers of different lengths.  */
16112  /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32.  */
16113 NUF(vabal,     0800500, 3, (RNQ, RND, RND),  neon_abal),
16114 NUF(vabdl,     0800700, 3, (RNQ, RND, RND),  neon_dyadic_long),
16115 NUF(vaddl,     0800000, 3, (RNQ, RND, RND),  neon_dyadic_long),
16116 NUF(vsubl,     0800200, 3, (RNQ, RND, RND),  neon_dyadic_long),
16117  /* If not scalar, fall back to neon_dyadic_long.
16118     Vector types as above, scalar types S16 S32 U16 U32.  */
16119 nUF(vmlal,     vmlal,   3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
16120 nUF(vmlsl,     vmlsl,   3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
16121  /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32.  */
16122 NUF(vaddw,     0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
16123 NUF(vsubw,     0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
16124  /* Dyadic, narrowing insns. Types I16 I32 I64.  */
16125 NUF(vaddhn,    0800400, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
16126 NUF(vraddhn,   1800400, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
16127 NUF(vsubhn,    0800600, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
16128 NUF(vrsubhn,   1800600, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
16129  /* Saturating doubling multiplies. Types S16 S32.  */
16130 nUF(vqdmlal,   vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16131 nUF(vqdmlsl,   vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16132 nUF(vqdmull,   vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16133  /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16134     S16 S32 U16 U32.  */
16135 nUF(vmull,     vmull,   3, (RNQ, RND, RND_RNSC), neon_vmull),
16136
16137  /* Extract. Size 8.  */
16138 NUF(vext,      0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
16139 NUF(vextq,     0b00000, 4, (RNQ,  oRNQ,  RNQ,  I15), neon_ext),
16140
16141  /* Two registers, miscellaneous.  */
16142  /* Reverse. Sizes 8 16 32 (must be < size in opcode).  */
16143 NUF(vrev64,    1b00000, 2, (RNDQ, RNDQ),     neon_rev),
16144 NUF(vrev64q,   1b00000, 2, (RNQ,  RNQ),      neon_rev),
16145 NUF(vrev32,    1b00080, 2, (RNDQ, RNDQ),     neon_rev),
16146 NUF(vrev32q,   1b00080, 2, (RNQ,  RNQ),      neon_rev),
16147 NUF(vrev16,    1b00100, 2, (RNDQ, RNDQ),     neon_rev),
16148 NUF(vrev16q,   1b00100, 2, (RNQ,  RNQ),      neon_rev),
16149  /* Vector replicate. Sizes 8 16 32.  */
16150 nCE(vdup,      vdup,    2, (RNDQ, RR_RNSC),  neon_dup),
16151 nCE(vdupq,     vdup,    2, (RNQ,  RR_RNSC),  neon_dup),
16152  /* VMOVL. Types S8 S16 S32 U8 U16 U32.  */
16153 NUF(vmovl,     0800a10, 2, (RNQ, RND),       neon_movl),
16154  /* VMOVN. Types I16 I32 I64.  */
16155 nUF(vmovn,     vmovn,   2, (RND, RNQ),       neon_movn),
16156  /* VQMOVN. Types S16 S32 S64 U16 U32 U64.  */
16157 nUF(vqmovn,    vqmovn,  2, (RND, RNQ),       neon_qmovn),
16158  /* VQMOVUN. Types S16 S32 S64.  */
16159 nUF(vqmovun,   vqmovun, 2, (RND, RNQ),       neon_qmovun),
16160  /* VZIP / VUZP. Sizes 8 16 32.  */
16161 NUF(vzip,      1b20180, 2, (RNDQ, RNDQ),     neon_zip_uzp),
16162 NUF(vzipq,     1b20180, 2, (RNQ,  RNQ),      neon_zip_uzp),
16163 NUF(vuzp,      1b20100, 2, (RNDQ, RNDQ),     neon_zip_uzp),
16164 NUF(vuzpq,     1b20100, 2, (RNQ,  RNQ),      neon_zip_uzp),
16165  /* VQABS / VQNEG. Types S8 S16 S32.  */
16166 NUF(vqabs,     1b00700, 2, (RNDQ, RNDQ),     neon_sat_abs_neg),
16167 NUF(vqabsq,    1b00700, 2, (RNQ,  RNQ),      neon_sat_abs_neg),
16168 NUF(vqneg,     1b00780, 2, (RNDQ, RNDQ),     neon_sat_abs_neg),
16169 NUF(vqnegq,    1b00780, 2, (RNQ,  RNQ),      neon_sat_abs_neg),
16170  /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32.  */
16171 NUF(vpadal,    1b00600, 2, (RNDQ, RNDQ),     neon_pair_long),
16172 NUF(vpadalq,   1b00600, 2, (RNQ,  RNQ),      neon_pair_long),
16173 NUF(vpaddl,    1b00200, 2, (RNDQ, RNDQ),     neon_pair_long),
16174 NUF(vpaddlq,   1b00200, 2, (RNQ,  RNQ),      neon_pair_long),
16175  /* Reciprocal estimates. Types U32 F32.  */
16176 NUF(vrecpe,    1b30400, 2, (RNDQ, RNDQ),     neon_recip_est),
16177 NUF(vrecpeq,   1b30400, 2, (RNQ,  RNQ),      neon_recip_est),
16178 NUF(vrsqrte,   1b30480, 2, (RNDQ, RNDQ),     neon_recip_est),
16179 NUF(vrsqrteq,  1b30480, 2, (RNQ,  RNQ),      neon_recip_est),
16180  /* VCLS. Types S8 S16 S32.  */
16181 NUF(vcls,      1b00400, 2, (RNDQ, RNDQ),     neon_cls),
16182 NUF(vclsq,     1b00400, 2, (RNQ,  RNQ),      neon_cls),
16183  /* VCLZ. Types I8 I16 I32.  */
16184 NUF(vclz,      1b00480, 2, (RNDQ, RNDQ),     neon_clz),
16185 NUF(vclzq,     1b00480, 2, (RNQ,  RNQ),      neon_clz),
16186  /* VCNT. Size 8.  */
16187 NUF(vcnt,      1b00500, 2, (RNDQ, RNDQ),     neon_cnt),
16188 NUF(vcntq,     1b00500, 2, (RNQ,  RNQ),      neon_cnt),
16189  /* Two address, untyped.  */
16190 NUF(vswp,      1b20000, 2, (RNDQ, RNDQ),     neon_swp),
16191 NUF(vswpq,     1b20000, 2, (RNQ,  RNQ),      neon_swp),
16192  /* VTRN. Sizes 8 16 32.  */
16193 nUF(vtrn,      vtrn,    2, (RNDQ, RNDQ),     neon_trn),
16194 nUF(vtrnq,     vtrn,    2, (RNQ,  RNQ),      neon_trn),
16195
16196  /* Table lookup. Size 8.  */
16197 NUF(vtbl,      1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
16198 NUF(vtbx,      1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
16199
16200#undef THUMB_VARIANT
16201#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16202#undef ARM_VARIANT
16203#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16204  /* Neon element/structure load/store.  */
16205 nUF(vld1,      vld1,    2, (NSTRLST, ADDR),  neon_ldx_stx),
16206 nUF(vst1,      vst1,    2, (NSTRLST, ADDR),  neon_ldx_stx),
16207 nUF(vld2,      vld2,    2, (NSTRLST, ADDR),  neon_ldx_stx),
16208 nUF(vst2,      vst2,    2, (NSTRLST, ADDR),  neon_ldx_stx),
16209 nUF(vld3,      vld3,    2, (NSTRLST, ADDR),  neon_ldx_stx),
16210 nUF(vst3,      vst3,    2, (NSTRLST, ADDR),  neon_ldx_stx),
16211 nUF(vld4,      vld4,    2, (NSTRLST, ADDR),  neon_ldx_stx),
16212 nUF(vst4,      vst4,    2, (NSTRLST, ADDR),  neon_ldx_stx),
16213
16214#undef THUMB_VARIANT
16215#define THUMB_VARIANT &fpu_vfp_ext_v3
16216#undef ARM_VARIANT
16217#define ARM_VARIANT &fpu_vfp_ext_v3
16218 cCE(fconsts,   eb00a00, 2, (RVS, I255),      vfp_sp_const),
16219 cCE(fconstd,   eb00b00, 2, (RVD, I255),      vfp_dp_const),
16220 cCE(fshtos,    eba0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
16221 cCE(fshtod,    eba0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
16222 cCE(fsltos,    eba0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
16223 cCE(fsltod,    eba0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
16224 cCE(fuhtos,    ebb0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
16225 cCE(fuhtod,    ebb0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
16226 cCE(fultos,    ebb0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
16227 cCE(fultod,    ebb0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
16228 cCE(ftoshs,    ebe0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
16229 cCE(ftoshd,    ebe0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
16230 cCE(ftosls,    ebe0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
16231 cCE(ftosld,    ebe0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
16232 cCE(ftouhs,    ebf0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
16233 cCE(ftouhd,    ebf0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
16234 cCE(ftouls,    ebf0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
16235 cCE(ftould,    ebf0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
16236
16237#undef THUMB_VARIANT
16238#undef ARM_VARIANT
16239#define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions.	 */
16240 cCE(mia,	e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16241 cCE(miaph,	e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16242 cCE(miabb,	e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16243 cCE(miabt,	e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16244 cCE(miatb,	e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16245 cCE(miatt,	e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16246 cCE(mar,	c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
16247 cCE(mra,	c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
16248
16249#undef ARM_VARIANT
16250#define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology.  */
16251 cCE(tandcb,	e13f130, 1, (RR),		    iwmmxt_tandorc),
16252 cCE(tandch,	e53f130, 1, (RR),		    iwmmxt_tandorc),
16253 cCE(tandcw,	e93f130, 1, (RR),		    iwmmxt_tandorc),
16254 cCE(tbcstb,	e400010, 2, (RIWR, RR),		    rn_rd),
16255 cCE(tbcsth,	e400050, 2, (RIWR, RR),		    rn_rd),
16256 cCE(tbcstw,	e400090, 2, (RIWR, RR),		    rn_rd),
16257 cCE(textrcb,	e130170, 2, (RR, I7),		    iwmmxt_textrc),
16258 cCE(textrch,	e530170, 2, (RR, I7),		    iwmmxt_textrc),
16259 cCE(textrcw,	e930170, 2, (RR, I7),		    iwmmxt_textrc),
16260 cCE(textrmub,	e100070, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
16261 cCE(textrmuh,	e500070, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
16262 cCE(textrmuw,	e900070, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
16263 cCE(textrmsb,	e100078, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
16264 cCE(textrmsh,	e500078, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
16265 cCE(textrmsw,	e900078, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
16266 cCE(tinsrb,	e600010, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
16267 cCE(tinsrh,	e600050, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
16268 cCE(tinsrw,	e600090, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
16269 cCE(tmcr,	e000110, 2, (RIWC_RIWG, RR),	    rn_rd),
16270 cCE(tmcrr,	c400000, 3, (RIWR, RR, RR),	    rm_rd_rn),
16271 cCE(tmia,	e200010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
16272 cCE(tmiaph,	e280010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
16273 cCE(tmiabb,	e2c0010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
16274 cCE(tmiabt,	e2d0010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
16275 cCE(tmiatb,	e2e0010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
16276 cCE(tmiatt,	e2f0010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
16277 cCE(tmovmskb,	e100030, 2, (RR, RIWR),		    rd_rn),
16278 cCE(tmovmskh,	e500030, 2, (RR, RIWR),		    rd_rn),
16279 cCE(tmovmskw,	e900030, 2, (RR, RIWR),		    rd_rn),
16280 cCE(tmrc,	e100110, 2, (RR, RIWC_RIWG),	    rd_rn),
16281 cCE(tmrrc,	c500000, 3, (RR, RR, RIWR),	    rd_rn_rm),
16282 cCE(torcb,	e13f150, 1, (RR),		    iwmmxt_tandorc),
16283 cCE(torch,	e53f150, 1, (RR),		    iwmmxt_tandorc),
16284 cCE(torcw,	e93f150, 1, (RR),		    iwmmxt_tandorc),
16285 cCE(waccb,	e0001c0, 2, (RIWR, RIWR),	    rd_rn),
16286 cCE(wacch,	e4001c0, 2, (RIWR, RIWR),	    rd_rn),
16287 cCE(waccw,	e8001c0, 2, (RIWR, RIWR),	    rd_rn),
16288 cCE(waddbss,	e300180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16289 cCE(waddb,	e000180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16290 cCE(waddbus,	e100180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16291 cCE(waddhss,	e700180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16292 cCE(waddh,	e400180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16293 cCE(waddhus,	e500180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16294 cCE(waddwss,	eb00180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16295 cCE(waddw,	e800180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16296 cCE(waddwus,	e900180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16297 cCE(waligni,	e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
16298 cCE(walignr0,	e800020, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16299 cCE(walignr1,	e900020, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16300 cCE(walignr2,	ea00020, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16301 cCE(walignr3,	eb00020, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16302 cCE(wand,	e200000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16303 cCE(wandn,	e300000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16304 cCE(wavg2b,	e800000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16305 cCE(wavg2br,	e900000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16306 cCE(wavg2h,	ec00000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16307 cCE(wavg2hr,	ed00000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16308 cCE(wcmpeqb,	e000060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16309 cCE(wcmpeqh,	e400060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16310 cCE(wcmpeqw,	e800060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16311 cCE(wcmpgtub,	e100060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16312 cCE(wcmpgtuh,	e500060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16313 cCE(wcmpgtuw,	e900060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16314 cCE(wcmpgtsb,	e300060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16315 cCE(wcmpgtsh,	e700060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16316 cCE(wcmpgtsw,	eb00060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16317 cCE(wldrb,	c100000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
16318 cCE(wldrh,	c500000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
16319 cCE(wldrw,	c100100, 2, (RIWR_RIWC, ADDR),	    iwmmxt_wldstw),
16320 cCE(wldrd,	c500100, 2, (RIWR, ADDR),	    iwmmxt_wldstd),
16321 cCE(wmacs,	e600100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16322 cCE(wmacsz,	e700100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16323 cCE(wmacu,	e400100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16324 cCE(wmacuz,	e500100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16325 cCE(wmadds,	ea00100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16326 cCE(wmaddu,	e800100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16327 cCE(wmaxsb,	e200160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16328 cCE(wmaxsh,	e600160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16329 cCE(wmaxsw,	ea00160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16330 cCE(wmaxub,	e000160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16331 cCE(wmaxuh,	e400160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16332 cCE(wmaxuw,	e800160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16333 cCE(wminsb,	e300160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16334 cCE(wminsh,	e700160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16335 cCE(wminsw,	eb00160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16336 cCE(wminub,	e100160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16337 cCE(wminuh,	e500160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16338 cCE(wminuw,	e900160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16339 cCE(wmov,	e000000, 2, (RIWR, RIWR),	    iwmmxt_wmov),
16340 cCE(wmulsm,	e300100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16341 cCE(wmulsl,	e200100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16342 cCE(wmulum,	e100100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16343 cCE(wmulul,	e000100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16344 cCE(wor,	e000000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16345 cCE(wpackhss,	e700080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16346 cCE(wpackhus,	e500080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16347 cCE(wpackwss,	eb00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16348 cCE(wpackwus,	e900080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16349 cCE(wpackdss,	ef00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16350 cCE(wpackdus,	ed00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16351 cCE(wrorh,	e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16352 cCE(wrorhg,	e700148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
16353 cCE(wrorw,	eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16354 cCE(wrorwg,	eb00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
16355 cCE(wrord,	ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16356 cCE(wrordg,	ef00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
16357 cCE(wsadb,	e000120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16358 cCE(wsadbz,	e100120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16359 cCE(wsadh,	e400120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16360 cCE(wsadhz,	e500120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16361 cCE(wshufh,	e0001e0, 3, (RIWR, RIWR, I255),	    iwmmxt_wshufh),
16362 cCE(wsllh,	e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16363 cCE(wsllhg,	e500148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
16364 cCE(wsllw,	e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16365 cCE(wsllwg,	e900148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
16366 cCE(wslld,	ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16367 cCE(wslldg,	ed00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
16368 cCE(wsrah,	e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16369 cCE(wsrahg,	e400148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
16370 cCE(wsraw,	e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16371 cCE(wsrawg,	e800148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
16372 cCE(wsrad,	ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16373 cCE(wsradg,	ec00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
16374 cCE(wsrlh,	e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16375 cCE(wsrlhg,	e600148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
16376 cCE(wsrlw,	ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16377 cCE(wsrlwg,	ea00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
16378 cCE(wsrld,	ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16379 cCE(wsrldg,	ee00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
16380 cCE(wstrb,	c000000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
16381 cCE(wstrh,	c400000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
16382 cCE(wstrw,	c000100, 2, (RIWR_RIWC, ADDR),	    iwmmxt_wldstw),
16383 cCE(wstrd,	c400100, 2, (RIWR, ADDR),	    iwmmxt_wldstd),
16384 cCE(wsubbss,	e3001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16385 cCE(wsubb,	e0001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16386 cCE(wsubbus,	e1001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16387 cCE(wsubhss,	e7001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16388 cCE(wsubh,	e4001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16389 cCE(wsubhus,	e5001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16390 cCE(wsubwss,	eb001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16391 cCE(wsubw,	e8001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16392 cCE(wsubwus,	e9001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16393 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR),	    rd_rn),
16394 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR),	    rd_rn),
16395 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR),	    rd_rn),
16396 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR),	    rd_rn),
16397 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR),	    rd_rn),
16398 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR),	    rd_rn),
16399 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16400 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16401 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16402 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR),	    rd_rn),
16403 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR),	    rd_rn),
16404 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR),	    rd_rn),
16405 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR),	    rd_rn),
16406 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR),	    rd_rn),
16407 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR),	    rd_rn),
16408 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16409 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16410 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16411 cCE(wxor,	e100000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
16412 cCE(wzero,	e300000, 1, (RIWR),		    iwmmxt_wzero),
16413
16414#undef ARM_VARIANT
16415#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2.  */
16416 cCE(torvscb,   e13f190, 1, (RR),		    iwmmxt_tandorc),
16417 cCE(torvsch,   e53f190, 1, (RR),		    iwmmxt_tandorc),
16418 cCE(torvscw,   e93f190, 1, (RR),		    iwmmxt_tandorc),
16419 cCE(wabsb,     e2001c0, 2, (RIWR, RIWR),           rd_rn),
16420 cCE(wabsh,     e6001c0, 2, (RIWR, RIWR),           rd_rn),
16421 cCE(wabsw,     ea001c0, 2, (RIWR, RIWR),           rd_rn),
16422 cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16423 cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16424 cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16425 cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16426 cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16427 cCE(waddhc,    e600180, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16428 cCE(waddwc,    ea00180, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16429 cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16430 cCE(wavg4,	e400000, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16431 cCE(wavg4r,    e500000, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16432 cCE(wmaddsn,   ee00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16433 cCE(wmaddsx,   eb00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16434 cCE(wmaddun,   ec00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16435 cCE(wmaddux,   e900100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16436 cCE(wmerge,    e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
16437 cCE(wmiabb,    e0000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16438 cCE(wmiabt,    e1000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16439 cCE(wmiatb,    e2000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16440 cCE(wmiatt,    e3000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16441 cCE(wmiabbn,   e4000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16442 cCE(wmiabtn,   e5000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16443 cCE(wmiatbn,   e6000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16444 cCE(wmiattn,   e7000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16445 cCE(wmiawbb,   e800120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16446 cCE(wmiawbt,   e900120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16447 cCE(wmiawtb,   ea00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16448 cCE(wmiawtt,   eb00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16449 cCE(wmiawbbn,  ec00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16450 cCE(wmiawbtn,  ed00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16451 cCE(wmiawtbn,  ee00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16452 cCE(wmiawttn,  ef00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16453 cCE(wmulsmr,   ef00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16454 cCE(wmulumr,   ed00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16455 cCE(wmulwumr,  ec000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16456 cCE(wmulwsmr,  ee000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16457 cCE(wmulwum,   ed000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16458 cCE(wmulwsm,   ef000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16459 cCE(wmulwl,    eb000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16460 cCE(wqmiabb,   e8000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16461 cCE(wqmiabt,   e9000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16462 cCE(wqmiatb,   ea000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16463 cCE(wqmiatt,   eb000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16464 cCE(wqmiabbn,  ec000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16465 cCE(wqmiabtn,  ed000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16466 cCE(wqmiatbn,  ee000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16467 cCE(wqmiattn,  ef000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16468 cCE(wqmulm,    e100080, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16469 cCE(wqmulmr,   e300080, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16470 cCE(wqmulwm,   ec000e0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16471 cCE(wqmulwmr,  ee000e0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16472 cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
16473
16474#undef ARM_VARIANT
16475#define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions.	*/
16476 cCE(cfldrs,	c100400, 2, (RMF, ADDRGLDC),	      rd_cpaddr),
16477 cCE(cfldrd,	c500400, 2, (RMD, ADDRGLDC),	      rd_cpaddr),
16478 cCE(cfldr32,	c100500, 2, (RMFX, ADDRGLDC),	      rd_cpaddr),
16479 cCE(cfldr64,	c500500, 2, (RMDX, ADDRGLDC),	      rd_cpaddr),
16480 cCE(cfstrs,	c000400, 2, (RMF, ADDRGLDC),	      rd_cpaddr),
16481 cCE(cfstrd,	c400400, 2, (RMD, ADDRGLDC),	      rd_cpaddr),
16482 cCE(cfstr32,	c000500, 2, (RMFX, ADDRGLDC),	      rd_cpaddr),
16483 cCE(cfstr64,	c400500, 2, (RMDX, ADDRGLDC),	      rd_cpaddr),
16484 cCE(cfmvsr,	e000450, 2, (RMF, RR),		      rn_rd),
16485 cCE(cfmvrs,	e100450, 2, (RR, RMF),		      rd_rn),
16486 cCE(cfmvdlr,	e000410, 2, (RMD, RR),		      rn_rd),
16487 cCE(cfmvrdl,	e100410, 2, (RR, RMD),		      rd_rn),
16488 cCE(cfmvdhr,	e000430, 2, (RMD, RR),		      rn_rd),
16489 cCE(cfmvrdh,	e100430, 2, (RR, RMD),		      rd_rn),
16490 cCE(cfmv64lr,	e000510, 2, (RMDX, RR),		      rn_rd),
16491 cCE(cfmvr64l,	e100510, 2, (RR, RMDX),		      rd_rn),
16492 cCE(cfmv64hr,	e000530, 2, (RMDX, RR),		      rn_rd),
16493 cCE(cfmvr64h,	e100530, 2, (RR, RMDX),		      rd_rn),
16494 cCE(cfmval32,	e200440, 2, (RMAX, RMFX),	      rd_rn),
16495 cCE(cfmv32al,	e100440, 2, (RMFX, RMAX),	      rd_rn),
16496 cCE(cfmvam32,	e200460, 2, (RMAX, RMFX),	      rd_rn),
16497 cCE(cfmv32am,	e100460, 2, (RMFX, RMAX),	      rd_rn),
16498 cCE(cfmvah32,	e200480, 2, (RMAX, RMFX),	      rd_rn),
16499 cCE(cfmv32ah,	e100480, 2, (RMFX, RMAX),	      rd_rn),
16500 cCE(cfmva32,	e2004a0, 2, (RMAX, RMFX),	      rd_rn),
16501 cCE(cfmv32a,	e1004a0, 2, (RMFX, RMAX),	      rd_rn),
16502 cCE(cfmva64,	e2004c0, 2, (RMAX, RMDX),	      rd_rn),
16503 cCE(cfmv64a,	e1004c0, 2, (RMDX, RMAX),	      rd_rn),
16504 cCE(cfmvsc32,	e2004e0, 2, (RMDS, RMDX),	      mav_dspsc),
16505 cCE(cfmv32sc,	e1004e0, 2, (RMDX, RMDS),	      rd),
16506 cCE(cfcpys,	e000400, 2, (RMF, RMF),		      rd_rn),
16507 cCE(cfcpyd,	e000420, 2, (RMD, RMD),		      rd_rn),
16508 cCE(cfcvtsd,	e000460, 2, (RMD, RMF),		      rd_rn),
16509 cCE(cfcvtds,	e000440, 2, (RMF, RMD),		      rd_rn),
16510 cCE(cfcvt32s,	e000480, 2, (RMF, RMFX),	      rd_rn),
16511 cCE(cfcvt32d,	e0004a0, 2, (RMD, RMFX),	      rd_rn),
16512 cCE(cfcvt64s,	e0004c0, 2, (RMF, RMDX),	      rd_rn),
16513 cCE(cfcvt64d,	e0004e0, 2, (RMD, RMDX),	      rd_rn),
16514 cCE(cfcvts32,	e100580, 2, (RMFX, RMF),	      rd_rn),
16515 cCE(cfcvtd32,	e1005a0, 2, (RMFX, RMD),	      rd_rn),
16516 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF),	      rd_rn),
16517 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD),	      rd_rn),
16518 cCE(cfrshl32,	e000550, 3, (RMFX, RMFX, RR),	      mav_triple),
16519 cCE(cfrshl64,	e000570, 3, (RMDX, RMDX, RR),	      mav_triple),
16520 cCE(cfsh32,	e000500, 3, (RMFX, RMFX, I63s),	      mav_shift),
16521 cCE(cfsh64,	e200500, 3, (RMDX, RMDX, I63s),	      mav_shift),
16522 cCE(cfcmps,	e100490, 3, (RR, RMF, RMF),	      rd_rn_rm),
16523 cCE(cfcmpd,	e1004b0, 3, (RR, RMD, RMD),	      rd_rn_rm),
16524 cCE(cfcmp32,	e100590, 3, (RR, RMFX, RMFX),	      rd_rn_rm),
16525 cCE(cfcmp64,	e1005b0, 3, (RR, RMDX, RMDX),	      rd_rn_rm),
16526 cCE(cfabss,	e300400, 2, (RMF, RMF),		      rd_rn),
16527 cCE(cfabsd,	e300420, 2, (RMD, RMD),		      rd_rn),
16528 cCE(cfnegs,	e300440, 2, (RMF, RMF),		      rd_rn),
16529 cCE(cfnegd,	e300460, 2, (RMD, RMD),		      rd_rn),
16530 cCE(cfadds,	e300480, 3, (RMF, RMF, RMF),	      rd_rn_rm),
16531 cCE(cfaddd,	e3004a0, 3, (RMD, RMD, RMD),	      rd_rn_rm),
16532 cCE(cfsubs,	e3004c0, 3, (RMF, RMF, RMF),	      rd_rn_rm),
16533 cCE(cfsubd,	e3004e0, 3, (RMD, RMD, RMD),	      rd_rn_rm),
16534 cCE(cfmuls,	e100400, 3, (RMF, RMF, RMF),	      rd_rn_rm),
16535 cCE(cfmuld,	e100420, 3, (RMD, RMD, RMD),	      rd_rn_rm),
16536 cCE(cfabs32,	e300500, 2, (RMFX, RMFX),	      rd_rn),
16537 cCE(cfabs64,	e300520, 2, (RMDX, RMDX),	      rd_rn),
16538 cCE(cfneg32,	e300540, 2, (RMFX, RMFX),	      rd_rn),
16539 cCE(cfneg64,	e300560, 2, (RMDX, RMDX),	      rd_rn),
16540 cCE(cfadd32,	e300580, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
16541 cCE(cfadd64,	e3005a0, 3, (RMDX, RMDX, RMDX),	      rd_rn_rm),
16542 cCE(cfsub32,	e3005c0, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
16543 cCE(cfsub64,	e3005e0, 3, (RMDX, RMDX, RMDX),	      rd_rn_rm),
16544 cCE(cfmul32,	e100500, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
16545 cCE(cfmul64,	e100520, 3, (RMDX, RMDX, RMDX),	      rd_rn_rm),
16546 cCE(cfmac32,	e100540, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
16547 cCE(cfmsc32,	e100560, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
16548 cCE(cfmadd32,	e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
16549 cCE(cfmsub32,	e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
16550 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
16551 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
16552};
16553#undef ARM_VARIANT
16554#undef THUMB_VARIANT
16555#undef TCE
16556#undef TCM
16557#undef TUE
16558#undef TUF
16559#undef TCC
16560#undef cCE
16561#undef cCL
16562#undef C3E
16563#undef CE
16564#undef CM
16565#undef UE
16566#undef UF
16567#undef UT
16568#undef NUF
16569#undef nUF
16570#undef NCE
16571#undef nCE
16572#undef OPS0
16573#undef OPS1
16574#undef OPS2
16575#undef OPS3
16576#undef OPS4
16577#undef OPS5
16578#undef OPS6
16579#undef do_0
16580
16581/* MD interface: bits in the object file.  */
16582
16583/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16584   for use in the a.out file, and stores them in the array pointed to by buf.
16585   This knows about the endian-ness of the target machine and does
16586   THE RIGHT THING, whatever it is.  Possible values for n are 1 (byte)
16587   2 (short) and 4 (long)  Floating numbers are put out as a series of
16588   LITTLENUMS (shorts, here at least).	*/
16589
16590void
16591md_number_to_chars (char * buf, valueT val, int n)
16592{
16593  if (target_big_endian)
16594    number_to_chars_bigendian (buf, val, n);
16595  else
16596    number_to_chars_littleendian (buf, val, n);
16597}
16598
16599static valueT
16600md_chars_to_number (char * buf, int n)
16601{
16602  valueT result = 0;
16603  unsigned char * where = (unsigned char *) buf;
16604
16605  if (target_big_endian)
16606    {
16607      while (n--)
16608	{
16609	  result <<= 8;
16610	  result |= (*where++ & 255);
16611	}
16612    }
16613  else
16614    {
16615      while (n--)
16616	{
16617	  result <<= 8;
16618	  result |= (where[n] & 255);
16619	}
16620    }
16621
16622  return result;
16623}
16624
16625/* MD interface: Sections.  */
16626
16627/* Estimate the size of a frag before relaxing.  Assume everything fits in
16628   2 bytes.  */
16629
16630int
16631md_estimate_size_before_relax (fragS * fragp,
16632			       segT    segtype ATTRIBUTE_UNUSED)
16633{
16634  fragp->fr_var = 2;
16635  return 2;
16636}
16637
16638/* Convert a machine dependent frag.  */
16639
16640void
16641md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
16642{
16643  unsigned long insn;
16644  unsigned long old_op;
16645  char *buf;
16646  expressionS exp;
16647  fixS *fixp;
16648  int reloc_type;
16649  int pc_rel;
16650  int opcode;
16651
16652  buf = fragp->fr_literal + fragp->fr_fix;
16653
16654  old_op = bfd_get_16(abfd, buf);
16655  if (fragp->fr_symbol) {
16656      exp.X_op = O_symbol;
16657      exp.X_add_symbol = fragp->fr_symbol;
16658  } else {
16659      exp.X_op = O_constant;
16660  }
16661  exp.X_add_number = fragp->fr_offset;
16662  opcode = fragp->fr_subtype;
16663  switch (opcode)
16664    {
16665    case T_MNEM_ldr_pc:
16666    case T_MNEM_ldr_pc2:
16667    case T_MNEM_ldr_sp:
16668    case T_MNEM_str_sp:
16669    case T_MNEM_ldr:
16670    case T_MNEM_ldrb:
16671    case T_MNEM_ldrh:
16672    case T_MNEM_str:
16673    case T_MNEM_strb:
16674    case T_MNEM_strh:
16675      if (fragp->fr_var == 4)
16676	{
16677	  insn = THUMB_OP32(opcode);
16678	  if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
16679	    {
16680	      insn |= (old_op & 0x700) << 4;
16681	    }
16682	  else
16683	    {
16684	      insn |= (old_op & 7) << 12;
16685	      insn |= (old_op & 0x38) << 13;
16686	    }
16687	  insn |= 0x00000c00;
16688	  put_thumb32_insn (buf, insn);
16689	  reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
16690	}
16691      else
16692	{
16693	  reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
16694	}
16695      pc_rel = (opcode == T_MNEM_ldr_pc2);
16696      break;
16697    case T_MNEM_adr:
16698      if (fragp->fr_var == 4)
16699	{
16700	  insn = THUMB_OP32 (opcode);
16701	  insn |= (old_op & 0xf0) << 4;
16702	  put_thumb32_insn (buf, insn);
16703	  reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
16704	}
16705      else
16706	{
16707	  reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16708	  exp.X_add_number -= 4;
16709	}
16710      pc_rel = 1;
16711      break;
16712    case T_MNEM_mov:
16713    case T_MNEM_movs:
16714    case T_MNEM_cmp:
16715    case T_MNEM_cmn:
16716      if (fragp->fr_var == 4)
16717	{
16718	  int r0off = (opcode == T_MNEM_mov
16719		       || opcode == T_MNEM_movs) ? 0 : 8;
16720	  insn = THUMB_OP32 (opcode);
16721	  insn = (insn & 0xe1ffffff) | 0x10000000;
16722	  insn |= (old_op & 0x700) << r0off;
16723	  put_thumb32_insn (buf, insn);
16724	  reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
16725	}
16726      else
16727	{
16728	  reloc_type = BFD_RELOC_ARM_THUMB_IMM;
16729	}
16730      pc_rel = 0;
16731      break;
16732    case T_MNEM_b:
16733      if (fragp->fr_var == 4)
16734	{
16735	  insn = THUMB_OP32(opcode);
16736	  put_thumb32_insn (buf, insn);
16737	  reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
16738	}
16739      else
16740	reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
16741      pc_rel = 1;
16742      break;
16743    case T_MNEM_bcond:
16744      if (fragp->fr_var == 4)
16745	{
16746	  insn = THUMB_OP32(opcode);
16747	  insn |= (old_op & 0xf00) << 14;
16748	  put_thumb32_insn (buf, insn);
16749	  reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
16750	}
16751      else
16752	reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
16753      pc_rel = 1;
16754      break;
16755    case T_MNEM_add_sp:
16756    case T_MNEM_add_pc:
16757    case T_MNEM_inc_sp:
16758    case T_MNEM_dec_sp:
16759      if (fragp->fr_var == 4)
16760	{
16761	  /* ??? Choose between add and addw.  */
16762	  insn = THUMB_OP32 (opcode);
16763	  insn |= (old_op & 0xf0) << 4;
16764	  put_thumb32_insn (buf, insn);
16765	  if (opcode == T_MNEM_add_pc)
16766	    reloc_type = BFD_RELOC_ARM_T32_IMM12;
16767	  else
16768	    reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
16769	}
16770      else
16771	reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16772      pc_rel = 0;
16773      break;
16774
16775    case T_MNEM_addi:
16776    case T_MNEM_addis:
16777    case T_MNEM_subi:
16778    case T_MNEM_subis:
16779      if (fragp->fr_var == 4)
16780	{
16781	  insn = THUMB_OP32 (opcode);
16782	  insn |= (old_op & 0xf0) << 4;
16783	  insn |= (old_op & 0xf) << 16;
16784	  put_thumb32_insn (buf, insn);
16785	  if (insn & (1 << 20))
16786	    reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
16787	  else
16788	    reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
16789	}
16790      else
16791	reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16792      pc_rel = 0;
16793      break;
16794    default:
16795      abort();
16796    }
16797  fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
16798		      reloc_type);
16799  fixp->fx_file = fragp->fr_file;
16800  fixp->fx_line = fragp->fr_line;
16801  fragp->fr_fix += fragp->fr_var;
16802}
16803
16804/* Return the size of a relaxable immediate operand instruction.
16805   SHIFT and SIZE specify the form of the allowable immediate.  */
16806static int
16807relax_immediate (fragS *fragp, int size, int shift)
16808{
16809  offsetT offset;
16810  offsetT mask;
16811  offsetT low;
16812
16813  /* ??? Should be able to do better than this.  */
16814  if (fragp->fr_symbol)
16815    return 4;
16816
16817  low = (1 << shift) - 1;
16818  mask = (1 << (shift + size)) - (1 << shift);
16819  offset = fragp->fr_offset;
16820  /* Force misaligned offsets to 32-bit variant.  */
16821  if (offset & low)
16822    return 4;
16823  if (offset & ~mask)
16824    return 4;
16825  return 2;
16826}
16827
16828/* Get the address of a symbol during relaxation.  */
16829static addressT
16830relaxed_symbol_addr(fragS *fragp, long stretch)
16831{
16832  fragS *sym_frag;
16833  addressT addr;
16834  symbolS *sym;
16835
16836  sym = fragp->fr_symbol;
16837  sym_frag = symbol_get_frag (sym);
16838  know (S_GET_SEGMENT (sym) != absolute_section
16839	|| sym_frag == &zero_address_frag);
16840  addr = S_GET_VALUE (sym) + fragp->fr_offset;
16841
16842  /* If frag has yet to be reached on this pass, assume it will
16843     move by STRETCH just as we did.  If this is not so, it will
16844     be because some frag between grows, and that will force
16845     another pass.  */
16846
16847  if (stretch != 0
16848      && sym_frag->relax_marker != fragp->relax_marker)
16849    addr += stretch;
16850
16851  return addr;
16852}
16853
16854/* Return the size of a relaxable adr pseudo-instruction or PC-relative
16855   load.  */
16856static int
16857relax_adr (fragS *fragp, asection *sec, long stretch)
16858{
16859  addressT addr;
16860  offsetT val;
16861
16862  /* Assume worst case for symbols not known to be in the same section.  */
16863  if (!S_IS_DEFINED(fragp->fr_symbol)
16864      || sec != S_GET_SEGMENT (fragp->fr_symbol))
16865    return 4;
16866
16867  val = relaxed_symbol_addr(fragp, stretch);
16868  addr = fragp->fr_address + fragp->fr_fix;
16869  addr = (addr + 4) & ~3;
16870  /* Force misaligned targets to 32-bit variant.  */
16871  if (val & 3)
16872    return 4;
16873  val -= addr;
16874  if (val < 0 || val > 1020)
16875    return 4;
16876  return 2;
16877}
16878
16879/* Return the size of a relaxable add/sub immediate instruction.  */
16880static int
16881relax_addsub (fragS *fragp, asection *sec)
16882{
16883  char *buf;
16884  int op;
16885
16886  buf = fragp->fr_literal + fragp->fr_fix;
16887  op = bfd_get_16(sec->owner, buf);
16888  if ((op & 0xf) == ((op >> 4) & 0xf))
16889    return relax_immediate (fragp, 8, 0);
16890  else
16891    return relax_immediate (fragp, 3, 0);
16892}
16893
16894
16895/* Return the size of a relaxable branch instruction.  BITS is the
16896   size of the offset field in the narrow instruction.  */
16897
16898static int
16899relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
16900{
16901  addressT addr;
16902  offsetT val;
16903  offsetT limit;
16904
16905  /* Assume worst case for symbols not known to be in the same section.  */
16906  if (!S_IS_DEFINED(fragp->fr_symbol)
16907      || sec != S_GET_SEGMENT (fragp->fr_symbol))
16908    return 4;
16909
16910  val = relaxed_symbol_addr(fragp, stretch);
16911  addr = fragp->fr_address + fragp->fr_fix + 4;
16912  val -= addr;
16913
16914  /* Offset is a signed value *2 */
16915  limit = 1 << bits;
16916  if (val >= limit || val < -limit)
16917    return 4;
16918  return 2;
16919}
16920
16921
16922/* Relax a machine dependent frag.  This returns the amount by which
16923   the current size of the frag should change.  */
16924
16925int
16926arm_relax_frag (asection *sec, fragS *fragp, long stretch)
16927{
16928  int oldsize;
16929  int newsize;
16930
16931  oldsize = fragp->fr_var;
16932  switch (fragp->fr_subtype)
16933    {
16934    case T_MNEM_ldr_pc2:
16935      newsize = relax_adr(fragp, sec, stretch);
16936      break;
16937    case T_MNEM_ldr_pc:
16938    case T_MNEM_ldr_sp:
16939    case T_MNEM_str_sp:
16940      newsize = relax_immediate(fragp, 8, 2);
16941      break;
16942    case T_MNEM_ldr:
16943    case T_MNEM_str:
16944      newsize = relax_immediate(fragp, 5, 2);
16945      break;
16946    case T_MNEM_ldrh:
16947    case T_MNEM_strh:
16948      newsize = relax_immediate(fragp, 5, 1);
16949      break;
16950    case T_MNEM_ldrb:
16951    case T_MNEM_strb:
16952      newsize = relax_immediate(fragp, 5, 0);
16953      break;
16954    case T_MNEM_adr:
16955      newsize = relax_adr(fragp, sec, stretch);
16956      break;
16957    case T_MNEM_mov:
16958    case T_MNEM_movs:
16959    case T_MNEM_cmp:
16960    case T_MNEM_cmn:
16961      newsize = relax_immediate(fragp, 8, 0);
16962      break;
16963    case T_MNEM_b:
16964      newsize = relax_branch(fragp, sec, 11, stretch);
16965      break;
16966    case T_MNEM_bcond:
16967      newsize = relax_branch(fragp, sec, 8, stretch);
16968      break;
16969    case T_MNEM_add_sp:
16970    case T_MNEM_add_pc:
16971      newsize = relax_immediate (fragp, 8, 2);
16972      break;
16973    case T_MNEM_inc_sp:
16974    case T_MNEM_dec_sp:
16975      newsize = relax_immediate (fragp, 7, 2);
16976      break;
16977    case T_MNEM_addi:
16978    case T_MNEM_addis:
16979    case T_MNEM_subi:
16980    case T_MNEM_subis:
16981      newsize = relax_addsub (fragp, sec);
16982      break;
16983    default:
16984      abort();
16985    }
16986
16987  fragp->fr_var = newsize;
16988  /* Freeze wide instructions that are at or before the same location as
16989     in the previous pass.  This avoids infinite loops.
16990     Don't freeze them unconditionally because targets may be artificialy
16991     misaligned by the expansion of preceeding frags.  */
16992  if (stretch <= 0 && newsize > 2)
16993    {
16994      md_convert_frag (sec->owner, sec, fragp);
16995      frag_wane(fragp);
16996    }
16997
16998  return newsize - oldsize;
16999}
17000
17001/* Round up a section size to the appropriate boundary.	 */
17002
17003valueT
17004md_section_align (segT	 segment ATTRIBUTE_UNUSED,
17005		  valueT size)
17006{
17007#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
17008  if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
17009    {
17010      /* For a.out, force the section size to be aligned.  If we don't do
17011	 this, BFD will align it for us, but it will not write out the
17012	 final bytes of the section.  This may be a bug in BFD, but it is
17013	 easier to fix it here since that is how the other a.out targets
17014	 work.  */
17015      int align;
17016
17017      align = bfd_get_section_alignment (stdoutput, segment);
17018      size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
17019    }
17020#endif
17021
17022  return size;
17023}
17024
17025/* This is called from HANDLE_ALIGN in write.c.	 Fill in the contents
17026   of an rs_align_code fragment.  */
17027
17028void
17029arm_handle_align (fragS * fragP)
17030{
17031  static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
17032  static char const thumb_noop[2] = { 0xc0, 0x46 };
17033  static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
17034  static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
17035
17036  int bytes, fix, noop_size;
17037  char * p;
17038  const char * noop;
17039
17040  if (fragP->fr_type != rs_align_code)
17041    return;
17042
17043  bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
17044  p = fragP->fr_literal + fragP->fr_fix;
17045  fix = 0;
17046
17047  if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
17048    bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
17049
17050  if (fragP->tc_frag_data)
17051    {
17052      if (target_big_endian)
17053	noop = thumb_bigend_noop;
17054      else
17055	noop = thumb_noop;
17056      noop_size = sizeof (thumb_noop);
17057    }
17058  else
17059    {
17060      if (target_big_endian)
17061	noop = arm_bigend_noop;
17062      else
17063	noop = arm_noop;
17064      noop_size = sizeof (arm_noop);
17065    }
17066
17067  if (bytes & (noop_size - 1))
17068    {
17069      fix = bytes & (noop_size - 1);
17070      memset (p, 0, fix);
17071      p += fix;
17072      bytes -= fix;
17073    }
17074
17075  while (bytes >= noop_size)
17076    {
17077      memcpy (p, noop, noop_size);
17078      p += noop_size;
17079      bytes -= noop_size;
17080      fix += noop_size;
17081    }
17082
17083  fragP->fr_fix += fix;
17084  fragP->fr_var = noop_size;
17085}
17086
17087/* Called from md_do_align.  Used to create an alignment
17088   frag in a code section.  */
17089
17090void
17091arm_frag_align_code (int n, int max)
17092{
17093  char * p;
17094
17095  /* We assume that there will never be a requirement
17096     to support alignments greater than 32 bytes.  */
17097  if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
17098    as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17099
17100  p = frag_var (rs_align_code,
17101		MAX_MEM_FOR_RS_ALIGN_CODE,
17102		1,
17103		(relax_substateT) max,
17104		(symbolS *) NULL,
17105		(offsetT) n,
17106		(char *) NULL);
17107  *p = 0;
17108}
17109
17110/* Perform target specific initialisation of a frag.  */
17111
17112void
17113arm_init_frag (fragS * fragP)
17114{
17115  /* Record whether this frag is in an ARM or a THUMB area.  */
17116  fragP->tc_frag_data = thumb_mode;
17117}
17118
17119#ifdef OBJ_ELF
17120/* When we change sections we need to issue a new mapping symbol.  */
17121
17122void
17123arm_elf_change_section (void)
17124{
17125  flagword flags;
17126  segment_info_type *seginfo;
17127
17128  /* Link an unlinked unwind index table section to the .text section.	*/
17129  if (elf_section_type (now_seg) == SHT_ARM_EXIDX
17130      && elf_linked_to_section (now_seg) == NULL)
17131    elf_linked_to_section (now_seg) = text_section;
17132
17133  if (!SEG_NORMAL (now_seg))
17134    return;
17135
17136  flags = bfd_get_section_flags (stdoutput, now_seg);
17137
17138  /* We can ignore sections that only contain debug info.  */
17139  if ((flags & SEC_ALLOC) == 0)
17140    return;
17141
17142  seginfo = seg_info (now_seg);
17143  mapstate = seginfo->tc_segment_info_data.mapstate;
17144  marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
17145}
17146
17147int
17148arm_elf_section_type (const char * str, size_t len)
17149{
17150  if (len == 5 && strncmp (str, "exidx", 5) == 0)
17151    return SHT_ARM_EXIDX;
17152
17153  return -1;
17154}
17155
17156/* Code to deal with unwinding tables.	*/
17157
17158static void add_unwind_adjustsp (offsetT);
17159
17160/* Cenerate and deferred unwind frame offset.  */
17161
17162static void
17163flush_pending_unwind (void)
17164{
17165  offsetT offset;
17166
17167  offset = unwind.pending_offset;
17168  unwind.pending_offset = 0;
17169  if (offset != 0)
17170    add_unwind_adjustsp (offset);
17171}
17172
17173/* Add an opcode to this list for this function.  Two-byte opcodes should
17174   be passed as op[0] << 8 | op[1].  The list of opcodes is built in reverse
17175   order.  */
17176
17177static void
17178add_unwind_opcode (valueT op, int length)
17179{
17180  /* Add any deferred stack adjustment.	 */
17181  if (unwind.pending_offset)
17182    flush_pending_unwind ();
17183
17184  unwind.sp_restored = 0;
17185
17186  if (unwind.opcode_count + length > unwind.opcode_alloc)
17187    {
17188      unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
17189      if (unwind.opcodes)
17190	unwind.opcodes = xrealloc (unwind.opcodes,
17191				   unwind.opcode_alloc);
17192      else
17193	unwind.opcodes = xmalloc (unwind.opcode_alloc);
17194    }
17195  while (length > 0)
17196    {
17197      length--;
17198      unwind.opcodes[unwind.opcode_count] = op & 0xff;
17199      op >>= 8;
17200      unwind.opcode_count++;
17201    }
17202}
17203
17204/* Add unwind opcodes to adjust the stack pointer.  */
17205
17206static void
17207add_unwind_adjustsp (offsetT offset)
17208{
17209  valueT op;
17210
17211  if (offset > 0x200)
17212    {
17213      /* We need at most 5 bytes to hold a 32-bit value in a uleb128.  */
17214      char bytes[5];
17215      int n;
17216      valueT o;
17217
17218      /* Long form: 0xb2, uleb128.  */
17219      /* This might not fit in a word so add the individual bytes,
17220	 remembering the list is built in reverse order.  */
17221      o = (valueT) ((offset - 0x204) >> 2);
17222      if (o == 0)
17223	add_unwind_opcode (0, 1);
17224
17225      /* Calculate the uleb128 encoding of the offset.	*/
17226      n = 0;
17227      while (o)
17228	{
17229	  bytes[n] = o & 0x7f;
17230	  o >>= 7;
17231	  if (o)
17232	    bytes[n] |= 0x80;
17233	  n++;
17234	}
17235      /* Add the insn.	*/
17236      for (; n; n--)
17237	add_unwind_opcode (bytes[n - 1], 1);
17238      add_unwind_opcode (0xb2, 1);
17239    }
17240  else if (offset > 0x100)
17241    {
17242      /* Two short opcodes.  */
17243      add_unwind_opcode (0x3f, 1);
17244      op = (offset - 0x104) >> 2;
17245      add_unwind_opcode (op, 1);
17246    }
17247  else if (offset > 0)
17248    {
17249      /* Short opcode.	*/
17250      op = (offset - 4) >> 2;
17251      add_unwind_opcode (op, 1);
17252    }
17253  else if (offset < 0)
17254    {
17255      offset = -offset;
17256      while (offset > 0x100)
17257	{
17258	  add_unwind_opcode (0x7f, 1);
17259	  offset -= 0x100;
17260	}
17261      op = ((offset - 4) >> 2) | 0x40;
17262      add_unwind_opcode (op, 1);
17263    }
17264}
17265
17266/* Finish the list of unwind opcodes for this function.	 */
17267static void
17268finish_unwind_opcodes (void)
17269{
17270  valueT op;
17271
17272  if (unwind.fp_used)
17273    {
17274      /* Adjust sp as necessary.  */
17275      unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
17276      flush_pending_unwind ();
17277
17278      /* After restoring sp from the frame pointer.  */
17279      op = 0x90 | unwind.fp_reg;
17280      add_unwind_opcode (op, 1);
17281    }
17282  else
17283    flush_pending_unwind ();
17284}
17285
17286
17287/* Start an exception table entry.  If idx is nonzero this is an index table
17288   entry.  */
17289
17290static void
17291start_unwind_section (const segT text_seg, int idx)
17292{
17293  const char * text_name;
17294  const char * prefix;
17295  const char * prefix_once;
17296  const char * group_name;
17297  size_t prefix_len;
17298  size_t text_len;
17299  char * sec_name;
17300  size_t sec_name_len;
17301  int type;
17302  int flags;
17303  int linkonce;
17304
17305  if (idx)
17306    {
17307      prefix = ELF_STRING_ARM_unwind;
17308      prefix_once = ELF_STRING_ARM_unwind_once;
17309      type = SHT_ARM_EXIDX;
17310    }
17311  else
17312    {
17313      prefix = ELF_STRING_ARM_unwind_info;
17314      prefix_once = ELF_STRING_ARM_unwind_info_once;
17315      type = SHT_PROGBITS;
17316    }
17317
17318  text_name = segment_name (text_seg);
17319  if (streq (text_name, ".text"))
17320    text_name = "";
17321
17322  if (strncmp (text_name, ".gnu.linkonce.t.",
17323	       strlen (".gnu.linkonce.t.")) == 0)
17324    {
17325      prefix = prefix_once;
17326      text_name += strlen (".gnu.linkonce.t.");
17327    }
17328
17329  prefix_len = strlen (prefix);
17330  text_len = strlen (text_name);
17331  sec_name_len = prefix_len + text_len;
17332  sec_name = xmalloc (sec_name_len + 1);
17333  memcpy (sec_name, prefix, prefix_len);
17334  memcpy (sec_name + prefix_len, text_name, text_len);
17335  sec_name[prefix_len + text_len] = '\0';
17336
17337  flags = SHF_ALLOC;
17338  linkonce = 0;
17339  group_name = 0;
17340
17341  /* Handle COMDAT group.  */
17342  if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
17343    {
17344      group_name = elf_group_name (text_seg);
17345      if (group_name == NULL)
17346	{
17347	  as_bad ("Group section `%s' has no group signature",
17348		  segment_name (text_seg));
17349	  ignore_rest_of_line ();
17350	  return;
17351	}
17352      flags |= SHF_GROUP;
17353      linkonce = 1;
17354    }
17355
17356  obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
17357
17358  /* Set the setion link for index tables.  */
17359  if (idx)
17360    elf_linked_to_section (now_seg) = text_seg;
17361}
17362
17363
17364/* Start an unwind table entry.	 HAVE_DATA is nonzero if we have additional
17365   personality routine data.  Returns zero, or the index table value for
17366   and inline entry.  */
17367
17368static valueT
17369create_unwind_entry (int have_data)
17370{
17371  int size;
17372  addressT where;
17373  char *ptr;
17374  /* The current word of data.	*/
17375  valueT data;
17376  /* The number of bytes left in this word.  */
17377  int n;
17378
17379  finish_unwind_opcodes ();
17380
17381  /* Remember the current text section.	 */
17382  unwind.saved_seg = now_seg;
17383  unwind.saved_subseg = now_subseg;
17384
17385  start_unwind_section (now_seg, 0);
17386
17387  if (unwind.personality_routine == NULL)
17388    {
17389      if (unwind.personality_index == -2)
17390	{
17391	  if (have_data)
17392	    as_bad (_("handerdata in cantunwind frame"));
17393	  return 1; /* EXIDX_CANTUNWIND.  */
17394	}
17395
17396      /* Use a default personality routine if none is specified.  */
17397      if (unwind.personality_index == -1)
17398	{
17399	  if (unwind.opcode_count > 3)
17400	    unwind.personality_index = 1;
17401	  else
17402	    unwind.personality_index = 0;
17403	}
17404
17405      /* Space for the personality routine entry.  */
17406      if (unwind.personality_index == 0)
17407	{
17408	  if (unwind.opcode_count > 3)
17409	    as_bad (_("too many unwind opcodes for personality routine 0"));
17410
17411	  if (!have_data)
17412	    {
17413	      /* All the data is inline in the index table.  */
17414	      data = 0x80;
17415	      n = 3;
17416	      while (unwind.opcode_count > 0)
17417		{
17418		  unwind.opcode_count--;
17419		  data = (data << 8) | unwind.opcodes[unwind.opcode_count];
17420		  n--;
17421		}
17422
17423	      /* Pad with "finish" opcodes.  */
17424	      while (n--)
17425		data = (data << 8) | 0xb0;
17426
17427	      return data;
17428	    }
17429	  size = 0;
17430	}
17431      else
17432	/* We get two opcodes "free" in the first word.	 */
17433	size = unwind.opcode_count - 2;
17434    }
17435  else
17436    /* An extra byte is required for the opcode count.	*/
17437    size = unwind.opcode_count + 1;
17438
17439  size = (size + 3) >> 2;
17440  if (size > 0xff)
17441    as_bad (_("too many unwind opcodes"));
17442
17443  frag_align (2, 0, 0);
17444  record_alignment (now_seg, 2);
17445  unwind.table_entry = expr_build_dot ();
17446
17447  /* Allocate the table entry.	*/
17448  ptr = frag_more ((size << 2) + 4);
17449  memset(ptr, 0, (size << 2) + 4);
17450  where = frag_now_fix () - ((size << 2) + 4);
17451
17452  switch (unwind.personality_index)
17453    {
17454    case -1:
17455      /* ??? Should this be a PLT generating relocation?  */
17456      /* Custom personality routine.  */
17457      fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
17458	       BFD_RELOC_ARM_PREL31);
17459
17460      where += 4;
17461      ptr += 4;
17462
17463      /* Set the first byte to the number of additional words.	*/
17464      data = size - 1;
17465      n = 3;
17466      break;
17467
17468    /* ABI defined personality routines.  */
17469    case 0:
17470      /* Three opcodes bytes are packed into the first word.  */
17471      data = 0x80;
17472      n = 3;
17473      break;
17474
17475    case 1:
17476    case 2:
17477      /* The size and first two opcode bytes go in the first word.  */
17478      data = ((0x80 + unwind.personality_index) << 8) | size;
17479      n = 2;
17480      break;
17481
17482    default:
17483      /* Should never happen.  */
17484      abort ();
17485    }
17486
17487  /* Pack the opcodes into words (MSB first), reversing the list at the same
17488     time.  */
17489  while (unwind.opcode_count > 0)
17490    {
17491      if (n == 0)
17492	{
17493	  md_number_to_chars (ptr, data, 4);
17494	  ptr += 4;
17495	  n = 4;
17496	  data = 0;
17497	}
17498      unwind.opcode_count--;
17499      n--;
17500      data = (data << 8) | unwind.opcodes[unwind.opcode_count];
17501    }
17502
17503  /* Finish off the last word.	*/
17504  if (n < 4)
17505    {
17506      /* Pad with "finish" opcodes.  */
17507      while (n--)
17508	data = (data << 8) | 0xb0;
17509
17510      md_number_to_chars (ptr, data, 4);
17511    }
17512
17513  if (!have_data)
17514    {
17515      /* Add an empty descriptor if there is no user-specified data.   */
17516      ptr = frag_more (4);
17517      md_number_to_chars (ptr, 0, 4);
17518    }
17519
17520  return 0;
17521}
17522
17523
17524/* Initialize the DWARF-2 unwind information for this procedure.  */
17525
17526void
17527tc_arm_frame_initial_instructions (void)
17528{
17529  cfi_add_CFA_def_cfa (REG_SP, 0);
17530}
17531#endif /* OBJ_ELF */
17532
17533/* Convert REGNAME to a DWARF-2 register number.  */
17534
17535int
17536tc_arm_regname_to_dw2regnum (char *regname)
17537{
17538  int reg = arm_reg_parse (&regname, REG_TYPE_RN);
17539
17540  if (reg == FAIL)
17541    return -1;
17542
17543  return reg;
17544}
17545
17546#ifdef TE_PE
17547void
17548tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
17549{
17550  expressionS expr;
17551
17552  expr.X_op = O_secrel;
17553  expr.X_add_symbol = symbol;
17554  expr.X_add_number = 0;
17555  emit_expr (&expr, size);
17556}
17557#endif
17558
17559/* MD interface: Symbol and relocation handling.  */
17560
17561/* Return the address within the segment that a PC-relative fixup is
17562   relative to.  For ARM, PC-relative fixups applied to instructions
17563   are generally relative to the location of the fixup plus 8 bytes.
17564   Thumb branches are offset by 4, and Thumb loads relative to PC
17565   require special handling.  */
17566
17567long
17568md_pcrel_from_section (fixS * fixP, segT seg)
17569{
17570  offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
17571
17572  /* If this is pc-relative and we are going to emit a relocation
17573     then we just want to put out any pipeline compensation that the linker
17574     will need.  Otherwise we want to use the calculated base.
17575     For WinCE we skip the bias for externals as well, since this
17576     is how the MS ARM-CE assembler behaves and we want to be compatible.  */
17577  if (fixP->fx_pcrel
17578      && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
17579	  || (arm_force_relocation (fixP)
17580#ifdef TE_WINCE
17581	      && !S_IS_EXTERNAL (fixP->fx_addsy)
17582#endif
17583	      )))
17584    base = 0;
17585
17586  switch (fixP->fx_r_type)
17587    {
17588      /* PC relative addressing on the Thumb is slightly odd as the
17589	 bottom two bits of the PC are forced to zero for the
17590	 calculation.  This happens *after* application of the
17591	 pipeline offset.  However, Thumb adrl already adjusts for
17592	 this, so we need not do it again.  */
17593    case BFD_RELOC_ARM_THUMB_ADD:
17594      return base & ~3;
17595
17596    case BFD_RELOC_ARM_THUMB_OFFSET:
17597    case BFD_RELOC_ARM_T32_OFFSET_IMM:
17598    case BFD_RELOC_ARM_T32_ADD_PC12:
17599    case BFD_RELOC_ARM_T32_CP_OFF_IMM:
17600      return (base + 4) & ~3;
17601
17602      /* Thumb branches are simply offset by +4.  */
17603    case BFD_RELOC_THUMB_PCREL_BRANCH7:
17604    case BFD_RELOC_THUMB_PCREL_BRANCH9:
17605    case BFD_RELOC_THUMB_PCREL_BRANCH12:
17606    case BFD_RELOC_THUMB_PCREL_BRANCH20:
17607    case BFD_RELOC_THUMB_PCREL_BRANCH23:
17608    case BFD_RELOC_THUMB_PCREL_BRANCH25:
17609    case BFD_RELOC_THUMB_PCREL_BLX:
17610      return base + 4;
17611
17612      /* ARM mode branches are offset by +8.  However, the Windows CE
17613	 loader expects the relocation not to take this into account.  */
17614    case BFD_RELOC_ARM_PCREL_BRANCH:
17615    case BFD_RELOC_ARM_PCREL_CALL:
17616    case BFD_RELOC_ARM_PCREL_JUMP:
17617    case BFD_RELOC_ARM_PCREL_BLX:
17618    case BFD_RELOC_ARM_PLT32:
17619#ifdef TE_WINCE
17620      /* When handling fixups immediately, because we have already
17621         discovered the value of a symbol, or the address of the frag involved
17622	 we must account for the offset by +8, as the OS loader will never see the reloc.
17623         see fixup_segment() in write.c
17624         The S_IS_EXTERNAL test handles the case of global symbols.
17625         Those need the calculated base, not just the pipe compensation the linker will need.  */
17626      if (fixP->fx_pcrel
17627	  && fixP->fx_addsy != NULL
17628	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
17629	  && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
17630	return base + 8;
17631      return base;
17632#else
17633      return base + 8;
17634#endif
17635
17636      /* ARM mode loads relative to PC are also offset by +8.  Unlike
17637	 branches, the Windows CE loader *does* expect the relocation
17638	 to take this into account.  */
17639    case BFD_RELOC_ARM_OFFSET_IMM:
17640    case BFD_RELOC_ARM_OFFSET_IMM8:
17641    case BFD_RELOC_ARM_HWLITERAL:
17642    case BFD_RELOC_ARM_LITERAL:
17643    case BFD_RELOC_ARM_CP_OFF_IMM:
17644      return base + 8;
17645
17646
17647      /* Other PC-relative relocations are un-offset.  */
17648    default:
17649      return base;
17650    }
17651}
17652
17653/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17654   Otherwise we have no need to default values of symbols.  */
17655
17656symbolS *
17657md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
17658{
17659#ifdef OBJ_ELF
17660  if (name[0] == '_' && name[1] == 'G'
17661      && streq (name, GLOBAL_OFFSET_TABLE_NAME))
17662    {
17663      if (!GOT_symbol)
17664	{
17665	  if (symbol_find (name))
17666	    as_bad ("GOT already in the symbol table");
17667
17668	  GOT_symbol = symbol_new (name, undefined_section,
17669				   (valueT) 0, & zero_address_frag);
17670	}
17671
17672      return GOT_symbol;
17673    }
17674#endif
17675
17676  return 0;
17677}
17678
17679/* Subroutine of md_apply_fix.	 Check to see if an immediate can be
17680   computed as two separate immediate values, added together.  We
17681   already know that this value cannot be computed by just one ARM
17682   instruction.	 */
17683
17684static unsigned int
17685validate_immediate_twopart (unsigned int   val,
17686			    unsigned int * highpart)
17687{
17688  unsigned int a;
17689  unsigned int i;
17690
17691  for (i = 0; i < 32; i += 2)
17692    if (((a = rotate_left (val, i)) & 0xff) != 0)
17693      {
17694	if (a & 0xff00)
17695	  {
17696	    if (a & ~ 0xffff)
17697	      continue;
17698	    * highpart = (a  >> 8) | ((i + 24) << 7);
17699	  }
17700	else if (a & 0xff0000)
17701	  {
17702	    if (a & 0xff000000)
17703	      continue;
17704	    * highpart = (a >> 16) | ((i + 16) << 7);
17705	  }
17706	else
17707	  {
17708	    assert (a & 0xff000000);
17709	    * highpart = (a >> 24) | ((i + 8) << 7);
17710	  }
17711
17712	return (a & 0xff) | (i << 7);
17713      }
17714
17715  return FAIL;
17716}
17717
17718static int
17719validate_offset_imm (unsigned int val, int hwse)
17720{
17721  if ((hwse && val > 255) || val > 4095)
17722    return FAIL;
17723  return val;
17724}
17725
17726/* Subroutine of md_apply_fix.	 Do those data_ops which can take a
17727   negative immediate constant by altering the instruction.  A bit of
17728   a hack really.
17729	MOV <-> MVN
17730	AND <-> BIC
17731	ADC <-> SBC
17732	by inverting the second operand, and
17733	ADD <-> SUB
17734	CMP <-> CMN
17735	by negating the second operand.	 */
17736
17737static int
17738negate_data_op (unsigned long * instruction,
17739		unsigned long	value)
17740{
17741  int op, new_inst;
17742  unsigned long negated, inverted;
17743
17744  negated = encode_arm_immediate (-value);
17745  inverted = encode_arm_immediate (~value);
17746
17747  op = (*instruction >> DATA_OP_SHIFT) & 0xf;
17748  switch (op)
17749    {
17750      /* First negates.	 */
17751    case OPCODE_SUB:		 /* ADD <-> SUB	 */
17752      new_inst = OPCODE_ADD;
17753      value = negated;
17754      break;
17755
17756    case OPCODE_ADD:
17757      new_inst = OPCODE_SUB;
17758      value = negated;
17759      break;
17760
17761    case OPCODE_CMP:		 /* CMP <-> CMN	 */
17762      new_inst = OPCODE_CMN;
17763      value = negated;
17764      break;
17765
17766    case OPCODE_CMN:
17767      new_inst = OPCODE_CMP;
17768      value = negated;
17769      break;
17770
17771      /* Now Inverted ops.  */
17772    case OPCODE_MOV:		 /* MOV <-> MVN	 */
17773      new_inst = OPCODE_MVN;
17774      value = inverted;
17775      break;
17776
17777    case OPCODE_MVN:
17778      new_inst = OPCODE_MOV;
17779      value = inverted;
17780      break;
17781
17782    case OPCODE_AND:		 /* AND <-> BIC	 */
17783      new_inst = OPCODE_BIC;
17784      value = inverted;
17785      break;
17786
17787    case OPCODE_BIC:
17788      new_inst = OPCODE_AND;
17789      value = inverted;
17790      break;
17791
17792    case OPCODE_ADC:		  /* ADC <-> SBC  */
17793      new_inst = OPCODE_SBC;
17794      value = inverted;
17795      break;
17796
17797    case OPCODE_SBC:
17798      new_inst = OPCODE_ADC;
17799      value = inverted;
17800      break;
17801
17802      /* We cannot do anything.	 */
17803    default:
17804      return FAIL;
17805    }
17806
17807  if (value == (unsigned) FAIL)
17808    return FAIL;
17809
17810  *instruction &= OPCODE_MASK;
17811  *instruction |= new_inst << DATA_OP_SHIFT;
17812  return value;
17813}
17814
17815/* Like negate_data_op, but for Thumb-2.   */
17816
17817static unsigned int
17818thumb32_negate_data_op (offsetT *instruction, unsigned int value)
17819{
17820  int op, new_inst;
17821  int rd;
17822  unsigned int negated, inverted;
17823
17824  negated = encode_thumb32_immediate (-value);
17825  inverted = encode_thumb32_immediate (~value);
17826
17827  rd = (*instruction >> 8) & 0xf;
17828  op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
17829  switch (op)
17830    {
17831      /* ADD <-> SUB.  Includes CMP <-> CMN.  */
17832    case T2_OPCODE_SUB:
17833      new_inst = T2_OPCODE_ADD;
17834      value = negated;
17835      break;
17836
17837    case T2_OPCODE_ADD:
17838      new_inst = T2_OPCODE_SUB;
17839      value = negated;
17840      break;
17841
17842      /* ORR <-> ORN.  Includes MOV <-> MVN.  */
17843    case T2_OPCODE_ORR:
17844      new_inst = T2_OPCODE_ORN;
17845      value = inverted;
17846      break;
17847
17848    case T2_OPCODE_ORN:
17849      new_inst = T2_OPCODE_ORR;
17850      value = inverted;
17851      break;
17852
17853      /* AND <-> BIC.  TST has no inverted equivalent.  */
17854    case T2_OPCODE_AND:
17855      new_inst = T2_OPCODE_BIC;
17856      if (rd == 15)
17857	value = FAIL;
17858      else
17859	value = inverted;
17860      break;
17861
17862    case T2_OPCODE_BIC:
17863      new_inst = T2_OPCODE_AND;
17864      value = inverted;
17865      break;
17866
17867      /* ADC <-> SBC  */
17868    case T2_OPCODE_ADC:
17869      new_inst = T2_OPCODE_SBC;
17870      value = inverted;
17871      break;
17872
17873    case T2_OPCODE_SBC:
17874      new_inst = T2_OPCODE_ADC;
17875      value = inverted;
17876      break;
17877
17878      /* We cannot do anything.	 */
17879    default:
17880      return FAIL;
17881    }
17882
17883  if (value == (unsigned int)FAIL)
17884    return FAIL;
17885
17886  *instruction &= T2_OPCODE_MASK;
17887  *instruction |= new_inst << T2_DATA_OP_SHIFT;
17888  return value;
17889}
17890
17891/* Read a 32-bit thumb instruction from buf.  */
17892static unsigned long
17893get_thumb32_insn (char * buf)
17894{
17895  unsigned long insn;
17896  insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
17897  insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
17898
17899  return insn;
17900}
17901
17902
17903/* We usually want to set the low bit on the address of thumb function
17904   symbols.  In particular .word foo - . should have the low bit set.
17905   Generic code tries to fold the difference of two symbols to
17906   a constant.  Prevent this and force a relocation when the first symbols
17907   is a thumb function.  */
17908int
17909arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
17910{
17911  if (op == O_subtract
17912      && l->X_op == O_symbol
17913      && r->X_op == O_symbol
17914      && THUMB_IS_FUNC (l->X_add_symbol))
17915    {
17916      l->X_op = O_subtract;
17917      l->X_op_symbol = r->X_add_symbol;
17918      l->X_add_number -= r->X_add_number;
17919      return 1;
17920    }
17921  /* Process as normal.  */
17922  return 0;
17923}
17924
17925void
17926md_apply_fix (fixS *	fixP,
17927	       valueT * valP,
17928	       segT	seg)
17929{
17930  offsetT	 value = * valP;
17931  offsetT	 newval;
17932  unsigned int	 newimm;
17933  unsigned long	 temp;
17934  int		 sign;
17935  char *	 buf = fixP->fx_where + fixP->fx_frag->fr_literal;
17936
17937  assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
17938
17939  /* Note whether this will delete the relocation.  */
17940
17941  if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
17942    fixP->fx_done = 1;
17943
17944  /* On a 64-bit host, silently truncate 'value' to 32 bits for
17945     consistency with the behavior on 32-bit hosts.  Remember value
17946     for emit_reloc.  */
17947  value &= 0xffffffff;
17948  value ^= 0x80000000;
17949  value -= 0x80000000;
17950
17951  *valP = value;
17952  fixP->fx_addnumber = value;
17953
17954  /* Same treatment for fixP->fx_offset.  */
17955  fixP->fx_offset &= 0xffffffff;
17956  fixP->fx_offset ^= 0x80000000;
17957  fixP->fx_offset -= 0x80000000;
17958
17959  switch (fixP->fx_r_type)
17960    {
17961    case BFD_RELOC_NONE:
17962      /* This will need to go in the object file.  */
17963      fixP->fx_done = 0;
17964      break;
17965
17966    case BFD_RELOC_ARM_IMMEDIATE:
17967      /* We claim that this fixup has been processed here,
17968	 even if in fact we generate an error because we do
17969	 not have a reloc for it, so tc_gen_reloc will reject it.  */
17970      fixP->fx_done = 1;
17971
17972      if (fixP->fx_addsy
17973	  && ! S_IS_DEFINED (fixP->fx_addsy))
17974	{
17975	  as_bad_where (fixP->fx_file, fixP->fx_line,
17976			_("undefined symbol %s used as an immediate value"),
17977			S_GET_NAME (fixP->fx_addsy));
17978	  break;
17979	}
17980
17981      newimm = encode_arm_immediate (value);
17982      temp = md_chars_to_number (buf, INSN_SIZE);
17983
17984      /* If the instruction will fail, see if we can fix things up by
17985	 changing the opcode.  */
17986      if (newimm == (unsigned int) FAIL
17987	  && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
17988	{
17989	  as_bad_where (fixP->fx_file, fixP->fx_line,
17990			_("invalid constant (%lx) after fixup"),
17991			(unsigned long) value);
17992	  break;
17993	}
17994
17995      newimm |= (temp & 0xfffff000);
17996      md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
17997      break;
17998
17999    case BFD_RELOC_ARM_ADRL_IMMEDIATE:
18000      {
18001	unsigned int highpart = 0;
18002	unsigned int newinsn  = 0xe1a00000; /* nop.  */
18003
18004	newimm = encode_arm_immediate (value);
18005	temp = md_chars_to_number (buf, INSN_SIZE);
18006
18007	/* If the instruction will fail, see if we can fix things up by
18008	   changing the opcode.	 */
18009	if (newimm == (unsigned int) FAIL
18010	    && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
18011	  {
18012	    /* No ?  OK - try using two ADD instructions to generate
18013	       the value.  */
18014	    newimm = validate_immediate_twopart (value, & highpart);
18015
18016	    /* Yes - then make sure that the second instruction is
18017	       also an add.  */
18018	    if (newimm != (unsigned int) FAIL)
18019	      newinsn = temp;
18020	    /* Still No ?  Try using a negated value.  */
18021	    else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
18022	      temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
18023	    /* Otherwise - give up.  */
18024	    else
18025	      {
18026		as_bad_where (fixP->fx_file, fixP->fx_line,
18027			      _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18028			      (long) value);
18029		break;
18030	      }
18031
18032	    /* Replace the first operand in the 2nd instruction (which
18033	       is the PC) with the destination register.  We have
18034	       already added in the PC in the first instruction and we
18035	       do not want to do it again.  */
18036	    newinsn &= ~ 0xf0000;
18037	    newinsn |= ((newinsn & 0x0f000) << 4);
18038	  }
18039
18040	newimm |= (temp & 0xfffff000);
18041	md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
18042
18043	highpart |= (newinsn & 0xfffff000);
18044	md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
18045      }
18046      break;
18047
18048    case BFD_RELOC_ARM_OFFSET_IMM:
18049      if (!fixP->fx_done && seg->use_rela_p)
18050	value = 0;
18051
18052    case BFD_RELOC_ARM_LITERAL:
18053      sign = value >= 0;
18054
18055      if (value < 0)
18056	value = - value;
18057
18058      if (validate_offset_imm (value, 0) == FAIL)
18059	{
18060	  if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
18061	    as_bad_where (fixP->fx_file, fixP->fx_line,
18062			  _("invalid literal constant: pool needs to be closer"));
18063	  else
18064	    as_bad_where (fixP->fx_file, fixP->fx_line,
18065			  _("bad immediate value for offset (%ld)"),
18066			  (long) value);
18067	  break;
18068	}
18069
18070      newval = md_chars_to_number (buf, INSN_SIZE);
18071      newval &= 0xff7ff000;
18072      newval |= value | (sign ? INDEX_UP : 0);
18073      md_number_to_chars (buf, newval, INSN_SIZE);
18074      break;
18075
18076    case BFD_RELOC_ARM_OFFSET_IMM8:
18077    case BFD_RELOC_ARM_HWLITERAL:
18078      sign = value >= 0;
18079
18080      if (value < 0)
18081	value = - value;
18082
18083      if (validate_offset_imm (value, 1) == FAIL)
18084	{
18085	  if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
18086	    as_bad_where (fixP->fx_file, fixP->fx_line,
18087			  _("invalid literal constant: pool needs to be closer"));
18088	  else
18089	    as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18090		    (long) value);
18091	  break;
18092	}
18093
18094      newval = md_chars_to_number (buf, INSN_SIZE);
18095      newval &= 0xff7ff0f0;
18096      newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
18097      md_number_to_chars (buf, newval, INSN_SIZE);
18098      break;
18099
18100    case BFD_RELOC_ARM_T32_OFFSET_U8:
18101      if (value < 0 || value > 1020 || value % 4 != 0)
18102	as_bad_where (fixP->fx_file, fixP->fx_line,
18103		      _("bad immediate value for offset (%ld)"), (long) value);
18104      value /= 4;
18105
18106      newval = md_chars_to_number (buf+2, THUMB_SIZE);
18107      newval |= value;
18108      md_number_to_chars (buf+2, newval, THUMB_SIZE);
18109      break;
18110
18111    case BFD_RELOC_ARM_T32_OFFSET_IMM:
18112      /* This is a complicated relocation used for all varieties of Thumb32
18113	 load/store instruction with immediate offset:
18114
18115	 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18116	                                           *4, optional writeback(W)
18117						   (doubleword load/store)
18118
18119	 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18120	 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18121	 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18122	 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18123	 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18124
18125	 Uppercase letters indicate bits that are already encoded at
18126	 this point.  Lowercase letters are our problem.  For the
18127	 second block of instructions, the secondary opcode nybble
18128	 (bits 8..11) is present, and bit 23 is zero, even if this is
18129	 a PC-relative operation.  */
18130      newval = md_chars_to_number (buf, THUMB_SIZE);
18131      newval <<= 16;
18132      newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
18133
18134      if ((newval & 0xf0000000) == 0xe0000000)
18135	{
18136	  /* Doubleword load/store: 8-bit offset, scaled by 4.  */
18137	  if (value >= 0)
18138	    newval |= (1 << 23);
18139	  else
18140	    value = -value;
18141	  if (value % 4 != 0)
18142	    {
18143	      as_bad_where (fixP->fx_file, fixP->fx_line,
18144			    _("offset not a multiple of 4"));
18145	      break;
18146	    }
18147	  value /= 4;
18148	  if (value > 0xff)
18149	    {
18150	      as_bad_where (fixP->fx_file, fixP->fx_line,
18151			    _("offset out of range"));
18152	      break;
18153	    }
18154	  newval &= ~0xff;
18155	}
18156      else if ((newval & 0x000f0000) == 0x000f0000)
18157	{
18158	  /* PC-relative, 12-bit offset.  */
18159	  if (value >= 0)
18160	    newval |= (1 << 23);
18161	  else
18162	    value = -value;
18163	  if (value > 0xfff)
18164	    {
18165	      as_bad_where (fixP->fx_file, fixP->fx_line,
18166			    _("offset out of range"));
18167	      break;
18168	    }
18169	  newval &= ~0xfff;
18170	}
18171      else if ((newval & 0x00000100) == 0x00000100)
18172	{
18173	  /* Writeback: 8-bit, +/- offset.  */
18174	  if (value >= 0)
18175	    newval |= (1 << 9);
18176	  else
18177	    value = -value;
18178	  if (value > 0xff)
18179	    {
18180	      as_bad_where (fixP->fx_file, fixP->fx_line,
18181			    _("offset out of range"));
18182	      break;
18183	    }
18184	  newval &= ~0xff;
18185	}
18186      else if ((newval & 0x00000f00) == 0x00000e00)
18187	{
18188	  /* T-instruction: positive 8-bit offset.  */
18189	  if (value < 0 || value > 0xff)
18190	    {
18191	      as_bad_where (fixP->fx_file, fixP->fx_line,
18192			    _("offset out of range"));
18193	      break;
18194	    }
18195	  newval &= ~0xff;
18196	  newval |= value;
18197	}
18198      else
18199	{
18200	  /* Positive 12-bit or negative 8-bit offset.  */
18201	  int limit;
18202	  if (value >= 0)
18203	    {
18204	      newval |= (1 << 23);
18205	      limit = 0xfff;
18206	    }
18207	  else
18208	    {
18209	      value = -value;
18210	      limit = 0xff;
18211	    }
18212	  if (value > limit)
18213	    {
18214	      as_bad_where (fixP->fx_file, fixP->fx_line,
18215			    _("offset out of range"));
18216	      break;
18217	    }
18218	  newval &= ~limit;
18219	}
18220
18221      newval |= value;
18222      md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
18223      md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
18224      break;
18225
18226    case BFD_RELOC_ARM_SHIFT_IMM:
18227      newval = md_chars_to_number (buf, INSN_SIZE);
18228      if (((unsigned long) value) > 32
18229	  || (value == 32
18230	      && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
18231	{
18232	  as_bad_where (fixP->fx_file, fixP->fx_line,
18233			_("shift expression is too large"));
18234	  break;
18235	}
18236
18237      if (value == 0)
18238	/* Shifts of zero must be done as lsl.	*/
18239	newval &= ~0x60;
18240      else if (value == 32)
18241	value = 0;
18242      newval &= 0xfffff07f;
18243      newval |= (value & 0x1f) << 7;
18244      md_number_to_chars (buf, newval, INSN_SIZE);
18245      break;
18246
18247    case BFD_RELOC_ARM_T32_IMMEDIATE:
18248    case BFD_RELOC_ARM_T32_ADD_IMM:
18249    case BFD_RELOC_ARM_T32_IMM12:
18250    case BFD_RELOC_ARM_T32_ADD_PC12:
18251      /* We claim that this fixup has been processed here,
18252	 even if in fact we generate an error because we do
18253	 not have a reloc for it, so tc_gen_reloc will reject it.  */
18254      fixP->fx_done = 1;
18255
18256      if (fixP->fx_addsy
18257	  && ! S_IS_DEFINED (fixP->fx_addsy))
18258	{
18259	  as_bad_where (fixP->fx_file, fixP->fx_line,
18260			_("undefined symbol %s used as an immediate value"),
18261			S_GET_NAME (fixP->fx_addsy));
18262	  break;
18263	}
18264
18265      newval = md_chars_to_number (buf, THUMB_SIZE);
18266      newval <<= 16;
18267      newval |= md_chars_to_number (buf+2, THUMB_SIZE);
18268
18269      newimm = FAIL;
18270      if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
18271	  || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
18272	{
18273	  newimm = encode_thumb32_immediate (value);
18274	  if (newimm == (unsigned int) FAIL)
18275	    newimm = thumb32_negate_data_op (&newval, value);
18276	}
18277      if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
18278	  && newimm == (unsigned int) FAIL)
18279	{
18280	  /* Turn add/sum into addw/subw.  */
18281	  if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
18282	    newval = (newval & 0xfeffffff) | 0x02000000;
18283
18284	  /* 12 bit immediate for addw/subw.  */
18285	  if (value < 0)
18286	    {
18287	      value = -value;
18288	      newval ^= 0x00a00000;
18289	    }
18290	  if (value > 0xfff)
18291	    newimm = (unsigned int) FAIL;
18292	  else
18293	    newimm = value;
18294	}
18295
18296      if (newimm == (unsigned int)FAIL)
18297	{
18298	  as_bad_where (fixP->fx_file, fixP->fx_line,
18299			_("invalid constant (%lx) after fixup"),
18300			(unsigned long) value);
18301	  break;
18302	}
18303
18304      newval |= (newimm & 0x800) << 15;
18305      newval |= (newimm & 0x700) << 4;
18306      newval |= (newimm & 0x0ff);
18307
18308      md_number_to_chars (buf,   (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
18309      md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
18310      break;
18311
18312    case BFD_RELOC_ARM_SMC:
18313      if (((unsigned long) value) > 0xffff)
18314	as_bad_where (fixP->fx_file, fixP->fx_line,
18315		      _("invalid smc expression"));
18316      newval = md_chars_to_number (buf, INSN_SIZE);
18317      newval |= (value & 0xf) | ((value & 0xfff0) << 4);
18318      md_number_to_chars (buf, newval, INSN_SIZE);
18319      break;
18320
18321    case BFD_RELOC_ARM_SWI:
18322      if (fixP->tc_fix_data != 0)
18323	{
18324	  if (((unsigned long) value) > 0xff)
18325	    as_bad_where (fixP->fx_file, fixP->fx_line,
18326			  _("invalid swi expression"));
18327	  newval = md_chars_to_number (buf, THUMB_SIZE);
18328	  newval |= value;
18329	  md_number_to_chars (buf, newval, THUMB_SIZE);
18330	}
18331      else
18332	{
18333	  if (((unsigned long) value) > 0x00ffffff)
18334	    as_bad_where (fixP->fx_file, fixP->fx_line,
18335			  _("invalid swi expression"));
18336	  newval = md_chars_to_number (buf, INSN_SIZE);
18337	  newval |= value;
18338	  md_number_to_chars (buf, newval, INSN_SIZE);
18339	}
18340      break;
18341
18342    case BFD_RELOC_ARM_MULTI:
18343      if (((unsigned long) value) > 0xffff)
18344	as_bad_where (fixP->fx_file, fixP->fx_line,
18345		      _("invalid expression in load/store multiple"));
18346      newval = value | md_chars_to_number (buf, INSN_SIZE);
18347      md_number_to_chars (buf, newval, INSN_SIZE);
18348      break;
18349
18350#ifdef OBJ_ELF
18351    case BFD_RELOC_ARM_PCREL_CALL:
18352      newval = md_chars_to_number (buf, INSN_SIZE);
18353      if ((newval & 0xf0000000) == 0xf0000000)
18354	temp = 1;
18355      else
18356	temp = 3;
18357      goto arm_branch_common;
18358
18359    case BFD_RELOC_ARM_PCREL_JUMP:
18360    case BFD_RELOC_ARM_PLT32:
18361#endif
18362    case BFD_RELOC_ARM_PCREL_BRANCH:
18363      temp = 3;
18364      goto arm_branch_common;
18365
18366    case BFD_RELOC_ARM_PCREL_BLX:
18367      temp = 1;
18368    arm_branch_common:
18369      /* We are going to store value (shifted right by two) in the
18370	 instruction, in a 24 bit, signed field.  Bits 26 through 32 either
18371	 all clear or all set and bit 0 must be clear.  For B/BL bit 1 must
18372	 also be be clear.  */
18373      if (value & temp)
18374	as_bad_where (fixP->fx_file, fixP->fx_line,
18375		      _("misaligned branch destination"));
18376      if ((value & (offsetT)0xfe000000) != (offsetT)0
18377	  && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
18378	as_bad_where (fixP->fx_file, fixP->fx_line,
18379		      _("branch out of range"));
18380
18381      if (fixP->fx_done || !seg->use_rela_p)
18382	{
18383	  newval = md_chars_to_number (buf, INSN_SIZE);
18384	  newval |= (value >> 2) & 0x00ffffff;
18385	  /* Set the H bit on BLX instructions.  */
18386	  if (temp == 1)
18387	    {
18388	      if (value & 2)
18389		newval |= 0x01000000;
18390	      else
18391		newval &= ~0x01000000;
18392	    }
18393	  md_number_to_chars (buf, newval, INSN_SIZE);
18394	}
18395      break;
18396
18397    case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
18398      /* CBZ can only branch forward.  */
18399
18400      /* Attempts to use CBZ to branch to the next instruction
18401         (which, strictly speaking, are prohibited) will be turned into
18402         no-ops.
18403
18404	 FIXME: It may be better to remove the instruction completely and
18405	 perform relaxation.  */
18406      if (value == -2)
18407	{
18408	  newval = md_chars_to_number (buf, THUMB_SIZE);
18409	  newval = 0xbf00; /* NOP encoding T1 */
18410	  md_number_to_chars (buf, newval, THUMB_SIZE);
18411	}
18412      else
18413	{
18414	  if (value & ~0x7e)
18415	    as_bad_where (fixP->fx_file, fixP->fx_line,
18416		          _("branch out of range"));
18417
18418          if (fixP->fx_done || !seg->use_rela_p)
18419	    {
18420	      newval = md_chars_to_number (buf, THUMB_SIZE);
18421	      newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
18422	      md_number_to_chars (buf, newval, THUMB_SIZE);
18423	    }
18424	}
18425      break;
18426
18427    case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch.	*/
18428      if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
18429	as_bad_where (fixP->fx_file, fixP->fx_line,
18430		      _("branch out of range"));
18431
18432      if (fixP->fx_done || !seg->use_rela_p)
18433	{
18434	  newval = md_chars_to_number (buf, THUMB_SIZE);
18435	  newval |= (value & 0x1ff) >> 1;
18436	  md_number_to_chars (buf, newval, THUMB_SIZE);
18437	}
18438      break;
18439
18440    case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch.  */
18441      if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
18442	as_bad_where (fixP->fx_file, fixP->fx_line,
18443		      _("branch out of range"));
18444
18445      if (fixP->fx_done || !seg->use_rela_p)
18446	{
18447	  newval = md_chars_to_number (buf, THUMB_SIZE);
18448	  newval |= (value & 0xfff) >> 1;
18449	  md_number_to_chars (buf, newval, THUMB_SIZE);
18450	}
18451      break;
18452
18453    case BFD_RELOC_THUMB_PCREL_BRANCH20:
18454      if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
18455	as_bad_where (fixP->fx_file, fixP->fx_line,
18456		      _("conditional branch out of range"));
18457
18458      if (fixP->fx_done || !seg->use_rela_p)
18459	{
18460	  offsetT newval2;
18461	  addressT S, J1, J2, lo, hi;
18462
18463	  S  = (value & 0x00100000) >> 20;
18464	  J2 = (value & 0x00080000) >> 19;
18465	  J1 = (value & 0x00040000) >> 18;
18466	  hi = (value & 0x0003f000) >> 12;
18467	  lo = (value & 0x00000ffe) >> 1;
18468
18469	  newval   = md_chars_to_number (buf, THUMB_SIZE);
18470	  newval2  = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18471	  newval  |= (S << 10) | hi;
18472	  newval2 |= (J1 << 13) | (J2 << 11) | lo;
18473	  md_number_to_chars (buf, newval, THUMB_SIZE);
18474	  md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18475	}
18476      break;
18477
18478    case BFD_RELOC_THUMB_PCREL_BLX:
18479    case BFD_RELOC_THUMB_PCREL_BRANCH23:
18480      if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
18481	as_bad_where (fixP->fx_file, fixP->fx_line,
18482		      _("branch out of range"));
18483
18484      if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
18485	/* For a BLX instruction, make sure that the relocation is rounded up
18486	   to a word boundary.  This follows the semantics of the instruction
18487	   which specifies that bit 1 of the target address will come from bit
18488	   1 of the base address.  */
18489	value = (value + 1) & ~ 1;
18490
18491      if (fixP->fx_done || !seg->use_rela_p)
18492	{
18493	  offsetT newval2;
18494
18495	  newval   = md_chars_to_number (buf, THUMB_SIZE);
18496	  newval2  = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18497	  newval  |= (value & 0x7fffff) >> 12;
18498	  newval2 |= (value & 0xfff) >> 1;
18499	  md_number_to_chars (buf, newval, THUMB_SIZE);
18500	  md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18501	}
18502      break;
18503
18504    case BFD_RELOC_THUMB_PCREL_BRANCH25:
18505      if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
18506	as_bad_where (fixP->fx_file, fixP->fx_line,
18507		      _("branch out of range"));
18508
18509      if (fixP->fx_done || !seg->use_rela_p)
18510	{
18511	  offsetT newval2;
18512	  addressT S, I1, I2, lo, hi;
18513
18514	  S  = (value & 0x01000000) >> 24;
18515	  I1 = (value & 0x00800000) >> 23;
18516	  I2 = (value & 0x00400000) >> 22;
18517	  hi = (value & 0x003ff000) >> 12;
18518	  lo = (value & 0x00000ffe) >> 1;
18519
18520	  I1 = !(I1 ^ S);
18521	  I2 = !(I2 ^ S);
18522
18523	  newval   = md_chars_to_number (buf, THUMB_SIZE);
18524	  newval2  = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18525	  newval  |= (S << 10) | hi;
18526	  newval2 |= (I1 << 13) | (I2 << 11) | lo;
18527	  md_number_to_chars (buf, newval, THUMB_SIZE);
18528	  md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18529	}
18530      break;
18531
18532    case BFD_RELOC_8:
18533      if (fixP->fx_done || !seg->use_rela_p)
18534	md_number_to_chars (buf, value, 1);
18535      break;
18536
18537    case BFD_RELOC_16:
18538      if (fixP->fx_done || !seg->use_rela_p)
18539	md_number_to_chars (buf, value, 2);
18540      break;
18541
18542#ifdef OBJ_ELF
18543    case BFD_RELOC_ARM_TLS_GD32:
18544    case BFD_RELOC_ARM_TLS_LE32:
18545    case BFD_RELOC_ARM_TLS_IE32:
18546    case BFD_RELOC_ARM_TLS_LDM32:
18547    case BFD_RELOC_ARM_TLS_LDO32:
18548      S_SET_THREAD_LOCAL (fixP->fx_addsy);
18549      /* fall through */
18550
18551    case BFD_RELOC_ARM_GOT32:
18552    case BFD_RELOC_ARM_GOTOFF:
18553    case BFD_RELOC_ARM_TARGET2:
18554      if (fixP->fx_done || !seg->use_rela_p)
18555	md_number_to_chars (buf, 0, 4);
18556      break;
18557#endif
18558
18559    case BFD_RELOC_RVA:
18560    case BFD_RELOC_32:
18561    case BFD_RELOC_ARM_TARGET1:
18562    case BFD_RELOC_ARM_ROSEGREL32:
18563    case BFD_RELOC_ARM_SBREL32:
18564    case BFD_RELOC_32_PCREL:
18565#ifdef TE_PE
18566    case BFD_RELOC_32_SECREL:
18567#endif
18568      if (fixP->fx_done || !seg->use_rela_p)
18569#ifdef TE_WINCE
18570	/* For WinCE we only do this for pcrel fixups.  */
18571	if (fixP->fx_done || fixP->fx_pcrel)
18572#endif
18573	  md_number_to_chars (buf, value, 4);
18574      break;
18575
18576#ifdef OBJ_ELF
18577    case BFD_RELOC_ARM_PREL31:
18578      if (fixP->fx_done || !seg->use_rela_p)
18579	{
18580	  newval = md_chars_to_number (buf, 4) & 0x80000000;
18581	  if ((value ^ (value >> 1)) & 0x40000000)
18582	    {
18583	      as_bad_where (fixP->fx_file, fixP->fx_line,
18584			    _("rel31 relocation overflow"));
18585	    }
18586	  newval |= value & 0x7fffffff;
18587	  md_number_to_chars (buf, newval, 4);
18588	}
18589      break;
18590#endif
18591
18592    case BFD_RELOC_ARM_CP_OFF_IMM:
18593    case BFD_RELOC_ARM_T32_CP_OFF_IMM:
18594      if (value < -1023 || value > 1023 || (value & 3))
18595	as_bad_where (fixP->fx_file, fixP->fx_line,
18596		      _("co-processor offset out of range"));
18597    cp_off_common:
18598      sign = value >= 0;
18599      if (value < 0)
18600	value = -value;
18601      if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
18602	  || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
18603	newval = md_chars_to_number (buf, INSN_SIZE);
18604      else
18605	newval = get_thumb32_insn (buf);
18606      newval &= 0xff7fff00;
18607      newval |= (value >> 2) | (sign ? INDEX_UP : 0);
18608      if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
18609	  || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
18610	md_number_to_chars (buf, newval, INSN_SIZE);
18611      else
18612	put_thumb32_insn (buf, newval);
18613      break;
18614
18615    case BFD_RELOC_ARM_CP_OFF_IMM_S2:
18616    case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
18617      if (value < -255 || value > 255)
18618	as_bad_where (fixP->fx_file, fixP->fx_line,
18619		      _("co-processor offset out of range"));
18620      value *= 4;
18621      goto cp_off_common;
18622
18623    case BFD_RELOC_ARM_THUMB_OFFSET:
18624      newval = md_chars_to_number (buf, THUMB_SIZE);
18625      /* Exactly what ranges, and where the offset is inserted depends
18626	 on the type of instruction, we can establish this from the
18627	 top 4 bits.  */
18628      switch (newval >> 12)
18629	{
18630	case 4: /* PC load.  */
18631	  /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18632	     forced to zero for these loads; md_pcrel_from has already
18633	     compensated for this.  */
18634	  if (value & 3)
18635	    as_bad_where (fixP->fx_file, fixP->fx_line,
18636			  _("invalid offset, target not word aligned (0x%08lX)"),
18637			  (((unsigned long) fixP->fx_frag->fr_address
18638			    + (unsigned long) fixP->fx_where) & ~3)
18639			  + (unsigned long) value);
18640
18641	  if (value & ~0x3fc)
18642	    as_bad_where (fixP->fx_file, fixP->fx_line,
18643			  _("invalid offset, value too big (0x%08lX)"),
18644			  (long) value);
18645
18646	  newval |= value >> 2;
18647	  break;
18648
18649	case 9: /* SP load/store.  */
18650	  if (value & ~0x3fc)
18651	    as_bad_where (fixP->fx_file, fixP->fx_line,
18652			  _("invalid offset, value too big (0x%08lX)"),
18653			  (long) value);
18654	  newval |= value >> 2;
18655	  break;
18656
18657	case 6: /* Word load/store.  */
18658	  if (value & ~0x7c)
18659	    as_bad_where (fixP->fx_file, fixP->fx_line,
18660			  _("invalid offset, value too big (0x%08lX)"),
18661			  (long) value);
18662	  newval |= value << 4; /* 6 - 2.  */
18663	  break;
18664
18665	case 7: /* Byte load/store.  */
18666	  if (value & ~0x1f)
18667	    as_bad_where (fixP->fx_file, fixP->fx_line,
18668			  _("invalid offset, value too big (0x%08lX)"),
18669			  (long) value);
18670	  newval |= value << 6;
18671	  break;
18672
18673	case 8: /* Halfword load/store.	 */
18674	  if (value & ~0x3e)
18675	    as_bad_where (fixP->fx_file, fixP->fx_line,
18676			  _("invalid offset, value too big (0x%08lX)"),
18677			  (long) value);
18678	  newval |= value << 5; /* 6 - 1.  */
18679	  break;
18680
18681	default:
18682	  as_bad_where (fixP->fx_file, fixP->fx_line,
18683			"Unable to process relocation for thumb opcode: %lx",
18684			(unsigned long) newval);
18685	  break;
18686	}
18687      md_number_to_chars (buf, newval, THUMB_SIZE);
18688      break;
18689
18690    case BFD_RELOC_ARM_THUMB_ADD:
18691      /* This is a complicated relocation, since we use it for all of
18692	 the following immediate relocations:
18693
18694	    3bit ADD/SUB
18695	    8bit ADD/SUB
18696	    9bit ADD/SUB SP word-aligned
18697	   10bit ADD PC/SP word-aligned
18698
18699	 The type of instruction being processed is encoded in the
18700	 instruction field:
18701
18702	   0x8000  SUB
18703	   0x00F0  Rd
18704	   0x000F  Rs
18705      */
18706      newval = md_chars_to_number (buf, THUMB_SIZE);
18707      {
18708	int rd = (newval >> 4) & 0xf;
18709	int rs = newval & 0xf;
18710	int subtract = !!(newval & 0x8000);
18711
18712	/* Check for HI regs, only very restricted cases allowed:
18713	   Adjusting SP, and using PC or SP to get an address.	*/
18714	if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
18715	    || (rs > 7 && rs != REG_SP && rs != REG_PC))
18716	  as_bad_where (fixP->fx_file, fixP->fx_line,
18717			_("invalid Hi register with immediate"));
18718
18719	/* If value is negative, choose the opposite instruction.  */
18720	if (value < 0)
18721	  {
18722	    value = -value;
18723	    subtract = !subtract;
18724	    if (value < 0)
18725	      as_bad_where (fixP->fx_file, fixP->fx_line,
18726			    _("immediate value out of range"));
18727	  }
18728
18729	if (rd == REG_SP)
18730	  {
18731	    if (value & ~0x1fc)
18732	      as_bad_where (fixP->fx_file, fixP->fx_line,
18733			    _("invalid immediate for stack address calculation"));
18734	    newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
18735	    newval |= value >> 2;
18736	  }
18737	else if (rs == REG_PC || rs == REG_SP)
18738	  {
18739	    if (subtract || value & ~0x3fc)
18740	      as_bad_where (fixP->fx_file, fixP->fx_line,
18741			    _("invalid immediate for address calculation (value = 0x%08lX)"),
18742			    (unsigned long) value);
18743	    newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
18744	    newval |= rd << 8;
18745	    newval |= value >> 2;
18746	  }
18747	else if (rs == rd)
18748	  {
18749	    if (value & ~0xff)
18750	      as_bad_where (fixP->fx_file, fixP->fx_line,
18751			    _("immediate value out of range"));
18752	    newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
18753	    newval |= (rd << 8) | value;
18754	  }
18755	else
18756	  {
18757	    if (value & ~0x7)
18758	      as_bad_where (fixP->fx_file, fixP->fx_line,
18759			    _("immediate value out of range"));
18760	    newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
18761	    newval |= rd | (rs << 3) | (value << 6);
18762	  }
18763      }
18764      md_number_to_chars (buf, newval, THUMB_SIZE);
18765      break;
18766
18767    case BFD_RELOC_ARM_THUMB_IMM:
18768      newval = md_chars_to_number (buf, THUMB_SIZE);
18769      if (value < 0 || value > 255)
18770	as_bad_where (fixP->fx_file, fixP->fx_line,
18771		      _("invalid immediate: %ld is too large"),
18772		      (long) value);
18773      newval |= value;
18774      md_number_to_chars (buf, newval, THUMB_SIZE);
18775      break;
18776
18777    case BFD_RELOC_ARM_THUMB_SHIFT:
18778      /* 5bit shift value (0..32).  LSL cannot take 32.	 */
18779      newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
18780      temp = newval & 0xf800;
18781      if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
18782	as_bad_where (fixP->fx_file, fixP->fx_line,
18783		      _("invalid shift value: %ld"), (long) value);
18784      /* Shifts of zero must be encoded as LSL.	 */
18785      if (value == 0)
18786	newval = (newval & 0x003f) | T_OPCODE_LSL_I;
18787      /* Shifts of 32 are encoded as zero.  */
18788      else if (value == 32)
18789	value = 0;
18790      newval |= value << 6;
18791      md_number_to_chars (buf, newval, THUMB_SIZE);
18792      break;
18793
18794    case BFD_RELOC_VTABLE_INHERIT:
18795    case BFD_RELOC_VTABLE_ENTRY:
18796      fixP->fx_done = 0;
18797      return;
18798
18799    case BFD_RELOC_ARM_MOVW:
18800    case BFD_RELOC_ARM_MOVT:
18801    case BFD_RELOC_ARM_THUMB_MOVW:
18802    case BFD_RELOC_ARM_THUMB_MOVT:
18803      if (fixP->fx_done || !seg->use_rela_p)
18804	{
18805	  /* REL format relocations are limited to a 16-bit addend.  */
18806	  if (!fixP->fx_done)
18807	    {
18808	      if (value < -0x1000 || value > 0xffff)
18809		  as_bad_where (fixP->fx_file, fixP->fx_line,
18810				_("offset too big"));
18811	    }
18812	  else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
18813		   || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
18814	    {
18815	      value >>= 16;
18816	    }
18817
18818	  if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
18819	      || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
18820	    {
18821	      newval = get_thumb32_insn (buf);
18822	      newval &= 0xfbf08f00;
18823	      newval |= (value & 0xf000) << 4;
18824	      newval |= (value & 0x0800) << 15;
18825	      newval |= (value & 0x0700) << 4;
18826	      newval |= (value & 0x00ff);
18827	      put_thumb32_insn (buf, newval);
18828	    }
18829	  else
18830	    {
18831	      newval = md_chars_to_number (buf, 4);
18832	      newval &= 0xfff0f000;
18833	      newval |= value & 0x0fff;
18834	      newval |= (value & 0xf000) << 4;
18835	      md_number_to_chars (buf, newval, 4);
18836	    }
18837	}
18838      return;
18839
18840   case BFD_RELOC_ARM_ALU_PC_G0_NC:
18841   case BFD_RELOC_ARM_ALU_PC_G0:
18842   case BFD_RELOC_ARM_ALU_PC_G1_NC:
18843   case BFD_RELOC_ARM_ALU_PC_G1:
18844   case BFD_RELOC_ARM_ALU_PC_G2:
18845   case BFD_RELOC_ARM_ALU_SB_G0_NC:
18846   case BFD_RELOC_ARM_ALU_SB_G0:
18847   case BFD_RELOC_ARM_ALU_SB_G1_NC:
18848   case BFD_RELOC_ARM_ALU_SB_G1:
18849   case BFD_RELOC_ARM_ALU_SB_G2:
18850     assert (!fixP->fx_done);
18851     if (!seg->use_rela_p)
18852       {
18853         bfd_vma insn;
18854         bfd_vma encoded_addend;
18855         bfd_vma addend_abs = abs (value);
18856
18857         /* Check that the absolute value of the addend can be
18858            expressed as an 8-bit constant plus a rotation.  */
18859         encoded_addend = encode_arm_immediate (addend_abs);
18860         if (encoded_addend == (unsigned int) FAIL)
18861	   as_bad_where (fixP->fx_file, fixP->fx_line,
18862	                 _("the offset 0x%08lX is not representable"),
18863                         (unsigned long) addend_abs);
18864
18865         /* Extract the instruction.  */
18866         insn = md_chars_to_number (buf, INSN_SIZE);
18867
18868         /* If the addend is positive, use an ADD instruction.
18869            Otherwise use a SUB.  Take care not to destroy the S bit.  */
18870         insn &= 0xff1fffff;
18871         if (value < 0)
18872           insn |= 1 << 22;
18873         else
18874           insn |= 1 << 23;
18875
18876         /* Place the encoded addend into the first 12 bits of the
18877            instruction.  */
18878         insn &= 0xfffff000;
18879         insn |= encoded_addend;
18880
18881         /* Update the instruction.  */
18882         md_number_to_chars (buf, insn, INSN_SIZE);
18883       }
18884     break;
18885
18886    case BFD_RELOC_ARM_LDR_PC_G0:
18887    case BFD_RELOC_ARM_LDR_PC_G1:
18888    case BFD_RELOC_ARM_LDR_PC_G2:
18889    case BFD_RELOC_ARM_LDR_SB_G0:
18890    case BFD_RELOC_ARM_LDR_SB_G1:
18891    case BFD_RELOC_ARM_LDR_SB_G2:
18892      assert (!fixP->fx_done);
18893      if (!seg->use_rela_p)
18894        {
18895          bfd_vma insn;
18896          bfd_vma addend_abs = abs (value);
18897
18898          /* Check that the absolute value of the addend can be
18899             encoded in 12 bits.  */
18900          if (addend_abs >= 0x1000)
18901	    as_bad_where (fixP->fx_file, fixP->fx_line,
18902	  	          _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18903                          (unsigned long) addend_abs);
18904
18905          /* Extract the instruction.  */
18906          insn = md_chars_to_number (buf, INSN_SIZE);
18907
18908          /* If the addend is negative, clear bit 23 of the instruction.
18909             Otherwise set it.  */
18910          if (value < 0)
18911            insn &= ~(1 << 23);
18912          else
18913            insn |= 1 << 23;
18914
18915          /* Place the absolute value of the addend into the first 12 bits
18916             of the instruction.  */
18917          insn &= 0xfffff000;
18918          insn |= addend_abs;
18919
18920          /* Update the instruction.  */
18921          md_number_to_chars (buf, insn, INSN_SIZE);
18922        }
18923      break;
18924
18925    case BFD_RELOC_ARM_LDRS_PC_G0:
18926    case BFD_RELOC_ARM_LDRS_PC_G1:
18927    case BFD_RELOC_ARM_LDRS_PC_G2:
18928    case BFD_RELOC_ARM_LDRS_SB_G0:
18929    case BFD_RELOC_ARM_LDRS_SB_G1:
18930    case BFD_RELOC_ARM_LDRS_SB_G2:
18931      assert (!fixP->fx_done);
18932      if (!seg->use_rela_p)
18933        {
18934          bfd_vma insn;
18935          bfd_vma addend_abs = abs (value);
18936
18937          /* Check that the absolute value of the addend can be
18938             encoded in 8 bits.  */
18939          if (addend_abs >= 0x100)
18940	    as_bad_where (fixP->fx_file, fixP->fx_line,
18941	  	          _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18942                          (unsigned long) addend_abs);
18943
18944          /* Extract the instruction.  */
18945          insn = md_chars_to_number (buf, INSN_SIZE);
18946
18947          /* If the addend is negative, clear bit 23 of the instruction.
18948             Otherwise set it.  */
18949          if (value < 0)
18950            insn &= ~(1 << 23);
18951          else
18952            insn |= 1 << 23;
18953
18954          /* Place the first four bits of the absolute value of the addend
18955             into the first 4 bits of the instruction, and the remaining
18956             four into bits 8 .. 11.  */
18957          insn &= 0xfffff0f0;
18958          insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
18959
18960          /* Update the instruction.  */
18961          md_number_to_chars (buf, insn, INSN_SIZE);
18962        }
18963      break;
18964
18965    case BFD_RELOC_ARM_LDC_PC_G0:
18966    case BFD_RELOC_ARM_LDC_PC_G1:
18967    case BFD_RELOC_ARM_LDC_PC_G2:
18968    case BFD_RELOC_ARM_LDC_SB_G0:
18969    case BFD_RELOC_ARM_LDC_SB_G1:
18970    case BFD_RELOC_ARM_LDC_SB_G2:
18971      assert (!fixP->fx_done);
18972      if (!seg->use_rela_p)
18973        {
18974          bfd_vma insn;
18975          bfd_vma addend_abs = abs (value);
18976
18977          /* Check that the absolute value of the addend is a multiple of
18978             four and, when divided by four, fits in 8 bits.  */
18979          if (addend_abs & 0x3)
18980	    as_bad_where (fixP->fx_file, fixP->fx_line,
18981	  	          _("bad offset 0x%08lX (must be word-aligned)"),
18982                          (unsigned long) addend_abs);
18983
18984          if ((addend_abs >> 2) > 0xff)
18985	    as_bad_where (fixP->fx_file, fixP->fx_line,
18986	  	          _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18987                          (unsigned long) addend_abs);
18988
18989          /* Extract the instruction.  */
18990          insn = md_chars_to_number (buf, INSN_SIZE);
18991
18992          /* If the addend is negative, clear bit 23 of the instruction.
18993             Otherwise set it.  */
18994          if (value < 0)
18995            insn &= ~(1 << 23);
18996          else
18997            insn |= 1 << 23;
18998
18999          /* Place the addend (divided by four) into the first eight
19000             bits of the instruction.  */
19001          insn &= 0xfffffff0;
19002          insn |= addend_abs >> 2;
19003
19004          /* Update the instruction.  */
19005          md_number_to_chars (buf, insn, INSN_SIZE);
19006        }
19007      break;
19008
19009    case BFD_RELOC_UNUSED:
19010    default:
19011      as_bad_where (fixP->fx_file, fixP->fx_line,
19012		    _("bad relocation fixup type (%d)"), fixP->fx_r_type);
19013    }
19014}
19015
19016/* Translate internal representation of relocation info to BFD target
19017   format.  */
19018
19019arelent *
19020tc_gen_reloc (asection *section, fixS *fixp)
19021{
19022  arelent * reloc;
19023  bfd_reloc_code_real_type code;
19024
19025  reloc = xmalloc (sizeof (arelent));
19026
19027  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
19028  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
19029  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
19030
19031  if (fixp->fx_pcrel)
19032    {
19033      if (section->use_rela_p)
19034	fixp->fx_offset -= md_pcrel_from_section (fixp, section);
19035      else
19036	fixp->fx_offset = reloc->address;
19037    }
19038  reloc->addend = fixp->fx_offset;
19039
19040  switch (fixp->fx_r_type)
19041    {
19042    case BFD_RELOC_8:
19043      if (fixp->fx_pcrel)
19044	{
19045	  code = BFD_RELOC_8_PCREL;
19046	  break;
19047	}
19048
19049    case BFD_RELOC_16:
19050      if (fixp->fx_pcrel)
19051	{
19052	  code = BFD_RELOC_16_PCREL;
19053	  break;
19054	}
19055
19056    case BFD_RELOC_32:
19057      if (fixp->fx_pcrel)
19058	{
19059	  code = BFD_RELOC_32_PCREL;
19060	  break;
19061	}
19062
19063    case BFD_RELOC_ARM_MOVW:
19064      if (fixp->fx_pcrel)
19065	{
19066	  code = BFD_RELOC_ARM_MOVW_PCREL;
19067	  break;
19068	}
19069
19070    case BFD_RELOC_ARM_MOVT:
19071      if (fixp->fx_pcrel)
19072	{
19073	  code = BFD_RELOC_ARM_MOVT_PCREL;
19074	  break;
19075	}
19076
19077    case BFD_RELOC_ARM_THUMB_MOVW:
19078      if (fixp->fx_pcrel)
19079	{
19080	  code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
19081	  break;
19082	}
19083
19084    case BFD_RELOC_ARM_THUMB_MOVT:
19085      if (fixp->fx_pcrel)
19086	{
19087	  code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
19088	  break;
19089	}
19090
19091    case BFD_RELOC_NONE:
19092    case BFD_RELOC_ARM_PCREL_BRANCH:
19093    case BFD_RELOC_ARM_PCREL_BLX:
19094    case BFD_RELOC_RVA:
19095    case BFD_RELOC_THUMB_PCREL_BRANCH7:
19096    case BFD_RELOC_THUMB_PCREL_BRANCH9:
19097    case BFD_RELOC_THUMB_PCREL_BRANCH12:
19098    case BFD_RELOC_THUMB_PCREL_BRANCH20:
19099    case BFD_RELOC_THUMB_PCREL_BRANCH23:
19100    case BFD_RELOC_THUMB_PCREL_BRANCH25:
19101    case BFD_RELOC_THUMB_PCREL_BLX:
19102    case BFD_RELOC_VTABLE_ENTRY:
19103    case BFD_RELOC_VTABLE_INHERIT:
19104#ifdef TE_PE
19105    case BFD_RELOC_32_SECREL:
19106#endif
19107      code = fixp->fx_r_type;
19108      break;
19109
19110    case BFD_RELOC_ARM_LITERAL:
19111    case BFD_RELOC_ARM_HWLITERAL:
19112      /* If this is called then the a literal has
19113	 been referenced across a section boundary.  */
19114      as_bad_where (fixp->fx_file, fixp->fx_line,
19115		    _("literal referenced across section boundary"));
19116      return NULL;
19117
19118#ifdef OBJ_ELF
19119    case BFD_RELOC_ARM_GOT32:
19120    case BFD_RELOC_ARM_GOTOFF:
19121    case BFD_RELOC_ARM_PLT32:
19122    case BFD_RELOC_ARM_TARGET1:
19123    case BFD_RELOC_ARM_ROSEGREL32:
19124    case BFD_RELOC_ARM_SBREL32:
19125    case BFD_RELOC_ARM_PREL31:
19126    case BFD_RELOC_ARM_TARGET2:
19127    case BFD_RELOC_ARM_TLS_LE32:
19128    case BFD_RELOC_ARM_TLS_LDO32:
19129    case BFD_RELOC_ARM_PCREL_CALL:
19130    case BFD_RELOC_ARM_PCREL_JUMP:
19131    case BFD_RELOC_ARM_ALU_PC_G0_NC:
19132    case BFD_RELOC_ARM_ALU_PC_G0:
19133    case BFD_RELOC_ARM_ALU_PC_G1_NC:
19134    case BFD_RELOC_ARM_ALU_PC_G1:
19135    case BFD_RELOC_ARM_ALU_PC_G2:
19136    case BFD_RELOC_ARM_LDR_PC_G0:
19137    case BFD_RELOC_ARM_LDR_PC_G1:
19138    case BFD_RELOC_ARM_LDR_PC_G2:
19139    case BFD_RELOC_ARM_LDRS_PC_G0:
19140    case BFD_RELOC_ARM_LDRS_PC_G1:
19141    case BFD_RELOC_ARM_LDRS_PC_G2:
19142    case BFD_RELOC_ARM_LDC_PC_G0:
19143    case BFD_RELOC_ARM_LDC_PC_G1:
19144    case BFD_RELOC_ARM_LDC_PC_G2:
19145    case BFD_RELOC_ARM_ALU_SB_G0_NC:
19146    case BFD_RELOC_ARM_ALU_SB_G0:
19147    case BFD_RELOC_ARM_ALU_SB_G1_NC:
19148    case BFD_RELOC_ARM_ALU_SB_G1:
19149    case BFD_RELOC_ARM_ALU_SB_G2:
19150    case BFD_RELOC_ARM_LDR_SB_G0:
19151    case BFD_RELOC_ARM_LDR_SB_G1:
19152    case BFD_RELOC_ARM_LDR_SB_G2:
19153    case BFD_RELOC_ARM_LDRS_SB_G0:
19154    case BFD_RELOC_ARM_LDRS_SB_G1:
19155    case BFD_RELOC_ARM_LDRS_SB_G2:
19156    case BFD_RELOC_ARM_LDC_SB_G0:
19157    case BFD_RELOC_ARM_LDC_SB_G1:
19158    case BFD_RELOC_ARM_LDC_SB_G2:
19159      code = fixp->fx_r_type;
19160      break;
19161
19162    case BFD_RELOC_ARM_TLS_GD32:
19163    case BFD_RELOC_ARM_TLS_IE32:
19164    case BFD_RELOC_ARM_TLS_LDM32:
19165      /* BFD will include the symbol's address in the addend.
19166	 But we don't want that, so subtract it out again here.  */
19167      if (!S_IS_COMMON (fixp->fx_addsy))
19168	reloc->addend -= (*reloc->sym_ptr_ptr)->value;
19169      code = fixp->fx_r_type;
19170      break;
19171#endif
19172
19173    case BFD_RELOC_ARM_IMMEDIATE:
19174      as_bad_where (fixp->fx_file, fixp->fx_line,
19175		    _("internal relocation (type: IMMEDIATE) not fixed up"));
19176      return NULL;
19177
19178    case BFD_RELOC_ARM_ADRL_IMMEDIATE:
19179      as_bad_where (fixp->fx_file, fixp->fx_line,
19180		    _("ADRL used for a symbol not defined in the same file"));
19181      return NULL;
19182
19183    case BFD_RELOC_ARM_OFFSET_IMM:
19184      if (section->use_rela_p)
19185	{
19186	  code = fixp->fx_r_type;
19187	  break;
19188	}
19189
19190      if (fixp->fx_addsy != NULL
19191	  && !S_IS_DEFINED (fixp->fx_addsy)
19192	  && S_IS_LOCAL (fixp->fx_addsy))
19193	{
19194	  as_bad_where (fixp->fx_file, fixp->fx_line,
19195			_("undefined local label `%s'"),
19196			S_GET_NAME (fixp->fx_addsy));
19197	  return NULL;
19198	}
19199
19200      as_bad_where (fixp->fx_file, fixp->fx_line,
19201		    _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19202      return NULL;
19203
19204    default:
19205      {
19206	char * type;
19207
19208	switch (fixp->fx_r_type)
19209	  {
19210	  case BFD_RELOC_NONE:		   type = "NONE";	  break;
19211	  case BFD_RELOC_ARM_OFFSET_IMM8:  type = "OFFSET_IMM8";  break;
19212	  case BFD_RELOC_ARM_SHIFT_IMM:	   type = "SHIFT_IMM";	  break;
19213	  case BFD_RELOC_ARM_SMC:	   type = "SMC";	  break;
19214	  case BFD_RELOC_ARM_SWI:	   type = "SWI";	  break;
19215	  case BFD_RELOC_ARM_MULTI:	   type = "MULTI";	  break;
19216	  case BFD_RELOC_ARM_CP_OFF_IMM:   type = "CP_OFF_IMM";	  break;
19217	  case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
19218	  case BFD_RELOC_ARM_THUMB_ADD:	   type = "THUMB_ADD";	  break;
19219	  case BFD_RELOC_ARM_THUMB_SHIFT:  type = "THUMB_SHIFT";  break;
19220	  case BFD_RELOC_ARM_THUMB_IMM:	   type = "THUMB_IMM";	  break;
19221	  case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
19222	  default:			   type = _("<unknown>"); break;
19223	  }
19224	as_bad_where (fixp->fx_file, fixp->fx_line,
19225		      _("cannot represent %s relocation in this object file format"),
19226		      type);
19227	return NULL;
19228      }
19229    }
19230
19231#ifdef OBJ_ELF
19232  if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
19233      && GOT_symbol
19234      && fixp->fx_addsy == GOT_symbol)
19235    {
19236      code = BFD_RELOC_ARM_GOTPC;
19237      reloc->addend = fixp->fx_offset = reloc->address;
19238    }
19239#endif
19240
19241  reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
19242
19243  if (reloc->howto == NULL)
19244    {
19245      as_bad_where (fixp->fx_file, fixp->fx_line,
19246		    _("cannot represent %s relocation in this object file format"),
19247		    bfd_get_reloc_code_name (code));
19248      return NULL;
19249    }
19250
19251  /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19252     vtable entry to be used in the relocation's section offset.  */
19253  if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
19254    reloc->address = fixp->fx_offset;
19255
19256  return reloc;
19257}
19258
19259/* This fix_new is called by cons via TC_CONS_FIX_NEW.	*/
19260
19261void
19262cons_fix_new_arm (fragS *	frag,
19263		  int		where,
19264		  int		size,
19265		  expressionS * exp)
19266{
19267  bfd_reloc_code_real_type type;
19268  int pcrel = 0;
19269
19270  /* Pick a reloc.
19271     FIXME: @@ Should look at CPU word size.  */
19272  switch (size)
19273    {
19274    case 1:
19275      type = BFD_RELOC_8;
19276      break;
19277    case 2:
19278      type = BFD_RELOC_16;
19279      break;
19280    case 4:
19281    default:
19282      type = BFD_RELOC_32;
19283      break;
19284    case 8:
19285      type = BFD_RELOC_64;
19286      break;
19287    }
19288
19289#ifdef TE_PE
19290  if (exp->X_op == O_secrel)
19291  {
19292    exp->X_op = O_symbol;
19293    type = BFD_RELOC_32_SECREL;
19294  }
19295#endif
19296
19297  fix_new_exp (frag, where, (int) size, exp, pcrel, type);
19298}
19299
19300#if defined OBJ_COFF || defined OBJ_ELF
19301void
19302arm_validate_fix (fixS * fixP)
19303{
19304  /* If the destination of the branch is a defined symbol which does not have
19305     the THUMB_FUNC attribute, then we must be calling a function which has
19306     the (interfacearm) attribute.  We look for the Thumb entry point to that
19307     function and change the branch to refer to that function instead.	*/
19308  if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
19309      && fixP->fx_addsy != NULL
19310      && S_IS_DEFINED (fixP->fx_addsy)
19311      && ! THUMB_IS_FUNC (fixP->fx_addsy))
19312    {
19313      fixP->fx_addsy = find_real_start (fixP->fx_addsy);
19314    }
19315}
19316#endif
19317
19318int
19319arm_force_relocation (struct fix * fixp)
19320{
19321#if defined (OBJ_COFF) && defined (TE_PE)
19322  if (fixp->fx_r_type == BFD_RELOC_RVA)
19323    return 1;
19324#endif
19325
19326  /* Resolve these relocations even if the symbol is extern or weak.  */
19327  if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
19328      || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
19329      || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
19330      || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
19331      || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
19332      || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
19333      || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
19334    return 0;
19335
19336  /* Always leave these relocations for the linker.  */
19337  if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
19338       && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
19339      || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
19340    return 1;
19341
19342  /* Always generate relocations against function symbols.  */
19343  if (fixp->fx_r_type == BFD_RELOC_32
19344      && fixp->fx_addsy
19345      && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
19346    return 1;
19347
19348  return generic_force_reloc (fixp);
19349}
19350
19351#if defined (OBJ_ELF) || defined (OBJ_COFF)
19352/* Relocations against function names must be left unadjusted,
19353   so that the linker can use this information to generate interworking
19354   stubs.  The MIPS version of this function
19355   also prevents relocations that are mips-16 specific, but I do not
19356   know why it does this.
19357
19358   FIXME:
19359   There is one other problem that ought to be addressed here, but
19360   which currently is not:  Taking the address of a label (rather
19361   than a function) and then later jumping to that address.  Such
19362   addresses also ought to have their bottom bit set (assuming that
19363   they reside in Thumb code), but at the moment they will not.	 */
19364
19365bfd_boolean
19366arm_fix_adjustable (fixS * fixP)
19367{
19368  if (fixP->fx_addsy == NULL)
19369    return 1;
19370
19371  /* Preserve relocations against symbols with function type.  */
19372  if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
19373    return 0;
19374
19375  if (THUMB_IS_FUNC (fixP->fx_addsy)
19376      && fixP->fx_subsy == NULL)
19377    return 0;
19378
19379  /* We need the symbol name for the VTABLE entries.  */
19380  if (	 fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
19381      || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
19382    return 0;
19383
19384  /* Don't allow symbols to be discarded on GOT related relocs.	 */
19385  if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
19386      || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
19387      || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
19388      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
19389      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
19390      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
19391      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
19392      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
19393      || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
19394    return 0;
19395
19396  /* Similarly for group relocations.  */
19397  if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
19398       && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
19399      || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
19400    return 0;
19401
19402  if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
19403      || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
19404      || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
19405      || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
19406    return 0;
19407
19408  return 1;
19409}
19410#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19411
19412#ifdef OBJ_ELF
19413
19414const char *
19415elf32_arm_target_format (void)
19416{
19417#ifdef TE_SYMBIAN
19418  return (target_big_endian
19419	  ? "elf32-bigarm-symbian"
19420	  : "elf32-littlearm-symbian");
19421#elif defined (TE_VXWORKS)
19422  return (target_big_endian
19423	  ? "elf32-bigarm-vxworks"
19424	  : "elf32-littlearm-vxworks");
19425#else
19426  if (target_big_endian)
19427    return "elf32-bigarm";
19428  else
19429    return "elf32-littlearm";
19430#endif
19431}
19432
19433void
19434armelf_frob_symbol (symbolS * symp,
19435		    int *     puntp)
19436{
19437  elf_frob_symbol (symp, puntp);
19438}
19439#endif
19440
19441/* MD interface: Finalization.	*/
19442
19443/* A good place to do this, although this was probably not intended
19444   for this kind of use.  We need to dump the literal pool before
19445   references are made to a null symbol pointer.  */
19446
19447void
19448arm_cleanup (void)
19449{
19450  literal_pool * pool;
19451
19452  for (pool = list_of_pools; pool; pool = pool->next)
19453    {
19454      /* Put it at the end of the relevent section.  */
19455      subseg_set (pool->section, pool->sub_section);
19456#ifdef OBJ_ELF
19457      arm_elf_change_section ();
19458#endif
19459      s_ltorg (0);
19460    }
19461}
19462
19463/* Adjust the symbol table.  This marks Thumb symbols as distinct from
19464   ARM ones.  */
19465
19466void
19467arm_adjust_symtab (void)
19468{
19469#ifdef OBJ_COFF
19470  symbolS * sym;
19471
19472  for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
19473    {
19474      if (ARM_IS_THUMB (sym))
19475	{
19476	  if (THUMB_IS_FUNC (sym))
19477	    {
19478	      /* Mark the symbol as a Thumb function.  */
19479	      if (   S_GET_STORAGE_CLASS (sym) == C_STAT
19480		  || S_GET_STORAGE_CLASS (sym) == C_LABEL)  /* This can happen!	 */
19481		S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
19482
19483	      else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
19484		S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
19485	      else
19486		as_bad (_("%s: unexpected function type: %d"),
19487			S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
19488	    }
19489	  else switch (S_GET_STORAGE_CLASS (sym))
19490	    {
19491	    case C_EXT:
19492	      S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
19493	      break;
19494	    case C_STAT:
19495	      S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
19496	      break;
19497	    case C_LABEL:
19498	      S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
19499	      break;
19500	    default:
19501	      /* Do nothing.  */
19502	      break;
19503	    }
19504	}
19505
19506      if (ARM_IS_INTERWORK (sym))
19507	coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
19508    }
19509#endif
19510#ifdef OBJ_ELF
19511  symbolS * sym;
19512  char	    bind;
19513
19514  for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
19515    {
19516      if (ARM_IS_THUMB (sym))
19517	{
19518	  elf_symbol_type * elf_sym;
19519
19520	  elf_sym = elf_symbol (symbol_get_bfdsym (sym));
19521	  bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
19522
19523	  if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
19524		BFD_ARM_SPECIAL_SYM_TYPE_ANY))
19525	    {
19526	      /* If it's a .thumb_func, declare it as so,
19527		 otherwise tag label as .code 16.  */
19528	      if (THUMB_IS_FUNC (sym))
19529		elf_sym->internal_elf_sym.st_info =
19530		  ELF_ST_INFO (bind, STT_ARM_TFUNC);
19531	      else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
19532		elf_sym->internal_elf_sym.st_info =
19533		  ELF_ST_INFO (bind, STT_ARM_16BIT);
19534	    }
19535	}
19536    }
19537#endif
19538}
19539
19540/* MD interface: Initialization.  */
19541
19542static void
19543set_constant_flonums (void)
19544{
19545  int i;
19546
19547  for (i = 0; i < NUM_FLOAT_VALS; i++)
19548    if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
19549      abort ();
19550}
19551
19552/* Auto-select Thumb mode if it's the only available instruction set for the
19553   given architecture.  */
19554
19555static void
19556autoselect_thumb_from_cpu_variant (void)
19557{
19558  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
19559    opcode_select (16);
19560}
19561
19562void
19563md_begin (void)
19564{
19565  unsigned mach;
19566  unsigned int i;
19567
19568  if (	 (arm_ops_hsh = hash_new ()) == NULL
19569      || (arm_cond_hsh = hash_new ()) == NULL
19570      || (arm_shift_hsh = hash_new ()) == NULL
19571      || (arm_psr_hsh = hash_new ()) == NULL
19572      || (arm_v7m_psr_hsh = hash_new ()) == NULL
19573      || (arm_reg_hsh = hash_new ()) == NULL
19574      || (arm_reloc_hsh = hash_new ()) == NULL
19575      || (arm_barrier_opt_hsh = hash_new ()) == NULL)
19576    as_fatal (_("virtual memory exhausted"));
19577
19578  for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
19579    hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
19580  for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
19581    hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
19582  for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
19583    hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
19584  for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
19585    hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
19586  for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
19587    hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i));
19588  for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
19589    hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
19590  for (i = 0;
19591       i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
19592       i++)
19593    hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template,
19594		 (PTR) (barrier_opt_names + i));
19595#ifdef OBJ_ELF
19596  for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
19597    hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
19598#endif
19599
19600  set_constant_flonums ();
19601
19602  /* Set the cpu variant based on the command-line options.  We prefer
19603     -mcpu= over -march= if both are set (as for GCC); and we prefer
19604     -mfpu= over any other way of setting the floating point unit.
19605     Use of legacy options with new options are faulted.  */
19606  if (legacy_cpu)
19607    {
19608      if (mcpu_cpu_opt || march_cpu_opt)
19609	as_bad (_("use of old and new-style options to set CPU type"));
19610
19611      mcpu_cpu_opt = legacy_cpu;
19612    }
19613  else if (!mcpu_cpu_opt)
19614    mcpu_cpu_opt = march_cpu_opt;
19615
19616  if (legacy_fpu)
19617    {
19618      if (mfpu_opt)
19619	as_bad (_("use of old and new-style options to set FPU type"));
19620
19621      mfpu_opt = legacy_fpu;
19622    }
19623  else if (!mfpu_opt)
19624    {
19625#if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19626      /* Some environments specify a default FPU.  If they don't, infer it
19627	 from the processor.  */
19628      if (mcpu_fpu_opt)
19629	mfpu_opt = mcpu_fpu_opt;
19630      else
19631	mfpu_opt = march_fpu_opt;
19632#else
19633      mfpu_opt = &fpu_default;
19634#endif
19635    }
19636
19637  if (!mfpu_opt)
19638    {
19639      if (mcpu_cpu_opt != NULL)
19640	mfpu_opt = &fpu_default;
19641      else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
19642	mfpu_opt = &fpu_arch_vfp_v2;
19643      else
19644	mfpu_opt = &fpu_arch_fpa;
19645    }
19646
19647#ifdef CPU_DEFAULT
19648  if (!mcpu_cpu_opt)
19649    {
19650      mcpu_cpu_opt = &cpu_default;
19651      selected_cpu = cpu_default;
19652    }
19653#else
19654  if (mcpu_cpu_opt)
19655    selected_cpu = *mcpu_cpu_opt;
19656  else
19657    mcpu_cpu_opt = &arm_arch_any;
19658#endif
19659
19660  ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
19661
19662  autoselect_thumb_from_cpu_variant ();
19663
19664  arm_arch_used = thumb_arch_used = arm_arch_none;
19665
19666#if defined OBJ_COFF || defined OBJ_ELF
19667  {
19668    unsigned int flags = 0;
19669
19670#if defined OBJ_ELF
19671    flags = meabi_flags;
19672
19673    switch (meabi_flags)
19674      {
19675      case EF_ARM_EABI_UNKNOWN:
19676#endif
19677	/* Set the flags in the private structure.  */
19678	if (uses_apcs_26)      flags |= F_APCS26;
19679	if (support_interwork) flags |= F_INTERWORK;
19680	if (uses_apcs_float)   flags |= F_APCS_FLOAT;
19681	if (pic_code)	       flags |= F_PIC;
19682	if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
19683	  flags |= F_SOFT_FLOAT;
19684
19685	switch (mfloat_abi_opt)
19686	  {
19687	  case ARM_FLOAT_ABI_SOFT:
19688	  case ARM_FLOAT_ABI_SOFTFP:
19689	    flags |= F_SOFT_FLOAT;
19690	    break;
19691
19692	  case ARM_FLOAT_ABI_HARD:
19693	    if (flags & F_SOFT_FLOAT)
19694	      as_bad (_("hard-float conflicts with specified fpu"));
19695	    break;
19696	  }
19697
19698	/* Using pure-endian doubles (even if soft-float).	*/
19699	if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
19700	  flags |= F_VFP_FLOAT;
19701
19702#if defined OBJ_ELF
19703	if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
19704	    flags |= EF_ARM_MAVERICK_FLOAT;
19705	break;
19706
19707      case EF_ARM_EABI_VER4:
19708      case EF_ARM_EABI_VER5:
19709	/* No additional flags to set.	*/
19710	break;
19711
19712      default:
19713	abort ();
19714      }
19715#endif
19716    bfd_set_private_flags (stdoutput, flags);
19717
19718    /* We have run out flags in the COFF header to encode the
19719       status of ATPCS support, so instead we create a dummy,
19720       empty, debug section called .arm.atpcs.	*/
19721    if (atpcs)
19722      {
19723	asection * sec;
19724
19725	sec = bfd_make_section (stdoutput, ".arm.atpcs");
19726
19727	if (sec != NULL)
19728	  {
19729	    bfd_set_section_flags
19730	      (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
19731	    bfd_set_section_size (stdoutput, sec, 0);
19732	    bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
19733	  }
19734      }
19735  }
19736#endif
19737
19738  /* Record the CPU type as well.  */
19739  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
19740    mach = bfd_mach_arm_iWMMXt2;
19741  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
19742    mach = bfd_mach_arm_iWMMXt;
19743  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
19744    mach = bfd_mach_arm_XScale;
19745  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
19746    mach = bfd_mach_arm_ep9312;
19747  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
19748    mach = bfd_mach_arm_5TE;
19749  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
19750    {
19751      if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
19752	mach = bfd_mach_arm_5T;
19753      else
19754	mach = bfd_mach_arm_5;
19755    }
19756  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
19757    {
19758      if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
19759	mach = bfd_mach_arm_4T;
19760      else
19761	mach = bfd_mach_arm_4;
19762    }
19763  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
19764    mach = bfd_mach_arm_3M;
19765  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
19766    mach = bfd_mach_arm_3;
19767  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
19768    mach = bfd_mach_arm_2a;
19769  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
19770    mach = bfd_mach_arm_2;
19771  else
19772    mach = bfd_mach_arm_unknown;
19773
19774  bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
19775}
19776
19777/* Command line processing.  */
19778
19779/* md_parse_option
19780      Invocation line includes a switch not recognized by the base assembler.
19781      See if it's a processor-specific option.
19782
19783      This routine is somewhat complicated by the need for backwards
19784      compatibility (since older releases of gcc can't be changed).
19785      The new options try to make the interface as compatible as
19786      possible with GCC.
19787
19788      New options (supported) are:
19789
19790	      -mcpu=<cpu name>		 Assemble for selected processor
19791	      -march=<architecture name> Assemble for selected architecture
19792	      -mfpu=<fpu architecture>	 Assemble for selected FPU.
19793	      -EB/-mbig-endian		 Big-endian
19794	      -EL/-mlittle-endian	 Little-endian
19795	      -k			 Generate PIC code
19796	      -mthumb			 Start in Thumb mode
19797	      -mthumb-interwork		 Code supports ARM/Thumb interworking
19798
19799      For now we will also provide support for:
19800
19801	      -mapcs-32			 32-bit Program counter
19802	      -mapcs-26			 26-bit Program counter
19803	      -macps-float		 Floats passed in FP registers
19804	      -mapcs-reentrant		 Reentrant code
19805	      -matpcs
19806      (sometime these will probably be replaced with -mapcs=<list of options>
19807      and -matpcs=<list of options>)
19808
19809      The remaining options are only supported for back-wards compatibility.
19810      Cpu variants, the arm part is optional:
19811	      -m[arm]1		      Currently not supported.
19812	      -m[arm]2, -m[arm]250    Arm 2 and Arm 250 processor
19813	      -m[arm]3		      Arm 3 processor
19814	      -m[arm]6[xx],	      Arm 6 processors
19815	      -m[arm]7[xx][t][[d]m]   Arm 7 processors
19816	      -m[arm]8[10]	      Arm 8 processors
19817	      -m[arm]9[20][tdmi]      Arm 9 processors
19818	      -mstrongarm[110[0]]     StrongARM processors
19819	      -mxscale		      XScale processors
19820	      -m[arm]v[2345[t[e]]]    Arm architectures
19821	      -mall		      All (except the ARM1)
19822      FP variants:
19823	      -mfpa10, -mfpa11	      FPA10 and 11 co-processor instructions
19824	      -mfpe-old		      (No float load/store multiples)
19825	      -mvfpxd		      VFP Single precision
19826	      -mvfp		      All VFP
19827	      -mno-fpu		      Disable all floating point instructions
19828
19829      The following CPU names are recognized:
19830	      arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19831	      arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19832	      arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19833	      arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19834	      arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19835	      arm10t arm10e, arm1020t, arm1020e, arm10200e,
19836	      strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19837
19838      */
19839
19840const char * md_shortopts = "m:k";
19841
19842#ifdef ARM_BI_ENDIAN
19843#define OPTION_EB (OPTION_MD_BASE + 0)
19844#define OPTION_EL (OPTION_MD_BASE + 1)
19845#else
19846#if TARGET_BYTES_BIG_ENDIAN
19847#define OPTION_EB (OPTION_MD_BASE + 0)
19848#else
19849#define OPTION_EL (OPTION_MD_BASE + 1)
19850#endif
19851#endif
19852
19853struct option md_longopts[] =
19854{
19855#ifdef OPTION_EB
19856  {"EB", no_argument, NULL, OPTION_EB},
19857#endif
19858#ifdef OPTION_EL
19859  {"EL", no_argument, NULL, OPTION_EL},
19860#endif
19861  {NULL, no_argument, NULL, 0}
19862};
19863
19864size_t md_longopts_size = sizeof (md_longopts);
19865
19866struct arm_option_table
19867{
19868  char *option;		/* Option name to match.  */
19869  char *help;		/* Help information.  */
19870  int  *var;		/* Variable to change.	*/
19871  int	value;		/* What to change it to.  */
19872  char *deprecated;	/* If non-null, print this message.  */
19873};
19874
19875struct arm_option_table arm_opts[] =
19876{
19877  {"k",	     N_("generate PIC code"),	   &pic_code,	 1, NULL},
19878  {"mthumb", N_("assemble Thumb code"),	   &thumb_mode,	 1, NULL},
19879  {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19880   &support_interwork, 1, NULL},
19881  {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
19882  {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
19883  {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
19884   1, NULL},
19885  {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
19886  {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
19887  {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
19888  {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
19889   NULL},
19890
19891  /* These are recognized by the assembler, but have no affect on code.	 */
19892  {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
19893  {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
19894  {NULL, NULL, NULL, 0, NULL}
19895};
19896
19897struct arm_legacy_option_table
19898{
19899  char *option;				/* Option name to match.  */
19900  const arm_feature_set	**var;		/* Variable to change.	*/
19901  const arm_feature_set	value;		/* What to change it to.  */
19902  char *deprecated;			/* If non-null, print this message.  */
19903};
19904
19905const struct arm_legacy_option_table arm_legacy_opts[] =
19906{
19907  /* DON'T add any new processors to this list -- we want the whole list
19908     to go away...  Add them to the processors table instead.  */
19909  {"marm1",	 &legacy_cpu, ARM_ARCH_V1,  N_("use -mcpu=arm1")},
19910  {"m1",	 &legacy_cpu, ARM_ARCH_V1,  N_("use -mcpu=arm1")},
19911  {"marm2",	 &legacy_cpu, ARM_ARCH_V2,  N_("use -mcpu=arm2")},
19912  {"m2",	 &legacy_cpu, ARM_ARCH_V2,  N_("use -mcpu=arm2")},
19913  {"marm250",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
19914  {"m250",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
19915  {"marm3",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
19916  {"m3",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
19917  {"marm6",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm6")},
19918  {"m6",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm6")},
19919  {"marm600",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm600")},
19920  {"m600",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm600")},
19921  {"marm610",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm610")},
19922  {"m610",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm610")},
19923  {"marm620",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm620")},
19924  {"m620",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm620")},
19925  {"marm7",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7")},
19926  {"m7",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7")},
19927  {"marm70",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm70")},
19928  {"m70",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm70")},
19929  {"marm700",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700")},
19930  {"m700",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700")},
19931  {"marm700i",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700i")},
19932  {"m700i",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700i")},
19933  {"marm710",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710")},
19934  {"m710",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710")},
19935  {"marm710c",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710c")},
19936  {"m710c",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710c")},
19937  {"marm720",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm720")},
19938  {"m720",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm720")},
19939  {"marm7d",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7d")},
19940  {"m7d",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7d")},
19941  {"marm7di",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7di")},
19942  {"m7di",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7di")},
19943  {"marm7m",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
19944  {"m7m",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
19945  {"marm7dm",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
19946  {"m7dm",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
19947  {"marm7dmi",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
19948  {"m7dmi",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
19949  {"marm7100",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7100")},
19950  {"m7100",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7100")},
19951  {"marm7500",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500")},
19952  {"m7500",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500")},
19953  {"marm7500fe", &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500fe")},
19954  {"m7500fe",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500fe")},
19955  {"marm7t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19956  {"m7t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19957  {"marm7tdmi",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19958  {"m7tdmi",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19959  {"marm710t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
19960  {"m710t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
19961  {"marm720t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
19962  {"m720t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
19963  {"marm740t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
19964  {"m740t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
19965  {"marm8",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm8")},
19966  {"m8",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm8")},
19967  {"marm810",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm810")},
19968  {"m810",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm810")},
19969  {"marm9",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
19970  {"m9",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
19971  {"marm9tdmi",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
19972  {"m9tdmi",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
19973  {"marm920",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
19974  {"m920",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
19975  {"marm940",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
19976  {"m940",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
19977  {"mstrongarm", &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=strongarm")},
19978  {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
19979   N_("use -mcpu=strongarm110")},
19980  {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
19981   N_("use -mcpu=strongarm1100")},
19982  {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
19983   N_("use -mcpu=strongarm1110")},
19984  {"mxscale",	 &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
19985  {"miwmmxt",	 &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
19986  {"mall",	 &legacy_cpu, ARM_ANY,	       N_("use -mcpu=all")},
19987
19988  /* Architecture variants -- don't add any more to this list either.  */
19989  {"mv2",	 &legacy_cpu, ARM_ARCH_V2,  N_("use -march=armv2")},
19990  {"marmv2",	 &legacy_cpu, ARM_ARCH_V2,  N_("use -march=armv2")},
19991  {"mv2a",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
19992  {"marmv2a",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
19993  {"mv3",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -march=armv3")},
19994  {"marmv3",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -march=armv3")},
19995  {"mv3m",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
19996  {"marmv3m",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
19997  {"mv4",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -march=armv4")},
19998  {"marmv4",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -march=armv4")},
19999  {"mv4t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
20000  {"marmv4t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
20001  {"mv5",	 &legacy_cpu, ARM_ARCH_V5,  N_("use -march=armv5")},
20002  {"marmv5",	 &legacy_cpu, ARM_ARCH_V5,  N_("use -march=armv5")},
20003  {"mv5t",	 &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
20004  {"marmv5t",	 &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
20005  {"mv5e",	 &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
20006  {"marmv5e",	 &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
20007
20008  /* Floating point variants -- don't add any more to this list either.	 */
20009  {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
20010  {"mfpa10",   &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
20011  {"mfpa11",   &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
20012  {"mno-fpu",  &legacy_fpu, ARM_ARCH_NONE,
20013   N_("use either -mfpu=softfpa or -mfpu=softvfp")},
20014
20015  {NULL, NULL, ARM_ARCH_NONE, NULL}
20016};
20017
20018struct arm_cpu_option_table
20019{
20020  char *name;
20021  const arm_feature_set	value;
20022  /* For some CPUs we assume an FPU unless the user explicitly sets
20023     -mfpu=...	*/
20024  const arm_feature_set	default_fpu;
20025  /* The canonical name of the CPU, or NULL to use NAME converted to upper
20026     case.  */
20027  const char *canonical_name;
20028};
20029
20030/* This list should, at a minimum, contain all the cpu names
20031   recognized by GCC.  */
20032static const struct arm_cpu_option_table arm_cpus[] =
20033{
20034  {"all",		ARM_ANY,	 FPU_ARCH_FPA,    NULL},
20035  {"arm1",		ARM_ARCH_V1,	 FPU_ARCH_FPA,    NULL},
20036  {"arm2",		ARM_ARCH_V2,	 FPU_ARCH_FPA,    NULL},
20037  {"arm250",		ARM_ARCH_V2S,	 FPU_ARCH_FPA,    NULL},
20038  {"arm3",		ARM_ARCH_V2S,	 FPU_ARCH_FPA,    NULL},
20039  {"arm6",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20040  {"arm60",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20041  {"arm600",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20042  {"arm610",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20043  {"arm620",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20044  {"arm7",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20045  {"arm7m",		ARM_ARCH_V3M,	 FPU_ARCH_FPA,    NULL},
20046  {"arm7d",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20047  {"arm7dm",		ARM_ARCH_V3M,	 FPU_ARCH_FPA,    NULL},
20048  {"arm7di",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20049  {"arm7dmi",		ARM_ARCH_V3M,	 FPU_ARCH_FPA,    NULL},
20050  {"arm70",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20051  {"arm700",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20052  {"arm700i",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20053  {"arm710",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20054  {"arm710t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
20055  {"arm720",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20056  {"arm720t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
20057  {"arm740t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
20058  {"arm710c",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20059  {"arm7100",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20060  {"arm7500",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20061  {"arm7500fe",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
20062  {"arm7t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
20063  {"arm7tdmi",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
20064  {"arm7tdmi-s",	ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
20065  {"arm8",		ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
20066  {"arm810",		ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
20067  {"strongarm",		ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
20068  {"strongarm1",	ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
20069  {"strongarm110",	ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
20070  {"strongarm1100",	ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
20071  {"strongarm1110",	ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
20072  {"arm9",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
20073  {"arm920",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    "ARM920T"},
20074  {"arm920t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
20075  {"arm922t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
20076  {"arm940t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
20077  {"arm9tdmi",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,	  NULL},
20078  /* For V5 or later processors we default to using VFP; but the user
20079     should really set the FPU type explicitly.	 */
20080  {"arm9e-r0",		ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
20081  {"arm9e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
20082  {"arm926ej",		ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP_V2, "ARM926EJ-S"},
20083  {"arm926ejs",		ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP_V2, "ARM926EJ-S"},
20084  {"arm926ej-s",	ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP_V2, NULL},
20085  {"arm946e-r0",	ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
20086  {"arm946e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, "ARM946E-S"},
20087  {"arm946e-s",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
20088  {"arm966e-r0",	ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
20089  {"arm966e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, "ARM966E-S"},
20090  {"arm966e-s",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
20091  {"arm968e-s",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
20092  {"arm10t",		ARM_ARCH_V5T,	 FPU_ARCH_VFP_V1, NULL},
20093  {"arm10tdmi",		ARM_ARCH_V5T,	 FPU_ARCH_VFP_V1, NULL},
20094  {"arm10e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
20095  {"arm1020",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, "ARM1020E"},
20096  {"arm1020t",		ARM_ARCH_V5T,	 FPU_ARCH_VFP_V1, NULL},
20097  {"arm1020e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
20098  {"arm1022e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
20099  {"arm1026ejs",	ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
20100  {"arm1026ej-s",	ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP_V2, NULL},
20101  {"arm1136js",		ARM_ARCH_V6,	 FPU_NONE,	  "ARM1136J-S"},
20102  {"arm1136j-s",	ARM_ARCH_V6,	 FPU_NONE,	  NULL},
20103  {"arm1136jfs",	ARM_ARCH_V6,	 FPU_ARCH_VFP_V2, "ARM1136JF-S"},
20104  {"arm1136jf-s",	ARM_ARCH_V6,	 FPU_ARCH_VFP_V2, NULL},
20105  {"mpcore",		ARM_ARCH_V6K,	 FPU_ARCH_VFP_V2, NULL},
20106  {"mpcorenovfp",	ARM_ARCH_V6K,	 FPU_NONE,	  NULL},
20107  {"arm1156t2-s",	ARM_ARCH_V6T2,	 FPU_NONE,	  NULL},
20108  {"arm1156t2f-s",	ARM_ARCH_V6T2,	 FPU_ARCH_VFP_V2, NULL},
20109  {"arm1176jz-s",	ARM_ARCH_V6ZK,	 FPU_NONE,	  NULL},
20110  {"arm1176jzf-s",	ARM_ARCH_V6ZK,	 FPU_ARCH_VFP_V2, NULL},
20111  {"cortex-a8",		ARM_ARCH_V7A,	 ARM_FEATURE(0, FPU_VFP_V3
20112                                                        | FPU_NEON_EXT_V1),
20113                                                          NULL},
20114  {"cortex-a9",		ARM_ARCH_V7A,	 ARM_FEATURE(0, FPU_VFP_V3
20115                                                        | FPU_NEON_EXT_V1),
20116                                                          NULL},
20117  {"cortex-r4",		ARM_ARCH_V7R,	 FPU_NONE,	  NULL},
20118  {"cortex-m3",		ARM_ARCH_V7M,	 FPU_NONE,	  NULL},
20119  /* ??? XSCALE is really an architecture.  */
20120  {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
20121  /* ??? iwmmxt is not a processor.  */
20122  {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
20123  {"iwmmxt2",		ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
20124  {"i80200",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
20125  /* Maverick */
20126  {"ep9312",	ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
20127  {NULL,		ARM_ARCH_NONE,	 ARM_ARCH_NONE, NULL}
20128};
20129
20130struct arm_arch_option_table
20131{
20132  char *name;
20133  const arm_feature_set	value;
20134  const arm_feature_set	default_fpu;
20135};
20136
20137/* This list should, at a minimum, contain all the architecture names
20138   recognized by GCC.  */
20139static const struct arm_arch_option_table arm_archs[] =
20140{
20141  {"all",		ARM_ANY,	 FPU_ARCH_FPA},
20142  {"armv1",		ARM_ARCH_V1,	 FPU_ARCH_FPA},
20143  {"armv2",		ARM_ARCH_V2,	 FPU_ARCH_FPA},
20144  {"armv2a",		ARM_ARCH_V2S,	 FPU_ARCH_FPA},
20145  {"armv2s",		ARM_ARCH_V2S,	 FPU_ARCH_FPA},
20146  {"armv3",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
20147  {"armv3m",		ARM_ARCH_V3M,	 FPU_ARCH_FPA},
20148  {"armv4",		ARM_ARCH_V4,	 FPU_ARCH_FPA},
20149  {"armv4xm",		ARM_ARCH_V4xM,	 FPU_ARCH_FPA},
20150  {"armv4t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA},
20151  {"armv4txm",		ARM_ARCH_V4TxM,	 FPU_ARCH_FPA},
20152  {"armv5",		ARM_ARCH_V5,	 FPU_ARCH_VFP},
20153  {"armv5t",		ARM_ARCH_V5T,	 FPU_ARCH_VFP},
20154  {"armv5txm",		ARM_ARCH_V5TxM,	 FPU_ARCH_VFP},
20155  {"armv5te",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP},
20156  {"armv5texp",		ARM_ARCH_V5TExP, FPU_ARCH_VFP},
20157  {"armv5tej",		ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP},
20158  {"armv6",		ARM_ARCH_V6,	 FPU_ARCH_VFP},
20159  {"armv6j",		ARM_ARCH_V6,	 FPU_ARCH_VFP},
20160  {"armv6k",		ARM_ARCH_V6K,	 FPU_ARCH_VFP},
20161  {"armv6z",		ARM_ARCH_V6Z,	 FPU_ARCH_VFP},
20162  {"armv6zk",		ARM_ARCH_V6ZK,	 FPU_ARCH_VFP},
20163  {"armv6t2",		ARM_ARCH_V6T2,	 FPU_ARCH_VFP},
20164  {"armv6kt2",		ARM_ARCH_V6KT2,	 FPU_ARCH_VFP},
20165  {"armv6zt2",		ARM_ARCH_V6ZT2,	 FPU_ARCH_VFP},
20166  {"armv6zkt2",		ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
20167  {"armv7",		ARM_ARCH_V7,	 FPU_ARCH_VFP},
20168  /* The official spelling of the ARMv7 profile variants is the dashed form.
20169     Accept the non-dashed form for compatibility with old toolchains.  */
20170  {"armv7a",		ARM_ARCH_V7A,	 FPU_ARCH_VFP},
20171  {"armv7r",		ARM_ARCH_V7R,	 FPU_ARCH_VFP},
20172  {"armv7m",		ARM_ARCH_V7M,	 FPU_ARCH_VFP},
20173  {"armv7-a",		ARM_ARCH_V7A,	 FPU_ARCH_VFP},
20174  {"armv7-r",		ARM_ARCH_V7R,	 FPU_ARCH_VFP},
20175  {"armv7-m",		ARM_ARCH_V7M,	 FPU_ARCH_VFP},
20176  {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP},
20177  {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
20178  {"iwmmxt2",		ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
20179  {NULL,		ARM_ARCH_NONE,	 ARM_ARCH_NONE}
20180};
20181
20182/* ISA extensions in the co-processor space.  */
20183struct arm_option_cpu_value_table
20184{
20185  char *name;
20186  const arm_feature_set value;
20187};
20188
20189static const struct arm_option_cpu_value_table arm_extensions[] =
20190{
20191  {"maverick",		ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
20192  {"xscale",		ARM_FEATURE (0, ARM_CEXT_XSCALE)},
20193  {"iwmmxt",		ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
20194  {"iwmmxt2",		ARM_FEATURE (0, ARM_CEXT_IWMMXT2)},
20195  {"sec",		ARM_FEATURE (ARM_EXT_V6Z, 0)},
20196  {NULL,		ARM_ARCH_NONE}
20197};
20198
20199/* This list should, at a minimum, contain all the fpu names
20200   recognized by GCC.  */
20201static const struct arm_option_cpu_value_table arm_fpus[] =
20202{
20203  {"softfpa",		FPU_NONE},
20204  {"fpe",		FPU_ARCH_FPE},
20205  {"fpe2",		FPU_ARCH_FPE},
20206  {"fpe3",		FPU_ARCH_FPA},	/* Third release supports LFM/SFM.  */
20207  {"fpa",		FPU_ARCH_FPA},
20208  {"fpa10",		FPU_ARCH_FPA},
20209  {"fpa11",		FPU_ARCH_FPA},
20210  {"arm7500fe",		FPU_ARCH_FPA},
20211  {"softvfp",		FPU_ARCH_VFP},
20212  {"softvfp+vfp",	FPU_ARCH_VFP_V2},
20213  {"vfp",		FPU_ARCH_VFP_V2},
20214  {"vfpv2",		FPU_ARCH_VFP_V2},
20215  {"vfp9",		FPU_ARCH_VFP_V2},
20216  {"vfp3",              FPU_ARCH_VFP_V3},
20217  {"vfpv3",             FPU_ARCH_VFP_V3},
20218  {"vfp10",		FPU_ARCH_VFP_V2},
20219  {"vfp10-r0",		FPU_ARCH_VFP_V1},
20220  {"vfpxd",		FPU_ARCH_VFP_V1xD},
20221  {"arm1020t",		FPU_ARCH_VFP_V1},
20222  {"arm1020e",		FPU_ARCH_VFP_V2},
20223  {"arm1136jfs",	FPU_ARCH_VFP_V2},
20224  {"arm1136jf-s",	FPU_ARCH_VFP_V2},
20225  {"maverick",		FPU_ARCH_MAVERICK},
20226  {"neon",              FPU_ARCH_VFP_V3_PLUS_NEON_V1},
20227  {NULL,		ARM_ARCH_NONE}
20228};
20229
20230struct arm_option_value_table
20231{
20232  char *name;
20233  long value;
20234};
20235
20236static const struct arm_option_value_table arm_float_abis[] =
20237{
20238  {"hard",	ARM_FLOAT_ABI_HARD},
20239  {"softfp",	ARM_FLOAT_ABI_SOFTFP},
20240  {"soft",	ARM_FLOAT_ABI_SOFT},
20241  {NULL,	0}
20242};
20243
20244#ifdef OBJ_ELF
20245/* We only know how to output GNU and ver 4/5 (AAELF) formats.  */
20246static const struct arm_option_value_table arm_eabis[] =
20247{
20248  {"gnu",	EF_ARM_EABI_UNKNOWN},
20249  {"4",		EF_ARM_EABI_VER4},
20250  {"5",		EF_ARM_EABI_VER5},
20251  {NULL,	0}
20252};
20253#endif
20254
20255struct arm_long_option_table
20256{
20257  char * option;		/* Substring to match.	*/
20258  char * help;			/* Help information.  */
20259  int (* func) (char * subopt);	/* Function to decode sub-option.  */
20260  char * deprecated;		/* If non-null, print this message.  */
20261};
20262
20263static int
20264arm_parse_extension (char * str, const arm_feature_set **opt_p)
20265{
20266  arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set));
20267
20268  /* Copy the feature set, so that we can modify it.  */
20269  *ext_set = **opt_p;
20270  *opt_p = ext_set;
20271
20272  while (str != NULL && *str != 0)
20273    {
20274      const struct arm_option_cpu_value_table * opt;
20275      char * ext;
20276      int optlen;
20277
20278      if (*str != '+')
20279	{
20280	  as_bad (_("invalid architectural extension"));
20281	  return 0;
20282	}
20283
20284      str++;
20285      ext = strchr (str, '+');
20286
20287      if (ext != NULL)
20288	optlen = ext - str;
20289      else
20290	optlen = strlen (str);
20291
20292      if (optlen == 0)
20293	{
20294	  as_bad (_("missing architectural extension"));
20295	  return 0;
20296	}
20297
20298      for (opt = arm_extensions; opt->name != NULL; opt++)
20299	if (strncmp (opt->name, str, optlen) == 0)
20300	  {
20301	    ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
20302	    break;
20303	  }
20304
20305      if (opt->name == NULL)
20306	{
20307	  as_bad (_("unknown architectural extnsion `%s'"), str);
20308	  return 0;
20309	}
20310
20311      str = ext;
20312    };
20313
20314  return 1;
20315}
20316
20317static int
20318arm_parse_cpu (char * str)
20319{
20320  const struct arm_cpu_option_table * opt;
20321  char * ext = strchr (str, '+');
20322  int optlen;
20323
20324  if (ext != NULL)
20325    optlen = ext - str;
20326  else
20327    optlen = strlen (str);
20328
20329  if (optlen == 0)
20330    {
20331      as_bad (_("missing cpu name `%s'"), str);
20332      return 0;
20333    }
20334
20335  for (opt = arm_cpus; opt->name != NULL; opt++)
20336    if (strncmp (opt->name, str, optlen) == 0)
20337      {
20338	mcpu_cpu_opt = &opt->value;
20339	mcpu_fpu_opt = &opt->default_fpu;
20340	if (opt->canonical_name)
20341	  strcpy(selected_cpu_name, opt->canonical_name);
20342	else
20343	  {
20344	    int i;
20345	    for (i = 0; i < optlen; i++)
20346	      selected_cpu_name[i] = TOUPPER (opt->name[i]);
20347	    selected_cpu_name[i] = 0;
20348	  }
20349
20350	if (ext != NULL)
20351	  return arm_parse_extension (ext, &mcpu_cpu_opt);
20352
20353	return 1;
20354      }
20355
20356  as_bad (_("unknown cpu `%s'"), str);
20357  return 0;
20358}
20359
20360static int
20361arm_parse_arch (char * str)
20362{
20363  const struct arm_arch_option_table *opt;
20364  char *ext = strchr (str, '+');
20365  int optlen;
20366
20367  if (ext != NULL)
20368    optlen = ext - str;
20369  else
20370    optlen = strlen (str);
20371
20372  if (optlen == 0)
20373    {
20374      as_bad (_("missing architecture name `%s'"), str);
20375      return 0;
20376    }
20377
20378  for (opt = arm_archs; opt->name != NULL; opt++)
20379    if (strncmp (opt->name, str, optlen) == 0)
20380      {
20381	march_cpu_opt = &opt->value;
20382	march_fpu_opt = &opt->default_fpu;
20383	strcpy(selected_cpu_name, opt->name);
20384
20385	if (ext != NULL)
20386	  return arm_parse_extension (ext, &march_cpu_opt);
20387
20388	return 1;
20389      }
20390
20391  as_bad (_("unknown architecture `%s'\n"), str);
20392  return 0;
20393}
20394
20395static int
20396arm_parse_fpu (char * str)
20397{
20398  const struct arm_option_cpu_value_table * opt;
20399
20400  for (opt = arm_fpus; opt->name != NULL; opt++)
20401    if (streq (opt->name, str))
20402      {
20403	mfpu_opt = &opt->value;
20404	return 1;
20405      }
20406
20407  as_bad (_("unknown floating point format `%s'\n"), str);
20408  return 0;
20409}
20410
20411static int
20412arm_parse_float_abi (char * str)
20413{
20414  const struct arm_option_value_table * opt;
20415
20416  for (opt = arm_float_abis; opt->name != NULL; opt++)
20417    if (streq (opt->name, str))
20418      {
20419	mfloat_abi_opt = opt->value;
20420	return 1;
20421      }
20422
20423  as_bad (_("unknown floating point abi `%s'\n"), str);
20424  return 0;
20425}
20426
20427#ifdef OBJ_ELF
20428static int
20429arm_parse_eabi (char * str)
20430{
20431  const struct arm_option_value_table *opt;
20432
20433  for (opt = arm_eabis; opt->name != NULL; opt++)
20434    if (streq (opt->name, str))
20435      {
20436	meabi_flags = opt->value;
20437	return 1;
20438      }
20439  as_bad (_("unknown EABI `%s'\n"), str);
20440  return 0;
20441}
20442#endif
20443
20444struct arm_long_option_table arm_long_opts[] =
20445{
20446  {"mcpu=", N_("<cpu name>\t  assemble for CPU <cpu name>"),
20447   arm_parse_cpu, NULL},
20448  {"march=", N_("<arch name>\t  assemble for architecture <arch name>"),
20449   arm_parse_arch, NULL},
20450  {"mfpu=", N_("<fpu name>\t  assemble for FPU architecture <fpu name>"),
20451   arm_parse_fpu, NULL},
20452  {"mfloat-abi=", N_("<abi>\t  assemble for floating point ABI <abi>"),
20453   arm_parse_float_abi, NULL},
20454#ifdef OBJ_ELF
20455  {"meabi=", N_("<ver>\t  assemble for eabi version <ver>"),
20456   arm_parse_eabi, NULL},
20457#endif
20458  {NULL, NULL, 0, NULL}
20459};
20460
20461int
20462md_parse_option (int c, char * arg)
20463{
20464  struct arm_option_table *opt;
20465  const struct arm_legacy_option_table *fopt;
20466  struct arm_long_option_table *lopt;
20467
20468  switch (c)
20469    {
20470#ifdef OPTION_EB
20471    case OPTION_EB:
20472      target_big_endian = 1;
20473      break;
20474#endif
20475
20476#ifdef OPTION_EL
20477    case OPTION_EL:
20478      target_big_endian = 0;
20479      break;
20480#endif
20481
20482    case 'a':
20483      /* Listing option.  Just ignore these, we don't support additional
20484	 ones.	*/
20485      return 0;
20486
20487    default:
20488      for (opt = arm_opts; opt->option != NULL; opt++)
20489	{
20490	  if (c == opt->option[0]
20491	      && ((arg == NULL && opt->option[1] == 0)
20492		  || streq (arg, opt->option + 1)))
20493	    {
20494#if WARN_DEPRECATED
20495	      /* If the option is deprecated, tell the user.  */
20496	      if (opt->deprecated != NULL)
20497		as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
20498			   arg ? arg : "", _(opt->deprecated));
20499#endif
20500
20501	      if (opt->var != NULL)
20502		*opt->var = opt->value;
20503
20504	      return 1;
20505	    }
20506	}
20507
20508      for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
20509	{
20510	  if (c == fopt->option[0]
20511	      && ((arg == NULL && fopt->option[1] == 0)
20512		  || streq (arg, fopt->option + 1)))
20513	    {
20514#if WARN_DEPRECATED
20515	      /* If the option is deprecated, tell the user.  */
20516	      if (fopt->deprecated != NULL)
20517		as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
20518			   arg ? arg : "", _(fopt->deprecated));
20519#endif
20520
20521	      if (fopt->var != NULL)
20522		*fopt->var = &fopt->value;
20523
20524	      return 1;
20525	    }
20526	}
20527
20528      for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
20529	{
20530	  /* These options are expected to have an argument.  */
20531	  if (c == lopt->option[0]
20532	      && arg != NULL
20533	      && strncmp (arg, lopt->option + 1,
20534			  strlen (lopt->option + 1)) == 0)
20535	    {
20536#if WARN_DEPRECATED
20537	      /* If the option is deprecated, tell the user.  */
20538	      if (lopt->deprecated != NULL)
20539		as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
20540			   _(lopt->deprecated));
20541#endif
20542
20543	      /* Call the sup-option parser.  */
20544	      return lopt->func (arg + strlen (lopt->option) - 1);
20545	    }
20546	}
20547
20548      return 0;
20549    }
20550
20551  return 1;
20552}
20553
20554void
20555md_show_usage (FILE * fp)
20556{
20557  struct arm_option_table *opt;
20558  struct arm_long_option_table *lopt;
20559
20560  fprintf (fp, _(" ARM-specific assembler options:\n"));
20561
20562  for (opt = arm_opts; opt->option != NULL; opt++)
20563    if (opt->help != NULL)
20564      fprintf (fp, "  -%-23s%s\n", opt->option, _(opt->help));
20565
20566  for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
20567    if (lopt->help != NULL)
20568      fprintf (fp, "  -%s%s\n", lopt->option, _(lopt->help));
20569
20570#ifdef OPTION_EB
20571  fprintf (fp, _("\
20572  -EB                     assemble code for a big-endian cpu\n"));
20573#endif
20574
20575#ifdef OPTION_EL
20576  fprintf (fp, _("\
20577  -EL                     assemble code for a little-endian cpu\n"));
20578#endif
20579}
20580
20581
20582#ifdef OBJ_ELF
20583typedef struct
20584{
20585  int val;
20586  arm_feature_set flags;
20587} cpu_arch_ver_table;
20588
20589/* Mapping from CPU features to EABI CPU arch values.  Table must be sorted
20590   least features first.  */
20591static const cpu_arch_ver_table cpu_arch_ver[] =
20592{
20593    {1, ARM_ARCH_V4},
20594    {2, ARM_ARCH_V4T},
20595    {3, ARM_ARCH_V5},
20596    {4, ARM_ARCH_V5TE},
20597    {5, ARM_ARCH_V5TEJ},
20598    {6, ARM_ARCH_V6},
20599    {7, ARM_ARCH_V6Z},
20600    {8, ARM_ARCH_V6K},
20601    {9, ARM_ARCH_V6T2},
20602    {10, ARM_ARCH_V7A},
20603    {10, ARM_ARCH_V7R},
20604    {10, ARM_ARCH_V7M},
20605    {0, ARM_ARCH_NONE}
20606};
20607
20608/* Set the public EABI object attributes.  */
20609static void
20610aeabi_set_public_attributes (void)
20611{
20612  int arch;
20613  arm_feature_set flags;
20614  arm_feature_set tmp;
20615  const cpu_arch_ver_table *p;
20616
20617  /* Choose the architecture based on the capabilities of the requested cpu
20618     (if any) and/or the instructions actually used.  */
20619  ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
20620  ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
20621  ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
20622  /*Allow the user to override the reported architecture.  */
20623  if (object_arch)
20624    {
20625      ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
20626      ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
20627    }
20628
20629  tmp = flags;
20630  arch = 0;
20631  for (p = cpu_arch_ver; p->val; p++)
20632    {
20633      if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
20634	{
20635	  arch = p->val;
20636	  ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
20637	}
20638    }
20639
20640  /* Tag_CPU_name.  */
20641  if (selected_cpu_name[0])
20642    {
20643      char *p;
20644
20645      p = selected_cpu_name;
20646      if (strncmp(p, "armv", 4) == 0)
20647	{
20648	  int i;
20649
20650	  p += 4;
20651	  for (i = 0; p[i]; i++)
20652	    p[i] = TOUPPER (p[i]);
20653	}
20654      bfd_elf_add_proc_attr_string (stdoutput, 5, p);
20655    }
20656  /* Tag_CPU_arch.  */
20657  bfd_elf_add_proc_attr_int (stdoutput, 6, arch);
20658  /* Tag_CPU_arch_profile.  */
20659  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
20660    bfd_elf_add_proc_attr_int (stdoutput, 7, 'A');
20661  else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
20662    bfd_elf_add_proc_attr_int (stdoutput, 7, 'R');
20663  else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m))
20664    bfd_elf_add_proc_attr_int (stdoutput, 7, 'M');
20665  /* Tag_ARM_ISA_use.  */
20666  if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
20667    bfd_elf_add_proc_attr_int (stdoutput, 8, 1);
20668  /* Tag_THUMB_ISA_use.  */
20669  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))
20670    bfd_elf_add_proc_attr_int (stdoutput, 9,
20671	ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
20672  /* Tag_VFP_arch.  */
20673  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3)
20674      || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3))
20675    bfd_elf_add_proc_attr_int (stdoutput, 10, 3);
20676  else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2)
20677           || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2))
20678    bfd_elf_add_proc_attr_int (stdoutput, 10, 2);
20679  else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1)
20680           || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1)
20681           || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd)
20682           || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd))
20683    bfd_elf_add_proc_attr_int (stdoutput, 10, 1);
20684  /* Tag_WMMX_arch.  */
20685  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
20686      || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))
20687    bfd_elf_add_proc_attr_int (stdoutput, 11, 1);
20688  /* Tag_NEON_arch.  */
20689  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1)
20690      || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1))
20691    bfd_elf_add_proc_attr_int (stdoutput, 12, 1);
20692}
20693
20694/* Add the default contents for the .ARM.attributes section.  */
20695void
20696arm_md_end (void)
20697{
20698  if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
20699    return;
20700
20701  aeabi_set_public_attributes ();
20702}
20703#endif /* OBJ_ELF */
20704
20705
20706/* Parse a .cpu directive.  */
20707
20708static void
20709s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
20710{
20711  const struct arm_cpu_option_table *opt;
20712  char *name;
20713  char saved_char;
20714
20715  name = input_line_pointer;
20716  while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20717    input_line_pointer++;
20718  saved_char = *input_line_pointer;
20719  *input_line_pointer = 0;
20720
20721  /* Skip the first "all" entry.  */
20722  for (opt = arm_cpus + 1; opt->name != NULL; opt++)
20723    if (streq (opt->name, name))
20724      {
20725	mcpu_cpu_opt = &opt->value;
20726	selected_cpu = opt->value;
20727	if (opt->canonical_name)
20728	  strcpy(selected_cpu_name, opt->canonical_name);
20729	else
20730	  {
20731	    int i;
20732	    for (i = 0; opt->name[i]; i++)
20733	      selected_cpu_name[i] = TOUPPER (opt->name[i]);
20734	    selected_cpu_name[i] = 0;
20735	  }
20736	ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
20737	*input_line_pointer = saved_char;
20738	demand_empty_rest_of_line ();
20739	return;
20740      }
20741  as_bad (_("unknown cpu `%s'"), name);
20742  *input_line_pointer = saved_char;
20743  ignore_rest_of_line ();
20744}
20745
20746
20747/* Parse a .arch directive.  */
20748
20749static void
20750s_arm_arch (int ignored ATTRIBUTE_UNUSED)
20751{
20752  const struct arm_arch_option_table *opt;
20753  char saved_char;
20754  char *name;
20755
20756  name = input_line_pointer;
20757  while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20758    input_line_pointer++;
20759  saved_char = *input_line_pointer;
20760  *input_line_pointer = 0;
20761
20762  /* Skip the first "all" entry.  */
20763  for (opt = arm_archs + 1; opt->name != NULL; opt++)
20764    if (streq (opt->name, name))
20765      {
20766	mcpu_cpu_opt = &opt->value;
20767	selected_cpu = opt->value;
20768	strcpy(selected_cpu_name, opt->name);
20769	ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
20770	*input_line_pointer = saved_char;
20771	demand_empty_rest_of_line ();
20772	return;
20773      }
20774
20775  as_bad (_("unknown architecture `%s'\n"), name);
20776  *input_line_pointer = saved_char;
20777  ignore_rest_of_line ();
20778}
20779
20780/* Parse a .arch_extension directive.  */
20781
20782static void
20783s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
20784{
20785  const struct arm_option_cpu_value_table *opt;
20786  char saved_char;
20787  char *name;
20788
20789  name = input_line_pointer;
20790  while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20791    input_line_pointer++;
20792  saved_char = *input_line_pointer;
20793  *input_line_pointer = 0;
20794
20795  for (opt = arm_extensions; opt->name != NULL; opt++)
20796    if (streq (opt->name, name))
20797      {
20798	ARM_MERGE_FEATURE_SETS (cpu_variant, cpu_variant, opt->value);
20799	*input_line_pointer = saved_char;
20800	demand_empty_rest_of_line ();
20801	return;
20802      }
20803
20804  as_bad (_("unknown architecture `%s'\n"), name);
20805  *input_line_pointer = saved_char;
20806  ignore_rest_of_line ();
20807}
20808
20809/* Parse a .object_arch directive.  */
20810
20811static void
20812s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
20813{
20814  const struct arm_arch_option_table *opt;
20815  char saved_char;
20816  char *name;
20817
20818  name = input_line_pointer;
20819  while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20820    input_line_pointer++;
20821  saved_char = *input_line_pointer;
20822  *input_line_pointer = 0;
20823
20824  /* Skip the first "all" entry.  */
20825  for (opt = arm_archs + 1; opt->name != NULL; opt++)
20826    if (streq (opt->name, name))
20827      {
20828	object_arch = &opt->value;
20829	*input_line_pointer = saved_char;
20830	demand_empty_rest_of_line ();
20831	return;
20832      }
20833
20834  as_bad (_("unknown architecture `%s'\n"), name);
20835  *input_line_pointer = saved_char;
20836  ignore_rest_of_line ();
20837}
20838
20839
20840/* Parse a .fpu directive.  */
20841
20842static void
20843s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
20844{
20845  const struct arm_option_cpu_value_table *opt;
20846  char saved_char;
20847  char *name;
20848
20849  name = input_line_pointer;
20850  while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20851    input_line_pointer++;
20852  saved_char = *input_line_pointer;
20853  *input_line_pointer = 0;
20854
20855  for (opt = arm_fpus; opt->name != NULL; opt++)
20856    if (streq (opt->name, name))
20857      {
20858	mfpu_opt = &opt->value;
20859	ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
20860	*input_line_pointer = saved_char;
20861	demand_empty_rest_of_line ();
20862	return;
20863      }
20864
20865  as_bad (_("unknown floating point format `%s'\n"), name);
20866  *input_line_pointer = saved_char;
20867  ignore_rest_of_line ();
20868}
20869
20870/* Copy symbol information.  */
20871void
20872arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
20873{
20874  ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
20875}
20876