1300829Sgrehan/*- 2336189Saraujo * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3336189Saraujo * 4300829Sgrehan * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> 5300829Sgrehan * All rights reserved. 6300829Sgrehan * 7300829Sgrehan * Redistribution and use in source and binary forms, with or without 8300829Sgrehan * modification, are permitted provided that the following conditions 9300829Sgrehan * are met: 10300829Sgrehan * 1. Redistributions of source code must retain the above copyright 11300829Sgrehan * notice, this list of conditions and the following disclaimer. 12300829Sgrehan * 2. Redistributions in binary form must reproduce the above copyright 13300829Sgrehan * notice, this list of conditions and the following disclaimer in the 14300829Sgrehan * documentation and/or other materials provided with the distribution. 15300829Sgrehan * 16300829Sgrehan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17300829Sgrehan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18300829Sgrehan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19300829Sgrehan * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20300829Sgrehan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21300829Sgrehan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22300829Sgrehan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23300829Sgrehan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24300829Sgrehan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25300829Sgrehan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26300829Sgrehan * SUCH DAMAGE. 27300829Sgrehan * 28300829Sgrehan * $FreeBSD: stable/11/usr.sbin/bhyve/vga.h 336189 2018-07-11 07:16:13Z araujo $ 29300829Sgrehan */ 30300829Sgrehan 31300829Sgrehan#ifndef _VGA_H_ 32300829Sgrehan#define _VGA_H_ 33300829Sgrehan 34300829Sgrehan#define VGA_IOPORT_START 0x3c0 35300829Sgrehan#define VGA_IOPORT_END 0x3df 36300829Sgrehan 37300829Sgrehan/* General registers */ 38300829Sgrehan#define GEN_INPUT_STS0_PORT 0x3c2 39300829Sgrehan#define GEN_FEATURE_CTRL_PORT 0x3ca 40300829Sgrehan#define GEN_MISC_OUTPUT_PORT 0x3cc 41300829Sgrehan#define GEN_INPUT_STS1_MONO_PORT 0x3ba 42300829Sgrehan#define GEN_INPUT_STS1_COLOR_PORT 0x3da 43336161Saraujo#define GEN_IS1_VR 0x08 /* Vertical retrace */ 44336161Saraujo#define GEN_IS1_DE 0x01 /* Display enable not */ 45300829Sgrehan 46300829Sgrehan/* Attribute controller registers. */ 47300829Sgrehan#define ATC_IDX_PORT 0x3c0 48300829Sgrehan#define ATC_DATA_PORT 0x3c1 49300829Sgrehan 50300829Sgrehan#define ATC_IDX_MASK 0x1f 51300829Sgrehan#define ATC_PALETTE0 0 52300829Sgrehan#define ATC_PALETTE15 15 53300829Sgrehan#define ATC_MODE_CONTROL 16 54336161Saraujo#define ATC_MC_IPS 0x80 /* Internal palette size */ 55336161Saraujo#define ATC_MC_GA 0x01 /* Graphics/alphanumeric */ 56300829Sgrehan#define ATC_OVERSCAN_COLOR 17 57300829Sgrehan#define ATC_COLOR_PLANE_ENABLE 18 58300829Sgrehan#define ATC_HORIZ_PIXEL_PANNING 19 59300829Sgrehan#define ATC_COLOR_SELECT 20 60336161Saraujo#define ATC_CS_C67 0x0c /* Color select bits 6+7 */ 61336161Saraujo#define ATC_CS_C45 0x03 /* Color select bits 4+5 */ 62300829Sgrehan 63300829Sgrehan/* Sequencer registers. */ 64300829Sgrehan#define SEQ_IDX_PORT 0x3c4 65300829Sgrehan#define SEQ_DATA_PORT 0x3c5 66300829Sgrehan 67300829Sgrehan#define SEQ_RESET 0 68300829Sgrehan#define SEQ_RESET_ASYNC 0x1 69300829Sgrehan#define SEQ_RESET_SYNC 0x2 70300829Sgrehan#define SEQ_CLOCKING_MODE 1 71336161Saraujo#define SEQ_CM_SO 0x20 /* Screen off */ 72336161Saraujo#define SEQ_CM_89 0x01 /* 8/9 dot clock */ 73300829Sgrehan#define SEQ_MAP_MASK 2 74300829Sgrehan#define SEQ_CHAR_MAP_SELECT 3 75336161Saraujo#define SEQ_CMS_SAH 0x20 /* Char map A bit 2 */ 76336161Saraujo#define SEQ_CMS_SAH_SHIFT 5 77336161Saraujo#define SEQ_CMS_SA 0x0c /* Char map A bits 0+1 */ 78336161Saraujo#define SEQ_CMS_SA_SHIFT 2 79336161Saraujo#define SEQ_CMS_SBH 0x10 /* Char map B bit 2 */ 80336161Saraujo#define SEQ_CMS_SBH_SHIFT 4 81336161Saraujo#define SEQ_CMS_SB 0x03 /* Char map B bits 0+1 */ 82336161Saraujo#define SEQ_CMS_SB_SHIFT 0 83300829Sgrehan#define SEQ_MEMORY_MODE 4 84336161Saraujo#define SEQ_MM_C4 0x08 /* Chain 4 */ 85336161Saraujo#define SEQ_MM_OE 0x04 /* Odd/even */ 86336161Saraujo#define SEQ_MM_EM 0x02 /* Extended memory */ 87300829Sgrehan 88300829Sgrehan/* Graphics controller registers. */ 89300829Sgrehan#define GC_IDX_PORT 0x3ce 90300829Sgrehan#define GC_DATA_PORT 0x3cf 91300829Sgrehan 92300829Sgrehan#define GC_SET_RESET 0 93300829Sgrehan#define GC_ENABLE_SET_RESET 1 94300829Sgrehan#define GC_COLOR_COMPARE 2 95300829Sgrehan#define GC_DATA_ROTATE 3 96300829Sgrehan#define GC_READ_MAP_SELECT 4 97300829Sgrehan#define GC_MODE 5 98336161Saraujo#define GC_MODE_OE 0x10 /* Odd/even */ 99336161Saraujo#define GC_MODE_C4 0x04 /* Chain 4 */ 100300829Sgrehan 101300829Sgrehan#define GC_MISCELLANEOUS 6 102336161Saraujo#define GC_MISC_GM 0x01 /* Graphics/alphanumeric */ 103336161Saraujo#define GC_MISC_MM 0x0c /* memory map */ 104336161Saraujo#define GC_MISC_MM_SHIFT 2 105300829Sgrehan#define GC_COLOR_DONT_CARE 7 106300829Sgrehan#define GC_BIT_MASK 8 107300829Sgrehan 108300829Sgrehan/* CRT controller registers. */ 109300829Sgrehan#define CRTC_IDX_MONO_PORT 0x3b4 110300829Sgrehan#define CRTC_DATA_MONO_PORT 0x3b5 111300829Sgrehan#define CRTC_IDX_COLOR_PORT 0x3d4 112300829Sgrehan#define CRTC_DATA_COLOR_PORT 0x3d5 113300829Sgrehan 114300829Sgrehan#define CRTC_HORIZ_TOTAL 0 115300829Sgrehan#define CRTC_HORIZ_DISP_END 1 116300829Sgrehan#define CRTC_START_HORIZ_BLANK 2 117300829Sgrehan#define CRTC_END_HORIZ_BLANK 3 118300829Sgrehan#define CRTC_START_HORIZ_RETRACE 4 119300829Sgrehan#define CRTC_END_HORIZ_RETRACE 5 120300829Sgrehan#define CRTC_VERT_TOTAL 6 121300829Sgrehan#define CRTC_OVERFLOW 7 122336161Saraujo#define CRTC_OF_VRS9 0x80 /* VRS bit 9 */ 123336161Saraujo#define CRTC_OF_VRS9_SHIFT 7 124336161Saraujo#define CRTC_OF_VDE9 0x40 /* VDE bit 9 */ 125336161Saraujo#define CRTC_OF_VDE9_SHIFT 6 126336161Saraujo#define CRTC_OF_VRS8 0x04 /* VRS bit 8 */ 127336161Saraujo#define CRTC_OF_VRS8_SHIFT 2 128336161Saraujo#define CRTC_OF_VDE8 0x02 /* VDE bit 8 */ 129336161Saraujo#define CRTC_OF_VDE8_SHIFT 1 130300829Sgrehan#define CRTC_PRESET_ROW_SCAN 8 131300829Sgrehan#define CRTC_MAX_SCAN_LINE 9 132336161Saraujo#define CRTC_MSL_MSL 0x1f 133300829Sgrehan#define CRTC_CURSOR_START 10 134336161Saraujo#define CRTC_CS_CO 0x20 /* Cursor off */ 135336161Saraujo#define CRTC_CS_CS 0x1f /* Cursor start */ 136300829Sgrehan#define CRTC_CURSOR_END 11 137336161Saraujo#define CRTC_CE_CE 0x1f /* Cursor end */ 138300829Sgrehan#define CRTC_START_ADDR_HIGH 12 139300829Sgrehan#define CRTC_START_ADDR_LOW 13 140300829Sgrehan#define CRTC_CURSOR_LOC_HIGH 14 141300829Sgrehan#define CRTC_CURSOR_LOC_LOW 15 142300829Sgrehan#define CRTC_VERT_RETRACE_START 16 143300829Sgrehan#define CRTC_VERT_RETRACE_END 17 144336161Saraujo#define CRTC_VRE_MASK 0xf 145300829Sgrehan#define CRTC_VERT_DISP_END 18 146300829Sgrehan#define CRTC_OFFSET 19 147300829Sgrehan#define CRTC_UNDERLINE_LOC 20 148300829Sgrehan#define CRTC_START_VERT_BLANK 21 149300829Sgrehan#define CRTC_END_VERT_BLANK 22 150300829Sgrehan#define CRTC_MODE_CONTROL 23 151336161Saraujo#define CRTC_MC_TE 0x80 /* Timing enable */ 152300829Sgrehan#define CRTC_LINE_COMPARE 24 153300829Sgrehan 154300829Sgrehan/* DAC registers */ 155300829Sgrehan#define DAC_MASK 0x3c6 156300829Sgrehan#define DAC_IDX_RD_PORT 0x3c7 157300829Sgrehan#define DAC_IDX_WR_PORT 0x3c8 158300829Sgrehan#define DAC_DATA_PORT 0x3c9 159300829Sgrehan 160300829Sgrehanvoid *vga_init(int io_only); 161300829Sgrehan 162300829Sgrehan#endif /* _VGA_H_ */ 163