pm.c revision 330449
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Hudson River Trading LLC 5 * Written by: John H. Baldwin <jhb@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/11/usr.sbin/bhyve/pm.c 330449 2018-03-05 07:26:05Z eadler $"); 32 33#include <sys/types.h> 34#include <machine/vmm.h> 35 36#include <assert.h> 37#include <errno.h> 38#include <pthread.h> 39#include <signal.h> 40#include <vmmapi.h> 41 42#include "acpi.h" 43#include "inout.h" 44#include "mevent.h" 45#include "pci_irq.h" 46#include "pci_lpc.h" 47 48static pthread_mutex_t pm_lock = PTHREAD_MUTEX_INITIALIZER; 49static struct mevent *power_button; 50static sig_t old_power_handler; 51 52/* 53 * Reset Control register at I/O port 0xcf9. Bit 2 forces a system 54 * reset when it transitions from 0 to 1. Bit 1 selects the type of 55 * reset to attempt: 0 selects a "soft" reset, and 1 selects a "hard" 56 * reset. 57 */ 58static int 59reset_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 60 uint32_t *eax, void *arg) 61{ 62 int error; 63 64 static uint8_t reset_control; 65 66 if (bytes != 1) 67 return (-1); 68 if (in) 69 *eax = reset_control; 70 else { 71 reset_control = *eax; 72 73 /* Treat hard and soft resets the same. */ 74 if (reset_control & 0x4) { 75 error = vm_suspend(ctx, VM_SUSPEND_RESET); 76 assert(error == 0 || errno == EALREADY); 77 } 78 } 79 return (0); 80} 81INOUT_PORT(reset_reg, 0xCF9, IOPORT_F_INOUT, reset_handler); 82 83/* 84 * ACPI's SCI is a level-triggered interrupt. 85 */ 86static int sci_active; 87 88static void 89sci_assert(struct vmctx *ctx) 90{ 91 92 if (sci_active) 93 return; 94 vm_isa_assert_irq(ctx, SCI_INT, SCI_INT); 95 sci_active = 1; 96} 97 98static void 99sci_deassert(struct vmctx *ctx) 100{ 101 102 if (!sci_active) 103 return; 104 vm_isa_deassert_irq(ctx, SCI_INT, SCI_INT); 105 sci_active = 0; 106} 107 108/* 109 * Power Management 1 Event Registers 110 * 111 * The only power management event supported is a power button upon 112 * receiving SIGTERM. 113 */ 114static uint16_t pm1_enable, pm1_status; 115 116#define PM1_TMR_STS 0x0001 117#define PM1_BM_STS 0x0010 118#define PM1_GBL_STS 0x0020 119#define PM1_PWRBTN_STS 0x0100 120#define PM1_SLPBTN_STS 0x0200 121#define PM1_RTC_STS 0x0400 122#define PM1_WAK_STS 0x8000 123 124#define PM1_TMR_EN 0x0001 125#define PM1_GBL_EN 0x0020 126#define PM1_PWRBTN_EN 0x0100 127#define PM1_SLPBTN_EN 0x0200 128#define PM1_RTC_EN 0x0400 129 130static void 131sci_update(struct vmctx *ctx) 132{ 133 int need_sci; 134 135 /* See if the SCI should be active or not. */ 136 need_sci = 0; 137 if ((pm1_enable & PM1_TMR_EN) && (pm1_status & PM1_TMR_STS)) 138 need_sci = 1; 139 if ((pm1_enable & PM1_GBL_EN) && (pm1_status & PM1_GBL_STS)) 140 need_sci = 1; 141 if ((pm1_enable & PM1_PWRBTN_EN) && (pm1_status & PM1_PWRBTN_STS)) 142 need_sci = 1; 143 if ((pm1_enable & PM1_SLPBTN_EN) && (pm1_status & PM1_SLPBTN_STS)) 144 need_sci = 1; 145 if ((pm1_enable & PM1_RTC_EN) && (pm1_status & PM1_RTC_STS)) 146 need_sci = 1; 147 if (need_sci) 148 sci_assert(ctx); 149 else 150 sci_deassert(ctx); 151} 152 153static int 154pm1_status_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 155 uint32_t *eax, void *arg) 156{ 157 158 if (bytes != 2) 159 return (-1); 160 161 pthread_mutex_lock(&pm_lock); 162 if (in) 163 *eax = pm1_status; 164 else { 165 /* 166 * Writes are only permitted to clear certain bits by 167 * writing 1 to those flags. 168 */ 169 pm1_status &= ~(*eax & (PM1_WAK_STS | PM1_RTC_STS | 170 PM1_SLPBTN_STS | PM1_PWRBTN_STS | PM1_BM_STS)); 171 sci_update(ctx); 172 } 173 pthread_mutex_unlock(&pm_lock); 174 return (0); 175} 176 177static int 178pm1_enable_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 179 uint32_t *eax, void *arg) 180{ 181 182 if (bytes != 2) 183 return (-1); 184 185 pthread_mutex_lock(&pm_lock); 186 if (in) 187 *eax = pm1_enable; 188 else { 189 /* 190 * Only permit certain bits to be set. We never use 191 * the global lock, but ACPI-CA whines profusely if it 192 * can't set GBL_EN. 193 */ 194 pm1_enable = *eax & (PM1_PWRBTN_EN | PM1_GBL_EN); 195 sci_update(ctx); 196 } 197 pthread_mutex_unlock(&pm_lock); 198 return (0); 199} 200INOUT_PORT(pm1_status, PM1A_EVT_ADDR, IOPORT_F_INOUT, pm1_status_handler); 201INOUT_PORT(pm1_enable, PM1A_EVT_ADDR + 2, IOPORT_F_INOUT, pm1_enable_handler); 202 203static void 204power_button_handler(int signal, enum ev_type type, void *arg) 205{ 206 struct vmctx *ctx; 207 208 ctx = arg; 209 pthread_mutex_lock(&pm_lock); 210 if (!(pm1_status & PM1_PWRBTN_STS)) { 211 pm1_status |= PM1_PWRBTN_STS; 212 sci_update(ctx); 213 } 214 pthread_mutex_unlock(&pm_lock); 215} 216 217/* 218 * Power Management 1 Control Register 219 * 220 * This is mostly unimplemented except that we wish to handle writes that 221 * set SPL_EN to handle S5 (soft power off). 222 */ 223static uint16_t pm1_control; 224 225#define PM1_SCI_EN 0x0001 226#define PM1_SLP_TYP 0x1c00 227#define PM1_SLP_EN 0x2000 228#define PM1_ALWAYS_ZERO 0xc003 229 230static int 231pm1_control_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 232 uint32_t *eax, void *arg) 233{ 234 int error; 235 236 if (bytes != 2) 237 return (-1); 238 if (in) 239 *eax = pm1_control; 240 else { 241 /* 242 * Various bits are write-only or reserved, so force them 243 * to zero in pm1_control. Always preserve SCI_EN as OSPM 244 * can never change it. 245 */ 246 pm1_control = (pm1_control & PM1_SCI_EN) | 247 (*eax & ~(PM1_SLP_EN | PM1_ALWAYS_ZERO)); 248 249 /* 250 * If SLP_EN is set, check for S5. Bhyve's _S5_ method 251 * says that '5' should be stored in SLP_TYP for S5. 252 */ 253 if (*eax & PM1_SLP_EN) { 254 if ((pm1_control & PM1_SLP_TYP) >> 10 == 5) { 255 error = vm_suspend(ctx, VM_SUSPEND_POWEROFF); 256 assert(error == 0 || errno == EALREADY); 257 } 258 } 259 } 260 return (0); 261} 262INOUT_PORT(pm1_control, PM1A_CNT_ADDR, IOPORT_F_INOUT, pm1_control_handler); 263SYSRES_IO(PM1A_EVT_ADDR, 8); 264 265/* 266 * ACPI SMI Command Register 267 * 268 * This write-only register is used to enable and disable ACPI. 269 */ 270static int 271smi_cmd_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 272 uint32_t *eax, void *arg) 273{ 274 275 assert(!in); 276 if (bytes != 1) 277 return (-1); 278 279 pthread_mutex_lock(&pm_lock); 280 switch (*eax) { 281 case BHYVE_ACPI_ENABLE: 282 pm1_control |= PM1_SCI_EN; 283 if (power_button == NULL) { 284 power_button = mevent_add(SIGTERM, EVF_SIGNAL, 285 power_button_handler, ctx); 286 old_power_handler = signal(SIGTERM, SIG_IGN); 287 } 288 break; 289 case BHYVE_ACPI_DISABLE: 290 pm1_control &= ~PM1_SCI_EN; 291 if (power_button != NULL) { 292 mevent_delete(power_button); 293 power_button = NULL; 294 signal(SIGTERM, old_power_handler); 295 } 296 break; 297 } 298 pthread_mutex_unlock(&pm_lock); 299 return (0); 300} 301INOUT_PORT(smi_cmd, SMI_CMD, IOPORT_F_OUT, smi_cmd_handler); 302SYSRES_IO(SMI_CMD, 1); 303 304void 305sci_init(struct vmctx *ctx) 306{ 307 308 /* 309 * Mark ACPI's SCI as level trigger and bump its use count 310 * in the PIRQ router. 311 */ 312 pci_irq_use(SCI_INT); 313 vm_isa_set_irq_trigger(ctx, SCI_INT, LEVEL_TRIGGER); 314} 315