1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org> 5 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/11/usr.sbin/bhyve/pci_lpc.c 330449 2018-03-05 07:26:05Z eadler $ 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: stable/11/usr.sbin/bhyve/pci_lpc.c 330449 2018-03-05 07:26:05Z eadler $"); 34 35#include <sys/types.h> 36#include <machine/vmm.h> 37 38#include <stdio.h> 39#include <stdlib.h> 40#include <string.h> 41 42#include <vmmapi.h> 43 44#include "acpi.h" 45#include "bootrom.h" 46#include "inout.h" 47#include "pci_emul.h" 48#include "pci_irq.h" 49#include "pci_lpc.h" 50#include "uart_emul.h" 51 52#define IO_ICU1 0x20 53#define IO_ICU2 0xA0 54 55SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt); 56SET_DECLARE(lpc_sysres_set, struct lpc_sysres); 57 58#define ELCR_PORT 0x4d0 59SYSRES_IO(ELCR_PORT, 2); 60 61#define IO_TIMER1_PORT 0x40 62 63#define NMISC_PORT 0x61 64SYSRES_IO(NMISC_PORT, 1); 65 66static struct pci_devinst *lpc_bridge; 67 68static const char *romfile; 69 70#define LPC_UART_NUM 2 71static struct lpc_uart_softc { 72 struct uart_softc *uart_softc; 73 const char *opts; 74 int iobase; 75 int irq; 76 int enabled; 77} lpc_uart_softc[LPC_UART_NUM]; 78 79static const char *lpc_uart_names[LPC_UART_NUM] = { "COM1", "COM2" }; 80 81/* 82 * LPC device configuration is in the following form: 83 * <lpc_device_name>[,<options>] 84 * For e.g. "com1,stdio" or "bootrom,/var/romfile" 85 */ 86int 87lpc_device_parse(const char *opts) 88{ 89 int unit, error; 90 char *str, *cpy, *lpcdev; 91 92 error = -1; 93 str = cpy = strdup(opts); 94 lpcdev = strsep(&str, ","); 95 if (lpcdev != NULL) { 96 if (strcasecmp(lpcdev, "bootrom") == 0) { 97 romfile = str; 98 error = 0; 99 goto done; 100 } 101 for (unit = 0; unit < LPC_UART_NUM; unit++) { 102 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) { 103 lpc_uart_softc[unit].opts = str; 104 error = 0; 105 goto done; 106 } 107 } 108 } 109 110done: 111 if (error) 112 free(cpy); 113 114 return (error); 115} 116 117const char * 118lpc_bootrom(void) 119{ 120 121 return (romfile); 122} 123 124static void 125lpc_uart_intr_assert(void *arg) 126{ 127 struct lpc_uart_softc *sc = arg; 128 129 assert(sc->irq >= 0); 130 131 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq); 132} 133 134static void 135lpc_uart_intr_deassert(void *arg) 136{ 137 /* 138 * The COM devices on the LPC bus generate edge triggered interrupts, 139 * so nothing more to do here. 140 */ 141} 142 143static int 144lpc_uart_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 145 uint32_t *eax, void *arg) 146{ 147 int offset; 148 struct lpc_uart_softc *sc = arg; 149 150 offset = port - sc->iobase; 151 152 switch (bytes) { 153 case 1: 154 if (in) 155 *eax = uart_read(sc->uart_softc, offset); 156 else 157 uart_write(sc->uart_softc, offset, *eax); 158 break; 159 case 2: 160 if (in) { 161 *eax = uart_read(sc->uart_softc, offset); 162 *eax |= uart_read(sc->uart_softc, offset + 1) << 8; 163 } else { 164 uart_write(sc->uart_softc, offset, *eax); 165 uart_write(sc->uart_softc, offset + 1, *eax >> 8); 166 } 167 break; 168 default: 169 return (-1); 170 } 171 172 return (0); 173} 174 175static int 176lpc_init(struct vmctx *ctx) 177{ 178 struct lpc_uart_softc *sc; 179 struct inout_port iop; 180 const char *name; 181 int unit, error; 182 183 if (romfile != NULL) { 184 error = bootrom_init(ctx, romfile); 185 if (error) 186 return (error); 187 } 188 189 /* COM1 and COM2 */ 190 for (unit = 0; unit < LPC_UART_NUM; unit++) { 191 sc = &lpc_uart_softc[unit]; 192 name = lpc_uart_names[unit]; 193 194 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) { 195 fprintf(stderr, "Unable to allocate resources for " 196 "LPC device %s\n", name); 197 return (-1); 198 } 199 pci_irq_reserve(sc->irq); 200 201 sc->uart_softc = uart_init(lpc_uart_intr_assert, 202 lpc_uart_intr_deassert, sc); 203 204 if (uart_set_backend(sc->uart_softc, sc->opts) != 0) { 205 fprintf(stderr, "Unable to initialize backend '%s' " 206 "for LPC device %s\n", sc->opts, name); 207 return (-1); 208 } 209 210 bzero(&iop, sizeof(struct inout_port)); 211 iop.name = name; 212 iop.port = sc->iobase; 213 iop.size = UART_IO_BAR_SIZE; 214 iop.flags = IOPORT_F_INOUT; 215 iop.handler = lpc_uart_io_handler; 216 iop.arg = sc; 217 218 error = register_inout(&iop); 219 assert(error == 0); 220 sc->enabled = 1; 221 } 222 223 return (0); 224} 225 226static void 227pci_lpc_write_dsdt(struct pci_devinst *pi) 228{ 229 struct lpc_dsdt **ldpp, *ldp; 230 231 dsdt_line(""); 232 dsdt_line("Device (ISA)"); 233 dsdt_line("{"); 234 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func); 235 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)"); 236 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)"); 237 dsdt_line(" {"); 238 dsdt_line(" Offset (0x60),"); 239 dsdt_line(" PIRA, 8,"); 240 dsdt_line(" PIRB, 8,"); 241 dsdt_line(" PIRC, 8,"); 242 dsdt_line(" PIRD, 8,"); 243 dsdt_line(" Offset (0x68),"); 244 dsdt_line(" PIRE, 8,"); 245 dsdt_line(" PIRF, 8,"); 246 dsdt_line(" PIRG, 8,"); 247 dsdt_line(" PIRH, 8"); 248 dsdt_line(" }"); 249 dsdt_line(""); 250 251 dsdt_indent(1); 252 SET_FOREACH(ldpp, lpc_dsdt_set) { 253 ldp = *ldpp; 254 ldp->handler(); 255 } 256 257 dsdt_line(""); 258 dsdt_line("Device (PIC)"); 259 dsdt_line("{"); 260 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))"); 261 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 262 dsdt_line(" {"); 263 dsdt_indent(2); 264 dsdt_fixed_ioport(IO_ICU1, 2); 265 dsdt_fixed_ioport(IO_ICU2, 2); 266 dsdt_fixed_irq(2); 267 dsdt_unindent(2); 268 dsdt_line(" })"); 269 dsdt_line("}"); 270 271 dsdt_line(""); 272 dsdt_line("Device (TIMR)"); 273 dsdt_line("{"); 274 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))"); 275 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 276 dsdt_line(" {"); 277 dsdt_indent(2); 278 dsdt_fixed_ioport(IO_TIMER1_PORT, 4); 279 dsdt_fixed_irq(0); 280 dsdt_unindent(2); 281 dsdt_line(" })"); 282 dsdt_line("}"); 283 dsdt_unindent(1); 284 285 dsdt_line("}"); 286} 287 288static void 289pci_lpc_sysres_dsdt(void) 290{ 291 struct lpc_sysres **lspp, *lsp; 292 293 dsdt_line(""); 294 dsdt_line("Device (SIO)"); 295 dsdt_line("{"); 296 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))"); 297 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 298 dsdt_line(" {"); 299 300 dsdt_indent(2); 301 SET_FOREACH(lspp, lpc_sysres_set) { 302 lsp = *lspp; 303 switch (lsp->type) { 304 case LPC_SYSRES_IO: 305 dsdt_fixed_ioport(lsp->base, lsp->length); 306 break; 307 case LPC_SYSRES_MEM: 308 dsdt_fixed_mem32(lsp->base, lsp->length); 309 break; 310 } 311 } 312 dsdt_unindent(2); 313 314 dsdt_line(" })"); 315 dsdt_line("}"); 316} 317LPC_DSDT(pci_lpc_sysres_dsdt); 318 319static void 320pci_lpc_uart_dsdt(void) 321{ 322 struct lpc_uart_softc *sc; 323 int unit; 324 325 for (unit = 0; unit < LPC_UART_NUM; unit++) { 326 sc = &lpc_uart_softc[unit]; 327 if (!sc->enabled) 328 continue; 329 dsdt_line(""); 330 dsdt_line("Device (%s)", lpc_uart_names[unit]); 331 dsdt_line("{"); 332 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))"); 333 dsdt_line(" Name (_UID, %d)", unit + 1); 334 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 335 dsdt_line(" {"); 336 dsdt_indent(2); 337 dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE); 338 dsdt_fixed_irq(sc->irq); 339 dsdt_unindent(2); 340 dsdt_line(" })"); 341 dsdt_line("}"); 342 } 343} 344LPC_DSDT(pci_lpc_uart_dsdt); 345 346static int 347pci_lpc_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 348 int coff, int bytes, uint32_t val) 349{ 350 int pirq_pin; 351 352 if (bytes == 1) { 353 pirq_pin = 0; 354 if (coff >= 0x60 && coff <= 0x63) 355 pirq_pin = coff - 0x60 + 1; 356 if (coff >= 0x68 && coff <= 0x6b) 357 pirq_pin = coff - 0x68 + 5; 358 if (pirq_pin != 0) { 359 pirq_write(ctx, pirq_pin, val); 360 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin)); 361 return (0); 362 } 363 } 364 return (-1); 365} 366 367static void 368pci_lpc_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 369 int baridx, uint64_t offset, int size, uint64_t value) 370{ 371} 372 373static uint64_t 374pci_lpc_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 375 int baridx, uint64_t offset, int size) 376{ 377 return (0); 378} 379 380#define LPC_DEV 0x7000 381#define LPC_VENDOR 0x8086 382 383static int 384pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 385{ 386 387 /* 388 * Do not allow more than one LPC bridge to be configured. 389 */ 390 if (lpc_bridge != NULL) { 391 fprintf(stderr, "Only one LPC bridge is allowed.\n"); 392 return (-1); 393 } 394 395 /* 396 * Enforce that the LPC can only be configured on bus 0. This 397 * simplifies the ACPI DSDT because it can provide a decode for 398 * all legacy i/o ports behind bus 0. 399 */ 400 if (pi->pi_bus != 0) { 401 fprintf(stderr, "LPC bridge can be present only on bus 0.\n"); 402 return (-1); 403 } 404 405 if (lpc_init(ctx) != 0) 406 return (-1); 407 408 /* initialize config space */ 409 pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV); 410 pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR); 411 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE); 412 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA); 413 414 lpc_bridge = pi; 415 416 return (0); 417} 418 419char * 420lpc_pirq_name(int pin) 421{ 422 char *name; 423 424 if (lpc_bridge == NULL) 425 return (NULL); 426 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1); 427 return (name); 428} 429 430void 431lpc_pirq_routed(void) 432{ 433 int pin; 434 435 if (lpc_bridge == NULL) 436 return; 437 438 for (pin = 0; pin < 4; pin++) 439 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1)); 440 for (pin = 0; pin < 4; pin++) 441 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5)); 442} 443 444struct pci_devemu pci_de_lpc = { 445 .pe_emu = "lpc", 446 .pe_init = pci_lpc_init, 447 .pe_write_dsdt = pci_lpc_write_dsdt, 448 .pe_cfgwrite = pci_lpc_cfgwrite, 449 .pe_barwrite = pci_lpc_write, 450 .pe_barread = pci_lpc_read 451}; 452PCI_EMUL_SET(pci_de_lpc); 453