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. tblgen - Target Description To C++ Code Generator . .nr rst2man-indent-level 0 . \\$1 \\n[an-margin] level \\n[rst2man-indent-level] level margin: \\n[rst2man-indent\\n[rst2man-indent-level]] - \\n[rst2man-indent0] \\n[rst2man-indent1] \\n[rst2man-indent2] .. .rstReportMargin pre:
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.. tblgen [options] [filename] tblgen translates from target description (.td) files into C++ code that can be included in the definition of an LLVM target library. Most users of LLVM will not need to use this program. It is only for assisting with writing an LLVM target backend. The input and output of tblgen is beyond the scope of this short introduction; please see the introduction to TableGen. The filename argument specifies the name of a Target Description (.td) file to read as input. NDENT 0.0

-help Print a summary of command line options. NINDENT NDENT 0.0

-o filename Specify the output file name. If filename is -, then tblgen sends its output to standard output. NINDENT NDENT 0.0

-I directory Specify where to find other target description files for inclusion. The directory value should be a full or partial path to a directory that contains target description files. NINDENT NDENT 0.0

-asmparsernum N Make -gen-asm-parser emit assembly writer number N. NINDENT NDENT 0.0

-asmwriternum N Make -gen-asm-writer emit assembly writer number N. NINDENT NDENT 0.0

-class className Print the enumeration list for this class. NINDENT NDENT 0.0

-print-records Print all records to standard output (default). NINDENT NDENT 0.0

-dump-json Print a JSON representation of all records, suitable for further automated processing. NINDENT NDENT 0.0

-print-enums Print enumeration values for a class. NINDENT NDENT 0.0

-print-sets Print expanded sets for testing DAG exprs. NINDENT NDENT 0.0

-gen-emitter Generate machine code emitter. NINDENT NDENT 0.0

-gen-register-info Generate registers and register classes info. NINDENT NDENT 0.0

-gen-instr-info Generate instruction descriptions. NINDENT NDENT 0.0

-gen-asm-writer Generate the assembly writer. NINDENT NDENT 0.0

-gen-disassembler Generate disassembler. NINDENT NDENT 0.0

-gen-pseudo-lowering Generate pseudo instruction lowering. NINDENT NDENT 0.0

-gen-dag-isel Generate a DAG (Directed Acycle Graph) instruction selector. NINDENT NDENT 0.0

-gen-asm-matcher Generate assembly instruction matcher. NINDENT NDENT 0.0

-gen-dfa-packetizer Generate DFA Packetizer for VLIW targets. NINDENT NDENT 0.0

-gen-fast-isel Generate a "fast" instruction selector. NINDENT NDENT 0.0

-gen-subtarget Generate subtarget enumerations. NINDENT NDENT 0.0

-gen-intrinsic-enums Generate intrinsic enums. NINDENT NDENT 0.0

-gen-intrinsic-impl Generate intrinsic implementation. NINDENT NDENT 0.0

-gen-tgt-intrinsic Generate target intrinsic information. NINDENT NDENT 0.0

-gen-enhanced-disassembly-info Generate enhanced disassembly info. NINDENT NDENT 0.0

-gen-exegesis Generate llvm-exegesis tables. NINDENT NDENT 0.0

-version Show the version number of this program. NINDENT

If tblgen succeeds, it will exit with 0. Otherwise, if an error occurs, it will exit with a non-zero value. Maintained by the LLVM Team (https://llvm.org/). 2003-2020, LLVM Project Generated by docutils manpage writer.
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