$FreeBSD: head/usr.bin/clang/llc/llc.1 231057 2012-02-05 23:56:22Z dim $
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Title "LLC 1" For nroff, turn off justification. Always turn off hyphenation; it makes
way too many mistakes in technical documents.
llc - LLVM static compiler Header "SYNOPSIS" \fBllc [options] [filename] Header "DESCRIPTION" The llc command compiles \s-1LLVM\s0 source inputs into assembly language for a specified architecture. The assembly language output can then be passed through a native assembler and linker to generate a native executable.

The choice of architecture for the output assembly code is automatically determined from the input file, unless the -march option is used to override the default.

Header "OPTIONS" If filename is - or omitted, llc reads from standard input. Otherwise, it will from filename. Inputs can be in either the \s-1LLVM\s0 assembly language format (.ll) or the \s-1LLVM\s0 bitcode format (.bc).

If the -o option is omitted, then llc will send its output to standard output if the input is from standard input. If the -o option specifies -, then the output will also be sent to standard output.

If no -o option is specified and an input file other than - is specified, then llc creates the output filename by taking the input filename, removing any existing .bc extension, and adding a .s suffix.

Other llc options are as follows:

Subsection "End-user Options" Item "-help" Print a summary of command line options. Item "-O=uint" Generate code at different optimization levels. These correspond to the -O0, \fI-O1, -O2, -O3, and -O4 optimization levels used by llvm-gcc and \fBclang. Item "-mtriple=target triple" Override the target triple specified in the input file with the specified string. Item "-march=arch" Specify the architecture for which to generate assembly, overriding the target encoded in the input file. See the output of llc -help for a list of valid architectures. By default this is inferred from the target triple or autodetected to the current architecture. Item "-mcpu=cpuname" Specify a specific chip in the current architecture to generate code for. By default this is inferred from the target triple and autodetected to the current architecture. For a list of available CPUs, use: \fBllvm-as < /dev/null | llc -march=xyz -mcpu=help Item "-mattr=a1,+a2,-a3,..." Override or control specific attributes of the target, such as whether \s-1SIMD\s0 operations are enabled or not. The default set of attributes is set by the current \s-1CPU\s0. For a list of available attributes, use: \fBllvm-as < /dev/null | llc -march=xyz -mattr=help Item "--disable-fp-elim" Disable frame pointer elimination optimization. Item "--disable-excess-fp-precision" Disable optimizations that may produce excess precision for floating point. Note that this option can dramatically slow down code on some systems (e.g. X86). Item "--enable-no-infs-fp-math" Enable optimizations that assume no Inf values. Item "--enable-no-nans-fp-math" Enable optimizations that assume no \s-1NAN\s0 values. Item "--enable-unsafe-fp-math" Enable optimizations that make unsafe assumptions about \s-1IEEE\s0 math (e.g. that addition is associative) or may not work for all input ranges. These optimizations allow the code generator to make use of some instructions which would otherwise not be usable (such as fsin on X86). Item "--enable-correct-eh-support" Instruct the lowerinvoke pass to insert code for correct exception handling support. This is expensive and is by default omitted for efficiency. Item "--stats" Print statistics recorded by code-generation passes. Item "--time-passes" Record the amount of time needed for each pass and print a report to standard error. Item "--load=dso_path" Dynamically load dso_path (a path to a dynamically shared object) that implements an \s-1LLVM\s0 target. This will permit the target name to be used with the \fB-march option so that code can be generated for that target. Subsection "Tuning/Configuration Options" Item "--print-machineinstrs" Print generated machine code between compilation phases (useful for debugging). Item "--regalloc=allocator" Specify the register allocator to use. The default allocator is local. Valid register allocators are: Item "--spiller=spiller" Specify the spiller to use for register allocators that support it. Currently this option is used only by the linear scan register allocator. The default \fIspiller is local. Valid spillers are: Subsection "Intel IA-32-specific Options" Item "--x86-asm-syntax=att|intel" Specify whether to emit assembly code in \s-1AT&T\s0 syntax (the default) or intel syntax. Header "EXIT STATUS" If llc succeeds, it will exit with 0. Otherwise, if an error occurs, it will exit with a non-zero value. Header "SEE ALSO" lli Header "AUTHORS" Maintained by the \s-1LLVM\s0 Team (<http://llvm.org/>).