dumpregs_5416.c revision 189059
1/*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/tools/tools/ath/athregs/dumpregs_5416.c 189059 2009-02-26 06:16:15Z sam $ 30 */ 31#include "diag.h" 32 33#include "ah.h" 34#include "ah_internal.h" 35#include "ar5416/ar5416reg.h" 36#include "ar5416/ar5416phy.h" 37 38#include "dumpregs.h" 39 40#define N(a) (sizeof(a) / sizeof(a[0])) 41 42#define MAC5416 SREV(13,8), SREV(0xff,0xff) /* XXX */ 43 44static struct dumpreg ar5416regs[] = { 45 { AR_CR, "CR", DUMP_BASIC }, 46 { AR_RXDP, "RXDP", DUMP_BASIC }, 47 { AR_CFG, "CFG", DUMP_BASIC }, 48 { AR_MIRT, "MIRT", DUMP_BASIC }, 49 { AR_TIMT, "TIMT", DUMP_BASIC }, 50 { AR_CST, "CST", DUMP_BASIC }, 51 { AR_IER, "IER", DUMP_BASIC }, 52 { AR_TXCFG, "TXCFG", DUMP_BASIC }, 53 { AR_RXCFG, "RXCFG", DUMP_BASIC }, 54 { AR_MIBC, "MIBC", DUMP_BASIC }, 55 { AR_TOPS, "TOPS", DUMP_BASIC }, 56 { AR_RXNPTO, "RXNPTO", DUMP_BASIC }, 57 { AR_TXNPTO, "TXNPTO", DUMP_BASIC }, 58 { AR_RPGTO, "RPGTO", DUMP_BASIC }, 59 { AR_RPCNT, "RPCNT", DUMP_BASIC }, 60 { AR_MACMISC, "MACMISC", DUMP_BASIC }, 61 { AR_SPC_0, "SPC_0", DUMP_BASIC }, 62 { AR_SPC_1, "SPC_1", DUMP_BASIC }, 63 { AR_GTXTO, "GTXTO", DUMP_BASIC }, 64 { AR_GTTM, "GTTM", DUMP_BASIC }, 65 66 { AR_ISR, "ISR", DUMP_INTERRUPT }, 67 { AR_ISR_S0, "ISR_S0", DUMP_INTERRUPT }, 68 { AR_ISR_S1, "ISR_S1", DUMP_INTERRUPT }, 69 { AR_ISR_S2, "ISR_S2", DUMP_INTERRUPT }, 70 { AR_ISR_S3, "ISR_S3", DUMP_INTERRUPT }, 71 { AR_ISR_S4, "ISR_S4", DUMP_INTERRUPT }, 72 { AR_IMR, "IMR", DUMP_INTERRUPT }, 73 { AR_IMR_S0, "IMR_S0", DUMP_INTERRUPT }, 74 { AR_IMR_S1, "IMR_S1", DUMP_INTERRUPT }, 75 { AR_IMR_S2, "IMR_S2", DUMP_INTERRUPT }, 76 { AR_IMR_S3, "IMR_S3", DUMP_INTERRUPT }, 77 { AR_IMR_S4, "IMR_S4", DUMP_INTERRUPT }, 78#if 0 79 /* NB: don't read the RAC so we don't affect operation */ 80 { AR_ISR_RAC, "ISR_RAC", DUMP_INTERRUPT }, 81#endif 82 { AR_ISR_S0_S, "ISR_S0_S", DUMP_INTERRUPT }, 83 { AR_ISR_S1_S, "ISR_S1_S", DUMP_INTERRUPT }, 84 { AR_ISR_S2_S, "ISR_S2_S", DUMP_INTERRUPT }, 85 { AR_ISR_S3_S, "ISR_S3_S", DUMP_INTERRUPT }, 86 { AR_ISR_S4_S, "ISR_S4_S", DUMP_INTERRUPT }, 87 88 { AR_DMADBG_0, "DMADBG0", DUMP_BASIC }, 89 { AR_DMADBG_1, "DMADBG1", DUMP_BASIC }, 90 { AR_DMADBG_2, "DMADBG2", DUMP_BASIC }, 91 { AR_DMADBG_3, "DMADBG3", DUMP_BASIC }, 92 { AR_DMADBG_4, "DMADBG4", DUMP_BASIC }, 93 { AR_DMADBG_5, "DMADBG5", DUMP_BASIC }, 94 { AR_DMADBG_6, "DMADBG6", DUMP_BASIC }, 95 { AR_DMADBG_7, "DMADBG7", DUMP_BASIC }, 96 97 { AR_DCM_A, "DCM_A", DUMP_BASIC }, 98 { AR_DCM_D, "DCM_D", DUMP_BASIC }, 99 { AR_DCCFG, "DCCFG", DUMP_BASIC }, 100 { AR_CCFG, "CCFG", DUMP_BASIC }, 101 { AR_CCUCFG, "CCUCFG", DUMP_BASIC }, 102 { AR_CPC_0, "CPC0", DUMP_BASIC }, 103 { AR_CPC_1, "CPC1", DUMP_BASIC }, 104 { AR_CPC_2, "CPC2", DUMP_BASIC }, 105 { AR_CPC_3, "CPC3", DUMP_BASIC }, 106 { AR_CPCOVF, "CPCOVF", DUMP_BASIC }, 107 108 { AR_Q0_TXDP, "Q0_TXDP", DUMP_QCU }, 109 { AR_Q1_TXDP, "Q1_TXDP", DUMP_QCU }, 110 { AR_Q2_TXDP, "Q2_TXDP", DUMP_QCU }, 111 { AR_Q3_TXDP, "Q3_TXDP", DUMP_QCU }, 112 { AR_Q4_TXDP, "Q4_TXDP", DUMP_QCU }, 113 { AR_Q5_TXDP, "Q5_TXDP", DUMP_QCU }, 114 { AR_Q6_TXDP, "Q6_TXDP", DUMP_QCU }, 115 { AR_Q7_TXDP, "Q7_TXDP", DUMP_QCU }, 116 { AR_Q8_TXDP, "Q8_TXDP", DUMP_QCU }, 117 { AR_Q9_TXDP, "Q9_TXDP", DUMP_QCU }, 118 119 { AR_Q_TXE, "Q_TXE", DUMP_QCU }, 120 { AR_Q_TXD, "Q_TXD", DUMP_QCU }, 121 122 { AR_Q0_CBRCFG, "Q0_CBR", DUMP_QCU }, 123 { AR_Q1_CBRCFG, "Q1_CBR", DUMP_QCU }, 124 { AR_Q2_CBRCFG, "Q2_CBR", DUMP_QCU }, 125 { AR_Q3_CBRCFG, "Q3_CBR", DUMP_QCU }, 126 { AR_Q4_CBRCFG, "Q4_CBR", DUMP_QCU }, 127 { AR_Q5_CBRCFG, "Q5_CBR", DUMP_QCU }, 128 { AR_Q6_CBRCFG, "Q6_CBR", DUMP_QCU }, 129 { AR_Q7_CBRCFG, "Q7_CBR", DUMP_QCU }, 130 { AR_Q8_CBRCFG, "Q8_CBR", DUMP_QCU }, 131 { AR_Q9_CBRCFG, "Q9_CBR", DUMP_QCU }, 132 133 { AR_Q0_RDYTIMECFG, "Q0_RDYT", DUMP_QCU }, 134 { AR_Q1_RDYTIMECFG, "Q1_RDYT", DUMP_QCU }, 135 { AR_Q2_RDYTIMECFG, "Q2_RDYT", DUMP_QCU }, 136 { AR_Q3_RDYTIMECFG, "Q3_RDYT", DUMP_QCU }, 137 { AR_Q4_RDYTIMECFG, "Q4_RDYT", DUMP_QCU }, 138 { AR_Q5_RDYTIMECFG, "Q5_RDYT", DUMP_QCU }, 139 { AR_Q6_RDYTIMECFG, "Q6_RDYT", DUMP_QCU }, 140 { AR_Q7_RDYTIMECFG, "Q7_RDYT", DUMP_QCU }, 141 { AR_Q8_RDYTIMECFG, "Q8_RDYT", DUMP_QCU }, 142 { AR_Q9_RDYTIMECFG, "Q9_RDYT", DUMP_QCU }, 143 144 { AR_Q_ONESHOTARM_SC,"Q_ONESHOTARM_SC", DUMP_QCU }, 145 { AR_Q_ONESHOTARM_CC,"Q_ONESHOTARM_CC", DUMP_QCU }, 146 147 { AR_Q0_MISC, "Q0_MISC", DUMP_QCU }, 148 { AR_Q1_MISC, "Q1_MISC", DUMP_QCU }, 149 { AR_Q2_MISC, "Q2_MISC", DUMP_QCU }, 150 { AR_Q3_MISC, "Q3_MISC", DUMP_QCU }, 151 { AR_Q4_MISC, "Q4_MISC", DUMP_QCU }, 152 { AR_Q5_MISC, "Q5_MISC", DUMP_QCU }, 153 { AR_Q6_MISC, "Q6_MISC", DUMP_QCU }, 154 { AR_Q7_MISC, "Q7_MISC", DUMP_QCU }, 155 { AR_Q8_MISC, "Q8_MISC", DUMP_QCU }, 156 { AR_Q9_MISC, "Q9_MISC", DUMP_QCU }, 157 158 { AR_Q0_STS, "Q0_STS", DUMP_QCU }, 159 { AR_Q1_STS, "Q1_STS", DUMP_QCU }, 160 { AR_Q2_STS, "Q2_STS", DUMP_QCU }, 161 { AR_Q3_STS, "Q3_STS", DUMP_QCU }, 162 { AR_Q4_STS, "Q4_STS", DUMP_QCU }, 163 { AR_Q5_STS, "Q5_STS", DUMP_QCU }, 164 { AR_Q6_STS, "Q6_STS", DUMP_QCU }, 165 { AR_Q7_STS, "Q7_STS", DUMP_QCU }, 166 { AR_Q8_STS, "Q8_STS", DUMP_QCU }, 167 { AR_Q9_STS, "Q9_STS", DUMP_QCU }, 168 169 { AR_Q_RDYTIMESHDN, "Q_RDYTIMSHD", DUMP_QCU }, 170 171 { AR_Q_CBBS, "Q_CBBS", DUMP_QCU }, 172 { AR_Q_CBBA, "Q_CBBA", DUMP_QCU }, 173 { AR_Q_CBC, "Q_CBC", DUMP_QCU }, 174 175 { AR_D0_QCUMASK, "D0_MASK", DUMP_DCU }, 176 { AR_D1_QCUMASK, "D1_MASK", DUMP_DCU }, 177 { AR_D2_QCUMASK, "D2_MASK", DUMP_DCU }, 178 { AR_D3_QCUMASK, "D3_MASK", DUMP_DCU }, 179 { AR_D4_QCUMASK, "D4_MASK", DUMP_DCU }, 180 { AR_D5_QCUMASK, "D5_MASK", DUMP_DCU }, 181 { AR_D6_QCUMASK, "D6_MASK", DUMP_DCU }, 182 { AR_D7_QCUMASK, "D7_MASK", DUMP_DCU }, 183 { AR_D8_QCUMASK, "D8_MASK", DUMP_DCU }, 184 { AR_D9_QCUMASK, "D9_MASK", DUMP_DCU }, 185 186 { AR_D0_LCL_IFS, "D0_IFS", DUMP_DCU }, 187 { AR_D1_LCL_IFS, "D1_IFS", DUMP_DCU }, 188 { AR_D2_LCL_IFS, "D2_IFS", DUMP_DCU }, 189 { AR_D3_LCL_IFS, "D3_IFS", DUMP_DCU }, 190 { AR_D4_LCL_IFS, "D4_IFS", DUMP_DCU }, 191 { AR_D5_LCL_IFS, "D5_IFS", DUMP_DCU }, 192 { AR_D6_LCL_IFS, "D6_IFS", DUMP_DCU }, 193 { AR_D7_LCL_IFS, "D7_IFS", DUMP_DCU }, 194 { AR_D8_LCL_IFS, "D8_IFS", DUMP_DCU }, 195 { AR_D9_LCL_IFS, "D9_IFS", DUMP_DCU }, 196 197 { AR_D0_RETRY_LIMIT,"D0_RTRY", DUMP_DCU }, 198 { AR_D1_RETRY_LIMIT,"D1_RTRY", DUMP_DCU }, 199 { AR_D2_RETRY_LIMIT,"D2_RTRY", DUMP_DCU }, 200 { AR_D3_RETRY_LIMIT,"D3_RTRY", DUMP_DCU }, 201 { AR_D4_RETRY_LIMIT,"D4_RTRY", DUMP_DCU }, 202 { AR_D5_RETRY_LIMIT,"D5_RTRY", DUMP_DCU }, 203 { AR_D6_RETRY_LIMIT,"D6_RTRY", DUMP_DCU }, 204 { AR_D7_RETRY_LIMIT,"D7_RTRY", DUMP_DCU }, 205 { AR_D8_RETRY_LIMIT,"D8_RTRY", DUMP_DCU }, 206 { AR_D9_RETRY_LIMIT,"D9_RTRY", DUMP_DCU }, 207 208 { AR_D0_CHNTIME, "D0_CHNT", DUMP_DCU }, 209 { AR_D1_CHNTIME, "D1_CHNT", DUMP_DCU }, 210 { AR_D2_CHNTIME, "D2_CHNT", DUMP_DCU }, 211 { AR_D3_CHNTIME, "D3_CHNT", DUMP_DCU }, 212 { AR_D4_CHNTIME, "D4_CHNT", DUMP_DCU }, 213 { AR_D5_CHNTIME, "D5_CHNT", DUMP_DCU }, 214 { AR_D6_CHNTIME, "D6_CHNT", DUMP_DCU }, 215 { AR_D7_CHNTIME, "D7_CHNT", DUMP_DCU }, 216 { AR_D8_CHNTIME, "D8_CHNT", DUMP_DCU }, 217 { AR_D9_CHNTIME, "D9_CHNT", DUMP_DCU }, 218 219 { AR_D0_MISC, "D0_MISC", DUMP_DCU }, 220 { AR_D1_MISC, "D1_MISC", DUMP_DCU }, 221 { AR_D2_MISC, "D2_MISC", DUMP_DCU }, 222 { AR_D3_MISC, "D3_MISC", DUMP_DCU }, 223 { AR_D4_MISC, "D4_MISC", DUMP_DCU }, 224 { AR_D5_MISC, "D5_MISC", DUMP_DCU }, 225 { AR_D6_MISC, "D6_MISC", DUMP_DCU }, 226 { AR_D7_MISC, "D7_MISC", DUMP_DCU }, 227 { AR_D8_MISC, "D8_MISC", DUMP_DCU }, 228 { AR_D9_MISC, "D9_MISC", DUMP_DCU }, 229 230 { AR_D_SEQNUM, "D_SEQ", DUMP_BASIC | DUMP_DCU }, 231 { AR_D_GBL_IFS_SIFS,"D_SIFS", DUMP_BASIC }, 232 { AR_D_GBL_IFS_SLOT,"D_SLOT", DUMP_BASIC }, 233 { AR_D_GBL_IFS_EIFS,"D_EIFS", DUMP_BASIC }, 234 { AR_D_GBL_IFS_MISC,"D_MISC", DUMP_BASIC }, 235 { AR_D_FPCTL, "D_FPCTL", DUMP_BASIC }, 236 { AR_D_TXPSE, "D_TXPSE", DUMP_BASIC }, 237#if 0 238 { AR_D_TXBLK_CMD, "D_CMD", DUMP_BASIC }, 239 { AR_D_TXBLK_DATA, "D_DATA", DUMP_BASIC }, 240 { AR_D_TXBLK_CLR, "D_CLR", DUMP_BASIC }, 241 { AR_D_TXBLK_SET, "D_SET", DUMP_BASIC }, 242#endif 243 244 { AR_MAC_LED, "MAC_LED", DUMP_BASIC }, 245 { AR_RC, "RC", DUMP_BASIC }, 246 { AR_SCR, "SCR", DUMP_BASIC }, 247 { AR_INTPEND, "INTPEND", DUMP_BASIC }, 248 { AR_SFR, "SFR", DUMP_BASIC }, 249 { AR_PCICFG, "PCICFG", DUMP_BASIC }, 250 { AR_SREV, "SREV", DUMP_BASIC }, 251 252 { AR_AHB_MODE, "AHBMODE", DUMP_BASIC }, 253 { AR5416_PCIE_PM_CTRL,"PCIEPMC", DUMP_BASIC }, 254 { AR5416_PCIE_SERDES,"SERDES", DUMP_BASIC }, 255 { AR5416_PCIE_SERDES2, "SERDES2", DUMP_BASIC }, 256 257 { AR_INTR_ASYNC_MASK,"IASYNCM", DUMP_BASIC }, 258 { AR_INTR_SYNC_MASK,"ISYNCM", DUMP_BASIC }, 259 { AR_RTC_RC, "RTC_RC", DUMP_BASIC }, 260 { AR_RTC_PLL_CONTROL,"RTC_PLL", DUMP_BASIC }, 261 262 { AR_GPIO_IN_OUT, "GPIOIO", DUMP_BASIC }, 263 { AR_GPIO_OE_OUT, "GPIOOE", DUMP_BASIC }, 264 { AR_GPIO_INTR_POL, "GPIOPOL", DUMP_BASIC }, 265 { AR_GPIO_INPUT_EN_VAL, "GPIOIEV", DUMP_BASIC }, 266 { AR_GPIO_INPUT_MUX1, "GPIMUX1", DUMP_BASIC }, 267 { AR_GPIO_INPUT_MUX2, "GPIMUX2", DUMP_BASIC }, 268 { AR_GPIO_OUTPUT_MUX1, "GPOMUX1", DUMP_BASIC }, 269 { AR_GPIO_OUTPUT_MUX2, "GPOMUX2", DUMP_BASIC }, 270 { AR_GPIO_OUTPUT_MUX3, "GPOMUX3", DUMP_BASIC }, 271 { AR_OBS, "OBS", DUMP_BASIC }, 272#if 0 273 { AR_EEPROM_ADDR, "EEADDR", DUMP_BASIC }, 274 { AR_EEPROM_DATA, "EEDATA", DUMP_BASIC }, 275 { AR_EEPROM_CMD, "EECMD", DUMP_BASIC }, 276 { AR_EEPROM_STS, "EESTS", DUMP_BASIC }, 277 { AR_EEPROM_CFG, "EECFG", DUMP_BASIC }, 278#endif 279 { AR_STA_ID0, "STA_ID0", DUMP_BASIC }, 280 { AR_STA_ID1, "STA_ID1", DUMP_BASIC | DUMP_KEYCACHE }, 281 { AR_BSS_ID0, "BSS_ID0", DUMP_BASIC }, 282 { AR_BSS_ID1, "BSS_ID1", DUMP_BASIC }, 283 { AR_SLOT_TIME, "SLOTTIME", DUMP_BASIC }, 284 { AR_TIME_OUT, "TIME_OUT", DUMP_BASIC }, 285 { AR_RSSI_THR, "RSSI_THR", DUMP_BASIC }, 286 { AR_USEC, "USEC", DUMP_BASIC }, 287 { AR_BEACON, "BEACON", DUMP_BASIC }, 288 { AR_CFP_PERIOD, "CFP_PER", DUMP_BASIC }, 289 { AR_TIMER0, "TIMER0", DUMP_BASIC }, 290 { AR_TIMER1, "TIMER1", DUMP_BASIC }, 291 { AR_TIMER2, "TIMER2", DUMP_BASIC }, 292 { AR_TIMER3, "TIMER3", DUMP_BASIC }, 293 { AR_CFP_DUR, "CFP_DUR", DUMP_BASIC }, 294 { AR_RX_FILTER, "RXFILTER", DUMP_BASIC }, 295 { AR_MCAST_FIL0, "MCAST_0", DUMP_BASIC }, 296 { AR_MCAST_FIL1, "MCAST_1", DUMP_BASIC }, 297 { AR_DIAG_SW, "DIAG_SW", DUMP_BASIC }, 298 { AR_TSF_L32, "TSF_L32", DUMP_BASIC }, 299 { AR_TSF_U32, "TSF_U32", DUMP_BASIC }, 300 { AR_TST_ADDAC, "TST_ADAC", DUMP_BASIC }, 301 { AR_DEF_ANTENNA, "DEF_ANT", DUMP_BASIC }, 302 { AR_QOS_MASK, "QOS_MASK", DUMP_BASIC }, 303 { AR_SEQ_MASK, "SEQ_MASK", DUMP_BASIC }, 304 { AR_OBSERV_2, "OBSERV2", DUMP_BASIC }, 305 { AR_OBSERV_1, "OBSERV1", DUMP_BASIC }, 306 307 { AR_LAST_TSTP, "LAST_TST", DUMP_BASIC }, 308 { AR_NAV, "NAV", DUMP_BASIC }, 309 { AR_RTS_OK, "RTS_OK", DUMP_BASIC }, 310 { AR_RTS_FAIL, "RTS_FAIL", DUMP_BASIC }, 311 { AR_ACK_FAIL, "ACK_FAIL", DUMP_BASIC }, 312 { AR_FCS_FAIL, "FCS_FAIL", DUMP_BASIC }, 313 { AR_BEACON_CNT, "BEAC_CNT", DUMP_BASIC }, 314 315 { AR_SLEEP1, "SLEEP1", DUMP_BASIC }, 316 { AR_SLEEP2, "SLEEP2", DUMP_BASIC }, 317 { AR_SLEEP3, "SLEEP3", DUMP_BASIC }, 318 { AR_BSSMSKL, "BSSMSKL", DUMP_BASIC }, 319 { AR_BSSMSKU, "BSSMSKU", DUMP_BASIC }, 320 { AR_TPC, "TPC", DUMP_BASIC }, 321 { AR_TFCNT, "TFCNT", DUMP_BASIC }, 322 { AR_RFCNT, "RFCNT", DUMP_BASIC }, 323 { AR_RCCNT, "RCCNT", DUMP_BASIC }, 324 { AR_CCCNT, "CCCNT", DUMP_BASIC }, 325 { AR_QUIET1, "QUIET1", DUMP_BASIC }, 326 { AR_QUIET2, "QUIET2", DUMP_BASIC }, 327 { AR_TSF_PARM, "TSF_PARM", DUMP_BASIC }, 328 { AR_NOACK, "NOACK", DUMP_BASIC }, 329 { AR_PHY_ERR, "PHY_ERR", DUMP_BASIC }, 330 { AR_QOS_CONTROL, "QOS_CTRL", DUMP_BASIC }, 331 { AR_QOS_SELECT, "QOS_SEL", DUMP_BASIC }, 332 { AR_MISC_MODE, "MISCMODE", DUMP_BASIC }, 333 { AR_FILTOFDM, "FILTOFDM", DUMP_BASIC }, 334 { AR_FILTCCK, "FILTCCK", DUMP_BASIC }, 335 { AR_PHYCNT1, "PHYCNT1", DUMP_BASIC }, 336 { AR_PHYCNTMASK1, "PHYCMSK1", DUMP_BASIC }, 337 { AR_PHYCNT2, "PHYCNT2", DUMP_BASIC }, 338 { AR_PHYCNTMASK2, "PHYCMSK2", DUMP_BASIC }, 339 340 { AR_TXOP_X, "TXOPX", DUMP_BASIC }, 341 { AR_NEXT_TBTT, "NXTTBTT", DUMP_BASIC}, 342 { AR_NEXT_DBA, "NXTDBA", DUMP_BASIC }, 343 { AR_NEXT_SWBA, "NXTSWBA", DUMP_BASIC }, 344 { AR_NEXT_CFP, "NXTCFP", DUMP_BASIC }, 345 { AR_NEXT_HCF, "NXTHCF", DUMP_BASIC }, 346 { AR_NEXT_DTIM, "NXTDTIM", DUMP_BASIC }, 347 { AR_NEXT_QUIET, "NXTQUIET", DUMP_BASIC }, 348 { AR_NEXT_NDP, "NXTNDP", DUMP_BASIC }, 349 { AR5416_BEACON_PERIOD, "BCNPER", DUMP_BASIC }, 350 { AR_DBA_PERIOD, "DBAPER", DUMP_BASIC }, 351 { AR_SWBA_PERIOD, "SWBAPER", DUMP_BASIC }, 352 { AR_TIM_PERIOD, "TIMPER", DUMP_BASIC }, 353 { AR_DTIM_PERIOD, "DTIMPER", DUMP_BASIC }, 354 { AR_QUIET_PERIOD, "QUIETPER", DUMP_BASIC }, 355 { AR_NDP_PERIOD, "NDPPER", DUMP_BASIC }, 356 { AR_TIMER_MODE, "TIMERMOD", DUMP_BASIC }, 357 { AR_2040_MODE, "2040MODE", DUMP_BASIC }, 358 { AR_PCU_TXBUF_CTRL,"PCUTXBUF", DUMP_BASIC }, 359 { AR_SLP32_MODE, "SLP32MOD", DUMP_BASIC }, 360 { AR_SLP32_WAKE, "SLP32WAK", DUMP_BASIC }, 361 { AR_SLP32_INC, "SLP32INC", DUMP_BASIC }, 362 { AR_SLP_CNT, "SLPCNT", DUMP_BASIC }, 363 { AR_SLP_MIB_CTRL, "SLPMIB", DUMP_BASIC }, 364 { AR_EXTRCCNT, "EXTRCCNT", DUMP_BASIC }, 365 366 /* XXX { AR_RATE_DURATION(0), AR_RATE_DURATION(0x20) }, */ 367}; 368 369static __constructor void 370ar5416_ctor(void) 371{ 372 register_regs(ar5416regs, N(ar5416regs), MAC5416, PHYANY); 373 register_keycache(128, MAC5416, PHYANY); 374 375 register_range(0x9800, 0x987c, DUMP_BASEBAND, MAC5416, PHYANY); 376 register_range(0x9900, 0x997c, DUMP_BASEBAND, MAC5416, PHYANY); 377 register_range(0x99a4, 0x99a4, DUMP_BASEBAND, MAC5416, PHYANY); 378 register_range(0x9c00, 0x9c1c, DUMP_BASEBAND, MAC5416, PHYANY); 379 register_range(0xa180, 0xa238, DUMP_BASEBAND, MAC5416, PHYANY); 380 register_range(0xa258, 0xa26c, DUMP_BASEBAND, MAC5416, PHYANY); 381 register_range(0xa3c8, 0xa3d4, DUMP_BASEBAND, MAC5416, PHYANY); 382 register_range(0xa864, 0xa864, DUMP_BASEBAND, MAC5416, PHYANY); 383 register_range(0xa9bc, 0xa9bc, DUMP_BASEBAND, MAC5416, PHYANY); 384 register_range(0xb864, 0xb864, DUMP_BASEBAND, MAC5416, PHYANY); 385 register_range(0xb9bc, 0xb9bc, DUMP_BASEBAND, MAC5416, PHYANY); 386} 387