fpu_emul.S revision 302408
1/*- 2 * Copyright (c) 2010 by Peter Jeremy <peterjeremy@acm.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 21 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 23 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <machine/asm.h> 27__FBSDID("$FreeBSD: stable/11/tools/test/testfloat/sparc64/fpu_emul.S 207151 2010-04-24 12:11:41Z marius $"); 28 29 .section "rodata1",#alloc 30 .align 8 31 32 .global insn_int32_to_float32 33insn_int32_to_float32: 34 fitos %f0,%f0 35 36 .global insn_int32_to_float64 37insn_int32_to_float64: 38 fitod %f0,%f0 39 40 .global insn_int32_to_float128 41insn_int32_to_float128: 42 fitoq %f0,%f0 43 44 .global insn_int64_to_float32 45insn_int64_to_float32: 46 fxtos %f0,%f0 47 48 .global insn_int64_to_float64 49insn_int64_to_float64: 50 fxtod %f0,%f0 51 52 .global insn_int64_to_float128 53insn_int64_to_float128: 54 fxtoq %f0,%f0 55 56 .global insn_float32_to_int32_round_to_zero 57insn_float32_to_int32_round_to_zero: 58 fstoi %f0,%f0 59 60 .global insn_float32_to_int64_round_to_zero 61insn_float32_to_int64_round_to_zero: 62 fstox %f0,%f0 63 64 .global insn_float32_to_float64 65insn_float32_to_float64: 66 fstod %f0,%f0 67 68 .global insn_float32_to_float128 69insn_float32_to_float128: 70 fstoq %f0,%f0 71 72 .global insn_float32_add 73insn_float32_add: 74 fadds %f0,%f1,%f0 75 76 .global insn_float32_sub 77insn_float32_sub: 78 fsubs %f0,%f1,%f0 79 80 .global insn_float32_mul 81insn_float32_mul: 82 fmuls %f0,%f1,%f0 83 84 .global insn_float32_div 85insn_float32_div: 86 fdivs %f0,%f1,%f0 87 88 .global insn_float32_sqrt 89insn_float32_sqrt: 90 fsqrts %f0,%f0 91 92 .global insn_float32_cmp 93insn_float32_cmp: 94 fcmps %fcc0,%f0,%f1 95 96 .global insn_float32_cmpe 97insn_float32_cmpe: 98 fcmpes %fcc0,%f0,%f1 99 100 .global insn_float64_to_int32_round_to_zero 101insn_float64_to_int32_round_to_zero: 102 fdtoi %f0,%f0 103 104 .global insn_float64_to_int64_round_to_zero 105insn_float64_to_int64_round_to_zero: 106 fdtox %f0,%f0 107 108 .global insn_float64_to_float32 109insn_float64_to_float32: 110 fdtos %f0,%f0 111 112 .global insn_float64_to_float128 113insn_float64_to_float128: 114 fdtoq %f0,%f0 115 116 .global insn_float64_add 117insn_float64_add: 118 faddd %f0,%f2,%f0 119 120 .global insn_float64_sub 121insn_float64_sub: 122 fsubd %f0,%f2,%f0 123 124 .global insn_float64_mul 125insn_float64_mul: 126 fmuld %f0,%f2,%f0 127 128 .global insn_float64_div 129insn_float64_div: 130 fdivd %f0,%f2,%f0 131 132 .global insn_float64_sqrt 133insn_float64_sqrt: 134 fsqrtd %f0,%f0 135 136 .global insn_float64_cmp 137insn_float64_cmp: 138 fcmpd %fcc0,%f0,%f2 139 140 .global insn_float64_cmpe 141insn_float64_cmpe: 142 fcmped %fcc0,%f0,%f2 143 144 .global insn_float128_to_int32_round_to_zero 145insn_float128_to_int32_round_to_zero: 146 fqtoi %f0,%f0 147 148 .global insn_float128_to_int64_round_to_zero 149insn_float128_to_int64_round_to_zero: 150 fqtox %f0,%f0 151 152 .global insn_float128_to_float32 153insn_float128_to_float32: 154 fqtos %f0,%f0 155 156 .global insn_float128_to_float64 157insn_float128_to_float64: 158 fqtod %f0,%f0 159 160 .global insn_float128_add 161insn_float128_add: 162 faddq %f0,%f4,%f0 163 164 .global insn_float128_sub 165insn_float128_sub: 166 fsubq %f0,%f4,%f0 167 168 .global insn_float128_mul 169insn_float128_mul: 170 fmulq %f0,%f4,%f0 171 172 .global insn_float128_div 173insn_float128_div: 174 fdivq %f0,%f4,%f0 175 176 .global insn_float128_sqrt 177insn_float128_sqrt: 178 fsqrtq %f0,%f0 179 180 .global insn_float128_cmp 181insn_float128_cmp: 182 fcmpq %fcc0,%f0,%f4 183 184 .global insn_float128_cmpe 185insn_float128_cmpe: 186 fcmpeq %fcc0,%f0,%f4 187